Remove pcibus.h header.

It is a subset of pci_cfgreg.h and both headers were included together.

memtemp: Add support for Intel Core Haswell and E3 v3 cpus

Tested-by: dillon@ (no sensors available though)

ecc/e3: Split it into two drivers, coremctl(4) and ecc(4)

coremctl(4), which maps the MCHBAR, is now the parent of ecc(4) for
Intel E3 cpus. This paves way to add Intel Core/E3 support to
memtemp(4

ecc/e3: Split it into two drivers, coremctl(4) and ecc(4)

coremctl(4), which maps the MCHBAR, is now the parent of ecc(4) for
Intel E3 cpus. This paves way to add Intel Core/E3 support to
memtemp(4).

Tested-by: dillon@ on i3/Haswell and E3/v3

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