1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) Intel Corporation. All rights reserved. 3 * Copyright (c) 2020, 2021 Mellanox Technologies LTD. All rights reserved. 4 * Copyright (c) 2021, 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 5 */ 6 7 #include "spdk/stdinc.h" 8 9 #include "spdk_cunit.h" 10 11 #include "spdk/log.h" 12 13 #include "common/lib/test_env.c" 14 15 #include "nvme/nvme_ctrlr.c" 16 #include "nvme/nvme_quirks.c" 17 18 SPDK_LOG_REGISTER_COMPONENT(nvme) 19 20 pid_t g_spdk_nvme_pid; 21 22 struct nvme_driver _g_nvme_driver = { 23 .lock = PTHREAD_MUTEX_INITIALIZER, 24 }; 25 26 struct nvme_driver *g_spdk_nvme_driver = &_g_nvme_driver; 27 28 struct spdk_nvme_registers g_ut_nvme_regs = {}; 29 typedef void (*set_reg_cb)(void); 30 set_reg_cb g_set_reg_cb; 31 32 __thread int nvme_thread_ioq_index = -1; 33 34 uint32_t set_size = 1; 35 36 int set_status_cpl = -1; 37 38 DEFINE_STUB(nvme_ctrlr_cmd_set_host_id, int, 39 (struct spdk_nvme_ctrlr *ctrlr, void *host_id, uint32_t host_id_size, 40 spdk_nvme_cmd_cb cb_fn, void *cb_arg), 0); 41 DEFINE_STUB_V(nvme_ns_set_identify_data, (struct spdk_nvme_ns *ns)); 42 DEFINE_STUB_V(nvme_ns_set_id_desc_list_data, (struct spdk_nvme_ns *ns)); 43 DEFINE_STUB_V(nvme_ns_free_iocs_specific_data, (struct spdk_nvme_ns *ns)); 44 DEFINE_STUB_V(nvme_qpair_abort_all_queued_reqs, (struct spdk_nvme_qpair *qpair, uint32_t dnr)); 45 DEFINE_STUB(spdk_nvme_poll_group_remove, int, (struct spdk_nvme_poll_group *group, 46 struct spdk_nvme_qpair *qpair), 0); 47 DEFINE_STUB_V(nvme_io_msg_ctrlr_update, (struct spdk_nvme_ctrlr *ctrlr)); 48 DEFINE_STUB(nvme_io_msg_process, int, (struct spdk_nvme_ctrlr *ctrlr), 0); 49 DEFINE_STUB(nvme_transport_ctrlr_reserve_cmb, int, (struct spdk_nvme_ctrlr *ctrlr), 0); 50 DEFINE_STUB(spdk_nvme_ctrlr_cmd_security_receive, int, (struct spdk_nvme_ctrlr *ctrlr, 51 uint8_t secp, uint16_t spsp, uint8_t nssf, void *payload, 52 uint32_t payload_size, spdk_nvme_cmd_cb cb_fn, void *cb_arg), 0); 53 DEFINE_STUB(spdk_nvme_ctrlr_cmd_security_send, int, (struct spdk_nvme_ctrlr *ctrlr, 54 uint8_t secp, uint16_t spsp, uint8_t nssf, void *payload, 55 uint32_t payload_size, spdk_nvme_cmd_cb cb_fn, void *cb_arg), 0); 56 DEFINE_STUB_V(nvme_qpair_abort_queued_reqs, (struct spdk_nvme_qpair *qpair, uint32_t dnr)); 57 58 DEFINE_RETURN_MOCK(nvme_transport_ctrlr_get_memory_domains, int); 59 int 60 nvme_transport_ctrlr_get_memory_domains(const struct spdk_nvme_ctrlr *ctrlr, 61 struct spdk_memory_domain **domains, int array_size) 62 { 63 HANDLE_RETURN_MOCK(nvme_transport_ctrlr_get_memory_domains); 64 65 return 0; 66 } 67 68 DEFINE_RETURN_MOCK(nvme_transport_ctrlr_ready, int); 69 int 70 nvme_transport_ctrlr_ready(struct spdk_nvme_ctrlr *ctrlr) 71 { 72 HANDLE_RETURN_MOCK(nvme_transport_ctrlr_ready); 73 return 0; 74 } 75 76 struct spdk_nvme_ctrlr *nvme_transport_ctrlr_construct(const struct spdk_nvme_transport_id *trid, 77 const struct spdk_nvme_ctrlr_opts *opts, 78 void *devhandle) 79 { 80 return NULL; 81 } 82 83 int 84 nvme_transport_ctrlr_destruct(struct spdk_nvme_ctrlr *ctrlr) 85 { 86 nvme_ctrlr_destruct_finish(ctrlr); 87 88 return 0; 89 } 90 91 int 92 nvme_transport_ctrlr_enable(struct spdk_nvme_ctrlr *ctrlr) 93 { 94 return 0; 95 } 96 97 int 98 nvme_transport_ctrlr_set_reg_4(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint32_t value) 99 { 100 SPDK_CU_ASSERT_FATAL(offset <= sizeof(struct spdk_nvme_registers) - 4); 101 *(uint32_t *)((uintptr_t)&g_ut_nvme_regs + offset) = value; 102 if (g_set_reg_cb) { 103 g_set_reg_cb(); 104 } 105 return 0; 106 } 107 108 int 109 nvme_transport_ctrlr_set_reg_8(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint64_t value) 110 { 111 SPDK_CU_ASSERT_FATAL(offset <= sizeof(struct spdk_nvme_registers) - 8); 112 *(uint64_t *)((uintptr_t)&g_ut_nvme_regs + offset) = value; 113 if (g_set_reg_cb) { 114 g_set_reg_cb(); 115 } 116 return 0; 117 } 118 119 int 120 nvme_transport_ctrlr_get_reg_4(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint32_t *value) 121 { 122 SPDK_CU_ASSERT_FATAL(offset <= sizeof(struct spdk_nvme_registers) - 4); 123 *value = *(uint32_t *)((uintptr_t)&g_ut_nvme_regs + offset); 124 return 0; 125 } 126 127 int 128 nvme_transport_ctrlr_get_reg_8(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint64_t *value) 129 { 130 SPDK_CU_ASSERT_FATAL(offset <= sizeof(struct spdk_nvme_registers) - 8); 131 *value = *(uint64_t *)((uintptr_t)&g_ut_nvme_regs + offset); 132 return 0; 133 } 134 135 int 136 nvme_transport_ctrlr_set_reg_4_async(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, 137 uint32_t value, spdk_nvme_reg_cb cb_fn, void *cb_arg) 138 { 139 struct spdk_nvme_cpl cpl = {}; 140 141 cpl.status.sct = SPDK_NVME_SCT_GENERIC; 142 cpl.status.sc = SPDK_NVME_SC_SUCCESS; 143 144 nvme_transport_ctrlr_set_reg_4(ctrlr, offset, value); 145 cb_fn(cb_arg, value, &cpl); 146 return 0; 147 } 148 149 int 150 nvme_transport_ctrlr_set_reg_8_async(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, 151 uint64_t value, spdk_nvme_reg_cb cb_fn, void *cb_arg) 152 { 153 struct spdk_nvme_cpl cpl = {}; 154 155 cpl.status.sct = SPDK_NVME_SCT_GENERIC; 156 cpl.status.sc = SPDK_NVME_SC_SUCCESS; 157 158 nvme_transport_ctrlr_set_reg_8(ctrlr, offset, value); 159 cb_fn(cb_arg, value, &cpl); 160 return 0; 161 } 162 163 int 164 nvme_transport_ctrlr_get_reg_4_async(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, 165 spdk_nvme_reg_cb cb_fn, void *cb_arg) 166 { 167 struct spdk_nvme_cpl cpl = {}; 168 uint32_t value; 169 170 cpl.status.sct = SPDK_NVME_SCT_GENERIC; 171 cpl.status.sc = SPDK_NVME_SC_SUCCESS; 172 173 nvme_transport_ctrlr_get_reg_4(ctrlr, offset, &value); 174 cb_fn(cb_arg, value, &cpl); 175 return 0; 176 } 177 178 int 179 nvme_transport_ctrlr_get_reg_8_async(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, 180 spdk_nvme_reg_cb cb_fn, void *cb_arg) 181 { 182 struct spdk_nvme_cpl cpl = {}; 183 uint64_t value; 184 185 cpl.status.sct = SPDK_NVME_SCT_GENERIC; 186 cpl.status.sc = SPDK_NVME_SC_SUCCESS; 187 188 nvme_transport_ctrlr_get_reg_8(ctrlr, offset, &value); 189 cb_fn(cb_arg, value, &cpl); 190 return 0; 191 } 192 193 uint32_t 194 nvme_transport_ctrlr_get_max_xfer_size(struct spdk_nvme_ctrlr *ctrlr) 195 { 196 return UINT32_MAX; 197 } 198 199 uint16_t 200 nvme_transport_ctrlr_get_max_sges(struct spdk_nvme_ctrlr *ctrlr) 201 { 202 return 1; 203 } 204 205 void * 206 nvme_transport_ctrlr_map_cmb(struct spdk_nvme_ctrlr *ctrlr, size_t *size) 207 { 208 return NULL; 209 } 210 211 int 212 nvme_transport_ctrlr_unmap_cmb(struct spdk_nvme_ctrlr *ctrlr) 213 { 214 return 0; 215 } 216 217 int 218 nvme_transport_ctrlr_enable_pmr(struct spdk_nvme_ctrlr *ctrlr) 219 { 220 return 0; 221 } 222 223 int 224 nvme_transport_ctrlr_disable_pmr(struct spdk_nvme_ctrlr *ctrlr) 225 { 226 return 0; 227 } 228 229 void * 230 nvme_transport_ctrlr_map_pmr(struct spdk_nvme_ctrlr *ctrlr, size_t *size) 231 { 232 return NULL; 233 } 234 235 int 236 nvme_transport_ctrlr_unmap_pmr(struct spdk_nvme_ctrlr *ctrlr) 237 { 238 return 0; 239 } 240 241 struct spdk_nvme_qpair * 242 nvme_transport_ctrlr_create_io_qpair(struct spdk_nvme_ctrlr *ctrlr, uint16_t qid, 243 const struct spdk_nvme_io_qpair_opts *opts) 244 { 245 struct spdk_nvme_qpair *qpair; 246 247 qpair = calloc(1, sizeof(*qpair)); 248 SPDK_CU_ASSERT_FATAL(qpair != NULL); 249 250 qpair->ctrlr = ctrlr; 251 qpair->id = qid; 252 qpair->qprio = opts->qprio; 253 254 return qpair; 255 } 256 257 void 258 nvme_transport_ctrlr_delete_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair) 259 { 260 free(qpair); 261 } 262 263 void 264 nvme_transport_ctrlr_disconnect_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair) 265 { 266 } 267 268 int 269 nvme_transport_qpair_reset(struct spdk_nvme_qpair *qpair) 270 { 271 return 0; 272 } 273 274 void 275 nvme_transport_admin_qpair_abort_aers(struct spdk_nvme_qpair *qpair) 276 { 277 } 278 279 void 280 nvme_transport_qpair_abort_reqs(struct spdk_nvme_qpair *qpair, uint32_t dnr) 281 { 282 } 283 284 int 285 nvme_driver_init(void) 286 { 287 return 0; 288 } 289 290 int 291 nvme_qpair_init(struct spdk_nvme_qpair *qpair, uint16_t id, 292 struct spdk_nvme_ctrlr *ctrlr, 293 enum spdk_nvme_qprio qprio, 294 uint32_t num_requests, bool async) 295 { 296 qpair->id = id; 297 qpair->qprio = qprio; 298 qpair->ctrlr = ctrlr; 299 qpair->async = async; 300 301 return 0; 302 } 303 304 static struct spdk_nvme_cpl fake_cpl = {}; 305 static enum spdk_nvme_generic_command_status_code set_status_code = SPDK_NVME_SC_SUCCESS; 306 307 static void 308 fake_cpl_sc(spdk_nvme_cmd_cb cb_fn, void *cb_arg) 309 { 310 fake_cpl.status.sc = set_status_code; 311 cb_fn(cb_arg, &fake_cpl); 312 } 313 314 static uint32_t g_ut_cdw11; 315 316 int 317 spdk_nvme_ctrlr_cmd_set_feature(struct spdk_nvme_ctrlr *ctrlr, uint8_t feature, 318 uint32_t cdw11, uint32_t cdw12, void *payload, uint32_t payload_size, 319 spdk_nvme_cmd_cb cb_fn, void *cb_arg) 320 { 321 g_ut_cdw11 = cdw11; 322 return 0; 323 } 324 325 int 326 spdk_nvme_ctrlr_cmd_get_feature(struct spdk_nvme_ctrlr *ctrlr, uint8_t feature, 327 uint32_t cdw11, void *payload, uint32_t payload_size, 328 spdk_nvme_cmd_cb cb_fn, void *cb_arg) 329 { 330 fake_cpl_sc(cb_fn, cb_arg); 331 return 0; 332 } 333 334 struct spdk_nvme_ana_page *g_ana_hdr; 335 struct spdk_nvme_ana_group_descriptor **g_ana_descs; 336 337 int 338 spdk_nvme_ctrlr_cmd_get_log_page(struct spdk_nvme_ctrlr *ctrlr, uint8_t log_page, 339 uint32_t nsid, void *payload, uint32_t payload_size, 340 uint64_t offset, spdk_nvme_cmd_cb cb_fn, void *cb_arg) 341 { 342 if ((log_page == SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS) && g_ana_hdr) { 343 uint32_t i; 344 uint8_t *ptr = payload; 345 346 memset(payload, 0, payload_size); 347 memcpy(ptr, g_ana_hdr, sizeof(*g_ana_hdr)); 348 ptr += sizeof(*g_ana_hdr); 349 for (i = 0; i < g_ana_hdr->num_ana_group_desc; ++i) { 350 uint32_t desc_size = sizeof(**g_ana_descs) + 351 g_ana_descs[i]->num_of_nsid * sizeof(uint32_t); 352 memcpy(ptr, g_ana_descs[i], desc_size); 353 ptr += desc_size; 354 } 355 } else if (log_page == SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY) { 356 struct spdk_nvme_intel_log_page_directory *log_page_directory = payload; 357 log_page_directory->read_latency_log_len = true; 358 log_page_directory->write_latency_log_len = true; 359 log_page_directory->temperature_statistics_log_len = true; 360 log_page_directory->smart_log_len = true; 361 log_page_directory->marketing_description_log_len = true; 362 } 363 364 fake_cpl_sc(cb_fn, cb_arg); 365 return 0; 366 } 367 368 int 369 spdk_nvme_ctrlr_cmd_get_log_page_ext(struct spdk_nvme_ctrlr *ctrlr, uint8_t log_page, 370 uint32_t nsid, void *payload, uint32_t payload_size, 371 uint64_t offset, uint32_t cdw10, uint32_t cdw11, 372 uint32_t cdw14, spdk_nvme_cmd_cb cb_fn, void *cb_arg) 373 { 374 fake_cpl_sc(cb_fn, cb_arg); 375 return 0; 376 } 377 378 int 379 nvme_qpair_submit_request(struct spdk_nvme_qpair *qpair, struct nvme_request *req) 380 { 381 CU_ASSERT(req->cmd.opc == SPDK_NVME_OPC_ASYNC_EVENT_REQUEST); 382 STAILQ_INSERT_HEAD(&qpair->free_req, req, stailq); 383 384 /* 385 * For the purposes of this unit test, we don't need to bother emulating request submission. 386 */ 387 388 return 0; 389 } 390 391 static int32_t g_wait_for_completion_return_val; 392 393 int32_t 394 spdk_nvme_qpair_process_completions(struct spdk_nvme_qpair *qpair, uint32_t max_completions) 395 { 396 return g_wait_for_completion_return_val; 397 } 398 399 void 400 nvme_qpair_complete_error_reqs(struct spdk_nvme_qpair *qpair) 401 { 402 } 403 404 405 void 406 nvme_completion_poll_cb(void *arg, const struct spdk_nvme_cpl *cpl) 407 { 408 struct nvme_completion_poll_status *status = arg; 409 /* This should not happen it test env since this callback is always called 410 * before wait_for_completion_* while this field can only be set to true in 411 * wait_for_completion_* functions */ 412 CU_ASSERT(status->timed_out == false); 413 414 status->cpl = *cpl; 415 status->done = true; 416 } 417 418 static struct nvme_completion_poll_status *g_failed_status; 419 420 int 421 nvme_wait_for_completion_robust_lock_timeout( 422 struct spdk_nvme_qpair *qpair, 423 struct nvme_completion_poll_status *status, 424 pthread_mutex_t *robust_mutex, 425 uint64_t timeout_in_usecs) 426 { 427 if (spdk_nvme_qpair_process_completions(qpair, 0) < 0) { 428 g_failed_status = status; 429 status->timed_out = true; 430 return -1; 431 } 432 433 status->done = true; 434 if (set_status_cpl == 1) { 435 status->cpl.status.sc = 1; 436 } 437 return spdk_nvme_cpl_is_error(&status->cpl) ? -EIO : 0; 438 } 439 440 int 441 nvme_wait_for_completion_robust_lock( 442 struct spdk_nvme_qpair *qpair, 443 struct nvme_completion_poll_status *status, 444 pthread_mutex_t *robust_mutex) 445 { 446 return nvme_wait_for_completion_robust_lock_timeout(qpair, status, robust_mutex, 0); 447 } 448 449 int 450 nvme_wait_for_completion(struct spdk_nvme_qpair *qpair, 451 struct nvme_completion_poll_status *status) 452 { 453 return nvme_wait_for_completion_robust_lock_timeout(qpair, status, NULL, 0); 454 } 455 456 int 457 nvme_wait_for_completion_timeout(struct spdk_nvme_qpair *qpair, 458 struct nvme_completion_poll_status *status, 459 uint64_t timeout_in_usecs) 460 { 461 return nvme_wait_for_completion_robust_lock_timeout(qpair, status, NULL, timeout_in_usecs); 462 } 463 464 int 465 nvme_ctrlr_cmd_set_async_event_config(struct spdk_nvme_ctrlr *ctrlr, 466 union spdk_nvme_feat_async_event_configuration config, spdk_nvme_cmd_cb cb_fn, 467 void *cb_arg) 468 { 469 fake_cpl_sc(cb_fn, cb_arg); 470 return 0; 471 } 472 473 static uint32_t *g_active_ns_list = NULL; 474 static uint32_t g_active_ns_list_length = 0; 475 static struct spdk_nvme_ctrlr_data *g_cdata = NULL; 476 static bool g_fail_next_identify = false; 477 478 int 479 nvme_ctrlr_cmd_identify(struct spdk_nvme_ctrlr *ctrlr, uint8_t cns, uint16_t cntid, uint32_t nsid, 480 uint8_t csi, void *payload, size_t payload_size, 481 spdk_nvme_cmd_cb cb_fn, void *cb_arg) 482 { 483 if (g_fail_next_identify) { 484 g_fail_next_identify = false; 485 return 1; 486 } 487 488 memset(payload, 0, payload_size); 489 if (cns == SPDK_NVME_IDENTIFY_ACTIVE_NS_LIST) { 490 uint32_t count = 0; 491 uint32_t i = 0; 492 struct spdk_nvme_ns_list *ns_list = (struct spdk_nvme_ns_list *)payload; 493 494 if (g_active_ns_list == NULL) { 495 for (i = 1; i <= ctrlr->cdata.nn; i++) { 496 if (i <= nsid) { 497 continue; 498 } 499 500 ns_list->ns_list[count++] = i; 501 if (count == SPDK_COUNTOF(ns_list->ns_list)) { 502 break; 503 } 504 } 505 } else { 506 for (i = 0; i < g_active_ns_list_length; i++) { 507 uint32_t cur_nsid = g_active_ns_list[i]; 508 if (cur_nsid <= nsid) { 509 continue; 510 } 511 512 ns_list->ns_list[count++] = cur_nsid; 513 if (count == SPDK_COUNTOF(ns_list->ns_list)) { 514 break; 515 } 516 } 517 } 518 } else if (cns == SPDK_NVME_IDENTIFY_CTRLR) { 519 if (g_cdata) { 520 memcpy(payload, g_cdata, sizeof(*g_cdata)); 521 } 522 } else if (cns == SPDK_NVME_IDENTIFY_NS_IOCS) { 523 return 0; 524 } 525 526 fake_cpl_sc(cb_fn, cb_arg); 527 return 0; 528 } 529 530 int 531 nvme_ctrlr_cmd_set_num_queues(struct spdk_nvme_ctrlr *ctrlr, 532 uint32_t num_queues, spdk_nvme_cmd_cb cb_fn, void *cb_arg) 533 { 534 fake_cpl_sc(cb_fn, cb_arg); 535 return 0; 536 } 537 538 int 539 nvme_ctrlr_cmd_get_num_queues(struct spdk_nvme_ctrlr *ctrlr, 540 spdk_nvme_cmd_cb cb_fn, void *cb_arg) 541 { 542 CU_ASSERT(0); 543 return -1; 544 } 545 546 int 547 nvme_ctrlr_cmd_attach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, 548 struct spdk_nvme_ctrlr_list *payload, spdk_nvme_cmd_cb cb_fn, void *cb_arg) 549 { 550 return 0; 551 } 552 553 int 554 nvme_ctrlr_cmd_detach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, 555 struct spdk_nvme_ctrlr_list *payload, spdk_nvme_cmd_cb cb_fn, void *cb_arg) 556 { 557 return 0; 558 } 559 560 int 561 nvme_ctrlr_cmd_create_ns(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_ns_data *payload, 562 spdk_nvme_cmd_cb cb_fn, void *cb_arg) 563 { 564 fake_cpl_sc(cb_fn, cb_arg); 565 return 0; 566 } 567 568 int 569 nvme_ctrlr_cmd_delete_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, spdk_nvme_cmd_cb cb_fn, 570 void *cb_arg) 571 { 572 return 0; 573 } 574 575 int 576 nvme_ctrlr_cmd_format(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, struct spdk_nvme_format *format, 577 spdk_nvme_cmd_cb cb_fn, void *cb_arg) 578 { 579 return 0; 580 } 581 582 int 583 spdk_nvme_ctrlr_cmd_directive_send(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, 584 uint32_t doper, uint32_t dtype, uint32_t dspec, 585 void *payload, uint32_t payload_size, uint32_t cdw12, 586 uint32_t cdw13, spdk_nvme_cmd_cb cb_fn, void *cb_arg) 587 { 588 return 0; 589 } 590 591 int 592 spdk_nvme_ctrlr_cmd_directive_receive(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, 593 uint32_t doper, uint32_t dtype, uint32_t dspec, 594 void *payload, uint32_t payload_size, uint32_t cdw12, 595 uint32_t cdw13, spdk_nvme_cmd_cb cb_fn, void *cb_arg) 596 { 597 return 0; 598 } 599 600 int 601 nvme_ctrlr_cmd_fw_commit(struct spdk_nvme_ctrlr *ctrlr, const struct spdk_nvme_fw_commit *fw_commit, 602 spdk_nvme_cmd_cb cb_fn, void *cb_arg) 603 { 604 CU_ASSERT(fw_commit->ca == SPDK_NVME_FW_COMMIT_REPLACE_IMG); 605 if (fw_commit->fs == 0) { 606 return -1; 607 } 608 set_status_cpl = 1; 609 if (ctrlr->is_resetting == true) { 610 set_status_cpl = 0; 611 } 612 return 0; 613 } 614 615 int 616 nvme_ctrlr_cmd_fw_image_download(struct spdk_nvme_ctrlr *ctrlr, 617 uint32_t size, uint32_t offset, void *payload, 618 spdk_nvme_cmd_cb cb_fn, void *cb_arg) 619 { 620 if ((size != 0 && payload == NULL) || (size == 0 && payload != NULL)) { 621 return -1; 622 } 623 CU_ASSERT(offset == 0); 624 return 0; 625 } 626 627 bool 628 nvme_ns_has_supported_iocs_specific_data(struct spdk_nvme_ns *ns) 629 { 630 switch (ns->csi) { 631 case SPDK_NVME_CSI_NVM: 632 /* 633 * NVM Command Set Specific Identify Namespace data structure 634 * is currently all-zeroes, reserved for future use. 635 */ 636 return false; 637 case SPDK_NVME_CSI_ZNS: 638 return true; 639 default: 640 SPDK_WARNLOG("Unsupported CSI: %u for NSID: %u\n", ns->csi, ns->id); 641 return false; 642 } 643 } 644 645 void 646 nvme_ns_free_zns_specific_data(struct spdk_nvme_ns *ns) 647 { 648 if (!ns->id) { 649 return; 650 } 651 652 if (ns->nsdata_zns) { 653 spdk_free(ns->nsdata_zns); 654 ns->nsdata_zns = NULL; 655 } 656 } 657 658 void 659 nvme_ns_destruct(struct spdk_nvme_ns *ns) 660 { 661 } 662 663 int 664 nvme_ns_construct(struct spdk_nvme_ns *ns, uint32_t id, 665 struct spdk_nvme_ctrlr *ctrlr) 666 { 667 return 0; 668 } 669 670 void 671 spdk_pci_device_detach(struct spdk_pci_device *device) 672 { 673 } 674 675 #define DECLARE_AND_CONSTRUCT_CTRLR() \ 676 struct spdk_nvme_ctrlr ctrlr = {}; \ 677 struct spdk_nvme_qpair adminq = {}; \ 678 struct nvme_request req; \ 679 \ 680 STAILQ_INIT(&adminq.free_req); \ 681 STAILQ_INSERT_HEAD(&adminq.free_req, &req, stailq); \ 682 ctrlr.adminq = &adminq; 683 684 static void 685 test_nvme_ctrlr_init_en_1_rdy_0(void) 686 { 687 DECLARE_AND_CONSTRUCT_CTRLR(); 688 689 memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs)); 690 691 /* 692 * Initial state: CC.EN = 1, CSTS.RDY = 0 693 */ 694 g_ut_nvme_regs.cc.bits.en = 1; 695 g_ut_nvme_regs.csts.bits.rdy = 0; 696 697 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 698 ctrlr.cdata.nn = 1; 699 ctrlr.page_size = 0x1000; 700 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 701 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 702 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 703 } 704 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 705 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1); 706 707 /* 708 * Transition to CSTS.RDY = 1. 709 * init() should set CC.EN = 0. 710 */ 711 g_ut_nvme_regs.csts.bits.rdy = 1; 712 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 713 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_EN_0); 714 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 715 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 716 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); 717 718 /* 719 * Transition to CSTS.RDY = 0. 720 */ 721 g_ut_nvme_regs.csts.bits.rdy = 0; 722 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 723 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 724 725 /* 726 * Start enabling the controller. 727 */ 728 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 729 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 730 731 /* 732 * Transition to CC.EN = 1 733 */ 734 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 735 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 736 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 737 738 /* 739 * Transition to CSTS.RDY = 1. 740 */ 741 g_ut_nvme_regs.csts.bits.rdy = 1; 742 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 743 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE); 744 745 /* 746 * Transition to READY. 747 */ 748 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 749 nvme_ctrlr_process_init(&ctrlr); 750 } 751 752 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 753 nvme_ctrlr_destruct(&ctrlr); 754 } 755 756 static void 757 test_nvme_ctrlr_init_en_1_rdy_1(void) 758 { 759 DECLARE_AND_CONSTRUCT_CTRLR(); 760 761 memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs)); 762 763 /* 764 * Initial state: CC.EN = 1, CSTS.RDY = 1 765 * init() should set CC.EN = 0. 766 */ 767 g_ut_nvme_regs.cc.bits.en = 1; 768 g_ut_nvme_regs.csts.bits.rdy = 1; 769 770 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 771 ctrlr.cdata.nn = 1; 772 ctrlr.page_size = 0x1000; 773 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 774 while (ctrlr.state != NVME_CTRLR_STATE_SET_EN_0) { 775 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 776 } 777 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 778 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 779 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); 780 781 /* 782 * Transition to CSTS.RDY = 0. 783 */ 784 g_ut_nvme_regs.csts.bits.rdy = 0; 785 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 786 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 787 788 /* 789 * Start enabling the controller. 790 */ 791 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 792 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 793 794 /* 795 * Transition to CC.EN = 1 796 */ 797 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 798 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 799 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 800 801 /* 802 * Transition to CSTS.RDY = 1. 803 */ 804 g_ut_nvme_regs.csts.bits.rdy = 1; 805 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 806 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE); 807 808 /* 809 * Transition to READY. 810 */ 811 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 812 nvme_ctrlr_process_init(&ctrlr); 813 } 814 815 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 816 nvme_ctrlr_destruct(&ctrlr); 817 } 818 819 static void 820 test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) 821 { 822 DECLARE_AND_CONSTRUCT_CTRLR(); 823 824 memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs)); 825 826 /* 827 * Initial state: CC.EN = 0, CSTS.RDY = 0 828 * init() should set CC.EN = 1. 829 */ 830 g_ut_nvme_regs.cc.bits.en = 0; 831 g_ut_nvme_regs.csts.bits.rdy = 0; 832 833 /* 834 * Default round robin enabled 835 */ 836 g_ut_nvme_regs.cap.bits.ams = 0x0; 837 ctrlr.cap = g_ut_nvme_regs.cap; 838 839 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 840 ctrlr.cdata.nn = 1; 841 ctrlr.page_size = 0x1000; 842 /* 843 * Case 1: default round robin arbitration mechanism selected 844 */ 845 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_RR; 846 847 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 848 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 849 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 850 } 851 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 852 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 853 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 854 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 855 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 856 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 857 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 858 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 859 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 860 CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR); 861 CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_RR); 862 863 /* 864 * Complete and destroy the controller 865 */ 866 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 867 nvme_ctrlr_destruct(&ctrlr); 868 869 /* 870 * Reset to initial state 871 */ 872 g_ut_nvme_regs.cc.bits.en = 0; 873 g_ut_nvme_regs.csts.bits.rdy = 0; 874 875 /* 876 * Case 2: weighted round robin arbitration mechanism selected 877 */ 878 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 879 ctrlr.cdata.nn = 1; 880 ctrlr.page_size = 0x1000; 881 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR; 882 883 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 884 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 885 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 886 } 887 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 888 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 889 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 890 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 891 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 892 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 893 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); 894 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); 895 896 /* 897 * Complete and destroy the controller 898 */ 899 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 900 nvme_ctrlr_destruct(&ctrlr); 901 902 /* 903 * Reset to initial state 904 */ 905 g_ut_nvme_regs.cc.bits.en = 0; 906 g_ut_nvme_regs.csts.bits.rdy = 0; 907 908 /* 909 * Case 3: vendor specific arbitration mechanism selected 910 */ 911 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 912 ctrlr.cdata.nn = 1; 913 ctrlr.page_size = 0x1000; 914 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS; 915 916 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 917 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 918 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 919 } 920 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 921 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 922 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 923 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 924 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 925 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 926 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); 927 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); 928 929 /* 930 * Complete and destroy the controller 931 */ 932 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 933 nvme_ctrlr_destruct(&ctrlr); 934 935 /* 936 * Reset to initial state 937 */ 938 g_ut_nvme_regs.cc.bits.en = 0; 939 g_ut_nvme_regs.csts.bits.rdy = 0; 940 941 /* 942 * Case 4: invalid arbitration mechanism selected 943 */ 944 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 945 ctrlr.cdata.nn = 1; 946 ctrlr.page_size = 0x1000; 947 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS + 1; 948 949 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 950 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 951 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 952 } 953 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 954 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 955 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 956 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 957 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 958 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 959 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); 960 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); 961 962 /* 963 * Complete and destroy the controller 964 */ 965 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 966 nvme_ctrlr_destruct(&ctrlr); 967 968 /* 969 * Reset to initial state 970 */ 971 g_ut_nvme_regs.cc.bits.en = 0; 972 g_ut_nvme_regs.csts.bits.rdy = 0; 973 974 /* 975 * Case 5: reset to default round robin arbitration mechanism 976 */ 977 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 978 ctrlr.cdata.nn = 1; 979 ctrlr.page_size = 0x1000; 980 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_RR; 981 982 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 983 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 984 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 985 } 986 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 987 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 988 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 989 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 990 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 991 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 992 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 993 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 994 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 995 CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR); 996 CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_RR); 997 998 /* 999 * Transition to CSTS.RDY = 1. 1000 */ 1001 g_ut_nvme_regs.csts.bits.rdy = 1; 1002 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1003 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE); 1004 1005 /* 1006 * Transition to READY. 1007 */ 1008 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 1009 nvme_ctrlr_process_init(&ctrlr); 1010 } 1011 1012 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1013 nvme_ctrlr_destruct(&ctrlr); 1014 } 1015 1016 static void 1017 test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void) 1018 { 1019 DECLARE_AND_CONSTRUCT_CTRLR(); 1020 1021 memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs)); 1022 1023 /* 1024 * Initial state: CC.EN = 0, CSTS.RDY = 0 1025 * init() should set CC.EN = 1. 1026 */ 1027 g_ut_nvme_regs.cc.bits.en = 0; 1028 g_ut_nvme_regs.csts.bits.rdy = 0; 1029 1030 /* 1031 * Weighted round robin enabled 1032 */ 1033 g_ut_nvme_regs.cap.bits.ams = SPDK_NVME_CAP_AMS_WRR; 1034 ctrlr.cap = g_ut_nvme_regs.cap; 1035 1036 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 1037 ctrlr.cdata.nn = 1; 1038 ctrlr.page_size = 0x1000; 1039 /* 1040 * Case 1: default round robin arbitration mechanism selected 1041 */ 1042 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_RR; 1043 1044 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 1045 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 1046 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1047 } 1048 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1049 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 1050 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1051 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 1052 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1053 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 1054 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1055 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 1056 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 1057 CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR); 1058 CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_RR); 1059 1060 /* 1061 * Complete and destroy the controller 1062 */ 1063 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1064 nvme_ctrlr_destruct(&ctrlr); 1065 1066 /* 1067 * Reset to initial state 1068 */ 1069 g_ut_nvme_regs.cc.bits.en = 0; 1070 g_ut_nvme_regs.csts.bits.rdy = 0; 1071 1072 /* 1073 * Case 2: weighted round robin arbitration mechanism selected 1074 */ 1075 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 1076 ctrlr.cdata.nn = 1; 1077 ctrlr.page_size = 0x1000; 1078 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR; 1079 1080 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 1081 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 1082 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1083 } 1084 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1085 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 1086 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1087 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 1088 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1089 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 1090 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1091 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 1092 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 1093 CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_WRR); 1094 CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_WRR); 1095 1096 /* 1097 * Complete and destroy the controller 1098 */ 1099 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1100 nvme_ctrlr_destruct(&ctrlr); 1101 1102 /* 1103 * Reset to initial state 1104 */ 1105 g_ut_nvme_regs.cc.bits.en = 0; 1106 g_ut_nvme_regs.csts.bits.rdy = 0; 1107 1108 /* 1109 * Case 3: vendor specific arbitration mechanism selected 1110 */ 1111 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 1112 ctrlr.cdata.nn = 1; 1113 ctrlr.page_size = 0x1000; 1114 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS; 1115 1116 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 1117 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 1118 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1119 } 1120 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1121 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 1122 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1123 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 1124 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1125 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 1126 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); 1127 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); 1128 1129 /* 1130 * Complete and destroy the controller 1131 */ 1132 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1133 nvme_ctrlr_destruct(&ctrlr); 1134 1135 /* 1136 * Reset to initial state 1137 */ 1138 g_ut_nvme_regs.cc.bits.en = 0; 1139 g_ut_nvme_regs.csts.bits.rdy = 0; 1140 1141 /* 1142 * Case 4: invalid arbitration mechanism selected 1143 */ 1144 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 1145 ctrlr.cdata.nn = 1; 1146 ctrlr.page_size = 0x1000; 1147 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS + 1; 1148 1149 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 1150 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 1151 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1152 } 1153 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1154 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 1155 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1156 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 1157 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1158 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 1159 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); 1160 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); 1161 1162 /* 1163 * Complete and destroy the controller 1164 */ 1165 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1166 nvme_ctrlr_destruct(&ctrlr); 1167 1168 /* 1169 * Reset to initial state 1170 */ 1171 g_ut_nvme_regs.cc.bits.en = 0; 1172 g_ut_nvme_regs.csts.bits.rdy = 0; 1173 1174 /* 1175 * Case 5: reset to weighted round robin arbitration mechanism 1176 */ 1177 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 1178 ctrlr.cdata.nn = 1; 1179 ctrlr.page_size = 0x1000; 1180 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR; 1181 1182 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 1183 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 1184 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1185 } 1186 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1187 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 1188 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1189 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 1190 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1191 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 1192 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1193 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 1194 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 1195 CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_WRR); 1196 CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_WRR); 1197 1198 /* 1199 * Transition to CSTS.RDY = 1. 1200 */ 1201 g_ut_nvme_regs.csts.bits.rdy = 1; 1202 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1203 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE); 1204 1205 /* 1206 * Transition to READY. 1207 */ 1208 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 1209 nvme_ctrlr_process_init(&ctrlr); 1210 } 1211 1212 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1213 nvme_ctrlr_destruct(&ctrlr); 1214 } 1215 static void 1216 test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void) 1217 { 1218 DECLARE_AND_CONSTRUCT_CTRLR(); 1219 1220 memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs)); 1221 1222 /* 1223 * Initial state: CC.EN = 0, CSTS.RDY = 0 1224 * init() should set CC.EN = 1. 1225 */ 1226 g_ut_nvme_regs.cc.bits.en = 0; 1227 g_ut_nvme_regs.csts.bits.rdy = 0; 1228 1229 /* 1230 * Default round robin enabled 1231 */ 1232 g_ut_nvme_regs.cap.bits.ams = SPDK_NVME_CAP_AMS_VS; 1233 ctrlr.cap = g_ut_nvme_regs.cap; 1234 1235 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 1236 ctrlr.cdata.nn = 1; 1237 ctrlr.page_size = 0x1000; 1238 /* 1239 * Case 1: default round robin arbitration mechanism selected 1240 */ 1241 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_RR; 1242 1243 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 1244 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 1245 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1246 } 1247 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1248 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 1249 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1250 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 1251 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1252 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 1253 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1254 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 1255 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 1256 CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR); 1257 CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_RR); 1258 1259 /* 1260 * Complete and destroy the controller 1261 */ 1262 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1263 nvme_ctrlr_destruct(&ctrlr); 1264 1265 /* 1266 * Reset to initial state 1267 */ 1268 g_ut_nvme_regs.cc.bits.en = 0; 1269 g_ut_nvme_regs.csts.bits.rdy = 0; 1270 1271 /* 1272 * Case 2: weighted round robin arbitration mechanism selected 1273 */ 1274 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 1275 ctrlr.cdata.nn = 1; 1276 ctrlr.page_size = 0x1000; 1277 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR; 1278 1279 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 1280 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 1281 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1282 } 1283 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1284 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 1285 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1286 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 1287 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1288 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 1289 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); 1290 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); 1291 1292 /* 1293 * Complete and destroy the controller 1294 */ 1295 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1296 nvme_ctrlr_destruct(&ctrlr); 1297 1298 /* 1299 * Reset to initial state 1300 */ 1301 g_ut_nvme_regs.cc.bits.en = 0; 1302 g_ut_nvme_regs.csts.bits.rdy = 0; 1303 1304 /* 1305 * Case 3: vendor specific arbitration mechanism selected 1306 */ 1307 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 1308 ctrlr.cdata.nn = 1; 1309 ctrlr.page_size = 0x1000; 1310 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS; 1311 1312 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 1313 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 1314 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1315 } 1316 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1317 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 1318 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1319 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 1320 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1321 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 1322 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1323 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 1324 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 1325 CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_VS); 1326 CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_VS); 1327 1328 /* 1329 * Complete and destroy the controller 1330 */ 1331 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1332 nvme_ctrlr_destruct(&ctrlr); 1333 1334 /* 1335 * Reset to initial state 1336 */ 1337 g_ut_nvme_regs.cc.bits.en = 0; 1338 g_ut_nvme_regs.csts.bits.rdy = 0; 1339 1340 /* 1341 * Case 4: invalid arbitration mechanism selected 1342 */ 1343 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 1344 ctrlr.cdata.nn = 1; 1345 ctrlr.page_size = 0x1000; 1346 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS + 1; 1347 1348 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 1349 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 1350 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1351 } 1352 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1353 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 1354 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1355 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 1356 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1357 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 1358 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); 1359 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); 1360 1361 /* 1362 * Complete and destroy the controller 1363 */ 1364 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1365 nvme_ctrlr_destruct(&ctrlr); 1366 1367 /* 1368 * Reset to initial state 1369 */ 1370 g_ut_nvme_regs.cc.bits.en = 0; 1371 g_ut_nvme_regs.csts.bits.rdy = 0; 1372 1373 /* 1374 * Case 5: reset to vendor specific arbitration mechanism 1375 */ 1376 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 1377 ctrlr.cdata.nn = 1; 1378 ctrlr.page_size = 0x1000; 1379 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS; 1380 1381 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 1382 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 1383 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1384 } 1385 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1386 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 1387 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1388 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 1389 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1390 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 1391 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1392 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 1393 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 1394 CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_VS); 1395 CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_VS); 1396 1397 /* 1398 * Transition to CSTS.RDY = 1. 1399 */ 1400 g_ut_nvme_regs.csts.bits.rdy = 1; 1401 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1402 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE); 1403 1404 /* 1405 * Transition to READY. 1406 */ 1407 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 1408 nvme_ctrlr_process_init(&ctrlr); 1409 } 1410 1411 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1412 nvme_ctrlr_destruct(&ctrlr); 1413 } 1414 1415 static void 1416 test_nvme_ctrlr_init_en_0_rdy_0(void) 1417 { 1418 DECLARE_AND_CONSTRUCT_CTRLR(); 1419 1420 memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs)); 1421 1422 /* 1423 * Initial state: CC.EN = 0, CSTS.RDY = 0 1424 * init() should set CC.EN = 1. 1425 */ 1426 g_ut_nvme_regs.cc.bits.en = 0; 1427 g_ut_nvme_regs.csts.bits.rdy = 0; 1428 1429 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 1430 ctrlr.cdata.nn = 1; 1431 ctrlr.page_size = 0x1000; 1432 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 1433 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 1434 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1435 } 1436 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1437 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 1438 1439 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1440 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 1441 1442 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1443 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 1444 1445 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1446 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 1447 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 1448 1449 /* 1450 * Transition to CSTS.RDY = 1. 1451 */ 1452 g_ut_nvme_regs.csts.bits.rdy = 1; 1453 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1454 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE); 1455 1456 /* 1457 * Transition to READY. 1458 */ 1459 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 1460 nvme_ctrlr_process_init(&ctrlr); 1461 } 1462 1463 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1464 nvme_ctrlr_destruct(&ctrlr); 1465 } 1466 1467 static void 1468 test_nvme_ctrlr_init_en_0_rdy_1(void) 1469 { 1470 DECLARE_AND_CONSTRUCT_CTRLR(); 1471 1472 memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs)); 1473 1474 /* 1475 * Initial state: CC.EN = 0, CSTS.RDY = 1 1476 */ 1477 g_ut_nvme_regs.cc.bits.en = 0; 1478 g_ut_nvme_regs.csts.bits.rdy = 1; 1479 1480 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 1481 ctrlr.cdata.nn = 1; 1482 ctrlr.page_size = 0x1000; 1483 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 1484 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 1485 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1486 } 1487 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1488 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 1489 1490 /* 1491 * Transition to CSTS.RDY = 0. 1492 */ 1493 g_ut_nvme_regs.csts.bits.rdy = 0; 1494 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1495 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 1496 1497 /* 1498 * Start enabling the controller. 1499 */ 1500 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1501 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 1502 1503 /* 1504 * Transition to CC.EN = 1 1505 */ 1506 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1507 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 1508 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 1509 1510 /* 1511 * Transition to CSTS.RDY = 1. 1512 */ 1513 g_ut_nvme_regs.csts.bits.rdy = 1; 1514 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1515 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE); 1516 1517 /* 1518 * Transition to READY. 1519 */ 1520 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 1521 nvme_ctrlr_process_init(&ctrlr); 1522 } 1523 1524 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1525 nvme_ctrlr_destruct(&ctrlr); 1526 } 1527 1528 static void 1529 setup_qpairs(struct spdk_nvme_ctrlr *ctrlr, uint32_t num_io_queues) 1530 { 1531 uint32_t i; 1532 1533 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(ctrlr) == 0); 1534 1535 ctrlr->page_size = 0x1000; 1536 ctrlr->opts.num_io_queues = num_io_queues; 1537 ctrlr->free_io_qids = spdk_bit_array_create(num_io_queues + 1); 1538 ctrlr->state = NVME_CTRLR_STATE_READY; 1539 SPDK_CU_ASSERT_FATAL(ctrlr->free_io_qids != NULL); 1540 1541 spdk_bit_array_clear(ctrlr->free_io_qids, 0); 1542 for (i = 1; i <= num_io_queues; i++) { 1543 spdk_bit_array_set(ctrlr->free_io_qids, i); 1544 } 1545 } 1546 1547 static void 1548 cleanup_qpairs(struct spdk_nvme_ctrlr *ctrlr) 1549 { 1550 nvme_ctrlr_destruct(ctrlr); 1551 } 1552 1553 static void 1554 test_alloc_io_qpair_rr_1(void) 1555 { 1556 struct spdk_nvme_io_qpair_opts opts; 1557 struct spdk_nvme_ctrlr ctrlr = {}; 1558 struct spdk_nvme_qpair *q0; 1559 1560 setup_qpairs(&ctrlr, 1); 1561 1562 /* 1563 * Fake to simulate the controller with default round robin 1564 * arbitration mechanism. 1565 */ 1566 g_ut_nvme_regs.cc.bits.ams = SPDK_NVME_CC_AMS_RR; 1567 1568 spdk_nvme_ctrlr_get_default_io_qpair_opts(&ctrlr, &opts, sizeof(opts)); 1569 1570 q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, NULL, 0); 1571 SPDK_CU_ASSERT_FATAL(q0 != NULL); 1572 SPDK_CU_ASSERT_FATAL(q0->qprio == 0); 1573 /* Only 1 I/O qpair was allocated, so this should fail */ 1574 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, NULL, 0) == NULL); 1575 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q0) == 0); 1576 1577 /* 1578 * Now that the qpair has been returned to the free list, 1579 * we should be able to allocate it again. 1580 */ 1581 q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, NULL, 0); 1582 SPDK_CU_ASSERT_FATAL(q0 != NULL); 1583 SPDK_CU_ASSERT_FATAL(q0->qprio == 0); 1584 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q0) == 0); 1585 1586 /* Only 0 qprio is acceptable for default round robin arbitration mechanism */ 1587 opts.qprio = 1; 1588 q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1589 SPDK_CU_ASSERT_FATAL(q0 == NULL); 1590 1591 opts.qprio = 2; 1592 q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1593 SPDK_CU_ASSERT_FATAL(q0 == NULL); 1594 1595 opts.qprio = 3; 1596 q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1597 SPDK_CU_ASSERT_FATAL(q0 == NULL); 1598 1599 /* Only 0 ~ 3 qprio is acceptable */ 1600 opts.qprio = 4; 1601 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)) == NULL); 1602 opts.qprio = 0; 1603 1604 /* IO qpair can only be created when ctrlr is in READY state */ 1605 ctrlr.state = NVME_CTRLR_STATE_ENABLE; 1606 q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1607 SPDK_CU_ASSERT_FATAL(q0 == NULL); 1608 ctrlr.state = NVME_CTRLR_STATE_READY; 1609 1610 cleanup_qpairs(&ctrlr); 1611 } 1612 1613 static void 1614 test_alloc_io_qpair_wrr_1(void) 1615 { 1616 struct spdk_nvme_io_qpair_opts opts; 1617 struct spdk_nvme_ctrlr ctrlr = {}; 1618 struct spdk_nvme_qpair *q0, *q1; 1619 1620 setup_qpairs(&ctrlr, 2); 1621 1622 /* 1623 * Fake to simulate the controller with weighted round robin 1624 * arbitration mechanism. 1625 */ 1626 ctrlr.process_init_cc.bits.ams = SPDK_NVME_CC_AMS_WRR; 1627 1628 spdk_nvme_ctrlr_get_default_io_qpair_opts(&ctrlr, &opts, sizeof(opts)); 1629 1630 /* 1631 * Allocate 2 qpairs and free them 1632 */ 1633 opts.qprio = 0; 1634 q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1635 SPDK_CU_ASSERT_FATAL(q0 != NULL); 1636 SPDK_CU_ASSERT_FATAL(q0->qprio == 0); 1637 1638 opts.qprio = 1; 1639 q1 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1640 SPDK_CU_ASSERT_FATAL(q1 != NULL); 1641 SPDK_CU_ASSERT_FATAL(q1->qprio == 1); 1642 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q1) == 0); 1643 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q0) == 0); 1644 1645 /* 1646 * Allocate 2 qpairs and free them in the reverse order 1647 */ 1648 opts.qprio = 2; 1649 q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1650 SPDK_CU_ASSERT_FATAL(q0 != NULL); 1651 SPDK_CU_ASSERT_FATAL(q0->qprio == 2); 1652 1653 opts.qprio = 3; 1654 q1 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1655 SPDK_CU_ASSERT_FATAL(q1 != NULL); 1656 SPDK_CU_ASSERT_FATAL(q1->qprio == 3); 1657 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q0) == 0); 1658 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q1) == 0); 1659 1660 /* Only 0 ~ 3 qprio is acceptable */ 1661 opts.qprio = 4; 1662 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)) == NULL); 1663 1664 cleanup_qpairs(&ctrlr); 1665 } 1666 1667 static void 1668 test_alloc_io_qpair_wrr_2(void) 1669 { 1670 struct spdk_nvme_io_qpair_opts opts; 1671 struct spdk_nvme_ctrlr ctrlr = {}; 1672 struct spdk_nvme_qpair *q0, *q1, *q2, *q3; 1673 1674 setup_qpairs(&ctrlr, 4); 1675 1676 /* 1677 * Fake to simulate the controller with weighted round robin 1678 * arbitration mechanism. 1679 */ 1680 ctrlr.process_init_cc.bits.ams = SPDK_NVME_CC_AMS_WRR; 1681 1682 spdk_nvme_ctrlr_get_default_io_qpair_opts(&ctrlr, &opts, sizeof(opts)); 1683 1684 opts.qprio = 0; 1685 q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1686 SPDK_CU_ASSERT_FATAL(q0 != NULL); 1687 SPDK_CU_ASSERT_FATAL(q0->qprio == 0); 1688 1689 opts.qprio = 1; 1690 q1 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1691 SPDK_CU_ASSERT_FATAL(q1 != NULL); 1692 SPDK_CU_ASSERT_FATAL(q1->qprio == 1); 1693 1694 opts.qprio = 2; 1695 q2 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1696 SPDK_CU_ASSERT_FATAL(q2 != NULL); 1697 SPDK_CU_ASSERT_FATAL(q2->qprio == 2); 1698 1699 opts.qprio = 3; 1700 q3 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1701 SPDK_CU_ASSERT_FATAL(q3 != NULL); 1702 SPDK_CU_ASSERT_FATAL(q3->qprio == 3); 1703 1704 /* Only 4 I/O qpairs was allocated, so this should fail */ 1705 opts.qprio = 0; 1706 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)) == NULL); 1707 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q3) == 0); 1708 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q2) == 0); 1709 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q1) == 0); 1710 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q0) == 0); 1711 1712 /* 1713 * Now that the qpair has been returned to the free list, 1714 * we should be able to allocate it again. 1715 * 1716 * Allocate 4 I/O qpairs and half of them with same qprio. 1717 */ 1718 opts.qprio = 1; 1719 q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1720 SPDK_CU_ASSERT_FATAL(q0 != NULL); 1721 SPDK_CU_ASSERT_FATAL(q0->qprio == 1); 1722 1723 opts.qprio = 1; 1724 q1 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1725 SPDK_CU_ASSERT_FATAL(q1 != NULL); 1726 SPDK_CU_ASSERT_FATAL(q1->qprio == 1); 1727 1728 opts.qprio = 3; 1729 q2 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1730 SPDK_CU_ASSERT_FATAL(q2 != NULL); 1731 SPDK_CU_ASSERT_FATAL(q2->qprio == 3); 1732 1733 opts.qprio = 3; 1734 q3 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1735 SPDK_CU_ASSERT_FATAL(q3 != NULL); 1736 SPDK_CU_ASSERT_FATAL(q3->qprio == 3); 1737 1738 /* 1739 * Free all I/O qpairs in reverse order 1740 */ 1741 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q0) == 0); 1742 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q1) == 0); 1743 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q2) == 0); 1744 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q3) == 0); 1745 1746 cleanup_qpairs(&ctrlr); 1747 } 1748 1749 bool g_connect_qpair_called = false; 1750 int g_connect_qpair_return_code = 0; 1751 int 1752 nvme_transport_ctrlr_connect_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair) 1753 { 1754 g_connect_qpair_called = true; 1755 qpair->state = NVME_QPAIR_CONNECTED; 1756 return g_connect_qpair_return_code; 1757 } 1758 1759 static void 1760 test_spdk_nvme_ctrlr_reconnect_io_qpair(void) 1761 { 1762 struct spdk_nvme_ctrlr ctrlr = {}; 1763 struct spdk_nvme_qpair qpair = {}; 1764 int rc; 1765 1766 CU_ASSERT(pthread_mutex_init(&ctrlr.ctrlr_lock, NULL) == 0); 1767 1768 /* Various states of controller disconnect. */ 1769 qpair.id = 1; 1770 qpair.ctrlr = &ctrlr; 1771 ctrlr.is_removed = 1; 1772 ctrlr.is_failed = 0; 1773 ctrlr.is_resetting = 0; 1774 rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair); 1775 CU_ASSERT(rc == -ENODEV) 1776 1777 ctrlr.is_removed = 0; 1778 ctrlr.is_failed = 1; 1779 rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair); 1780 CU_ASSERT(rc == -ENXIO) 1781 1782 ctrlr.is_failed = 0; 1783 ctrlr.is_resetting = 1; 1784 rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair); 1785 CU_ASSERT(rc == -EAGAIN) 1786 1787 /* Confirm precedence for controller states: removed > resetting > failed */ 1788 ctrlr.is_removed = 1; 1789 ctrlr.is_failed = 1; 1790 rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair); 1791 CU_ASSERT(rc == -ENODEV) 1792 1793 ctrlr.is_removed = 0; 1794 rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair); 1795 CU_ASSERT(rc == -EAGAIN) 1796 1797 ctrlr.is_resetting = 0; 1798 rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair); 1799 CU_ASSERT(rc == -ENXIO) 1800 1801 /* qpair not failed. Make sure we don't call down to the transport */ 1802 ctrlr.is_failed = 0; 1803 qpair.state = NVME_QPAIR_CONNECTED; 1804 g_connect_qpair_called = false; 1805 rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair); 1806 CU_ASSERT(g_connect_qpair_called == false); 1807 CU_ASSERT(rc == 0) 1808 1809 /* transport qpair is failed. make sure we call down to the transport */ 1810 qpair.state = NVME_QPAIR_DISCONNECTED; 1811 rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair); 1812 CU_ASSERT(g_connect_qpair_called == true); 1813 CU_ASSERT(rc == 0) 1814 1815 CU_ASSERT(pthread_mutex_destroy(&ctrlr.ctrlr_lock) == 0); 1816 } 1817 1818 static void 1819 test_nvme_ctrlr_fail(void) 1820 { 1821 struct spdk_nvme_ctrlr ctrlr = {}; 1822 1823 ctrlr.opts.num_io_queues = 0; 1824 nvme_ctrlr_fail(&ctrlr, false); 1825 1826 CU_ASSERT(ctrlr.is_failed == true); 1827 } 1828 1829 static void 1830 test_nvme_ctrlr_construct_intel_support_log_page_list(void) 1831 { 1832 bool res; 1833 struct spdk_nvme_ctrlr ctrlr = {}; 1834 struct spdk_nvme_intel_log_page_directory payload = {}; 1835 struct spdk_pci_id pci_id = {}; 1836 1837 /* Get quirks for a device with all 0 vendor/device id */ 1838 ctrlr.quirks = nvme_get_quirks(&pci_id); 1839 CU_ASSERT(ctrlr.quirks == 0); 1840 1841 /* Set the vendor to Intel, but provide no device id */ 1842 pci_id.class_id = SPDK_PCI_CLASS_NVME; 1843 ctrlr.cdata.vid = pci_id.vendor_id = SPDK_PCI_VID_INTEL; 1844 payload.temperature_statistics_log_len = 1; 1845 ctrlr.quirks = nvme_get_quirks(&pci_id); 1846 memset(ctrlr.log_page_supported, 0, sizeof(ctrlr.log_page_supported)); 1847 1848 nvme_ctrlr_construct_intel_support_log_page_list(&ctrlr, &payload); 1849 res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY); 1850 CU_ASSERT(res == true); 1851 res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_TEMPERATURE); 1852 CU_ASSERT(res == true); 1853 res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY); 1854 CU_ASSERT(res == false); 1855 res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_SMART); 1856 CU_ASSERT(res == false); 1857 1858 /* set valid vendor id, device id and sub device id */ 1859 ctrlr.cdata.vid = SPDK_PCI_VID_INTEL; 1860 payload.temperature_statistics_log_len = 0; 1861 pci_id.vendor_id = SPDK_PCI_VID_INTEL; 1862 pci_id.device_id = 0x0953; 1863 pci_id.subvendor_id = SPDK_PCI_VID_INTEL; 1864 pci_id.subdevice_id = 0x3702; 1865 ctrlr.quirks = nvme_get_quirks(&pci_id); 1866 memset(ctrlr.log_page_supported, 0, sizeof(ctrlr.log_page_supported)); 1867 1868 nvme_ctrlr_construct_intel_support_log_page_list(&ctrlr, &payload); 1869 res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY); 1870 CU_ASSERT(res == true); 1871 res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_TEMPERATURE); 1872 CU_ASSERT(res == false); 1873 res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY); 1874 CU_ASSERT(res == true); 1875 res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_SMART); 1876 CU_ASSERT(res == false); 1877 } 1878 1879 static void 1880 test_nvme_ctrlr_set_supported_features(void) 1881 { 1882 bool res; 1883 struct spdk_nvme_ctrlr ctrlr = {}; 1884 1885 /* set a invalid vendor id */ 1886 ctrlr.cdata.vid = 0xFFFF; 1887 nvme_ctrlr_set_supported_features(&ctrlr); 1888 res = spdk_nvme_ctrlr_is_feature_supported(&ctrlr, SPDK_NVME_FEAT_ARBITRATION); 1889 CU_ASSERT(res == true); 1890 res = spdk_nvme_ctrlr_is_feature_supported(&ctrlr, SPDK_NVME_INTEL_FEAT_MAX_LBA); 1891 CU_ASSERT(res == false); 1892 1893 ctrlr.cdata.vid = SPDK_PCI_VID_INTEL; 1894 nvme_ctrlr_set_supported_features(&ctrlr); 1895 res = spdk_nvme_ctrlr_is_feature_supported(&ctrlr, SPDK_NVME_FEAT_ARBITRATION); 1896 CU_ASSERT(res == true); 1897 res = spdk_nvme_ctrlr_is_feature_supported(&ctrlr, SPDK_NVME_INTEL_FEAT_MAX_LBA); 1898 CU_ASSERT(res == true); 1899 } 1900 1901 static void 1902 test_ctrlr_get_default_ctrlr_opts(void) 1903 { 1904 struct spdk_nvme_ctrlr_opts opts = {}; 1905 1906 CU_ASSERT(spdk_uuid_parse(&g_spdk_nvme_driver->default_extended_host_id, 1907 "e53e9258-c93b-48b5-be1a-f025af6d232a") == 0); 1908 1909 memset(&opts, 0, sizeof(opts)); 1910 1911 /* set a smaller opts_size */ 1912 CU_ASSERT(sizeof(opts) > 8); 1913 spdk_nvme_ctrlr_get_default_ctrlr_opts(&opts, 8); 1914 CU_ASSERT_EQUAL(opts.num_io_queues, DEFAULT_MAX_IO_QUEUES); 1915 CU_ASSERT_FALSE(opts.use_cmb_sqs); 1916 /* check below fields are not initialized by default value */ 1917 CU_ASSERT_EQUAL(opts.arb_mechanism, 0); 1918 CU_ASSERT_EQUAL(opts.keep_alive_timeout_ms, 0); 1919 CU_ASSERT_EQUAL(opts.io_queue_size, 0); 1920 CU_ASSERT_EQUAL(opts.io_queue_requests, 0); 1921 for (int i = 0; i < 8; i++) { 1922 CU_ASSERT(opts.host_id[i] == 0); 1923 } 1924 for (int i = 0; i < 16; i++) { 1925 CU_ASSERT(opts.extended_host_id[i] == 0); 1926 } 1927 CU_ASSERT(strlen(opts.hostnqn) == 0); 1928 CU_ASSERT(strlen(opts.src_addr) == 0); 1929 CU_ASSERT(strlen(opts.src_svcid) == 0); 1930 CU_ASSERT_EQUAL(opts.admin_timeout_ms, 0); 1931 1932 /* set a consistent opts_size */ 1933 spdk_nvme_ctrlr_get_default_ctrlr_opts(&opts, sizeof(opts)); 1934 CU_ASSERT_EQUAL(opts.num_io_queues, DEFAULT_MAX_IO_QUEUES); 1935 CU_ASSERT_FALSE(opts.use_cmb_sqs); 1936 CU_ASSERT_EQUAL(opts.arb_mechanism, SPDK_NVME_CC_AMS_RR); 1937 CU_ASSERT_EQUAL(opts.keep_alive_timeout_ms, 10 * 1000); 1938 CU_ASSERT_EQUAL(opts.io_queue_size, DEFAULT_IO_QUEUE_SIZE); 1939 CU_ASSERT_EQUAL(opts.io_queue_requests, DEFAULT_IO_QUEUE_REQUESTS); 1940 for (int i = 0; i < 8; i++) { 1941 CU_ASSERT(opts.host_id[i] == 0); 1942 } 1943 CU_ASSERT_STRING_EQUAL(opts.hostnqn, 1944 "nqn.2014-08.org.nvmexpress:uuid:e53e9258-c93b-48b5-be1a-f025af6d232a"); 1945 CU_ASSERT(memcmp(opts.extended_host_id, &g_spdk_nvme_driver->default_extended_host_id, 1946 sizeof(opts.extended_host_id)) == 0); 1947 CU_ASSERT(strlen(opts.src_addr) == 0); 1948 CU_ASSERT(strlen(opts.src_svcid) == 0); 1949 CU_ASSERT_EQUAL(opts.admin_timeout_ms, NVME_MAX_ADMIN_TIMEOUT_IN_SECS * 1000); 1950 } 1951 1952 static void 1953 test_ctrlr_get_default_io_qpair_opts(void) 1954 { 1955 struct spdk_nvme_ctrlr ctrlr = {}; 1956 struct spdk_nvme_io_qpair_opts opts = {}; 1957 1958 memset(&opts, 0, sizeof(opts)); 1959 1960 /* set a smaller opts_size */ 1961 ctrlr.opts.io_queue_size = DEFAULT_IO_QUEUE_SIZE; 1962 CU_ASSERT(sizeof(opts) > 8); 1963 spdk_nvme_ctrlr_get_default_io_qpair_opts(&ctrlr, &opts, 8); 1964 CU_ASSERT_EQUAL(opts.qprio, SPDK_NVME_QPRIO_URGENT); 1965 CU_ASSERT_EQUAL(opts.io_queue_size, DEFAULT_IO_QUEUE_SIZE); 1966 /* check below field is not initialized by default value */ 1967 CU_ASSERT_EQUAL(opts.io_queue_requests, 0); 1968 1969 /* set a consistent opts_size */ 1970 ctrlr.opts.io_queue_size = DEFAULT_IO_QUEUE_SIZE; 1971 ctrlr.opts.io_queue_requests = DEFAULT_IO_QUEUE_REQUESTS; 1972 spdk_nvme_ctrlr_get_default_io_qpair_opts(&ctrlr, &opts, sizeof(opts)); 1973 CU_ASSERT_EQUAL(opts.qprio, SPDK_NVME_QPRIO_URGENT); 1974 CU_ASSERT_EQUAL(opts.io_queue_size, DEFAULT_IO_QUEUE_SIZE); 1975 CU_ASSERT_EQUAL(opts.io_queue_requests, DEFAULT_IO_QUEUE_REQUESTS); 1976 } 1977 1978 #if 0 /* TODO: move to PCIe-specific unit test */ 1979 static void 1980 test_nvme_ctrlr_alloc_cmb(void) 1981 { 1982 int rc; 1983 uint64_t offset; 1984 struct spdk_nvme_ctrlr ctrlr = {}; 1985 1986 ctrlr.cmb_size = 0x1000000; 1987 ctrlr.cmb_current_offset = 0x100; 1988 rc = nvme_ctrlr_alloc_cmb(&ctrlr, 0x200, 0x1000, &offset); 1989 CU_ASSERT(rc == 0); 1990 CU_ASSERT(offset == 0x1000); 1991 CU_ASSERT(ctrlr.cmb_current_offset == 0x1200); 1992 1993 rc = nvme_ctrlr_alloc_cmb(&ctrlr, 0x800, 0x1000, &offset); 1994 CU_ASSERT(rc == 0); 1995 CU_ASSERT(offset == 0x2000); 1996 CU_ASSERT(ctrlr.cmb_current_offset == 0x2800); 1997 1998 rc = nvme_ctrlr_alloc_cmb(&ctrlr, 0x800000, 0x100000, &offset); 1999 CU_ASSERT(rc == 0); 2000 CU_ASSERT(offset == 0x100000); 2001 CU_ASSERT(ctrlr.cmb_current_offset == 0x900000); 2002 2003 rc = nvme_ctrlr_alloc_cmb(&ctrlr, 0x8000000, 0x1000, &offset); 2004 CU_ASSERT(rc == -1); 2005 } 2006 #endif 2007 2008 static void 2009 test_spdk_nvme_ctrlr_update_firmware(void) 2010 { 2011 struct spdk_nvme_ctrlr ctrlr = {}; 2012 void *payload = NULL; 2013 int point_payload = 1; 2014 int slot = 0; 2015 int ret = 0; 2016 struct spdk_nvme_status status; 2017 enum spdk_nvme_fw_commit_action commit_action = SPDK_NVME_FW_COMMIT_REPLACE_IMG; 2018 2019 CU_ASSERT(pthread_mutex_init(&ctrlr.ctrlr_lock, NULL) == 0); 2020 2021 /* Set invalid size check function return value */ 2022 set_size = 5; 2023 ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status); 2024 CU_ASSERT(ret == -1); 2025 2026 /* When payload is NULL but set_size < min_page_size */ 2027 set_size = 4; 2028 ctrlr.min_page_size = 5; 2029 ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status); 2030 CU_ASSERT(ret == -1); 2031 2032 /* When payload not NULL but min_page_size is 0 */ 2033 set_size = 4; 2034 ctrlr.min_page_size = 0; 2035 payload = &point_payload; 2036 ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status); 2037 CU_ASSERT(ret == -1); 2038 2039 /* Check firmware image download when payload not NULL and min_page_size not 0 , status.cpl value is 1 */ 2040 set_status_cpl = 1; 2041 set_size = 4; 2042 ctrlr.min_page_size = 5; 2043 payload = &point_payload; 2044 ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status); 2045 CU_ASSERT(ret == -ENXIO); 2046 2047 /* Check firmware image download and set status.cpl value is 0 */ 2048 set_status_cpl = 0; 2049 set_size = 4; 2050 ctrlr.min_page_size = 5; 2051 payload = &point_payload; 2052 ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status); 2053 CU_ASSERT(ret == -1); 2054 2055 /* Check firmware commit */ 2056 ctrlr.is_resetting = false; 2057 set_status_cpl = 0; 2058 slot = 1; 2059 set_size = 4; 2060 ctrlr.min_page_size = 5; 2061 payload = &point_payload; 2062 ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status); 2063 CU_ASSERT(ret == -ENXIO); 2064 2065 /* Set size check firmware download and firmware commit */ 2066 ctrlr.is_resetting = true; 2067 set_status_cpl = 0; 2068 slot = 1; 2069 set_size = 4; 2070 ctrlr.min_page_size = 5; 2071 payload = &point_payload; 2072 ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status); 2073 CU_ASSERT(ret == 0); 2074 2075 /* nvme_wait_for_completion returns an error */ 2076 g_wait_for_completion_return_val = -1; 2077 ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status); 2078 CU_ASSERT(ret == -ENXIO); 2079 CU_ASSERT(g_failed_status != NULL); 2080 CU_ASSERT(g_failed_status->timed_out == true); 2081 /* status should be freed by callback, which is not triggered in test env. 2082 Store status to global variable and free it manually. 2083 If spdk_nvme_ctrlr_update_firmware changes its behaviour and frees the status 2084 itself, we'll get a double free here.. */ 2085 free(g_failed_status); 2086 g_failed_status = NULL; 2087 g_wait_for_completion_return_val = 0; 2088 2089 CU_ASSERT(pthread_mutex_destroy(&ctrlr.ctrlr_lock) == 0); 2090 set_status_cpl = 0; 2091 } 2092 2093 int 2094 nvme_ctrlr_cmd_doorbell_buffer_config(struct spdk_nvme_ctrlr *ctrlr, uint64_t prp1, uint64_t prp2, 2095 spdk_nvme_cmd_cb cb_fn, void *cb_arg) 2096 { 2097 fake_cpl_sc(cb_fn, cb_arg); 2098 return 0; 2099 } 2100 2101 static void 2102 test_spdk_nvme_ctrlr_doorbell_buffer_config(void) 2103 { 2104 struct spdk_nvme_ctrlr ctrlr = {}; 2105 int ret = -1; 2106 2107 ctrlr.cdata.oacs.doorbell_buffer_config = 1; 2108 ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_PCIE; 2109 ctrlr.page_size = 0x1000; 2110 MOCK_CLEAR(spdk_malloc); 2111 MOCK_CLEAR(spdk_zmalloc); 2112 ret = nvme_ctrlr_set_doorbell_buffer_config(&ctrlr); 2113 CU_ASSERT(ret == 0); 2114 nvme_ctrlr_free_doorbell_buffer(&ctrlr); 2115 } 2116 2117 static void 2118 test_nvme_ctrlr_test_active_ns(void) 2119 { 2120 uint32_t nsid, minor; 2121 size_t ns_id_count; 2122 struct spdk_nvme_ctrlr ctrlr = {}; 2123 uint32_t active_ns_list[1531]; 2124 2125 for (nsid = 1; nsid <= 1531; nsid++) { 2126 active_ns_list[nsid - 1] = nsid; 2127 } 2128 2129 g_active_ns_list = active_ns_list; 2130 2131 ctrlr.page_size = 0x1000; 2132 2133 for (minor = 0; minor <= 2; minor++) { 2134 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2135 ctrlr.state = NVME_CTRLR_STATE_READY; 2136 2137 ctrlr.vs.bits.mjr = 1; 2138 ctrlr.vs.bits.mnr = minor; 2139 ctrlr.vs.bits.ter = 0; 2140 ctrlr.cdata.nn = 1531; 2141 2142 RB_INIT(&ctrlr.ns); 2143 2144 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list); 2145 nvme_ctrlr_identify_active_ns(&ctrlr); 2146 2147 for (nsid = 1; nsid <= ctrlr.cdata.nn; nsid++) { 2148 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, nsid) == true); 2149 } 2150 2151 for (; nsid <= 1559; nsid++) { 2152 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, nsid) == false); 2153 } 2154 2155 g_active_ns_list_length = 0; 2156 if (minor <= 1) { 2157 ctrlr.cdata.nn = 0; 2158 } 2159 nvme_ctrlr_identify_active_ns(&ctrlr); 2160 CU_ASSERT(spdk_nvme_ctrlr_get_first_active_ns(&ctrlr) == 0); 2161 2162 g_active_ns_list_length = 1; 2163 if (minor <= 1) { 2164 ctrlr.cdata.nn = 1; 2165 } 2166 nvme_ctrlr_identify_active_ns(&ctrlr); 2167 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1) == true); 2168 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 2) == false); 2169 nsid = spdk_nvme_ctrlr_get_first_active_ns(&ctrlr); 2170 CU_ASSERT(nsid == 1); 2171 2172 if (minor >= 2) { 2173 /* For NVMe 1.2 and newer, the namespace list can have "holes" where 2174 * some namespaces are not active. Test this. */ 2175 g_active_ns_list_length = 2; 2176 g_active_ns_list[1] = 3; 2177 nvme_ctrlr_identify_active_ns(&ctrlr); 2178 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1) == true); 2179 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 2) == false); 2180 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 3) == true); 2181 nsid = spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, nsid); 2182 CU_ASSERT(nsid == 3); 2183 nsid = spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, nsid); 2184 CU_ASSERT(nsid == 0); 2185 2186 /* Reset the active namespace list array */ 2187 g_active_ns_list[1] = 2; 2188 } 2189 2190 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list); 2191 if (minor <= 1) { 2192 ctrlr.cdata.nn = 1531; 2193 } 2194 nvme_ctrlr_identify_active_ns(&ctrlr); 2195 2196 ns_id_count = 0; 2197 for (nsid = spdk_nvme_ctrlr_get_first_active_ns(&ctrlr); 2198 nsid != 0; nsid = spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, nsid)) { 2199 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, nsid) == true); 2200 ns_id_count++; 2201 } 2202 CU_ASSERT(ns_id_count == ctrlr.cdata.nn); 2203 2204 nvme_ctrlr_destruct(&ctrlr); 2205 } 2206 2207 g_active_ns_list = NULL; 2208 g_active_ns_list_length = 0; 2209 } 2210 2211 static void 2212 test_nvme_ctrlr_test_active_ns_error_case(void) 2213 { 2214 int rc; 2215 struct spdk_nvme_ctrlr ctrlr = {.state = NVME_CTRLR_STATE_READY}; 2216 2217 ctrlr.page_size = 0x1000; 2218 ctrlr.vs.bits.mjr = 1; 2219 ctrlr.vs.bits.mnr = 2; 2220 ctrlr.vs.bits.ter = 0; 2221 ctrlr.cdata.nn = 2; 2222 2223 set_status_code = SPDK_NVME_SC_INVALID_FIELD; 2224 rc = nvme_ctrlr_identify_active_ns(&ctrlr); 2225 CU_ASSERT(rc == -ENXIO); 2226 set_status_code = SPDK_NVME_SC_SUCCESS; 2227 } 2228 2229 static void 2230 test_nvme_ctrlr_init_delay(void) 2231 { 2232 DECLARE_AND_CONSTRUCT_CTRLR(); 2233 2234 memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs)); 2235 2236 /* 2237 * Initial state: CC.EN = 0, CSTS.RDY = 0 2238 * init() should set CC.EN = 1. 2239 */ 2240 g_ut_nvme_regs.cc.bits.en = 0; 2241 g_ut_nvme_regs.csts.bits.rdy = 0; 2242 2243 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2244 /* Test that the initialization delay works correctly. We only 2245 * do the initialization delay on SSDs that require it, so 2246 * set that quirk here. 2247 */ 2248 ctrlr.quirks = NVME_QUIRK_DELAY_BEFORE_INIT; 2249 ctrlr.cdata.nn = 1; 2250 ctrlr.page_size = 0x1000; 2251 ctrlr.state = NVME_CTRLR_STATE_INIT_DELAY; 2252 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2253 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 2254 CU_ASSERT(ctrlr.sleep_timeout_tsc != 0); 2255 2256 /* delay 1s, just return as sleep time isn't enough */ 2257 spdk_delay_us(1 * spdk_get_ticks_hz()); 2258 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2259 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 2260 CU_ASSERT(ctrlr.sleep_timeout_tsc != 0); 2261 2262 /* sleep timeout, start to initialize */ 2263 spdk_delay_us(2 * spdk_get_ticks_hz()); 2264 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 2265 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2266 } 2267 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2268 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 2269 2270 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2271 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 2272 2273 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2274 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 2275 2276 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2277 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 2278 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 2279 2280 /* 2281 * Transition to CSTS.RDY = 1. 2282 */ 2283 g_ut_nvme_regs.csts.bits.rdy = 1; 2284 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2285 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE); 2286 2287 /* 2288 * Transition to READY. 2289 */ 2290 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 2291 nvme_ctrlr_process_init(&ctrlr); 2292 } 2293 2294 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 2295 nvme_ctrlr_destruct(&ctrlr); 2296 } 2297 2298 static void 2299 test_spdk_nvme_ctrlr_set_trid(void) 2300 { 2301 struct spdk_nvme_ctrlr ctrlr = {{0}}; 2302 struct spdk_nvme_transport_id new_trid = {{0}}; 2303 2304 CU_ASSERT(pthread_mutex_init(&ctrlr.ctrlr_lock, NULL) == 0); 2305 2306 ctrlr.is_failed = false; 2307 ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_RDMA; 2308 snprintf(ctrlr.trid.subnqn, SPDK_NVMF_NQN_MAX_LEN, "%s", "nqn.2016-06.io.spdk:cnode1"); 2309 snprintf(ctrlr.trid.traddr, SPDK_NVMF_TRADDR_MAX_LEN, "%s", "192.168.100.8"); 2310 snprintf(ctrlr.trid.trsvcid, SPDK_NVMF_TRSVCID_MAX_LEN, "%s", "4420"); 2311 CU_ASSERT(spdk_nvme_ctrlr_set_trid(&ctrlr, &new_trid) == -EPERM); 2312 2313 ctrlr.is_failed = true; 2314 new_trid.trtype = SPDK_NVME_TRANSPORT_TCP; 2315 CU_ASSERT(spdk_nvme_ctrlr_set_trid(&ctrlr, &new_trid) == -EINVAL); 2316 CU_ASSERT(ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_RDMA); 2317 2318 new_trid.trtype = SPDK_NVME_TRANSPORT_RDMA; 2319 snprintf(new_trid.subnqn, SPDK_NVMF_NQN_MAX_LEN, "%s", "nqn.2016-06.io.spdk:cnode2"); 2320 CU_ASSERT(spdk_nvme_ctrlr_set_trid(&ctrlr, &new_trid) == -EINVAL); 2321 CU_ASSERT(strncmp(ctrlr.trid.subnqn, "nqn.2016-06.io.spdk:cnode1", SPDK_NVMF_NQN_MAX_LEN) == 0); 2322 2323 2324 snprintf(new_trid.subnqn, SPDK_NVMF_NQN_MAX_LEN, "%s", "nqn.2016-06.io.spdk:cnode1"); 2325 snprintf(new_trid.traddr, SPDK_NVMF_TRADDR_MAX_LEN, "%s", "192.168.100.9"); 2326 snprintf(new_trid.trsvcid, SPDK_NVMF_TRSVCID_MAX_LEN, "%s", "4421"); 2327 CU_ASSERT(spdk_nvme_ctrlr_set_trid(&ctrlr, &new_trid) == 0); 2328 CU_ASSERT(strncmp(ctrlr.trid.traddr, "192.168.100.9", SPDK_NVMF_TRADDR_MAX_LEN) == 0); 2329 CU_ASSERT(strncmp(ctrlr.trid.trsvcid, "4421", SPDK_NVMF_TRSVCID_MAX_LEN) == 0); 2330 2331 CU_ASSERT(pthread_mutex_destroy(&ctrlr.ctrlr_lock) == 0); 2332 } 2333 2334 static void 2335 test_nvme_ctrlr_init_set_nvmf_ioccsz(void) 2336 { 2337 struct spdk_nvme_ctrlr_data cdata = {}; 2338 DECLARE_AND_CONSTRUCT_CTRLR(); 2339 /* equivalent of 4096 bytes */ 2340 cdata.nvmf_specific.ioccsz = 260; 2341 cdata.nvmf_specific.icdoff = 1; 2342 g_cdata = &cdata; 2343 2344 /* Check PCI trtype, */ 2345 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2346 ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_PCIE; 2347 2348 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY; 2349 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2350 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER); 2351 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2352 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT); 2353 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2354 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC); 2355 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2356 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES); 2357 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2358 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS); 2359 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2360 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS); 2361 2362 CU_ASSERT(ctrlr.ioccsz_bytes == 0); 2363 CU_ASSERT(ctrlr.icdoff == 0); 2364 2365 nvme_ctrlr_destruct(&ctrlr); 2366 2367 /* Check RDMA trtype, */ 2368 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2369 ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_RDMA; 2370 2371 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY; 2372 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2373 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER); 2374 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2375 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT); 2376 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2377 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC); 2378 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2379 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES); 2380 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2381 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS); 2382 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2383 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS); 2384 2385 CU_ASSERT(ctrlr.ioccsz_bytes == 4096); 2386 CU_ASSERT(ctrlr.icdoff == 1); 2387 ctrlr.ioccsz_bytes = 0; 2388 ctrlr.icdoff = 0; 2389 2390 nvme_ctrlr_destruct(&ctrlr); 2391 2392 /* Check TCP trtype, */ 2393 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2394 ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_TCP; 2395 2396 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY; 2397 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2398 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER); 2399 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2400 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT); 2401 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2402 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC); 2403 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2404 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES); 2405 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2406 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS); 2407 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2408 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS); 2409 2410 CU_ASSERT(ctrlr.ioccsz_bytes == 4096); 2411 CU_ASSERT(ctrlr.icdoff == 1); 2412 ctrlr.ioccsz_bytes = 0; 2413 ctrlr.icdoff = 0; 2414 2415 nvme_ctrlr_destruct(&ctrlr); 2416 2417 /* Check FC trtype, */ 2418 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2419 ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_FC; 2420 2421 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY; 2422 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2423 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER); 2424 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2425 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT); 2426 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2427 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC); 2428 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2429 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES); 2430 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2431 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS); 2432 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2433 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS); 2434 2435 CU_ASSERT(ctrlr.ioccsz_bytes == 4096); 2436 CU_ASSERT(ctrlr.icdoff == 1); 2437 ctrlr.ioccsz_bytes = 0; 2438 ctrlr.icdoff = 0; 2439 2440 nvme_ctrlr_destruct(&ctrlr); 2441 2442 /* Check CUSTOM trtype, */ 2443 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2444 ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_CUSTOM; 2445 2446 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY; 2447 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2448 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER); 2449 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2450 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT); 2451 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2452 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC); 2453 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2454 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES); 2455 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2456 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS); 2457 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2458 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS); 2459 2460 CU_ASSERT(ctrlr.ioccsz_bytes == 0); 2461 CU_ASSERT(ctrlr.icdoff == 0); 2462 2463 nvme_ctrlr_destruct(&ctrlr); 2464 2465 g_cdata = NULL; 2466 } 2467 2468 static void 2469 test_nvme_ctrlr_init_set_num_queues(void) 2470 { 2471 DECLARE_AND_CONSTRUCT_CTRLR(); 2472 2473 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2474 2475 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY; 2476 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2477 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER); 2478 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2479 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT); 2480 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2481 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC); 2482 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2483 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES); 2484 2485 ctrlr.opts.num_io_queues = 64; 2486 /* Num queues is zero-based. So, use 31 to get 32 queues */ 2487 fake_cpl.cdw0 = 31 + (31 << 16); 2488 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); /* -> IDENTIFY_ACTIVE_NS */ 2489 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS); 2490 CU_ASSERT(ctrlr.opts.num_io_queues == 32); 2491 fake_cpl.cdw0 = 0; 2492 2493 nvme_ctrlr_destruct(&ctrlr); 2494 } 2495 2496 static void 2497 test_nvme_ctrlr_init_set_keep_alive_timeout(void) 2498 { 2499 DECLARE_AND_CONSTRUCT_CTRLR(); 2500 2501 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2502 2503 ctrlr.opts.keep_alive_timeout_ms = 60000; 2504 ctrlr.cdata.kas = 1; 2505 ctrlr.state = NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT; 2506 fake_cpl.cdw0 = 120000; 2507 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); /* -> IDENTIFY_IOCS_SPECIFIC */ 2508 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC); 2509 CU_ASSERT(ctrlr.opts.keep_alive_timeout_ms == 120000); 2510 fake_cpl.cdw0 = 0; 2511 2512 /* Target does not support Get Feature "Keep Alive Timer" */ 2513 ctrlr.opts.keep_alive_timeout_ms = 60000; 2514 ctrlr.cdata.kas = 1; 2515 ctrlr.state = NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT; 2516 set_status_code = SPDK_NVME_SC_INVALID_FIELD; 2517 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); /* -> IDENTIFY_IOCS_SPECIFIC */ 2518 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC); 2519 CU_ASSERT(ctrlr.opts.keep_alive_timeout_ms == 60000); 2520 set_status_code = SPDK_NVME_SC_SUCCESS; 2521 2522 /* Target fails Get Feature "Keep Alive Timer" for another reason */ 2523 ctrlr.opts.keep_alive_timeout_ms = 60000; 2524 ctrlr.cdata.kas = 1; 2525 ctrlr.state = NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT; 2526 set_status_code = SPDK_NVME_SC_INTERNAL_DEVICE_ERROR; 2527 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); /* -> ERROR */ 2528 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ERROR); 2529 set_status_code = SPDK_NVME_SC_SUCCESS; 2530 2531 nvme_ctrlr_destruct(&ctrlr); 2532 } 2533 2534 static void 2535 test_alloc_io_qpair_fail(void) 2536 { 2537 struct spdk_nvme_ctrlr ctrlr = {}; 2538 struct spdk_nvme_qpair *q0; 2539 2540 setup_qpairs(&ctrlr, 1); 2541 2542 /* Modify the connect_qpair return code to inject a failure */ 2543 g_connect_qpair_return_code = 1; 2544 2545 /* Attempt to allocate a qpair, this should fail */ 2546 q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, NULL, 0); 2547 SPDK_CU_ASSERT_FATAL(q0 == NULL); 2548 2549 /* Verify that the qpair is removed from the lists */ 2550 SPDK_CU_ASSERT_FATAL(TAILQ_EMPTY(&ctrlr.active_io_qpairs)); 2551 2552 g_connect_qpair_return_code = 0; 2553 cleanup_qpairs(&ctrlr); 2554 } 2555 2556 static void 2557 test_nvme_ctrlr_add_remove_process(void) 2558 { 2559 struct spdk_nvme_ctrlr ctrlr = {}; 2560 void *devhandle = (void *)0xDEADBEEF; 2561 struct spdk_nvme_ctrlr_process *proc = NULL; 2562 int rc; 2563 2564 ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_PCIE; 2565 TAILQ_INIT(&ctrlr.active_procs); 2566 2567 rc = nvme_ctrlr_add_process(&ctrlr, devhandle); 2568 CU_ASSERT(rc == 0); 2569 proc = TAILQ_FIRST(&ctrlr.active_procs); 2570 SPDK_CU_ASSERT_FATAL(proc != NULL); 2571 CU_ASSERT(proc->is_primary == true); 2572 CU_ASSERT(proc->pid == getpid()); 2573 CU_ASSERT(proc->devhandle == (void *)0xDEADBEEF); 2574 CU_ASSERT(proc->ref == 0); 2575 2576 nvme_ctrlr_remove_process(&ctrlr, proc); 2577 CU_ASSERT(TAILQ_EMPTY(&ctrlr.active_procs)); 2578 } 2579 2580 static void 2581 test_nvme_ctrlr_set_arbitration_feature(void) 2582 { 2583 struct spdk_nvme_ctrlr ctrlr = {}; 2584 2585 ctrlr.opts.arbitration_burst = 6; 2586 ctrlr.flags |= SPDK_NVME_CTRLR_WRR_SUPPORTED; 2587 ctrlr.opts.low_priority_weight = 1; 2588 ctrlr.opts.medium_priority_weight = 2; 2589 ctrlr.opts.high_priority_weight = 3; 2590 /* g_ut_cdw11 used to record value command feature set. */ 2591 g_ut_cdw11 = 0; 2592 2593 /* arbitration_burst count available. */ 2594 nvme_ctrlr_set_arbitration_feature(&ctrlr); 2595 CU_ASSERT((uint8_t)g_ut_cdw11 == 6); 2596 CU_ASSERT((uint8_t)(g_ut_cdw11 >> 8) == 1); 2597 CU_ASSERT((uint8_t)(g_ut_cdw11 >> 16) == 2); 2598 CU_ASSERT((uint8_t)(g_ut_cdw11 >> 24) == 3); 2599 2600 /* arbitration_burst unavailable. */ 2601 g_ut_cdw11 = 0; 2602 ctrlr.opts.arbitration_burst = 8; 2603 2604 nvme_ctrlr_set_arbitration_feature(&ctrlr); 2605 CU_ASSERT(g_ut_cdw11 == 0); 2606 } 2607 2608 static void 2609 test_nvme_ctrlr_set_state(void) 2610 { 2611 struct spdk_nvme_ctrlr ctrlr = {}; 2612 MOCK_SET(spdk_get_ticks, 0); 2613 2614 nvme_ctrlr_set_state(&ctrlr, NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT, 1000); 2615 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT); 2616 CU_ASSERT(ctrlr.state_timeout_tsc == 1000000); 2617 2618 nvme_ctrlr_set_state(&ctrlr, NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT, 0); 2619 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT); 2620 CU_ASSERT(ctrlr.state_timeout_tsc == NVME_TIMEOUT_INFINITE); 2621 2622 /* Time out ticks causes integer overflow. */ 2623 MOCK_SET(spdk_get_ticks, UINT64_MAX); 2624 2625 nvme_ctrlr_set_state(&ctrlr, NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT, 1000); 2626 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT); 2627 CU_ASSERT(ctrlr.state_timeout_tsc == NVME_TIMEOUT_INFINITE); 2628 MOCK_CLEAR(spdk_get_ticks); 2629 } 2630 2631 static void 2632 test_nvme_ctrlr_active_ns_list_v0(void) 2633 { 2634 DECLARE_AND_CONSTRUCT_CTRLR(); 2635 2636 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2637 2638 ctrlr.vs.bits.mjr = 1; 2639 ctrlr.vs.bits.mnr = 0; 2640 ctrlr.vs.bits.ter = 0; 2641 ctrlr.cdata.nn = 1024; 2642 2643 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS; 2644 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0); 2645 SPDK_CU_ASSERT_FATAL(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS); 2646 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1)); 2647 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1024)); 2648 CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1025)); 2649 CU_ASSERT(spdk_nvme_ctrlr_get_first_active_ns(&ctrlr) == 1); 2650 CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1023) == 1024); 2651 CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1024) == 0); 2652 CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1025) == 0); 2653 2654 nvme_ctrlr_destruct(&ctrlr); 2655 } 2656 2657 static void 2658 test_nvme_ctrlr_active_ns_list_v2(void) 2659 { 2660 uint32_t i; 2661 uint32_t active_ns_list[1024]; 2662 DECLARE_AND_CONSTRUCT_CTRLR(); 2663 2664 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2665 2666 ctrlr.vs.bits.mjr = 1; 2667 ctrlr.vs.bits.mnr = 2; 2668 ctrlr.vs.bits.ter = 0; 2669 ctrlr.cdata.nn = 4096; 2670 2671 g_active_ns_list = active_ns_list; 2672 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list); 2673 2674 /* No active namespaces */ 2675 memset(active_ns_list, 0, sizeof(active_ns_list)); 2676 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS; 2677 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0); 2678 SPDK_CU_ASSERT_FATAL(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS); 2679 CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1)); 2680 CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1024)); 2681 CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1025)); 2682 CU_ASSERT(spdk_nvme_ctrlr_get_first_active_ns(&ctrlr) == 0); 2683 CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1024) == 0); 2684 2685 nvme_ctrlr_destruct(&ctrlr); 2686 2687 /* 1024 active namespaces - one full page */ 2688 memset(active_ns_list, 0, sizeof(active_ns_list)); 2689 for (i = 0; i < 1024; ++i) { 2690 active_ns_list[i] = i + 1; 2691 } 2692 2693 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2694 2695 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS; 2696 g_active_ns_list = active_ns_list; 2697 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list); 2698 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0); 2699 SPDK_CU_ASSERT_FATAL(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS); 2700 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1)); 2701 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1024)); 2702 CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1025)); 2703 CU_ASSERT(spdk_nvme_ctrlr_get_first_active_ns(&ctrlr) == 1); 2704 CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1023) == 1024); 2705 CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1024) == 0); 2706 CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1025) == 0); 2707 2708 nvme_ctrlr_destruct(&ctrlr); 2709 2710 /* 1023 active namespaces - full page minus one */ 2711 memset(active_ns_list, 0, sizeof(active_ns_list)); 2712 for (i = 0; i < 1023; ++i) { 2713 active_ns_list[i] = i + 1; 2714 } 2715 2716 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2717 2718 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS; 2719 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0); 2720 SPDK_CU_ASSERT_FATAL(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS); 2721 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1)); 2722 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1023)); 2723 CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1024)); 2724 CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1025)); 2725 CU_ASSERT(spdk_nvme_ctrlr_get_first_active_ns(&ctrlr) == 1); 2726 CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1023) == 0); 2727 CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1024) == 0); 2728 CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1025) == 0); 2729 2730 nvme_ctrlr_destruct(&ctrlr); 2731 2732 g_active_ns_list = NULL; 2733 g_active_ns_list_length = 0; 2734 } 2735 2736 static void 2737 test_nvme_ctrlr_ns_mgmt(void) 2738 { 2739 DECLARE_AND_CONSTRUCT_CTRLR(); 2740 uint32_t active_ns_list[] = { 1, 2, 100, 1024 }; 2741 uint32_t active_ns_list2[] = { 1, 2, 3, 100, 1024 }; 2742 struct spdk_nvme_ns_data nsdata = {}; 2743 struct spdk_nvme_ctrlr_list ctrlr_list = {}; 2744 uint32_t nsid; 2745 2746 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2747 2748 ctrlr.vs.bits.mjr = 1; 2749 ctrlr.vs.bits.mnr = 2; 2750 ctrlr.vs.bits.ter = 0; 2751 ctrlr.cdata.nn = 4096; 2752 2753 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS; 2754 g_active_ns_list = active_ns_list; 2755 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list); 2756 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 2757 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0); 2758 } 2759 2760 fake_cpl.cdw0 = 3; 2761 nsid = spdk_nvme_ctrlr_create_ns(&ctrlr, &nsdata); 2762 fake_cpl.cdw0 = 0; 2763 CU_ASSERT(nsid == 3); 2764 CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 3)); 2765 CU_ASSERT(spdk_nvme_ctrlr_get_ns(&ctrlr, 3) != NULL); 2766 2767 g_active_ns_list = active_ns_list2; 2768 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list2); 2769 CU_ASSERT(spdk_nvme_ctrlr_attach_ns(&ctrlr, 3, &ctrlr_list) == 0); 2770 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 3)); 2771 CU_ASSERT(spdk_nvme_ctrlr_get_ns(&ctrlr, 3) != NULL); 2772 2773 g_active_ns_list = active_ns_list; 2774 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list); 2775 CU_ASSERT(spdk_nvme_ctrlr_detach_ns(&ctrlr, 3, &ctrlr_list) == 0); 2776 CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 3)); 2777 CU_ASSERT(spdk_nvme_ctrlr_get_ns(&ctrlr, 3) != NULL); 2778 2779 CU_ASSERT(spdk_nvme_ctrlr_delete_ns(&ctrlr, 3) == 0); 2780 CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 3)); 2781 CU_ASSERT(spdk_nvme_ctrlr_get_ns(&ctrlr, 3) != NULL); 2782 g_active_ns_list = NULL; 2783 g_active_ns_list_length = 0; 2784 2785 nvme_ctrlr_destruct(&ctrlr); 2786 } 2787 2788 static void 2789 check_en_set_rdy(void) 2790 { 2791 if (g_ut_nvme_regs.cc.bits.en == 1) { 2792 g_ut_nvme_regs.csts.bits.rdy = 1; 2793 } 2794 } 2795 2796 static void 2797 test_nvme_ctrlr_reset(void) 2798 { 2799 DECLARE_AND_CONSTRUCT_CTRLR(); 2800 struct spdk_nvme_ctrlr_data cdata = { .nn = 4096 }; 2801 uint32_t active_ns_list[] = { 1, 2, 100, 1024 }; 2802 uint32_t active_ns_list2[] = { 1, 100, 1024 }; 2803 2804 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2805 2806 g_ut_nvme_regs.vs.bits.mjr = 1; 2807 g_ut_nvme_regs.vs.bits.mnr = 2; 2808 g_ut_nvme_regs.vs.bits.ter = 0; 2809 nvme_ctrlr_get_vs(&ctrlr, &ctrlr.vs); 2810 ctrlr.cdata.nn = 2048; 2811 2812 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS; 2813 g_active_ns_list = active_ns_list; 2814 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list); 2815 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 2816 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0); 2817 } 2818 CU_ASSERT(spdk_nvme_ctrlr_get_num_ns(&ctrlr) == 2048); 2819 CU_ASSERT(spdk_nvme_ctrlr_get_ns(&ctrlr, 2) != NULL); 2820 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 2)); 2821 2822 /* Reset controller with changed number of namespaces */ 2823 g_cdata = &cdata; 2824 g_active_ns_list = active_ns_list2; 2825 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list2); 2826 STAILQ_INSERT_HEAD(&adminq.free_req, &req, stailq); 2827 g_ut_nvme_regs.cc.raw = 0; 2828 g_ut_nvme_regs.csts.raw = 0; 2829 g_set_reg_cb = check_en_set_rdy; 2830 g_wait_for_completion_return_val = -ENXIO; 2831 CU_ASSERT(spdk_nvme_ctrlr_reset(&ctrlr) == 0); 2832 g_set_reg_cb = NULL; 2833 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_READY); 2834 g_cdata = NULL; 2835 g_active_ns_list = NULL; 2836 g_active_ns_list_length = 0; 2837 2838 CU_ASSERT(spdk_nvme_ctrlr_get_num_ns(&ctrlr) == 4096); 2839 CU_ASSERT(spdk_nvme_ctrlr_get_ns(&ctrlr, 2) != NULL); 2840 CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 2)); 2841 2842 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 2843 nvme_ctrlr_destruct(&ctrlr); 2844 2845 g_wait_for_completion_return_val = 0; 2846 } 2847 2848 static uint32_t g_aer_cb_counter; 2849 2850 static void 2851 aer_cb(void *aer_cb_arg, const struct spdk_nvme_cpl *cpl) 2852 { 2853 g_aer_cb_counter++; 2854 } 2855 2856 static void 2857 test_nvme_ctrlr_aer_callback(void) 2858 { 2859 DECLARE_AND_CONSTRUCT_CTRLR(); 2860 uint32_t active_ns_list[] = { 1, 2, 100, 1024 }; 2861 union spdk_nvme_async_event_completion aer_event = { 2862 .bits.async_event_type = SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE, 2863 .bits.async_event_info = SPDK_NVME_ASYNC_EVENT_NS_ATTR_CHANGED 2864 }; 2865 struct spdk_nvme_cpl aer_cpl = { 2866 .status.sct = SPDK_NVME_SCT_GENERIC, 2867 .status.sc = SPDK_NVME_SC_SUCCESS, 2868 .cdw0 = aer_event.raw 2869 }; 2870 2871 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2872 2873 ctrlr.vs.bits.mjr = 1; 2874 ctrlr.vs.bits.mnr = 2; 2875 ctrlr.vs.bits.ter = 0; 2876 ctrlr.cdata.nn = 4096; 2877 2878 ctrlr.state = NVME_CTRLR_STATE_CONFIGURE_AER; 2879 g_active_ns_list = active_ns_list; 2880 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list); 2881 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 2882 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0); 2883 } 2884 2885 CU_ASSERT(nvme_ctrlr_add_process(&ctrlr, NULL) == 0); 2886 spdk_nvme_ctrlr_register_aer_callback(&ctrlr, aer_cb, NULL); 2887 2888 /* Async event */ 2889 g_aer_cb_counter = 0; 2890 nvme_ctrlr_async_event_cb(&ctrlr.aer[0], &aer_cpl); 2891 nvme_ctrlr_complete_queued_async_events(&ctrlr); 2892 CU_ASSERT(g_aer_cb_counter == 1); 2893 g_active_ns_list = NULL; 2894 g_active_ns_list_length = 0; 2895 2896 nvme_ctrlr_free_processes(&ctrlr); 2897 nvme_ctrlr_destruct(&ctrlr); 2898 } 2899 2900 static void 2901 test_nvme_ctrlr_ns_attr_changed(void) 2902 { 2903 DECLARE_AND_CONSTRUCT_CTRLR(); 2904 uint32_t active_ns_list[] = { 1, 2, 100, 1024 }; 2905 uint32_t active_ns_list2[] = { 1, 2, 1024 }; 2906 uint32_t active_ns_list3[] = { 1, 2, 101, 1024 }; 2907 union spdk_nvme_async_event_completion aer_event = { 2908 .bits.async_event_type = SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE, 2909 .bits.async_event_info = SPDK_NVME_ASYNC_EVENT_NS_ATTR_CHANGED 2910 }; 2911 struct spdk_nvme_cpl aer_cpl = { 2912 .status.sct = SPDK_NVME_SCT_GENERIC, 2913 .status.sc = SPDK_NVME_SC_SUCCESS, 2914 .cdw0 = aer_event.raw 2915 }; 2916 2917 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2918 2919 ctrlr.vs.bits.mjr = 1; 2920 ctrlr.vs.bits.mnr = 3; 2921 ctrlr.vs.bits.ter = 0; 2922 ctrlr.cap.bits.css |= SPDK_NVME_CAP_CSS_IOCS; 2923 ctrlr.cdata.nn = 4096; 2924 2925 ctrlr.state = NVME_CTRLR_STATE_CONFIGURE_AER; 2926 g_active_ns_list = active_ns_list; 2927 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list); 2928 2929 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 2930 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0); 2931 } 2932 2933 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 100)); 2934 2935 CU_ASSERT(nvme_ctrlr_add_process(&ctrlr, NULL) == 0); 2936 spdk_nvme_ctrlr_register_aer_callback(&ctrlr, aer_cb, NULL); 2937 2938 /* Remove NS 100 */ 2939 g_aer_cb_counter = 0; 2940 g_active_ns_list = active_ns_list2; 2941 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list2); 2942 nvme_ctrlr_async_event_cb(&ctrlr.aer[0], &aer_cpl); 2943 nvme_ctrlr_complete_queued_async_events(&ctrlr); 2944 CU_ASSERT(g_aer_cb_counter == 1); 2945 CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 100)); 2946 2947 /* Add NS 101 */ 2948 g_active_ns_list = active_ns_list3; 2949 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list3); 2950 nvme_ctrlr_async_event_cb(&ctrlr.aer[0], &aer_cpl); 2951 nvme_ctrlr_complete_queued_async_events(&ctrlr); 2952 CU_ASSERT(g_aer_cb_counter == 2); 2953 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 101)); 2954 2955 g_active_ns_list = NULL; 2956 g_active_ns_list_length = 0; 2957 nvme_ctrlr_free_processes(&ctrlr); 2958 nvme_ctrlr_destruct(&ctrlr); 2959 } 2960 2961 static void 2962 test_nvme_ctrlr_identify_namespaces_iocs_specific_next(void) 2963 { 2964 struct spdk_nvme_ctrlr ctrlr = {}; 2965 uint32_t prev_nsid; 2966 struct spdk_nvme_ns ns[5] = {}; 2967 struct spdk_nvme_ctrlr ns_ctrlr[5] = {}; 2968 int rc = 0; 2969 int i; 2970 2971 RB_INIT(&ctrlr.ns); 2972 for (i = 0; i < 5; i++) { 2973 ns[i].id = i + 1; 2974 ns[i].active = true; 2975 } 2976 2977 CU_ASSERT(pthread_mutex_init(&ctrlr.ctrlr_lock, NULL) == 0); 2978 2979 ctrlr.cdata.nn = 5; 2980 /* case 1: No first/next active NS, move on to the next state, expect: pass */ 2981 prev_nsid = 0; 2982 ctrlr.active_ns_count = 0; 2983 ctrlr.opts.admin_timeout_ms = NVME_TIMEOUT_INFINITE; 2984 rc = nvme_ctrlr_identify_namespaces_iocs_specific_next(&ctrlr, prev_nsid); 2985 CU_ASSERT(rc == 0); 2986 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES); 2987 CU_ASSERT(ctrlr.state_timeout_tsc == NVME_TIMEOUT_INFINITE); 2988 2989 /* case 2: move on to the next active NS, and no namespace with (supported) iocs specific data found , expect: pass */ 2990 memset(&ctrlr.state, 0x00, sizeof(ctrlr.state)); 2991 memset(&ctrlr.state_timeout_tsc, 0x00, sizeof(ctrlr.state_timeout_tsc)); 2992 prev_nsid = 1; 2993 for (i = 0; i < 5; i++) { 2994 RB_INSERT(nvme_ns_tree, &ctrlr.ns, &ns[i]); 2995 } 2996 ctrlr.active_ns_count = 5; 2997 ns[1].csi = SPDK_NVME_CSI_NVM; 2998 ns[1].id = 2; 2999 rc = nvme_ctrlr_identify_namespaces_iocs_specific_next(&ctrlr, prev_nsid); 3000 CU_ASSERT(rc == 0); 3001 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES); 3002 CU_ASSERT(ctrlr.state_timeout_tsc == NVME_TIMEOUT_INFINITE); 3003 3004 /* case 3: ns.csi is SPDK_NVME_CSI_ZNS, do not loop, expect: pass */ 3005 memset(&ctrlr.state, 0x00, sizeof(ctrlr.state)); 3006 memset(&ctrlr.state_timeout_tsc, 0x00, sizeof(ctrlr.state_timeout_tsc)); 3007 ctrlr.opts.admin_timeout_ms = NVME_TIMEOUT_INFINITE; 3008 prev_nsid = 0; 3009 ctrlr.active_ns_count = 5; 3010 3011 for (int i = 0; i < 5; i++) { 3012 ns[i].csi = SPDK_NVME_CSI_NVM; 3013 ns[i].id = i + 1; 3014 ns[i].ctrlr = &ns_ctrlr[i]; 3015 } 3016 ns[4].csi = SPDK_NVME_CSI_ZNS; 3017 ns_ctrlr[4].opts.admin_timeout_ms = NVME_TIMEOUT_INFINITE; 3018 3019 rc = nvme_ctrlr_identify_namespaces_iocs_specific_next(&ctrlr, prev_nsid); 3020 CU_ASSERT(rc == 0); 3021 CU_ASSERT(ctrlr.state == 0); 3022 CU_ASSERT(ctrlr.state_timeout_tsc == NVME_TIMEOUT_INFINITE); 3023 CU_ASSERT(ns_ctrlr[4].state == NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC); 3024 CU_ASSERT(ns_ctrlr[4].state_timeout_tsc == NVME_TIMEOUT_INFINITE); 3025 3026 for (int i = 0; i < 5; i++) { 3027 nvme_ns_free_zns_specific_data(&ns[i]); 3028 } 3029 3030 /* case 4: nvme_ctrlr_identify_ns_iocs_specific_async return 1, expect: false */ 3031 memset(&ctrlr.state, 0x00, sizeof(ctrlr.state)); 3032 memset(&ctrlr.state_timeout_tsc, 0x00, sizeof(ctrlr.state_timeout_tsc)); 3033 prev_nsid = 1; 3034 ctrlr.active_ns_count = 5; 3035 ns[1].csi = SPDK_NVME_CSI_ZNS; 3036 g_fail_next_identify = true; 3037 rc = nvme_ctrlr_identify_namespaces_iocs_specific_next(&ctrlr, prev_nsid); 3038 CU_ASSERT(rc == 1); 3039 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ERROR); 3040 CU_ASSERT(ctrlr.state_timeout_tsc == NVME_TIMEOUT_INFINITE); 3041 3042 CU_ASSERT(pthread_mutex_destroy(&ctrlr.ctrlr_lock) == 0); 3043 } 3044 3045 static void 3046 test_nvme_ctrlr_set_supported_log_pages(void) 3047 { 3048 int rc; 3049 struct spdk_nvme_ctrlr ctrlr = {}; 3050 3051 /* ana supported */ 3052 memset(&ctrlr, 0, sizeof(ctrlr)); 3053 ctrlr.cdata.cmic.ana_reporting = true; 3054 ctrlr.cdata.lpa.celp = 1; 3055 ctrlr.cdata.nanagrpid = 1; 3056 ctrlr.active_ns_count = 1; 3057 3058 rc = nvme_ctrlr_set_supported_log_pages(&ctrlr); 3059 CU_ASSERT(rc == 0); 3060 CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_ERROR] == true); 3061 CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_HEALTH_INFORMATION] == true); 3062 CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_FIRMWARE_SLOT] == true); 3063 CU_ASSERT(ctrlr.ana_log_page_size == sizeof(struct spdk_nvme_ana_page) + 3064 sizeof(struct spdk_nvme_ana_group_descriptor) * 1 + sizeof(uint32_t) * 1); 3065 CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS] == true); 3066 free(ctrlr.ana_log_page); 3067 free(ctrlr.copied_ana_desc); 3068 } 3069 3070 static void 3071 test_nvme_ctrlr_set_intel_supported_log_pages(void) 3072 { 3073 DECLARE_AND_CONSTRUCT_CTRLR(); 3074 3075 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 3076 3077 ctrlr.opts.admin_timeout_ms = NVME_TIMEOUT_INFINITE; 3078 ctrlr.cdata.vid = SPDK_PCI_VID_INTEL; 3079 ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_PCIE; 3080 ctrlr.state = NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES; 3081 3082 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 3083 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES); 3084 3085 set_status_code = SPDK_NVME_SC_SUCCESS; 3086 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 3087 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES); 3088 3089 CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_ERROR] == true); 3090 CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_HEALTH_INFORMATION] == true); 3091 CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_FIRMWARE_SLOT] == true); 3092 CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY] == true); 3093 CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_INTEL_LOG_WRITE_CMD_LATENCY] == true); 3094 CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_INTEL_LOG_TEMPERATURE] == true); 3095 CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_INTEL_LOG_SMART] == true); 3096 CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_INTEL_MARKETING_DESCRIPTION] == true); 3097 3098 nvme_ctrlr_destruct(&ctrlr); 3099 } 3100 3101 #define UT_ANA_DESC_SIZE (sizeof(struct spdk_nvme_ana_group_descriptor) + \ 3102 sizeof(uint32_t)) 3103 static void 3104 test_nvme_ctrlr_parse_ana_log_page(void) 3105 { 3106 int rc, i; 3107 struct spdk_nvme_ctrlr ctrlr = {}; 3108 struct spdk_nvme_ns ns[3] = {}; 3109 struct spdk_nvme_ana_page ana_hdr; 3110 char _ana_desc[UT_ANA_DESC_SIZE]; 3111 struct spdk_nvme_ana_group_descriptor *ana_desc; 3112 uint32_t offset; 3113 3114 RB_INIT(&ctrlr.ns); 3115 for (i = 0; i < 3; i++) { 3116 ns[i].id = i + 1; 3117 ns[i].active = true; 3118 RB_INSERT(nvme_ns_tree, &ctrlr.ns, &ns[i]); 3119 } 3120 3121 CU_ASSERT(pthread_mutex_init(&ctrlr.ctrlr_lock, NULL) == 0); 3122 3123 ctrlr.cdata.nn = 3; 3124 ctrlr.cdata.nanagrpid = 3; 3125 ctrlr.active_ns_count = 3; 3126 3127 rc = nvme_ctrlr_update_ana_log_page(&ctrlr); 3128 CU_ASSERT(rc == 0); 3129 CU_ASSERT(ctrlr.ana_log_page != NULL); 3130 CU_ASSERT(ctrlr.copied_ana_desc != NULL); 3131 3132 /* 3133 * Create ANA log page data - There are three ANA groups. 3134 * Each ANA group has a namespace and has a different ANA state. 3135 */ 3136 memset(&ana_hdr, 0, sizeof(ana_hdr)); 3137 ana_hdr.num_ana_group_desc = 3; 3138 3139 SPDK_CU_ASSERT_FATAL(sizeof(ana_hdr) <= ctrlr.ana_log_page_size); 3140 memcpy((char *)ctrlr.ana_log_page, (char *)&ana_hdr, sizeof(ana_hdr)); 3141 offset = sizeof(ana_hdr); 3142 3143 ana_desc = (struct spdk_nvme_ana_group_descriptor *)_ana_desc; 3144 memset(ana_desc, 0, UT_ANA_DESC_SIZE); 3145 ana_desc->num_of_nsid = 1; 3146 3147 ana_desc->ana_group_id = 1; 3148 ana_desc->ana_state = SPDK_NVME_ANA_OPTIMIZED_STATE; 3149 ana_desc->nsid[0] = 3; 3150 3151 SPDK_CU_ASSERT_FATAL(offset + UT_ANA_DESC_SIZE <= ctrlr.ana_log_page_size); 3152 memcpy((char *)ctrlr.ana_log_page + offset, (char *)ana_desc, UT_ANA_DESC_SIZE); 3153 offset += UT_ANA_DESC_SIZE; 3154 3155 ana_desc->ana_group_id = 2; 3156 ana_desc->ana_state = SPDK_NVME_ANA_NON_OPTIMIZED_STATE; 3157 ana_desc->nsid[0] = 2; 3158 3159 SPDK_CU_ASSERT_FATAL(offset + UT_ANA_DESC_SIZE <= ctrlr.ana_log_page_size); 3160 memcpy((char *)ctrlr.ana_log_page + offset, (char *)ana_desc, UT_ANA_DESC_SIZE); 3161 offset += UT_ANA_DESC_SIZE; 3162 3163 ana_desc->ana_group_id = 3; 3164 ana_desc->ana_state = SPDK_NVME_ANA_INACCESSIBLE_STATE; 3165 ana_desc->nsid[0] = 1; 3166 3167 SPDK_CU_ASSERT_FATAL(offset + UT_ANA_DESC_SIZE <= ctrlr.ana_log_page_size); 3168 memcpy((char *)ctrlr.ana_log_page + offset, (char *)ana_desc, UT_ANA_DESC_SIZE); 3169 3170 /* Parse the created ANA log page data, and update ANA states. */ 3171 rc = nvme_ctrlr_parse_ana_log_page(&ctrlr, nvme_ctrlr_update_ns_ana_states, 3172 &ctrlr); 3173 CU_ASSERT(rc == 0); 3174 CU_ASSERT(ns[0].ana_group_id == 3); 3175 CU_ASSERT(ns[0].ana_state == SPDK_NVME_ANA_INACCESSIBLE_STATE); 3176 CU_ASSERT(ns[1].ana_group_id == 2); 3177 CU_ASSERT(ns[1].ana_state == SPDK_NVME_ANA_NON_OPTIMIZED_STATE); 3178 CU_ASSERT(ns[2].ana_group_id == 1); 3179 CU_ASSERT(ns[2].ana_state == SPDK_NVME_ANA_OPTIMIZED_STATE); 3180 3181 CU_ASSERT(pthread_mutex_destroy(&ctrlr.ctrlr_lock) == 0); 3182 3183 free(ctrlr.ana_log_page); 3184 free(ctrlr.copied_ana_desc); 3185 } 3186 3187 static void 3188 test_nvme_ctrlr_ana_resize(void) 3189 { 3190 DECLARE_AND_CONSTRUCT_CTRLR(); 3191 uint32_t active_ns_list[] = { 1, 2, 3, 4 }; 3192 struct spdk_nvme_ana_page ana_hdr = { 3193 .change_count = 0, 3194 .num_ana_group_desc = 1 3195 }; 3196 uint8_t ana_desc_buf[sizeof(struct spdk_nvme_ana_group_descriptor) + 4 * sizeof(uint32_t)] = {}; 3197 struct spdk_nvme_ana_group_descriptor *ana_desc = 3198 (struct spdk_nvme_ana_group_descriptor *)ana_desc_buf; 3199 struct spdk_nvme_ns *ns; 3200 union spdk_nvme_async_event_completion aer_event = { 3201 .bits.async_event_type = SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE, 3202 .bits.async_event_info = SPDK_NVME_ASYNC_EVENT_NS_ATTR_CHANGED 3203 }; 3204 struct spdk_nvme_cpl aer_cpl = { 3205 .status.sct = SPDK_NVME_SCT_GENERIC, 3206 .status.sc = SPDK_NVME_SC_SUCCESS, 3207 .cdw0 = aer_event.raw 3208 }; 3209 uint32_t i; 3210 3211 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 3212 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_add_process(&ctrlr, NULL) == 0); 3213 3214 ctrlr.vs.bits.mjr = 1; 3215 ctrlr.vs.bits.mnr = 4; 3216 ctrlr.vs.bits.ter = 0; 3217 ctrlr.cdata.nn = 4096; 3218 ctrlr.cdata.cmic.ana_reporting = true; 3219 ctrlr.cdata.nanagrpid = 1; 3220 3221 ctrlr.state = NVME_CTRLR_STATE_CONFIGURE_AER; 3222 /* Start with 2 active namespaces */ 3223 g_active_ns_list = active_ns_list; 3224 g_active_ns_list_length = 2; 3225 g_ana_hdr = &ana_hdr; 3226 g_ana_descs = &ana_desc; 3227 ana_desc->ana_group_id = 1; 3228 ana_desc->ana_state = SPDK_NVME_ANA_NON_OPTIMIZED_STATE; 3229 ana_desc->num_of_nsid = 2; 3230 for (i = 0; i < ana_desc->num_of_nsid; ++i) { 3231 ana_desc->nsid[i] = i + 1; 3232 } 3233 3234 /* Bring controller to ready state */ 3235 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 3236 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0); 3237 } 3238 3239 for (i = 0; i < ana_desc->num_of_nsid; ++i) { 3240 ns = spdk_nvme_ctrlr_get_ns(&ctrlr, i + 1); 3241 CU_ASSERT(ns->ana_state == SPDK_NVME_ANA_NON_OPTIMIZED_STATE); 3242 } 3243 3244 /* Add more namespaces */ 3245 g_active_ns_list_length = 4; 3246 nvme_ctrlr_async_event_cb(&ctrlr.aer[0], &aer_cpl); 3247 nvme_ctrlr_complete_queued_async_events(&ctrlr); 3248 3249 /* Update ANA log with new namespaces */ 3250 ana_desc->ana_state = SPDK_NVME_ANA_OPTIMIZED_STATE; 3251 ana_desc->num_of_nsid = 4; 3252 for (i = 0; i < ana_desc->num_of_nsid; ++i) { 3253 ana_desc->nsid[i] = i + 1; 3254 } 3255 aer_event.bits.async_event_info = SPDK_NVME_ASYNC_EVENT_ANA_CHANGE; 3256 aer_cpl.cdw0 = aer_event.raw; 3257 nvme_ctrlr_async_event_cb(&ctrlr.aer[0], &aer_cpl); 3258 nvme_ctrlr_complete_queued_async_events(&ctrlr); 3259 3260 for (i = 0; i < ana_desc->num_of_nsid; ++i) { 3261 ns = spdk_nvme_ctrlr_get_ns(&ctrlr, i + 1); 3262 CU_ASSERT(ns->ana_state == SPDK_NVME_ANA_OPTIMIZED_STATE); 3263 } 3264 3265 g_active_ns_list = NULL; 3266 g_active_ns_list_length = 0; 3267 g_ana_hdr = NULL; 3268 g_ana_descs = NULL; 3269 nvme_ctrlr_free_processes(&ctrlr); 3270 nvme_ctrlr_destruct(&ctrlr); 3271 } 3272 3273 static void 3274 test_nvme_ctrlr_get_memory_domains(void) 3275 { 3276 struct spdk_nvme_ctrlr ctrlr = {}; 3277 3278 MOCK_SET(nvme_transport_ctrlr_get_memory_domains, 1); 3279 CU_ASSERT(spdk_nvme_ctrlr_get_memory_domains(&ctrlr, NULL, 0) == 1); 3280 3281 MOCK_SET(nvme_transport_ctrlr_get_memory_domains, 0); 3282 CU_ASSERT(spdk_nvme_ctrlr_get_memory_domains(&ctrlr, NULL, 0) == 0); 3283 3284 MOCK_CLEAR(nvme_transport_ctrlr_get_memory_domains); 3285 } 3286 3287 static void 3288 test_nvme_transport_ctrlr_ready(void) 3289 { 3290 DECLARE_AND_CONSTRUCT_CTRLR(); 3291 3292 /* Transport init succeeded */ 3293 ctrlr.state = NVME_CTRLR_STATE_TRANSPORT_READY; 3294 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0); 3295 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_READY); 3296 3297 /* Transport init failed */ 3298 ctrlr.state = NVME_CTRLR_STATE_TRANSPORT_READY; 3299 MOCK_SET(nvme_transport_ctrlr_ready, -1); 3300 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == -1); 3301 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ERROR); 3302 MOCK_CLEAR(nvme_transport_ctrlr_ready); 3303 } 3304 3305 int 3306 main(int argc, char **argv) 3307 { 3308 CU_pSuite suite = NULL; 3309 unsigned int num_failures; 3310 3311 CU_set_error_action(CUEA_ABORT); 3312 CU_initialize_registry(); 3313 3314 suite = CU_add_suite("nvme_ctrlr", NULL, NULL); 3315 3316 CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_1_rdy_0); 3317 CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_1_rdy_1); 3318 CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_0_rdy_0); 3319 CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_0_rdy_1); 3320 CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_0_rdy_0_ams_rr); 3321 CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr); 3322 CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_0_rdy_0_ams_vs); 3323 CU_ADD_TEST(suite, test_nvme_ctrlr_init_delay); 3324 CU_ADD_TEST(suite, test_alloc_io_qpair_rr_1); 3325 CU_ADD_TEST(suite, test_ctrlr_get_default_ctrlr_opts); 3326 CU_ADD_TEST(suite, test_ctrlr_get_default_io_qpair_opts); 3327 CU_ADD_TEST(suite, test_alloc_io_qpair_wrr_1); 3328 CU_ADD_TEST(suite, test_alloc_io_qpair_wrr_2); 3329 CU_ADD_TEST(suite, test_spdk_nvme_ctrlr_update_firmware); 3330 CU_ADD_TEST(suite, test_nvme_ctrlr_fail); 3331 CU_ADD_TEST(suite, test_nvme_ctrlr_construct_intel_support_log_page_list); 3332 CU_ADD_TEST(suite, test_nvme_ctrlr_set_supported_features); 3333 CU_ADD_TEST(suite, test_spdk_nvme_ctrlr_doorbell_buffer_config); 3334 #if 0 /* TODO: move to PCIe-specific unit test */ 3335 CU_ADD_TEST(suite, test_nvme_ctrlr_alloc_cmb); 3336 #endif 3337 CU_ADD_TEST(suite, test_nvme_ctrlr_test_active_ns); 3338 CU_ADD_TEST(suite, test_nvme_ctrlr_test_active_ns_error_case); 3339 CU_ADD_TEST(suite, test_spdk_nvme_ctrlr_reconnect_io_qpair); 3340 CU_ADD_TEST(suite, test_spdk_nvme_ctrlr_set_trid); 3341 CU_ADD_TEST(suite, test_nvme_ctrlr_init_set_nvmf_ioccsz); 3342 CU_ADD_TEST(suite, test_nvme_ctrlr_init_set_num_queues); 3343 CU_ADD_TEST(suite, test_nvme_ctrlr_init_set_keep_alive_timeout); 3344 CU_ADD_TEST(suite, test_alloc_io_qpair_fail); 3345 CU_ADD_TEST(suite, test_nvme_ctrlr_add_remove_process); 3346 CU_ADD_TEST(suite, test_nvme_ctrlr_set_arbitration_feature); 3347 CU_ADD_TEST(suite, test_nvme_ctrlr_set_state); 3348 CU_ADD_TEST(suite, test_nvme_ctrlr_active_ns_list_v0); 3349 CU_ADD_TEST(suite, test_nvme_ctrlr_active_ns_list_v2); 3350 CU_ADD_TEST(suite, test_nvme_ctrlr_ns_mgmt); 3351 CU_ADD_TEST(suite, test_nvme_ctrlr_reset); 3352 CU_ADD_TEST(suite, test_nvme_ctrlr_aer_callback); 3353 CU_ADD_TEST(suite, test_nvme_ctrlr_ns_attr_changed); 3354 CU_ADD_TEST(suite, test_nvme_ctrlr_identify_namespaces_iocs_specific_next); 3355 CU_ADD_TEST(suite, test_nvme_ctrlr_set_supported_log_pages); 3356 CU_ADD_TEST(suite, test_nvme_ctrlr_set_intel_supported_log_pages); 3357 CU_ADD_TEST(suite, test_nvme_ctrlr_parse_ana_log_page); 3358 CU_ADD_TEST(suite, test_nvme_ctrlr_ana_resize); 3359 CU_ADD_TEST(suite, test_nvme_ctrlr_get_memory_domains); 3360 CU_ADD_TEST(suite, test_nvme_transport_ctrlr_ready); 3361 3362 CU_basic_set_mode(CU_BRM_VERBOSE); 3363 CU_basic_run_tests(); 3364 num_failures = CU_get_number_of_failures(); 3365 CU_cleanup_registry(); 3366 return num_failures; 3367 } 3368