1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) Intel Corporation. All rights reserved. 3 * Copyright (c) 2020, 2021 Mellanox Technologies LTD. All rights reserved. 4 * Copyright (c) 2021, 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 5 */ 6 7 #include "spdk/stdinc.h" 8 9 #include "spdk_cunit.h" 10 11 #include "spdk/log.h" 12 13 #include "common/lib/test_env.c" 14 15 #include "nvme/nvme_ctrlr.c" 16 #include "nvme/nvme_quirks.c" 17 18 SPDK_LOG_REGISTER_COMPONENT(nvme) 19 20 pid_t g_spdk_nvme_pid; 21 22 struct nvme_driver _g_nvme_driver = { 23 .lock = PTHREAD_MUTEX_INITIALIZER, 24 }; 25 26 struct nvme_driver *g_spdk_nvme_driver = &_g_nvme_driver; 27 28 struct spdk_nvme_registers g_ut_nvme_regs = {}; 29 typedef void (*set_reg_cb)(void); 30 set_reg_cb g_set_reg_cb; 31 32 __thread int nvme_thread_ioq_index = -1; 33 34 uint32_t set_size = 1; 35 36 int set_status_cpl = -1; 37 38 DEFINE_STUB(nvme_ctrlr_cmd_set_host_id, int, 39 (struct spdk_nvme_ctrlr *ctrlr, void *host_id, uint32_t host_id_size, 40 spdk_nvme_cmd_cb cb_fn, void *cb_arg), 0); 41 DEFINE_STUB_V(nvme_ns_set_identify_data, (struct spdk_nvme_ns *ns)); 42 DEFINE_STUB_V(nvme_ns_set_id_desc_list_data, (struct spdk_nvme_ns *ns)); 43 DEFINE_STUB_V(nvme_ns_free_iocs_specific_data, (struct spdk_nvme_ns *ns)); 44 DEFINE_STUB_V(nvme_qpair_abort_all_queued_reqs, (struct spdk_nvme_qpair *qpair, uint32_t dnr)); 45 DEFINE_STUB(spdk_nvme_poll_group_remove, int, (struct spdk_nvme_poll_group *group, 46 struct spdk_nvme_qpair *qpair), 0); 47 DEFINE_STUB_V(nvme_io_msg_ctrlr_update, (struct spdk_nvme_ctrlr *ctrlr)); 48 DEFINE_STUB(nvme_io_msg_process, int, (struct spdk_nvme_ctrlr *ctrlr), 0); 49 DEFINE_STUB(nvme_transport_ctrlr_reserve_cmb, int, (struct spdk_nvme_ctrlr *ctrlr), 0); 50 DEFINE_STUB(spdk_nvme_ctrlr_cmd_security_receive, int, (struct spdk_nvme_ctrlr *ctrlr, 51 uint8_t secp, uint16_t spsp, uint8_t nssf, void *payload, 52 uint32_t payload_size, spdk_nvme_cmd_cb cb_fn, void *cb_arg), 0); 53 DEFINE_STUB(spdk_nvme_ctrlr_cmd_security_send, int, (struct spdk_nvme_ctrlr *ctrlr, 54 uint8_t secp, uint16_t spsp, uint8_t nssf, void *payload, 55 uint32_t payload_size, spdk_nvme_cmd_cb cb_fn, void *cb_arg), 0); 56 DEFINE_STUB_V(nvme_qpair_abort_queued_reqs, (struct spdk_nvme_qpair *qpair, uint32_t dnr)); 57 58 DEFINE_RETURN_MOCK(nvme_transport_ctrlr_get_memory_domains, int); 59 int 60 nvme_transport_ctrlr_get_memory_domains(const struct spdk_nvme_ctrlr *ctrlr, 61 struct spdk_memory_domain **domains, int array_size) 62 { 63 HANDLE_RETURN_MOCK(nvme_transport_ctrlr_get_memory_domains); 64 65 return 0; 66 } 67 68 struct spdk_nvme_ctrlr *nvme_transport_ctrlr_construct(const struct spdk_nvme_transport_id *trid, 69 const struct spdk_nvme_ctrlr_opts *opts, 70 void *devhandle) 71 { 72 return NULL; 73 } 74 75 int 76 nvme_transport_ctrlr_destruct(struct spdk_nvme_ctrlr *ctrlr) 77 { 78 nvme_ctrlr_destruct_finish(ctrlr); 79 80 return 0; 81 } 82 83 int 84 nvme_transport_ctrlr_enable(struct spdk_nvme_ctrlr *ctrlr) 85 { 86 return 0; 87 } 88 89 int 90 nvme_transport_ctrlr_set_reg_4(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint32_t value) 91 { 92 SPDK_CU_ASSERT_FATAL(offset <= sizeof(struct spdk_nvme_registers) - 4); 93 *(uint32_t *)((uintptr_t)&g_ut_nvme_regs + offset) = value; 94 if (g_set_reg_cb) { 95 g_set_reg_cb(); 96 } 97 return 0; 98 } 99 100 int 101 nvme_transport_ctrlr_set_reg_8(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint64_t value) 102 { 103 SPDK_CU_ASSERT_FATAL(offset <= sizeof(struct spdk_nvme_registers) - 8); 104 *(uint64_t *)((uintptr_t)&g_ut_nvme_regs + offset) = value; 105 if (g_set_reg_cb) { 106 g_set_reg_cb(); 107 } 108 return 0; 109 } 110 111 int 112 nvme_transport_ctrlr_get_reg_4(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint32_t *value) 113 { 114 SPDK_CU_ASSERT_FATAL(offset <= sizeof(struct spdk_nvme_registers) - 4); 115 *value = *(uint32_t *)((uintptr_t)&g_ut_nvme_regs + offset); 116 return 0; 117 } 118 119 int 120 nvme_transport_ctrlr_get_reg_8(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint64_t *value) 121 { 122 SPDK_CU_ASSERT_FATAL(offset <= sizeof(struct spdk_nvme_registers) - 8); 123 *value = *(uint64_t *)((uintptr_t)&g_ut_nvme_regs + offset); 124 return 0; 125 } 126 127 int 128 nvme_transport_ctrlr_set_reg_4_async(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, 129 uint32_t value, spdk_nvme_reg_cb cb_fn, void *cb_arg) 130 { 131 struct spdk_nvme_cpl cpl = {}; 132 133 cpl.status.sct = SPDK_NVME_SCT_GENERIC; 134 cpl.status.sc = SPDK_NVME_SC_SUCCESS; 135 136 nvme_transport_ctrlr_set_reg_4(ctrlr, offset, value); 137 cb_fn(cb_arg, value, &cpl); 138 return 0; 139 } 140 141 int 142 nvme_transport_ctrlr_set_reg_8_async(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, 143 uint64_t value, spdk_nvme_reg_cb cb_fn, void *cb_arg) 144 { 145 struct spdk_nvme_cpl cpl = {}; 146 147 cpl.status.sct = SPDK_NVME_SCT_GENERIC; 148 cpl.status.sc = SPDK_NVME_SC_SUCCESS; 149 150 nvme_transport_ctrlr_set_reg_8(ctrlr, offset, value); 151 cb_fn(cb_arg, value, &cpl); 152 return 0; 153 } 154 155 int 156 nvme_transport_ctrlr_get_reg_4_async(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, 157 spdk_nvme_reg_cb cb_fn, void *cb_arg) 158 { 159 struct spdk_nvme_cpl cpl = {}; 160 uint32_t value; 161 162 cpl.status.sct = SPDK_NVME_SCT_GENERIC; 163 cpl.status.sc = SPDK_NVME_SC_SUCCESS; 164 165 nvme_transport_ctrlr_get_reg_4(ctrlr, offset, &value); 166 cb_fn(cb_arg, value, &cpl); 167 return 0; 168 } 169 170 int 171 nvme_transport_ctrlr_get_reg_8_async(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, 172 spdk_nvme_reg_cb cb_fn, void *cb_arg) 173 { 174 struct spdk_nvme_cpl cpl = {}; 175 uint64_t value; 176 177 cpl.status.sct = SPDK_NVME_SCT_GENERIC; 178 cpl.status.sc = SPDK_NVME_SC_SUCCESS; 179 180 nvme_transport_ctrlr_get_reg_8(ctrlr, offset, &value); 181 cb_fn(cb_arg, value, &cpl); 182 return 0; 183 } 184 185 uint32_t 186 nvme_transport_ctrlr_get_max_xfer_size(struct spdk_nvme_ctrlr *ctrlr) 187 { 188 return UINT32_MAX; 189 } 190 191 uint16_t 192 nvme_transport_ctrlr_get_max_sges(struct spdk_nvme_ctrlr *ctrlr) 193 { 194 return 1; 195 } 196 197 void * 198 nvme_transport_ctrlr_map_cmb(struct spdk_nvme_ctrlr *ctrlr, size_t *size) 199 { 200 return NULL; 201 } 202 203 int 204 nvme_transport_ctrlr_unmap_cmb(struct spdk_nvme_ctrlr *ctrlr) 205 { 206 return 0; 207 } 208 209 int 210 nvme_transport_ctrlr_enable_pmr(struct spdk_nvme_ctrlr *ctrlr) 211 { 212 return 0; 213 } 214 215 int 216 nvme_transport_ctrlr_disable_pmr(struct spdk_nvme_ctrlr *ctrlr) 217 { 218 return 0; 219 } 220 221 void * 222 nvme_transport_ctrlr_map_pmr(struct spdk_nvme_ctrlr *ctrlr, size_t *size) 223 { 224 return NULL; 225 } 226 227 int 228 nvme_transport_ctrlr_unmap_pmr(struct spdk_nvme_ctrlr *ctrlr) 229 { 230 return 0; 231 } 232 233 struct spdk_nvme_qpair * 234 nvme_transport_ctrlr_create_io_qpair(struct spdk_nvme_ctrlr *ctrlr, uint16_t qid, 235 const struct spdk_nvme_io_qpair_opts *opts) 236 { 237 struct spdk_nvme_qpair *qpair; 238 239 qpair = calloc(1, sizeof(*qpair)); 240 SPDK_CU_ASSERT_FATAL(qpair != NULL); 241 242 qpair->ctrlr = ctrlr; 243 qpair->id = qid; 244 qpair->qprio = opts->qprio; 245 246 return qpair; 247 } 248 249 void 250 nvme_transport_ctrlr_delete_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair) 251 { 252 free(qpair); 253 } 254 255 void 256 nvme_transport_ctrlr_disconnect_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair) 257 { 258 } 259 260 int 261 nvme_transport_qpair_reset(struct spdk_nvme_qpair *qpair) 262 { 263 return 0; 264 } 265 266 void 267 nvme_transport_admin_qpair_abort_aers(struct spdk_nvme_qpair *qpair) 268 { 269 } 270 271 void 272 nvme_transport_qpair_abort_reqs(struct spdk_nvme_qpair *qpair, uint32_t dnr) 273 { 274 } 275 276 int 277 nvme_driver_init(void) 278 { 279 return 0; 280 } 281 282 int 283 nvme_qpair_init(struct spdk_nvme_qpair *qpair, uint16_t id, 284 struct spdk_nvme_ctrlr *ctrlr, 285 enum spdk_nvme_qprio qprio, 286 uint32_t num_requests, bool async) 287 { 288 qpair->id = id; 289 qpair->qprio = qprio; 290 qpair->ctrlr = ctrlr; 291 qpair->async = async; 292 293 return 0; 294 } 295 296 static struct spdk_nvme_cpl fake_cpl = {}; 297 static enum spdk_nvme_generic_command_status_code set_status_code = SPDK_NVME_SC_SUCCESS; 298 299 static void 300 fake_cpl_sc(spdk_nvme_cmd_cb cb_fn, void *cb_arg) 301 { 302 fake_cpl.status.sc = set_status_code; 303 cb_fn(cb_arg, &fake_cpl); 304 } 305 306 static uint32_t g_ut_cdw11; 307 308 int 309 spdk_nvme_ctrlr_cmd_set_feature(struct spdk_nvme_ctrlr *ctrlr, uint8_t feature, 310 uint32_t cdw11, uint32_t cdw12, void *payload, uint32_t payload_size, 311 spdk_nvme_cmd_cb cb_fn, void *cb_arg) 312 { 313 g_ut_cdw11 = cdw11; 314 return 0; 315 } 316 317 int 318 spdk_nvme_ctrlr_cmd_get_feature(struct spdk_nvme_ctrlr *ctrlr, uint8_t feature, 319 uint32_t cdw11, void *payload, uint32_t payload_size, 320 spdk_nvme_cmd_cb cb_fn, void *cb_arg) 321 { 322 fake_cpl_sc(cb_fn, cb_arg); 323 return 0; 324 } 325 326 struct spdk_nvme_ana_page *g_ana_hdr; 327 struct spdk_nvme_ana_group_descriptor **g_ana_descs; 328 329 int 330 spdk_nvme_ctrlr_cmd_get_log_page(struct spdk_nvme_ctrlr *ctrlr, uint8_t log_page, 331 uint32_t nsid, void *payload, uint32_t payload_size, 332 uint64_t offset, spdk_nvme_cmd_cb cb_fn, void *cb_arg) 333 { 334 if ((log_page == SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS) && g_ana_hdr) { 335 uint32_t i; 336 uint8_t *ptr = payload; 337 338 memset(payload, 0, payload_size); 339 memcpy(ptr, g_ana_hdr, sizeof(*g_ana_hdr)); 340 ptr += sizeof(*g_ana_hdr); 341 for (i = 0; i < g_ana_hdr->num_ana_group_desc; ++i) { 342 uint32_t desc_size = sizeof(**g_ana_descs) + 343 g_ana_descs[i]->num_of_nsid * sizeof(uint32_t); 344 memcpy(ptr, g_ana_descs[i], desc_size); 345 ptr += desc_size; 346 } 347 } else if (log_page == SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY) { 348 struct spdk_nvme_intel_log_page_directory *log_page_directory = payload; 349 log_page_directory->read_latency_log_len = true; 350 log_page_directory->write_latency_log_len = true; 351 log_page_directory->temperature_statistics_log_len = true; 352 log_page_directory->smart_log_len = true; 353 log_page_directory->marketing_description_log_len = true; 354 } 355 356 fake_cpl_sc(cb_fn, cb_arg); 357 return 0; 358 } 359 360 int 361 spdk_nvme_ctrlr_cmd_get_log_page_ext(struct spdk_nvme_ctrlr *ctrlr, uint8_t log_page, 362 uint32_t nsid, void *payload, uint32_t payload_size, 363 uint64_t offset, uint32_t cdw10, uint32_t cdw11, 364 uint32_t cdw14, spdk_nvme_cmd_cb cb_fn, void *cb_arg) 365 { 366 fake_cpl_sc(cb_fn, cb_arg); 367 return 0; 368 } 369 370 int 371 nvme_qpair_submit_request(struct spdk_nvme_qpair *qpair, struct nvme_request *req) 372 { 373 CU_ASSERT(req->cmd.opc == SPDK_NVME_OPC_ASYNC_EVENT_REQUEST); 374 STAILQ_INSERT_HEAD(&qpair->free_req, req, stailq); 375 376 /* 377 * For the purposes of this unit test, we don't need to bother emulating request submission. 378 */ 379 380 return 0; 381 } 382 383 static int32_t g_wait_for_completion_return_val; 384 385 int32_t 386 spdk_nvme_qpair_process_completions(struct spdk_nvme_qpair *qpair, uint32_t max_completions) 387 { 388 return g_wait_for_completion_return_val; 389 } 390 391 void 392 nvme_qpair_complete_error_reqs(struct spdk_nvme_qpair *qpair) 393 { 394 } 395 396 397 void 398 nvme_completion_poll_cb(void *arg, const struct spdk_nvme_cpl *cpl) 399 { 400 struct nvme_completion_poll_status *status = arg; 401 /* This should not happen it test env since this callback is always called 402 * before wait_for_completion_* while this field can only be set to true in 403 * wait_for_completion_* functions */ 404 CU_ASSERT(status->timed_out == false); 405 406 status->cpl = *cpl; 407 status->done = true; 408 } 409 410 static struct nvme_completion_poll_status *g_failed_status; 411 412 int 413 nvme_wait_for_completion_robust_lock_timeout( 414 struct spdk_nvme_qpair *qpair, 415 struct nvme_completion_poll_status *status, 416 pthread_mutex_t *robust_mutex, 417 uint64_t timeout_in_usecs) 418 { 419 if (spdk_nvme_qpair_process_completions(qpair, 0) < 0) { 420 g_failed_status = status; 421 status->timed_out = true; 422 return -1; 423 } 424 425 status->done = true; 426 if (set_status_cpl == 1) { 427 status->cpl.status.sc = 1; 428 } 429 return spdk_nvme_cpl_is_error(&status->cpl) ? -EIO : 0; 430 } 431 432 int 433 nvme_wait_for_completion_robust_lock( 434 struct spdk_nvme_qpair *qpair, 435 struct nvme_completion_poll_status *status, 436 pthread_mutex_t *robust_mutex) 437 { 438 return nvme_wait_for_completion_robust_lock_timeout(qpair, status, robust_mutex, 0); 439 } 440 441 int 442 nvme_wait_for_completion(struct spdk_nvme_qpair *qpair, 443 struct nvme_completion_poll_status *status) 444 { 445 return nvme_wait_for_completion_robust_lock_timeout(qpair, status, NULL, 0); 446 } 447 448 int 449 nvme_wait_for_completion_timeout(struct spdk_nvme_qpair *qpair, 450 struct nvme_completion_poll_status *status, 451 uint64_t timeout_in_usecs) 452 { 453 return nvme_wait_for_completion_robust_lock_timeout(qpair, status, NULL, timeout_in_usecs); 454 } 455 456 int 457 nvme_ctrlr_cmd_set_async_event_config(struct spdk_nvme_ctrlr *ctrlr, 458 union spdk_nvme_feat_async_event_configuration config, spdk_nvme_cmd_cb cb_fn, 459 void *cb_arg) 460 { 461 fake_cpl_sc(cb_fn, cb_arg); 462 return 0; 463 } 464 465 static uint32_t *g_active_ns_list = NULL; 466 static uint32_t g_active_ns_list_length = 0; 467 static struct spdk_nvme_ctrlr_data *g_cdata = NULL; 468 static bool g_fail_next_identify = false; 469 470 int 471 nvme_ctrlr_cmd_identify(struct spdk_nvme_ctrlr *ctrlr, uint8_t cns, uint16_t cntid, uint32_t nsid, 472 uint8_t csi, void *payload, size_t payload_size, 473 spdk_nvme_cmd_cb cb_fn, void *cb_arg) 474 { 475 if (g_fail_next_identify) { 476 g_fail_next_identify = false; 477 return 1; 478 } 479 480 memset(payload, 0, payload_size); 481 if (cns == SPDK_NVME_IDENTIFY_ACTIVE_NS_LIST) { 482 uint32_t count = 0; 483 uint32_t i = 0; 484 struct spdk_nvme_ns_list *ns_list = (struct spdk_nvme_ns_list *)payload; 485 486 if (g_active_ns_list == NULL) { 487 for (i = 1; i <= ctrlr->cdata.nn; i++) { 488 if (i <= nsid) { 489 continue; 490 } 491 492 ns_list->ns_list[count++] = i; 493 if (count == SPDK_COUNTOF(ns_list->ns_list)) { 494 break; 495 } 496 } 497 } else { 498 for (i = 0; i < g_active_ns_list_length; i++) { 499 uint32_t cur_nsid = g_active_ns_list[i]; 500 if (cur_nsid <= nsid) { 501 continue; 502 } 503 504 ns_list->ns_list[count++] = cur_nsid; 505 if (count == SPDK_COUNTOF(ns_list->ns_list)) { 506 break; 507 } 508 } 509 } 510 } else if (cns == SPDK_NVME_IDENTIFY_CTRLR) { 511 if (g_cdata) { 512 memcpy(payload, g_cdata, sizeof(*g_cdata)); 513 } 514 } else if (cns == SPDK_NVME_IDENTIFY_NS_IOCS) { 515 return 0; 516 } 517 518 fake_cpl_sc(cb_fn, cb_arg); 519 return 0; 520 } 521 522 int 523 nvme_ctrlr_cmd_set_num_queues(struct spdk_nvme_ctrlr *ctrlr, 524 uint32_t num_queues, spdk_nvme_cmd_cb cb_fn, void *cb_arg) 525 { 526 fake_cpl_sc(cb_fn, cb_arg); 527 return 0; 528 } 529 530 int 531 nvme_ctrlr_cmd_get_num_queues(struct spdk_nvme_ctrlr *ctrlr, 532 spdk_nvme_cmd_cb cb_fn, void *cb_arg) 533 { 534 CU_ASSERT(0); 535 return -1; 536 } 537 538 int 539 nvme_ctrlr_cmd_attach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, 540 struct spdk_nvme_ctrlr_list *payload, spdk_nvme_cmd_cb cb_fn, void *cb_arg) 541 { 542 return 0; 543 } 544 545 int 546 nvme_ctrlr_cmd_detach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, 547 struct spdk_nvme_ctrlr_list *payload, spdk_nvme_cmd_cb cb_fn, void *cb_arg) 548 { 549 return 0; 550 } 551 552 int 553 nvme_ctrlr_cmd_create_ns(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_ns_data *payload, 554 spdk_nvme_cmd_cb cb_fn, void *cb_arg) 555 { 556 fake_cpl_sc(cb_fn, cb_arg); 557 return 0; 558 } 559 560 int 561 nvme_ctrlr_cmd_delete_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, spdk_nvme_cmd_cb cb_fn, 562 void *cb_arg) 563 { 564 return 0; 565 } 566 567 int 568 nvme_ctrlr_cmd_format(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, struct spdk_nvme_format *format, 569 spdk_nvme_cmd_cb cb_fn, void *cb_arg) 570 { 571 return 0; 572 } 573 574 int 575 spdk_nvme_ctrlr_cmd_directive_send(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, 576 uint32_t doper, uint32_t dtype, uint32_t dspec, 577 void *payload, uint32_t payload_size, uint32_t cdw12, 578 uint32_t cdw13, spdk_nvme_cmd_cb cb_fn, void *cb_arg) 579 { 580 return 0; 581 } 582 583 int 584 spdk_nvme_ctrlr_cmd_directive_receive(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, 585 uint32_t doper, uint32_t dtype, uint32_t dspec, 586 void *payload, uint32_t payload_size, uint32_t cdw12, 587 uint32_t cdw13, spdk_nvme_cmd_cb cb_fn, void *cb_arg) 588 { 589 return 0; 590 } 591 592 int 593 nvme_ctrlr_cmd_fw_commit(struct spdk_nvme_ctrlr *ctrlr, const struct spdk_nvme_fw_commit *fw_commit, 594 spdk_nvme_cmd_cb cb_fn, void *cb_arg) 595 { 596 CU_ASSERT(fw_commit->ca == SPDK_NVME_FW_COMMIT_REPLACE_IMG); 597 if (fw_commit->fs == 0) { 598 return -1; 599 } 600 set_status_cpl = 1; 601 if (ctrlr->is_resetting == true) { 602 set_status_cpl = 0; 603 } 604 return 0; 605 } 606 607 int 608 nvme_ctrlr_cmd_fw_image_download(struct spdk_nvme_ctrlr *ctrlr, 609 uint32_t size, uint32_t offset, void *payload, 610 spdk_nvme_cmd_cb cb_fn, void *cb_arg) 611 { 612 if ((size != 0 && payload == NULL) || (size == 0 && payload != NULL)) { 613 return -1; 614 } 615 CU_ASSERT(offset == 0); 616 return 0; 617 } 618 619 bool 620 nvme_ns_has_supported_iocs_specific_data(struct spdk_nvme_ns *ns) 621 { 622 switch (ns->csi) { 623 case SPDK_NVME_CSI_NVM: 624 /* 625 * NVM Command Set Specific Identify Namespace data structure 626 * is currently all-zeroes, reserved for future use. 627 */ 628 return false; 629 case SPDK_NVME_CSI_ZNS: 630 return true; 631 default: 632 SPDK_WARNLOG("Unsupported CSI: %u for NSID: %u\n", ns->csi, ns->id); 633 return false; 634 } 635 } 636 637 void 638 nvme_ns_free_zns_specific_data(struct spdk_nvme_ns *ns) 639 { 640 if (!ns->id) { 641 return; 642 } 643 644 if (ns->nsdata_zns) { 645 spdk_free(ns->nsdata_zns); 646 ns->nsdata_zns = NULL; 647 } 648 } 649 650 void 651 nvme_ns_destruct(struct spdk_nvme_ns *ns) 652 { 653 } 654 655 int 656 nvme_ns_construct(struct spdk_nvme_ns *ns, uint32_t id, 657 struct spdk_nvme_ctrlr *ctrlr) 658 { 659 return 0; 660 } 661 662 void 663 spdk_pci_device_detach(struct spdk_pci_device *device) 664 { 665 } 666 667 #define DECLARE_AND_CONSTRUCT_CTRLR() \ 668 struct spdk_nvme_ctrlr ctrlr = {}; \ 669 struct spdk_nvme_qpair adminq = {}; \ 670 struct nvme_request req; \ 671 \ 672 STAILQ_INIT(&adminq.free_req); \ 673 STAILQ_INSERT_HEAD(&adminq.free_req, &req, stailq); \ 674 ctrlr.adminq = &adminq; 675 676 static void 677 test_nvme_ctrlr_init_en_1_rdy_0(void) 678 { 679 DECLARE_AND_CONSTRUCT_CTRLR(); 680 681 memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs)); 682 683 /* 684 * Initial state: CC.EN = 1, CSTS.RDY = 0 685 */ 686 g_ut_nvme_regs.cc.bits.en = 1; 687 g_ut_nvme_regs.csts.bits.rdy = 0; 688 689 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 690 ctrlr.cdata.nn = 1; 691 ctrlr.page_size = 0x1000; 692 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 693 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 694 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 695 } 696 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 697 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1); 698 699 /* 700 * Transition to CSTS.RDY = 1. 701 * init() should set CC.EN = 0. 702 */ 703 g_ut_nvme_regs.csts.bits.rdy = 1; 704 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 705 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_EN_0); 706 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 707 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 708 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); 709 710 /* 711 * Transition to CSTS.RDY = 0. 712 */ 713 g_ut_nvme_regs.csts.bits.rdy = 0; 714 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 715 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 716 717 /* 718 * Start enabling the controller. 719 */ 720 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 721 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 722 723 /* 724 * Transition to CC.EN = 1 725 */ 726 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 727 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 728 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 729 730 /* 731 * Transition to CSTS.RDY = 1. 732 */ 733 g_ut_nvme_regs.csts.bits.rdy = 1; 734 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 735 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE); 736 737 /* 738 * Transition to READY. 739 */ 740 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 741 nvme_ctrlr_process_init(&ctrlr); 742 } 743 744 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 745 nvme_ctrlr_destruct(&ctrlr); 746 } 747 748 static void 749 test_nvme_ctrlr_init_en_1_rdy_1(void) 750 { 751 DECLARE_AND_CONSTRUCT_CTRLR(); 752 753 memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs)); 754 755 /* 756 * Initial state: CC.EN = 1, CSTS.RDY = 1 757 * init() should set CC.EN = 0. 758 */ 759 g_ut_nvme_regs.cc.bits.en = 1; 760 g_ut_nvme_regs.csts.bits.rdy = 1; 761 762 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 763 ctrlr.cdata.nn = 1; 764 ctrlr.page_size = 0x1000; 765 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 766 while (ctrlr.state != NVME_CTRLR_STATE_SET_EN_0) { 767 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 768 } 769 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 770 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 771 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); 772 773 /* 774 * Transition to CSTS.RDY = 0. 775 */ 776 g_ut_nvme_regs.csts.bits.rdy = 0; 777 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 778 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 779 780 /* 781 * Start enabling the controller. 782 */ 783 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 784 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 785 786 /* 787 * Transition to CC.EN = 1 788 */ 789 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 790 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 791 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 792 793 /* 794 * Transition to CSTS.RDY = 1. 795 */ 796 g_ut_nvme_regs.csts.bits.rdy = 1; 797 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 798 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE); 799 800 /* 801 * Transition to READY. 802 */ 803 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 804 nvme_ctrlr_process_init(&ctrlr); 805 } 806 807 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 808 nvme_ctrlr_destruct(&ctrlr); 809 } 810 811 static void 812 test_nvme_ctrlr_init_en_0_rdy_0_ams_rr(void) 813 { 814 DECLARE_AND_CONSTRUCT_CTRLR(); 815 816 memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs)); 817 818 /* 819 * Initial state: CC.EN = 0, CSTS.RDY = 0 820 * init() should set CC.EN = 1. 821 */ 822 g_ut_nvme_regs.cc.bits.en = 0; 823 g_ut_nvme_regs.csts.bits.rdy = 0; 824 825 /* 826 * Default round robin enabled 827 */ 828 g_ut_nvme_regs.cap.bits.ams = 0x0; 829 ctrlr.cap = g_ut_nvme_regs.cap; 830 831 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 832 ctrlr.cdata.nn = 1; 833 ctrlr.page_size = 0x1000; 834 /* 835 * Case 1: default round robin arbitration mechanism selected 836 */ 837 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_RR; 838 839 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 840 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 841 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 842 } 843 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 844 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 845 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 846 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 847 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 848 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 849 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 850 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 851 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 852 CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR); 853 CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_RR); 854 855 /* 856 * Complete and destroy the controller 857 */ 858 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 859 nvme_ctrlr_destruct(&ctrlr); 860 861 /* 862 * Reset to initial state 863 */ 864 g_ut_nvme_regs.cc.bits.en = 0; 865 g_ut_nvme_regs.csts.bits.rdy = 0; 866 867 /* 868 * Case 2: weighted round robin arbitration mechanism selected 869 */ 870 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 871 ctrlr.cdata.nn = 1; 872 ctrlr.page_size = 0x1000; 873 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR; 874 875 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 876 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 877 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 878 } 879 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 880 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 881 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 882 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 883 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 884 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 885 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); 886 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); 887 888 /* 889 * Complete and destroy the controller 890 */ 891 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 892 nvme_ctrlr_destruct(&ctrlr); 893 894 /* 895 * Reset to initial state 896 */ 897 g_ut_nvme_regs.cc.bits.en = 0; 898 g_ut_nvme_regs.csts.bits.rdy = 0; 899 900 /* 901 * Case 3: vendor specific arbitration mechanism selected 902 */ 903 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 904 ctrlr.cdata.nn = 1; 905 ctrlr.page_size = 0x1000; 906 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS; 907 908 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 909 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 910 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 911 } 912 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 913 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 914 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 915 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 916 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 917 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 918 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); 919 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); 920 921 /* 922 * Complete and destroy the controller 923 */ 924 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 925 nvme_ctrlr_destruct(&ctrlr); 926 927 /* 928 * Reset to initial state 929 */ 930 g_ut_nvme_regs.cc.bits.en = 0; 931 g_ut_nvme_regs.csts.bits.rdy = 0; 932 933 /* 934 * Case 4: invalid arbitration mechanism selected 935 */ 936 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 937 ctrlr.cdata.nn = 1; 938 ctrlr.page_size = 0x1000; 939 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS + 1; 940 941 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 942 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 943 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 944 } 945 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 946 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 947 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 948 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 949 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 950 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 951 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); 952 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); 953 954 /* 955 * Complete and destroy the controller 956 */ 957 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 958 nvme_ctrlr_destruct(&ctrlr); 959 960 /* 961 * Reset to initial state 962 */ 963 g_ut_nvme_regs.cc.bits.en = 0; 964 g_ut_nvme_regs.csts.bits.rdy = 0; 965 966 /* 967 * Case 5: reset to default round robin arbitration mechanism 968 */ 969 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 970 ctrlr.cdata.nn = 1; 971 ctrlr.page_size = 0x1000; 972 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_RR; 973 974 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 975 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 976 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 977 } 978 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 979 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 980 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 981 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 982 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 983 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 984 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 985 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 986 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 987 CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR); 988 CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_RR); 989 990 /* 991 * Transition to CSTS.RDY = 1. 992 */ 993 g_ut_nvme_regs.csts.bits.rdy = 1; 994 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 995 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE); 996 997 /* 998 * Transition to READY. 999 */ 1000 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 1001 nvme_ctrlr_process_init(&ctrlr); 1002 } 1003 1004 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1005 nvme_ctrlr_destruct(&ctrlr); 1006 } 1007 1008 static void 1009 test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr(void) 1010 { 1011 DECLARE_AND_CONSTRUCT_CTRLR(); 1012 1013 memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs)); 1014 1015 /* 1016 * Initial state: CC.EN = 0, CSTS.RDY = 0 1017 * init() should set CC.EN = 1. 1018 */ 1019 g_ut_nvme_regs.cc.bits.en = 0; 1020 g_ut_nvme_regs.csts.bits.rdy = 0; 1021 1022 /* 1023 * Weighted round robin enabled 1024 */ 1025 g_ut_nvme_regs.cap.bits.ams = SPDK_NVME_CAP_AMS_WRR; 1026 ctrlr.cap = g_ut_nvme_regs.cap; 1027 1028 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 1029 ctrlr.cdata.nn = 1; 1030 ctrlr.page_size = 0x1000; 1031 /* 1032 * Case 1: default round robin arbitration mechanism selected 1033 */ 1034 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_RR; 1035 1036 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 1037 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 1038 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1039 } 1040 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1041 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 1042 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1043 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 1044 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1045 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 1046 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1047 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 1048 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 1049 CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR); 1050 CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_RR); 1051 1052 /* 1053 * Complete and destroy the controller 1054 */ 1055 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1056 nvme_ctrlr_destruct(&ctrlr); 1057 1058 /* 1059 * Reset to initial state 1060 */ 1061 g_ut_nvme_regs.cc.bits.en = 0; 1062 g_ut_nvme_regs.csts.bits.rdy = 0; 1063 1064 /* 1065 * Case 2: weighted round robin arbitration mechanism selected 1066 */ 1067 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 1068 ctrlr.cdata.nn = 1; 1069 ctrlr.page_size = 0x1000; 1070 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR; 1071 1072 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 1073 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 1074 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1075 } 1076 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1077 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 1078 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1079 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 1080 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1081 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 1082 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1083 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 1084 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 1085 CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_WRR); 1086 CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_WRR); 1087 1088 /* 1089 * Complete and destroy the controller 1090 */ 1091 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1092 nvme_ctrlr_destruct(&ctrlr); 1093 1094 /* 1095 * Reset to initial state 1096 */ 1097 g_ut_nvme_regs.cc.bits.en = 0; 1098 g_ut_nvme_regs.csts.bits.rdy = 0; 1099 1100 /* 1101 * Case 3: vendor specific arbitration mechanism selected 1102 */ 1103 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 1104 ctrlr.cdata.nn = 1; 1105 ctrlr.page_size = 0x1000; 1106 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS; 1107 1108 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 1109 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 1110 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1111 } 1112 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1113 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 1114 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1115 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 1116 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1117 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 1118 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); 1119 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); 1120 1121 /* 1122 * Complete and destroy the controller 1123 */ 1124 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1125 nvme_ctrlr_destruct(&ctrlr); 1126 1127 /* 1128 * Reset to initial state 1129 */ 1130 g_ut_nvme_regs.cc.bits.en = 0; 1131 g_ut_nvme_regs.csts.bits.rdy = 0; 1132 1133 /* 1134 * Case 4: invalid arbitration mechanism selected 1135 */ 1136 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 1137 ctrlr.cdata.nn = 1; 1138 ctrlr.page_size = 0x1000; 1139 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS + 1; 1140 1141 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 1142 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 1143 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1144 } 1145 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1146 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 1147 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1148 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 1149 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1150 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 1151 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); 1152 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); 1153 1154 /* 1155 * Complete and destroy the controller 1156 */ 1157 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1158 nvme_ctrlr_destruct(&ctrlr); 1159 1160 /* 1161 * Reset to initial state 1162 */ 1163 g_ut_nvme_regs.cc.bits.en = 0; 1164 g_ut_nvme_regs.csts.bits.rdy = 0; 1165 1166 /* 1167 * Case 5: reset to weighted round robin arbitration mechanism 1168 */ 1169 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 1170 ctrlr.cdata.nn = 1; 1171 ctrlr.page_size = 0x1000; 1172 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR; 1173 1174 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 1175 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 1176 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1177 } 1178 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1179 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 1180 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1181 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 1182 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1183 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 1184 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1185 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 1186 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 1187 CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_WRR); 1188 CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_WRR); 1189 1190 /* 1191 * Transition to CSTS.RDY = 1. 1192 */ 1193 g_ut_nvme_regs.csts.bits.rdy = 1; 1194 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1195 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE); 1196 1197 /* 1198 * Transition to READY. 1199 */ 1200 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 1201 nvme_ctrlr_process_init(&ctrlr); 1202 } 1203 1204 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1205 nvme_ctrlr_destruct(&ctrlr); 1206 } 1207 static void 1208 test_nvme_ctrlr_init_en_0_rdy_0_ams_vs(void) 1209 { 1210 DECLARE_AND_CONSTRUCT_CTRLR(); 1211 1212 memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs)); 1213 1214 /* 1215 * Initial state: CC.EN = 0, CSTS.RDY = 0 1216 * init() should set CC.EN = 1. 1217 */ 1218 g_ut_nvme_regs.cc.bits.en = 0; 1219 g_ut_nvme_regs.csts.bits.rdy = 0; 1220 1221 /* 1222 * Default round robin enabled 1223 */ 1224 g_ut_nvme_regs.cap.bits.ams = SPDK_NVME_CAP_AMS_VS; 1225 ctrlr.cap = g_ut_nvme_regs.cap; 1226 1227 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 1228 ctrlr.cdata.nn = 1; 1229 ctrlr.page_size = 0x1000; 1230 /* 1231 * Case 1: default round robin arbitration mechanism selected 1232 */ 1233 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_RR; 1234 1235 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 1236 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 1237 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1238 } 1239 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1240 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 1241 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1242 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 1243 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1244 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 1245 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1246 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 1247 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 1248 CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_RR); 1249 CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_RR); 1250 1251 /* 1252 * Complete and destroy the controller 1253 */ 1254 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1255 nvme_ctrlr_destruct(&ctrlr); 1256 1257 /* 1258 * Reset to initial state 1259 */ 1260 g_ut_nvme_regs.cc.bits.en = 0; 1261 g_ut_nvme_regs.csts.bits.rdy = 0; 1262 1263 /* 1264 * Case 2: weighted round robin arbitration mechanism selected 1265 */ 1266 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 1267 ctrlr.cdata.nn = 1; 1268 ctrlr.page_size = 0x1000; 1269 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_WRR; 1270 1271 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 1272 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 1273 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1274 } 1275 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1276 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 1277 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1278 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 1279 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1280 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 1281 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); 1282 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); 1283 1284 /* 1285 * Complete and destroy the controller 1286 */ 1287 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1288 nvme_ctrlr_destruct(&ctrlr); 1289 1290 /* 1291 * Reset to initial state 1292 */ 1293 g_ut_nvme_regs.cc.bits.en = 0; 1294 g_ut_nvme_regs.csts.bits.rdy = 0; 1295 1296 /* 1297 * Case 3: vendor specific arbitration mechanism selected 1298 */ 1299 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 1300 ctrlr.cdata.nn = 1; 1301 ctrlr.page_size = 0x1000; 1302 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS; 1303 1304 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 1305 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 1306 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1307 } 1308 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1309 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 1310 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1311 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 1312 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1313 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 1314 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1315 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 1316 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 1317 CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_VS); 1318 CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_VS); 1319 1320 /* 1321 * Complete and destroy the controller 1322 */ 1323 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1324 nvme_ctrlr_destruct(&ctrlr); 1325 1326 /* 1327 * Reset to initial state 1328 */ 1329 g_ut_nvme_regs.cc.bits.en = 0; 1330 g_ut_nvme_regs.csts.bits.rdy = 0; 1331 1332 /* 1333 * Case 4: invalid arbitration mechanism selected 1334 */ 1335 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 1336 ctrlr.cdata.nn = 1; 1337 ctrlr.page_size = 0x1000; 1338 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS + 1; 1339 1340 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 1341 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 1342 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1343 } 1344 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1345 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 1346 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1347 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 1348 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1349 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 1350 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) != 0); 1351 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 0); 1352 1353 /* 1354 * Complete and destroy the controller 1355 */ 1356 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1357 nvme_ctrlr_destruct(&ctrlr); 1358 1359 /* 1360 * Reset to initial state 1361 */ 1362 g_ut_nvme_regs.cc.bits.en = 0; 1363 g_ut_nvme_regs.csts.bits.rdy = 0; 1364 1365 /* 1366 * Case 5: reset to vendor specific arbitration mechanism 1367 */ 1368 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 1369 ctrlr.cdata.nn = 1; 1370 ctrlr.page_size = 0x1000; 1371 ctrlr.opts.arb_mechanism = SPDK_NVME_CC_AMS_VS; 1372 1373 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 1374 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 1375 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1376 } 1377 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1378 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 1379 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1380 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 1381 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1382 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 1383 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1384 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 1385 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 1386 CU_ASSERT(g_ut_nvme_regs.cc.bits.ams == SPDK_NVME_CC_AMS_VS); 1387 CU_ASSERT(ctrlr.opts.arb_mechanism == SPDK_NVME_CC_AMS_VS); 1388 1389 /* 1390 * Transition to CSTS.RDY = 1. 1391 */ 1392 g_ut_nvme_regs.csts.bits.rdy = 1; 1393 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1394 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE); 1395 1396 /* 1397 * Transition to READY. 1398 */ 1399 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 1400 nvme_ctrlr_process_init(&ctrlr); 1401 } 1402 1403 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1404 nvme_ctrlr_destruct(&ctrlr); 1405 } 1406 1407 static void 1408 test_nvme_ctrlr_init_en_0_rdy_0(void) 1409 { 1410 DECLARE_AND_CONSTRUCT_CTRLR(); 1411 1412 memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs)); 1413 1414 /* 1415 * Initial state: CC.EN = 0, CSTS.RDY = 0 1416 * init() should set CC.EN = 1. 1417 */ 1418 g_ut_nvme_regs.cc.bits.en = 0; 1419 g_ut_nvme_regs.csts.bits.rdy = 0; 1420 1421 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 1422 ctrlr.cdata.nn = 1; 1423 ctrlr.page_size = 0x1000; 1424 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 1425 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 1426 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1427 } 1428 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1429 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 1430 1431 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1432 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 1433 1434 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1435 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 1436 1437 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1438 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 1439 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 1440 1441 /* 1442 * Transition to CSTS.RDY = 1. 1443 */ 1444 g_ut_nvme_regs.csts.bits.rdy = 1; 1445 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1446 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE); 1447 1448 /* 1449 * Transition to READY. 1450 */ 1451 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 1452 nvme_ctrlr_process_init(&ctrlr); 1453 } 1454 1455 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1456 nvme_ctrlr_destruct(&ctrlr); 1457 } 1458 1459 static void 1460 test_nvme_ctrlr_init_en_0_rdy_1(void) 1461 { 1462 DECLARE_AND_CONSTRUCT_CTRLR(); 1463 1464 memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs)); 1465 1466 /* 1467 * Initial state: CC.EN = 0, CSTS.RDY = 1 1468 */ 1469 g_ut_nvme_regs.cc.bits.en = 0; 1470 g_ut_nvme_regs.csts.bits.rdy = 1; 1471 1472 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 1473 ctrlr.cdata.nn = 1; 1474 ctrlr.page_size = 0x1000; 1475 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 1476 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 1477 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1478 } 1479 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1480 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 1481 1482 /* 1483 * Transition to CSTS.RDY = 0. 1484 */ 1485 g_ut_nvme_regs.csts.bits.rdy = 0; 1486 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1487 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 1488 1489 /* 1490 * Start enabling the controller. 1491 */ 1492 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1493 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 1494 1495 /* 1496 * Transition to CC.EN = 1 1497 */ 1498 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1499 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 1500 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 1501 1502 /* 1503 * Transition to CSTS.RDY = 1. 1504 */ 1505 g_ut_nvme_regs.csts.bits.rdy = 1; 1506 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 1507 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE); 1508 1509 /* 1510 * Transition to READY. 1511 */ 1512 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 1513 nvme_ctrlr_process_init(&ctrlr); 1514 } 1515 1516 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 1517 nvme_ctrlr_destruct(&ctrlr); 1518 } 1519 1520 static void 1521 setup_qpairs(struct spdk_nvme_ctrlr *ctrlr, uint32_t num_io_queues) 1522 { 1523 uint32_t i; 1524 1525 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(ctrlr) == 0); 1526 1527 ctrlr->page_size = 0x1000; 1528 ctrlr->opts.num_io_queues = num_io_queues; 1529 ctrlr->free_io_qids = spdk_bit_array_create(num_io_queues + 1); 1530 ctrlr->state = NVME_CTRLR_STATE_READY; 1531 SPDK_CU_ASSERT_FATAL(ctrlr->free_io_qids != NULL); 1532 1533 spdk_bit_array_clear(ctrlr->free_io_qids, 0); 1534 for (i = 1; i <= num_io_queues; i++) { 1535 spdk_bit_array_set(ctrlr->free_io_qids, i); 1536 } 1537 } 1538 1539 static void 1540 cleanup_qpairs(struct spdk_nvme_ctrlr *ctrlr) 1541 { 1542 nvme_ctrlr_destruct(ctrlr); 1543 } 1544 1545 static void 1546 test_alloc_io_qpair_rr_1(void) 1547 { 1548 struct spdk_nvme_io_qpair_opts opts; 1549 struct spdk_nvme_ctrlr ctrlr = {}; 1550 struct spdk_nvme_qpair *q0; 1551 1552 setup_qpairs(&ctrlr, 1); 1553 1554 /* 1555 * Fake to simulate the controller with default round robin 1556 * arbitration mechanism. 1557 */ 1558 g_ut_nvme_regs.cc.bits.ams = SPDK_NVME_CC_AMS_RR; 1559 1560 spdk_nvme_ctrlr_get_default_io_qpair_opts(&ctrlr, &opts, sizeof(opts)); 1561 1562 q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, NULL, 0); 1563 SPDK_CU_ASSERT_FATAL(q0 != NULL); 1564 SPDK_CU_ASSERT_FATAL(q0->qprio == 0); 1565 /* Only 1 I/O qpair was allocated, so this should fail */ 1566 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, NULL, 0) == NULL); 1567 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q0) == 0); 1568 1569 /* 1570 * Now that the qpair has been returned to the free list, 1571 * we should be able to allocate it again. 1572 */ 1573 q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, NULL, 0); 1574 SPDK_CU_ASSERT_FATAL(q0 != NULL); 1575 SPDK_CU_ASSERT_FATAL(q0->qprio == 0); 1576 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q0) == 0); 1577 1578 /* Only 0 qprio is acceptable for default round robin arbitration mechanism */ 1579 opts.qprio = 1; 1580 q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1581 SPDK_CU_ASSERT_FATAL(q0 == NULL); 1582 1583 opts.qprio = 2; 1584 q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1585 SPDK_CU_ASSERT_FATAL(q0 == NULL); 1586 1587 opts.qprio = 3; 1588 q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1589 SPDK_CU_ASSERT_FATAL(q0 == NULL); 1590 1591 /* Only 0 ~ 3 qprio is acceptable */ 1592 opts.qprio = 4; 1593 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)) == NULL); 1594 opts.qprio = 0; 1595 1596 /* IO qpair can only be created when ctrlr is in READY state */ 1597 ctrlr.state = NVME_CTRLR_STATE_ENABLE; 1598 q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1599 SPDK_CU_ASSERT_FATAL(q0 == NULL); 1600 ctrlr.state = NVME_CTRLR_STATE_READY; 1601 1602 cleanup_qpairs(&ctrlr); 1603 } 1604 1605 static void 1606 test_alloc_io_qpair_wrr_1(void) 1607 { 1608 struct spdk_nvme_io_qpair_opts opts; 1609 struct spdk_nvme_ctrlr ctrlr = {}; 1610 struct spdk_nvme_qpair *q0, *q1; 1611 1612 setup_qpairs(&ctrlr, 2); 1613 1614 /* 1615 * Fake to simulate the controller with weighted round robin 1616 * arbitration mechanism. 1617 */ 1618 ctrlr.process_init_cc.bits.ams = SPDK_NVME_CC_AMS_WRR; 1619 1620 spdk_nvme_ctrlr_get_default_io_qpair_opts(&ctrlr, &opts, sizeof(opts)); 1621 1622 /* 1623 * Allocate 2 qpairs and free them 1624 */ 1625 opts.qprio = 0; 1626 q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1627 SPDK_CU_ASSERT_FATAL(q0 != NULL); 1628 SPDK_CU_ASSERT_FATAL(q0->qprio == 0); 1629 1630 opts.qprio = 1; 1631 q1 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1632 SPDK_CU_ASSERT_FATAL(q1 != NULL); 1633 SPDK_CU_ASSERT_FATAL(q1->qprio == 1); 1634 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q1) == 0); 1635 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q0) == 0); 1636 1637 /* 1638 * Allocate 2 qpairs and free them in the reverse order 1639 */ 1640 opts.qprio = 2; 1641 q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1642 SPDK_CU_ASSERT_FATAL(q0 != NULL); 1643 SPDK_CU_ASSERT_FATAL(q0->qprio == 2); 1644 1645 opts.qprio = 3; 1646 q1 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1647 SPDK_CU_ASSERT_FATAL(q1 != NULL); 1648 SPDK_CU_ASSERT_FATAL(q1->qprio == 3); 1649 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q0) == 0); 1650 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q1) == 0); 1651 1652 /* Only 0 ~ 3 qprio is acceptable */ 1653 opts.qprio = 4; 1654 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)) == NULL); 1655 1656 cleanup_qpairs(&ctrlr); 1657 } 1658 1659 static void 1660 test_alloc_io_qpair_wrr_2(void) 1661 { 1662 struct spdk_nvme_io_qpair_opts opts; 1663 struct spdk_nvme_ctrlr ctrlr = {}; 1664 struct spdk_nvme_qpair *q0, *q1, *q2, *q3; 1665 1666 setup_qpairs(&ctrlr, 4); 1667 1668 /* 1669 * Fake to simulate the controller with weighted round robin 1670 * arbitration mechanism. 1671 */ 1672 ctrlr.process_init_cc.bits.ams = SPDK_NVME_CC_AMS_WRR; 1673 1674 spdk_nvme_ctrlr_get_default_io_qpair_opts(&ctrlr, &opts, sizeof(opts)); 1675 1676 opts.qprio = 0; 1677 q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1678 SPDK_CU_ASSERT_FATAL(q0 != NULL); 1679 SPDK_CU_ASSERT_FATAL(q0->qprio == 0); 1680 1681 opts.qprio = 1; 1682 q1 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1683 SPDK_CU_ASSERT_FATAL(q1 != NULL); 1684 SPDK_CU_ASSERT_FATAL(q1->qprio == 1); 1685 1686 opts.qprio = 2; 1687 q2 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1688 SPDK_CU_ASSERT_FATAL(q2 != NULL); 1689 SPDK_CU_ASSERT_FATAL(q2->qprio == 2); 1690 1691 opts.qprio = 3; 1692 q3 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1693 SPDK_CU_ASSERT_FATAL(q3 != NULL); 1694 SPDK_CU_ASSERT_FATAL(q3->qprio == 3); 1695 1696 /* Only 4 I/O qpairs was allocated, so this should fail */ 1697 opts.qprio = 0; 1698 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)) == NULL); 1699 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q3) == 0); 1700 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q2) == 0); 1701 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q1) == 0); 1702 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q0) == 0); 1703 1704 /* 1705 * Now that the qpair has been returned to the free list, 1706 * we should be able to allocate it again. 1707 * 1708 * Allocate 4 I/O qpairs and half of them with same qprio. 1709 */ 1710 opts.qprio = 1; 1711 q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1712 SPDK_CU_ASSERT_FATAL(q0 != NULL); 1713 SPDK_CU_ASSERT_FATAL(q0->qprio == 1); 1714 1715 opts.qprio = 1; 1716 q1 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1717 SPDK_CU_ASSERT_FATAL(q1 != NULL); 1718 SPDK_CU_ASSERT_FATAL(q1->qprio == 1); 1719 1720 opts.qprio = 3; 1721 q2 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1722 SPDK_CU_ASSERT_FATAL(q2 != NULL); 1723 SPDK_CU_ASSERT_FATAL(q2->qprio == 3); 1724 1725 opts.qprio = 3; 1726 q3 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, &opts, sizeof(opts)); 1727 SPDK_CU_ASSERT_FATAL(q3 != NULL); 1728 SPDK_CU_ASSERT_FATAL(q3->qprio == 3); 1729 1730 /* 1731 * Free all I/O qpairs in reverse order 1732 */ 1733 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q0) == 0); 1734 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q1) == 0); 1735 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q2) == 0); 1736 SPDK_CU_ASSERT_FATAL(spdk_nvme_ctrlr_free_io_qpair(q3) == 0); 1737 1738 cleanup_qpairs(&ctrlr); 1739 } 1740 1741 bool g_connect_qpair_called = false; 1742 int g_connect_qpair_return_code = 0; 1743 int 1744 nvme_transport_ctrlr_connect_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair) 1745 { 1746 g_connect_qpair_called = true; 1747 qpair->state = NVME_QPAIR_CONNECTED; 1748 return g_connect_qpair_return_code; 1749 } 1750 1751 static void 1752 test_spdk_nvme_ctrlr_reconnect_io_qpair(void) 1753 { 1754 struct spdk_nvme_ctrlr ctrlr = {}; 1755 struct spdk_nvme_qpair qpair = {}; 1756 int rc; 1757 1758 CU_ASSERT(pthread_mutex_init(&ctrlr.ctrlr_lock, NULL) == 0); 1759 1760 /* Various states of controller disconnect. */ 1761 qpair.id = 1; 1762 qpair.ctrlr = &ctrlr; 1763 ctrlr.is_removed = 1; 1764 ctrlr.is_failed = 0; 1765 ctrlr.is_resetting = 0; 1766 rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair); 1767 CU_ASSERT(rc == -ENODEV) 1768 1769 ctrlr.is_removed = 0; 1770 ctrlr.is_failed = 1; 1771 rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair); 1772 CU_ASSERT(rc == -ENXIO) 1773 1774 ctrlr.is_failed = 0; 1775 ctrlr.is_resetting = 1; 1776 rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair); 1777 CU_ASSERT(rc == -EAGAIN) 1778 1779 /* Confirm precedence for controller states: removed > resetting > failed */ 1780 ctrlr.is_removed = 1; 1781 ctrlr.is_failed = 1; 1782 rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair); 1783 CU_ASSERT(rc == -ENODEV) 1784 1785 ctrlr.is_removed = 0; 1786 rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair); 1787 CU_ASSERT(rc == -EAGAIN) 1788 1789 ctrlr.is_resetting = 0; 1790 rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair); 1791 CU_ASSERT(rc == -ENXIO) 1792 1793 /* qpair not failed. Make sure we don't call down to the transport */ 1794 ctrlr.is_failed = 0; 1795 qpair.state = NVME_QPAIR_CONNECTED; 1796 g_connect_qpair_called = false; 1797 rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair); 1798 CU_ASSERT(g_connect_qpair_called == false); 1799 CU_ASSERT(rc == 0) 1800 1801 /* transport qpair is failed. make sure we call down to the transport */ 1802 qpair.state = NVME_QPAIR_DISCONNECTED; 1803 rc = spdk_nvme_ctrlr_reconnect_io_qpair(&qpair); 1804 CU_ASSERT(g_connect_qpair_called == true); 1805 CU_ASSERT(rc == 0) 1806 1807 CU_ASSERT(pthread_mutex_destroy(&ctrlr.ctrlr_lock) == 0); 1808 } 1809 1810 static void 1811 test_nvme_ctrlr_fail(void) 1812 { 1813 struct spdk_nvme_ctrlr ctrlr = {}; 1814 1815 ctrlr.opts.num_io_queues = 0; 1816 nvme_ctrlr_fail(&ctrlr, false); 1817 1818 CU_ASSERT(ctrlr.is_failed == true); 1819 } 1820 1821 static void 1822 test_nvme_ctrlr_construct_intel_support_log_page_list(void) 1823 { 1824 bool res; 1825 struct spdk_nvme_ctrlr ctrlr = {}; 1826 struct spdk_nvme_intel_log_page_directory payload = {}; 1827 struct spdk_pci_id pci_id = {}; 1828 1829 /* Get quirks for a device with all 0 vendor/device id */ 1830 ctrlr.quirks = nvme_get_quirks(&pci_id); 1831 CU_ASSERT(ctrlr.quirks == 0); 1832 1833 /* Set the vendor to Intel, but provide no device id */ 1834 pci_id.class_id = SPDK_PCI_CLASS_NVME; 1835 ctrlr.cdata.vid = pci_id.vendor_id = SPDK_PCI_VID_INTEL; 1836 payload.temperature_statistics_log_len = 1; 1837 ctrlr.quirks = nvme_get_quirks(&pci_id); 1838 memset(ctrlr.log_page_supported, 0, sizeof(ctrlr.log_page_supported)); 1839 1840 nvme_ctrlr_construct_intel_support_log_page_list(&ctrlr, &payload); 1841 res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY); 1842 CU_ASSERT(res == true); 1843 res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_TEMPERATURE); 1844 CU_ASSERT(res == true); 1845 res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY); 1846 CU_ASSERT(res == false); 1847 res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_SMART); 1848 CU_ASSERT(res == false); 1849 1850 /* set valid vendor id, device id and sub device id */ 1851 ctrlr.cdata.vid = SPDK_PCI_VID_INTEL; 1852 payload.temperature_statistics_log_len = 0; 1853 pci_id.vendor_id = SPDK_PCI_VID_INTEL; 1854 pci_id.device_id = 0x0953; 1855 pci_id.subvendor_id = SPDK_PCI_VID_INTEL; 1856 pci_id.subdevice_id = 0x3702; 1857 ctrlr.quirks = nvme_get_quirks(&pci_id); 1858 memset(ctrlr.log_page_supported, 0, sizeof(ctrlr.log_page_supported)); 1859 1860 nvme_ctrlr_construct_intel_support_log_page_list(&ctrlr, &payload); 1861 res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY); 1862 CU_ASSERT(res == true); 1863 res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_TEMPERATURE); 1864 CU_ASSERT(res == false); 1865 res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY); 1866 CU_ASSERT(res == true); 1867 res = spdk_nvme_ctrlr_is_log_page_supported(&ctrlr, SPDK_NVME_INTEL_LOG_SMART); 1868 CU_ASSERT(res == false); 1869 } 1870 1871 static void 1872 test_nvme_ctrlr_set_supported_features(void) 1873 { 1874 bool res; 1875 struct spdk_nvme_ctrlr ctrlr = {}; 1876 1877 /* set a invalid vendor id */ 1878 ctrlr.cdata.vid = 0xFFFF; 1879 nvme_ctrlr_set_supported_features(&ctrlr); 1880 res = spdk_nvme_ctrlr_is_feature_supported(&ctrlr, SPDK_NVME_FEAT_ARBITRATION); 1881 CU_ASSERT(res == true); 1882 res = spdk_nvme_ctrlr_is_feature_supported(&ctrlr, SPDK_NVME_INTEL_FEAT_MAX_LBA); 1883 CU_ASSERT(res == false); 1884 1885 ctrlr.cdata.vid = SPDK_PCI_VID_INTEL; 1886 nvme_ctrlr_set_supported_features(&ctrlr); 1887 res = spdk_nvme_ctrlr_is_feature_supported(&ctrlr, SPDK_NVME_FEAT_ARBITRATION); 1888 CU_ASSERT(res == true); 1889 res = spdk_nvme_ctrlr_is_feature_supported(&ctrlr, SPDK_NVME_INTEL_FEAT_MAX_LBA); 1890 CU_ASSERT(res == true); 1891 } 1892 1893 static void 1894 test_ctrlr_get_default_ctrlr_opts(void) 1895 { 1896 struct spdk_nvme_ctrlr_opts opts = {}; 1897 1898 CU_ASSERT(spdk_uuid_parse(&g_spdk_nvme_driver->default_extended_host_id, 1899 "e53e9258-c93b-48b5-be1a-f025af6d232a") == 0); 1900 1901 memset(&opts, 0, sizeof(opts)); 1902 1903 /* set a smaller opts_size */ 1904 CU_ASSERT(sizeof(opts) > 8); 1905 spdk_nvme_ctrlr_get_default_ctrlr_opts(&opts, 8); 1906 CU_ASSERT_EQUAL(opts.num_io_queues, DEFAULT_MAX_IO_QUEUES); 1907 CU_ASSERT_FALSE(opts.use_cmb_sqs); 1908 /* check below fields are not initialized by default value */ 1909 CU_ASSERT_EQUAL(opts.arb_mechanism, 0); 1910 CU_ASSERT_EQUAL(opts.keep_alive_timeout_ms, 0); 1911 CU_ASSERT_EQUAL(opts.io_queue_size, 0); 1912 CU_ASSERT_EQUAL(opts.io_queue_requests, 0); 1913 for (int i = 0; i < 8; i++) { 1914 CU_ASSERT(opts.host_id[i] == 0); 1915 } 1916 for (int i = 0; i < 16; i++) { 1917 CU_ASSERT(opts.extended_host_id[i] == 0); 1918 } 1919 CU_ASSERT(strlen(opts.hostnqn) == 0); 1920 CU_ASSERT(strlen(opts.src_addr) == 0); 1921 CU_ASSERT(strlen(opts.src_svcid) == 0); 1922 CU_ASSERT_EQUAL(opts.admin_timeout_ms, 0); 1923 1924 /* set a consistent opts_size */ 1925 spdk_nvme_ctrlr_get_default_ctrlr_opts(&opts, sizeof(opts)); 1926 CU_ASSERT_EQUAL(opts.num_io_queues, DEFAULT_MAX_IO_QUEUES); 1927 CU_ASSERT_FALSE(opts.use_cmb_sqs); 1928 CU_ASSERT_EQUAL(opts.arb_mechanism, SPDK_NVME_CC_AMS_RR); 1929 CU_ASSERT_EQUAL(opts.keep_alive_timeout_ms, 10 * 1000); 1930 CU_ASSERT_EQUAL(opts.io_queue_size, DEFAULT_IO_QUEUE_SIZE); 1931 CU_ASSERT_EQUAL(opts.io_queue_requests, DEFAULT_IO_QUEUE_REQUESTS); 1932 for (int i = 0; i < 8; i++) { 1933 CU_ASSERT(opts.host_id[i] == 0); 1934 } 1935 CU_ASSERT_STRING_EQUAL(opts.hostnqn, 1936 "nqn.2014-08.org.nvmexpress:uuid:e53e9258-c93b-48b5-be1a-f025af6d232a"); 1937 CU_ASSERT(memcmp(opts.extended_host_id, &g_spdk_nvme_driver->default_extended_host_id, 1938 sizeof(opts.extended_host_id)) == 0); 1939 CU_ASSERT(strlen(opts.src_addr) == 0); 1940 CU_ASSERT(strlen(opts.src_svcid) == 0); 1941 CU_ASSERT_EQUAL(opts.admin_timeout_ms, NVME_MAX_ADMIN_TIMEOUT_IN_SECS * 1000); 1942 } 1943 1944 static void 1945 test_ctrlr_get_default_io_qpair_opts(void) 1946 { 1947 struct spdk_nvme_ctrlr ctrlr = {}; 1948 struct spdk_nvme_io_qpair_opts opts = {}; 1949 1950 memset(&opts, 0, sizeof(opts)); 1951 1952 /* set a smaller opts_size */ 1953 ctrlr.opts.io_queue_size = DEFAULT_IO_QUEUE_SIZE; 1954 CU_ASSERT(sizeof(opts) > 8); 1955 spdk_nvme_ctrlr_get_default_io_qpair_opts(&ctrlr, &opts, 8); 1956 CU_ASSERT_EQUAL(opts.qprio, SPDK_NVME_QPRIO_URGENT); 1957 CU_ASSERT_EQUAL(opts.io_queue_size, DEFAULT_IO_QUEUE_SIZE); 1958 /* check below field is not initialized by default value */ 1959 CU_ASSERT_EQUAL(opts.io_queue_requests, 0); 1960 1961 /* set a consistent opts_size */ 1962 ctrlr.opts.io_queue_size = DEFAULT_IO_QUEUE_SIZE; 1963 ctrlr.opts.io_queue_requests = DEFAULT_IO_QUEUE_REQUESTS; 1964 spdk_nvme_ctrlr_get_default_io_qpair_opts(&ctrlr, &opts, sizeof(opts)); 1965 CU_ASSERT_EQUAL(opts.qprio, SPDK_NVME_QPRIO_URGENT); 1966 CU_ASSERT_EQUAL(opts.io_queue_size, DEFAULT_IO_QUEUE_SIZE); 1967 CU_ASSERT_EQUAL(opts.io_queue_requests, DEFAULT_IO_QUEUE_REQUESTS); 1968 } 1969 1970 #if 0 /* TODO: move to PCIe-specific unit test */ 1971 static void 1972 test_nvme_ctrlr_alloc_cmb(void) 1973 { 1974 int rc; 1975 uint64_t offset; 1976 struct spdk_nvme_ctrlr ctrlr = {}; 1977 1978 ctrlr.cmb_size = 0x1000000; 1979 ctrlr.cmb_current_offset = 0x100; 1980 rc = nvme_ctrlr_alloc_cmb(&ctrlr, 0x200, 0x1000, &offset); 1981 CU_ASSERT(rc == 0); 1982 CU_ASSERT(offset == 0x1000); 1983 CU_ASSERT(ctrlr.cmb_current_offset == 0x1200); 1984 1985 rc = nvme_ctrlr_alloc_cmb(&ctrlr, 0x800, 0x1000, &offset); 1986 CU_ASSERT(rc == 0); 1987 CU_ASSERT(offset == 0x2000); 1988 CU_ASSERT(ctrlr.cmb_current_offset == 0x2800); 1989 1990 rc = nvme_ctrlr_alloc_cmb(&ctrlr, 0x800000, 0x100000, &offset); 1991 CU_ASSERT(rc == 0); 1992 CU_ASSERT(offset == 0x100000); 1993 CU_ASSERT(ctrlr.cmb_current_offset == 0x900000); 1994 1995 rc = nvme_ctrlr_alloc_cmb(&ctrlr, 0x8000000, 0x1000, &offset); 1996 CU_ASSERT(rc == -1); 1997 } 1998 #endif 1999 2000 static void 2001 test_spdk_nvme_ctrlr_update_firmware(void) 2002 { 2003 struct spdk_nvme_ctrlr ctrlr = {}; 2004 void *payload = NULL; 2005 int point_payload = 1; 2006 int slot = 0; 2007 int ret = 0; 2008 struct spdk_nvme_status status; 2009 enum spdk_nvme_fw_commit_action commit_action = SPDK_NVME_FW_COMMIT_REPLACE_IMG; 2010 2011 CU_ASSERT(pthread_mutex_init(&ctrlr.ctrlr_lock, NULL) == 0); 2012 2013 /* Set invalid size check function return value */ 2014 set_size = 5; 2015 ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status); 2016 CU_ASSERT(ret == -1); 2017 2018 /* When payload is NULL but set_size < min_page_size */ 2019 set_size = 4; 2020 ctrlr.min_page_size = 5; 2021 ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status); 2022 CU_ASSERT(ret == -1); 2023 2024 /* When payload not NULL but min_page_size is 0 */ 2025 set_size = 4; 2026 ctrlr.min_page_size = 0; 2027 payload = &point_payload; 2028 ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status); 2029 CU_ASSERT(ret == -1); 2030 2031 /* Check firmware image download when payload not NULL and min_page_size not 0 , status.cpl value is 1 */ 2032 set_status_cpl = 1; 2033 set_size = 4; 2034 ctrlr.min_page_size = 5; 2035 payload = &point_payload; 2036 ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status); 2037 CU_ASSERT(ret == -ENXIO); 2038 2039 /* Check firmware image download and set status.cpl value is 0 */ 2040 set_status_cpl = 0; 2041 set_size = 4; 2042 ctrlr.min_page_size = 5; 2043 payload = &point_payload; 2044 ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status); 2045 CU_ASSERT(ret == -1); 2046 2047 /* Check firmware commit */ 2048 ctrlr.is_resetting = false; 2049 set_status_cpl = 0; 2050 slot = 1; 2051 set_size = 4; 2052 ctrlr.min_page_size = 5; 2053 payload = &point_payload; 2054 ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status); 2055 CU_ASSERT(ret == -ENXIO); 2056 2057 /* Set size check firmware download and firmware commit */ 2058 ctrlr.is_resetting = true; 2059 set_status_cpl = 0; 2060 slot = 1; 2061 set_size = 4; 2062 ctrlr.min_page_size = 5; 2063 payload = &point_payload; 2064 ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status); 2065 CU_ASSERT(ret == 0); 2066 2067 /* nvme_wait_for_completion returns an error */ 2068 g_wait_for_completion_return_val = -1; 2069 ret = spdk_nvme_ctrlr_update_firmware(&ctrlr, payload, set_size, slot, commit_action, &status); 2070 CU_ASSERT(ret == -ENXIO); 2071 CU_ASSERT(g_failed_status != NULL); 2072 CU_ASSERT(g_failed_status->timed_out == true); 2073 /* status should be freed by callback, which is not triggered in test env. 2074 Store status to global variable and free it manually. 2075 If spdk_nvme_ctrlr_update_firmware changes its behaviour and frees the status 2076 itself, we'll get a double free here.. */ 2077 free(g_failed_status); 2078 g_failed_status = NULL; 2079 g_wait_for_completion_return_val = 0; 2080 2081 CU_ASSERT(pthread_mutex_destroy(&ctrlr.ctrlr_lock) == 0); 2082 set_status_cpl = 0; 2083 } 2084 2085 int 2086 nvme_ctrlr_cmd_doorbell_buffer_config(struct spdk_nvme_ctrlr *ctrlr, uint64_t prp1, uint64_t prp2, 2087 spdk_nvme_cmd_cb cb_fn, void *cb_arg) 2088 { 2089 fake_cpl_sc(cb_fn, cb_arg); 2090 return 0; 2091 } 2092 2093 static void 2094 test_spdk_nvme_ctrlr_doorbell_buffer_config(void) 2095 { 2096 struct spdk_nvme_ctrlr ctrlr = {}; 2097 int ret = -1; 2098 2099 ctrlr.cdata.oacs.doorbell_buffer_config = 1; 2100 ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_PCIE; 2101 ctrlr.page_size = 0x1000; 2102 MOCK_CLEAR(spdk_malloc); 2103 MOCK_CLEAR(spdk_zmalloc); 2104 ret = nvme_ctrlr_set_doorbell_buffer_config(&ctrlr); 2105 CU_ASSERT(ret == 0); 2106 nvme_ctrlr_free_doorbell_buffer(&ctrlr); 2107 } 2108 2109 static void 2110 test_nvme_ctrlr_test_active_ns(void) 2111 { 2112 uint32_t nsid, minor; 2113 size_t ns_id_count; 2114 struct spdk_nvme_ctrlr ctrlr = {}; 2115 uint32_t active_ns_list[1531]; 2116 2117 for (nsid = 1; nsid <= 1531; nsid++) { 2118 active_ns_list[nsid - 1] = nsid; 2119 } 2120 2121 g_active_ns_list = active_ns_list; 2122 2123 ctrlr.page_size = 0x1000; 2124 2125 for (minor = 0; minor <= 2; minor++) { 2126 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2127 ctrlr.state = NVME_CTRLR_STATE_READY; 2128 2129 ctrlr.vs.bits.mjr = 1; 2130 ctrlr.vs.bits.mnr = minor; 2131 ctrlr.vs.bits.ter = 0; 2132 ctrlr.cdata.nn = 1531; 2133 2134 RB_INIT(&ctrlr.ns); 2135 2136 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list); 2137 nvme_ctrlr_identify_active_ns(&ctrlr); 2138 2139 for (nsid = 1; nsid <= ctrlr.cdata.nn; nsid++) { 2140 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, nsid) == true); 2141 } 2142 2143 for (; nsid <= 1559; nsid++) { 2144 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, nsid) == false); 2145 } 2146 2147 g_active_ns_list_length = 0; 2148 if (minor <= 1) { 2149 ctrlr.cdata.nn = 0; 2150 } 2151 nvme_ctrlr_identify_active_ns(&ctrlr); 2152 CU_ASSERT(spdk_nvme_ctrlr_get_first_active_ns(&ctrlr) == 0); 2153 2154 g_active_ns_list_length = 1; 2155 if (minor <= 1) { 2156 ctrlr.cdata.nn = 1; 2157 } 2158 nvme_ctrlr_identify_active_ns(&ctrlr); 2159 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1) == true); 2160 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 2) == false); 2161 nsid = spdk_nvme_ctrlr_get_first_active_ns(&ctrlr); 2162 CU_ASSERT(nsid == 1); 2163 2164 if (minor >= 2) { 2165 /* For NVMe 1.2 and newer, the namespace list can have "holes" where 2166 * some namespaces are not active. Test this. */ 2167 g_active_ns_list_length = 2; 2168 g_active_ns_list[1] = 3; 2169 nvme_ctrlr_identify_active_ns(&ctrlr); 2170 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1) == true); 2171 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 2) == false); 2172 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 3) == true); 2173 nsid = spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, nsid); 2174 CU_ASSERT(nsid == 3); 2175 nsid = spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, nsid); 2176 CU_ASSERT(nsid == 0); 2177 2178 /* Reset the active namespace list array */ 2179 g_active_ns_list[1] = 2; 2180 } 2181 2182 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list); 2183 if (minor <= 1) { 2184 ctrlr.cdata.nn = 1531; 2185 } 2186 nvme_ctrlr_identify_active_ns(&ctrlr); 2187 2188 ns_id_count = 0; 2189 for (nsid = spdk_nvme_ctrlr_get_first_active_ns(&ctrlr); 2190 nsid != 0; nsid = spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, nsid)) { 2191 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, nsid) == true); 2192 ns_id_count++; 2193 } 2194 CU_ASSERT(ns_id_count == ctrlr.cdata.nn); 2195 2196 nvme_ctrlr_destruct(&ctrlr); 2197 } 2198 2199 g_active_ns_list = NULL; 2200 g_active_ns_list_length = 0; 2201 } 2202 2203 static void 2204 test_nvme_ctrlr_test_active_ns_error_case(void) 2205 { 2206 int rc; 2207 struct spdk_nvme_ctrlr ctrlr = {.state = NVME_CTRLR_STATE_READY}; 2208 2209 ctrlr.page_size = 0x1000; 2210 ctrlr.vs.bits.mjr = 1; 2211 ctrlr.vs.bits.mnr = 2; 2212 ctrlr.vs.bits.ter = 0; 2213 ctrlr.cdata.nn = 2; 2214 2215 set_status_code = SPDK_NVME_SC_INVALID_FIELD; 2216 rc = nvme_ctrlr_identify_active_ns(&ctrlr); 2217 CU_ASSERT(rc == -ENXIO); 2218 set_status_code = SPDK_NVME_SC_SUCCESS; 2219 } 2220 2221 static void 2222 test_nvme_ctrlr_init_delay(void) 2223 { 2224 DECLARE_AND_CONSTRUCT_CTRLR(); 2225 2226 memset(&g_ut_nvme_regs, 0, sizeof(g_ut_nvme_regs)); 2227 2228 /* 2229 * Initial state: CC.EN = 0, CSTS.RDY = 0 2230 * init() should set CC.EN = 1. 2231 */ 2232 g_ut_nvme_regs.cc.bits.en = 0; 2233 g_ut_nvme_regs.csts.bits.rdy = 0; 2234 2235 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2236 /* Test that the initialization delay works correctly. We only 2237 * do the initialization delay on SSDs that require it, so 2238 * set that quirk here. 2239 */ 2240 ctrlr.quirks = NVME_QUIRK_DELAY_BEFORE_INIT; 2241 ctrlr.cdata.nn = 1; 2242 ctrlr.page_size = 0x1000; 2243 ctrlr.state = NVME_CTRLR_STATE_INIT_DELAY; 2244 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2245 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 2246 CU_ASSERT(ctrlr.sleep_timeout_tsc != 0); 2247 2248 /* delay 1s, just return as sleep time isn't enough */ 2249 spdk_delay_us(1 * spdk_get_ticks_hz()); 2250 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2251 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_INIT); 2252 CU_ASSERT(ctrlr.sleep_timeout_tsc != 0); 2253 2254 /* sleep timeout, start to initialize */ 2255 spdk_delay_us(2 * spdk_get_ticks_hz()); 2256 while (ctrlr.state != NVME_CTRLR_STATE_CHECK_EN) { 2257 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2258 } 2259 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2260 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0); 2261 2262 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2263 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_DISABLED); 2264 2265 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2266 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE); 2267 2268 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2269 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1); 2270 CU_ASSERT(g_ut_nvme_regs.cc.bits.en == 1); 2271 2272 /* 2273 * Transition to CSTS.RDY = 1. 2274 */ 2275 g_ut_nvme_regs.csts.bits.rdy = 1; 2276 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2277 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_RESET_ADMIN_QUEUE); 2278 2279 /* 2280 * Transition to READY. 2281 */ 2282 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 2283 nvme_ctrlr_process_init(&ctrlr); 2284 } 2285 2286 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 2287 nvme_ctrlr_destruct(&ctrlr); 2288 } 2289 2290 static void 2291 test_spdk_nvme_ctrlr_set_trid(void) 2292 { 2293 struct spdk_nvme_ctrlr ctrlr = {{0}}; 2294 struct spdk_nvme_transport_id new_trid = {{0}}; 2295 2296 CU_ASSERT(pthread_mutex_init(&ctrlr.ctrlr_lock, NULL) == 0); 2297 2298 ctrlr.is_failed = false; 2299 ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_RDMA; 2300 snprintf(ctrlr.trid.subnqn, SPDK_NVMF_NQN_MAX_LEN, "%s", "nqn.2016-06.io.spdk:cnode1"); 2301 snprintf(ctrlr.trid.traddr, SPDK_NVMF_TRADDR_MAX_LEN, "%s", "192.168.100.8"); 2302 snprintf(ctrlr.trid.trsvcid, SPDK_NVMF_TRSVCID_MAX_LEN, "%s", "4420"); 2303 CU_ASSERT(spdk_nvme_ctrlr_set_trid(&ctrlr, &new_trid) == -EPERM); 2304 2305 ctrlr.is_failed = true; 2306 new_trid.trtype = SPDK_NVME_TRANSPORT_TCP; 2307 CU_ASSERT(spdk_nvme_ctrlr_set_trid(&ctrlr, &new_trid) == -EINVAL); 2308 CU_ASSERT(ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_RDMA); 2309 2310 new_trid.trtype = SPDK_NVME_TRANSPORT_RDMA; 2311 snprintf(new_trid.subnqn, SPDK_NVMF_NQN_MAX_LEN, "%s", "nqn.2016-06.io.spdk:cnode2"); 2312 CU_ASSERT(spdk_nvme_ctrlr_set_trid(&ctrlr, &new_trid) == -EINVAL); 2313 CU_ASSERT(strncmp(ctrlr.trid.subnqn, "nqn.2016-06.io.spdk:cnode1", SPDK_NVMF_NQN_MAX_LEN) == 0); 2314 2315 2316 snprintf(new_trid.subnqn, SPDK_NVMF_NQN_MAX_LEN, "%s", "nqn.2016-06.io.spdk:cnode1"); 2317 snprintf(new_trid.traddr, SPDK_NVMF_TRADDR_MAX_LEN, "%s", "192.168.100.9"); 2318 snprintf(new_trid.trsvcid, SPDK_NVMF_TRSVCID_MAX_LEN, "%s", "4421"); 2319 CU_ASSERT(spdk_nvme_ctrlr_set_trid(&ctrlr, &new_trid) == 0); 2320 CU_ASSERT(strncmp(ctrlr.trid.traddr, "192.168.100.9", SPDK_NVMF_TRADDR_MAX_LEN) == 0); 2321 CU_ASSERT(strncmp(ctrlr.trid.trsvcid, "4421", SPDK_NVMF_TRSVCID_MAX_LEN) == 0); 2322 2323 CU_ASSERT(pthread_mutex_destroy(&ctrlr.ctrlr_lock) == 0); 2324 } 2325 2326 static void 2327 test_nvme_ctrlr_init_set_nvmf_ioccsz(void) 2328 { 2329 struct spdk_nvme_ctrlr_data cdata = {}; 2330 DECLARE_AND_CONSTRUCT_CTRLR(); 2331 /* equivalent of 4096 bytes */ 2332 cdata.nvmf_specific.ioccsz = 260; 2333 cdata.nvmf_specific.icdoff = 1; 2334 g_cdata = &cdata; 2335 2336 /* Check PCI trtype, */ 2337 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2338 ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_PCIE; 2339 2340 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY; 2341 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2342 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER); 2343 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2344 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT); 2345 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2346 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC); 2347 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2348 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES); 2349 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2350 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS); 2351 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2352 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS); 2353 2354 CU_ASSERT(ctrlr.ioccsz_bytes == 0); 2355 CU_ASSERT(ctrlr.icdoff == 0); 2356 2357 nvme_ctrlr_destruct(&ctrlr); 2358 2359 /* Check RDMA trtype, */ 2360 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2361 ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_RDMA; 2362 2363 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY; 2364 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2365 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER); 2366 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2367 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT); 2368 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2369 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC); 2370 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2371 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES); 2372 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2373 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS); 2374 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2375 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS); 2376 2377 CU_ASSERT(ctrlr.ioccsz_bytes == 4096); 2378 CU_ASSERT(ctrlr.icdoff == 1); 2379 ctrlr.ioccsz_bytes = 0; 2380 ctrlr.icdoff = 0; 2381 2382 nvme_ctrlr_destruct(&ctrlr); 2383 2384 /* Check TCP trtype, */ 2385 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2386 ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_TCP; 2387 2388 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY; 2389 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2390 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER); 2391 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2392 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT); 2393 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2394 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC); 2395 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2396 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES); 2397 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2398 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS); 2399 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2400 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS); 2401 2402 CU_ASSERT(ctrlr.ioccsz_bytes == 4096); 2403 CU_ASSERT(ctrlr.icdoff == 1); 2404 ctrlr.ioccsz_bytes = 0; 2405 ctrlr.icdoff = 0; 2406 2407 nvme_ctrlr_destruct(&ctrlr); 2408 2409 /* Check FC trtype, */ 2410 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2411 ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_FC; 2412 2413 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY; 2414 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2415 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER); 2416 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2417 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT); 2418 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2419 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC); 2420 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2421 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES); 2422 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2423 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS); 2424 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2425 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS); 2426 2427 CU_ASSERT(ctrlr.ioccsz_bytes == 4096); 2428 CU_ASSERT(ctrlr.icdoff == 1); 2429 ctrlr.ioccsz_bytes = 0; 2430 ctrlr.icdoff = 0; 2431 2432 nvme_ctrlr_destruct(&ctrlr); 2433 2434 /* Check CUSTOM trtype, */ 2435 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2436 ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_CUSTOM; 2437 2438 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY; 2439 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2440 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER); 2441 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2442 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT); 2443 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2444 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC); 2445 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2446 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES); 2447 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2448 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS); 2449 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2450 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS); 2451 2452 CU_ASSERT(ctrlr.ioccsz_bytes == 0); 2453 CU_ASSERT(ctrlr.icdoff == 0); 2454 2455 nvme_ctrlr_destruct(&ctrlr); 2456 2457 g_cdata = NULL; 2458 } 2459 2460 static void 2461 test_nvme_ctrlr_init_set_num_queues(void) 2462 { 2463 DECLARE_AND_CONSTRUCT_CTRLR(); 2464 2465 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2466 2467 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY; 2468 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2469 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_CONFIGURE_AER); 2470 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2471 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT); 2472 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2473 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC); 2474 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 2475 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_NUM_QUEUES); 2476 2477 ctrlr.opts.num_io_queues = 64; 2478 /* Num queues is zero-based. So, use 31 to get 32 queues */ 2479 fake_cpl.cdw0 = 31 + (31 << 16); 2480 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); /* -> IDENTIFY_ACTIVE_NS */ 2481 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS); 2482 CU_ASSERT(ctrlr.opts.num_io_queues == 32); 2483 fake_cpl.cdw0 = 0; 2484 2485 nvme_ctrlr_destruct(&ctrlr); 2486 } 2487 2488 static void 2489 test_nvme_ctrlr_init_set_keep_alive_timeout(void) 2490 { 2491 DECLARE_AND_CONSTRUCT_CTRLR(); 2492 2493 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2494 2495 ctrlr.opts.keep_alive_timeout_ms = 60000; 2496 ctrlr.cdata.kas = 1; 2497 ctrlr.state = NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT; 2498 fake_cpl.cdw0 = 120000; 2499 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); /* -> IDENTIFY_IOCS_SPECIFIC */ 2500 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC); 2501 CU_ASSERT(ctrlr.opts.keep_alive_timeout_ms == 120000); 2502 fake_cpl.cdw0 = 0; 2503 2504 /* Target does not support Get Feature "Keep Alive Timer" */ 2505 ctrlr.opts.keep_alive_timeout_ms = 60000; 2506 ctrlr.cdata.kas = 1; 2507 ctrlr.state = NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT; 2508 set_status_code = SPDK_NVME_SC_INVALID_FIELD; 2509 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); /* -> IDENTIFY_IOCS_SPECIFIC */ 2510 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC); 2511 CU_ASSERT(ctrlr.opts.keep_alive_timeout_ms == 60000); 2512 set_status_code = SPDK_NVME_SC_SUCCESS; 2513 2514 /* Target fails Get Feature "Keep Alive Timer" for another reason */ 2515 ctrlr.opts.keep_alive_timeout_ms = 60000; 2516 ctrlr.cdata.kas = 1; 2517 ctrlr.state = NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT; 2518 set_status_code = SPDK_NVME_SC_INTERNAL_DEVICE_ERROR; 2519 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); /* -> ERROR */ 2520 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ERROR); 2521 set_status_code = SPDK_NVME_SC_SUCCESS; 2522 2523 nvme_ctrlr_destruct(&ctrlr); 2524 } 2525 2526 static void 2527 test_alloc_io_qpair_fail(void) 2528 { 2529 struct spdk_nvme_ctrlr ctrlr = {}; 2530 struct spdk_nvme_qpair *q0; 2531 2532 setup_qpairs(&ctrlr, 1); 2533 2534 /* Modify the connect_qpair return code to inject a failure */ 2535 g_connect_qpair_return_code = 1; 2536 2537 /* Attempt to allocate a qpair, this should fail */ 2538 q0 = spdk_nvme_ctrlr_alloc_io_qpair(&ctrlr, NULL, 0); 2539 SPDK_CU_ASSERT_FATAL(q0 == NULL); 2540 2541 /* Verify that the qpair is removed from the lists */ 2542 SPDK_CU_ASSERT_FATAL(TAILQ_EMPTY(&ctrlr.active_io_qpairs)); 2543 2544 g_connect_qpair_return_code = 0; 2545 cleanup_qpairs(&ctrlr); 2546 } 2547 2548 static void 2549 test_nvme_ctrlr_add_remove_process(void) 2550 { 2551 struct spdk_nvme_ctrlr ctrlr = {}; 2552 void *devhandle = (void *)0xDEADBEEF; 2553 struct spdk_nvme_ctrlr_process *proc = NULL; 2554 int rc; 2555 2556 ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_PCIE; 2557 TAILQ_INIT(&ctrlr.active_procs); 2558 2559 rc = nvme_ctrlr_add_process(&ctrlr, devhandle); 2560 CU_ASSERT(rc == 0); 2561 proc = TAILQ_FIRST(&ctrlr.active_procs); 2562 SPDK_CU_ASSERT_FATAL(proc != NULL); 2563 CU_ASSERT(proc->is_primary == true); 2564 CU_ASSERT(proc->pid == getpid()); 2565 CU_ASSERT(proc->devhandle == (void *)0xDEADBEEF); 2566 CU_ASSERT(proc->ref == 0); 2567 2568 nvme_ctrlr_remove_process(&ctrlr, proc); 2569 CU_ASSERT(TAILQ_EMPTY(&ctrlr.active_procs)); 2570 } 2571 2572 static void 2573 test_nvme_ctrlr_set_arbitration_feature(void) 2574 { 2575 struct spdk_nvme_ctrlr ctrlr = {}; 2576 2577 ctrlr.opts.arbitration_burst = 6; 2578 ctrlr.flags |= SPDK_NVME_CTRLR_WRR_SUPPORTED; 2579 ctrlr.opts.low_priority_weight = 1; 2580 ctrlr.opts.medium_priority_weight = 2; 2581 ctrlr.opts.high_priority_weight = 3; 2582 /* g_ut_cdw11 used to record value command feature set. */ 2583 g_ut_cdw11 = 0; 2584 2585 /* arbitration_burst count available. */ 2586 nvme_ctrlr_set_arbitration_feature(&ctrlr); 2587 CU_ASSERT((uint8_t)g_ut_cdw11 == 6); 2588 CU_ASSERT((uint8_t)(g_ut_cdw11 >> 8) == 1); 2589 CU_ASSERT((uint8_t)(g_ut_cdw11 >> 16) == 2); 2590 CU_ASSERT((uint8_t)(g_ut_cdw11 >> 24) == 3); 2591 2592 /* arbitration_burst unavailable. */ 2593 g_ut_cdw11 = 0; 2594 ctrlr.opts.arbitration_burst = 8; 2595 2596 nvme_ctrlr_set_arbitration_feature(&ctrlr); 2597 CU_ASSERT(g_ut_cdw11 == 0); 2598 } 2599 2600 static void 2601 test_nvme_ctrlr_set_state(void) 2602 { 2603 struct spdk_nvme_ctrlr ctrlr = {}; 2604 MOCK_SET(spdk_get_ticks, 0); 2605 2606 nvme_ctrlr_set_state(&ctrlr, NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT, 1000); 2607 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT); 2608 CU_ASSERT(ctrlr.state_timeout_tsc == 1000000); 2609 2610 nvme_ctrlr_set_state(&ctrlr, NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT, 0); 2611 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT); 2612 CU_ASSERT(ctrlr.state_timeout_tsc == NVME_TIMEOUT_INFINITE); 2613 2614 /* Time out ticks causes integer overflow. */ 2615 MOCK_SET(spdk_get_ticks, UINT64_MAX); 2616 2617 nvme_ctrlr_set_state(&ctrlr, NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT, 1000); 2618 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT); 2619 CU_ASSERT(ctrlr.state_timeout_tsc == NVME_TIMEOUT_INFINITE); 2620 MOCK_CLEAR(spdk_get_ticks); 2621 } 2622 2623 static void 2624 test_nvme_ctrlr_active_ns_list_v0(void) 2625 { 2626 DECLARE_AND_CONSTRUCT_CTRLR(); 2627 2628 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2629 2630 ctrlr.vs.bits.mjr = 1; 2631 ctrlr.vs.bits.mnr = 0; 2632 ctrlr.vs.bits.ter = 0; 2633 ctrlr.cdata.nn = 1024; 2634 2635 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS; 2636 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0); 2637 SPDK_CU_ASSERT_FATAL(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS); 2638 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1)); 2639 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1024)); 2640 CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1025)); 2641 CU_ASSERT(spdk_nvme_ctrlr_get_first_active_ns(&ctrlr) == 1); 2642 CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1023) == 1024); 2643 CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1024) == 0); 2644 CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1025) == 0); 2645 2646 nvme_ctrlr_destruct(&ctrlr); 2647 } 2648 2649 static void 2650 test_nvme_ctrlr_active_ns_list_v2(void) 2651 { 2652 uint32_t i; 2653 uint32_t active_ns_list[1024]; 2654 DECLARE_AND_CONSTRUCT_CTRLR(); 2655 2656 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2657 2658 ctrlr.vs.bits.mjr = 1; 2659 ctrlr.vs.bits.mnr = 2; 2660 ctrlr.vs.bits.ter = 0; 2661 ctrlr.cdata.nn = 4096; 2662 2663 g_active_ns_list = active_ns_list; 2664 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list); 2665 2666 /* No active namespaces */ 2667 memset(active_ns_list, 0, sizeof(active_ns_list)); 2668 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS; 2669 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0); 2670 SPDK_CU_ASSERT_FATAL(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS); 2671 CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1)); 2672 CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1024)); 2673 CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1025)); 2674 CU_ASSERT(spdk_nvme_ctrlr_get_first_active_ns(&ctrlr) == 0); 2675 CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1024) == 0); 2676 2677 nvme_ctrlr_destruct(&ctrlr); 2678 2679 /* 1024 active namespaces - one full page */ 2680 memset(active_ns_list, 0, sizeof(active_ns_list)); 2681 for (i = 0; i < 1024; ++i) { 2682 active_ns_list[i] = i + 1; 2683 } 2684 2685 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2686 2687 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS; 2688 g_active_ns_list = active_ns_list; 2689 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list); 2690 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0); 2691 SPDK_CU_ASSERT_FATAL(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS); 2692 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1)); 2693 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1024)); 2694 CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1025)); 2695 CU_ASSERT(spdk_nvme_ctrlr_get_first_active_ns(&ctrlr) == 1); 2696 CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1023) == 1024); 2697 CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1024) == 0); 2698 CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1025) == 0); 2699 2700 nvme_ctrlr_destruct(&ctrlr); 2701 2702 /* 1023 active namespaces - full page minus one */ 2703 memset(active_ns_list, 0, sizeof(active_ns_list)); 2704 for (i = 0; i < 1023; ++i) { 2705 active_ns_list[i] = i + 1; 2706 } 2707 2708 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2709 2710 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS; 2711 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0); 2712 SPDK_CU_ASSERT_FATAL(ctrlr.state == NVME_CTRLR_STATE_IDENTIFY_NS); 2713 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1)); 2714 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1023)); 2715 CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1024)); 2716 CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 1025)); 2717 CU_ASSERT(spdk_nvme_ctrlr_get_first_active_ns(&ctrlr) == 1); 2718 CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1023) == 0); 2719 CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1024) == 0); 2720 CU_ASSERT(spdk_nvme_ctrlr_get_next_active_ns(&ctrlr, 1025) == 0); 2721 2722 nvme_ctrlr_destruct(&ctrlr); 2723 2724 g_active_ns_list = NULL; 2725 g_active_ns_list_length = 0; 2726 } 2727 2728 static void 2729 test_nvme_ctrlr_ns_mgmt(void) 2730 { 2731 DECLARE_AND_CONSTRUCT_CTRLR(); 2732 uint32_t active_ns_list[] = { 1, 2, 100, 1024 }; 2733 uint32_t active_ns_list2[] = { 1, 2, 3, 100, 1024 }; 2734 struct spdk_nvme_ns_data nsdata = {}; 2735 struct spdk_nvme_ctrlr_list ctrlr_list = {}; 2736 uint32_t nsid; 2737 2738 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2739 2740 ctrlr.vs.bits.mjr = 1; 2741 ctrlr.vs.bits.mnr = 2; 2742 ctrlr.vs.bits.ter = 0; 2743 ctrlr.cdata.nn = 4096; 2744 2745 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS; 2746 g_active_ns_list = active_ns_list; 2747 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list); 2748 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 2749 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0); 2750 } 2751 2752 fake_cpl.cdw0 = 3; 2753 nsid = spdk_nvme_ctrlr_create_ns(&ctrlr, &nsdata); 2754 fake_cpl.cdw0 = 0; 2755 CU_ASSERT(nsid == 3); 2756 CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 3)); 2757 CU_ASSERT(spdk_nvme_ctrlr_get_ns(&ctrlr, 3) != NULL); 2758 2759 g_active_ns_list = active_ns_list2; 2760 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list2); 2761 CU_ASSERT(spdk_nvme_ctrlr_attach_ns(&ctrlr, 3, &ctrlr_list) == 0); 2762 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 3)); 2763 CU_ASSERT(spdk_nvme_ctrlr_get_ns(&ctrlr, 3) != NULL); 2764 2765 g_active_ns_list = active_ns_list; 2766 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list); 2767 CU_ASSERT(spdk_nvme_ctrlr_detach_ns(&ctrlr, 3, &ctrlr_list) == 0); 2768 CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 3)); 2769 CU_ASSERT(spdk_nvme_ctrlr_get_ns(&ctrlr, 3) != NULL); 2770 2771 CU_ASSERT(spdk_nvme_ctrlr_delete_ns(&ctrlr, 3) == 0); 2772 CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 3)); 2773 CU_ASSERT(spdk_nvme_ctrlr_get_ns(&ctrlr, 3) != NULL); 2774 g_active_ns_list = NULL; 2775 g_active_ns_list_length = 0; 2776 2777 nvme_ctrlr_destruct(&ctrlr); 2778 } 2779 2780 static void 2781 check_en_set_rdy(void) 2782 { 2783 if (g_ut_nvme_regs.cc.bits.en == 1) { 2784 g_ut_nvme_regs.csts.bits.rdy = 1; 2785 } 2786 } 2787 2788 static void 2789 test_nvme_ctrlr_reset(void) 2790 { 2791 DECLARE_AND_CONSTRUCT_CTRLR(); 2792 struct spdk_nvme_ctrlr_data cdata = { .nn = 4096 }; 2793 uint32_t active_ns_list[] = { 1, 2, 100, 1024 }; 2794 uint32_t active_ns_list2[] = { 1, 100, 1024 }; 2795 2796 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2797 2798 g_ut_nvme_regs.vs.bits.mjr = 1; 2799 g_ut_nvme_regs.vs.bits.mnr = 2; 2800 g_ut_nvme_regs.vs.bits.ter = 0; 2801 nvme_ctrlr_get_vs(&ctrlr, &ctrlr.vs); 2802 ctrlr.cdata.nn = 2048; 2803 2804 ctrlr.state = NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS; 2805 g_active_ns_list = active_ns_list; 2806 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list); 2807 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 2808 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0); 2809 } 2810 CU_ASSERT(spdk_nvme_ctrlr_get_num_ns(&ctrlr) == 2048); 2811 CU_ASSERT(spdk_nvme_ctrlr_get_ns(&ctrlr, 2) != NULL); 2812 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 2)); 2813 2814 /* Reset controller with changed number of namespaces */ 2815 g_cdata = &cdata; 2816 g_active_ns_list = active_ns_list2; 2817 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list2); 2818 STAILQ_INSERT_HEAD(&adminq.free_req, &req, stailq); 2819 g_ut_nvme_regs.cc.raw = 0; 2820 g_ut_nvme_regs.csts.raw = 0; 2821 g_set_reg_cb = check_en_set_rdy; 2822 g_wait_for_completion_return_val = -ENXIO; 2823 CU_ASSERT(spdk_nvme_ctrlr_reset(&ctrlr) == 0); 2824 g_set_reg_cb = NULL; 2825 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_READY); 2826 g_cdata = NULL; 2827 g_active_ns_list = NULL; 2828 g_active_ns_list_length = 0; 2829 2830 CU_ASSERT(spdk_nvme_ctrlr_get_num_ns(&ctrlr) == 4096); 2831 CU_ASSERT(spdk_nvme_ctrlr_get_ns(&ctrlr, 2) != NULL); 2832 CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 2)); 2833 2834 g_ut_nvme_regs.csts.bits.shst = SPDK_NVME_SHST_COMPLETE; 2835 nvme_ctrlr_destruct(&ctrlr); 2836 2837 g_wait_for_completion_return_val = 0; 2838 } 2839 2840 static uint32_t g_aer_cb_counter; 2841 2842 static void 2843 aer_cb(void *aer_cb_arg, const struct spdk_nvme_cpl *cpl) 2844 { 2845 g_aer_cb_counter++; 2846 } 2847 2848 static void 2849 test_nvme_ctrlr_aer_callback(void) 2850 { 2851 DECLARE_AND_CONSTRUCT_CTRLR(); 2852 uint32_t active_ns_list[] = { 1, 2, 100, 1024 }; 2853 union spdk_nvme_async_event_completion aer_event = { 2854 .bits.async_event_type = SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE, 2855 .bits.async_event_info = SPDK_NVME_ASYNC_EVENT_NS_ATTR_CHANGED 2856 }; 2857 struct spdk_nvme_cpl aer_cpl = { 2858 .status.sct = SPDK_NVME_SCT_GENERIC, 2859 .status.sc = SPDK_NVME_SC_SUCCESS, 2860 .cdw0 = aer_event.raw 2861 }; 2862 2863 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2864 2865 ctrlr.vs.bits.mjr = 1; 2866 ctrlr.vs.bits.mnr = 2; 2867 ctrlr.vs.bits.ter = 0; 2868 ctrlr.cdata.nn = 4096; 2869 2870 ctrlr.state = NVME_CTRLR_STATE_CONFIGURE_AER; 2871 g_active_ns_list = active_ns_list; 2872 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list); 2873 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 2874 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0); 2875 } 2876 2877 CU_ASSERT(nvme_ctrlr_add_process(&ctrlr, NULL) == 0); 2878 spdk_nvme_ctrlr_register_aer_callback(&ctrlr, aer_cb, NULL); 2879 2880 /* Async event */ 2881 g_aer_cb_counter = 0; 2882 nvme_ctrlr_async_event_cb(&ctrlr.aer[0], &aer_cpl); 2883 nvme_ctrlr_complete_queued_async_events(&ctrlr); 2884 CU_ASSERT(g_aer_cb_counter == 1); 2885 g_active_ns_list = NULL; 2886 g_active_ns_list_length = 0; 2887 2888 nvme_ctrlr_free_processes(&ctrlr); 2889 nvme_ctrlr_destruct(&ctrlr); 2890 } 2891 2892 static void 2893 test_nvme_ctrlr_ns_attr_changed(void) 2894 { 2895 DECLARE_AND_CONSTRUCT_CTRLR(); 2896 uint32_t active_ns_list[] = { 1, 2, 100, 1024 }; 2897 uint32_t active_ns_list2[] = { 1, 2, 1024 }; 2898 uint32_t active_ns_list3[] = { 1, 2, 101, 1024 }; 2899 union spdk_nvme_async_event_completion aer_event = { 2900 .bits.async_event_type = SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE, 2901 .bits.async_event_info = SPDK_NVME_ASYNC_EVENT_NS_ATTR_CHANGED 2902 }; 2903 struct spdk_nvme_cpl aer_cpl = { 2904 .status.sct = SPDK_NVME_SCT_GENERIC, 2905 .status.sc = SPDK_NVME_SC_SUCCESS, 2906 .cdw0 = aer_event.raw 2907 }; 2908 2909 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 2910 2911 ctrlr.vs.bits.mjr = 1; 2912 ctrlr.vs.bits.mnr = 3; 2913 ctrlr.vs.bits.ter = 0; 2914 ctrlr.cap.bits.css |= SPDK_NVME_CAP_CSS_IOCS; 2915 ctrlr.cdata.nn = 4096; 2916 2917 ctrlr.state = NVME_CTRLR_STATE_CONFIGURE_AER; 2918 g_active_ns_list = active_ns_list; 2919 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list); 2920 2921 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 2922 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0); 2923 } 2924 2925 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 100)); 2926 2927 CU_ASSERT(nvme_ctrlr_add_process(&ctrlr, NULL) == 0); 2928 spdk_nvme_ctrlr_register_aer_callback(&ctrlr, aer_cb, NULL); 2929 2930 /* Remove NS 100 */ 2931 g_aer_cb_counter = 0; 2932 g_active_ns_list = active_ns_list2; 2933 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list2); 2934 nvme_ctrlr_async_event_cb(&ctrlr.aer[0], &aer_cpl); 2935 nvme_ctrlr_complete_queued_async_events(&ctrlr); 2936 CU_ASSERT(g_aer_cb_counter == 1); 2937 CU_ASSERT(!spdk_nvme_ctrlr_is_active_ns(&ctrlr, 100)); 2938 2939 /* Add NS 101 */ 2940 g_active_ns_list = active_ns_list3; 2941 g_active_ns_list_length = SPDK_COUNTOF(active_ns_list3); 2942 nvme_ctrlr_async_event_cb(&ctrlr.aer[0], &aer_cpl); 2943 nvme_ctrlr_complete_queued_async_events(&ctrlr); 2944 CU_ASSERT(g_aer_cb_counter == 2); 2945 CU_ASSERT(spdk_nvme_ctrlr_is_active_ns(&ctrlr, 101)); 2946 2947 g_active_ns_list = NULL; 2948 g_active_ns_list_length = 0; 2949 nvme_ctrlr_free_processes(&ctrlr); 2950 nvme_ctrlr_destruct(&ctrlr); 2951 } 2952 2953 static void 2954 test_nvme_ctrlr_identify_namespaces_iocs_specific_next(void) 2955 { 2956 struct spdk_nvme_ctrlr ctrlr = {}; 2957 uint32_t prev_nsid; 2958 struct spdk_nvme_ns ns[5] = {}; 2959 struct spdk_nvme_ctrlr ns_ctrlr[5] = {}; 2960 int rc = 0; 2961 int i; 2962 2963 RB_INIT(&ctrlr.ns); 2964 for (i = 0; i < 5; i++) { 2965 ns[i].id = i + 1; 2966 ns[i].active = true; 2967 } 2968 2969 CU_ASSERT(pthread_mutex_init(&ctrlr.ctrlr_lock, NULL) == 0); 2970 2971 ctrlr.cdata.nn = 5; 2972 /* case 1: No first/next active NS, move on to the next state, expect: pass */ 2973 prev_nsid = 0; 2974 ctrlr.active_ns_count = 0; 2975 ctrlr.opts.admin_timeout_ms = NVME_TIMEOUT_INFINITE; 2976 rc = nvme_ctrlr_identify_namespaces_iocs_specific_next(&ctrlr, prev_nsid); 2977 CU_ASSERT(rc == 0); 2978 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES); 2979 CU_ASSERT(ctrlr.state_timeout_tsc == NVME_TIMEOUT_INFINITE); 2980 2981 /* case 2: move on to the next active NS, and no namespace with (supported) iocs specific data found , expect: pass */ 2982 memset(&ctrlr.state, 0x00, sizeof(ctrlr.state)); 2983 memset(&ctrlr.state_timeout_tsc, 0x00, sizeof(ctrlr.state_timeout_tsc)); 2984 prev_nsid = 1; 2985 for (i = 0; i < 5; i++) { 2986 RB_INSERT(nvme_ns_tree, &ctrlr.ns, &ns[i]); 2987 } 2988 ctrlr.active_ns_count = 5; 2989 ns[1].csi = SPDK_NVME_CSI_NVM; 2990 ns[1].id = 2; 2991 rc = nvme_ctrlr_identify_namespaces_iocs_specific_next(&ctrlr, prev_nsid); 2992 CU_ASSERT(rc == 0); 2993 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES); 2994 CU_ASSERT(ctrlr.state_timeout_tsc == NVME_TIMEOUT_INFINITE); 2995 2996 /* case 3: ns.csi is SPDK_NVME_CSI_ZNS, do not loop, expect: pass */ 2997 memset(&ctrlr.state, 0x00, sizeof(ctrlr.state)); 2998 memset(&ctrlr.state_timeout_tsc, 0x00, sizeof(ctrlr.state_timeout_tsc)); 2999 ctrlr.opts.admin_timeout_ms = NVME_TIMEOUT_INFINITE; 3000 prev_nsid = 0; 3001 ctrlr.active_ns_count = 5; 3002 3003 for (int i = 0; i < 5; i++) { 3004 ns[i].csi = SPDK_NVME_CSI_NVM; 3005 ns[i].id = i + 1; 3006 ns[i].ctrlr = &ns_ctrlr[i]; 3007 } 3008 ns[4].csi = SPDK_NVME_CSI_ZNS; 3009 ns_ctrlr[4].opts.admin_timeout_ms = NVME_TIMEOUT_INFINITE; 3010 3011 rc = nvme_ctrlr_identify_namespaces_iocs_specific_next(&ctrlr, prev_nsid); 3012 CU_ASSERT(rc == 0); 3013 CU_ASSERT(ctrlr.state == 0); 3014 CU_ASSERT(ctrlr.state_timeout_tsc == NVME_TIMEOUT_INFINITE); 3015 CU_ASSERT(ns_ctrlr[4].state == NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC); 3016 CU_ASSERT(ns_ctrlr[4].state_timeout_tsc == NVME_TIMEOUT_INFINITE); 3017 3018 for (int i = 0; i < 5; i++) { 3019 nvme_ns_free_zns_specific_data(&ns[i]); 3020 } 3021 3022 /* case 4: nvme_ctrlr_identify_ns_iocs_specific_async return 1, expect: false */ 3023 memset(&ctrlr.state, 0x00, sizeof(ctrlr.state)); 3024 memset(&ctrlr.state_timeout_tsc, 0x00, sizeof(ctrlr.state_timeout_tsc)); 3025 prev_nsid = 1; 3026 ctrlr.active_ns_count = 5; 3027 ns[1].csi = SPDK_NVME_CSI_ZNS; 3028 g_fail_next_identify = true; 3029 rc = nvme_ctrlr_identify_namespaces_iocs_specific_next(&ctrlr, prev_nsid); 3030 CU_ASSERT(rc == 1); 3031 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_ERROR); 3032 CU_ASSERT(ctrlr.state_timeout_tsc == NVME_TIMEOUT_INFINITE); 3033 3034 CU_ASSERT(pthread_mutex_destroy(&ctrlr.ctrlr_lock) == 0); 3035 } 3036 3037 static void 3038 test_nvme_ctrlr_set_supported_log_pages(void) 3039 { 3040 int rc; 3041 struct spdk_nvme_ctrlr ctrlr = {}; 3042 3043 /* ana supported */ 3044 memset(&ctrlr, 0, sizeof(ctrlr)); 3045 ctrlr.cdata.cmic.ana_reporting = true; 3046 ctrlr.cdata.lpa.celp = 1; 3047 ctrlr.cdata.nanagrpid = 1; 3048 ctrlr.active_ns_count = 1; 3049 3050 rc = nvme_ctrlr_set_supported_log_pages(&ctrlr); 3051 CU_ASSERT(rc == 0); 3052 CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_ERROR] == true); 3053 CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_HEALTH_INFORMATION] == true); 3054 CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_FIRMWARE_SLOT] == true); 3055 CU_ASSERT(ctrlr.ana_log_page_size == sizeof(struct spdk_nvme_ana_page) + 3056 sizeof(struct spdk_nvme_ana_group_descriptor) * 1 + sizeof(uint32_t) * 1); 3057 CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS] == true); 3058 free(ctrlr.ana_log_page); 3059 free(ctrlr.copied_ana_desc); 3060 } 3061 3062 static void 3063 test_nvme_ctrlr_set_intel_supported_log_pages(void) 3064 { 3065 DECLARE_AND_CONSTRUCT_CTRLR(); 3066 3067 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 3068 3069 ctrlr.opts.admin_timeout_ms = NVME_TIMEOUT_INFINITE; 3070 ctrlr.cdata.vid = SPDK_PCI_VID_INTEL; 3071 ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_PCIE; 3072 ctrlr.state = NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES; 3073 3074 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 3075 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES); 3076 3077 set_status_code = SPDK_NVME_SC_SUCCESS; 3078 CU_ASSERT(nvme_ctrlr_process_init(&ctrlr) == 0); 3079 CU_ASSERT(ctrlr.state == NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES); 3080 3081 CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_ERROR] == true); 3082 CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_HEALTH_INFORMATION] == true); 3083 CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_LOG_FIRMWARE_SLOT] == true); 3084 CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY] == true); 3085 CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_INTEL_LOG_WRITE_CMD_LATENCY] == true); 3086 CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_INTEL_LOG_TEMPERATURE] == true); 3087 CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_INTEL_LOG_SMART] == true); 3088 CU_ASSERT(ctrlr.log_page_supported[SPDK_NVME_INTEL_MARKETING_DESCRIPTION] == true); 3089 3090 nvme_ctrlr_destruct(&ctrlr); 3091 } 3092 3093 #define UT_ANA_DESC_SIZE (sizeof(struct spdk_nvme_ana_group_descriptor) + \ 3094 sizeof(uint32_t)) 3095 static void 3096 test_nvme_ctrlr_parse_ana_log_page(void) 3097 { 3098 int rc, i; 3099 struct spdk_nvme_ctrlr ctrlr = {}; 3100 struct spdk_nvme_ns ns[3] = {}; 3101 struct spdk_nvme_ana_page ana_hdr; 3102 char _ana_desc[UT_ANA_DESC_SIZE]; 3103 struct spdk_nvme_ana_group_descriptor *ana_desc; 3104 uint32_t offset; 3105 3106 RB_INIT(&ctrlr.ns); 3107 for (i = 0; i < 3; i++) { 3108 ns[i].id = i + 1; 3109 ns[i].active = true; 3110 RB_INSERT(nvme_ns_tree, &ctrlr.ns, &ns[i]); 3111 } 3112 3113 CU_ASSERT(pthread_mutex_init(&ctrlr.ctrlr_lock, NULL) == 0); 3114 3115 ctrlr.cdata.nn = 3; 3116 ctrlr.cdata.nanagrpid = 3; 3117 ctrlr.active_ns_count = 3; 3118 3119 rc = nvme_ctrlr_update_ana_log_page(&ctrlr); 3120 CU_ASSERT(rc == 0); 3121 CU_ASSERT(ctrlr.ana_log_page != NULL); 3122 CU_ASSERT(ctrlr.copied_ana_desc != NULL); 3123 3124 /* 3125 * Create ANA log page data - There are three ANA groups. 3126 * Each ANA group has a namespace and has a different ANA state. 3127 */ 3128 memset(&ana_hdr, 0, sizeof(ana_hdr)); 3129 ana_hdr.num_ana_group_desc = 3; 3130 3131 SPDK_CU_ASSERT_FATAL(sizeof(ana_hdr) <= ctrlr.ana_log_page_size); 3132 memcpy((char *)ctrlr.ana_log_page, (char *)&ana_hdr, sizeof(ana_hdr)); 3133 offset = sizeof(ana_hdr); 3134 3135 ana_desc = (struct spdk_nvme_ana_group_descriptor *)_ana_desc; 3136 memset(ana_desc, 0, UT_ANA_DESC_SIZE); 3137 ana_desc->num_of_nsid = 1; 3138 3139 ana_desc->ana_group_id = 1; 3140 ana_desc->ana_state = SPDK_NVME_ANA_OPTIMIZED_STATE; 3141 ana_desc->nsid[0] = 3; 3142 3143 SPDK_CU_ASSERT_FATAL(offset + UT_ANA_DESC_SIZE <= ctrlr.ana_log_page_size); 3144 memcpy((char *)ctrlr.ana_log_page + offset, (char *)ana_desc, UT_ANA_DESC_SIZE); 3145 offset += UT_ANA_DESC_SIZE; 3146 3147 ana_desc->ana_group_id = 2; 3148 ana_desc->ana_state = SPDK_NVME_ANA_NON_OPTIMIZED_STATE; 3149 ana_desc->nsid[0] = 2; 3150 3151 SPDK_CU_ASSERT_FATAL(offset + UT_ANA_DESC_SIZE <= ctrlr.ana_log_page_size); 3152 memcpy((char *)ctrlr.ana_log_page + offset, (char *)ana_desc, UT_ANA_DESC_SIZE); 3153 offset += UT_ANA_DESC_SIZE; 3154 3155 ana_desc->ana_group_id = 3; 3156 ana_desc->ana_state = SPDK_NVME_ANA_INACCESSIBLE_STATE; 3157 ana_desc->nsid[0] = 1; 3158 3159 SPDK_CU_ASSERT_FATAL(offset + UT_ANA_DESC_SIZE <= ctrlr.ana_log_page_size); 3160 memcpy((char *)ctrlr.ana_log_page + offset, (char *)ana_desc, UT_ANA_DESC_SIZE); 3161 3162 /* Parse the created ANA log page data, and update ANA states. */ 3163 rc = nvme_ctrlr_parse_ana_log_page(&ctrlr, nvme_ctrlr_update_ns_ana_states, 3164 &ctrlr); 3165 CU_ASSERT(rc == 0); 3166 CU_ASSERT(ns[0].ana_group_id == 3); 3167 CU_ASSERT(ns[0].ana_state == SPDK_NVME_ANA_INACCESSIBLE_STATE); 3168 CU_ASSERT(ns[1].ana_group_id == 2); 3169 CU_ASSERT(ns[1].ana_state == SPDK_NVME_ANA_NON_OPTIMIZED_STATE); 3170 CU_ASSERT(ns[2].ana_group_id == 1); 3171 CU_ASSERT(ns[2].ana_state == SPDK_NVME_ANA_OPTIMIZED_STATE); 3172 3173 CU_ASSERT(pthread_mutex_destroy(&ctrlr.ctrlr_lock) == 0); 3174 3175 free(ctrlr.ana_log_page); 3176 free(ctrlr.copied_ana_desc); 3177 } 3178 3179 static void 3180 test_nvme_ctrlr_ana_resize(void) 3181 { 3182 DECLARE_AND_CONSTRUCT_CTRLR(); 3183 uint32_t active_ns_list[] = { 1, 2, 3, 4 }; 3184 struct spdk_nvme_ana_page ana_hdr = { 3185 .change_count = 0, 3186 .num_ana_group_desc = 1 3187 }; 3188 uint8_t ana_desc_buf[sizeof(struct spdk_nvme_ana_group_descriptor) + 4 * sizeof(uint32_t)] = {}; 3189 struct spdk_nvme_ana_group_descriptor *ana_desc = 3190 (struct spdk_nvme_ana_group_descriptor *)ana_desc_buf; 3191 struct spdk_nvme_ns *ns; 3192 union spdk_nvme_async_event_completion aer_event = { 3193 .bits.async_event_type = SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE, 3194 .bits.async_event_info = SPDK_NVME_ASYNC_EVENT_NS_ATTR_CHANGED 3195 }; 3196 struct spdk_nvme_cpl aer_cpl = { 3197 .status.sct = SPDK_NVME_SCT_GENERIC, 3198 .status.sc = SPDK_NVME_SC_SUCCESS, 3199 .cdw0 = aer_event.raw 3200 }; 3201 uint32_t i; 3202 3203 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_construct(&ctrlr) == 0); 3204 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_add_process(&ctrlr, NULL) == 0); 3205 3206 ctrlr.vs.bits.mjr = 1; 3207 ctrlr.vs.bits.mnr = 4; 3208 ctrlr.vs.bits.ter = 0; 3209 ctrlr.cdata.nn = 4096; 3210 ctrlr.cdata.cmic.ana_reporting = true; 3211 ctrlr.cdata.nanagrpid = 1; 3212 3213 ctrlr.state = NVME_CTRLR_STATE_CONFIGURE_AER; 3214 /* Start with 2 active namespaces */ 3215 g_active_ns_list = active_ns_list; 3216 g_active_ns_list_length = 2; 3217 g_ana_hdr = &ana_hdr; 3218 g_ana_descs = &ana_desc; 3219 ana_desc->ana_group_id = 1; 3220 ana_desc->ana_state = SPDK_NVME_ANA_NON_OPTIMIZED_STATE; 3221 ana_desc->num_of_nsid = 2; 3222 for (i = 0; i < ana_desc->num_of_nsid; ++i) { 3223 ana_desc->nsid[i] = i + 1; 3224 } 3225 3226 /* Bring controller to ready state */ 3227 while (ctrlr.state != NVME_CTRLR_STATE_READY) { 3228 SPDK_CU_ASSERT_FATAL(nvme_ctrlr_process_init(&ctrlr) == 0); 3229 } 3230 3231 for (i = 0; i < ana_desc->num_of_nsid; ++i) { 3232 ns = spdk_nvme_ctrlr_get_ns(&ctrlr, i + 1); 3233 CU_ASSERT(ns->ana_state == SPDK_NVME_ANA_NON_OPTIMIZED_STATE); 3234 } 3235 3236 /* Add more namespaces */ 3237 g_active_ns_list_length = 4; 3238 nvme_ctrlr_async_event_cb(&ctrlr.aer[0], &aer_cpl); 3239 nvme_ctrlr_complete_queued_async_events(&ctrlr); 3240 3241 /* Update ANA log with new namespaces */ 3242 ana_desc->ana_state = SPDK_NVME_ANA_OPTIMIZED_STATE; 3243 ana_desc->num_of_nsid = 4; 3244 for (i = 0; i < ana_desc->num_of_nsid; ++i) { 3245 ana_desc->nsid[i] = i + 1; 3246 } 3247 aer_event.bits.async_event_info = SPDK_NVME_ASYNC_EVENT_ANA_CHANGE; 3248 aer_cpl.cdw0 = aer_event.raw; 3249 nvme_ctrlr_async_event_cb(&ctrlr.aer[0], &aer_cpl); 3250 nvme_ctrlr_complete_queued_async_events(&ctrlr); 3251 3252 for (i = 0; i < ana_desc->num_of_nsid; ++i) { 3253 ns = spdk_nvme_ctrlr_get_ns(&ctrlr, i + 1); 3254 CU_ASSERT(ns->ana_state == SPDK_NVME_ANA_OPTIMIZED_STATE); 3255 } 3256 3257 g_active_ns_list = NULL; 3258 g_active_ns_list_length = 0; 3259 g_ana_hdr = NULL; 3260 g_ana_descs = NULL; 3261 nvme_ctrlr_free_processes(&ctrlr); 3262 nvme_ctrlr_destruct(&ctrlr); 3263 } 3264 3265 static void 3266 test_nvme_ctrlr_get_memory_domains(void) 3267 { 3268 struct spdk_nvme_ctrlr ctrlr = {}; 3269 3270 MOCK_SET(nvme_transport_ctrlr_get_memory_domains, 1); 3271 CU_ASSERT(spdk_nvme_ctrlr_get_memory_domains(&ctrlr, NULL, 0) == 1); 3272 3273 MOCK_SET(nvme_transport_ctrlr_get_memory_domains, 0); 3274 CU_ASSERT(spdk_nvme_ctrlr_get_memory_domains(&ctrlr, NULL, 0) == 0); 3275 3276 MOCK_CLEAR(nvme_transport_ctrlr_get_memory_domains); 3277 } 3278 3279 int 3280 main(int argc, char **argv) 3281 { 3282 CU_pSuite suite = NULL; 3283 unsigned int num_failures; 3284 3285 CU_set_error_action(CUEA_ABORT); 3286 CU_initialize_registry(); 3287 3288 suite = CU_add_suite("nvme_ctrlr", NULL, NULL); 3289 3290 CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_1_rdy_0); 3291 CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_1_rdy_1); 3292 CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_0_rdy_0); 3293 CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_0_rdy_1); 3294 CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_0_rdy_0_ams_rr); 3295 CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_0_rdy_0_ams_wrr); 3296 CU_ADD_TEST(suite, test_nvme_ctrlr_init_en_0_rdy_0_ams_vs); 3297 CU_ADD_TEST(suite, test_nvme_ctrlr_init_delay); 3298 CU_ADD_TEST(suite, test_alloc_io_qpair_rr_1); 3299 CU_ADD_TEST(suite, test_ctrlr_get_default_ctrlr_opts); 3300 CU_ADD_TEST(suite, test_ctrlr_get_default_io_qpair_opts); 3301 CU_ADD_TEST(suite, test_alloc_io_qpair_wrr_1); 3302 CU_ADD_TEST(suite, test_alloc_io_qpair_wrr_2); 3303 CU_ADD_TEST(suite, test_spdk_nvme_ctrlr_update_firmware); 3304 CU_ADD_TEST(suite, test_nvme_ctrlr_fail); 3305 CU_ADD_TEST(suite, test_nvme_ctrlr_construct_intel_support_log_page_list); 3306 CU_ADD_TEST(suite, test_nvme_ctrlr_set_supported_features); 3307 CU_ADD_TEST(suite, test_spdk_nvme_ctrlr_doorbell_buffer_config); 3308 #if 0 /* TODO: move to PCIe-specific unit test */ 3309 CU_ADD_TEST(suite, test_nvme_ctrlr_alloc_cmb); 3310 #endif 3311 CU_ADD_TEST(suite, test_nvme_ctrlr_test_active_ns); 3312 CU_ADD_TEST(suite, test_nvme_ctrlr_test_active_ns_error_case); 3313 CU_ADD_TEST(suite, test_spdk_nvme_ctrlr_reconnect_io_qpair); 3314 CU_ADD_TEST(suite, test_spdk_nvme_ctrlr_set_trid); 3315 CU_ADD_TEST(suite, test_nvme_ctrlr_init_set_nvmf_ioccsz); 3316 CU_ADD_TEST(suite, test_nvme_ctrlr_init_set_num_queues); 3317 CU_ADD_TEST(suite, test_nvme_ctrlr_init_set_keep_alive_timeout); 3318 CU_ADD_TEST(suite, test_alloc_io_qpair_fail); 3319 CU_ADD_TEST(suite, test_nvme_ctrlr_add_remove_process); 3320 CU_ADD_TEST(suite, test_nvme_ctrlr_set_arbitration_feature); 3321 CU_ADD_TEST(suite, test_nvme_ctrlr_set_state); 3322 CU_ADD_TEST(suite, test_nvme_ctrlr_active_ns_list_v0); 3323 CU_ADD_TEST(suite, test_nvme_ctrlr_active_ns_list_v2); 3324 CU_ADD_TEST(suite, test_nvme_ctrlr_ns_mgmt); 3325 CU_ADD_TEST(suite, test_nvme_ctrlr_reset); 3326 CU_ADD_TEST(suite, test_nvme_ctrlr_aer_callback); 3327 CU_ADD_TEST(suite, test_nvme_ctrlr_ns_attr_changed); 3328 CU_ADD_TEST(suite, test_nvme_ctrlr_identify_namespaces_iocs_specific_next); 3329 CU_ADD_TEST(suite, test_nvme_ctrlr_set_supported_log_pages); 3330 CU_ADD_TEST(suite, test_nvme_ctrlr_set_intel_supported_log_pages); 3331 CU_ADD_TEST(suite, test_nvme_ctrlr_parse_ana_log_page); 3332 CU_ADD_TEST(suite, test_nvme_ctrlr_ana_resize); 3333 CU_ADD_TEST(suite, test_nvme_ctrlr_get_memory_domains); 3334 3335 CU_basic_set_mode(CU_BRM_VERBOSE); 3336 CU_basic_run_tests(); 3337 num_failures = CU_get_number_of_failures(); 3338 CU_cleanup_registry(); 3339 return num_failures; 3340 } 3341