1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 */ 4 5 #include "spdk/stdinc.h" 6 7 struct accel_mlx5_attr { 8 /* The number of entries in qp submission/receive queue */ 9 uint16_t qp_size; 10 /* The number of requests in the global pool */ 11 uint32_t num_requests; 12 /* Comma separated list of allowed device names */ 13 char *allowed_devs; 14 /* Apply crypto operation for each X data blocks. Works only if multiblock crypto operation is supported by HW. 15 * 0 means no limit */ 16 uint16_t crypto_split_blocks; 17 /* Enables accel_mlx5 platform driver. The driver can execute a limited scope of operations */ 18 bool enable_driver; 19 }; 20 21 enum accel_mlx5_dump_state_level { 22 /** Dump only grand total statistics */ 23 ACCEL_MLX5_DUMP_STAT_LEVEL_TOTAL, 24 /** Dump grand total statistics and per channel statistics over all devices */ 25 ACCEL_MLX5_DUMP_STAT_LEVEL_CHANNEL, 26 /** Dump grand total statistics and per channel statistics for each individual device */ 27 ACCEL_MLX5_DUMP_STAT_LEVEL_DEV 28 }; 29 30 typedef void(*accel_mlx5_dump_stat_done_cb)(void *ctx, int rc); 31 32 void accel_mlx5_get_default_attr(struct accel_mlx5_attr *attr); 33 int accel_mlx5_enable(struct accel_mlx5_attr *attr); 34 int accel_mlx5_dump_stats(struct spdk_json_write_ctx *w, enum accel_mlx5_dump_state_level level, 35 accel_mlx5_dump_stat_done_cb cb, void *ctx); 36