1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (C) 2019 Intel Corporation. 3 * All rights reserved. 4 */ 5 6 #ifndef VMD_SPEC_H 7 #define VMD_SPEC_H 8 9 #define MAX_VMD_SUPPORTED 48 /* max number of vmd controllers in a system - */ 10 11 #define PCI_INVALID_VENDORID 0xFFFF 12 #define ONE_MB (1<<20) 13 #define PCI_OFFSET_OF(object, member) ((uint32_t)&((object*)0)->member) 14 #define TWOS_COMPLEMENT(value) (~(value) + 1) 15 16 #define VMD_UPPER_BASE_SIGNATURE 0xFFFFFFEF 17 #define VMD_UPPER_LIMIT_SIGNATURE 0xFFFFFFED 18 19 /* VMD Registers */ 20 #define PCI_VMD_VMCAP 0x40 21 #define PCI_VMD_VMCONFIG 0x44 22 23 /* 24 * BAR assignment constants 25 */ 26 #define PCI_DWORD_SHIFT 32 27 #define PCI_BASE_ADDR_MASK 0xFFFFFFF0 28 #define PCI_BAR_MEMORY_MASK 0x0000000F 29 #define PCI_BAR_MEMORY_MEM_IND 0x1 30 #define PCI_BAR_MEMORY_TYPE 0x6 31 #define PCI_BAR_MEMORY_PREFETCH 0x8 32 #define PCI_BAR_MEMORY_TYPE_32 0x0 33 #define PCI_BAR_MEMORY_TYPE_64 0x4 34 #define PCI_BAR_MB_MASK 0xFFFFF 35 #define PCI_PCI_BRIDGE_ADDR_DEF 0xFFF0 36 #define PCI_BRIDGE_MEMORY_MASK 0xFFF0 37 #define PCI_BRIDGE_PREFETCH_64 0x0001 38 #define PCI_BRIDGE_MEMORY_SHIFT 16 39 #define PCI_CONFIG_ACCESS_DELAY 500 40 41 #define PCI_MAX_CFG_SIZE 0x1000 42 43 #define PCI_HEADER_TYPE 0x0e 44 #define PCI_HEADER_TYPE_NORMAL 0 45 #define PCI_HEADER_TYPE_BRIDGE 1 46 #define PCI_MULTI_FUNCTION 0x80 47 48 #define PCI_COMMAND_MEMORY 0x2 49 #define PCI_COMMAND_MASTER 0x4 50 51 #define PCIE_TYPE_FLAGS 0xf0 52 #define PCIE_TYPE_SHIFT 4 53 #define PCIE_TYPE_ROOT_PORT 0x4 54 #define PCIE_TYPE_DOWNSTREAM 0x6 55 56 #define PCI_CLASS_STORAGE_EXPRESS 0x010802 57 #define ADDR_ELEM_COUNT 32 58 #define PCI_MAX_BUS_NUMBER 0x7F 59 #define RESERVED_HOTPLUG_BUSES 1 60 #define isHotPlugCapable(slotCap) ((slotCap) & (1<<6)) 61 #define CONFIG_OFFSET_ADDR(bus, device, function, reg) (((bus)<<20) | (device)<<15 | (function<<12) | (reg)) 62 #define BRIDGE_BASEREG(reg) (0xFFF0 & ((reg)>>16)) 63 64 #define MISCCTRLSTS_0_OFFSET 0x188 65 #define ENABLE_ACPI_MODE_FOR_HOTPLUG (1 << 3) 66 67 /* Bit encodings for Command Register */ 68 #define IO_SPACE_ENABLE 0x0001 69 #define MEMORY_SPACE_ENABLE 0x0002 70 #define BUS_MASTER_ENABLE 0x0004 71 72 /* Bit encodings for Status Register */ 73 #define PCI_CAPABILITIES_LIST 0x0010 74 #define PCI_RECEIVED_TARGET_ABORT 0x1000 75 #define PCI_RECEIVED_MASTER_ABORT 0x2000 76 #define PCI_SIGNALED_SYSTEM_ERROR 0x4000 77 #define PCI_DETECTED_PARITY_ERROR 0x8000 78 79 /* Capability IDs */ 80 #define CAPABILITY_ID_POWER_MANAGEMENT 0x01 81 #define CAPABILITY_ID_MSI 0x05 82 #define CAPABILITY_ID_PCI_EXPRESS 0x10 83 #define CAPABILITY_ID_MSIX 0x11 84 85 #define PCI_MSIX_ENABLE (1 << 15) /* bit 15 of MSIX Message Control */ 86 #define PCI_MSIX_FUNCTION_MASK (1 << 14) /* bit 14 of MSIX Message Control */ 87 88 /* extended capability */ 89 #define EXTENDED_CAPABILITY_OFFSET 0x100 90 #define DEVICE_SERIAL_NUMBER_CAP_ID 0x3 91 92 #define BAR_SIZE (1 << 20) 93 94 struct pci_enhanced_capability_header { 95 uint16_t capability_id; 96 uint16_t version: 4; 97 uint16_t next: 12; 98 }; 99 100 struct serial_number_capability { 101 struct pci_enhanced_capability_header hdr; 102 uint32_t sn_low; 103 uint32_t sn_hi; 104 }; 105 106 struct pci_header_common { 107 uint16_t vendor_id; 108 uint16_t device_id; 109 uint16_t command; 110 uint16_t status; 111 uint32_t rev_class; 112 uint8_t cache_line_size; 113 uint8_t master_lat_timer; 114 uint8_t header_type; 115 uint8_t BIST; 116 uint8_t rsvd12[36]; 117 uint8_t cap_pointer; 118 uint8_t rsvd53[7]; 119 uint8_t int_line; 120 uint8_t int_pin; 121 uint8_t rsvd62[2]; 122 }; 123 124 struct pci_header_zero { 125 uint16_t vendor_id; 126 uint16_t device_id; 127 uint16_t command; 128 uint16_t status; 129 uint32_t rev_class; 130 uint8_t cache_line_size; 131 uint8_t master_lat_timer; 132 uint8_t header_type; 133 uint8_t BIST; 134 uint32_t BAR[6]; 135 uint32_t carbus_cis_pointer; 136 uint16_t ssvid; 137 uint16_t ssid; 138 uint32_t exp_rom_base_addr; 139 uint8_t cap_pointer; 140 uint8_t rsvd53[7]; 141 uint8_t intLine; 142 uint8_t int_pin; 143 uint8_t min_gnt; 144 uint8_t max_lat; 145 }; 146 147 struct pci_header_one { 148 uint16_t vendor_id; 149 uint16_t device_id; 150 uint16_t command; 151 uint16_t status; 152 uint32_t rev_class; 153 uint8_t cache_line_size; 154 uint8_t master_lat_timer; 155 uint8_t header_type; 156 uint8_t BIST; 157 uint32_t BAR[2]; 158 uint8_t primary; 159 uint8_t secondary; 160 uint8_t subordinate; 161 uint8_t secondary_lat_timer; 162 uint8_t io_base; 163 uint8_t io_limit; 164 uint16_t secondary_status; 165 uint16_t mem_base; 166 uint16_t mem_limit; 167 uint16_t prefetch_base; 168 uint16_t prefetch_limit; 169 uint32_t prefetch_base_upper; 170 uint32_t prefetch_limit_upper; 171 uint16_t io_base_upper; 172 uint16_t io_limit_upper; 173 uint8_t cap_pointer; 174 uint8_t rsvd53[3]; 175 uint32_t exp_romBase_addr; 176 uint8_t int_line; 177 uint8_t int_pin; 178 uint16_t bridge_control; 179 }; 180 181 struct pci_capabilities_header { 182 uint8_t capability_id; 183 uint8_t next; 184 }; 185 186 /* 187 * MSI capability structure for msi interrupt vectors 188 */ 189 #define MAX_MSIX_TABLE_SIZE 0x800 190 #define MSIX_ENTRY_VECTOR_CTRL_MASKBIT 1 191 #define PORT_INT_VECTOR 0; 192 #define CLEAR_MSIX_DESTINATION_ID 0xfff00fff 193 struct pci_msi_cap { 194 struct pci_capabilities_header header; 195 union _MsiControl { 196 uint16_t as_uint16_t; 197 struct _PCI_MSI_MESSAGE_CONTROL { 198 uint16_t msi_enable : 1; 199 uint16_t multiple_message_capable : 3; 200 uint16_t multiple_message_enable : 3; 201 uint16_t capable_of_64bits : 1; 202 uint16_t per_vector_mask_capable : 1; 203 uint16_t reserved : 7; 204 } bit; 205 } message_control; 206 union { 207 struct _PCI_MSI_MESSAGE_ADDRESS { 208 uint32_t reserved : 2; 209 uint32_t address : 30; 210 } reg; 211 uint32_t raw; 212 } message_address_lower; 213 union { 214 struct _Option32_bit { 215 uint16_t message_data; 216 } option32_bit; 217 struct _Option64_bit { 218 uint32_t message_address_upper; 219 uint16_t message_data; 220 uint16_t reserved; 221 uint32_t mask_bits; 222 uint32_t pending_bits; 223 } option64_bit; 224 }; 225 }; 226 227 struct pcix_table_pointer { 228 union { 229 struct { 230 uint32_t BaseIndexRegister : 3; 231 uint32_t Reserved : 29; 232 } TableBIR; 233 uint32_t TableOffset; 234 }; 235 }; 236 237 struct pci_msix_capability { 238 struct pci_capabilities_header header; 239 union _MsixControl { 240 uint16_t as_uint16_t; 241 struct msg_ctrl { 242 uint16_t table_size : 11; 243 uint16_t reserved : 3; 244 uint16_t function_mask : 1; 245 uint16_t msix_enable : 1; 246 } bit; 247 } message_control; 248 249 struct pcix_table_pointer message_table; 250 struct pcix_table_pointer pba_table; 251 }; 252 253 struct pci_msix_table_entry { 254 volatile uint32_t message_addr_lo; 255 volatile uint32_t message_addr_hi; 256 volatile uint32_t message_data; 257 volatile uint32_t vector_control; 258 }; 259 260 /* 261 * Pci express capability 262 */ 263 enum PciExpressCapabilities { 264 /* 0001b Legacy PCI Express Endpoint */ 265 LegacyEndpoint = 0x1, 266 /* 0000b PCI Express Endpoint */ 267 ExpressEndpoint = 0x0, 268 /* 0100b Root Port of PCI Express Root Complex* */ 269 RootComplexRootPort = 0x4, 270 /* 0101b Upstream Port of PCI Express Switch* */ 271 SwitchUpstreamPort = 0x5, 272 /* 0110b Downstream Port of PCI Express Switch* */ 273 SwitchDownStreamPort = 0x6, 274 /* 0111b PCI Express to PCI/PCI-X Bridge* */ 275 ExpressToPciBridge = 0x7, 276 /* 1000b PCI/PCI-X to PCI Express Bridge* */ 277 PciToExpressBridge = 0x8, 278 /* 1001b Root Complex Integrated Endpoint */ 279 RCIntegratedEndpoint = 0x9, 280 /* 1010b Root Complex Event Collector */ 281 RootComplexEventCollector = 0xa, 282 InvalidCapability = 0xff 283 }; 284 285 union express_capability_register { 286 struct { 287 uint16_t capability_version : 4; 288 uint16_t device_type : 4; 289 uint16_t slot_implemented : 1; 290 uint16_t interrupt_message_number : 5; 291 uint16_t rsv : 2; 292 } bit_field; 293 uint16_t as_uint16_t; 294 }; 295 296 union express_slot_capabilities_register { 297 struct { 298 uint32_t attention_button_present : 1; 299 uint32_t power_controller_present : 1; 300 uint32_t MRL_sensor_present : 1; 301 uint32_t attention_indicator_present : 1; 302 uint32_t power_indicator_present : 1; 303 uint32_t hotplug_surprise : 1; 304 uint32_t hotplug_capable : 1; 305 uint32_t slot_power_limit : 8; 306 uint32_t slotPower_limit_scale : 2; 307 uint32_t electromechanical_lock_present : 1; 308 uint32_t no_command_completed_support : 1; 309 uint32_t physical_slot_number : 13; 310 } bit_field; 311 uint32_t as_uint32_t; 312 }; 313 314 union express_slot_control_register { 315 struct { 316 uint16_t attention_button_enable : 1; 317 uint16_t power_fault_detect_enable : 1; 318 uint16_t MRLsensor_enable : 1; 319 uint16_t presence_detect_enable : 1; 320 uint16_t command_completed_enable : 1; 321 uint16_t hotplug_interrupt_enable : 1; 322 uint16_t attention_indicator_control : 2; 323 uint16_t power_indicator_control : 2; 324 uint16_t power_controller_control : 1; 325 uint16_t electromechanical_lockcontrol : 1; 326 uint16_t datalink_state_change_enable : 1; 327 uint16_t Rsvd : 3; 328 } bit_field; 329 uint16_t as_uint16_t; 330 }; 331 332 union express_slot_status_register { 333 struct { 334 uint16_t attention_button_pressed : 1; 335 uint16_t power_fault_detected : 1; 336 uint16_t MRL_sensor_changed : 1; 337 uint16_t presence_detect_changed : 1; 338 uint16_t command_completed : 1; 339 uint16_t MRL_sensor_state : 1; 340 uint16_t presence_detect_state : 1; 341 uint16_t electromechanical_lock_engaged : 1; 342 uint16_t datalink_state_changed : 1; 343 uint16_t rsvd : 7; 344 } bit_field; 345 uint16_t as_uint16_t; 346 }; 347 348 union express_root_control_register { 349 struct { 350 uint16_t CorrectableSerrEnable : 1; 351 uint16_t NonFatalSerrEnable : 1; 352 uint16_t FatalSerrEnable : 1; 353 uint16_t PMEInterruptEnable : 1; 354 uint16_t CRSSoftwareVisibilityEnable : 1; 355 uint16_t Rsvd : 11; 356 } bit_field; 357 uint16_t as_uint16_t; 358 }; 359 360 union express_link_capability_register { 361 struct { 362 uint32_t maximum_link_speed : 4; 363 uint32_t maximum_link_width : 6; 364 uint32_t active_state_pms_support : 2; 365 uint32_t l0_exit_latency : 3; 366 uint32_t l1_exit_latency : 3; 367 uint32_t clock_power_management : 1; 368 uint32_t surprise_down_error_reporting_capable : 1; 369 uint32_t datalink_layer_active_reporting_capable : 1; 370 uint32_t link_bandwidth_notification_capability : 1; 371 uint32_t aspm_optionality_compliance : 1; 372 uint32_t rsvd : 1; 373 uint32_t port_number : 8; 374 } bit_field; 375 uint32_t as_uint32_t; 376 }; 377 378 union express_link_control_register { 379 struct { 380 uint16_t active_state_pm_control : 2; 381 uint16_t rsvd1 : 1; 382 uint16_t read_completion_boundary : 1; 383 uint16_t link_disable : 1; 384 uint16_t retrain_link : 1; 385 uint16_t common_clock_config : 1; 386 uint16_t extended_synch : 1; 387 uint16_t enable_clock_power_management : 1; 388 uint16_t rsvd2 : 7; 389 } bit_field; 390 uint16_t as_uint16_t; 391 }; 392 393 union express_link_status_register { 394 struct { 395 uint16_t link_speed : 4; 396 uint16_t link_width : 6; 397 uint16_t undefined : 1; 398 uint16_t link_training : 1; 399 uint16_t slot_clock_config : 1; 400 uint16_t datalink_layer_active : 1; 401 uint16_t asvd : 2; 402 } bit_field; 403 uint16_t as_uint16_t; 404 }; 405 406 struct pci_express_cap { 407 uint8_t capid; 408 uint8_t next_cap; 409 union express_capability_register express_cap_register; 410 uint32_t device_cap; 411 uint16_t device_control; 412 uint16_t device_status; 413 union express_link_capability_register link_cap; 414 union express_link_control_register link_control; 415 union express_link_status_register link_status; 416 union express_slot_capabilities_register slot_cap; 417 union express_slot_control_register slot_control; 418 union express_slot_status_register slot_status; 419 uint32_t root_status; 420 uint32_t deviceCap2; 421 uint16_t deviceControl2; 422 uint16_t deviceStatus2; 423 uint32_t linkCap2; 424 uint16_t linkControl2; 425 uint16_t linkStatus2; 426 uint32_t slotCap2; 427 uint16_t slotControl2; 428 uint16_t slotStatus2; 429 }; 430 431 struct pci_msix_cap { 432 uint8_t cap_idd; 433 uint8_t next_cap; 434 uint16_t msg_control_reg; 435 uint32_t msix_table_offset; 436 uint32_t pba_offset; 437 }; 438 439 struct pci_header { 440 union { 441 struct pci_header_common common; 442 struct pci_header_zero zero; 443 struct pci_header_one one; 444 }; 445 }; 446 447 #endif /* VMD_SPEC_H */ 448