1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) Intel Corporation. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 35 #ifndef VMD_SPEC_H 36 #define VMD_SPEC_H 37 38 #define MAX_VMD_SUPPORTED 48 /* max number of vmd controllers in a system - */ 39 #define VMD_DOMAIN_START 0x201D 40 41 #define PCI_INVALID_VENDORID 0xFFFF 42 #define ONE_MB (1<<20) 43 #define PCI_OFFSET_OF(object, member) ((uint32_t)&((object*)0)->member) 44 #define TWOS_COMPLEMENT(value) (~(value) + 1) 45 46 #define VMD_UPPER_BASE_SIGNATURE 0xFFFFFFEF 47 #define VMD_UPPER_LIMIT_SIGNATURE 0xFFFFFFED 48 49 /* 50 * BAR assignment constants 51 */ 52 #define PCI_DWORD_SHIFT 32 53 #define PCI_BASE_ADDR_MASK 0xFFFFFFF0 54 #define PCI_BAR_MEMORY_MASK 0x0000000F 55 #define PCI_BAR_MEMORY_MEM_IND 0x1 56 #define PCI_BAR_MEMORY_TYPE 0x6 57 #define PCI_BAR_MEMORY_PREFETCH 0x8 58 #define PCI_BAR_MEMORY_TYPE_32 0x0 59 #define PCI_BAR_MEMORY_TYPE_64 0x4 60 #define PCI_BAR_MB_MASK 0xFFFFF 61 #define PCI_PCI_BRIDGE_ADDR_DEF 0xFFF0 62 #define PCI_BRIDGE_MEMORY_MASK 0xFFF0 63 #define PCI_BRIDGE_PREFETCH_64 0x0001 64 #define PCI_BRIDGE_MEMORY_SHIFT 16 65 #define PCI_CONFIG_ACCESS_DELAY 500 66 67 #define PCI_MAX_CFG_SIZE 0x1000 68 69 #define PCI_HEADER_TYPE 0x0e 70 #define PCI_HEADER_TYPE_NORMAL 0 71 #define PCI_HEADER_TYPE_BRIDGE 1 72 #define PCI_MULTI_FUNCTION 0x80 73 74 #define PCI_COMMAND_MEMORY 0x2 75 #define PCI_COMMAND_MASTER 0x4 76 77 #define PCIE_TYPE_FLAGS 0xf0 78 #define PCIE_TYPE_SHIFT 4 79 #define PCIE_TYPE_ROOT_PORT 0x4 80 #define PCIE_TYPE_DOWNSTREAM 0x6 81 82 #define PCI_CLASS_STORAGE_EXPRESS 0x010802 83 #define ADDR_ELEM_COUNT 32 84 #define PCI_MAX_BUS_NUMBER 0x7F 85 #define RESERVED_HOTPLUG_BUSES 1 86 #define isHotPlugCapable(slotCap) ((slotCap) & (1<<6)) 87 #define CONFIG_OFFSET_ADDR(bus, device, function, reg) (((bus)<<20) | (device)<<15 | (function<<12) | (reg)) 88 #define BRIDGE_BASEREG(reg) (0xFFF0 & ((reg)>>16)) 89 90 #define MISCCTRLSTS_0_OFFSET 0x188 91 #define ENABLE_ACPI_MODE_FOR_HOTPLUG (1 << 3) 92 93 /* Bit encodings for Command Register */ 94 #define IO_SPACE_ENABLE 0x0001 95 #define MEMORY_SPACE_ENABLE 0x0002 96 #define BUS_MASTER_ENABLE 0x0004 97 98 /* Bit encodings for Status Register */ 99 #define PCI_CAPABILITIES_LIST 0x0010 100 #define PCI_RECEIVED_TARGET_ABORT 0x1000 101 #define PCI_RECEIVED_MASTER_ABORT 0x2000 102 #define PCI_SIGNALED_SYSTEM_ERROR 0x4000 103 #define PCI_DETECTED_PARITY_ERROR 0x8000 104 105 /* Capability IDs */ 106 #define CAPABILITY_ID_POWER_MANAGEMENT 0x01 107 #define CAPABILITY_ID_MSI 0x05 108 #define CAPABILITY_ID_PCI_EXPRESS 0x10 109 #define CAPABILITY_ID_MSIX 0x11 110 111 #define PCI_MSIX_ENABLE (1 << 15) /* bit 15 of MSIX Message Control */ 112 #define PCI_MSIX_FUNCTION_MASK (1 << 14) /* bit 14 of MSIX Message Control */ 113 114 /* extended capability */ 115 #define EXTENDED_CAPABILITY_OFFSET 0x100 116 #define DEVICE_SERIAL_NUMBER_CAP_ID 0x3 117 118 #define BAR_SIZE (1 << 20) 119 120 struct pci_enhanced_capability_header { 121 uint16_t capability_id; 122 uint16_t version: 4; 123 uint16_t next: 12; 124 }; 125 126 struct serial_number_capability { 127 struct pci_enhanced_capability_header hdr; 128 uint32_t sn_low; 129 uint32_t sn_hi; 130 }; 131 132 struct pci_header_common { 133 uint16_t vendor_id; 134 uint16_t device_id; 135 uint16_t command; 136 uint16_t status; 137 uint32_t rev_class; 138 uint8_t cache_line_size; 139 uint8_t master_lat_timer; 140 uint8_t header_type; 141 uint8_t BIST; 142 uint8_t rsvd12[36]; 143 uint8_t cap_pointer; 144 uint8_t rsvd53[7]; 145 uint8_t int_line; 146 uint8_t int_pin; 147 uint8_t rsvd62[2]; 148 }; 149 150 struct pci_header_zero { 151 uint16_t vendor_id; 152 uint16_t device_id; 153 uint16_t command; 154 uint16_t status; 155 uint32_t rev_class; 156 uint8_t cache_line_size; 157 uint8_t master_lat_timer; 158 uint8_t header_type; 159 uint8_t BIST; 160 uint32_t BAR[6]; 161 uint32_t carbus_cis_pointer; 162 uint16_t ssvid; 163 uint16_t ssid; 164 uint32_t exp_rom_base_addr; 165 uint8_t cap_pointer; 166 uint8_t rsvd53[7]; 167 uint8_t intLine; 168 uint8_t int_pin; 169 uint8_t min_gnt; 170 uint8_t max_lat; 171 }; 172 173 struct pci_header_one { 174 uint16_t vendor_id; 175 uint16_t device_id; 176 uint16_t command; 177 uint16_t status; 178 uint32_t rev_class; 179 uint8_t cache_line_size; 180 uint8_t master_lat_timer; 181 uint8_t header_type; 182 uint8_t BIST; 183 uint32_t BAR[2]; 184 uint8_t primary; 185 uint8_t secondary; 186 uint8_t subordinate; 187 uint8_t secondary_lat_timer; 188 uint8_t io_base; 189 uint8_t io_limit; 190 uint16_t secondary_status; 191 uint16_t mem_base; 192 uint16_t mem_limit; 193 uint16_t prefetch_base; 194 uint16_t prefetch_limit; 195 uint32_t prefetch_base_upper; 196 uint32_t prefetch_limit_upper; 197 uint16_t io_base_upper; 198 uint16_t io_limit_upper; 199 uint8_t cap_pointer; 200 uint8_t rsvd53[3]; 201 uint32_t exp_romBase_addr; 202 uint8_t int_line; 203 uint8_t int_pin; 204 uint16_t bridge_control; 205 }; 206 207 struct pci_capabilities_header { 208 uint8_t capability_id; 209 uint8_t next; 210 }; 211 212 /* 213 * MSI capability structure for msi interrupt vectors 214 */ 215 #define MAX_MSIX_TABLE_SIZE 0x800 216 #define MSIX_ENTRY_VECTOR_CTRL_MASKBIT 1 217 #define PORT_INT_VECTOR 0; 218 #define CLEAR_MSIX_DESTINATION_ID 0xfff00fff 219 struct pci_msi_cap { 220 struct pci_capabilities_header header; 221 union _MsiControl { 222 uint16_t as_uint16_t; 223 struct _PCI_MSI_MESSAGE_CONTROL { 224 uint16_t msi_enable : 1; 225 uint16_t multiple_message_capable : 3; 226 uint16_t multiple_message_enable : 3; 227 uint16_t capable_of_64bits : 1; 228 uint16_t per_vector_mask_capable : 1; 229 uint16_t reserved : 7; 230 } bit; 231 } message_control; 232 union { 233 struct _PCI_MSI_MESSAGE_ADDRESS { 234 uint32_t reserved : 2; 235 uint32_t address : 30; 236 } reg; 237 uint32_t raw; 238 } message_address_lower; 239 union { 240 struct _Option32_bit { 241 uint16_t message_data; 242 } option32_bit; 243 struct _Option64_bit { 244 uint32_t message_address_upper; 245 uint16_t message_data; 246 uint16_t reserved; 247 uint32_t mask_bits; 248 uint32_t pending_bits; 249 } option64_bit; 250 }; 251 }; 252 253 struct pcix_table_pointer { 254 union { 255 struct { 256 uint32_t BaseIndexRegister : 3; 257 uint32_t Reserved : 29; 258 } TableBIR; 259 uint32_t TableOffset; 260 }; 261 }; 262 263 struct pci_msix_capability { 264 struct pci_capabilities_header header; 265 union _MsixControl { 266 uint16_t as_uint16_t; 267 struct msg_ctrl { 268 uint16_t table_size : 11; 269 uint16_t reserved : 3; 270 uint16_t function_mask : 1; 271 uint16_t msix_enable : 1; 272 } bit; 273 } message_control; 274 275 struct pcix_table_pointer message_table; 276 struct pcix_table_pointer pba_table; 277 }; 278 279 struct pci_msix_table_entry { 280 volatile uint32_t message_addr_lo; 281 volatile uint32_t message_addr_hi; 282 volatile uint32_t message_data; 283 volatile uint32_t vector_control; 284 }; 285 286 /* 287 * Pci express capability 288 */ 289 enum PciExpressCapabilities { 290 /* 0001b Legacy PCI Express Endpoint */ 291 LegacyEndpoint = 0x1, 292 /* 0000b PCI Express Endpoint */ 293 ExpressEndpoint = 0x0, 294 /* 0100b Root Port of PCI Express Root Complex* */ 295 RootComplexRootPort = 0x4, 296 /* 0101b Upstream Port of PCI Express Switch* */ 297 SwitchUpstreamPort = 0x5, 298 /* 0110b Downstream Port of PCI Express Switch* */ 299 SwitchDownStreamPort = 0x6, 300 /* 0111b PCI Express to PCI/PCI-X Bridge* */ 301 ExpressToPciBridge = 0x7, 302 /* 1000b PCI/PCI-X to PCI Express Bridge* */ 303 PciToExpressBridge = 0x8, 304 /* 1001b Root Complex Integrated Endpoint */ 305 RCIntegratedEndpoint = 0x9, 306 /* 1010b Root Complex Event Collector */ 307 RootComplexEventCollector = 0xa, 308 InvalidCapability = 0xff 309 }; 310 311 union express_capability_register { 312 struct { 313 uint16_t capability_version : 4; 314 uint16_t device_type : 4; 315 uint16_t slot_implemented : 1; 316 uint16_t interrupt_message_number : 5; 317 uint16_t rsv : 2; 318 } bit_field; 319 uint16_t as_uint16_t; 320 }; 321 322 union express_slot_capabilities_register { 323 struct { 324 uint32_t attention_button_present : 1; 325 uint32_t power_controller_present : 1; 326 uint32_t MRL_sensor_present : 1; 327 uint32_t attention_indicator_present : 1; 328 uint32_t power_indicator_present : 1; 329 uint32_t hotplug_surprise : 1; 330 uint32_t hotplug_capable : 1; 331 uint32_t slot_power_limit : 8; 332 uint32_t slotPower_limit_scale : 2; 333 uint32_t electromechanical_lock_present : 1; 334 uint32_t no_command_completed_support : 1; 335 uint32_t physical_slot_number : 13; 336 } bit_field; 337 uint32_t as_uint32_t; 338 }; 339 340 union express_slot_control_register { 341 struct { 342 uint16_t attention_button_enable : 1; 343 uint16_t power_fault_detect_enable : 1; 344 uint16_t MRLsensor_enable : 1; 345 uint16_t presence_detect_enable : 1; 346 uint16_t command_completed_enable : 1; 347 uint16_t hotplug_interrupt_enable : 1; 348 uint16_t attention_indicator_control : 2; 349 uint16_t power_indicator_control : 2; 350 uint16_t power_controller_control : 1; 351 uint16_t electromechanical_lockcontrol : 1; 352 uint16_t datalink_state_change_enable : 1; 353 uint16_t Rsvd : 3; 354 } bit_field; 355 uint16_t as_uint16_t; 356 }; 357 358 union express_slot_status_register { 359 struct { 360 uint16_t attention_button_pressed : 1; 361 uint16_t power_fault_detected : 1; 362 uint16_t MRL_sensor_changed : 1; 363 uint16_t presence_detect_changed : 1; 364 uint16_t command_completed : 1; 365 uint16_t MRL_sensor_state : 1; 366 uint16_t presence_detect_state : 1; 367 uint16_t electromechanical_lock_engaged : 1; 368 uint16_t datalink_state_changed : 1; 369 uint16_t rsvd : 7; 370 } bit_field; 371 uint16_t as_uint16_t; 372 }; 373 374 union express_root_control_register { 375 struct { 376 uint16_t CorrectableSerrEnable : 1; 377 uint16_t NonFatalSerrEnable : 1; 378 uint16_t FatalSerrEnable : 1; 379 uint16_t PMEInterruptEnable : 1; 380 uint16_t CRSSoftwareVisibilityEnable : 1; 381 uint16_t Rsvd : 11; 382 } bit_field; 383 uint16_t as_uint16_t; 384 }; 385 386 union express_link_capability_register { 387 struct { 388 uint32_t maximum_link_speed : 4; 389 uint32_t maximum_link_width : 6; 390 uint32_t active_state_pms_support : 2; 391 uint32_t l0_exit_latency : 3; 392 uint32_t l1_exit_latency : 3; 393 uint32_t clock_power_management : 1; 394 uint32_t surprise_down_error_reporting_capable : 1; 395 uint32_t datalink_layer_active_reporting_capable : 1; 396 uint32_t link_bandwidth_notification_capability : 1; 397 uint32_t aspm_optionality_compliance : 1; 398 uint32_t rsvd : 1; 399 uint32_t port_number : 8; 400 } bit_field; 401 uint32_t as_uint32_t; 402 }; 403 404 union express_link_control_register { 405 struct { 406 uint16_t active_state_pm_control : 2; 407 uint16_t rsvd1 : 1; 408 uint16_t read_completion_boundary : 1; 409 uint16_t link_disable : 1; 410 uint16_t retrain_link : 1; 411 uint16_t common_clock_config : 1; 412 uint16_t extended_synch : 1; 413 uint16_t enable_clock_power_management : 1; 414 uint16_t rsvd2 : 7; 415 } bit_field; 416 uint16_t as_uint16_t; 417 }; 418 419 union express_link_status_register { 420 struct { 421 uint16_t link_speed : 4; 422 uint16_t link_width : 6; 423 uint16_t undefined : 1; 424 uint16_t link_training : 1; 425 uint16_t slot_clock_config : 1; 426 uint16_t datalink_layer_active : 1; 427 uint16_t asvd : 2; 428 } bit_field; 429 uint16_t as_uint16_t; 430 }; 431 432 struct pci_express_cap { 433 uint8_t capid; 434 uint8_t next_cap; 435 union express_capability_register express_cap_register; 436 uint32_t device_cap; 437 uint16_t device_control; 438 uint16_t device_status; 439 union express_link_capability_register link_cap; 440 union express_link_control_register link_control; 441 union express_link_status_register link_status; 442 union express_slot_capabilities_register slot_cap; 443 union express_slot_control_register slot_control; 444 union express_slot_status_register slot_status; 445 uint32_t root_status; 446 uint32_t deviceCap2; 447 uint16_t deviceControl2; 448 uint16_t deviceStatus2; 449 uint32_t linkCap2; 450 uint16_t linkControl2; 451 uint16_t linkStatus2; 452 uint32_t slotCap2; 453 uint16_t slotControl2; 454 uint16_t slotStatus2; 455 }; 456 457 struct pci_msix_cap { 458 uint8_t cap_idd; 459 uint8_t next_cap; 460 uint16_t msg_control_reg; 461 uint32_t msix_table_offset; 462 uint32_t pba_offset; 463 }; 464 465 struct pci_header { 466 union { 467 struct pci_header_common common; 468 struct pci_header_zero zero; 469 struct pci_header_one one; 470 }; 471 }; 472 473 #endif /* VMD_SPEC_H */ 474