1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) Intel Corporation. All rights reserved. 3 * Copyright (c) 2020, 2021 Mellanox Technologies LTD. All rights reserved. 4 * Copyright (c) 2021, 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 5 */ 6 7 #ifndef __NVME_INTERNAL_H__ 8 #define __NVME_INTERNAL_H__ 9 10 #include "spdk/config.h" 11 #include "spdk/likely.h" 12 #include "spdk/stdinc.h" 13 14 #include "spdk/nvme.h" 15 16 #if defined(__i386__) || defined(__x86_64__) 17 #include <x86intrin.h> 18 #endif 19 20 #include "spdk/queue.h" 21 #include "spdk/barrier.h" 22 #include "spdk/bit_array.h" 23 #include "spdk/mmio.h" 24 #include "spdk/pci_ids.h" 25 #include "spdk/util.h" 26 #include "spdk/memory.h" 27 #include "spdk/nvme_intel.h" 28 #include "spdk/nvmf_spec.h" 29 #include "spdk/tree.h" 30 #include "spdk/uuid.h" 31 32 #include "spdk_internal/assert.h" 33 #include "spdk/log.h" 34 35 extern pid_t g_spdk_nvme_pid; 36 37 /* 38 * Some Intel devices support vendor-unique read latency log page even 39 * though the log page directory says otherwise. 40 */ 41 #define NVME_INTEL_QUIRK_READ_LATENCY 0x1 42 43 /* 44 * Some Intel devices support vendor-unique write latency log page even 45 * though the log page directory says otherwise. 46 */ 47 #define NVME_INTEL_QUIRK_WRITE_LATENCY 0x2 48 49 /* 50 * The controller needs a delay before starts checking the device 51 * readiness, which is done by reading the NVME_CSTS_RDY bit. 52 */ 53 #define NVME_QUIRK_DELAY_BEFORE_CHK_RDY 0x4 54 55 /* 56 * The controller performs best when I/O is split on particular 57 * LBA boundaries. 58 */ 59 #define NVME_INTEL_QUIRK_STRIPING 0x8 60 61 /* 62 * The controller needs a delay after allocating an I/O queue pair 63 * before it is ready to accept I/O commands. 64 */ 65 #define NVME_QUIRK_DELAY_AFTER_QUEUE_ALLOC 0x10 66 67 /* 68 * Earlier NVMe devices do not indicate whether unmapped blocks 69 * will read all zeroes or not. This define indicates that the 70 * device does in fact read all zeroes after an unmap event 71 */ 72 #define NVME_QUIRK_READ_ZERO_AFTER_DEALLOCATE 0x20 73 74 /* 75 * The controller doesn't handle Identify value others than 0 or 1 correctly. 76 */ 77 #define NVME_QUIRK_IDENTIFY_CNS 0x40 78 79 /* 80 * The controller supports Open Channel command set if matching additional 81 * condition, like the first byte (value 0x1) in the vendor specific 82 * bits of the namespace identify structure is set. 83 */ 84 #define NVME_QUIRK_OCSSD 0x80 85 86 /* 87 * The controller has an Intel vendor ID but does not support Intel vendor-specific 88 * log pages. This is primarily for QEMU emulated SSDs which report an Intel vendor 89 * ID but do not support these log pages. 90 */ 91 #define NVME_INTEL_QUIRK_NO_LOG_PAGES 0x100 92 93 /* 94 * The controller does not set SHST_COMPLETE in a reasonable amount of time. This 95 * is primarily seen in virtual VMWare NVMe SSDs. This quirk merely adds an additional 96 * error message that on VMWare NVMe SSDs, the shutdown timeout may be expected. 97 */ 98 #define NVME_QUIRK_SHST_COMPLETE 0x200 99 100 /* 101 * The controller requires an extra delay before starting the initialization process 102 * during attach. 103 */ 104 #define NVME_QUIRK_DELAY_BEFORE_INIT 0x400 105 106 /* 107 * Some SSDs exhibit poor performance with the default SPDK NVMe IO queue size. 108 * This quirk will increase the default to 1024 which matches other operating 109 * systems, at the cost of some extra memory usage. Users can still override 110 * the increased default by changing the spdk_nvme_io_qpair_opts when allocating 111 * a new queue pair. 112 */ 113 #define NVME_QUIRK_MINIMUM_IO_QUEUE_SIZE 0x800 114 115 /** 116 * The maximum access width to PCI memory space is 8 Bytes, don't use AVX2 or 117 * SSE instructions to optimize the memory access(memcpy or memset) larger than 118 * 8 Bytes. 119 */ 120 #define NVME_QUIRK_MAXIMUM_PCI_ACCESS_WIDTH 0x1000 121 122 /** 123 * The SSD does not support OPAL even through it sets the security bit in OACS. 124 */ 125 #define NVME_QUIRK_OACS_SECURITY 0x2000 126 127 /** 128 * Intel P55XX SSDs can't support Dataset Management command with SGL format, 129 * so use PRP with DSM command. 130 */ 131 #define NVME_QUIRK_NO_SGL_FOR_DSM 0x4000 132 133 /** 134 * Maximum Data Transfer Size(MDTS) excludes interleaved metadata. 135 */ 136 #define NVME_QUIRK_MDTS_EXCLUDE_MD 0x8000 137 138 /** 139 * Force not to use SGL even the controller report that it can 140 * support it. 141 */ 142 #define NVME_QUIRK_NOT_USE_SGL 0x10000 143 144 #define NVME_MAX_ASYNC_EVENTS (8) 145 146 #define NVME_MAX_ADMIN_TIMEOUT_IN_SECS (30) 147 148 /* Maximum log page size to fetch for AERs. */ 149 #define NVME_MAX_AER_LOG_SIZE (4096) 150 151 /* 152 * NVME_MAX_IO_QUEUES in nvme_spec.h defines the 64K spec-limit, but this 153 * define specifies the maximum number of queues this driver will actually 154 * try to configure, if available. 155 */ 156 #define DEFAULT_MAX_IO_QUEUES (1024) 157 #define DEFAULT_ADMIN_QUEUE_SIZE (32) 158 #define DEFAULT_IO_QUEUE_SIZE (256) 159 #define DEFAULT_IO_QUEUE_SIZE_FOR_QUIRK (1024) /* Matches Linux kernel driver */ 160 161 #define DEFAULT_IO_QUEUE_REQUESTS (512) 162 163 #define SPDK_NVME_DEFAULT_RETRY_COUNT (4) 164 165 #define SPDK_NVME_TRANSPORT_ACK_TIMEOUT_DISABLED (0) 166 #define SPDK_NVME_DEFAULT_TRANSPORT_ACK_TIMEOUT SPDK_NVME_TRANSPORT_ACK_TIMEOUT_DISABLED 167 168 #define MIN_KEEP_ALIVE_TIMEOUT_IN_MS (10000) 169 170 /* We want to fit submission and completion rings each in a single 2MB 171 * hugepage to ensure physical address contiguity. 172 */ 173 #define MAX_IO_QUEUE_ENTRIES (VALUE_2MB / spdk_max( \ 174 sizeof(struct spdk_nvme_cmd), \ 175 sizeof(struct spdk_nvme_cpl))) 176 177 /* Default timeout for fabrics connect commands. */ 178 #ifdef DEBUG 179 #define NVME_FABRIC_CONNECT_COMMAND_TIMEOUT 0 180 #else 181 /* 500 millisecond timeout. */ 182 #define NVME_FABRIC_CONNECT_COMMAND_TIMEOUT 500000 183 #endif 184 185 /* This value indicates that a read from a PCIe register is invalid. This can happen when a device is no longer present */ 186 #define SPDK_NVME_INVALID_REGISTER_VALUE 0xFFFFFFFFu 187 188 enum nvme_payload_type { 189 NVME_PAYLOAD_TYPE_INVALID = 0, 190 191 /** nvme_request::u.payload.contig_buffer is valid for this request */ 192 NVME_PAYLOAD_TYPE_CONTIG, 193 194 /** nvme_request::u.sgl is valid for this request */ 195 NVME_PAYLOAD_TYPE_SGL, 196 }; 197 198 /** Boot partition write states */ 199 enum nvme_bp_write_state { 200 SPDK_NVME_BP_WS_DOWNLOADING = 0x0, 201 SPDK_NVME_BP_WS_DOWNLOADED = 0x1, 202 SPDK_NVME_BP_WS_REPLACE = 0x2, 203 SPDK_NVME_BP_WS_ACTIVATE = 0x3, 204 }; 205 206 /** 207 * Descriptor for a request data payload. 208 */ 209 struct nvme_payload { 210 /** 211 * Functions for retrieving physical addresses for scattered payloads. 212 */ 213 spdk_nvme_req_reset_sgl_cb reset_sgl_fn; 214 spdk_nvme_req_next_sge_cb next_sge_fn; 215 216 /** 217 * Extended IO options passed by the user 218 */ 219 struct spdk_nvme_ns_cmd_ext_io_opts *opts; 220 /** 221 * If reset_sgl_fn == NULL, this is a contig payload, and contig_or_cb_arg contains the 222 * virtual memory address of a single virtually contiguous buffer. 223 * 224 * If reset_sgl_fn != NULL, this is a SGL payload, and contig_or_cb_arg contains the 225 * cb_arg that will be passed to the SGL callback functions. 226 */ 227 void *contig_or_cb_arg; 228 229 /** Virtual memory address of a single virtually contiguous metadata buffer */ 230 void *md; 231 }; 232 233 #define NVME_PAYLOAD_CONTIG(contig_, md_) \ 234 (struct nvme_payload) { \ 235 .reset_sgl_fn = NULL, \ 236 .next_sge_fn = NULL, \ 237 .contig_or_cb_arg = (contig_), \ 238 .md = (md_), \ 239 } 240 241 #define NVME_PAYLOAD_SGL(reset_sgl_fn_, next_sge_fn_, cb_arg_, md_) \ 242 (struct nvme_payload) { \ 243 .reset_sgl_fn = (reset_sgl_fn_), \ 244 .next_sge_fn = (next_sge_fn_), \ 245 .contig_or_cb_arg = (cb_arg_), \ 246 .md = (md_), \ 247 } 248 249 static inline enum nvme_payload_type 250 nvme_payload_type(const struct nvme_payload *payload) { 251 return payload->reset_sgl_fn ? NVME_PAYLOAD_TYPE_SGL : NVME_PAYLOAD_TYPE_CONTIG; 252 } 253 254 struct nvme_error_cmd { 255 bool do_not_submit; 256 uint64_t timeout_tsc; 257 uint32_t err_count; 258 uint8_t opc; 259 struct spdk_nvme_status status; 260 TAILQ_ENTRY(nvme_error_cmd) link; 261 }; 262 263 struct nvme_request { 264 struct spdk_nvme_cmd cmd; 265 266 uint8_t retries; 267 268 uint8_t timed_out : 1; 269 270 /** 271 * True if the request is in the queued_req list. 272 */ 273 uint8_t queued : 1; 274 uint8_t reserved : 6; 275 276 /** 277 * Number of children requests still outstanding for this 278 * request which was split into multiple child requests. 279 */ 280 uint16_t num_children; 281 282 /** 283 * Offset in bytes from the beginning of payload for this request. 284 * This is used for I/O commands that are split into multiple requests. 285 */ 286 uint32_t payload_offset; 287 uint32_t md_offset; 288 289 uint32_t payload_size; 290 291 /** 292 * Timeout ticks for error injection requests, can be extended in future 293 * to support per-request timeout feature. 294 */ 295 uint64_t timeout_tsc; 296 297 /** 298 * Data payload for this request's command. 299 */ 300 struct nvme_payload payload; 301 302 spdk_nvme_cmd_cb cb_fn; 303 void *cb_arg; 304 STAILQ_ENTRY(nvme_request) stailq; 305 306 struct spdk_nvme_qpair *qpair; 307 308 /* 309 * The value of spdk_get_ticks() when the request was submitted to the hardware. 310 * Only set if ctrlr->timeout_enabled is true. 311 */ 312 uint64_t submit_tick; 313 314 /** 315 * The active admin request can be moved to a per process pending 316 * list based on the saved pid to tell which process it belongs 317 * to. The cpl saves the original completion information which 318 * is used in the completion callback. 319 * NOTE: these below two fields are only used for admin request. 320 */ 321 pid_t pid; 322 struct spdk_nvme_cpl cpl; 323 324 uint32_t md_size; 325 326 /** 327 * The following members should not be reordered with members 328 * above. These members are only needed when splitting 329 * requests which is done rarely, and the driver is careful 330 * to not touch the following fields until a split operation is 331 * needed, to avoid touching an extra cacheline. 332 */ 333 334 /** 335 * Points to the outstanding child requests for a parent request. 336 * Only valid if a request was split into multiple children 337 * requests, and is not initialized for non-split requests. 338 */ 339 TAILQ_HEAD(, nvme_request) children; 340 341 /** 342 * Linked-list pointers for a child request in its parent's list. 343 */ 344 TAILQ_ENTRY(nvme_request) child_tailq; 345 346 /** 347 * Points to a parent request if part of a split request, 348 * NULL otherwise. 349 */ 350 struct nvme_request *parent; 351 352 /** 353 * Completion status for a parent request. Initialized to all 0's 354 * (SUCCESS) before child requests are submitted. If a child 355 * request completes with error, the error status is copied here, 356 * to ensure that the parent request is also completed with error 357 * status once all child requests are completed. 358 */ 359 struct spdk_nvme_cpl parent_status; 360 361 /** 362 * The user_cb_fn and user_cb_arg fields are used for holding the original 363 * callback data when using nvme_allocate_request_user_copy. 364 */ 365 spdk_nvme_cmd_cb user_cb_fn; 366 void *user_cb_arg; 367 void *user_buffer; 368 }; 369 370 struct nvme_completion_poll_status { 371 struct spdk_nvme_cpl cpl; 372 uint64_t timeout_tsc; 373 /** 374 * DMA buffer retained throughout the duration of the command. It'll be released 375 * automatically if the command times out, otherwise the user is responsible for freeing it. 376 */ 377 void *dma_data; 378 bool done; 379 /* This flag indicates that the request has been timed out and the memory 380 must be freed in a completion callback */ 381 bool timed_out; 382 }; 383 384 struct nvme_async_event_request { 385 struct spdk_nvme_ctrlr *ctrlr; 386 struct nvme_request *req; 387 struct spdk_nvme_cpl cpl; 388 }; 389 390 enum nvme_qpair_state { 391 NVME_QPAIR_DISCONNECTED, 392 NVME_QPAIR_DISCONNECTING, 393 NVME_QPAIR_CONNECTING, 394 NVME_QPAIR_CONNECTED, 395 NVME_QPAIR_ENABLING, 396 NVME_QPAIR_ENABLED, 397 NVME_QPAIR_DESTROYING, 398 }; 399 400 struct spdk_nvme_qpair { 401 struct spdk_nvme_ctrlr *ctrlr; 402 403 uint16_t id; 404 405 uint8_t qprio; 406 407 uint8_t state : 3; 408 409 uint8_t async: 1; 410 411 uint8_t is_new_qpair: 1; 412 413 /* 414 * Members for handling IO qpair deletion inside of a completion context. 415 * These are specifically defined as single bits, so that they do not 416 * push this data structure out to another cacheline. 417 */ 418 uint8_t in_completion_context : 1; 419 uint8_t delete_after_completion_context: 1; 420 421 /* 422 * Set when no deletion notification is needed. For example, the process 423 * which allocated this qpair exited unexpectedly. 424 */ 425 uint8_t no_deletion_notification_needed: 1; 426 427 uint8_t last_fuse: 2; 428 429 uint8_t transport_failure_reason: 2; 430 uint8_t last_transport_failure_reason: 2; 431 432 enum spdk_nvme_transport_type trtype; 433 434 /* request object used only for this qpair's FABRICS/CONNECT command (if needed) */ 435 struct nvme_request *reserved_req; 436 437 STAILQ_HEAD(, nvme_request) free_req; 438 STAILQ_HEAD(, nvme_request) queued_req; 439 440 /* List entry for spdk_nvme_transport_poll_group::qpairs */ 441 STAILQ_ENTRY(spdk_nvme_qpair) poll_group_stailq; 442 443 /** Commands opcode in this list will return error */ 444 TAILQ_HEAD(, nvme_error_cmd) err_cmd_head; 445 /** Requests in this list will return error */ 446 STAILQ_HEAD(, nvme_request) err_req_head; 447 448 struct spdk_nvme_ctrlr_process *active_proc; 449 450 struct spdk_nvme_transport_poll_group *poll_group; 451 452 void *poll_group_tailq_head; 453 454 const struct spdk_nvme_transport *transport; 455 456 /* Entries below here are not touched in the main I/O path. */ 457 458 struct nvme_completion_poll_status *poll_status; 459 460 /* List entry for spdk_nvme_ctrlr::active_io_qpairs */ 461 TAILQ_ENTRY(spdk_nvme_qpair) tailq; 462 463 /* List entry for spdk_nvme_ctrlr_process::allocated_io_qpairs */ 464 TAILQ_ENTRY(spdk_nvme_qpair) per_process_tailq; 465 466 STAILQ_HEAD(, nvme_request) aborting_queued_req; 467 468 void *req_buf; 469 }; 470 471 struct spdk_nvme_poll_group { 472 void *ctx; 473 struct spdk_nvme_accel_fn_table accel_fn_table; 474 STAILQ_HEAD(, spdk_nvme_transport_poll_group) tgroups; 475 }; 476 477 struct spdk_nvme_transport_poll_group { 478 struct spdk_nvme_poll_group *group; 479 const struct spdk_nvme_transport *transport; 480 STAILQ_HEAD(, spdk_nvme_qpair) connected_qpairs; 481 STAILQ_HEAD(, spdk_nvme_qpair) disconnected_qpairs; 482 STAILQ_ENTRY(spdk_nvme_transport_poll_group) link; 483 }; 484 485 struct spdk_nvme_ns { 486 struct spdk_nvme_ctrlr *ctrlr; 487 uint32_t sector_size; 488 489 /* 490 * Size of data transferred as part of each block, 491 * including metadata if FLBAS indicates the metadata is transferred 492 * as part of the data buffer at the end of each LBA. 493 */ 494 uint32_t extended_lba_size; 495 496 uint32_t md_size; 497 uint32_t pi_type; 498 uint32_t sectors_per_max_io; 499 uint32_t sectors_per_max_io_no_md; 500 uint32_t sectors_per_stripe; 501 uint32_t id; 502 uint16_t flags; 503 bool active; 504 505 /* Command Set Identifier */ 506 enum spdk_nvme_csi csi; 507 508 /* Namespace Identification Descriptor List (CNS = 03h) */ 509 uint8_t id_desc_list[4096]; 510 511 uint32_t ana_group_id; 512 enum spdk_nvme_ana_state ana_state; 513 514 /* Identify Namespace data. */ 515 struct spdk_nvme_ns_data nsdata; 516 517 /* Zoned Namespace Command Set Specific Identify Namespace data. */ 518 struct spdk_nvme_zns_ns_data *nsdata_zns; 519 520 RB_ENTRY(spdk_nvme_ns) node; 521 }; 522 523 /** 524 * State of struct spdk_nvme_ctrlr (in particular, during initialization). 525 */ 526 enum nvme_ctrlr_state { 527 /** 528 * Wait before initializing the controller. 529 */ 530 NVME_CTRLR_STATE_INIT_DELAY, 531 532 /** 533 * Connect the admin queue. 534 */ 535 NVME_CTRLR_STATE_CONNECT_ADMINQ, 536 537 /** 538 * Controller has not started initialized yet. 539 */ 540 NVME_CTRLR_STATE_INIT = NVME_CTRLR_STATE_CONNECT_ADMINQ, 541 542 /** 543 * Waiting for admin queue to connect. 544 */ 545 NVME_CTRLR_STATE_WAIT_FOR_CONNECT_ADMINQ, 546 547 /** 548 * Read Version (VS) register. 549 */ 550 NVME_CTRLR_STATE_READ_VS, 551 552 /** 553 * Waiting for Version (VS) register to be read. 554 */ 555 NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS, 556 557 /** 558 * Read Capabilities (CAP) register. 559 */ 560 NVME_CTRLR_STATE_READ_CAP, 561 562 /** 563 * Waiting for Capabilities (CAP) register to be read. 564 */ 565 NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP, 566 567 /** 568 * Check EN to prepare for controller initialization. 569 */ 570 NVME_CTRLR_STATE_CHECK_EN, 571 572 /** 573 * Waiting for CC to be read as part of EN check. 574 */ 575 NVME_CTRLR_STATE_CHECK_EN_WAIT_FOR_CC, 576 577 /** 578 * Waiting for CSTS.RDY to transition from 0 to 1 so that CC.EN may be set to 0. 579 */ 580 NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1, 581 582 /** 583 * Waiting for CSTS register to be read as part of waiting for CSTS.RDY = 1. 584 */ 585 NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS, 586 587 /** 588 * Disabling the controller by setting CC.EN to 0. 589 */ 590 NVME_CTRLR_STATE_SET_EN_0, 591 592 /** 593 * Waiting for the CC register to be read as part of disabling the controller. 594 */ 595 NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC, 596 597 /** 598 * Waiting for CSTS.RDY to transition from 1 to 0 so that CC.EN may be set to 1. 599 */ 600 NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0, 601 602 /** 603 * Waiting for CSTS register to be read as part of waiting for CSTS.RDY = 0. 604 */ 605 NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS, 606 607 /** 608 * The controller is disabled. (CC.EN and CSTS.RDY are 0.) 609 */ 610 NVME_CTRLR_STATE_DISABLED, 611 612 /** 613 * Enable the controller by writing CC.EN to 1 614 */ 615 NVME_CTRLR_STATE_ENABLE, 616 617 /** 618 * Waiting for CC register to be written as part of enabling the controller. 619 */ 620 NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC, 621 622 /** 623 * Waiting for CSTS.RDY to transition from 0 to 1 after enabling the controller. 624 */ 625 NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1, 626 627 /** 628 * Waiting for CSTS register to be read as part of waiting for CSTS.RDY = 1. 629 */ 630 NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS, 631 632 /** 633 * Reset the Admin queue of the controller. 634 */ 635 NVME_CTRLR_STATE_RESET_ADMIN_QUEUE, 636 637 /** 638 * Identify Controller command will be sent to then controller. 639 */ 640 NVME_CTRLR_STATE_IDENTIFY, 641 642 /** 643 * Waiting for Identify Controller command be completed. 644 */ 645 NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY, 646 647 /** 648 * Configure AER of the controller. 649 */ 650 NVME_CTRLR_STATE_CONFIGURE_AER, 651 652 /** 653 * Waiting for the Configure AER to be completed. 654 */ 655 NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER, 656 657 /** 658 * Set Keep Alive Timeout of the controller. 659 */ 660 NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT, 661 662 /** 663 * Waiting for Set Keep Alive Timeout to be completed. 664 */ 665 NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT, 666 667 /** 668 * Get Identify I/O Command Set Specific Controller data structure. 669 */ 670 NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC, 671 672 /** 673 * Waiting for Identify I/O Command Set Specific Controller command to be completed. 674 */ 675 NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC, 676 677 /** 678 * Get Commands Supported and Effects log page for the Zoned Namespace Command Set. 679 */ 680 NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG, 681 682 /** 683 * Waiting for the Get Log Page command to be completed. 684 */ 685 NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG, 686 687 /** 688 * Set Number of Queues of the controller. 689 */ 690 NVME_CTRLR_STATE_SET_NUM_QUEUES, 691 692 /** 693 * Waiting for Set Num of Queues command to be completed. 694 */ 695 NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES, 696 697 /** 698 * Get active Namespace list of the controller. 699 */ 700 NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS, 701 702 /** 703 * Waiting for the Identify Active Namespace commands to be completed. 704 */ 705 NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS, 706 707 /** 708 * Get Identify Namespace Data structure for each NS. 709 */ 710 NVME_CTRLR_STATE_IDENTIFY_NS, 711 712 /** 713 * Waiting for the Identify Namespace commands to be completed. 714 */ 715 NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS, 716 717 /** 718 * Get Identify Namespace Identification Descriptors. 719 */ 720 NVME_CTRLR_STATE_IDENTIFY_ID_DESCS, 721 722 /** 723 * Get Identify I/O Command Set Specific Namespace data structure for each NS. 724 */ 725 NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC, 726 727 /** 728 * Waiting for the Identify I/O Command Set Specific Namespace commands to be completed. 729 */ 730 NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC, 731 732 /** 733 * Waiting for the Identify Namespace Identification 734 * Descriptors to be completed. 735 */ 736 NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS, 737 738 /** 739 * Set supported log pages of the controller. 740 */ 741 NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES, 742 743 /** 744 * Set supported log pages of INTEL controller. 745 */ 746 NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES, 747 748 /** 749 * Waiting for supported log pages of INTEL controller. 750 */ 751 NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES, 752 753 /** 754 * Set supported features of the controller. 755 */ 756 NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES, 757 758 /** 759 * Set Doorbell Buffer Config of the controller. 760 */ 761 NVME_CTRLR_STATE_SET_DB_BUF_CFG, 762 763 /** 764 * Waiting for Doorbell Buffer Config to be completed. 765 */ 766 NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG, 767 768 /** 769 * Set Host ID of the controller. 770 */ 771 NVME_CTRLR_STATE_SET_HOST_ID, 772 773 /** 774 * Waiting for Set Host ID to be completed. 775 */ 776 NVME_CTRLR_STATE_WAIT_FOR_HOST_ID, 777 778 /** 779 * Let transport layer do its part of initialization. 780 */ 781 NVME_CTRLR_STATE_TRANSPORT_READY, 782 783 /** 784 * Controller initialization has completed and the controller is ready. 785 */ 786 NVME_CTRLR_STATE_READY, 787 788 /** 789 * Controller initialization has an error. 790 */ 791 NVME_CTRLR_STATE_ERROR 792 }; 793 794 #define NVME_TIMEOUT_INFINITE 0 795 #define NVME_TIMEOUT_KEEP_EXISTING UINT64_MAX 796 797 struct spdk_nvme_ctrlr_aer_completion_list { 798 struct spdk_nvme_cpl cpl; 799 STAILQ_ENTRY(spdk_nvme_ctrlr_aer_completion_list) link; 800 }; 801 802 /* 803 * Used to track properties for all processes accessing the controller. 804 */ 805 struct spdk_nvme_ctrlr_process { 806 /** Whether it is the primary process */ 807 bool is_primary; 808 809 /** Process ID */ 810 pid_t pid; 811 812 /** Active admin requests to be completed */ 813 STAILQ_HEAD(, nvme_request) active_reqs; 814 815 TAILQ_ENTRY(spdk_nvme_ctrlr_process) tailq; 816 817 /** Per process PCI device handle */ 818 struct spdk_pci_device *devhandle; 819 820 /** Reference to track the number of attachment to this controller. */ 821 int ref; 822 823 /** Allocated IO qpairs */ 824 TAILQ_HEAD(, spdk_nvme_qpair) allocated_io_qpairs; 825 826 spdk_nvme_aer_cb aer_cb_fn; 827 void *aer_cb_arg; 828 829 /** 830 * A function pointer to timeout callback function 831 */ 832 spdk_nvme_timeout_cb timeout_cb_fn; 833 void *timeout_cb_arg; 834 /** separate timeout values for io vs. admin reqs */ 835 uint64_t timeout_io_ticks; 836 uint64_t timeout_admin_ticks; 837 838 /** List to publish AENs to all procs in multiprocess setup */ 839 STAILQ_HEAD(, spdk_nvme_ctrlr_aer_completion_list) async_events; 840 }; 841 842 struct nvme_register_completion { 843 struct spdk_nvme_cpl cpl; 844 uint64_t value; 845 spdk_nvme_reg_cb cb_fn; 846 void *cb_ctx; 847 STAILQ_ENTRY(nvme_register_completion) stailq; 848 }; 849 850 /* 851 * One of these per allocated PCI device. 852 */ 853 struct spdk_nvme_ctrlr { 854 /* Hot data (accessed in I/O path) starts here. */ 855 856 /* Tree of namespaces */ 857 RB_HEAD(nvme_ns_tree, spdk_nvme_ns) ns; 858 859 /* The number of active namespaces */ 860 uint32_t active_ns_count; 861 862 bool is_removed; 863 864 bool is_resetting; 865 866 bool is_failed; 867 868 bool is_destructed; 869 870 bool timeout_enabled; 871 872 /* The application is preparing to reset the controller. Transports 873 * can use this to skip unnecessary parts of the qpair deletion process 874 * for example, like the DELETE_SQ/CQ commands. 875 */ 876 bool prepare_for_reset; 877 878 bool is_disconnecting; 879 880 uint16_t max_sges; 881 882 uint16_t cntlid; 883 884 /** Controller support flags */ 885 uint64_t flags; 886 887 /** NVMEoF in-capsule data size in bytes */ 888 uint32_t ioccsz_bytes; 889 890 /** NVMEoF in-capsule data offset in 16 byte units */ 891 uint16_t icdoff; 892 893 /* Cold data (not accessed in normal I/O path) is after this point. */ 894 895 struct spdk_nvme_transport_id trid; 896 897 union spdk_nvme_cap_register cap; 898 union spdk_nvme_vs_register vs; 899 900 int state; 901 uint64_t state_timeout_tsc; 902 903 uint64_t next_keep_alive_tick; 904 uint64_t keep_alive_interval_ticks; 905 906 TAILQ_ENTRY(spdk_nvme_ctrlr) tailq; 907 908 /** All the log pages supported */ 909 bool log_page_supported[256]; 910 911 /** All the features supported */ 912 bool feature_supported[256]; 913 914 /** maximum i/o size in bytes */ 915 uint32_t max_xfer_size; 916 917 /** minimum page size supported by this controller in bytes */ 918 uint32_t min_page_size; 919 920 /** selected memory page size for this controller in bytes */ 921 uint32_t page_size; 922 923 uint32_t num_aers; 924 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS]; 925 926 /** guards access to the controller itself, including admin queues */ 927 pthread_mutex_t ctrlr_lock; 928 929 struct spdk_nvme_qpair *adminq; 930 931 /** shadow doorbell buffer */ 932 uint32_t *shadow_doorbell; 933 /** eventidx buffer */ 934 uint32_t *eventidx; 935 936 /** 937 * Identify Controller data. 938 */ 939 struct spdk_nvme_ctrlr_data cdata; 940 941 /** 942 * Zoned Namespace Command Set Specific Identify Controller data. 943 */ 944 struct spdk_nvme_zns_ctrlr_data *cdata_zns; 945 946 struct spdk_bit_array *free_io_qids; 947 TAILQ_HEAD(, spdk_nvme_qpair) active_io_qpairs; 948 949 struct spdk_nvme_ctrlr_opts opts; 950 951 uint64_t quirks; 952 953 /* Extra sleep time during controller initialization */ 954 uint64_t sleep_timeout_tsc; 955 956 /** Track all the processes manage this controller */ 957 TAILQ_HEAD(, spdk_nvme_ctrlr_process) active_procs; 958 959 960 STAILQ_HEAD(, nvme_request) queued_aborts; 961 uint32_t outstanding_aborts; 962 963 /* CB to notify the user when the ctrlr is removed/failed. */ 964 spdk_nvme_remove_cb remove_cb; 965 void *cb_ctx; 966 967 struct spdk_nvme_qpair *external_io_msgs_qpair; 968 pthread_mutex_t external_io_msgs_lock; 969 struct spdk_ring *external_io_msgs; 970 971 STAILQ_HEAD(, nvme_io_msg_producer) io_producers; 972 973 struct spdk_nvme_ana_page *ana_log_page; 974 struct spdk_nvme_ana_group_descriptor *copied_ana_desc; 975 uint32_t ana_log_page_size; 976 977 /* scratchpad pointer that can be used to send data between two NVME_CTRLR_STATEs */ 978 void *tmp_ptr; 979 980 /* maximum zone append size in bytes */ 981 uint32_t max_zone_append_size; 982 983 /* PMR size in bytes */ 984 uint64_t pmr_size; 985 986 /* Boot Partition Info */ 987 enum nvme_bp_write_state bp_ws; 988 uint32_t bpid; 989 spdk_nvme_cmd_cb bp_write_cb_fn; 990 void *bp_write_cb_arg; 991 992 /* Firmware Download */ 993 void *fw_payload; 994 unsigned int fw_size_remaining; 995 unsigned int fw_offset; 996 unsigned int fw_transfer_size; 997 998 /* Completed register operations */ 999 STAILQ_HEAD(, nvme_register_completion) register_operations; 1000 1001 union spdk_nvme_cc_register process_init_cc; 1002 }; 1003 1004 struct spdk_nvme_probe_ctx { 1005 struct spdk_nvme_transport_id trid; 1006 void *cb_ctx; 1007 spdk_nvme_probe_cb probe_cb; 1008 spdk_nvme_attach_cb attach_cb; 1009 spdk_nvme_remove_cb remove_cb; 1010 TAILQ_HEAD(, spdk_nvme_ctrlr) init_ctrlrs; 1011 }; 1012 1013 typedef void (*nvme_ctrlr_detach_cb)(struct spdk_nvme_ctrlr *ctrlr); 1014 1015 enum nvme_ctrlr_detach_state { 1016 NVME_CTRLR_DETACH_SET_CC, 1017 NVME_CTRLR_DETACH_CHECK_CSTS, 1018 NVME_CTRLR_DETACH_GET_CSTS, 1019 NVME_CTRLR_DETACH_GET_CSTS_DONE, 1020 }; 1021 1022 struct nvme_ctrlr_detach_ctx { 1023 struct spdk_nvme_ctrlr *ctrlr; 1024 nvme_ctrlr_detach_cb cb_fn; 1025 uint64_t shutdown_start_tsc; 1026 uint32_t shutdown_timeout_ms; 1027 bool shutdown_complete; 1028 enum nvme_ctrlr_detach_state state; 1029 union spdk_nvme_csts_register csts; 1030 TAILQ_ENTRY(nvme_ctrlr_detach_ctx) link; 1031 }; 1032 1033 struct spdk_nvme_detach_ctx { 1034 TAILQ_HEAD(, nvme_ctrlr_detach_ctx) head; 1035 }; 1036 1037 struct nvme_driver { 1038 pthread_mutex_t lock; 1039 1040 /** Multi-process shared attached controller list */ 1041 TAILQ_HEAD(, spdk_nvme_ctrlr) shared_attached_ctrlrs; 1042 1043 bool initialized; 1044 struct spdk_uuid default_extended_host_id; 1045 1046 /** netlink socket fd for hotplug messages */ 1047 int hotplug_fd; 1048 }; 1049 1050 extern struct nvme_driver *g_spdk_nvme_driver; 1051 1052 int nvme_driver_init(void); 1053 1054 #define nvme_delay usleep 1055 1056 static inline bool 1057 nvme_qpair_is_admin_queue(struct spdk_nvme_qpair *qpair) 1058 { 1059 return qpair->id == 0; 1060 } 1061 1062 static inline bool 1063 nvme_qpair_is_io_queue(struct spdk_nvme_qpair *qpair) 1064 { 1065 return qpair->id != 0; 1066 } 1067 1068 static inline int 1069 nvme_robust_mutex_lock(pthread_mutex_t *mtx) 1070 { 1071 int rc = pthread_mutex_lock(mtx); 1072 1073 #ifndef __FreeBSD__ 1074 if (rc == EOWNERDEAD) { 1075 rc = pthread_mutex_consistent(mtx); 1076 } 1077 #endif 1078 1079 return rc; 1080 } 1081 1082 static inline int 1083 nvme_robust_mutex_unlock(pthread_mutex_t *mtx) 1084 { 1085 return pthread_mutex_unlock(mtx); 1086 } 1087 1088 /* Poll group management functions. */ 1089 int nvme_poll_group_connect_qpair(struct spdk_nvme_qpair *qpair); 1090 int nvme_poll_group_disconnect_qpair(struct spdk_nvme_qpair *qpair); 1091 1092 /* Admin functions */ 1093 int nvme_ctrlr_cmd_identify(struct spdk_nvme_ctrlr *ctrlr, 1094 uint8_t cns, uint16_t cntid, uint32_t nsid, 1095 uint8_t csi, void *payload, size_t payload_size, 1096 spdk_nvme_cmd_cb cb_fn, void *cb_arg); 1097 int nvme_ctrlr_cmd_set_num_queues(struct spdk_nvme_ctrlr *ctrlr, 1098 uint32_t num_queues, spdk_nvme_cmd_cb cb_fn, 1099 void *cb_arg); 1100 int nvme_ctrlr_cmd_get_num_queues(struct spdk_nvme_ctrlr *ctrlr, 1101 spdk_nvme_cmd_cb cb_fn, void *cb_arg); 1102 int nvme_ctrlr_cmd_set_async_event_config(struct spdk_nvme_ctrlr *ctrlr, 1103 union spdk_nvme_feat_async_event_configuration config, 1104 spdk_nvme_cmd_cb cb_fn, void *cb_arg); 1105 int nvme_ctrlr_cmd_set_host_id(struct spdk_nvme_ctrlr *ctrlr, void *host_id, uint32_t host_id_size, 1106 spdk_nvme_cmd_cb cb_fn, void *cb_arg); 1107 int nvme_ctrlr_cmd_attach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, 1108 struct spdk_nvme_ctrlr_list *payload, spdk_nvme_cmd_cb cb_fn, void *cb_arg); 1109 int nvme_ctrlr_cmd_detach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, 1110 struct spdk_nvme_ctrlr_list *payload, spdk_nvme_cmd_cb cb_fn, void *cb_arg); 1111 int nvme_ctrlr_cmd_create_ns(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_ns_data *payload, 1112 spdk_nvme_cmd_cb cb_fn, void *cb_arg); 1113 int nvme_ctrlr_cmd_doorbell_buffer_config(struct spdk_nvme_ctrlr *ctrlr, 1114 uint64_t prp1, uint64_t prp2, 1115 spdk_nvme_cmd_cb cb_fn, void *cb_arg); 1116 int nvme_ctrlr_cmd_delete_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, spdk_nvme_cmd_cb cb_fn, 1117 void *cb_arg); 1118 int nvme_ctrlr_cmd_format(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, 1119 struct spdk_nvme_format *format, spdk_nvme_cmd_cb cb_fn, void *cb_arg); 1120 int nvme_ctrlr_cmd_fw_commit(struct spdk_nvme_ctrlr *ctrlr, 1121 const struct spdk_nvme_fw_commit *fw_commit, 1122 spdk_nvme_cmd_cb cb_fn, void *cb_arg); 1123 int nvme_ctrlr_cmd_fw_image_download(struct spdk_nvme_ctrlr *ctrlr, 1124 uint32_t size, uint32_t offset, void *payload, 1125 spdk_nvme_cmd_cb cb_fn, void *cb_arg); 1126 int nvme_ctrlr_cmd_sanitize(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, 1127 struct spdk_nvme_sanitize *sanitize, uint32_t cdw11, 1128 spdk_nvme_cmd_cb cb_fn, void *cb_arg); 1129 void nvme_completion_poll_cb(void *arg, const struct spdk_nvme_cpl *cpl); 1130 int nvme_wait_for_completion(struct spdk_nvme_qpair *qpair, 1131 struct nvme_completion_poll_status *status); 1132 int nvme_wait_for_completion_robust_lock(struct spdk_nvme_qpair *qpair, 1133 struct nvme_completion_poll_status *status, 1134 pthread_mutex_t *robust_mutex); 1135 int nvme_wait_for_completion_timeout(struct spdk_nvme_qpair *qpair, 1136 struct nvme_completion_poll_status *status, 1137 uint64_t timeout_in_usecs); 1138 int nvme_wait_for_completion_robust_lock_timeout(struct spdk_nvme_qpair *qpair, 1139 struct nvme_completion_poll_status *status, 1140 pthread_mutex_t *robust_mutex, 1141 uint64_t timeout_in_usecs); 1142 int nvme_wait_for_completion_robust_lock_timeout_poll(struct spdk_nvme_qpair *qpair, 1143 struct nvme_completion_poll_status *status, 1144 pthread_mutex_t *robust_mutex); 1145 1146 struct spdk_nvme_ctrlr_process *nvme_ctrlr_get_process(struct spdk_nvme_ctrlr *ctrlr, 1147 pid_t pid); 1148 struct spdk_nvme_ctrlr_process *nvme_ctrlr_get_current_process(struct spdk_nvme_ctrlr *ctrlr); 1149 int nvme_ctrlr_add_process(struct spdk_nvme_ctrlr *ctrlr, void *devhandle); 1150 void nvme_ctrlr_free_processes(struct spdk_nvme_ctrlr *ctrlr); 1151 struct spdk_pci_device *nvme_ctrlr_proc_get_devhandle(struct spdk_nvme_ctrlr *ctrlr); 1152 1153 int nvme_ctrlr_probe(const struct spdk_nvme_transport_id *trid, 1154 struct spdk_nvme_probe_ctx *probe_ctx, void *devhandle); 1155 1156 int nvme_ctrlr_construct(struct spdk_nvme_ctrlr *ctrlr); 1157 void nvme_ctrlr_destruct_finish(struct spdk_nvme_ctrlr *ctrlr); 1158 void nvme_ctrlr_destruct(struct spdk_nvme_ctrlr *ctrlr); 1159 void nvme_ctrlr_destruct_async(struct spdk_nvme_ctrlr *ctrlr, 1160 struct nvme_ctrlr_detach_ctx *ctx); 1161 int nvme_ctrlr_destruct_poll_async(struct spdk_nvme_ctrlr *ctrlr, 1162 struct nvme_ctrlr_detach_ctx *ctx); 1163 void nvme_ctrlr_fail(struct spdk_nvme_ctrlr *ctrlr, bool hot_remove); 1164 int nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr); 1165 void nvme_ctrlr_disable(struct spdk_nvme_ctrlr *ctrlr); 1166 int nvme_ctrlr_disable_poll(struct spdk_nvme_ctrlr *ctrlr); 1167 void nvme_ctrlr_connected(struct spdk_nvme_probe_ctx *probe_ctx, 1168 struct spdk_nvme_ctrlr *ctrlr); 1169 1170 int nvme_ctrlr_submit_admin_request(struct spdk_nvme_ctrlr *ctrlr, 1171 struct nvme_request *req); 1172 int nvme_ctrlr_get_cap(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cap_register *cap); 1173 int nvme_ctrlr_get_vs(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_vs_register *vs); 1174 int nvme_ctrlr_get_cmbsz(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cmbsz_register *cmbsz); 1175 int nvme_ctrlr_get_pmrcap(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_pmrcap_register *pmrcap); 1176 int nvme_ctrlr_get_bpinfo(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_bpinfo_register *bpinfo); 1177 int nvme_ctrlr_set_bprsel(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_bprsel_register *bprsel); 1178 int nvme_ctrlr_set_bpmbl(struct spdk_nvme_ctrlr *ctrlr, uint64_t bpmbl_value); 1179 bool nvme_ctrlr_multi_iocs_enabled(struct spdk_nvme_ctrlr *ctrlr); 1180 void nvme_ctrlr_process_async_event(struct spdk_nvme_ctrlr *ctrlr, 1181 const struct spdk_nvme_cpl *cpl); 1182 void nvme_ctrlr_disconnect_qpair(struct spdk_nvme_qpair *qpair); 1183 void nvme_ctrlr_complete_queued_async_events(struct spdk_nvme_ctrlr *ctrlr); 1184 void nvme_ctrlr_abort_queued_aborts(struct spdk_nvme_ctrlr *ctrlr); 1185 int nvme_qpair_init(struct spdk_nvme_qpair *qpair, uint16_t id, 1186 struct spdk_nvme_ctrlr *ctrlr, 1187 enum spdk_nvme_qprio qprio, 1188 uint32_t num_requests, bool async); 1189 void nvme_qpair_deinit(struct spdk_nvme_qpair *qpair); 1190 void nvme_qpair_complete_error_reqs(struct spdk_nvme_qpair *qpair); 1191 int nvme_qpair_submit_request(struct spdk_nvme_qpair *qpair, 1192 struct nvme_request *req); 1193 void nvme_qpair_abort_all_queued_reqs(struct spdk_nvme_qpair *qpair, uint32_t dnr); 1194 uint32_t nvme_qpair_abort_queued_reqs_with_cbarg(struct spdk_nvme_qpair *qpair, void *cmd_cb_arg); 1195 void nvme_qpair_abort_queued_reqs(struct spdk_nvme_qpair *qpair, uint32_t dnr); 1196 void nvme_qpair_resubmit_requests(struct spdk_nvme_qpair *qpair, uint32_t num_requests); 1197 int nvme_ctrlr_identify_active_ns(struct spdk_nvme_ctrlr *ctrlr); 1198 void nvme_ns_set_identify_data(struct spdk_nvme_ns *ns); 1199 void nvme_ns_set_id_desc_list_data(struct spdk_nvme_ns *ns); 1200 void nvme_ns_free_zns_specific_data(struct spdk_nvme_ns *ns); 1201 void nvme_ns_free_iocs_specific_data(struct spdk_nvme_ns *ns); 1202 bool nvme_ns_has_supported_iocs_specific_data(struct spdk_nvme_ns *ns); 1203 int nvme_ns_construct(struct spdk_nvme_ns *ns, uint32_t id, 1204 struct spdk_nvme_ctrlr *ctrlr); 1205 void nvme_ns_destruct(struct spdk_nvme_ns *ns); 1206 int nvme_ns_cmd_zone_append_with_md(struct spdk_nvme_ns *ns, struct spdk_nvme_qpair *qpair, 1207 void *buffer, void *metadata, uint64_t zslba, 1208 uint32_t lba_count, spdk_nvme_cmd_cb cb_fn, void *cb_arg, 1209 uint32_t io_flags, uint16_t apptag_mask, uint16_t apptag); 1210 int nvme_ns_cmd_zone_appendv_with_md(struct spdk_nvme_ns *ns, struct spdk_nvme_qpair *qpair, 1211 uint64_t zslba, uint32_t lba_count, 1212 spdk_nvme_cmd_cb cb_fn, void *cb_arg, uint32_t io_flags, 1213 spdk_nvme_req_reset_sgl_cb reset_sgl_fn, 1214 spdk_nvme_req_next_sge_cb next_sge_fn, void *metadata, 1215 uint16_t apptag_mask, uint16_t apptag); 1216 1217 int nvme_fabric_ctrlr_set_reg_4(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint32_t value); 1218 int nvme_fabric_ctrlr_set_reg_8(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint64_t value); 1219 int nvme_fabric_ctrlr_get_reg_4(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint32_t *value); 1220 int nvme_fabric_ctrlr_get_reg_8(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint64_t *value); 1221 int nvme_fabric_ctrlr_set_reg_4_async(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, 1222 uint32_t value, spdk_nvme_reg_cb cb_fn, void *cb_arg); 1223 int nvme_fabric_ctrlr_set_reg_8_async(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, 1224 uint64_t value, spdk_nvme_reg_cb cb_fn, void *cb_arg); 1225 int nvme_fabric_ctrlr_get_reg_4_async(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, 1226 spdk_nvme_reg_cb cb_fn, void *cb_arg); 1227 int nvme_fabric_ctrlr_get_reg_8_async(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, 1228 spdk_nvme_reg_cb cb_fn, void *cb_arg); 1229 int nvme_fabric_ctrlr_scan(struct spdk_nvme_probe_ctx *probe_ctx, bool direct_connect); 1230 int nvme_fabric_ctrlr_discover(struct spdk_nvme_ctrlr *ctrlr, 1231 struct spdk_nvme_probe_ctx *probe_ctx); 1232 int nvme_fabric_qpair_connect(struct spdk_nvme_qpair *qpair, uint32_t num_entries); 1233 int nvme_fabric_qpair_connect_async(struct spdk_nvme_qpair *qpair, uint32_t num_entries); 1234 int nvme_fabric_qpair_connect_poll(struct spdk_nvme_qpair *qpair); 1235 1236 typedef int (*spdk_nvme_parse_ana_log_page_cb)( 1237 const struct spdk_nvme_ana_group_descriptor *desc, void *cb_arg); 1238 int nvme_ctrlr_parse_ana_log_page(struct spdk_nvme_ctrlr *ctrlr, 1239 spdk_nvme_parse_ana_log_page_cb cb_fn, void *cb_arg); 1240 1241 #define NVME_INIT_REQUEST(req, _cb_fn, _cb_arg, _payload, _payload_size, _md_size) \ 1242 do { \ 1243 req->cb_fn = _cb_fn; \ 1244 req->cb_arg = _cb_arg; \ 1245 req->payload = _payload; \ 1246 req->payload_size = _payload_size; \ 1247 req->md_size = _md_size; \ 1248 req->pid = g_spdk_nvme_pid; \ 1249 req->submit_tick = 0; \ 1250 } while (0); 1251 1252 static inline struct nvme_request * 1253 nvme_allocate_request(struct spdk_nvme_qpair *qpair, 1254 const struct nvme_payload *payload, uint32_t payload_size, uint32_t md_size, 1255 spdk_nvme_cmd_cb cb_fn, void *cb_arg) 1256 { 1257 struct nvme_request *req; 1258 1259 req = STAILQ_FIRST(&qpair->free_req); 1260 if (req == NULL) { 1261 return req; 1262 } 1263 1264 STAILQ_REMOVE_HEAD(&qpair->free_req, stailq); 1265 1266 /* 1267 * Only memset/zero fields that need it. All other fields 1268 * will be initialized appropriately either later in this 1269 * function, or before they are needed later in the 1270 * submission patch. For example, the children 1271 * TAILQ_ENTRY and following members are 1272 * only used as part of I/O splitting so we avoid 1273 * memsetting them until it is actually needed. 1274 * They will be initialized in nvme_request_add_child() 1275 * if the request is split. 1276 */ 1277 memset(req, 0, offsetof(struct nvme_request, payload_size)); 1278 1279 NVME_INIT_REQUEST(req, cb_fn, cb_arg, *payload, payload_size, md_size); 1280 1281 return req; 1282 } 1283 1284 static inline struct nvme_request * 1285 nvme_allocate_request_contig(struct spdk_nvme_qpair *qpair, 1286 void *buffer, uint32_t payload_size, 1287 spdk_nvme_cmd_cb cb_fn, void *cb_arg) 1288 { 1289 struct nvme_payload payload; 1290 1291 payload = NVME_PAYLOAD_CONTIG(buffer, NULL); 1292 1293 return nvme_allocate_request(qpair, &payload, payload_size, 0, cb_fn, cb_arg); 1294 } 1295 1296 static inline struct nvme_request * 1297 nvme_allocate_request_null(struct spdk_nvme_qpair *qpair, spdk_nvme_cmd_cb cb_fn, void *cb_arg) 1298 { 1299 return nvme_allocate_request_contig(qpair, NULL, 0, cb_fn, cb_arg); 1300 } 1301 1302 struct nvme_request *nvme_allocate_request_user_copy(struct spdk_nvme_qpair *qpair, 1303 void *buffer, uint32_t payload_size, 1304 spdk_nvme_cmd_cb cb_fn, void *cb_arg, bool host_to_controller); 1305 1306 static inline void 1307 nvme_complete_request(spdk_nvme_cmd_cb cb_fn, void *cb_arg, struct spdk_nvme_qpair *qpair, 1308 struct nvme_request *req, struct spdk_nvme_cpl *cpl) 1309 { 1310 struct spdk_nvme_cpl err_cpl; 1311 struct nvme_error_cmd *cmd; 1312 1313 /* error injection at completion path, 1314 * only inject for successful completed commands 1315 */ 1316 if (spdk_unlikely(!TAILQ_EMPTY(&qpair->err_cmd_head) && 1317 !spdk_nvme_cpl_is_error(cpl))) { 1318 TAILQ_FOREACH(cmd, &qpair->err_cmd_head, link) { 1319 1320 if (cmd->do_not_submit) { 1321 continue; 1322 } 1323 1324 if ((cmd->opc == req->cmd.opc) && cmd->err_count) { 1325 1326 err_cpl = *cpl; 1327 err_cpl.status.sct = cmd->status.sct; 1328 err_cpl.status.sc = cmd->status.sc; 1329 1330 cpl = &err_cpl; 1331 cmd->err_count--; 1332 break; 1333 } 1334 } 1335 } 1336 1337 if (cb_fn) { 1338 cb_fn(cb_arg, cpl); 1339 } 1340 } 1341 1342 static inline void 1343 nvme_free_request(struct nvme_request *req) 1344 { 1345 assert(req != NULL); 1346 assert(req->num_children == 0); 1347 assert(req->qpair != NULL); 1348 1349 /* The reserved_req does not go in the free_req STAILQ - it is 1350 * saved only for use with a FABRICS/CONNECT command. 1351 */ 1352 if (spdk_likely(req->qpair->reserved_req != req)) { 1353 STAILQ_INSERT_HEAD(&req->qpair->free_req, req, stailq); 1354 } 1355 } 1356 1357 static inline void 1358 nvme_qpair_set_state(struct spdk_nvme_qpair *qpair, enum nvme_qpair_state state) 1359 { 1360 qpair->state = state; 1361 if (state == NVME_QPAIR_ENABLED) { 1362 qpair->is_new_qpair = false; 1363 } 1364 } 1365 1366 static inline enum nvme_qpair_state 1367 nvme_qpair_get_state(struct spdk_nvme_qpair *qpair) { 1368 return qpair->state; 1369 } 1370 1371 static inline void 1372 nvme_qpair_free_request(struct spdk_nvme_qpair *qpair, struct nvme_request *req) 1373 { 1374 assert(req != NULL); 1375 assert(req->num_children == 0); 1376 1377 STAILQ_INSERT_HEAD(&qpair->free_req, req, stailq); 1378 } 1379 1380 static inline void 1381 nvme_request_remove_child(struct nvme_request *parent, struct nvme_request *child) 1382 { 1383 assert(parent != NULL); 1384 assert(child != NULL); 1385 assert(child->parent == parent); 1386 assert(parent->num_children != 0); 1387 1388 parent->num_children--; 1389 child->parent = NULL; 1390 TAILQ_REMOVE(&parent->children, child, child_tailq); 1391 } 1392 1393 static inline void 1394 nvme_cb_complete_child(void *child_arg, const struct spdk_nvme_cpl *cpl) 1395 { 1396 struct nvme_request *child = child_arg; 1397 struct nvme_request *parent = child->parent; 1398 1399 nvme_request_remove_child(parent, child); 1400 1401 if (spdk_nvme_cpl_is_error(cpl)) { 1402 memcpy(&parent->parent_status, cpl, sizeof(*cpl)); 1403 } 1404 1405 if (parent->num_children == 0) { 1406 nvme_complete_request(parent->cb_fn, parent->cb_arg, parent->qpair, 1407 parent, &parent->parent_status); 1408 nvme_free_request(parent); 1409 } 1410 } 1411 1412 static inline void 1413 nvme_request_add_child(struct nvme_request *parent, struct nvme_request *child) 1414 { 1415 assert(parent->num_children != UINT16_MAX); 1416 1417 if (parent->num_children == 0) { 1418 /* 1419 * Defer initialization of the children TAILQ since it falls 1420 * on a separate cacheline. This ensures we do not touch this 1421 * cacheline except on request splitting cases, which are 1422 * relatively rare. 1423 */ 1424 TAILQ_INIT(&parent->children); 1425 parent->parent = NULL; 1426 memset(&parent->parent_status, 0, sizeof(struct spdk_nvme_cpl)); 1427 } 1428 1429 parent->num_children++; 1430 TAILQ_INSERT_TAIL(&parent->children, child, child_tailq); 1431 child->parent = parent; 1432 child->cb_fn = nvme_cb_complete_child; 1433 child->cb_arg = child; 1434 } 1435 1436 static inline void 1437 nvme_request_free_children(struct nvme_request *req) 1438 { 1439 struct nvme_request *child, *tmp; 1440 1441 if (req->num_children == 0) { 1442 return; 1443 } 1444 1445 /* free all child nvme_request */ 1446 TAILQ_FOREACH_SAFE(child, &req->children, child_tailq, tmp) { 1447 nvme_request_remove_child(req, child); 1448 nvme_request_free_children(child); 1449 nvme_free_request(child); 1450 } 1451 } 1452 1453 int nvme_request_check_timeout(struct nvme_request *req, uint16_t cid, 1454 struct spdk_nvme_ctrlr_process *active_proc, uint64_t now_tick); 1455 uint64_t nvme_get_quirks(const struct spdk_pci_id *id); 1456 1457 int nvme_robust_mutex_init_shared(pthread_mutex_t *mtx); 1458 int nvme_robust_mutex_init_recursive_shared(pthread_mutex_t *mtx); 1459 1460 bool nvme_completion_is_retry(const struct spdk_nvme_cpl *cpl); 1461 1462 struct spdk_nvme_ctrlr *nvme_get_ctrlr_by_trid_unsafe( 1463 const struct spdk_nvme_transport_id *trid); 1464 1465 const struct spdk_nvme_transport *nvme_get_transport(const char *transport_name); 1466 const struct spdk_nvme_transport *nvme_get_first_transport(void); 1467 const struct spdk_nvme_transport *nvme_get_next_transport(const struct spdk_nvme_transport 1468 *transport); 1469 void nvme_ctrlr_update_namespaces(struct spdk_nvme_ctrlr *ctrlr); 1470 1471 /* Transport specific functions */ 1472 struct spdk_nvme_ctrlr *nvme_transport_ctrlr_construct(const struct spdk_nvme_transport_id *trid, 1473 const struct spdk_nvme_ctrlr_opts *opts, 1474 void *devhandle); 1475 int nvme_transport_ctrlr_destruct(struct spdk_nvme_ctrlr *ctrlr); 1476 int nvme_transport_ctrlr_scan(struct spdk_nvme_probe_ctx *probe_ctx, bool direct_connect); 1477 int nvme_transport_ctrlr_enable(struct spdk_nvme_ctrlr *ctrlr); 1478 int nvme_transport_ctrlr_ready(struct spdk_nvme_ctrlr *ctrlr); 1479 int nvme_transport_ctrlr_set_reg_4(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint32_t value); 1480 int nvme_transport_ctrlr_set_reg_8(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint64_t value); 1481 int nvme_transport_ctrlr_get_reg_4(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint32_t *value); 1482 int nvme_transport_ctrlr_get_reg_8(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, uint64_t *value); 1483 int nvme_transport_ctrlr_set_reg_4_async(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, 1484 uint32_t value, spdk_nvme_reg_cb cb_fn, void *cb_arg); 1485 int nvme_transport_ctrlr_set_reg_8_async(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, 1486 uint64_t value, spdk_nvme_reg_cb cb_fn, void *cb_arg); 1487 int nvme_transport_ctrlr_get_reg_4_async(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, 1488 spdk_nvme_reg_cb cb_fn, void *cb_arg); 1489 int nvme_transport_ctrlr_get_reg_8_async(struct spdk_nvme_ctrlr *ctrlr, uint32_t offset, 1490 spdk_nvme_reg_cb cb_fn, void *cb_arg); 1491 uint32_t nvme_transport_ctrlr_get_max_xfer_size(struct spdk_nvme_ctrlr *ctrlr); 1492 uint16_t nvme_transport_ctrlr_get_max_sges(struct spdk_nvme_ctrlr *ctrlr); 1493 struct spdk_nvme_qpair *nvme_transport_ctrlr_create_io_qpair(struct spdk_nvme_ctrlr *ctrlr, 1494 uint16_t qid, const struct spdk_nvme_io_qpair_opts *opts); 1495 int nvme_transport_ctrlr_reserve_cmb(struct spdk_nvme_ctrlr *ctrlr); 1496 void *nvme_transport_ctrlr_map_cmb(struct spdk_nvme_ctrlr *ctrlr, size_t *size); 1497 int nvme_transport_ctrlr_unmap_cmb(struct spdk_nvme_ctrlr *ctrlr); 1498 int nvme_transport_ctrlr_enable_pmr(struct spdk_nvme_ctrlr *ctrlr); 1499 int nvme_transport_ctrlr_disable_pmr(struct spdk_nvme_ctrlr *ctrlr); 1500 void *nvme_transport_ctrlr_map_pmr(struct spdk_nvme_ctrlr *ctrlr, size_t *size); 1501 int nvme_transport_ctrlr_unmap_pmr(struct spdk_nvme_ctrlr *ctrlr); 1502 void nvme_transport_ctrlr_delete_io_qpair(struct spdk_nvme_ctrlr *ctrlr, 1503 struct spdk_nvme_qpair *qpair); 1504 int nvme_transport_ctrlr_connect_qpair(struct spdk_nvme_ctrlr *ctrlr, 1505 struct spdk_nvme_qpair *qpair); 1506 void nvme_transport_ctrlr_disconnect_qpair(struct spdk_nvme_ctrlr *ctrlr, 1507 struct spdk_nvme_qpair *qpair); 1508 void nvme_transport_ctrlr_disconnect_qpair_done(struct spdk_nvme_qpair *qpair); 1509 int nvme_transport_ctrlr_get_memory_domains(const struct spdk_nvme_ctrlr *ctrlr, 1510 struct spdk_memory_domain **domains, int array_size); 1511 void nvme_transport_qpair_abort_reqs(struct spdk_nvme_qpair *qpair, uint32_t dnr); 1512 int nvme_transport_qpair_reset(struct spdk_nvme_qpair *qpair); 1513 int nvme_transport_qpair_submit_request(struct spdk_nvme_qpair *qpair, struct nvme_request *req); 1514 int32_t nvme_transport_qpair_process_completions(struct spdk_nvme_qpair *qpair, 1515 uint32_t max_completions); 1516 void nvme_transport_admin_qpair_abort_aers(struct spdk_nvme_qpair *qpair); 1517 int nvme_transport_qpair_iterate_requests(struct spdk_nvme_qpair *qpair, 1518 int (*iter_fn)(struct nvme_request *req, void *arg), 1519 void *arg); 1520 1521 struct spdk_nvme_transport_poll_group *nvme_transport_poll_group_create( 1522 const struct spdk_nvme_transport *transport); 1523 struct spdk_nvme_transport_poll_group *nvme_transport_qpair_get_optimal_poll_group( 1524 const struct spdk_nvme_transport *transport, 1525 struct spdk_nvme_qpair *qpair); 1526 int nvme_transport_poll_group_add(struct spdk_nvme_transport_poll_group *tgroup, 1527 struct spdk_nvme_qpair *qpair); 1528 int nvme_transport_poll_group_remove(struct spdk_nvme_transport_poll_group *tgroup, 1529 struct spdk_nvme_qpair *qpair); 1530 int nvme_transport_poll_group_disconnect_qpair(struct spdk_nvme_qpair *qpair); 1531 int nvme_transport_poll_group_connect_qpair(struct spdk_nvme_qpair *qpair); 1532 int64_t nvme_transport_poll_group_process_completions(struct spdk_nvme_transport_poll_group *tgroup, 1533 uint32_t completions_per_qpair, spdk_nvme_disconnected_qpair_cb disconnected_qpair_cb); 1534 int nvme_transport_poll_group_destroy(struct spdk_nvme_transport_poll_group *tgroup); 1535 int nvme_transport_poll_group_get_stats(struct spdk_nvme_transport_poll_group *tgroup, 1536 struct spdk_nvme_transport_poll_group_stat **stats); 1537 void nvme_transport_poll_group_free_stats(struct spdk_nvme_transport_poll_group *tgroup, 1538 struct spdk_nvme_transport_poll_group_stat *stats); 1539 enum spdk_nvme_transport_type nvme_transport_get_trtype(const struct spdk_nvme_transport 1540 *transport); 1541 /* 1542 * Below ref related functions must be called with the global 1543 * driver lock held for the multi-process condition. 1544 * Within these functions, the per ctrlr ctrlr_lock is also 1545 * acquired for the multi-thread condition. 1546 */ 1547 void nvme_ctrlr_proc_get_ref(struct spdk_nvme_ctrlr *ctrlr); 1548 void nvme_ctrlr_proc_put_ref(struct spdk_nvme_ctrlr *ctrlr); 1549 int nvme_ctrlr_get_ref_count(struct spdk_nvme_ctrlr *ctrlr); 1550 1551 static inline bool 1552 _is_page_aligned(uint64_t address, uint64_t page_size) 1553 { 1554 return (address & (page_size - 1)) == 0; 1555 } 1556 1557 #endif /* __NVME_INTERNAL_H__ */ 1558