1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (C) 2015 Intel Corporation. All rights reserved. 3 * Copyright (c) 2019-2021 Mellanox Technologies LTD. All rights reserved. 4 * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 5 */ 6 7 #include "spdk/stdinc.h" 8 9 #include "nvme_internal.h" 10 #include "nvme_io_msg.h" 11 12 #include "spdk/env.h" 13 #include "spdk/string.h" 14 #include "spdk/endian.h" 15 16 struct nvme_active_ns_ctx; 17 18 static int nvme_ctrlr_construct_and_submit_aer(struct spdk_nvme_ctrlr *ctrlr, 19 struct nvme_async_event_request *aer); 20 static void nvme_ctrlr_identify_active_ns_async(struct nvme_active_ns_ctx *ctx); 21 static int nvme_ctrlr_identify_ns_async(struct spdk_nvme_ns *ns); 22 static int nvme_ctrlr_identify_ns_iocs_specific_async(struct spdk_nvme_ns *ns); 23 static int nvme_ctrlr_identify_id_desc_async(struct spdk_nvme_ns *ns); 24 static void nvme_ctrlr_init_cap(struct spdk_nvme_ctrlr *ctrlr); 25 static void nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state, 26 uint64_t timeout_in_ms); 27 28 static int 29 nvme_ns_cmp(struct spdk_nvme_ns *ns1, struct spdk_nvme_ns *ns2) 30 { 31 if (ns1->id < ns2->id) { 32 return -1; 33 } else if (ns1->id > ns2->id) { 34 return 1; 35 } else { 36 return 0; 37 } 38 } 39 40 RB_GENERATE_STATIC(nvme_ns_tree, spdk_nvme_ns, node, nvme_ns_cmp); 41 42 #define CTRLR_STRING(ctrlr) \ 43 ((ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_TCP || ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_RDMA) ? \ 44 ctrlr->trid.subnqn : ctrlr->trid.traddr) 45 46 #define NVME_CTRLR_ERRLOG(ctrlr, format, ...) \ 47 SPDK_ERRLOG("[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__); 48 49 #define NVME_CTRLR_WARNLOG(ctrlr, format, ...) \ 50 SPDK_WARNLOG("[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__); 51 52 #define NVME_CTRLR_NOTICELOG(ctrlr, format, ...) \ 53 SPDK_NOTICELOG("[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__); 54 55 #define NVME_CTRLR_INFOLOG(ctrlr, format, ...) \ 56 SPDK_INFOLOG(nvme, "[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__); 57 58 #ifdef DEBUG 59 #define NVME_CTRLR_DEBUGLOG(ctrlr, format, ...) \ 60 SPDK_DEBUGLOG(nvme, "[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__); 61 #else 62 #define NVME_CTRLR_DEBUGLOG(ctrlr, ...) do { } while (0) 63 #endif 64 65 #define nvme_ctrlr_get_reg_async(ctrlr, reg, sz, cb_fn, cb_arg) \ 66 nvme_transport_ctrlr_get_reg_ ## sz ## _async(ctrlr, \ 67 offsetof(struct spdk_nvme_registers, reg), cb_fn, cb_arg) 68 69 #define nvme_ctrlr_set_reg_async(ctrlr, reg, sz, val, cb_fn, cb_arg) \ 70 nvme_transport_ctrlr_set_reg_ ## sz ## _async(ctrlr, \ 71 offsetof(struct spdk_nvme_registers, reg), val, cb_fn, cb_arg) 72 73 #define nvme_ctrlr_get_cc_async(ctrlr, cb_fn, cb_arg) \ 74 nvme_ctrlr_get_reg_async(ctrlr, cc, 4, cb_fn, cb_arg) 75 76 #define nvme_ctrlr_get_csts_async(ctrlr, cb_fn, cb_arg) \ 77 nvme_ctrlr_get_reg_async(ctrlr, csts, 4, cb_fn, cb_arg) 78 79 #define nvme_ctrlr_get_cap_async(ctrlr, cb_fn, cb_arg) \ 80 nvme_ctrlr_get_reg_async(ctrlr, cap, 8, cb_fn, cb_arg) 81 82 #define nvme_ctrlr_get_vs_async(ctrlr, cb_fn, cb_arg) \ 83 nvme_ctrlr_get_reg_async(ctrlr, vs, 4, cb_fn, cb_arg) 84 85 #define nvme_ctrlr_set_cc_async(ctrlr, value, cb_fn, cb_arg) \ 86 nvme_ctrlr_set_reg_async(ctrlr, cc, 4, value, cb_fn, cb_arg) 87 88 static int 89 nvme_ctrlr_get_cc(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cc_register *cc) 90 { 91 return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, cc.raw), 92 &cc->raw); 93 } 94 95 static int 96 nvme_ctrlr_get_csts(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_csts_register *csts) 97 { 98 return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, csts.raw), 99 &csts->raw); 100 } 101 102 int 103 nvme_ctrlr_get_cap(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cap_register *cap) 104 { 105 return nvme_transport_ctrlr_get_reg_8(ctrlr, offsetof(struct spdk_nvme_registers, cap.raw), 106 &cap->raw); 107 } 108 109 int 110 nvme_ctrlr_get_vs(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_vs_register *vs) 111 { 112 return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, vs.raw), 113 &vs->raw); 114 } 115 116 int 117 nvme_ctrlr_get_cmbsz(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cmbsz_register *cmbsz) 118 { 119 return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, cmbsz.raw), 120 &cmbsz->raw); 121 } 122 123 int 124 nvme_ctrlr_get_pmrcap(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_pmrcap_register *pmrcap) 125 { 126 return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, pmrcap.raw), 127 &pmrcap->raw); 128 } 129 130 int 131 nvme_ctrlr_get_bpinfo(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_bpinfo_register *bpinfo) 132 { 133 return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, bpinfo.raw), 134 &bpinfo->raw); 135 } 136 137 int 138 nvme_ctrlr_set_bprsel(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_bprsel_register *bprsel) 139 { 140 return nvme_transport_ctrlr_set_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, bprsel.raw), 141 bprsel->raw); 142 } 143 144 int 145 nvme_ctrlr_set_bpmbl(struct spdk_nvme_ctrlr *ctrlr, uint64_t bpmbl_value) 146 { 147 return nvme_transport_ctrlr_set_reg_8(ctrlr, offsetof(struct spdk_nvme_registers, bpmbl), 148 bpmbl_value); 149 } 150 151 static int 152 nvme_ctrlr_set_nssr(struct spdk_nvme_ctrlr *ctrlr, uint32_t nssr_value) 153 { 154 return nvme_transport_ctrlr_set_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, nssr), 155 nssr_value); 156 } 157 158 bool 159 nvme_ctrlr_multi_iocs_enabled(struct spdk_nvme_ctrlr *ctrlr) 160 { 161 return ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS && 162 ctrlr->opts.command_set == SPDK_NVME_CC_CSS_IOCS; 163 } 164 165 /* When the field in spdk_nvme_ctrlr_opts are changed and you change this function, please 166 * also update the nvme_ctrl_opts_init function in nvme_ctrlr.c 167 */ 168 void 169 spdk_nvme_ctrlr_get_default_ctrlr_opts(struct spdk_nvme_ctrlr_opts *opts, size_t opts_size) 170 { 171 char host_id_str[SPDK_UUID_STRING_LEN]; 172 173 assert(opts); 174 175 opts->opts_size = opts_size; 176 177 #define FIELD_OK(field) \ 178 offsetof(struct spdk_nvme_ctrlr_opts, field) + sizeof(opts->field) <= opts_size 179 180 #define SET_FIELD(field, value) \ 181 if (offsetof(struct spdk_nvme_ctrlr_opts, field) + sizeof(opts->field) <= opts_size) { \ 182 opts->field = value; \ 183 } \ 184 185 SET_FIELD(num_io_queues, DEFAULT_MAX_IO_QUEUES); 186 SET_FIELD(use_cmb_sqs, false); 187 SET_FIELD(no_shn_notification, false); 188 SET_FIELD(arb_mechanism, SPDK_NVME_CC_AMS_RR); 189 SET_FIELD(arbitration_burst, 0); 190 SET_FIELD(low_priority_weight, 0); 191 SET_FIELD(medium_priority_weight, 0); 192 SET_FIELD(high_priority_weight, 0); 193 SET_FIELD(keep_alive_timeout_ms, MIN_KEEP_ALIVE_TIMEOUT_IN_MS); 194 SET_FIELD(transport_retry_count, SPDK_NVME_DEFAULT_RETRY_COUNT); 195 SET_FIELD(io_queue_size, DEFAULT_IO_QUEUE_SIZE); 196 197 if (nvme_driver_init() == 0) { 198 if (FIELD_OK(hostnqn)) { 199 spdk_uuid_fmt_lower(host_id_str, sizeof(host_id_str), 200 &g_spdk_nvme_driver->default_extended_host_id); 201 snprintf(opts->hostnqn, sizeof(opts->hostnqn), 202 "nqn.2014-08.org.nvmexpress:uuid:%s", host_id_str); 203 } 204 205 if (FIELD_OK(extended_host_id)) { 206 memcpy(opts->extended_host_id, &g_spdk_nvme_driver->default_extended_host_id, 207 sizeof(opts->extended_host_id)); 208 } 209 210 } 211 212 SET_FIELD(io_queue_requests, DEFAULT_IO_QUEUE_REQUESTS); 213 214 if (FIELD_OK(src_addr)) { 215 memset(opts->src_addr, 0, sizeof(opts->src_addr)); 216 } 217 218 if (FIELD_OK(src_svcid)) { 219 memset(opts->src_svcid, 0, sizeof(opts->src_svcid)); 220 } 221 222 if (FIELD_OK(host_id)) { 223 memset(opts->host_id, 0, sizeof(opts->host_id)); 224 } 225 226 SET_FIELD(command_set, CHAR_BIT); 227 SET_FIELD(admin_timeout_ms, NVME_MAX_ADMIN_TIMEOUT_IN_SECS * 1000); 228 SET_FIELD(header_digest, false); 229 SET_FIELD(data_digest, false); 230 SET_FIELD(disable_error_logging, false); 231 SET_FIELD(transport_ack_timeout, SPDK_NVME_DEFAULT_TRANSPORT_ACK_TIMEOUT); 232 SET_FIELD(admin_queue_size, DEFAULT_ADMIN_QUEUE_SIZE); 233 SET_FIELD(fabrics_connect_timeout_us, NVME_FABRIC_CONNECT_COMMAND_TIMEOUT); 234 SET_FIELD(disable_read_ana_log_page, false); 235 SET_FIELD(disable_read_changed_ns_list_log_page, false); 236 SET_FIELD(tls_psk, NULL); 237 238 if (FIELD_OK(psk)) { 239 memset(opts->psk, 0, sizeof(opts->psk)); 240 } 241 242 #undef FIELD_OK 243 #undef SET_FIELD 244 } 245 246 const struct spdk_nvme_ctrlr_opts * 247 spdk_nvme_ctrlr_get_opts(struct spdk_nvme_ctrlr *ctrlr) 248 { 249 return &ctrlr->opts; 250 } 251 252 /** 253 * This function will be called when the process allocates the IO qpair. 254 * Note: the ctrlr_lock must be held when calling this function. 255 */ 256 static void 257 nvme_ctrlr_proc_add_io_qpair(struct spdk_nvme_qpair *qpair) 258 { 259 struct spdk_nvme_ctrlr_process *active_proc; 260 struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr; 261 262 active_proc = nvme_ctrlr_get_current_process(ctrlr); 263 if (active_proc) { 264 TAILQ_INSERT_TAIL(&active_proc->allocated_io_qpairs, qpair, per_process_tailq); 265 qpair->active_proc = active_proc; 266 } 267 } 268 269 /** 270 * This function will be called when the process frees the IO qpair. 271 * Note: the ctrlr_lock must be held when calling this function. 272 */ 273 static void 274 nvme_ctrlr_proc_remove_io_qpair(struct spdk_nvme_qpair *qpair) 275 { 276 struct spdk_nvme_ctrlr_process *active_proc; 277 struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr; 278 struct spdk_nvme_qpair *active_qpair, *tmp_qpair; 279 280 active_proc = nvme_ctrlr_get_current_process(ctrlr); 281 if (!active_proc) { 282 return; 283 } 284 285 TAILQ_FOREACH_SAFE(active_qpair, &active_proc->allocated_io_qpairs, 286 per_process_tailq, tmp_qpair) { 287 if (active_qpair == qpair) { 288 TAILQ_REMOVE(&active_proc->allocated_io_qpairs, 289 active_qpair, per_process_tailq); 290 291 break; 292 } 293 } 294 } 295 296 void 297 spdk_nvme_ctrlr_get_default_io_qpair_opts(struct spdk_nvme_ctrlr *ctrlr, 298 struct spdk_nvme_io_qpair_opts *opts, 299 size_t opts_size) 300 { 301 assert(ctrlr); 302 303 assert(opts); 304 305 memset(opts, 0, opts_size); 306 307 #define FIELD_OK(field) \ 308 offsetof(struct spdk_nvme_io_qpair_opts, field) + sizeof(opts->field) <= opts_size 309 310 if (FIELD_OK(qprio)) { 311 opts->qprio = SPDK_NVME_QPRIO_URGENT; 312 } 313 314 if (FIELD_OK(io_queue_size)) { 315 opts->io_queue_size = ctrlr->opts.io_queue_size; 316 } 317 318 if (FIELD_OK(io_queue_requests)) { 319 opts->io_queue_requests = ctrlr->opts.io_queue_requests; 320 } 321 322 if (FIELD_OK(delay_cmd_submit)) { 323 opts->delay_cmd_submit = false; 324 } 325 326 if (FIELD_OK(sq.vaddr)) { 327 opts->sq.vaddr = NULL; 328 } 329 330 if (FIELD_OK(sq.paddr)) { 331 opts->sq.paddr = 0; 332 } 333 334 if (FIELD_OK(sq.buffer_size)) { 335 opts->sq.buffer_size = 0; 336 } 337 338 if (FIELD_OK(cq.vaddr)) { 339 opts->cq.vaddr = NULL; 340 } 341 342 if (FIELD_OK(cq.paddr)) { 343 opts->cq.paddr = 0; 344 } 345 346 if (FIELD_OK(cq.buffer_size)) { 347 opts->cq.buffer_size = 0; 348 } 349 350 if (FIELD_OK(create_only)) { 351 opts->create_only = false; 352 } 353 354 if (FIELD_OK(async_mode)) { 355 opts->async_mode = false; 356 } 357 358 #undef FIELD_OK 359 } 360 361 static struct spdk_nvme_qpair * 362 nvme_ctrlr_create_io_qpair(struct spdk_nvme_ctrlr *ctrlr, 363 const struct spdk_nvme_io_qpair_opts *opts) 364 { 365 int32_t qid; 366 struct spdk_nvme_qpair *qpair; 367 union spdk_nvme_cc_register cc; 368 369 if (!ctrlr) { 370 return NULL; 371 } 372 373 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 374 cc.raw = ctrlr->process_init_cc.raw; 375 376 if (opts->qprio & ~SPDK_NVME_CREATE_IO_SQ_QPRIO_MASK) { 377 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 378 return NULL; 379 } 380 381 /* 382 * Only value SPDK_NVME_QPRIO_URGENT(0) is valid for the 383 * default round robin arbitration method. 384 */ 385 if ((cc.bits.ams == SPDK_NVME_CC_AMS_RR) && (opts->qprio != SPDK_NVME_QPRIO_URGENT)) { 386 NVME_CTRLR_ERRLOG(ctrlr, "invalid queue priority for default round robin arbitration method\n"); 387 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 388 return NULL; 389 } 390 391 qid = spdk_nvme_ctrlr_alloc_qid(ctrlr); 392 if (qid < 0) { 393 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 394 return NULL; 395 } 396 397 qpair = nvme_transport_ctrlr_create_io_qpair(ctrlr, qid, opts); 398 if (qpair == NULL) { 399 NVME_CTRLR_ERRLOG(ctrlr, "nvme_transport_ctrlr_create_io_qpair() failed\n"); 400 spdk_nvme_ctrlr_free_qid(ctrlr, qid); 401 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 402 return NULL; 403 } 404 405 TAILQ_INSERT_TAIL(&ctrlr->active_io_qpairs, qpair, tailq); 406 407 nvme_ctrlr_proc_add_io_qpair(qpair); 408 409 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 410 411 return qpair; 412 } 413 414 int 415 spdk_nvme_ctrlr_connect_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair) 416 { 417 int rc; 418 419 if (nvme_qpair_get_state(qpair) != NVME_QPAIR_DISCONNECTED) { 420 return -EISCONN; 421 } 422 423 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 424 rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair); 425 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 426 427 if (ctrlr->quirks & NVME_QUIRK_DELAY_AFTER_QUEUE_ALLOC) { 428 spdk_delay_us(100); 429 } 430 431 return rc; 432 } 433 434 void 435 spdk_nvme_ctrlr_disconnect_io_qpair(struct spdk_nvme_qpair *qpair) 436 { 437 struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr; 438 439 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 440 nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair); 441 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 442 } 443 444 struct spdk_nvme_qpair * 445 spdk_nvme_ctrlr_alloc_io_qpair(struct spdk_nvme_ctrlr *ctrlr, 446 const struct spdk_nvme_io_qpair_opts *user_opts, 447 size_t opts_size) 448 { 449 450 struct spdk_nvme_qpair *qpair = NULL; 451 struct spdk_nvme_io_qpair_opts opts; 452 int rc; 453 454 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 455 456 if (spdk_unlikely(ctrlr->state != NVME_CTRLR_STATE_READY)) { 457 /* When controller is resetting or initializing, free_io_qids is deleted or not created yet. 458 * We can't create IO qpair in that case */ 459 goto unlock; 460 } 461 462 /* 463 * Get the default options, then overwrite them with the user-provided options 464 * up to opts_size. 465 * 466 * This allows for extensions of the opts structure without breaking 467 * ABI compatibility. 468 */ 469 spdk_nvme_ctrlr_get_default_io_qpair_opts(ctrlr, &opts, sizeof(opts)); 470 if (user_opts) { 471 memcpy(&opts, user_opts, spdk_min(sizeof(opts), opts_size)); 472 473 /* If user passes buffers, make sure they're big enough for the requested queue size */ 474 if (opts.sq.vaddr) { 475 if (opts.sq.buffer_size < (opts.io_queue_size * sizeof(struct spdk_nvme_cmd))) { 476 NVME_CTRLR_ERRLOG(ctrlr, "sq buffer size %" PRIx64 " is too small for sq size %zx\n", 477 opts.sq.buffer_size, (opts.io_queue_size * sizeof(struct spdk_nvme_cmd))); 478 goto unlock; 479 } 480 } 481 if (opts.cq.vaddr) { 482 if (opts.cq.buffer_size < (opts.io_queue_size * sizeof(struct spdk_nvme_cpl))) { 483 NVME_CTRLR_ERRLOG(ctrlr, "cq buffer size %" PRIx64 " is too small for cq size %zx\n", 484 opts.cq.buffer_size, (opts.io_queue_size * sizeof(struct spdk_nvme_cpl))); 485 goto unlock; 486 } 487 } 488 } 489 490 qpair = nvme_ctrlr_create_io_qpair(ctrlr, &opts); 491 492 if (qpair == NULL || opts.create_only == true) { 493 goto unlock; 494 } 495 496 rc = spdk_nvme_ctrlr_connect_io_qpair(ctrlr, qpair); 497 if (rc != 0) { 498 NVME_CTRLR_ERRLOG(ctrlr, "nvme_transport_ctrlr_connect_io_qpair() failed\n"); 499 nvme_ctrlr_proc_remove_io_qpair(qpair); 500 TAILQ_REMOVE(&ctrlr->active_io_qpairs, qpair, tailq); 501 spdk_bit_array_set(ctrlr->free_io_qids, qpair->id); 502 nvme_transport_ctrlr_delete_io_qpair(ctrlr, qpair); 503 qpair = NULL; 504 goto unlock; 505 } 506 507 unlock: 508 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 509 510 return qpair; 511 } 512 513 int 514 spdk_nvme_ctrlr_reconnect_io_qpair(struct spdk_nvme_qpair *qpair) 515 { 516 struct spdk_nvme_ctrlr *ctrlr; 517 enum nvme_qpair_state qpair_state; 518 int rc; 519 520 assert(qpair != NULL); 521 assert(nvme_qpair_is_admin_queue(qpair) == false); 522 assert(qpair->ctrlr != NULL); 523 524 ctrlr = qpair->ctrlr; 525 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 526 qpair_state = nvme_qpair_get_state(qpair); 527 528 if (ctrlr->is_removed) { 529 rc = -ENODEV; 530 goto out; 531 } 532 533 if (ctrlr->is_resetting || qpair_state == NVME_QPAIR_DISCONNECTING) { 534 rc = -EAGAIN; 535 goto out; 536 } 537 538 if (ctrlr->is_failed || qpair_state == NVME_QPAIR_DESTROYING) { 539 rc = -ENXIO; 540 goto out; 541 } 542 543 if (qpair_state != NVME_QPAIR_DISCONNECTED) { 544 rc = 0; 545 goto out; 546 } 547 548 rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair); 549 if (rc) { 550 rc = -EAGAIN; 551 goto out; 552 } 553 554 out: 555 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 556 return rc; 557 } 558 559 spdk_nvme_qp_failure_reason 560 spdk_nvme_ctrlr_get_admin_qp_failure_reason(struct spdk_nvme_ctrlr *ctrlr) 561 { 562 return ctrlr->adminq->transport_failure_reason; 563 } 564 565 /* 566 * This internal function will attempt to take the controller 567 * lock before calling disconnect on a controller qpair. 568 * Functions already holding the controller lock should 569 * call nvme_transport_ctrlr_disconnect_qpair directly. 570 */ 571 void 572 nvme_ctrlr_disconnect_qpair(struct spdk_nvme_qpair *qpair) 573 { 574 struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr; 575 576 assert(ctrlr != NULL); 577 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 578 nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair); 579 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 580 } 581 582 int 583 spdk_nvme_ctrlr_free_io_qpair(struct spdk_nvme_qpair *qpair) 584 { 585 struct spdk_nvme_ctrlr *ctrlr; 586 587 if (qpair == NULL) { 588 return 0; 589 } 590 591 ctrlr = qpair->ctrlr; 592 593 if (qpair->in_completion_context) { 594 /* 595 * There are many cases where it is convenient to delete an io qpair in the context 596 * of that qpair's completion routine. To handle this properly, set a flag here 597 * so that the completion routine will perform an actual delete after the context 598 * unwinds. 599 */ 600 qpair->delete_after_completion_context = 1; 601 return 0; 602 } 603 604 qpair->destroy_in_progress = 1; 605 606 nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair); 607 608 if (qpair->poll_group && (qpair->active_proc == nvme_ctrlr_get_current_process(ctrlr))) { 609 spdk_nvme_poll_group_remove(qpair->poll_group->group, qpair); 610 } 611 612 /* Do not retry. */ 613 nvme_qpair_set_state(qpair, NVME_QPAIR_DESTROYING); 614 615 /* In the multi-process case, a process may call this function on a foreign 616 * I/O qpair (i.e. one that this process did not create) when that qpairs process 617 * exits unexpectedly. In that case, we must not try to abort any reqs associated 618 * with that qpair, since the callbacks will also be foreign to this process. 619 */ 620 if (qpair->active_proc == nvme_ctrlr_get_current_process(ctrlr)) { 621 nvme_qpair_abort_all_queued_reqs(qpair); 622 } 623 624 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 625 626 nvme_ctrlr_proc_remove_io_qpair(qpair); 627 628 TAILQ_REMOVE(&ctrlr->active_io_qpairs, qpair, tailq); 629 spdk_nvme_ctrlr_free_qid(ctrlr, qpair->id); 630 631 nvme_transport_ctrlr_delete_io_qpair(ctrlr, qpair); 632 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 633 return 0; 634 } 635 636 static void 637 nvme_ctrlr_construct_intel_support_log_page_list(struct spdk_nvme_ctrlr *ctrlr, 638 struct spdk_nvme_intel_log_page_directory *log_page_directory) 639 { 640 if (log_page_directory == NULL) { 641 return; 642 } 643 644 assert(ctrlr->cdata.vid == SPDK_PCI_VID_INTEL); 645 646 ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY] = true; 647 648 if (log_page_directory->read_latency_log_len || 649 (ctrlr->quirks & NVME_INTEL_QUIRK_READ_LATENCY)) { 650 ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY] = true; 651 } 652 if (log_page_directory->write_latency_log_len || 653 (ctrlr->quirks & NVME_INTEL_QUIRK_WRITE_LATENCY)) { 654 ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_WRITE_CMD_LATENCY] = true; 655 } 656 if (log_page_directory->temperature_statistics_log_len) { 657 ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_TEMPERATURE] = true; 658 } 659 if (log_page_directory->smart_log_len) { 660 ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_SMART] = true; 661 } 662 if (log_page_directory->marketing_description_log_len) { 663 ctrlr->log_page_supported[SPDK_NVME_INTEL_MARKETING_DESCRIPTION] = true; 664 } 665 } 666 667 struct intel_log_pages_ctx { 668 struct spdk_nvme_intel_log_page_directory log_page_directory; 669 struct spdk_nvme_ctrlr *ctrlr; 670 }; 671 672 static void 673 nvme_ctrlr_set_intel_support_log_pages_done(void *arg, const struct spdk_nvme_cpl *cpl) 674 { 675 struct intel_log_pages_ctx *ctx = arg; 676 struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr; 677 678 if (!spdk_nvme_cpl_is_error(cpl)) { 679 nvme_ctrlr_construct_intel_support_log_page_list(ctrlr, &ctx->log_page_directory); 680 } 681 682 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES, 683 ctrlr->opts.admin_timeout_ms); 684 free(ctx); 685 } 686 687 static int 688 nvme_ctrlr_set_intel_support_log_pages(struct spdk_nvme_ctrlr *ctrlr) 689 { 690 int rc = 0; 691 struct intel_log_pages_ctx *ctx; 692 693 ctx = calloc(1, sizeof(*ctx)); 694 if (!ctx) { 695 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES, 696 ctrlr->opts.admin_timeout_ms); 697 return 0; 698 } 699 700 ctx->ctrlr = ctrlr; 701 702 rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr, SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY, 703 SPDK_NVME_GLOBAL_NS_TAG, &ctx->log_page_directory, 704 sizeof(struct spdk_nvme_intel_log_page_directory), 705 0, nvme_ctrlr_set_intel_support_log_pages_done, ctx); 706 if (rc != 0) { 707 free(ctx); 708 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES, 709 ctrlr->opts.admin_timeout_ms); 710 return 0; 711 } 712 713 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES, 714 ctrlr->opts.admin_timeout_ms); 715 716 return 0; 717 } 718 719 static int 720 nvme_ctrlr_alloc_ana_log_page(struct spdk_nvme_ctrlr *ctrlr) 721 { 722 uint32_t ana_log_page_size; 723 724 ana_log_page_size = sizeof(struct spdk_nvme_ana_page) + ctrlr->cdata.nanagrpid * 725 sizeof(struct spdk_nvme_ana_group_descriptor) + ctrlr->active_ns_count * 726 sizeof(uint32_t); 727 728 /* Number of active namespaces may have changed. 729 * Check if ANA log page fits into existing buffer. 730 */ 731 if (ana_log_page_size > ctrlr->ana_log_page_size) { 732 void *new_buffer; 733 734 if (ctrlr->ana_log_page) { 735 new_buffer = realloc(ctrlr->ana_log_page, ana_log_page_size); 736 } else { 737 new_buffer = calloc(1, ana_log_page_size); 738 } 739 740 if (!new_buffer) { 741 NVME_CTRLR_ERRLOG(ctrlr, "could not allocate ANA log page buffer, size %u\n", 742 ana_log_page_size); 743 return -ENXIO; 744 } 745 746 ctrlr->ana_log_page = new_buffer; 747 if (ctrlr->copied_ana_desc) { 748 new_buffer = realloc(ctrlr->copied_ana_desc, ana_log_page_size); 749 } else { 750 new_buffer = calloc(1, ana_log_page_size); 751 } 752 753 if (!new_buffer) { 754 NVME_CTRLR_ERRLOG(ctrlr, "could not allocate a buffer to parse ANA descriptor, size %u\n", 755 ana_log_page_size); 756 return -ENOMEM; 757 } 758 759 ctrlr->copied_ana_desc = new_buffer; 760 ctrlr->ana_log_page_size = ana_log_page_size; 761 } 762 763 return 0; 764 } 765 766 static int 767 nvme_ctrlr_update_ana_log_page(struct spdk_nvme_ctrlr *ctrlr) 768 { 769 struct nvme_completion_poll_status *status; 770 int rc; 771 772 rc = nvme_ctrlr_alloc_ana_log_page(ctrlr); 773 if (rc != 0) { 774 return rc; 775 } 776 777 status = calloc(1, sizeof(*status)); 778 if (status == NULL) { 779 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n"); 780 return -ENOMEM; 781 } 782 783 rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr, SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS, 784 SPDK_NVME_GLOBAL_NS_TAG, ctrlr->ana_log_page, 785 ctrlr->ana_log_page_size, 0, 786 nvme_completion_poll_cb, status); 787 if (rc != 0) { 788 free(status); 789 return rc; 790 } 791 792 if (nvme_wait_for_completion_robust_lock_timeout(ctrlr->adminq, status, &ctrlr->ctrlr_lock, 793 ctrlr->opts.admin_timeout_ms * 1000)) { 794 if (!status->timed_out) { 795 free(status); 796 } 797 return -EIO; 798 } 799 800 free(status); 801 return 0; 802 } 803 804 static int 805 nvme_ctrlr_update_ns_ana_states(const struct spdk_nvme_ana_group_descriptor *desc, 806 void *cb_arg) 807 { 808 struct spdk_nvme_ctrlr *ctrlr = cb_arg; 809 struct spdk_nvme_ns *ns; 810 uint32_t i, nsid; 811 812 for (i = 0; i < desc->num_of_nsid; i++) { 813 nsid = desc->nsid[i]; 814 if (nsid == 0 || nsid > ctrlr->cdata.nn) { 815 continue; 816 } 817 818 ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid); 819 assert(ns != NULL); 820 821 ns->ana_group_id = desc->ana_group_id; 822 ns->ana_state = desc->ana_state; 823 } 824 825 return 0; 826 } 827 828 int 829 nvme_ctrlr_parse_ana_log_page(struct spdk_nvme_ctrlr *ctrlr, 830 spdk_nvme_parse_ana_log_page_cb cb_fn, void *cb_arg) 831 { 832 struct spdk_nvme_ana_group_descriptor *copied_desc; 833 uint8_t *orig_desc; 834 uint32_t i, desc_size, copy_len; 835 int rc = 0; 836 837 if (ctrlr->ana_log_page == NULL) { 838 return -EINVAL; 839 } 840 841 copied_desc = ctrlr->copied_ana_desc; 842 843 orig_desc = (uint8_t *)ctrlr->ana_log_page + sizeof(struct spdk_nvme_ana_page); 844 copy_len = ctrlr->ana_log_page_size - sizeof(struct spdk_nvme_ana_page); 845 846 for (i = 0; i < ctrlr->ana_log_page->num_ana_group_desc; i++) { 847 memcpy(copied_desc, orig_desc, copy_len); 848 849 rc = cb_fn(copied_desc, cb_arg); 850 if (rc != 0) { 851 break; 852 } 853 854 desc_size = sizeof(struct spdk_nvme_ana_group_descriptor) + 855 copied_desc->num_of_nsid * sizeof(uint32_t); 856 orig_desc += desc_size; 857 copy_len -= desc_size; 858 } 859 860 return rc; 861 } 862 863 static int 864 nvme_ctrlr_set_supported_log_pages(struct spdk_nvme_ctrlr *ctrlr) 865 { 866 int rc = 0; 867 868 memset(ctrlr->log_page_supported, 0, sizeof(ctrlr->log_page_supported)); 869 /* Mandatory pages */ 870 ctrlr->log_page_supported[SPDK_NVME_LOG_ERROR] = true; 871 ctrlr->log_page_supported[SPDK_NVME_LOG_HEALTH_INFORMATION] = true; 872 ctrlr->log_page_supported[SPDK_NVME_LOG_FIRMWARE_SLOT] = true; 873 if (ctrlr->cdata.lpa.celp) { 874 ctrlr->log_page_supported[SPDK_NVME_LOG_COMMAND_EFFECTS_LOG] = true; 875 } 876 877 if (ctrlr->cdata.cmic.ana_reporting) { 878 ctrlr->log_page_supported[SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS] = true; 879 if (!ctrlr->opts.disable_read_ana_log_page) { 880 rc = nvme_ctrlr_update_ana_log_page(ctrlr); 881 if (rc == 0) { 882 nvme_ctrlr_parse_ana_log_page(ctrlr, nvme_ctrlr_update_ns_ana_states, 883 ctrlr); 884 } 885 } 886 } 887 888 if (ctrlr->cdata.ctratt.fdps) { 889 ctrlr->log_page_supported[SPDK_NVME_LOG_FDP_CONFIGURATIONS] = true; 890 ctrlr->log_page_supported[SPDK_NVME_LOG_RECLAIM_UNIT_HANDLE_USAGE] = true; 891 ctrlr->log_page_supported[SPDK_NVME_LOG_FDP_STATISTICS] = true; 892 ctrlr->log_page_supported[SPDK_NVME_LOG_FDP_EVENTS] = true; 893 } 894 895 if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL && 896 ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE && 897 !(ctrlr->quirks & NVME_INTEL_QUIRK_NO_LOG_PAGES)) { 898 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES, 899 ctrlr->opts.admin_timeout_ms); 900 901 } else { 902 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES, 903 ctrlr->opts.admin_timeout_ms); 904 905 } 906 907 return rc; 908 } 909 910 static void 911 nvme_ctrlr_set_intel_supported_features(struct spdk_nvme_ctrlr *ctrlr) 912 { 913 ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_MAX_LBA] = true; 914 ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_NATIVE_MAX_LBA] = true; 915 ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_POWER_GOVERNOR_SETTING] = true; 916 ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_SMBUS_ADDRESS] = true; 917 ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_LED_PATTERN] = true; 918 ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_RESET_TIMED_WORKLOAD_COUNTERS] = true; 919 ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_LATENCY_TRACKING] = true; 920 } 921 922 static void 923 nvme_ctrlr_set_arbitration_feature(struct spdk_nvme_ctrlr *ctrlr) 924 { 925 uint32_t cdw11; 926 struct nvme_completion_poll_status *status; 927 928 if (ctrlr->opts.arbitration_burst == 0) { 929 return; 930 } 931 932 if (ctrlr->opts.arbitration_burst > 7) { 933 NVME_CTRLR_WARNLOG(ctrlr, "Valid arbitration burst values is from 0-7\n"); 934 return; 935 } 936 937 status = calloc(1, sizeof(*status)); 938 if (!status) { 939 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n"); 940 return; 941 } 942 943 cdw11 = ctrlr->opts.arbitration_burst; 944 945 if (spdk_nvme_ctrlr_get_flags(ctrlr) & SPDK_NVME_CTRLR_WRR_SUPPORTED) { 946 cdw11 |= (uint32_t)ctrlr->opts.low_priority_weight << 8; 947 cdw11 |= (uint32_t)ctrlr->opts.medium_priority_weight << 16; 948 cdw11 |= (uint32_t)ctrlr->opts.high_priority_weight << 24; 949 } 950 951 if (spdk_nvme_ctrlr_cmd_set_feature(ctrlr, SPDK_NVME_FEAT_ARBITRATION, 952 cdw11, 0, NULL, 0, 953 nvme_completion_poll_cb, status) < 0) { 954 NVME_CTRLR_ERRLOG(ctrlr, "Set arbitration feature failed\n"); 955 free(status); 956 return; 957 } 958 959 if (nvme_wait_for_completion_timeout(ctrlr->adminq, status, 960 ctrlr->opts.admin_timeout_ms * 1000)) { 961 NVME_CTRLR_ERRLOG(ctrlr, "Timeout to set arbitration feature\n"); 962 } 963 964 if (!status->timed_out) { 965 free(status); 966 } 967 } 968 969 static void 970 nvme_ctrlr_set_supported_features(struct spdk_nvme_ctrlr *ctrlr) 971 { 972 memset(ctrlr->feature_supported, 0, sizeof(ctrlr->feature_supported)); 973 /* Mandatory features */ 974 ctrlr->feature_supported[SPDK_NVME_FEAT_ARBITRATION] = true; 975 ctrlr->feature_supported[SPDK_NVME_FEAT_POWER_MANAGEMENT] = true; 976 ctrlr->feature_supported[SPDK_NVME_FEAT_TEMPERATURE_THRESHOLD] = true; 977 ctrlr->feature_supported[SPDK_NVME_FEAT_ERROR_RECOVERY] = true; 978 ctrlr->feature_supported[SPDK_NVME_FEAT_NUMBER_OF_QUEUES] = true; 979 ctrlr->feature_supported[SPDK_NVME_FEAT_INTERRUPT_COALESCING] = true; 980 ctrlr->feature_supported[SPDK_NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION] = true; 981 ctrlr->feature_supported[SPDK_NVME_FEAT_WRITE_ATOMICITY] = true; 982 ctrlr->feature_supported[SPDK_NVME_FEAT_ASYNC_EVENT_CONFIGURATION] = true; 983 /* Optional features */ 984 if (ctrlr->cdata.vwc.present) { 985 ctrlr->feature_supported[SPDK_NVME_FEAT_VOLATILE_WRITE_CACHE] = true; 986 } 987 if (ctrlr->cdata.apsta.supported) { 988 ctrlr->feature_supported[SPDK_NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION] = true; 989 } 990 if (ctrlr->cdata.hmpre) { 991 ctrlr->feature_supported[SPDK_NVME_FEAT_HOST_MEM_BUFFER] = true; 992 } 993 if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL) { 994 nvme_ctrlr_set_intel_supported_features(ctrlr); 995 } 996 997 nvme_ctrlr_set_arbitration_feature(ctrlr); 998 } 999 1000 bool 1001 spdk_nvme_ctrlr_is_failed(struct spdk_nvme_ctrlr *ctrlr) 1002 { 1003 return ctrlr->is_failed; 1004 } 1005 1006 void 1007 nvme_ctrlr_fail(struct spdk_nvme_ctrlr *ctrlr, bool hot_remove) 1008 { 1009 /* 1010 * Set the flag here and leave the work failure of qpairs to 1011 * spdk_nvme_qpair_process_completions(). 1012 */ 1013 if (hot_remove) { 1014 ctrlr->is_removed = true; 1015 } 1016 1017 if (ctrlr->is_failed) { 1018 NVME_CTRLR_NOTICELOG(ctrlr, "already in failed state\n"); 1019 return; 1020 } 1021 1022 if (ctrlr->is_disconnecting) { 1023 NVME_CTRLR_DEBUGLOG(ctrlr, "already disconnecting\n"); 1024 return; 1025 } 1026 1027 ctrlr->is_failed = true; 1028 nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq); 1029 NVME_CTRLR_ERRLOG(ctrlr, "in failed state.\n"); 1030 } 1031 1032 /** 1033 * This public API function will try to take the controller lock. 1034 * Any private functions being called from a thread already holding 1035 * the ctrlr lock should call nvme_ctrlr_fail directly. 1036 */ 1037 void 1038 spdk_nvme_ctrlr_fail(struct spdk_nvme_ctrlr *ctrlr) 1039 { 1040 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 1041 nvme_ctrlr_fail(ctrlr, false); 1042 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 1043 } 1044 1045 static void 1046 nvme_ctrlr_shutdown_set_cc_done(void *_ctx, uint64_t value, const struct spdk_nvme_cpl *cpl) 1047 { 1048 struct nvme_ctrlr_detach_ctx *ctx = _ctx; 1049 struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr; 1050 1051 if (spdk_nvme_cpl_is_error(cpl)) { 1052 NVME_CTRLR_ERRLOG(ctrlr, "Failed to write CC.SHN\n"); 1053 ctx->shutdown_complete = true; 1054 return; 1055 } 1056 1057 if (ctrlr->opts.no_shn_notification) { 1058 ctx->shutdown_complete = true; 1059 return; 1060 } 1061 1062 /* 1063 * The NVMe specification defines RTD3E to be the time between 1064 * setting SHN = 1 until the controller will set SHST = 10b. 1065 * If the device doesn't report RTD3 entry latency, or if it 1066 * reports RTD3 entry latency less than 10 seconds, pick 1067 * 10 seconds as a reasonable amount of time to 1068 * wait before proceeding. 1069 */ 1070 NVME_CTRLR_DEBUGLOG(ctrlr, "RTD3E = %" PRIu32 " us\n", ctrlr->cdata.rtd3e); 1071 ctx->shutdown_timeout_ms = SPDK_CEIL_DIV(ctrlr->cdata.rtd3e, 1000); 1072 ctx->shutdown_timeout_ms = spdk_max(ctx->shutdown_timeout_ms, 10000); 1073 NVME_CTRLR_DEBUGLOG(ctrlr, "shutdown timeout = %" PRIu32 " ms\n", ctx->shutdown_timeout_ms); 1074 1075 ctx->shutdown_start_tsc = spdk_get_ticks(); 1076 ctx->state = NVME_CTRLR_DETACH_CHECK_CSTS; 1077 } 1078 1079 static void 1080 nvme_ctrlr_shutdown_get_cc_done(void *_ctx, uint64_t value, const struct spdk_nvme_cpl *cpl) 1081 { 1082 struct nvme_ctrlr_detach_ctx *ctx = _ctx; 1083 struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr; 1084 union spdk_nvme_cc_register cc; 1085 int rc; 1086 1087 if (spdk_nvme_cpl_is_error(cpl)) { 1088 NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n"); 1089 ctx->shutdown_complete = true; 1090 return; 1091 } 1092 1093 assert(value <= UINT32_MAX); 1094 cc.raw = (uint32_t)value; 1095 1096 if (ctrlr->opts.no_shn_notification) { 1097 NVME_CTRLR_INFOLOG(ctrlr, "Disable SSD without shutdown notification\n"); 1098 if (cc.bits.en == 0) { 1099 ctx->shutdown_complete = true; 1100 return; 1101 } 1102 1103 cc.bits.en = 0; 1104 } else { 1105 cc.bits.shn = SPDK_NVME_SHN_NORMAL; 1106 } 1107 1108 rc = nvme_ctrlr_set_cc_async(ctrlr, cc.raw, nvme_ctrlr_shutdown_set_cc_done, ctx); 1109 if (rc != 0) { 1110 NVME_CTRLR_ERRLOG(ctrlr, "Failed to write CC.SHN\n"); 1111 ctx->shutdown_complete = true; 1112 } 1113 } 1114 1115 static void 1116 nvme_ctrlr_shutdown_async(struct spdk_nvme_ctrlr *ctrlr, 1117 struct nvme_ctrlr_detach_ctx *ctx) 1118 { 1119 int rc; 1120 1121 if (ctrlr->is_removed) { 1122 ctx->shutdown_complete = true; 1123 return; 1124 } 1125 1126 if (ctrlr->adminq == NULL || 1127 ctrlr->adminq->transport_failure_reason != SPDK_NVME_QPAIR_FAILURE_NONE) { 1128 NVME_CTRLR_INFOLOG(ctrlr, "Adminq is not connected.\n"); 1129 ctx->shutdown_complete = true; 1130 return; 1131 } 1132 1133 ctx->state = NVME_CTRLR_DETACH_SET_CC; 1134 rc = nvme_ctrlr_get_cc_async(ctrlr, nvme_ctrlr_shutdown_get_cc_done, ctx); 1135 if (rc != 0) { 1136 NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n"); 1137 ctx->shutdown_complete = true; 1138 } 1139 } 1140 1141 static void 1142 nvme_ctrlr_shutdown_get_csts_done(void *_ctx, uint64_t value, const struct spdk_nvme_cpl *cpl) 1143 { 1144 struct nvme_ctrlr_detach_ctx *ctx = _ctx; 1145 1146 if (spdk_nvme_cpl_is_error(cpl)) { 1147 NVME_CTRLR_ERRLOG(ctx->ctrlr, "Failed to read the CSTS register\n"); 1148 ctx->shutdown_complete = true; 1149 return; 1150 } 1151 1152 assert(value <= UINT32_MAX); 1153 ctx->csts.raw = (uint32_t)value; 1154 ctx->state = NVME_CTRLR_DETACH_GET_CSTS_DONE; 1155 } 1156 1157 static int 1158 nvme_ctrlr_shutdown_poll_async(struct spdk_nvme_ctrlr *ctrlr, 1159 struct nvme_ctrlr_detach_ctx *ctx) 1160 { 1161 union spdk_nvme_csts_register csts; 1162 uint32_t ms_waited; 1163 1164 switch (ctx->state) { 1165 case NVME_CTRLR_DETACH_SET_CC: 1166 case NVME_CTRLR_DETACH_GET_CSTS: 1167 /* We're still waiting for the register operation to complete */ 1168 spdk_nvme_qpair_process_completions(ctrlr->adminq, 0); 1169 return -EAGAIN; 1170 1171 case NVME_CTRLR_DETACH_CHECK_CSTS: 1172 ctx->state = NVME_CTRLR_DETACH_GET_CSTS; 1173 if (nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_shutdown_get_csts_done, ctx)) { 1174 NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n"); 1175 return -EIO; 1176 } 1177 return -EAGAIN; 1178 1179 case NVME_CTRLR_DETACH_GET_CSTS_DONE: 1180 ctx->state = NVME_CTRLR_DETACH_CHECK_CSTS; 1181 break; 1182 1183 default: 1184 assert(0 && "Should never happen"); 1185 return -EINVAL; 1186 } 1187 1188 ms_waited = (spdk_get_ticks() - ctx->shutdown_start_tsc) * 1000 / spdk_get_ticks_hz(); 1189 csts.raw = ctx->csts.raw; 1190 1191 if (csts.bits.shst == SPDK_NVME_SHST_COMPLETE) { 1192 NVME_CTRLR_DEBUGLOG(ctrlr, "shutdown complete in %u milliseconds\n", ms_waited); 1193 return 0; 1194 } 1195 1196 if (ms_waited < ctx->shutdown_timeout_ms) { 1197 return -EAGAIN; 1198 } 1199 1200 NVME_CTRLR_ERRLOG(ctrlr, "did not shutdown within %u milliseconds\n", 1201 ctx->shutdown_timeout_ms); 1202 if (ctrlr->quirks & NVME_QUIRK_SHST_COMPLETE) { 1203 NVME_CTRLR_ERRLOG(ctrlr, "likely due to shutdown handling in the VMWare emulated NVMe SSD\n"); 1204 } 1205 1206 return 0; 1207 } 1208 1209 static inline uint64_t 1210 nvme_ctrlr_get_ready_timeout(struct spdk_nvme_ctrlr *ctrlr) 1211 { 1212 return ctrlr->cap.bits.to * 500; 1213 } 1214 1215 static void 1216 nvme_ctrlr_set_cc_en_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl) 1217 { 1218 struct spdk_nvme_ctrlr *ctrlr = ctx; 1219 1220 if (spdk_nvme_cpl_is_error(cpl)) { 1221 NVME_CTRLR_ERRLOG(ctrlr, "Failed to set the CC register\n"); 1222 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 1223 return; 1224 } 1225 1226 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1, 1227 nvme_ctrlr_get_ready_timeout(ctrlr)); 1228 } 1229 1230 static int 1231 nvme_ctrlr_enable(struct spdk_nvme_ctrlr *ctrlr) 1232 { 1233 union spdk_nvme_cc_register cc; 1234 int rc; 1235 1236 rc = nvme_transport_ctrlr_enable(ctrlr); 1237 if (rc != 0) { 1238 NVME_CTRLR_ERRLOG(ctrlr, "transport ctrlr_enable failed\n"); 1239 return rc; 1240 } 1241 1242 cc.raw = ctrlr->process_init_cc.raw; 1243 if (cc.bits.en != 0) { 1244 NVME_CTRLR_ERRLOG(ctrlr, "called with CC.EN = 1\n"); 1245 return -EINVAL; 1246 } 1247 1248 cc.bits.en = 1; 1249 cc.bits.css = 0; 1250 cc.bits.shn = 0; 1251 cc.bits.iosqes = 6; /* SQ entry size == 64 == 2^6 */ 1252 cc.bits.iocqes = 4; /* CQ entry size == 16 == 2^4 */ 1253 1254 /* Page size is 2 ^ (12 + mps). */ 1255 cc.bits.mps = spdk_u32log2(ctrlr->page_size) - 12; 1256 1257 /* 1258 * Since NVMe 1.0, a controller should have at least one bit set in CAP.CSS. 1259 * A controller that does not have any bit set in CAP.CSS is not spec compliant. 1260 * Try to support such a controller regardless. 1261 */ 1262 if (ctrlr->cap.bits.css == 0) { 1263 NVME_CTRLR_INFOLOG(ctrlr, "Drive reports no command sets supported. Assuming NVM is supported.\n"); 1264 ctrlr->cap.bits.css = SPDK_NVME_CAP_CSS_NVM; 1265 } 1266 1267 /* 1268 * If the user did not explicitly request a command set, or supplied a value larger than 1269 * what can be saved in CC.CSS, use the most reasonable default. 1270 */ 1271 if (ctrlr->opts.command_set >= CHAR_BIT) { 1272 if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS) { 1273 ctrlr->opts.command_set = SPDK_NVME_CC_CSS_IOCS; 1274 } else if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_NVM) { 1275 ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM; 1276 } else if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_NOIO) { 1277 ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NOIO; 1278 } else { 1279 /* Invalid supported bits detected, falling back to NVM. */ 1280 ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM; 1281 } 1282 } 1283 1284 /* Verify that the selected command set is supported by the controller. */ 1285 if (!(ctrlr->cap.bits.css & (1u << ctrlr->opts.command_set))) { 1286 NVME_CTRLR_DEBUGLOG(ctrlr, "Requested I/O command set %u but supported mask is 0x%x\n", 1287 ctrlr->opts.command_set, ctrlr->cap.bits.css); 1288 NVME_CTRLR_DEBUGLOG(ctrlr, "Falling back to NVM. Assuming NVM is supported.\n"); 1289 ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM; 1290 } 1291 1292 cc.bits.css = ctrlr->opts.command_set; 1293 1294 switch (ctrlr->opts.arb_mechanism) { 1295 case SPDK_NVME_CC_AMS_RR: 1296 break; 1297 case SPDK_NVME_CC_AMS_WRR: 1298 if (SPDK_NVME_CAP_AMS_WRR & ctrlr->cap.bits.ams) { 1299 break; 1300 } 1301 return -EINVAL; 1302 case SPDK_NVME_CC_AMS_VS: 1303 if (SPDK_NVME_CAP_AMS_VS & ctrlr->cap.bits.ams) { 1304 break; 1305 } 1306 return -EINVAL; 1307 default: 1308 return -EINVAL; 1309 } 1310 1311 cc.bits.ams = ctrlr->opts.arb_mechanism; 1312 ctrlr->process_init_cc.raw = cc.raw; 1313 1314 if (nvme_ctrlr_set_cc_async(ctrlr, cc.raw, nvme_ctrlr_set_cc_en_done, ctrlr)) { 1315 NVME_CTRLR_ERRLOG(ctrlr, "set_cc() failed\n"); 1316 return -EIO; 1317 } 1318 1319 return 0; 1320 } 1321 1322 static const char * 1323 nvme_ctrlr_state_string(enum nvme_ctrlr_state state) 1324 { 1325 switch (state) { 1326 case NVME_CTRLR_STATE_INIT_DELAY: 1327 return "delay init"; 1328 case NVME_CTRLR_STATE_CONNECT_ADMINQ: 1329 return "connect adminq"; 1330 case NVME_CTRLR_STATE_WAIT_FOR_CONNECT_ADMINQ: 1331 return "wait for connect adminq"; 1332 case NVME_CTRLR_STATE_READ_VS: 1333 return "read vs"; 1334 case NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS: 1335 return "read vs wait for vs"; 1336 case NVME_CTRLR_STATE_READ_CAP: 1337 return "read cap"; 1338 case NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP: 1339 return "read cap wait for cap"; 1340 case NVME_CTRLR_STATE_CHECK_EN: 1341 return "check en"; 1342 case NVME_CTRLR_STATE_CHECK_EN_WAIT_FOR_CC: 1343 return "check en wait for cc"; 1344 case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1: 1345 return "disable and wait for CSTS.RDY = 1"; 1346 case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS: 1347 return "disable and wait for CSTS.RDY = 1 reg"; 1348 case NVME_CTRLR_STATE_SET_EN_0: 1349 return "set CC.EN = 0"; 1350 case NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC: 1351 return "set CC.EN = 0 wait for cc"; 1352 case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0: 1353 return "disable and wait for CSTS.RDY = 0"; 1354 case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS: 1355 return "disable and wait for CSTS.RDY = 0 reg"; 1356 case NVME_CTRLR_STATE_DISABLED: 1357 return "controller is disabled"; 1358 case NVME_CTRLR_STATE_ENABLE: 1359 return "enable controller by writing CC.EN = 1"; 1360 case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC: 1361 return "enable controller by writing CC.EN = 1 reg"; 1362 case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1: 1363 return "wait for CSTS.RDY = 1"; 1364 case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS: 1365 return "wait for CSTS.RDY = 1 reg"; 1366 case NVME_CTRLR_STATE_RESET_ADMIN_QUEUE: 1367 return "reset admin queue"; 1368 case NVME_CTRLR_STATE_IDENTIFY: 1369 return "identify controller"; 1370 case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY: 1371 return "wait for identify controller"; 1372 case NVME_CTRLR_STATE_CONFIGURE_AER: 1373 return "configure AER"; 1374 case NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER: 1375 return "wait for configure aer"; 1376 case NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT: 1377 return "set keep alive timeout"; 1378 case NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT: 1379 return "wait for set keep alive timeout"; 1380 case NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC: 1381 return "identify controller iocs specific"; 1382 case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC: 1383 return "wait for identify controller iocs specific"; 1384 case NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG: 1385 return "get zns cmd and effects log page"; 1386 case NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG: 1387 return "wait for get zns cmd and effects log page"; 1388 case NVME_CTRLR_STATE_SET_NUM_QUEUES: 1389 return "set number of queues"; 1390 case NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES: 1391 return "wait for set number of queues"; 1392 case NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS: 1393 return "identify active ns"; 1394 case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS: 1395 return "wait for identify active ns"; 1396 case NVME_CTRLR_STATE_IDENTIFY_NS: 1397 return "identify ns"; 1398 case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS: 1399 return "wait for identify ns"; 1400 case NVME_CTRLR_STATE_IDENTIFY_ID_DESCS: 1401 return "identify namespace id descriptors"; 1402 case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS: 1403 return "wait for identify namespace id descriptors"; 1404 case NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC: 1405 return "identify ns iocs specific"; 1406 case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC: 1407 return "wait for identify ns iocs specific"; 1408 case NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES: 1409 return "set supported log pages"; 1410 case NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES: 1411 return "set supported INTEL log pages"; 1412 case NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES: 1413 return "wait for supported INTEL log pages"; 1414 case NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES: 1415 return "set supported features"; 1416 case NVME_CTRLR_STATE_SET_DB_BUF_CFG: 1417 return "set doorbell buffer config"; 1418 case NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG: 1419 return "wait for doorbell buffer config"; 1420 case NVME_CTRLR_STATE_SET_HOST_ID: 1421 return "set host ID"; 1422 case NVME_CTRLR_STATE_WAIT_FOR_HOST_ID: 1423 return "wait for set host ID"; 1424 case NVME_CTRLR_STATE_TRANSPORT_READY: 1425 return "transport ready"; 1426 case NVME_CTRLR_STATE_READY: 1427 return "ready"; 1428 case NVME_CTRLR_STATE_ERROR: 1429 return "error"; 1430 case NVME_CTRLR_STATE_DISCONNECTED: 1431 return "disconnected"; 1432 } 1433 return "unknown"; 1434 }; 1435 1436 static void 1437 _nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state, 1438 uint64_t timeout_in_ms, bool quiet) 1439 { 1440 uint64_t ticks_per_ms, timeout_in_ticks, now_ticks; 1441 1442 ctrlr->state = state; 1443 if (timeout_in_ms == NVME_TIMEOUT_KEEP_EXISTING) { 1444 if (!quiet) { 1445 NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (keeping existing timeout)\n", 1446 nvme_ctrlr_state_string(ctrlr->state)); 1447 } 1448 return; 1449 } 1450 1451 if (timeout_in_ms == NVME_TIMEOUT_INFINITE) { 1452 goto inf; 1453 } 1454 1455 ticks_per_ms = spdk_get_ticks_hz() / 1000; 1456 if (timeout_in_ms > UINT64_MAX / ticks_per_ms) { 1457 NVME_CTRLR_ERRLOG(ctrlr, 1458 "Specified timeout would cause integer overflow. Defaulting to no timeout.\n"); 1459 goto inf; 1460 } 1461 1462 now_ticks = spdk_get_ticks(); 1463 timeout_in_ticks = timeout_in_ms * ticks_per_ms; 1464 if (timeout_in_ticks > UINT64_MAX - now_ticks) { 1465 NVME_CTRLR_ERRLOG(ctrlr, 1466 "Specified timeout would cause integer overflow. Defaulting to no timeout.\n"); 1467 goto inf; 1468 } 1469 1470 ctrlr->state_timeout_tsc = timeout_in_ticks + now_ticks; 1471 if (!quiet) { 1472 NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (timeout %" PRIu64 " ms)\n", 1473 nvme_ctrlr_state_string(ctrlr->state), timeout_in_ms); 1474 } 1475 return; 1476 inf: 1477 if (!quiet) { 1478 NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (no timeout)\n", 1479 nvme_ctrlr_state_string(ctrlr->state)); 1480 } 1481 ctrlr->state_timeout_tsc = NVME_TIMEOUT_INFINITE; 1482 } 1483 1484 static void 1485 nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state, 1486 uint64_t timeout_in_ms) 1487 { 1488 _nvme_ctrlr_set_state(ctrlr, state, timeout_in_ms, false); 1489 } 1490 1491 static void 1492 nvme_ctrlr_set_state_quiet(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state, 1493 uint64_t timeout_in_ms) 1494 { 1495 _nvme_ctrlr_set_state(ctrlr, state, timeout_in_ms, true); 1496 } 1497 1498 static void 1499 nvme_ctrlr_free_zns_specific_data(struct spdk_nvme_ctrlr *ctrlr) 1500 { 1501 spdk_free(ctrlr->cdata_zns); 1502 ctrlr->cdata_zns = NULL; 1503 } 1504 1505 static void 1506 nvme_ctrlr_free_iocs_specific_data(struct spdk_nvme_ctrlr *ctrlr) 1507 { 1508 nvme_ctrlr_free_zns_specific_data(ctrlr); 1509 } 1510 1511 static void 1512 nvme_ctrlr_free_doorbell_buffer(struct spdk_nvme_ctrlr *ctrlr) 1513 { 1514 if (ctrlr->shadow_doorbell) { 1515 spdk_free(ctrlr->shadow_doorbell); 1516 ctrlr->shadow_doorbell = NULL; 1517 } 1518 1519 if (ctrlr->eventidx) { 1520 spdk_free(ctrlr->eventidx); 1521 ctrlr->eventidx = NULL; 1522 } 1523 } 1524 1525 static void 1526 nvme_ctrlr_set_doorbell_buffer_config_done(void *arg, const struct spdk_nvme_cpl *cpl) 1527 { 1528 struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg; 1529 1530 if (spdk_nvme_cpl_is_error(cpl)) { 1531 NVME_CTRLR_WARNLOG(ctrlr, "Doorbell buffer config failed\n"); 1532 } else { 1533 NVME_CTRLR_INFOLOG(ctrlr, "Doorbell buffer config enabled\n"); 1534 } 1535 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID, 1536 ctrlr->opts.admin_timeout_ms); 1537 } 1538 1539 static int 1540 nvme_ctrlr_set_doorbell_buffer_config(struct spdk_nvme_ctrlr *ctrlr) 1541 { 1542 int rc = 0; 1543 uint64_t prp1, prp2, len; 1544 1545 if (!ctrlr->cdata.oacs.doorbell_buffer_config) { 1546 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID, 1547 ctrlr->opts.admin_timeout_ms); 1548 return 0; 1549 } 1550 1551 if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) { 1552 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID, 1553 ctrlr->opts.admin_timeout_ms); 1554 return 0; 1555 } 1556 1557 /* only 1 page size for doorbell buffer */ 1558 ctrlr->shadow_doorbell = spdk_zmalloc(ctrlr->page_size, ctrlr->page_size, 1559 NULL, SPDK_ENV_LCORE_ID_ANY, 1560 SPDK_MALLOC_DMA | SPDK_MALLOC_SHARE); 1561 if (ctrlr->shadow_doorbell == NULL) { 1562 rc = -ENOMEM; 1563 goto error; 1564 } 1565 1566 len = ctrlr->page_size; 1567 prp1 = spdk_vtophys(ctrlr->shadow_doorbell, &len); 1568 if (prp1 == SPDK_VTOPHYS_ERROR || len != ctrlr->page_size) { 1569 rc = -EFAULT; 1570 goto error; 1571 } 1572 1573 ctrlr->eventidx = spdk_zmalloc(ctrlr->page_size, ctrlr->page_size, 1574 NULL, SPDK_ENV_LCORE_ID_ANY, 1575 SPDK_MALLOC_DMA | SPDK_MALLOC_SHARE); 1576 if (ctrlr->eventidx == NULL) { 1577 rc = -ENOMEM; 1578 goto error; 1579 } 1580 1581 len = ctrlr->page_size; 1582 prp2 = spdk_vtophys(ctrlr->eventidx, &len); 1583 if (prp2 == SPDK_VTOPHYS_ERROR || len != ctrlr->page_size) { 1584 rc = -EFAULT; 1585 goto error; 1586 } 1587 1588 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG, 1589 ctrlr->opts.admin_timeout_ms); 1590 1591 rc = nvme_ctrlr_cmd_doorbell_buffer_config(ctrlr, prp1, prp2, 1592 nvme_ctrlr_set_doorbell_buffer_config_done, ctrlr); 1593 if (rc != 0) { 1594 goto error; 1595 } 1596 1597 return 0; 1598 1599 error: 1600 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 1601 nvme_ctrlr_free_doorbell_buffer(ctrlr); 1602 return rc; 1603 } 1604 1605 void 1606 nvme_ctrlr_abort_queued_aborts(struct spdk_nvme_ctrlr *ctrlr) 1607 { 1608 struct nvme_request *req, *tmp; 1609 struct spdk_nvme_cpl cpl = {}; 1610 1611 cpl.status.sc = SPDK_NVME_SC_ABORTED_SQ_DELETION; 1612 cpl.status.sct = SPDK_NVME_SCT_GENERIC; 1613 1614 STAILQ_FOREACH_SAFE(req, &ctrlr->queued_aborts, stailq, tmp) { 1615 STAILQ_REMOVE_HEAD(&ctrlr->queued_aborts, stailq); 1616 ctrlr->outstanding_aborts++; 1617 1618 nvme_complete_request(req->cb_fn, req->cb_arg, req->qpair, req, &cpl); 1619 } 1620 } 1621 1622 static int 1623 nvme_ctrlr_disconnect(struct spdk_nvme_ctrlr *ctrlr) 1624 { 1625 if (ctrlr->is_resetting || ctrlr->is_removed) { 1626 /* 1627 * Controller is already resetting or has been removed. Return 1628 * immediately since there is no need to kick off another 1629 * reset in these cases. 1630 */ 1631 return ctrlr->is_resetting ? -EBUSY : -ENXIO; 1632 } 1633 1634 ctrlr->is_resetting = true; 1635 ctrlr->is_failed = false; 1636 ctrlr->is_disconnecting = true; 1637 ctrlr->prepare_for_reset = true; 1638 1639 NVME_CTRLR_NOTICELOG(ctrlr, "resetting controller\n"); 1640 1641 /* Disable keep-alive, it'll be re-enabled as part of the init process */ 1642 ctrlr->keep_alive_interval_ticks = 0; 1643 1644 /* Abort all of the queued abort requests */ 1645 nvme_ctrlr_abort_queued_aborts(ctrlr); 1646 1647 nvme_transport_admin_qpair_abort_aers(ctrlr->adminq); 1648 1649 ctrlr->adminq->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL; 1650 nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq); 1651 1652 return 0; 1653 } 1654 1655 static void 1656 nvme_ctrlr_disconnect_done(struct spdk_nvme_ctrlr *ctrlr) 1657 { 1658 assert(ctrlr->is_failed == false); 1659 ctrlr->is_disconnecting = false; 1660 1661 /* Doorbell buffer config is invalid during reset */ 1662 nvme_ctrlr_free_doorbell_buffer(ctrlr); 1663 1664 /* I/O Command Set Specific Identify Controller data is invalidated during reset */ 1665 nvme_ctrlr_free_iocs_specific_data(ctrlr); 1666 1667 spdk_bit_array_free(&ctrlr->free_io_qids); 1668 1669 /* Set the state back to DISCONNECTED to cause a full hardware reset. */ 1670 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISCONNECTED, NVME_TIMEOUT_INFINITE); 1671 } 1672 1673 int 1674 spdk_nvme_ctrlr_disconnect(struct spdk_nvme_ctrlr *ctrlr) 1675 { 1676 int rc; 1677 1678 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 1679 rc = nvme_ctrlr_disconnect(ctrlr); 1680 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 1681 1682 return rc; 1683 } 1684 1685 void 1686 spdk_nvme_ctrlr_reconnect_async(struct spdk_nvme_ctrlr *ctrlr) 1687 { 1688 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 1689 1690 ctrlr->prepare_for_reset = false; 1691 1692 /* Set the state back to INIT to cause a full hardware reset. */ 1693 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE); 1694 1695 /* Return without releasing ctrlr_lock. ctrlr_lock will be released when 1696 * spdk_nvme_ctrlr_reset_poll_async() returns 0. 1697 */ 1698 } 1699 1700 int 1701 nvme_ctrlr_reinitialize_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair) 1702 { 1703 bool async; 1704 int rc; 1705 1706 if (nvme_ctrlr_get_current_process(ctrlr) != qpair->active_proc || 1707 spdk_nvme_ctrlr_is_fabrics(ctrlr) || nvme_qpair_is_admin_queue(qpair)) { 1708 assert(false); 1709 return -EINVAL; 1710 } 1711 1712 /* Force a synchronous connect. */ 1713 async = qpair->async; 1714 qpair->async = false; 1715 rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair); 1716 qpair->async = async; 1717 1718 if (rc != 0) { 1719 qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL; 1720 } 1721 1722 return rc; 1723 } 1724 1725 /** 1726 * This function will be called when the controller is being reinitialized. 1727 * Note: the ctrlr_lock must be held when calling this function. 1728 */ 1729 int 1730 spdk_nvme_ctrlr_reconnect_poll_async(struct spdk_nvme_ctrlr *ctrlr) 1731 { 1732 struct spdk_nvme_ns *ns, *tmp_ns; 1733 struct spdk_nvme_qpair *qpair; 1734 int rc = 0, rc_tmp = 0; 1735 1736 if (nvme_ctrlr_process_init(ctrlr) != 0) { 1737 NVME_CTRLR_ERRLOG(ctrlr, "controller reinitialization failed\n"); 1738 rc = -1; 1739 } 1740 if (ctrlr->state != NVME_CTRLR_STATE_READY && rc != -1) { 1741 return -EAGAIN; 1742 } 1743 1744 /* 1745 * For non-fabrics controllers, the memory locations of the transport qpair 1746 * don't change when the controller is reset. They simply need to be 1747 * re-enabled with admin commands to the controller. For fabric 1748 * controllers we need to disconnect and reconnect the qpair on its 1749 * own thread outside of the context of the reset. 1750 */ 1751 if (rc == 0 && !spdk_nvme_ctrlr_is_fabrics(ctrlr)) { 1752 /* Reinitialize qpairs */ 1753 TAILQ_FOREACH(qpair, &ctrlr->active_io_qpairs, tailq) { 1754 /* Always clear the qid bit here, even for a foreign qpair. We need 1755 * to make sure another process doesn't get the chance to grab that 1756 * qid. 1757 */ 1758 assert(spdk_bit_array_get(ctrlr->free_io_qids, qpair->id)); 1759 spdk_bit_array_clear(ctrlr->free_io_qids, qpair->id); 1760 if (nvme_ctrlr_get_current_process(ctrlr) != qpair->active_proc) { 1761 /* 1762 * We cannot reinitialize a foreign qpair. The qpair's owning 1763 * process will take care of it. Set failure reason to FAILURE_RESET 1764 * to ensure that happens. 1765 */ 1766 qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_RESET; 1767 continue; 1768 } 1769 rc_tmp = nvme_ctrlr_reinitialize_io_qpair(ctrlr, qpair); 1770 if (rc_tmp != 0) { 1771 rc = rc_tmp; 1772 } 1773 } 1774 } 1775 1776 /* 1777 * Take this opportunity to remove inactive namespaces. During a reset namespace 1778 * handles can be invalidated. 1779 */ 1780 RB_FOREACH_SAFE(ns, nvme_ns_tree, &ctrlr->ns, tmp_ns) { 1781 if (!ns->active) { 1782 RB_REMOVE(nvme_ns_tree, &ctrlr->ns, ns); 1783 spdk_free(ns); 1784 } 1785 } 1786 1787 if (rc) { 1788 nvme_ctrlr_fail(ctrlr, false); 1789 } 1790 ctrlr->is_resetting = false; 1791 1792 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 1793 1794 if (!ctrlr->cdata.oaes.ns_attribute_notices) { 1795 /* 1796 * If controller doesn't support ns_attribute_notices and 1797 * namespace attributes change (e.g. number of namespaces) 1798 * we need to update system handling device reset. 1799 */ 1800 nvme_io_msg_ctrlr_update(ctrlr); 1801 } 1802 1803 return rc; 1804 } 1805 1806 /* 1807 * For PCIe transport, spdk_nvme_ctrlr_disconnect() will do a Controller Level Reset 1808 * (Change CC.EN from 1 to 0) as a operation to disconnect the admin qpair. 1809 * The following two functions are added to do a Controller Level Reset. They have 1810 * to be called under the nvme controller's lock. 1811 */ 1812 void 1813 nvme_ctrlr_disable(struct spdk_nvme_ctrlr *ctrlr) 1814 { 1815 assert(ctrlr->is_disconnecting == true); 1816 1817 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN, NVME_TIMEOUT_INFINITE); 1818 } 1819 1820 int 1821 nvme_ctrlr_disable_poll(struct spdk_nvme_ctrlr *ctrlr) 1822 { 1823 int rc = 0; 1824 1825 if (nvme_ctrlr_process_init(ctrlr) != 0) { 1826 NVME_CTRLR_ERRLOG(ctrlr, "failed to disable controller\n"); 1827 rc = -1; 1828 } 1829 1830 if (ctrlr->state != NVME_CTRLR_STATE_DISABLED && rc != -1) { 1831 return -EAGAIN; 1832 } 1833 1834 return rc; 1835 } 1836 1837 static void 1838 nvme_ctrlr_fail_io_qpairs(struct spdk_nvme_ctrlr *ctrlr) 1839 { 1840 struct spdk_nvme_qpair *qpair; 1841 1842 TAILQ_FOREACH(qpair, &ctrlr->active_io_qpairs, tailq) { 1843 qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL; 1844 } 1845 } 1846 1847 int 1848 spdk_nvme_ctrlr_reset(struct spdk_nvme_ctrlr *ctrlr) 1849 { 1850 int rc; 1851 1852 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 1853 1854 rc = nvme_ctrlr_disconnect(ctrlr); 1855 if (rc == 0) { 1856 nvme_ctrlr_fail_io_qpairs(ctrlr); 1857 } 1858 1859 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 1860 1861 if (rc != 0) { 1862 if (rc == -EBUSY) { 1863 rc = 0; 1864 } 1865 return rc; 1866 } 1867 1868 while (1) { 1869 rc = spdk_nvme_ctrlr_process_admin_completions(ctrlr); 1870 if (rc == -ENXIO) { 1871 break; 1872 } 1873 } 1874 1875 spdk_nvme_ctrlr_reconnect_async(ctrlr); 1876 1877 while (true) { 1878 rc = spdk_nvme_ctrlr_reconnect_poll_async(ctrlr); 1879 if (rc != -EAGAIN) { 1880 break; 1881 } 1882 } 1883 1884 return rc; 1885 } 1886 1887 int 1888 spdk_nvme_ctrlr_reset_subsystem(struct spdk_nvme_ctrlr *ctrlr) 1889 { 1890 union spdk_nvme_cap_register cap; 1891 int rc = 0; 1892 1893 cap = spdk_nvme_ctrlr_get_regs_cap(ctrlr); 1894 if (cap.bits.nssrs == 0) { 1895 NVME_CTRLR_WARNLOG(ctrlr, "subsystem reset is not supported\n"); 1896 return -ENOTSUP; 1897 } 1898 1899 NVME_CTRLR_NOTICELOG(ctrlr, "resetting subsystem\n"); 1900 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 1901 ctrlr->is_resetting = true; 1902 rc = nvme_ctrlr_set_nssr(ctrlr, SPDK_NVME_NSSR_VALUE); 1903 ctrlr->is_resetting = false; 1904 1905 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 1906 /* 1907 * No more cleanup at this point like in the ctrlr reset. A subsystem reset will cause 1908 * a hot remove for PCIe transport. The hot remove handling does all the necessary ctrlr cleanup. 1909 */ 1910 return rc; 1911 } 1912 1913 int 1914 spdk_nvme_ctrlr_set_trid(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_transport_id *trid) 1915 { 1916 int rc = 0; 1917 1918 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 1919 1920 if (ctrlr->is_failed == false) { 1921 rc = -EPERM; 1922 goto out; 1923 } 1924 1925 if (trid->trtype != ctrlr->trid.trtype) { 1926 rc = -EINVAL; 1927 goto out; 1928 } 1929 1930 if (strncmp(trid->subnqn, ctrlr->trid.subnqn, SPDK_NVMF_NQN_MAX_LEN)) { 1931 rc = -EINVAL; 1932 goto out; 1933 } 1934 1935 ctrlr->trid = *trid; 1936 1937 out: 1938 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 1939 return rc; 1940 } 1941 1942 void 1943 spdk_nvme_ctrlr_set_remove_cb(struct spdk_nvme_ctrlr *ctrlr, 1944 spdk_nvme_remove_cb remove_cb, void *remove_ctx) 1945 { 1946 if (!spdk_process_is_primary()) { 1947 return; 1948 } 1949 1950 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 1951 ctrlr->remove_cb = remove_cb; 1952 ctrlr->cb_ctx = remove_ctx; 1953 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 1954 } 1955 1956 static void 1957 nvme_ctrlr_identify_done(void *arg, const struct spdk_nvme_cpl *cpl) 1958 { 1959 struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg; 1960 1961 if (spdk_nvme_cpl_is_error(cpl)) { 1962 NVME_CTRLR_ERRLOG(ctrlr, "nvme_identify_controller failed!\n"); 1963 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 1964 return; 1965 } 1966 1967 /* 1968 * Use MDTS to ensure our default max_xfer_size doesn't exceed what the 1969 * controller supports. 1970 */ 1971 ctrlr->max_xfer_size = nvme_transport_ctrlr_get_max_xfer_size(ctrlr); 1972 NVME_CTRLR_DEBUGLOG(ctrlr, "transport max_xfer_size %u\n", ctrlr->max_xfer_size); 1973 if (ctrlr->cdata.mdts > 0) { 1974 ctrlr->max_xfer_size = spdk_min(ctrlr->max_xfer_size, 1975 ctrlr->min_page_size * (1 << ctrlr->cdata.mdts)); 1976 NVME_CTRLR_DEBUGLOG(ctrlr, "MDTS max_xfer_size %u\n", ctrlr->max_xfer_size); 1977 } 1978 1979 NVME_CTRLR_DEBUGLOG(ctrlr, "CNTLID 0x%04" PRIx16 "\n", ctrlr->cdata.cntlid); 1980 if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) { 1981 ctrlr->cntlid = ctrlr->cdata.cntlid; 1982 } else { 1983 /* 1984 * Fabrics controllers should already have CNTLID from the Connect command. 1985 * 1986 * If CNTLID from Connect doesn't match CNTLID in the Identify Controller data, 1987 * trust the one from Connect. 1988 */ 1989 if (ctrlr->cntlid != ctrlr->cdata.cntlid) { 1990 NVME_CTRLR_DEBUGLOG(ctrlr, "Identify CNTLID 0x%04" PRIx16 " != Connect CNTLID 0x%04" PRIx16 "\n", 1991 ctrlr->cdata.cntlid, ctrlr->cntlid); 1992 } 1993 } 1994 1995 if (ctrlr->cdata.sgls.supported && !(ctrlr->quirks & NVME_QUIRK_NOT_USE_SGL)) { 1996 assert(ctrlr->cdata.sgls.supported != 0x3); 1997 ctrlr->flags |= SPDK_NVME_CTRLR_SGL_SUPPORTED; 1998 if (ctrlr->cdata.sgls.supported == 0x2) { 1999 ctrlr->flags |= SPDK_NVME_CTRLR_SGL_REQUIRES_DWORD_ALIGNMENT; 2000 } 2001 2002 ctrlr->max_sges = nvme_transport_ctrlr_get_max_sges(ctrlr); 2003 NVME_CTRLR_DEBUGLOG(ctrlr, "transport max_sges %u\n", ctrlr->max_sges); 2004 } 2005 2006 if (ctrlr->cdata.sgls.metadata_address && !(ctrlr->quirks & NVME_QUIRK_NOT_USE_SGL)) { 2007 ctrlr->flags |= SPDK_NVME_CTRLR_MPTR_SGL_SUPPORTED; 2008 } 2009 2010 if (ctrlr->cdata.oacs.security && !(ctrlr->quirks & NVME_QUIRK_OACS_SECURITY)) { 2011 ctrlr->flags |= SPDK_NVME_CTRLR_SECURITY_SEND_RECV_SUPPORTED; 2012 } 2013 2014 if (ctrlr->cdata.oacs.directives) { 2015 ctrlr->flags |= SPDK_NVME_CTRLR_DIRECTIVES_SUPPORTED; 2016 } 2017 2018 NVME_CTRLR_DEBUGLOG(ctrlr, "fuses compare and write: %d\n", 2019 ctrlr->cdata.fuses.compare_and_write); 2020 if (ctrlr->cdata.fuses.compare_and_write) { 2021 ctrlr->flags |= SPDK_NVME_CTRLR_COMPARE_AND_WRITE_SUPPORTED; 2022 } 2023 2024 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CONFIGURE_AER, 2025 ctrlr->opts.admin_timeout_ms); 2026 } 2027 2028 static int 2029 nvme_ctrlr_identify(struct spdk_nvme_ctrlr *ctrlr) 2030 { 2031 int rc; 2032 2033 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY, 2034 ctrlr->opts.admin_timeout_ms); 2035 2036 rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_CTRLR, 0, 0, 0, 2037 &ctrlr->cdata, sizeof(ctrlr->cdata), 2038 nvme_ctrlr_identify_done, ctrlr); 2039 if (rc != 0) { 2040 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2041 return rc; 2042 } 2043 2044 return 0; 2045 } 2046 2047 static void 2048 nvme_ctrlr_get_zns_cmd_and_effects_log_done(void *arg, const struct spdk_nvme_cpl *cpl) 2049 { 2050 struct spdk_nvme_cmds_and_effect_log_page *log_page; 2051 struct spdk_nvme_ctrlr *ctrlr = arg; 2052 2053 if (spdk_nvme_cpl_is_error(cpl)) { 2054 NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_get_zns_cmd_and_effects_log failed!\n"); 2055 spdk_free(ctrlr->tmp_ptr); 2056 ctrlr->tmp_ptr = NULL; 2057 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2058 return; 2059 } 2060 2061 log_page = ctrlr->tmp_ptr; 2062 2063 if (log_page->io_cmds_supported[SPDK_NVME_OPC_ZONE_APPEND].csupp) { 2064 ctrlr->flags |= SPDK_NVME_CTRLR_ZONE_APPEND_SUPPORTED; 2065 } 2066 spdk_free(ctrlr->tmp_ptr); 2067 ctrlr->tmp_ptr = NULL; 2068 2069 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES, ctrlr->opts.admin_timeout_ms); 2070 } 2071 2072 static int 2073 nvme_ctrlr_get_zns_cmd_and_effects_log(struct spdk_nvme_ctrlr *ctrlr) 2074 { 2075 int rc; 2076 2077 assert(!ctrlr->tmp_ptr); 2078 ctrlr->tmp_ptr = spdk_zmalloc(sizeof(struct spdk_nvme_cmds_and_effect_log_page), 64, NULL, 2079 SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE | SPDK_MALLOC_DMA); 2080 if (!ctrlr->tmp_ptr) { 2081 rc = -ENOMEM; 2082 goto error; 2083 } 2084 2085 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG, 2086 ctrlr->opts.admin_timeout_ms); 2087 2088 rc = spdk_nvme_ctrlr_cmd_get_log_page_ext(ctrlr, SPDK_NVME_LOG_COMMAND_EFFECTS_LOG, 2089 0, ctrlr->tmp_ptr, sizeof(struct spdk_nvme_cmds_and_effect_log_page), 2090 0, 0, 0, SPDK_NVME_CSI_ZNS << 24, 2091 nvme_ctrlr_get_zns_cmd_and_effects_log_done, ctrlr); 2092 if (rc != 0) { 2093 goto error; 2094 } 2095 2096 return 0; 2097 2098 error: 2099 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2100 spdk_free(ctrlr->tmp_ptr); 2101 ctrlr->tmp_ptr = NULL; 2102 return rc; 2103 } 2104 2105 static void 2106 nvme_ctrlr_identify_zns_specific_done(void *arg, const struct spdk_nvme_cpl *cpl) 2107 { 2108 struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg; 2109 2110 if (spdk_nvme_cpl_is_error(cpl)) { 2111 /* no need to print an error, the controller simply does not support ZNS */ 2112 nvme_ctrlr_free_zns_specific_data(ctrlr); 2113 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES, 2114 ctrlr->opts.admin_timeout_ms); 2115 return; 2116 } 2117 2118 /* A zero zasl value means use mdts */ 2119 if (ctrlr->cdata_zns->zasl) { 2120 uint32_t max_append = ctrlr->min_page_size * (1 << ctrlr->cdata_zns->zasl); 2121 ctrlr->max_zone_append_size = spdk_min(ctrlr->max_xfer_size, max_append); 2122 } else { 2123 ctrlr->max_zone_append_size = ctrlr->max_xfer_size; 2124 } 2125 2126 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG, 2127 ctrlr->opts.admin_timeout_ms); 2128 } 2129 2130 /** 2131 * This function will try to fetch the I/O Command Specific Controller data structure for 2132 * each I/O Command Set supported by SPDK. 2133 * 2134 * If an I/O Command Set is not supported by the controller, "Invalid Field in Command" 2135 * will be returned. Since we are fetching in a exploratively way, getting an error back 2136 * from the controller should not be treated as fatal. 2137 * 2138 * I/O Command Sets not supported by SPDK will be skipped (e.g. Key Value Command Set). 2139 * 2140 * I/O Command Sets without a IOCS specific data structure (i.e. a zero-filled IOCS specific 2141 * data structure) will be skipped (e.g. NVM Command Set, Key Value Command Set). 2142 */ 2143 static int 2144 nvme_ctrlr_identify_iocs_specific(struct spdk_nvme_ctrlr *ctrlr) 2145 { 2146 int rc; 2147 2148 if (!nvme_ctrlr_multi_iocs_enabled(ctrlr)) { 2149 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES, 2150 ctrlr->opts.admin_timeout_ms); 2151 return 0; 2152 } 2153 2154 /* 2155 * Since SPDK currently only needs to fetch a single Command Set, keep the code here, 2156 * instead of creating multiple NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC substates, 2157 * which would require additional functions and complexity for no good reason. 2158 */ 2159 assert(!ctrlr->cdata_zns); 2160 ctrlr->cdata_zns = spdk_zmalloc(sizeof(*ctrlr->cdata_zns), 64, NULL, SPDK_ENV_SOCKET_ID_ANY, 2161 SPDK_MALLOC_SHARE | SPDK_MALLOC_DMA); 2162 if (!ctrlr->cdata_zns) { 2163 rc = -ENOMEM; 2164 goto error; 2165 } 2166 2167 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC, 2168 ctrlr->opts.admin_timeout_ms); 2169 2170 rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_CTRLR_IOCS, 0, 0, SPDK_NVME_CSI_ZNS, 2171 ctrlr->cdata_zns, sizeof(*ctrlr->cdata_zns), 2172 nvme_ctrlr_identify_zns_specific_done, ctrlr); 2173 if (rc != 0) { 2174 goto error; 2175 } 2176 2177 return 0; 2178 2179 error: 2180 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2181 nvme_ctrlr_free_zns_specific_data(ctrlr); 2182 return rc; 2183 } 2184 2185 enum nvme_active_ns_state { 2186 NVME_ACTIVE_NS_STATE_IDLE, 2187 NVME_ACTIVE_NS_STATE_PROCESSING, 2188 NVME_ACTIVE_NS_STATE_DONE, 2189 NVME_ACTIVE_NS_STATE_ERROR 2190 }; 2191 2192 typedef void (*nvme_active_ns_ctx_deleter)(struct nvme_active_ns_ctx *); 2193 2194 struct nvme_active_ns_ctx { 2195 struct spdk_nvme_ctrlr *ctrlr; 2196 uint32_t page_count; 2197 uint32_t next_nsid; 2198 uint32_t *new_ns_list; 2199 nvme_active_ns_ctx_deleter deleter; 2200 2201 enum nvme_active_ns_state state; 2202 }; 2203 2204 static struct nvme_active_ns_ctx * 2205 nvme_active_ns_ctx_create(struct spdk_nvme_ctrlr *ctrlr, nvme_active_ns_ctx_deleter deleter) 2206 { 2207 struct nvme_active_ns_ctx *ctx; 2208 uint32_t *new_ns_list = NULL; 2209 2210 ctx = calloc(1, sizeof(*ctx)); 2211 if (!ctx) { 2212 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate nvme_active_ns_ctx!\n"); 2213 return NULL; 2214 } 2215 2216 new_ns_list = spdk_zmalloc(sizeof(struct spdk_nvme_ns_list), ctrlr->page_size, 2217 NULL, SPDK_ENV_LCORE_ID_ANY, SPDK_MALLOC_SHARE); 2218 if (!new_ns_list) { 2219 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate active_ns_list!\n"); 2220 free(ctx); 2221 return NULL; 2222 } 2223 2224 ctx->page_count = 1; 2225 ctx->new_ns_list = new_ns_list; 2226 ctx->ctrlr = ctrlr; 2227 ctx->deleter = deleter; 2228 2229 return ctx; 2230 } 2231 2232 static void 2233 nvme_active_ns_ctx_destroy(struct nvme_active_ns_ctx *ctx) 2234 { 2235 spdk_free(ctx->new_ns_list); 2236 free(ctx); 2237 } 2238 2239 static int 2240 nvme_ctrlr_destruct_namespace(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid) 2241 { 2242 struct spdk_nvme_ns tmp, *ns; 2243 2244 assert(ctrlr != NULL); 2245 2246 tmp.id = nsid; 2247 ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp); 2248 if (ns == NULL) { 2249 return -EINVAL; 2250 } 2251 2252 nvme_ns_destruct(ns); 2253 ns->active = false; 2254 2255 return 0; 2256 } 2257 2258 static int 2259 nvme_ctrlr_construct_namespace(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid) 2260 { 2261 struct spdk_nvme_ns *ns; 2262 2263 if (nsid < 1 || nsid > ctrlr->cdata.nn) { 2264 return -EINVAL; 2265 } 2266 2267 /* Namespaces are constructed on demand, so simply request it. */ 2268 ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid); 2269 if (ns == NULL) { 2270 return -ENOMEM; 2271 } 2272 2273 ns->active = true; 2274 2275 return 0; 2276 } 2277 2278 static void 2279 nvme_ctrlr_identify_active_ns_swap(struct spdk_nvme_ctrlr *ctrlr, uint32_t *new_ns_list, 2280 size_t max_entries) 2281 { 2282 uint32_t active_ns_count = 0; 2283 size_t i; 2284 uint32_t nsid; 2285 struct spdk_nvme_ns *ns, *tmp_ns; 2286 int rc; 2287 2288 /* First, remove namespaces that no longer exist */ 2289 RB_FOREACH_SAFE(ns, nvme_ns_tree, &ctrlr->ns, tmp_ns) { 2290 nsid = new_ns_list[0]; 2291 active_ns_count = 0; 2292 while (nsid != 0) { 2293 if (nsid == ns->id) { 2294 break; 2295 } 2296 2297 nsid = new_ns_list[active_ns_count++]; 2298 } 2299 2300 if (nsid != ns->id) { 2301 /* Did not find this namespace id in the new list. */ 2302 NVME_CTRLR_DEBUGLOG(ctrlr, "Namespace %u was removed\n", ns->id); 2303 nvme_ctrlr_destruct_namespace(ctrlr, ns->id); 2304 } 2305 } 2306 2307 /* Next, add new namespaces */ 2308 active_ns_count = 0; 2309 for (i = 0; i < max_entries; i++) { 2310 nsid = new_ns_list[active_ns_count]; 2311 2312 if (nsid == 0) { 2313 break; 2314 } 2315 2316 /* If the namespace already exists, this will not construct it a second time. */ 2317 rc = nvme_ctrlr_construct_namespace(ctrlr, nsid); 2318 if (rc != 0) { 2319 /* We can't easily handle a failure here. But just move on. */ 2320 assert(false); 2321 NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to allocate a namespace object.\n"); 2322 continue; 2323 } 2324 2325 active_ns_count++; 2326 } 2327 2328 ctrlr->active_ns_count = active_ns_count; 2329 } 2330 2331 static void 2332 nvme_ctrlr_identify_active_ns_async_done(void *arg, const struct spdk_nvme_cpl *cpl) 2333 { 2334 struct nvme_active_ns_ctx *ctx = arg; 2335 uint32_t *new_ns_list = NULL; 2336 2337 if (spdk_nvme_cpl_is_error(cpl)) { 2338 ctx->state = NVME_ACTIVE_NS_STATE_ERROR; 2339 goto out; 2340 } 2341 2342 ctx->next_nsid = ctx->new_ns_list[1024 * ctx->page_count - 1]; 2343 if (ctx->next_nsid == 0) { 2344 ctx->state = NVME_ACTIVE_NS_STATE_DONE; 2345 goto out; 2346 } 2347 2348 ctx->page_count++; 2349 new_ns_list = spdk_realloc(ctx->new_ns_list, 2350 ctx->page_count * sizeof(struct spdk_nvme_ns_list), 2351 ctx->ctrlr->page_size); 2352 if (!new_ns_list) { 2353 SPDK_ERRLOG("Failed to reallocate active_ns_list!\n"); 2354 ctx->state = NVME_ACTIVE_NS_STATE_ERROR; 2355 goto out; 2356 } 2357 2358 ctx->new_ns_list = new_ns_list; 2359 nvme_ctrlr_identify_active_ns_async(ctx); 2360 return; 2361 2362 out: 2363 if (ctx->deleter) { 2364 ctx->deleter(ctx); 2365 } 2366 } 2367 2368 static void 2369 nvme_ctrlr_identify_active_ns_async(struct nvme_active_ns_ctx *ctx) 2370 { 2371 struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr; 2372 uint32_t i; 2373 int rc; 2374 2375 if (ctrlr->cdata.nn == 0) { 2376 ctx->state = NVME_ACTIVE_NS_STATE_DONE; 2377 goto out; 2378 } 2379 2380 assert(ctx->new_ns_list != NULL); 2381 2382 /* 2383 * If controller doesn't support active ns list CNS 0x02 dummy up 2384 * an active ns list, i.e. all namespaces report as active 2385 */ 2386 if (ctrlr->vs.raw < SPDK_NVME_VERSION(1, 1, 0) || ctrlr->quirks & NVME_QUIRK_IDENTIFY_CNS) { 2387 uint32_t *new_ns_list; 2388 2389 /* 2390 * Active NS list must always end with zero element. 2391 * So, we allocate for cdata.nn+1. 2392 */ 2393 ctx->page_count = spdk_divide_round_up(ctrlr->cdata.nn + 1, 2394 sizeof(struct spdk_nvme_ns_list) / sizeof(new_ns_list[0])); 2395 new_ns_list = spdk_realloc(ctx->new_ns_list, 2396 ctx->page_count * sizeof(struct spdk_nvme_ns_list), 2397 ctx->ctrlr->page_size); 2398 if (!new_ns_list) { 2399 SPDK_ERRLOG("Failed to reallocate active_ns_list!\n"); 2400 ctx->state = NVME_ACTIVE_NS_STATE_ERROR; 2401 goto out; 2402 } 2403 2404 ctx->new_ns_list = new_ns_list; 2405 ctx->new_ns_list[ctrlr->cdata.nn] = 0; 2406 for (i = 0; i < ctrlr->cdata.nn; i++) { 2407 ctx->new_ns_list[i] = i + 1; 2408 } 2409 2410 ctx->state = NVME_ACTIVE_NS_STATE_DONE; 2411 goto out; 2412 } 2413 2414 ctx->state = NVME_ACTIVE_NS_STATE_PROCESSING; 2415 rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_ACTIVE_NS_LIST, 0, ctx->next_nsid, 0, 2416 &ctx->new_ns_list[1024 * (ctx->page_count - 1)], sizeof(struct spdk_nvme_ns_list), 2417 nvme_ctrlr_identify_active_ns_async_done, ctx); 2418 if (rc != 0) { 2419 ctx->state = NVME_ACTIVE_NS_STATE_ERROR; 2420 goto out; 2421 } 2422 2423 return; 2424 2425 out: 2426 if (ctx->deleter) { 2427 ctx->deleter(ctx); 2428 } 2429 } 2430 2431 static void 2432 _nvme_active_ns_ctx_deleter(struct nvme_active_ns_ctx *ctx) 2433 { 2434 struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr; 2435 struct spdk_nvme_ns *ns; 2436 2437 if (ctx->state == NVME_ACTIVE_NS_STATE_ERROR) { 2438 nvme_active_ns_ctx_destroy(ctx); 2439 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2440 return; 2441 } 2442 2443 assert(ctx->state == NVME_ACTIVE_NS_STATE_DONE); 2444 2445 RB_FOREACH(ns, nvme_ns_tree, &ctrlr->ns) { 2446 nvme_ns_free_iocs_specific_data(ns); 2447 } 2448 2449 nvme_ctrlr_identify_active_ns_swap(ctrlr, ctx->new_ns_list, ctx->page_count * 1024); 2450 nvme_active_ns_ctx_destroy(ctx); 2451 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS, ctrlr->opts.admin_timeout_ms); 2452 } 2453 2454 static void 2455 _nvme_ctrlr_identify_active_ns(struct spdk_nvme_ctrlr *ctrlr) 2456 { 2457 struct nvme_active_ns_ctx *ctx; 2458 2459 ctx = nvme_active_ns_ctx_create(ctrlr, _nvme_active_ns_ctx_deleter); 2460 if (!ctx) { 2461 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2462 return; 2463 } 2464 2465 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS, 2466 ctrlr->opts.admin_timeout_ms); 2467 nvme_ctrlr_identify_active_ns_async(ctx); 2468 } 2469 2470 int 2471 nvme_ctrlr_identify_active_ns(struct spdk_nvme_ctrlr *ctrlr) 2472 { 2473 struct nvme_active_ns_ctx *ctx; 2474 int rc; 2475 2476 ctx = nvme_active_ns_ctx_create(ctrlr, NULL); 2477 if (!ctx) { 2478 return -ENOMEM; 2479 } 2480 2481 nvme_ctrlr_identify_active_ns_async(ctx); 2482 while (ctx->state == NVME_ACTIVE_NS_STATE_PROCESSING) { 2483 rc = spdk_nvme_qpair_process_completions(ctrlr->adminq, 0); 2484 if (rc < 0) { 2485 ctx->state = NVME_ACTIVE_NS_STATE_ERROR; 2486 break; 2487 } 2488 } 2489 2490 if (ctx->state == NVME_ACTIVE_NS_STATE_ERROR) { 2491 nvme_active_ns_ctx_destroy(ctx); 2492 return -ENXIO; 2493 } 2494 2495 assert(ctx->state == NVME_ACTIVE_NS_STATE_DONE); 2496 nvme_ctrlr_identify_active_ns_swap(ctrlr, ctx->new_ns_list, ctx->page_count * 1024); 2497 nvme_active_ns_ctx_destroy(ctx); 2498 2499 return 0; 2500 } 2501 2502 static void 2503 nvme_ctrlr_identify_ns_async_done(void *arg, const struct spdk_nvme_cpl *cpl) 2504 { 2505 struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg; 2506 struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr; 2507 uint32_t nsid; 2508 int rc; 2509 2510 if (spdk_nvme_cpl_is_error(cpl)) { 2511 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2512 return; 2513 } 2514 2515 nvme_ns_set_identify_data(ns); 2516 2517 /* move on to the next active NS */ 2518 nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id); 2519 ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid); 2520 if (ns == NULL) { 2521 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ID_DESCS, 2522 ctrlr->opts.admin_timeout_ms); 2523 return; 2524 } 2525 ns->ctrlr = ctrlr; 2526 ns->id = nsid; 2527 2528 rc = nvme_ctrlr_identify_ns_async(ns); 2529 if (rc) { 2530 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2531 } 2532 } 2533 2534 static int 2535 nvme_ctrlr_identify_ns_async(struct spdk_nvme_ns *ns) 2536 { 2537 struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr; 2538 struct spdk_nvme_ns_data *nsdata; 2539 2540 nsdata = &ns->nsdata; 2541 2542 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS, 2543 ctrlr->opts.admin_timeout_ms); 2544 return nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS, 0, ns->id, 0, 2545 nsdata, sizeof(*nsdata), 2546 nvme_ctrlr_identify_ns_async_done, ns); 2547 } 2548 2549 static int 2550 nvme_ctrlr_identify_namespaces(struct spdk_nvme_ctrlr *ctrlr) 2551 { 2552 uint32_t nsid; 2553 struct spdk_nvme_ns *ns; 2554 int rc; 2555 2556 nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr); 2557 ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid); 2558 if (ns == NULL) { 2559 /* No active NS, move on to the next state */ 2560 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ID_DESCS, 2561 ctrlr->opts.admin_timeout_ms); 2562 return 0; 2563 } 2564 2565 ns->ctrlr = ctrlr; 2566 ns->id = nsid; 2567 2568 rc = nvme_ctrlr_identify_ns_async(ns); 2569 if (rc) { 2570 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2571 } 2572 2573 return rc; 2574 } 2575 2576 static int 2577 nvme_ctrlr_identify_namespaces_iocs_specific_next(struct spdk_nvme_ctrlr *ctrlr, uint32_t prev_nsid) 2578 { 2579 uint32_t nsid; 2580 struct spdk_nvme_ns *ns; 2581 int rc; 2582 2583 if (!prev_nsid) { 2584 nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr); 2585 } else { 2586 /* move on to the next active NS */ 2587 nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, prev_nsid); 2588 } 2589 2590 ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid); 2591 if (ns == NULL) { 2592 /* No first/next active NS, move on to the next state */ 2593 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES, 2594 ctrlr->opts.admin_timeout_ms); 2595 return 0; 2596 } 2597 2598 /* loop until we find a ns which has (supported) iocs specific data */ 2599 while (!nvme_ns_has_supported_iocs_specific_data(ns)) { 2600 nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id); 2601 ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid); 2602 if (ns == NULL) { 2603 /* no namespace with (supported) iocs specific data found */ 2604 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES, 2605 ctrlr->opts.admin_timeout_ms); 2606 return 0; 2607 } 2608 } 2609 2610 rc = nvme_ctrlr_identify_ns_iocs_specific_async(ns); 2611 if (rc) { 2612 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2613 } 2614 2615 return rc; 2616 } 2617 2618 static void 2619 nvme_ctrlr_identify_ns_zns_specific_async_done(void *arg, const struct spdk_nvme_cpl *cpl) 2620 { 2621 struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg; 2622 struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr; 2623 2624 if (spdk_nvme_cpl_is_error(cpl)) { 2625 nvme_ns_free_zns_specific_data(ns); 2626 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2627 return; 2628 } 2629 2630 nvme_ctrlr_identify_namespaces_iocs_specific_next(ctrlr, ns->id); 2631 } 2632 2633 static int 2634 nvme_ctrlr_identify_ns_iocs_specific_async(struct spdk_nvme_ns *ns) 2635 { 2636 struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr; 2637 int rc; 2638 2639 switch (ns->csi) { 2640 case SPDK_NVME_CSI_ZNS: 2641 break; 2642 default: 2643 /* 2644 * This switch must handle all cases for which 2645 * nvme_ns_has_supported_iocs_specific_data() returns true, 2646 * other cases should never happen. 2647 */ 2648 assert(0); 2649 } 2650 2651 assert(!ns->nsdata_zns); 2652 ns->nsdata_zns = spdk_zmalloc(sizeof(*ns->nsdata_zns), 64, NULL, SPDK_ENV_SOCKET_ID_ANY, 2653 SPDK_MALLOC_SHARE); 2654 if (!ns->nsdata_zns) { 2655 return -ENOMEM; 2656 } 2657 2658 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC, 2659 ctrlr->opts.admin_timeout_ms); 2660 rc = nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS_IOCS, 0, ns->id, ns->csi, 2661 ns->nsdata_zns, sizeof(*ns->nsdata_zns), 2662 nvme_ctrlr_identify_ns_zns_specific_async_done, ns); 2663 if (rc) { 2664 nvme_ns_free_zns_specific_data(ns); 2665 } 2666 2667 return rc; 2668 } 2669 2670 static int 2671 nvme_ctrlr_identify_namespaces_iocs_specific(struct spdk_nvme_ctrlr *ctrlr) 2672 { 2673 if (!nvme_ctrlr_multi_iocs_enabled(ctrlr)) { 2674 /* Multi IOCS not supported/enabled, move on to the next state */ 2675 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES, 2676 ctrlr->opts.admin_timeout_ms); 2677 return 0; 2678 } 2679 2680 return nvme_ctrlr_identify_namespaces_iocs_specific_next(ctrlr, 0); 2681 } 2682 2683 static void 2684 nvme_ctrlr_identify_id_desc_async_done(void *arg, const struct spdk_nvme_cpl *cpl) 2685 { 2686 struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg; 2687 struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr; 2688 uint32_t nsid; 2689 int rc; 2690 2691 if (spdk_nvme_cpl_is_error(cpl)) { 2692 /* 2693 * Many controllers claim to be compatible with NVMe 1.3, however, 2694 * they do not implement NS ID Desc List. Therefore, instead of setting 2695 * the state to NVME_CTRLR_STATE_ERROR, silently ignore the completion 2696 * error and move on to the next state. 2697 * 2698 * The proper way is to create a new quirk for controllers that violate 2699 * the NVMe 1.3 spec by not supporting NS ID Desc List. 2700 * (Re-using the NVME_QUIRK_IDENTIFY_CNS quirk is not possible, since 2701 * it is too generic and was added in order to handle controllers that 2702 * violate the NVMe 1.1 spec by not supporting ACTIVE LIST). 2703 */ 2704 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC, 2705 ctrlr->opts.admin_timeout_ms); 2706 return; 2707 } 2708 2709 nvme_ns_set_id_desc_list_data(ns); 2710 2711 /* move on to the next active NS */ 2712 nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id); 2713 ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid); 2714 if (ns == NULL) { 2715 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC, 2716 ctrlr->opts.admin_timeout_ms); 2717 return; 2718 } 2719 2720 rc = nvme_ctrlr_identify_id_desc_async(ns); 2721 if (rc) { 2722 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2723 } 2724 } 2725 2726 static int 2727 nvme_ctrlr_identify_id_desc_async(struct spdk_nvme_ns *ns) 2728 { 2729 struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr; 2730 2731 memset(ns->id_desc_list, 0, sizeof(ns->id_desc_list)); 2732 2733 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS, 2734 ctrlr->opts.admin_timeout_ms); 2735 return nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS_ID_DESCRIPTOR_LIST, 2736 0, ns->id, 0, ns->id_desc_list, sizeof(ns->id_desc_list), 2737 nvme_ctrlr_identify_id_desc_async_done, ns); 2738 } 2739 2740 static int 2741 nvme_ctrlr_identify_id_desc_namespaces(struct spdk_nvme_ctrlr *ctrlr) 2742 { 2743 uint32_t nsid; 2744 struct spdk_nvme_ns *ns; 2745 int rc; 2746 2747 if ((ctrlr->vs.raw < SPDK_NVME_VERSION(1, 3, 0) && 2748 !(ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS)) || 2749 (ctrlr->quirks & NVME_QUIRK_IDENTIFY_CNS)) { 2750 NVME_CTRLR_DEBUGLOG(ctrlr, "Version < 1.3; not attempting to retrieve NS ID Descriptor List\n"); 2751 /* NS ID Desc List not supported, move on to the next state */ 2752 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC, 2753 ctrlr->opts.admin_timeout_ms); 2754 return 0; 2755 } 2756 2757 nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr); 2758 ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid); 2759 if (ns == NULL) { 2760 /* No active NS, move on to the next state */ 2761 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC, 2762 ctrlr->opts.admin_timeout_ms); 2763 return 0; 2764 } 2765 2766 rc = nvme_ctrlr_identify_id_desc_async(ns); 2767 if (rc) { 2768 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2769 } 2770 2771 return rc; 2772 } 2773 2774 static void 2775 nvme_ctrlr_update_nvmf_ioccsz(struct spdk_nvme_ctrlr *ctrlr) 2776 { 2777 if (spdk_nvme_ctrlr_is_fabrics(ctrlr)) { 2778 if (ctrlr->cdata.nvmf_specific.ioccsz < 4) { 2779 NVME_CTRLR_ERRLOG(ctrlr, "Incorrect IOCCSZ %u, the minimum value should be 4\n", 2780 ctrlr->cdata.nvmf_specific.ioccsz); 2781 ctrlr->cdata.nvmf_specific.ioccsz = 4; 2782 assert(0); 2783 } 2784 ctrlr->ioccsz_bytes = ctrlr->cdata.nvmf_specific.ioccsz * 16 - sizeof(struct spdk_nvme_cmd); 2785 ctrlr->icdoff = ctrlr->cdata.nvmf_specific.icdoff; 2786 } 2787 } 2788 2789 static void 2790 nvme_ctrlr_set_num_queues_done(void *arg, const struct spdk_nvme_cpl *cpl) 2791 { 2792 uint32_t cq_allocated, sq_allocated, min_allocated, i; 2793 struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg; 2794 2795 if (spdk_nvme_cpl_is_error(cpl)) { 2796 NVME_CTRLR_ERRLOG(ctrlr, "Set Features - Number of Queues failed!\n"); 2797 ctrlr->opts.num_io_queues = 0; 2798 } else { 2799 /* 2800 * Data in cdw0 is 0-based. 2801 * Lower 16-bits indicate number of submission queues allocated. 2802 * Upper 16-bits indicate number of completion queues allocated. 2803 */ 2804 sq_allocated = (cpl->cdw0 & 0xFFFF) + 1; 2805 cq_allocated = (cpl->cdw0 >> 16) + 1; 2806 2807 /* 2808 * For 1:1 queue mapping, set number of allocated queues to be minimum of 2809 * submission and completion queues. 2810 */ 2811 min_allocated = spdk_min(sq_allocated, cq_allocated); 2812 2813 /* Set number of queues to be minimum of requested and actually allocated. */ 2814 ctrlr->opts.num_io_queues = spdk_min(min_allocated, ctrlr->opts.num_io_queues); 2815 } 2816 2817 ctrlr->free_io_qids = spdk_bit_array_create(ctrlr->opts.num_io_queues + 1); 2818 if (ctrlr->free_io_qids == NULL) { 2819 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2820 return; 2821 } 2822 2823 /* Initialize list of free I/O queue IDs. QID 0 is the admin queue (implicitly allocated). */ 2824 for (i = 1; i <= ctrlr->opts.num_io_queues; i++) { 2825 spdk_nvme_ctrlr_free_qid(ctrlr, i); 2826 } 2827 2828 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS, 2829 ctrlr->opts.admin_timeout_ms); 2830 } 2831 2832 static int 2833 nvme_ctrlr_set_num_queues(struct spdk_nvme_ctrlr *ctrlr) 2834 { 2835 int rc; 2836 2837 if (ctrlr->opts.num_io_queues > SPDK_NVME_MAX_IO_QUEUES) { 2838 NVME_CTRLR_NOTICELOG(ctrlr, "Limiting requested num_io_queues %u to max %d\n", 2839 ctrlr->opts.num_io_queues, SPDK_NVME_MAX_IO_QUEUES); 2840 ctrlr->opts.num_io_queues = SPDK_NVME_MAX_IO_QUEUES; 2841 } else if (ctrlr->opts.num_io_queues < 1) { 2842 NVME_CTRLR_NOTICELOG(ctrlr, "Requested num_io_queues 0, increasing to 1\n"); 2843 ctrlr->opts.num_io_queues = 1; 2844 } 2845 2846 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES, 2847 ctrlr->opts.admin_timeout_ms); 2848 2849 rc = nvme_ctrlr_cmd_set_num_queues(ctrlr, ctrlr->opts.num_io_queues, 2850 nvme_ctrlr_set_num_queues_done, ctrlr); 2851 if (rc != 0) { 2852 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2853 return rc; 2854 } 2855 2856 return 0; 2857 } 2858 2859 static void 2860 nvme_ctrlr_set_keep_alive_timeout_done(void *arg, const struct spdk_nvme_cpl *cpl) 2861 { 2862 uint32_t keep_alive_interval_us; 2863 struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg; 2864 2865 if (spdk_nvme_cpl_is_error(cpl)) { 2866 if ((cpl->status.sct == SPDK_NVME_SCT_GENERIC) && 2867 (cpl->status.sc == SPDK_NVME_SC_INVALID_FIELD)) { 2868 NVME_CTRLR_DEBUGLOG(ctrlr, "Keep alive timeout Get Feature is not supported\n"); 2869 } else { 2870 NVME_CTRLR_ERRLOG(ctrlr, "Keep alive timeout Get Feature failed: SC %x SCT %x\n", 2871 cpl->status.sc, cpl->status.sct); 2872 ctrlr->opts.keep_alive_timeout_ms = 0; 2873 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2874 return; 2875 } 2876 } else { 2877 if (ctrlr->opts.keep_alive_timeout_ms != cpl->cdw0) { 2878 NVME_CTRLR_DEBUGLOG(ctrlr, "Controller adjusted keep alive timeout to %u ms\n", 2879 cpl->cdw0); 2880 } 2881 2882 ctrlr->opts.keep_alive_timeout_ms = cpl->cdw0; 2883 } 2884 2885 if (ctrlr->opts.keep_alive_timeout_ms == 0) { 2886 ctrlr->keep_alive_interval_ticks = 0; 2887 } else { 2888 keep_alive_interval_us = ctrlr->opts.keep_alive_timeout_ms * 1000 / 2; 2889 2890 NVME_CTRLR_DEBUGLOG(ctrlr, "Sending keep alive every %u us\n", keep_alive_interval_us); 2891 2892 ctrlr->keep_alive_interval_ticks = (keep_alive_interval_us * spdk_get_ticks_hz()) / 2893 UINT64_C(1000000); 2894 2895 /* Schedule the first Keep Alive to be sent as soon as possible. */ 2896 ctrlr->next_keep_alive_tick = spdk_get_ticks(); 2897 } 2898 2899 if (spdk_nvme_ctrlr_is_discovery(ctrlr)) { 2900 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE); 2901 } else { 2902 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC, 2903 ctrlr->opts.admin_timeout_ms); 2904 } 2905 } 2906 2907 static int 2908 nvme_ctrlr_set_keep_alive_timeout(struct spdk_nvme_ctrlr *ctrlr) 2909 { 2910 int rc; 2911 2912 if (ctrlr->opts.keep_alive_timeout_ms == 0) { 2913 if (spdk_nvme_ctrlr_is_discovery(ctrlr)) { 2914 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE); 2915 } else { 2916 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC, 2917 ctrlr->opts.admin_timeout_ms); 2918 } 2919 return 0; 2920 } 2921 2922 /* Note: Discovery controller identify data does not populate KAS according to spec. */ 2923 if (!spdk_nvme_ctrlr_is_discovery(ctrlr) && ctrlr->cdata.kas == 0) { 2924 NVME_CTRLR_DEBUGLOG(ctrlr, "Controller KAS is 0 - not enabling Keep Alive\n"); 2925 ctrlr->opts.keep_alive_timeout_ms = 0; 2926 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC, 2927 ctrlr->opts.admin_timeout_ms); 2928 return 0; 2929 } 2930 2931 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT, 2932 ctrlr->opts.admin_timeout_ms); 2933 2934 /* Retrieve actual keep alive timeout, since the controller may have adjusted it. */ 2935 rc = spdk_nvme_ctrlr_cmd_get_feature(ctrlr, SPDK_NVME_FEAT_KEEP_ALIVE_TIMER, 0, NULL, 0, 2936 nvme_ctrlr_set_keep_alive_timeout_done, ctrlr); 2937 if (rc != 0) { 2938 NVME_CTRLR_ERRLOG(ctrlr, "Keep alive timeout Get Feature failed: %d\n", rc); 2939 ctrlr->opts.keep_alive_timeout_ms = 0; 2940 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2941 return rc; 2942 } 2943 2944 return 0; 2945 } 2946 2947 static void 2948 nvme_ctrlr_set_host_id_done(void *arg, const struct spdk_nvme_cpl *cpl) 2949 { 2950 struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg; 2951 2952 if (spdk_nvme_cpl_is_error(cpl)) { 2953 /* 2954 * Treat Set Features - Host ID failure as non-fatal, since the Host ID feature 2955 * is optional. 2956 */ 2957 NVME_CTRLR_WARNLOG(ctrlr, "Set Features - Host ID failed: SC 0x%x SCT 0x%x\n", 2958 cpl->status.sc, cpl->status.sct); 2959 } else { 2960 NVME_CTRLR_DEBUGLOG(ctrlr, "Set Features - Host ID was successful\n"); 2961 } 2962 2963 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_TRANSPORT_READY, ctrlr->opts.admin_timeout_ms); 2964 } 2965 2966 static int 2967 nvme_ctrlr_set_host_id(struct spdk_nvme_ctrlr *ctrlr) 2968 { 2969 uint8_t *host_id; 2970 uint32_t host_id_size; 2971 int rc; 2972 2973 if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) { 2974 /* 2975 * NVMe-oF sends the host ID during Connect and doesn't allow 2976 * Set Features - Host Identifier after Connect, so we don't need to do anything here. 2977 */ 2978 NVME_CTRLR_DEBUGLOG(ctrlr, "NVMe-oF transport - not sending Set Features - Host ID\n"); 2979 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_TRANSPORT_READY, ctrlr->opts.admin_timeout_ms); 2980 return 0; 2981 } 2982 2983 if (ctrlr->cdata.ctratt.host_id_exhid_supported) { 2984 NVME_CTRLR_DEBUGLOG(ctrlr, "Using 128-bit extended host identifier\n"); 2985 host_id = ctrlr->opts.extended_host_id; 2986 host_id_size = sizeof(ctrlr->opts.extended_host_id); 2987 } else { 2988 NVME_CTRLR_DEBUGLOG(ctrlr, "Using 64-bit host identifier\n"); 2989 host_id = ctrlr->opts.host_id; 2990 host_id_size = sizeof(ctrlr->opts.host_id); 2991 } 2992 2993 /* If the user specified an all-zeroes host identifier, don't send the command. */ 2994 if (spdk_mem_all_zero(host_id, host_id_size)) { 2995 NVME_CTRLR_DEBUGLOG(ctrlr, "User did not specify host ID - not sending Set Features - Host ID\n"); 2996 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_TRANSPORT_READY, ctrlr->opts.admin_timeout_ms); 2997 return 0; 2998 } 2999 3000 SPDK_LOGDUMP(nvme, "host_id", host_id, host_id_size); 3001 3002 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_HOST_ID, 3003 ctrlr->opts.admin_timeout_ms); 3004 3005 rc = nvme_ctrlr_cmd_set_host_id(ctrlr, host_id, host_id_size, nvme_ctrlr_set_host_id_done, ctrlr); 3006 if (rc != 0) { 3007 NVME_CTRLR_ERRLOG(ctrlr, "Set Features - Host ID failed: %d\n", rc); 3008 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3009 return rc; 3010 } 3011 3012 return 0; 3013 } 3014 3015 void 3016 nvme_ctrlr_update_namespaces(struct spdk_nvme_ctrlr *ctrlr) 3017 { 3018 uint32_t nsid; 3019 struct spdk_nvme_ns *ns; 3020 3021 for (nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr); 3022 nsid != 0; nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, nsid)) { 3023 ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid); 3024 nvme_ns_construct(ns, nsid, ctrlr); 3025 } 3026 } 3027 3028 static int 3029 nvme_ctrlr_clear_changed_ns_log(struct spdk_nvme_ctrlr *ctrlr) 3030 { 3031 struct nvme_completion_poll_status *status; 3032 int rc = -ENOMEM; 3033 char *buffer = NULL; 3034 uint32_t nsid; 3035 size_t buf_size = (SPDK_NVME_MAX_CHANGED_NAMESPACES * sizeof(uint32_t)); 3036 3037 if (ctrlr->opts.disable_read_changed_ns_list_log_page) { 3038 return 0; 3039 } 3040 3041 buffer = spdk_dma_zmalloc(buf_size, 4096, NULL); 3042 if (!buffer) { 3043 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate buffer for getting " 3044 "changed ns log.\n"); 3045 return rc; 3046 } 3047 3048 status = calloc(1, sizeof(*status)); 3049 if (!status) { 3050 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n"); 3051 goto free_buffer; 3052 } 3053 3054 rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr, 3055 SPDK_NVME_LOG_CHANGED_NS_LIST, 3056 SPDK_NVME_GLOBAL_NS_TAG, 3057 buffer, buf_size, 0, 3058 nvme_completion_poll_cb, status); 3059 3060 if (rc) { 3061 NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_cmd_get_log_page() failed: rc=%d\n", rc); 3062 free(status); 3063 goto free_buffer; 3064 } 3065 3066 rc = nvme_wait_for_completion_timeout(ctrlr->adminq, status, 3067 ctrlr->opts.admin_timeout_ms * 1000); 3068 if (!status->timed_out) { 3069 free(status); 3070 } 3071 3072 if (rc) { 3073 NVME_CTRLR_ERRLOG(ctrlr, "wait for spdk_nvme_ctrlr_cmd_get_log_page failed: rc=%d\n", rc); 3074 goto free_buffer; 3075 } 3076 3077 /* only check the case of overflow. */ 3078 nsid = from_le32(buffer); 3079 if (nsid == 0xffffffffu) { 3080 NVME_CTRLR_WARNLOG(ctrlr, "changed ns log overflowed.\n"); 3081 } 3082 3083 free_buffer: 3084 spdk_dma_free(buffer); 3085 return rc; 3086 } 3087 3088 void 3089 nvme_ctrlr_process_async_event(struct spdk_nvme_ctrlr *ctrlr, 3090 const struct spdk_nvme_cpl *cpl) 3091 { 3092 union spdk_nvme_async_event_completion event; 3093 struct spdk_nvme_ctrlr_process *active_proc; 3094 int rc; 3095 3096 event.raw = cpl->cdw0; 3097 3098 if ((event.bits.async_event_type == SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE) && 3099 (event.bits.async_event_info == SPDK_NVME_ASYNC_EVENT_NS_ATTR_CHANGED)) { 3100 nvme_ctrlr_clear_changed_ns_log(ctrlr); 3101 3102 rc = nvme_ctrlr_identify_active_ns(ctrlr); 3103 if (rc) { 3104 return; 3105 } 3106 nvme_ctrlr_update_namespaces(ctrlr); 3107 nvme_io_msg_ctrlr_update(ctrlr); 3108 } 3109 3110 if ((event.bits.async_event_type == SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE) && 3111 (event.bits.async_event_info == SPDK_NVME_ASYNC_EVENT_ANA_CHANGE)) { 3112 if (!ctrlr->opts.disable_read_ana_log_page) { 3113 rc = nvme_ctrlr_update_ana_log_page(ctrlr); 3114 if (rc) { 3115 return; 3116 } 3117 nvme_ctrlr_parse_ana_log_page(ctrlr, nvme_ctrlr_update_ns_ana_states, 3118 ctrlr); 3119 } 3120 } 3121 3122 active_proc = nvme_ctrlr_get_current_process(ctrlr); 3123 if (active_proc && active_proc->aer_cb_fn) { 3124 active_proc->aer_cb_fn(active_proc->aer_cb_arg, cpl); 3125 } 3126 } 3127 3128 static void 3129 nvme_ctrlr_queue_async_event(struct spdk_nvme_ctrlr *ctrlr, 3130 const struct spdk_nvme_cpl *cpl) 3131 { 3132 struct spdk_nvme_ctrlr_aer_completion_list *nvme_event; 3133 struct spdk_nvme_ctrlr_process *proc; 3134 3135 /* Add async event to each process objects event list */ 3136 TAILQ_FOREACH(proc, &ctrlr->active_procs, tailq) { 3137 /* Must be shared memory so other processes can access */ 3138 nvme_event = spdk_zmalloc(sizeof(*nvme_event), 0, NULL, SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE); 3139 if (!nvme_event) { 3140 NVME_CTRLR_ERRLOG(ctrlr, "Alloc nvme event failed, ignore the event\n"); 3141 return; 3142 } 3143 nvme_event->cpl = *cpl; 3144 3145 STAILQ_INSERT_TAIL(&proc->async_events, nvme_event, link); 3146 } 3147 } 3148 3149 void 3150 nvme_ctrlr_complete_queued_async_events(struct spdk_nvme_ctrlr *ctrlr) 3151 { 3152 struct spdk_nvme_ctrlr_aer_completion_list *nvme_event, *nvme_event_tmp; 3153 struct spdk_nvme_ctrlr_process *active_proc; 3154 3155 active_proc = nvme_ctrlr_get_current_process(ctrlr); 3156 3157 STAILQ_FOREACH_SAFE(nvme_event, &active_proc->async_events, link, nvme_event_tmp) { 3158 STAILQ_REMOVE(&active_proc->async_events, nvme_event, 3159 spdk_nvme_ctrlr_aer_completion_list, link); 3160 nvme_ctrlr_process_async_event(ctrlr, &nvme_event->cpl); 3161 spdk_free(nvme_event); 3162 3163 } 3164 } 3165 3166 static void 3167 nvme_ctrlr_async_event_cb(void *arg, const struct spdk_nvme_cpl *cpl) 3168 { 3169 struct nvme_async_event_request *aer = arg; 3170 struct spdk_nvme_ctrlr *ctrlr = aer->ctrlr; 3171 3172 if (cpl->status.sct == SPDK_NVME_SCT_GENERIC && 3173 cpl->status.sc == SPDK_NVME_SC_ABORTED_SQ_DELETION) { 3174 /* 3175 * This is simulated when controller is being shut down, to 3176 * effectively abort outstanding asynchronous event requests 3177 * and make sure all memory is freed. Do not repost the 3178 * request in this case. 3179 */ 3180 return; 3181 } 3182 3183 if (cpl->status.sct == SPDK_NVME_SCT_COMMAND_SPECIFIC && 3184 cpl->status.sc == SPDK_NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED) { 3185 /* 3186 * SPDK will only send as many AERs as the device says it supports, 3187 * so this status code indicates an out-of-spec device. Do not repost 3188 * the request in this case. 3189 */ 3190 NVME_CTRLR_ERRLOG(ctrlr, "Controller appears out-of-spec for asynchronous event request\n" 3191 "handling. Do not repost this AER.\n"); 3192 return; 3193 } 3194 3195 /* Add the events to the list */ 3196 nvme_ctrlr_queue_async_event(ctrlr, cpl); 3197 3198 /* If the ctrlr was removed or in the destruct state, we should not send aer again */ 3199 if (ctrlr->is_removed || ctrlr->is_destructed) { 3200 return; 3201 } 3202 3203 /* 3204 * Repost another asynchronous event request to replace the one 3205 * that just completed. 3206 */ 3207 if (nvme_ctrlr_construct_and_submit_aer(ctrlr, aer)) { 3208 /* 3209 * We can't do anything to recover from a failure here, 3210 * so just print a warning message and leave the AER unsubmitted. 3211 */ 3212 NVME_CTRLR_ERRLOG(ctrlr, "resubmitting AER failed!\n"); 3213 } 3214 } 3215 3216 static int 3217 nvme_ctrlr_construct_and_submit_aer(struct spdk_nvme_ctrlr *ctrlr, 3218 struct nvme_async_event_request *aer) 3219 { 3220 struct nvme_request *req; 3221 3222 aer->ctrlr = ctrlr; 3223 req = nvme_allocate_request_null(ctrlr->adminq, nvme_ctrlr_async_event_cb, aer); 3224 aer->req = req; 3225 if (req == NULL) { 3226 return -1; 3227 } 3228 3229 req->cmd.opc = SPDK_NVME_OPC_ASYNC_EVENT_REQUEST; 3230 return nvme_ctrlr_submit_admin_request(ctrlr, req); 3231 } 3232 3233 static void 3234 nvme_ctrlr_configure_aer_done(void *arg, const struct spdk_nvme_cpl *cpl) 3235 { 3236 struct nvme_async_event_request *aer; 3237 int rc; 3238 uint32_t i; 3239 struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg; 3240 3241 if (spdk_nvme_cpl_is_error(cpl)) { 3242 NVME_CTRLR_NOTICELOG(ctrlr, "nvme_ctrlr_configure_aer failed!\n"); 3243 ctrlr->num_aers = 0; 3244 } else { 3245 /* aerl is a zero-based value, so we need to add 1 here. */ 3246 ctrlr->num_aers = spdk_min(NVME_MAX_ASYNC_EVENTS, (ctrlr->cdata.aerl + 1)); 3247 } 3248 3249 for (i = 0; i < ctrlr->num_aers; i++) { 3250 aer = &ctrlr->aer[i]; 3251 rc = nvme_ctrlr_construct_and_submit_aer(ctrlr, aer); 3252 if (rc) { 3253 NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_construct_and_submit_aer failed!\n"); 3254 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3255 return; 3256 } 3257 } 3258 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT, ctrlr->opts.admin_timeout_ms); 3259 } 3260 3261 static int 3262 nvme_ctrlr_configure_aer(struct spdk_nvme_ctrlr *ctrlr) 3263 { 3264 union spdk_nvme_feat_async_event_configuration config; 3265 int rc; 3266 3267 config.raw = 0; 3268 3269 if (spdk_nvme_ctrlr_is_discovery(ctrlr)) { 3270 config.bits.discovery_log_change_notice = 1; 3271 } else { 3272 config.bits.crit_warn.bits.available_spare = 1; 3273 config.bits.crit_warn.bits.temperature = 1; 3274 config.bits.crit_warn.bits.device_reliability = 1; 3275 config.bits.crit_warn.bits.read_only = 1; 3276 config.bits.crit_warn.bits.volatile_memory_backup = 1; 3277 3278 if (ctrlr->vs.raw >= SPDK_NVME_VERSION(1, 2, 0)) { 3279 if (ctrlr->cdata.oaes.ns_attribute_notices) { 3280 config.bits.ns_attr_notice = 1; 3281 } 3282 if (ctrlr->cdata.oaes.fw_activation_notices) { 3283 config.bits.fw_activation_notice = 1; 3284 } 3285 if (ctrlr->cdata.oaes.ana_change_notices) { 3286 config.bits.ana_change_notice = 1; 3287 } 3288 } 3289 if (ctrlr->vs.raw >= SPDK_NVME_VERSION(1, 3, 0) && ctrlr->cdata.lpa.telemetry) { 3290 config.bits.telemetry_log_notice = 1; 3291 } 3292 } 3293 3294 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER, 3295 ctrlr->opts.admin_timeout_ms); 3296 3297 rc = nvme_ctrlr_cmd_set_async_event_config(ctrlr, config, 3298 nvme_ctrlr_configure_aer_done, 3299 ctrlr); 3300 if (rc != 0) { 3301 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3302 return rc; 3303 } 3304 3305 return 0; 3306 } 3307 3308 struct spdk_nvme_ctrlr_process * 3309 nvme_ctrlr_get_process(struct spdk_nvme_ctrlr *ctrlr, pid_t pid) 3310 { 3311 struct spdk_nvme_ctrlr_process *active_proc; 3312 3313 TAILQ_FOREACH(active_proc, &ctrlr->active_procs, tailq) { 3314 if (active_proc->pid == pid) { 3315 return active_proc; 3316 } 3317 } 3318 3319 return NULL; 3320 } 3321 3322 struct spdk_nvme_ctrlr_process * 3323 nvme_ctrlr_get_current_process(struct spdk_nvme_ctrlr *ctrlr) 3324 { 3325 return nvme_ctrlr_get_process(ctrlr, getpid()); 3326 } 3327 3328 /** 3329 * This function will be called when a process is using the controller. 3330 * 1. For the primary process, it is called when constructing the controller. 3331 * 2. For the secondary process, it is called at probing the controller. 3332 * Note: will check whether the process is already added for the same process. 3333 */ 3334 int 3335 nvme_ctrlr_add_process(struct spdk_nvme_ctrlr *ctrlr, void *devhandle) 3336 { 3337 struct spdk_nvme_ctrlr_process *ctrlr_proc; 3338 pid_t pid = getpid(); 3339 3340 /* Check whether the process is already added or not */ 3341 if (nvme_ctrlr_get_process(ctrlr, pid)) { 3342 return 0; 3343 } 3344 3345 /* Initialize the per process properties for this ctrlr */ 3346 ctrlr_proc = spdk_zmalloc(sizeof(struct spdk_nvme_ctrlr_process), 3347 64, NULL, SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE); 3348 if (ctrlr_proc == NULL) { 3349 NVME_CTRLR_ERRLOG(ctrlr, "failed to allocate memory to track the process props\n"); 3350 3351 return -1; 3352 } 3353 3354 ctrlr_proc->is_primary = spdk_process_is_primary(); 3355 ctrlr_proc->pid = pid; 3356 STAILQ_INIT(&ctrlr_proc->active_reqs); 3357 ctrlr_proc->devhandle = devhandle; 3358 ctrlr_proc->ref = 0; 3359 TAILQ_INIT(&ctrlr_proc->allocated_io_qpairs); 3360 STAILQ_INIT(&ctrlr_proc->async_events); 3361 3362 TAILQ_INSERT_TAIL(&ctrlr->active_procs, ctrlr_proc, tailq); 3363 3364 return 0; 3365 } 3366 3367 /** 3368 * This function will be called when the process detaches the controller. 3369 * Note: the ctrlr_lock must be held when calling this function. 3370 */ 3371 static void 3372 nvme_ctrlr_remove_process(struct spdk_nvme_ctrlr *ctrlr, 3373 struct spdk_nvme_ctrlr_process *proc) 3374 { 3375 struct spdk_nvme_qpair *qpair, *tmp_qpair; 3376 3377 assert(STAILQ_EMPTY(&proc->active_reqs)); 3378 3379 TAILQ_FOREACH_SAFE(qpair, &proc->allocated_io_qpairs, per_process_tailq, tmp_qpair) { 3380 spdk_nvme_ctrlr_free_io_qpair(qpair); 3381 } 3382 3383 TAILQ_REMOVE(&ctrlr->active_procs, proc, tailq); 3384 3385 if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) { 3386 spdk_pci_device_detach(proc->devhandle); 3387 } 3388 3389 spdk_free(proc); 3390 } 3391 3392 /** 3393 * This function will be called when the process exited unexpectedly 3394 * in order to free any incomplete nvme request, allocated IO qpairs 3395 * and allocated memory. 3396 * Note: the ctrlr_lock must be held when calling this function. 3397 */ 3398 static void 3399 nvme_ctrlr_cleanup_process(struct spdk_nvme_ctrlr_process *proc) 3400 { 3401 struct nvme_request *req, *tmp_req; 3402 struct spdk_nvme_qpair *qpair, *tmp_qpair; 3403 struct spdk_nvme_ctrlr_aer_completion_list *event; 3404 3405 STAILQ_FOREACH_SAFE(req, &proc->active_reqs, stailq, tmp_req) { 3406 STAILQ_REMOVE(&proc->active_reqs, req, nvme_request, stailq); 3407 3408 assert(req->pid == proc->pid); 3409 nvme_cleanup_user_req(req); 3410 nvme_free_request(req); 3411 } 3412 3413 /* Remove async event from each process objects event list */ 3414 while (!STAILQ_EMPTY(&proc->async_events)) { 3415 event = STAILQ_FIRST(&proc->async_events); 3416 STAILQ_REMOVE_HEAD(&proc->async_events, link); 3417 spdk_free(event); 3418 } 3419 3420 TAILQ_FOREACH_SAFE(qpair, &proc->allocated_io_qpairs, per_process_tailq, tmp_qpair) { 3421 TAILQ_REMOVE(&proc->allocated_io_qpairs, qpair, per_process_tailq); 3422 3423 /* 3424 * The process may have been killed while some qpairs were in their 3425 * completion context. Clear that flag here to allow these IO 3426 * qpairs to be deleted. 3427 */ 3428 qpair->in_completion_context = 0; 3429 3430 qpair->no_deletion_notification_needed = 1; 3431 3432 spdk_nvme_ctrlr_free_io_qpair(qpair); 3433 } 3434 3435 spdk_free(proc); 3436 } 3437 3438 /** 3439 * This function will be called when destructing the controller. 3440 * 1. There is no more admin request on this controller. 3441 * 2. Clean up any left resource allocation when its associated process is gone. 3442 */ 3443 void 3444 nvme_ctrlr_free_processes(struct spdk_nvme_ctrlr *ctrlr) 3445 { 3446 struct spdk_nvme_ctrlr_process *active_proc, *tmp; 3447 3448 /* Free all the processes' properties and make sure no pending admin IOs */ 3449 TAILQ_FOREACH_SAFE(active_proc, &ctrlr->active_procs, tailq, tmp) { 3450 TAILQ_REMOVE(&ctrlr->active_procs, active_proc, tailq); 3451 3452 assert(STAILQ_EMPTY(&active_proc->active_reqs)); 3453 3454 spdk_free(active_proc); 3455 } 3456 } 3457 3458 /** 3459 * This function will be called when any other process attaches or 3460 * detaches the controller in order to cleanup those unexpectedly 3461 * terminated processes. 3462 * Note: the ctrlr_lock must be held when calling this function. 3463 */ 3464 static int 3465 nvme_ctrlr_remove_inactive_proc(struct spdk_nvme_ctrlr *ctrlr) 3466 { 3467 struct spdk_nvme_ctrlr_process *active_proc, *tmp; 3468 int active_proc_count = 0; 3469 3470 TAILQ_FOREACH_SAFE(active_proc, &ctrlr->active_procs, tailq, tmp) { 3471 if ((kill(active_proc->pid, 0) == -1) && (errno == ESRCH)) { 3472 NVME_CTRLR_ERRLOG(ctrlr, "process %d terminated unexpected\n", active_proc->pid); 3473 3474 TAILQ_REMOVE(&ctrlr->active_procs, active_proc, tailq); 3475 3476 nvme_ctrlr_cleanup_process(active_proc); 3477 } else { 3478 active_proc_count++; 3479 } 3480 } 3481 3482 return active_proc_count; 3483 } 3484 3485 void 3486 nvme_ctrlr_proc_get_ref(struct spdk_nvme_ctrlr *ctrlr) 3487 { 3488 struct spdk_nvme_ctrlr_process *active_proc; 3489 3490 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 3491 3492 nvme_ctrlr_remove_inactive_proc(ctrlr); 3493 3494 active_proc = nvme_ctrlr_get_current_process(ctrlr); 3495 if (active_proc) { 3496 active_proc->ref++; 3497 } 3498 3499 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 3500 } 3501 3502 void 3503 nvme_ctrlr_proc_put_ref(struct spdk_nvme_ctrlr *ctrlr) 3504 { 3505 struct spdk_nvme_ctrlr_process *active_proc; 3506 int proc_count; 3507 3508 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 3509 3510 proc_count = nvme_ctrlr_remove_inactive_proc(ctrlr); 3511 3512 active_proc = nvme_ctrlr_get_current_process(ctrlr); 3513 if (active_proc) { 3514 active_proc->ref--; 3515 assert(active_proc->ref >= 0); 3516 3517 /* 3518 * The last active process will be removed at the end of 3519 * the destruction of the controller. 3520 */ 3521 if (active_proc->ref == 0 && proc_count != 1) { 3522 nvme_ctrlr_remove_process(ctrlr, active_proc); 3523 } 3524 } 3525 3526 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 3527 } 3528 3529 int 3530 nvme_ctrlr_get_ref_count(struct spdk_nvme_ctrlr *ctrlr) 3531 { 3532 struct spdk_nvme_ctrlr_process *active_proc; 3533 int ref = 0; 3534 3535 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 3536 3537 nvme_ctrlr_remove_inactive_proc(ctrlr); 3538 3539 TAILQ_FOREACH(active_proc, &ctrlr->active_procs, tailq) { 3540 ref += active_proc->ref; 3541 } 3542 3543 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 3544 3545 return ref; 3546 } 3547 3548 /** 3549 * Get the PCI device handle which is only visible to its associated process. 3550 */ 3551 struct spdk_pci_device * 3552 nvme_ctrlr_proc_get_devhandle(struct spdk_nvme_ctrlr *ctrlr) 3553 { 3554 struct spdk_nvme_ctrlr_process *active_proc; 3555 struct spdk_pci_device *devhandle = NULL; 3556 3557 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 3558 3559 active_proc = nvme_ctrlr_get_current_process(ctrlr); 3560 if (active_proc) { 3561 devhandle = active_proc->devhandle; 3562 } 3563 3564 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 3565 3566 return devhandle; 3567 } 3568 3569 static void 3570 nvme_ctrlr_process_init_vs_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl) 3571 { 3572 struct spdk_nvme_ctrlr *ctrlr = ctx; 3573 3574 if (spdk_nvme_cpl_is_error(cpl)) { 3575 NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the VS register\n"); 3576 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3577 return; 3578 } 3579 3580 assert(value <= UINT32_MAX); 3581 ctrlr->vs.raw = (uint32_t)value; 3582 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_CAP, NVME_TIMEOUT_INFINITE); 3583 } 3584 3585 static void 3586 nvme_ctrlr_process_init_cap_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl) 3587 { 3588 struct spdk_nvme_ctrlr *ctrlr = ctx; 3589 3590 if (spdk_nvme_cpl_is_error(cpl)) { 3591 NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CAP register\n"); 3592 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3593 return; 3594 } 3595 3596 ctrlr->cap.raw = value; 3597 nvme_ctrlr_init_cap(ctrlr); 3598 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN, NVME_TIMEOUT_INFINITE); 3599 } 3600 3601 static void 3602 nvme_ctrlr_process_init_check_en(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl) 3603 { 3604 struct spdk_nvme_ctrlr *ctrlr = ctx; 3605 enum nvme_ctrlr_state state; 3606 3607 if (spdk_nvme_cpl_is_error(cpl)) { 3608 NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n"); 3609 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3610 return; 3611 } 3612 3613 assert(value <= UINT32_MAX); 3614 ctrlr->process_init_cc.raw = (uint32_t)value; 3615 3616 if (ctrlr->process_init_cc.bits.en) { 3617 NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1\n"); 3618 state = NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1; 3619 } else { 3620 state = NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0; 3621 } 3622 3623 nvme_ctrlr_set_state(ctrlr, state, nvme_ctrlr_get_ready_timeout(ctrlr)); 3624 } 3625 3626 static void 3627 nvme_ctrlr_process_init_set_en_0(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl) 3628 { 3629 struct spdk_nvme_ctrlr *ctrlr = ctx; 3630 3631 if (spdk_nvme_cpl_is_error(cpl)) { 3632 NVME_CTRLR_ERRLOG(ctrlr, "Failed to write the CC register\n"); 3633 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3634 return; 3635 } 3636 3637 /* 3638 * Wait 2.5 seconds before accessing PCI registers. 3639 * Not using sleep() to avoid blocking other controller's initialization. 3640 */ 3641 if (ctrlr->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY) { 3642 NVME_CTRLR_DEBUGLOG(ctrlr, "Applying quirk: delay 2.5 seconds before reading registers\n"); 3643 ctrlr->sleep_timeout_tsc = spdk_get_ticks() + (2500 * spdk_get_ticks_hz() / 1000); 3644 } 3645 3646 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0, 3647 nvme_ctrlr_get_ready_timeout(ctrlr)); 3648 } 3649 3650 static void 3651 nvme_ctrlr_process_init_set_en_0_read_cc(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl) 3652 { 3653 struct spdk_nvme_ctrlr *ctrlr = ctx; 3654 union spdk_nvme_cc_register cc; 3655 int rc; 3656 3657 if (spdk_nvme_cpl_is_error(cpl)) { 3658 NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n"); 3659 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3660 return; 3661 } 3662 3663 assert(value <= UINT32_MAX); 3664 cc.raw = (uint32_t)value; 3665 cc.bits.en = 0; 3666 ctrlr->process_init_cc.raw = cc.raw; 3667 3668 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC, 3669 nvme_ctrlr_get_ready_timeout(ctrlr)); 3670 3671 rc = nvme_ctrlr_set_cc_async(ctrlr, cc.raw, nvme_ctrlr_process_init_set_en_0, ctrlr); 3672 if (rc != 0) { 3673 NVME_CTRLR_ERRLOG(ctrlr, "set_cc() failed\n"); 3674 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3675 } 3676 } 3677 3678 static void 3679 nvme_ctrlr_process_init_wait_for_ready_1(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl) 3680 { 3681 struct spdk_nvme_ctrlr *ctrlr = ctx; 3682 union spdk_nvme_csts_register csts; 3683 3684 if (spdk_nvme_cpl_is_error(cpl)) { 3685 /* While a device is resetting, it may be unable to service MMIO reads 3686 * temporarily. Allow for this case. 3687 */ 3688 if (!ctrlr->is_failed && ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE) { 3689 NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to read the CSTS register\n"); 3690 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1, 3691 NVME_TIMEOUT_KEEP_EXISTING); 3692 } else { 3693 NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n"); 3694 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3695 } 3696 3697 return; 3698 } 3699 3700 assert(value <= UINT32_MAX); 3701 csts.raw = (uint32_t)value; 3702 if (csts.bits.rdy == 1 || csts.bits.cfs == 1) { 3703 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_EN_0, 3704 nvme_ctrlr_get_ready_timeout(ctrlr)); 3705 } else { 3706 NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1 && CSTS.RDY = 0 - waiting for reset to complete\n"); 3707 nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1, 3708 NVME_TIMEOUT_KEEP_EXISTING); 3709 } 3710 } 3711 3712 static void 3713 nvme_ctrlr_process_init_wait_for_ready_0(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl) 3714 { 3715 struct spdk_nvme_ctrlr *ctrlr = ctx; 3716 union spdk_nvme_csts_register csts; 3717 3718 if (spdk_nvme_cpl_is_error(cpl)) { 3719 /* While a device is resetting, it may be unable to service MMIO reads 3720 * temporarily. Allow for this case. 3721 */ 3722 if (!ctrlr->is_failed && ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE) { 3723 NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to read the CSTS register\n"); 3724 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0, 3725 NVME_TIMEOUT_KEEP_EXISTING); 3726 } else { 3727 NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n"); 3728 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3729 } 3730 3731 return; 3732 } 3733 3734 assert(value <= UINT32_MAX); 3735 csts.raw = (uint32_t)value; 3736 if (csts.bits.rdy == 0) { 3737 NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 0 && CSTS.RDY = 0\n"); 3738 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLED, 3739 nvme_ctrlr_get_ready_timeout(ctrlr)); 3740 } else { 3741 nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0, 3742 NVME_TIMEOUT_KEEP_EXISTING); 3743 } 3744 } 3745 3746 static void 3747 nvme_ctrlr_process_init_enable_wait_for_ready_1(void *ctx, uint64_t value, 3748 const struct spdk_nvme_cpl *cpl) 3749 { 3750 struct spdk_nvme_ctrlr *ctrlr = ctx; 3751 union spdk_nvme_csts_register csts; 3752 3753 if (spdk_nvme_cpl_is_error(cpl)) { 3754 /* While a device is resetting, it may be unable to service MMIO reads 3755 * temporarily. Allow for this case. 3756 */ 3757 if (!ctrlr->is_failed && ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE) { 3758 NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to read the CSTS register\n"); 3759 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1, 3760 NVME_TIMEOUT_KEEP_EXISTING); 3761 } else { 3762 NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n"); 3763 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3764 } 3765 3766 return; 3767 } 3768 3769 assert(value <= UINT32_MAX); 3770 csts.raw = value; 3771 if (csts.bits.rdy == 1) { 3772 NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1 && CSTS.RDY = 1 - controller is ready\n"); 3773 /* 3774 * The controller has been enabled. 3775 * Perform the rest of initialization serially. 3776 */ 3777 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_RESET_ADMIN_QUEUE, 3778 ctrlr->opts.admin_timeout_ms); 3779 } else { 3780 nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1, 3781 NVME_TIMEOUT_KEEP_EXISTING); 3782 } 3783 } 3784 3785 /** 3786 * This function will be called repeatedly during initialization until the controller is ready. 3787 */ 3788 int 3789 nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr) 3790 { 3791 uint32_t ready_timeout_in_ms; 3792 uint64_t ticks; 3793 int rc = 0; 3794 3795 ticks = spdk_get_ticks(); 3796 3797 /* 3798 * May need to avoid accessing any register on the target controller 3799 * for a while. Return early without touching the FSM. 3800 * Check sleep_timeout_tsc > 0 for unit test. 3801 */ 3802 if ((ctrlr->sleep_timeout_tsc > 0) && 3803 (ticks <= ctrlr->sleep_timeout_tsc)) { 3804 return 0; 3805 } 3806 ctrlr->sleep_timeout_tsc = 0; 3807 3808 ready_timeout_in_ms = nvme_ctrlr_get_ready_timeout(ctrlr); 3809 3810 /* 3811 * Check if the current initialization step is done or has timed out. 3812 */ 3813 switch (ctrlr->state) { 3814 case NVME_CTRLR_STATE_INIT_DELAY: 3815 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, ready_timeout_in_ms); 3816 if (ctrlr->quirks & NVME_QUIRK_DELAY_BEFORE_INIT) { 3817 /* 3818 * Controller may need some delay before it's enabled. 3819 * 3820 * This is a workaround for an issue where the PCIe-attached NVMe controller 3821 * is not ready after VFIO reset. We delay the initialization rather than the 3822 * enabling itself, because this is required only for the very first enabling 3823 * - directly after a VFIO reset. 3824 */ 3825 NVME_CTRLR_DEBUGLOG(ctrlr, "Adding 2 second delay before initializing the controller\n"); 3826 ctrlr->sleep_timeout_tsc = ticks + (2000 * spdk_get_ticks_hz() / 1000); 3827 } 3828 break; 3829 3830 case NVME_CTRLR_STATE_DISCONNECTED: 3831 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE); 3832 break; 3833 3834 case NVME_CTRLR_STATE_CONNECT_ADMINQ: /* synonymous with NVME_CTRLR_STATE_INIT and NVME_CTRLR_STATE_DISCONNECTED */ 3835 rc = nvme_transport_ctrlr_connect_qpair(ctrlr, ctrlr->adminq); 3836 if (rc == 0) { 3837 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_CONNECT_ADMINQ, 3838 NVME_TIMEOUT_INFINITE); 3839 } else { 3840 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3841 } 3842 break; 3843 3844 case NVME_CTRLR_STATE_WAIT_FOR_CONNECT_ADMINQ: 3845 spdk_nvme_qpair_process_completions(ctrlr->adminq, 0); 3846 3847 switch (nvme_qpair_get_state(ctrlr->adminq)) { 3848 case NVME_QPAIR_CONNECTING: 3849 break; 3850 case NVME_QPAIR_CONNECTED: 3851 nvme_qpair_set_state(ctrlr->adminq, NVME_QPAIR_ENABLED); 3852 /* Fall through */ 3853 case NVME_QPAIR_ENABLED: 3854 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_VS, 3855 NVME_TIMEOUT_INFINITE); 3856 /* Abort any queued requests that were sent while the adminq was connecting 3857 * to avoid stalling the init process during a reset, as requests don't get 3858 * resubmitted while the controller is resetting and subsequent commands 3859 * would get queued too. 3860 */ 3861 nvme_qpair_abort_queued_reqs(ctrlr->adminq); 3862 break; 3863 case NVME_QPAIR_DISCONNECTING: 3864 assert(ctrlr->adminq->async == true); 3865 break; 3866 case NVME_QPAIR_DISCONNECTED: 3867 /* fallthrough */ 3868 default: 3869 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3870 break; 3871 } 3872 3873 break; 3874 3875 case NVME_CTRLR_STATE_READ_VS: 3876 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS, NVME_TIMEOUT_INFINITE); 3877 rc = nvme_ctrlr_get_vs_async(ctrlr, nvme_ctrlr_process_init_vs_done, ctrlr); 3878 break; 3879 3880 case NVME_CTRLR_STATE_READ_CAP: 3881 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP, NVME_TIMEOUT_INFINITE); 3882 rc = nvme_ctrlr_get_cap_async(ctrlr, nvme_ctrlr_process_init_cap_done, ctrlr); 3883 break; 3884 3885 case NVME_CTRLR_STATE_CHECK_EN: 3886 /* Begin the hardware initialization by making sure the controller is disabled. */ 3887 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN_WAIT_FOR_CC, ready_timeout_in_ms); 3888 rc = nvme_ctrlr_get_cc_async(ctrlr, nvme_ctrlr_process_init_check_en, ctrlr); 3889 break; 3890 3891 case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1: 3892 /* 3893 * Controller is currently enabled. We need to disable it to cause a reset. 3894 * 3895 * If CC.EN = 1 && CSTS.RDY = 0, the controller is in the process of becoming ready. 3896 * Wait for the ready bit to be 1 before disabling the controller. 3897 */ 3898 nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS, 3899 NVME_TIMEOUT_KEEP_EXISTING); 3900 rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_wait_for_ready_1, ctrlr); 3901 break; 3902 3903 case NVME_CTRLR_STATE_SET_EN_0: 3904 NVME_CTRLR_DEBUGLOG(ctrlr, "Setting CC.EN = 0\n"); 3905 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC, ready_timeout_in_ms); 3906 rc = nvme_ctrlr_get_cc_async(ctrlr, nvme_ctrlr_process_init_set_en_0_read_cc, ctrlr); 3907 break; 3908 3909 case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0: 3910 nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS, 3911 NVME_TIMEOUT_KEEP_EXISTING); 3912 rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_wait_for_ready_0, ctrlr); 3913 break; 3914 3915 case NVME_CTRLR_STATE_DISABLED: 3916 if (ctrlr->is_disconnecting) { 3917 NVME_CTRLR_DEBUGLOG(ctrlr, "Ctrlr was disabled.\n"); 3918 } else { 3919 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE, ready_timeout_in_ms); 3920 3921 /* 3922 * Delay 100us before setting CC.EN = 1. Some NVMe SSDs miss CC.EN getting 3923 * set to 1 if it is too soon after CSTS.RDY is reported as 0. 3924 */ 3925 spdk_delay_us(100); 3926 } 3927 break; 3928 3929 case NVME_CTRLR_STATE_ENABLE: 3930 NVME_CTRLR_DEBUGLOG(ctrlr, "Setting CC.EN = 1\n"); 3931 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC, ready_timeout_in_ms); 3932 rc = nvme_ctrlr_enable(ctrlr); 3933 if (rc) { 3934 NVME_CTRLR_ERRLOG(ctrlr, "Ctrlr enable failed with error: %d", rc); 3935 } 3936 return rc; 3937 3938 case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1: 3939 nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS, 3940 NVME_TIMEOUT_KEEP_EXISTING); 3941 rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_enable_wait_for_ready_1, 3942 ctrlr); 3943 break; 3944 3945 case NVME_CTRLR_STATE_RESET_ADMIN_QUEUE: 3946 nvme_transport_qpair_reset(ctrlr->adminq); 3947 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY, NVME_TIMEOUT_INFINITE); 3948 break; 3949 3950 case NVME_CTRLR_STATE_IDENTIFY: 3951 rc = nvme_ctrlr_identify(ctrlr); 3952 break; 3953 3954 case NVME_CTRLR_STATE_CONFIGURE_AER: 3955 rc = nvme_ctrlr_configure_aer(ctrlr); 3956 break; 3957 3958 case NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT: 3959 rc = nvme_ctrlr_set_keep_alive_timeout(ctrlr); 3960 break; 3961 3962 case NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC: 3963 rc = nvme_ctrlr_identify_iocs_specific(ctrlr); 3964 break; 3965 3966 case NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG: 3967 rc = nvme_ctrlr_get_zns_cmd_and_effects_log(ctrlr); 3968 break; 3969 3970 case NVME_CTRLR_STATE_SET_NUM_QUEUES: 3971 nvme_ctrlr_update_nvmf_ioccsz(ctrlr); 3972 rc = nvme_ctrlr_set_num_queues(ctrlr); 3973 break; 3974 3975 case NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS: 3976 _nvme_ctrlr_identify_active_ns(ctrlr); 3977 break; 3978 3979 case NVME_CTRLR_STATE_IDENTIFY_NS: 3980 rc = nvme_ctrlr_identify_namespaces(ctrlr); 3981 break; 3982 3983 case NVME_CTRLR_STATE_IDENTIFY_ID_DESCS: 3984 rc = nvme_ctrlr_identify_id_desc_namespaces(ctrlr); 3985 break; 3986 3987 case NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC: 3988 rc = nvme_ctrlr_identify_namespaces_iocs_specific(ctrlr); 3989 break; 3990 3991 case NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES: 3992 rc = nvme_ctrlr_set_supported_log_pages(ctrlr); 3993 break; 3994 3995 case NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES: 3996 rc = nvme_ctrlr_set_intel_support_log_pages(ctrlr); 3997 break; 3998 3999 case NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES: 4000 nvme_ctrlr_set_supported_features(ctrlr); 4001 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_DB_BUF_CFG, 4002 ctrlr->opts.admin_timeout_ms); 4003 break; 4004 4005 case NVME_CTRLR_STATE_SET_DB_BUF_CFG: 4006 rc = nvme_ctrlr_set_doorbell_buffer_config(ctrlr); 4007 break; 4008 4009 case NVME_CTRLR_STATE_SET_HOST_ID: 4010 rc = nvme_ctrlr_set_host_id(ctrlr); 4011 break; 4012 4013 case NVME_CTRLR_STATE_TRANSPORT_READY: 4014 rc = nvme_transport_ctrlr_ready(ctrlr); 4015 if (rc) { 4016 NVME_CTRLR_ERRLOG(ctrlr, "Transport controller ready step failed: rc %d\n", rc); 4017 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 4018 } else { 4019 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE); 4020 } 4021 break; 4022 4023 case NVME_CTRLR_STATE_READY: 4024 NVME_CTRLR_DEBUGLOG(ctrlr, "Ctrlr already in ready state\n"); 4025 return 0; 4026 4027 case NVME_CTRLR_STATE_ERROR: 4028 NVME_CTRLR_ERRLOG(ctrlr, "Ctrlr is in error state\n"); 4029 return -1; 4030 4031 case NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS: 4032 case NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP: 4033 case NVME_CTRLR_STATE_CHECK_EN_WAIT_FOR_CC: 4034 case NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC: 4035 case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS: 4036 case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS: 4037 case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC: 4038 case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS: 4039 case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY: 4040 case NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER: 4041 case NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT: 4042 case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC: 4043 case NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG: 4044 case NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES: 4045 case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS: 4046 case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS: 4047 case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS: 4048 case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC: 4049 case NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES: 4050 case NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG: 4051 case NVME_CTRLR_STATE_WAIT_FOR_HOST_ID: 4052 /* 4053 * nvme_ctrlr_process_init() may be called from the completion context 4054 * for the admin qpair. Avoid recursive calls for this case. 4055 */ 4056 if (!ctrlr->adminq->in_completion_context) { 4057 spdk_nvme_qpair_process_completions(ctrlr->adminq, 0); 4058 } 4059 break; 4060 4061 default: 4062 assert(0); 4063 return -1; 4064 } 4065 4066 if (rc) { 4067 NVME_CTRLR_ERRLOG(ctrlr, "Ctrlr operation failed with error: %d, ctrlr state: %d (%s)\n", 4068 rc, ctrlr->state, nvme_ctrlr_state_string(ctrlr->state)); 4069 } 4070 4071 /* Note: we use the ticks captured when we entered this function. 4072 * This covers environments where the SPDK process gets swapped out after 4073 * we tried to advance the state but before we check the timeout here. 4074 * It is not normal for this to happen, but harmless to handle it in this 4075 * way. 4076 */ 4077 if (ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE && 4078 ticks > ctrlr->state_timeout_tsc) { 4079 NVME_CTRLR_ERRLOG(ctrlr, "Initialization timed out in state %d (%s)\n", 4080 ctrlr->state, nvme_ctrlr_state_string(ctrlr->state)); 4081 return -1; 4082 } 4083 4084 return rc; 4085 } 4086 4087 int 4088 nvme_robust_mutex_init_recursive_shared(pthread_mutex_t *mtx) 4089 { 4090 pthread_mutexattr_t attr; 4091 int rc = 0; 4092 4093 if (pthread_mutexattr_init(&attr)) { 4094 return -1; 4095 } 4096 if (pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_RECURSIVE) || 4097 #ifndef __FreeBSD__ 4098 pthread_mutexattr_setrobust(&attr, PTHREAD_MUTEX_ROBUST) || 4099 pthread_mutexattr_setpshared(&attr, PTHREAD_PROCESS_SHARED) || 4100 #endif 4101 pthread_mutex_init(mtx, &attr)) { 4102 rc = -1; 4103 } 4104 pthread_mutexattr_destroy(&attr); 4105 return rc; 4106 } 4107 4108 int 4109 nvme_ctrlr_construct(struct spdk_nvme_ctrlr *ctrlr) 4110 { 4111 int rc; 4112 4113 if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) { 4114 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT_DELAY, NVME_TIMEOUT_INFINITE); 4115 } else { 4116 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE); 4117 } 4118 4119 if (ctrlr->opts.admin_queue_size > SPDK_NVME_ADMIN_QUEUE_MAX_ENTRIES) { 4120 NVME_CTRLR_ERRLOG(ctrlr, "admin_queue_size %u exceeds max defined by NVMe spec, use max value\n", 4121 ctrlr->opts.admin_queue_size); 4122 ctrlr->opts.admin_queue_size = SPDK_NVME_ADMIN_QUEUE_MAX_ENTRIES; 4123 } 4124 4125 if (ctrlr->quirks & NVME_QUIRK_MINIMUM_ADMIN_QUEUE_SIZE && 4126 (ctrlr->opts.admin_queue_size % SPDK_NVME_ADMIN_QUEUE_QUIRK_ENTRIES_MULTIPLE) != 0) { 4127 NVME_CTRLR_ERRLOG(ctrlr, 4128 "admin_queue_size %u is invalid for this NVMe device, adjust to next multiple\n", 4129 ctrlr->opts.admin_queue_size); 4130 ctrlr->opts.admin_queue_size = SPDK_ALIGN_CEIL(ctrlr->opts.admin_queue_size, 4131 SPDK_NVME_ADMIN_QUEUE_QUIRK_ENTRIES_MULTIPLE); 4132 } 4133 4134 if (ctrlr->opts.admin_queue_size < SPDK_NVME_ADMIN_QUEUE_MIN_ENTRIES) { 4135 NVME_CTRLR_ERRLOG(ctrlr, 4136 "admin_queue_size %u is less than minimum defined by NVMe spec, use min value\n", 4137 ctrlr->opts.admin_queue_size); 4138 ctrlr->opts.admin_queue_size = SPDK_NVME_ADMIN_QUEUE_MIN_ENTRIES; 4139 } 4140 4141 ctrlr->flags = 0; 4142 ctrlr->free_io_qids = NULL; 4143 ctrlr->is_resetting = false; 4144 ctrlr->is_failed = false; 4145 ctrlr->is_destructed = false; 4146 4147 TAILQ_INIT(&ctrlr->active_io_qpairs); 4148 STAILQ_INIT(&ctrlr->queued_aborts); 4149 ctrlr->outstanding_aborts = 0; 4150 4151 ctrlr->ana_log_page = NULL; 4152 ctrlr->ana_log_page_size = 0; 4153 4154 rc = nvme_robust_mutex_init_recursive_shared(&ctrlr->ctrlr_lock); 4155 if (rc != 0) { 4156 return rc; 4157 } 4158 4159 TAILQ_INIT(&ctrlr->active_procs); 4160 STAILQ_INIT(&ctrlr->register_operations); 4161 4162 RB_INIT(&ctrlr->ns); 4163 4164 return rc; 4165 } 4166 4167 static void 4168 nvme_ctrlr_init_cap(struct spdk_nvme_ctrlr *ctrlr) 4169 { 4170 if (ctrlr->cap.bits.ams & SPDK_NVME_CAP_AMS_WRR) { 4171 ctrlr->flags |= SPDK_NVME_CTRLR_WRR_SUPPORTED; 4172 } 4173 4174 ctrlr->min_page_size = 1u << (12 + ctrlr->cap.bits.mpsmin); 4175 4176 /* For now, always select page_size == min_page_size. */ 4177 ctrlr->page_size = ctrlr->min_page_size; 4178 4179 ctrlr->opts.io_queue_size = spdk_max(ctrlr->opts.io_queue_size, SPDK_NVME_IO_QUEUE_MIN_ENTRIES); 4180 ctrlr->opts.io_queue_size = spdk_min(ctrlr->opts.io_queue_size, MAX_IO_QUEUE_ENTRIES); 4181 if (ctrlr->quirks & NVME_QUIRK_MINIMUM_IO_QUEUE_SIZE && 4182 ctrlr->opts.io_queue_size == DEFAULT_IO_QUEUE_SIZE) { 4183 /* If the user specifically set an IO queue size different than the 4184 * default, use that value. Otherwise overwrite with the quirked value. 4185 * This allows this quirk to be overridden when necessary. 4186 * However, cap.mqes still needs to be respected. 4187 */ 4188 ctrlr->opts.io_queue_size = DEFAULT_IO_QUEUE_SIZE_FOR_QUIRK; 4189 } 4190 ctrlr->opts.io_queue_size = spdk_min(ctrlr->opts.io_queue_size, ctrlr->cap.bits.mqes + 1u); 4191 4192 ctrlr->opts.io_queue_requests = spdk_max(ctrlr->opts.io_queue_requests, ctrlr->opts.io_queue_size); 4193 } 4194 4195 void 4196 nvme_ctrlr_destruct_finish(struct spdk_nvme_ctrlr *ctrlr) 4197 { 4198 pthread_mutex_destroy(&ctrlr->ctrlr_lock); 4199 4200 nvme_ctrlr_free_processes(ctrlr); 4201 } 4202 4203 void 4204 nvme_ctrlr_destruct_async(struct spdk_nvme_ctrlr *ctrlr, 4205 struct nvme_ctrlr_detach_ctx *ctx) 4206 { 4207 struct spdk_nvme_qpair *qpair, *tmp; 4208 4209 NVME_CTRLR_DEBUGLOG(ctrlr, "Prepare to destruct SSD\n"); 4210 4211 ctrlr->prepare_for_reset = false; 4212 ctrlr->is_destructed = true; 4213 4214 spdk_nvme_qpair_process_completions(ctrlr->adminq, 0); 4215 4216 nvme_ctrlr_abort_queued_aborts(ctrlr); 4217 nvme_transport_admin_qpair_abort_aers(ctrlr->adminq); 4218 4219 TAILQ_FOREACH_SAFE(qpair, &ctrlr->active_io_qpairs, tailq, tmp) { 4220 spdk_nvme_ctrlr_free_io_qpair(qpair); 4221 } 4222 4223 nvme_ctrlr_free_doorbell_buffer(ctrlr); 4224 nvme_ctrlr_free_iocs_specific_data(ctrlr); 4225 4226 nvme_ctrlr_shutdown_async(ctrlr, ctx); 4227 } 4228 4229 int 4230 nvme_ctrlr_destruct_poll_async(struct spdk_nvme_ctrlr *ctrlr, 4231 struct nvme_ctrlr_detach_ctx *ctx) 4232 { 4233 struct spdk_nvme_ns *ns, *tmp_ns; 4234 int rc = 0; 4235 4236 if (!ctx->shutdown_complete) { 4237 rc = nvme_ctrlr_shutdown_poll_async(ctrlr, ctx); 4238 if (rc == -EAGAIN) { 4239 return -EAGAIN; 4240 } 4241 /* Destruct ctrlr forcefully for any other error. */ 4242 } 4243 4244 if (ctx->cb_fn) { 4245 ctx->cb_fn(ctrlr); 4246 } 4247 4248 nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq); 4249 4250 RB_FOREACH_SAFE(ns, nvme_ns_tree, &ctrlr->ns, tmp_ns) { 4251 nvme_ctrlr_destruct_namespace(ctrlr, ns->id); 4252 RB_REMOVE(nvme_ns_tree, &ctrlr->ns, ns); 4253 spdk_free(ns); 4254 } 4255 4256 ctrlr->active_ns_count = 0; 4257 4258 spdk_bit_array_free(&ctrlr->free_io_qids); 4259 4260 free(ctrlr->ana_log_page); 4261 free(ctrlr->copied_ana_desc); 4262 ctrlr->ana_log_page = NULL; 4263 ctrlr->copied_ana_desc = NULL; 4264 ctrlr->ana_log_page_size = 0; 4265 4266 nvme_transport_ctrlr_destruct(ctrlr); 4267 4268 return rc; 4269 } 4270 4271 void 4272 nvme_ctrlr_destruct(struct spdk_nvme_ctrlr *ctrlr) 4273 { 4274 struct nvme_ctrlr_detach_ctx ctx = { .ctrlr = ctrlr }; 4275 int rc; 4276 4277 nvme_ctrlr_destruct_async(ctrlr, &ctx); 4278 4279 while (1) { 4280 rc = nvme_ctrlr_destruct_poll_async(ctrlr, &ctx); 4281 if (rc != -EAGAIN) { 4282 break; 4283 } 4284 nvme_delay(1000); 4285 } 4286 } 4287 4288 int 4289 nvme_ctrlr_submit_admin_request(struct spdk_nvme_ctrlr *ctrlr, 4290 struct nvme_request *req) 4291 { 4292 return nvme_qpair_submit_request(ctrlr->adminq, req); 4293 } 4294 4295 static void 4296 nvme_keep_alive_completion(void *cb_ctx, const struct spdk_nvme_cpl *cpl) 4297 { 4298 /* Do nothing */ 4299 } 4300 4301 /* 4302 * Check if we need to send a Keep Alive command. 4303 * Caller must hold ctrlr->ctrlr_lock. 4304 */ 4305 static int 4306 nvme_ctrlr_keep_alive(struct spdk_nvme_ctrlr *ctrlr) 4307 { 4308 uint64_t now; 4309 struct nvme_request *req; 4310 struct spdk_nvme_cmd *cmd; 4311 int rc = 0; 4312 4313 now = spdk_get_ticks(); 4314 if (now < ctrlr->next_keep_alive_tick) { 4315 return rc; 4316 } 4317 4318 req = nvme_allocate_request_null(ctrlr->adminq, nvme_keep_alive_completion, NULL); 4319 if (req == NULL) { 4320 return rc; 4321 } 4322 4323 cmd = &req->cmd; 4324 cmd->opc = SPDK_NVME_OPC_KEEP_ALIVE; 4325 4326 rc = nvme_ctrlr_submit_admin_request(ctrlr, req); 4327 if (rc != 0) { 4328 NVME_CTRLR_ERRLOG(ctrlr, "Submitting Keep Alive failed\n"); 4329 rc = -ENXIO; 4330 } 4331 4332 ctrlr->next_keep_alive_tick = now + ctrlr->keep_alive_interval_ticks; 4333 return rc; 4334 } 4335 4336 int32_t 4337 spdk_nvme_ctrlr_process_admin_completions(struct spdk_nvme_ctrlr *ctrlr) 4338 { 4339 int32_t num_completions; 4340 int32_t rc; 4341 struct spdk_nvme_ctrlr_process *active_proc; 4342 4343 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 4344 4345 if (ctrlr->keep_alive_interval_ticks) { 4346 rc = nvme_ctrlr_keep_alive(ctrlr); 4347 if (rc) { 4348 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 4349 return rc; 4350 } 4351 } 4352 4353 rc = nvme_io_msg_process(ctrlr); 4354 if (rc < 0) { 4355 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 4356 return rc; 4357 } 4358 num_completions = rc; 4359 4360 rc = spdk_nvme_qpair_process_completions(ctrlr->adminq, 0); 4361 4362 /* Each process has an async list, complete the ones for this process object */ 4363 active_proc = nvme_ctrlr_get_current_process(ctrlr); 4364 if (active_proc) { 4365 nvme_ctrlr_complete_queued_async_events(ctrlr); 4366 } 4367 4368 if (rc == -ENXIO && ctrlr->is_disconnecting) { 4369 nvme_ctrlr_disconnect_done(ctrlr); 4370 } 4371 4372 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 4373 4374 if (rc < 0) { 4375 num_completions = rc; 4376 } else { 4377 num_completions += rc; 4378 } 4379 4380 return num_completions; 4381 } 4382 4383 const struct spdk_nvme_ctrlr_data * 4384 spdk_nvme_ctrlr_get_data(struct spdk_nvme_ctrlr *ctrlr) 4385 { 4386 return &ctrlr->cdata; 4387 } 4388 4389 union spdk_nvme_csts_register spdk_nvme_ctrlr_get_regs_csts(struct spdk_nvme_ctrlr *ctrlr) 4390 { 4391 union spdk_nvme_csts_register csts; 4392 4393 if (nvme_ctrlr_get_csts(ctrlr, &csts)) { 4394 csts.raw = SPDK_NVME_INVALID_REGISTER_VALUE; 4395 } 4396 return csts; 4397 } 4398 4399 union spdk_nvme_cc_register spdk_nvme_ctrlr_get_regs_cc(struct spdk_nvme_ctrlr *ctrlr) 4400 { 4401 union spdk_nvme_cc_register cc; 4402 4403 if (nvme_ctrlr_get_cc(ctrlr, &cc)) { 4404 cc.raw = SPDK_NVME_INVALID_REGISTER_VALUE; 4405 } 4406 return cc; 4407 } 4408 4409 union spdk_nvme_cap_register spdk_nvme_ctrlr_get_regs_cap(struct spdk_nvme_ctrlr *ctrlr) 4410 { 4411 return ctrlr->cap; 4412 } 4413 4414 union spdk_nvme_vs_register spdk_nvme_ctrlr_get_regs_vs(struct spdk_nvme_ctrlr *ctrlr) 4415 { 4416 return ctrlr->vs; 4417 } 4418 4419 union spdk_nvme_cmbsz_register spdk_nvme_ctrlr_get_regs_cmbsz(struct spdk_nvme_ctrlr *ctrlr) 4420 { 4421 union spdk_nvme_cmbsz_register cmbsz; 4422 4423 if (nvme_ctrlr_get_cmbsz(ctrlr, &cmbsz)) { 4424 cmbsz.raw = 0; 4425 } 4426 4427 return cmbsz; 4428 } 4429 4430 union spdk_nvme_pmrcap_register spdk_nvme_ctrlr_get_regs_pmrcap(struct spdk_nvme_ctrlr *ctrlr) 4431 { 4432 union spdk_nvme_pmrcap_register pmrcap; 4433 4434 if (nvme_ctrlr_get_pmrcap(ctrlr, &pmrcap)) { 4435 pmrcap.raw = 0; 4436 } 4437 4438 return pmrcap; 4439 } 4440 4441 union spdk_nvme_bpinfo_register spdk_nvme_ctrlr_get_regs_bpinfo(struct spdk_nvme_ctrlr *ctrlr) 4442 { 4443 union spdk_nvme_bpinfo_register bpinfo; 4444 4445 if (nvme_ctrlr_get_bpinfo(ctrlr, &bpinfo)) { 4446 bpinfo.raw = 0; 4447 } 4448 4449 return bpinfo; 4450 } 4451 4452 uint64_t 4453 spdk_nvme_ctrlr_get_pmrsz(struct spdk_nvme_ctrlr *ctrlr) 4454 { 4455 return ctrlr->pmr_size; 4456 } 4457 4458 uint32_t 4459 spdk_nvme_ctrlr_get_num_ns(struct spdk_nvme_ctrlr *ctrlr) 4460 { 4461 return ctrlr->cdata.nn; 4462 } 4463 4464 bool 4465 spdk_nvme_ctrlr_is_active_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid) 4466 { 4467 struct spdk_nvme_ns tmp, *ns; 4468 4469 tmp.id = nsid; 4470 ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp); 4471 4472 if (ns != NULL) { 4473 return ns->active; 4474 } 4475 4476 return false; 4477 } 4478 4479 uint32_t 4480 spdk_nvme_ctrlr_get_first_active_ns(struct spdk_nvme_ctrlr *ctrlr) 4481 { 4482 struct spdk_nvme_ns *ns; 4483 4484 ns = RB_MIN(nvme_ns_tree, &ctrlr->ns); 4485 if (ns == NULL) { 4486 return 0; 4487 } 4488 4489 while (ns != NULL) { 4490 if (ns->active) { 4491 return ns->id; 4492 } 4493 4494 ns = RB_NEXT(nvme_ns_tree, &ctrlr->ns, ns); 4495 } 4496 4497 return 0; 4498 } 4499 4500 uint32_t 4501 spdk_nvme_ctrlr_get_next_active_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t prev_nsid) 4502 { 4503 struct spdk_nvme_ns tmp, *ns; 4504 4505 tmp.id = prev_nsid; 4506 ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp); 4507 if (ns == NULL) { 4508 return 0; 4509 } 4510 4511 ns = RB_NEXT(nvme_ns_tree, &ctrlr->ns, ns); 4512 while (ns != NULL) { 4513 if (ns->active) { 4514 return ns->id; 4515 } 4516 4517 ns = RB_NEXT(nvme_ns_tree, &ctrlr->ns, ns); 4518 } 4519 4520 return 0; 4521 } 4522 4523 struct spdk_nvme_ns * 4524 spdk_nvme_ctrlr_get_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid) 4525 { 4526 struct spdk_nvme_ns tmp; 4527 struct spdk_nvme_ns *ns; 4528 4529 if (nsid < 1 || nsid > ctrlr->cdata.nn) { 4530 return NULL; 4531 } 4532 4533 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 4534 4535 tmp.id = nsid; 4536 ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp); 4537 4538 if (ns == NULL) { 4539 ns = spdk_zmalloc(sizeof(struct spdk_nvme_ns), 64, NULL, SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE); 4540 if (ns == NULL) { 4541 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 4542 return NULL; 4543 } 4544 4545 NVME_CTRLR_DEBUGLOG(ctrlr, "Namespace %u was added\n", nsid); 4546 ns->id = nsid; 4547 RB_INSERT(nvme_ns_tree, &ctrlr->ns, ns); 4548 } 4549 4550 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 4551 4552 return ns; 4553 } 4554 4555 struct spdk_pci_device * 4556 spdk_nvme_ctrlr_get_pci_device(struct spdk_nvme_ctrlr *ctrlr) 4557 { 4558 if (ctrlr == NULL) { 4559 return NULL; 4560 } 4561 4562 if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) { 4563 return NULL; 4564 } 4565 4566 return nvme_ctrlr_proc_get_devhandle(ctrlr); 4567 } 4568 4569 uint32_t 4570 spdk_nvme_ctrlr_get_max_xfer_size(const struct spdk_nvme_ctrlr *ctrlr) 4571 { 4572 return ctrlr->max_xfer_size; 4573 } 4574 4575 uint16_t 4576 spdk_nvme_ctrlr_get_max_sges(const struct spdk_nvme_ctrlr *ctrlr) 4577 { 4578 if (ctrlr->flags & SPDK_NVME_CTRLR_SGL_SUPPORTED) { 4579 return ctrlr->max_sges; 4580 } else { 4581 return UINT16_MAX; 4582 } 4583 } 4584 4585 void 4586 spdk_nvme_ctrlr_register_aer_callback(struct spdk_nvme_ctrlr *ctrlr, 4587 spdk_nvme_aer_cb aer_cb_fn, 4588 void *aer_cb_arg) 4589 { 4590 struct spdk_nvme_ctrlr_process *active_proc; 4591 4592 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 4593 4594 active_proc = nvme_ctrlr_get_current_process(ctrlr); 4595 if (active_proc) { 4596 active_proc->aer_cb_fn = aer_cb_fn; 4597 active_proc->aer_cb_arg = aer_cb_arg; 4598 } 4599 4600 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 4601 } 4602 4603 void 4604 spdk_nvme_ctrlr_disable_read_changed_ns_list_log_page(struct spdk_nvme_ctrlr *ctrlr) 4605 { 4606 ctrlr->opts.disable_read_changed_ns_list_log_page = true; 4607 } 4608 4609 void 4610 spdk_nvme_ctrlr_register_timeout_callback(struct spdk_nvme_ctrlr *ctrlr, 4611 uint64_t timeout_io_us, uint64_t timeout_admin_us, 4612 spdk_nvme_timeout_cb cb_fn, void *cb_arg) 4613 { 4614 struct spdk_nvme_ctrlr_process *active_proc; 4615 4616 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 4617 4618 active_proc = nvme_ctrlr_get_current_process(ctrlr); 4619 if (active_proc) { 4620 active_proc->timeout_io_ticks = timeout_io_us * spdk_get_ticks_hz() / 1000000ULL; 4621 active_proc->timeout_admin_ticks = timeout_admin_us * spdk_get_ticks_hz() / 1000000ULL; 4622 active_proc->timeout_cb_fn = cb_fn; 4623 active_proc->timeout_cb_arg = cb_arg; 4624 } 4625 4626 ctrlr->timeout_enabled = true; 4627 4628 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 4629 } 4630 4631 bool 4632 spdk_nvme_ctrlr_is_log_page_supported(struct spdk_nvme_ctrlr *ctrlr, uint8_t log_page) 4633 { 4634 /* No bounds check necessary, since log_page is uint8_t and log_page_supported has 256 entries */ 4635 SPDK_STATIC_ASSERT(sizeof(ctrlr->log_page_supported) == 256, "log_page_supported size mismatch"); 4636 return ctrlr->log_page_supported[log_page]; 4637 } 4638 4639 bool 4640 spdk_nvme_ctrlr_is_feature_supported(struct spdk_nvme_ctrlr *ctrlr, uint8_t feature_code) 4641 { 4642 /* No bounds check necessary, since feature_code is uint8_t and feature_supported has 256 entries */ 4643 SPDK_STATIC_ASSERT(sizeof(ctrlr->feature_supported) == 256, "feature_supported size mismatch"); 4644 return ctrlr->feature_supported[feature_code]; 4645 } 4646 4647 int 4648 spdk_nvme_ctrlr_attach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, 4649 struct spdk_nvme_ctrlr_list *payload) 4650 { 4651 struct nvme_completion_poll_status *status; 4652 struct spdk_nvme_ns *ns; 4653 int res; 4654 4655 if (nsid == 0) { 4656 return -EINVAL; 4657 } 4658 4659 status = calloc(1, sizeof(*status)); 4660 if (!status) { 4661 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n"); 4662 return -ENOMEM; 4663 } 4664 4665 res = nvme_ctrlr_cmd_attach_ns(ctrlr, nsid, payload, 4666 nvme_completion_poll_cb, status); 4667 if (res) { 4668 free(status); 4669 return res; 4670 } 4671 if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) { 4672 NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_attach_ns failed!\n"); 4673 if (!status->timed_out) { 4674 free(status); 4675 } 4676 return -ENXIO; 4677 } 4678 free(status); 4679 4680 res = nvme_ctrlr_identify_active_ns(ctrlr); 4681 if (res) { 4682 return res; 4683 } 4684 4685 ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid); 4686 if (ns == NULL) { 4687 NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_get_ns failed!\n"); 4688 return -ENXIO; 4689 } 4690 4691 return nvme_ns_construct(ns, nsid, ctrlr); 4692 } 4693 4694 int 4695 spdk_nvme_ctrlr_detach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, 4696 struct spdk_nvme_ctrlr_list *payload) 4697 { 4698 struct nvme_completion_poll_status *status; 4699 int res; 4700 4701 if (nsid == 0) { 4702 return -EINVAL; 4703 } 4704 4705 status = calloc(1, sizeof(*status)); 4706 if (!status) { 4707 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n"); 4708 return -ENOMEM; 4709 } 4710 4711 res = nvme_ctrlr_cmd_detach_ns(ctrlr, nsid, payload, 4712 nvme_completion_poll_cb, status); 4713 if (res) { 4714 free(status); 4715 return res; 4716 } 4717 if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) { 4718 NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_detach_ns failed!\n"); 4719 if (!status->timed_out) { 4720 free(status); 4721 } 4722 return -ENXIO; 4723 } 4724 free(status); 4725 4726 return nvme_ctrlr_identify_active_ns(ctrlr); 4727 } 4728 4729 uint32_t 4730 spdk_nvme_ctrlr_create_ns(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_ns_data *payload) 4731 { 4732 struct nvme_completion_poll_status *status; 4733 int res; 4734 uint32_t nsid; 4735 4736 status = calloc(1, sizeof(*status)); 4737 if (!status) { 4738 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n"); 4739 return 0; 4740 } 4741 4742 res = nvme_ctrlr_cmd_create_ns(ctrlr, payload, nvme_completion_poll_cb, status); 4743 if (res) { 4744 free(status); 4745 return 0; 4746 } 4747 if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) { 4748 NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_create_ns failed!\n"); 4749 if (!status->timed_out) { 4750 free(status); 4751 } 4752 return 0; 4753 } 4754 4755 nsid = status->cpl.cdw0; 4756 free(status); 4757 4758 assert(nsid > 0); 4759 4760 /* Return the namespace ID that was created */ 4761 return nsid; 4762 } 4763 4764 int 4765 spdk_nvme_ctrlr_delete_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid) 4766 { 4767 struct nvme_completion_poll_status *status; 4768 int res; 4769 4770 if (nsid == 0) { 4771 return -EINVAL; 4772 } 4773 4774 status = calloc(1, sizeof(*status)); 4775 if (!status) { 4776 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n"); 4777 return -ENOMEM; 4778 } 4779 4780 res = nvme_ctrlr_cmd_delete_ns(ctrlr, nsid, nvme_completion_poll_cb, status); 4781 if (res) { 4782 free(status); 4783 return res; 4784 } 4785 if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) { 4786 NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_delete_ns failed!\n"); 4787 if (!status->timed_out) { 4788 free(status); 4789 } 4790 return -ENXIO; 4791 } 4792 free(status); 4793 4794 return nvme_ctrlr_identify_active_ns(ctrlr); 4795 } 4796 4797 int 4798 spdk_nvme_ctrlr_format(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, 4799 struct spdk_nvme_format *format) 4800 { 4801 struct nvme_completion_poll_status *status; 4802 int res; 4803 4804 status = calloc(1, sizeof(*status)); 4805 if (!status) { 4806 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n"); 4807 return -ENOMEM; 4808 } 4809 4810 res = nvme_ctrlr_cmd_format(ctrlr, nsid, format, nvme_completion_poll_cb, 4811 status); 4812 if (res) { 4813 free(status); 4814 return res; 4815 } 4816 if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) { 4817 NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_format failed!\n"); 4818 if (!status->timed_out) { 4819 free(status); 4820 } 4821 return -ENXIO; 4822 } 4823 free(status); 4824 4825 return spdk_nvme_ctrlr_reset(ctrlr); 4826 } 4827 4828 int 4829 spdk_nvme_ctrlr_update_firmware(struct spdk_nvme_ctrlr *ctrlr, void *payload, uint32_t size, 4830 int slot, enum spdk_nvme_fw_commit_action commit_action, struct spdk_nvme_status *completion_status) 4831 { 4832 struct spdk_nvme_fw_commit fw_commit; 4833 struct nvme_completion_poll_status *status; 4834 int res; 4835 unsigned int size_remaining; 4836 unsigned int offset; 4837 unsigned int transfer; 4838 uint8_t *p; 4839 4840 if (!completion_status) { 4841 return -EINVAL; 4842 } 4843 memset(completion_status, 0, sizeof(struct spdk_nvme_status)); 4844 if (size % 4) { 4845 NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_update_firmware invalid size!\n"); 4846 return -1; 4847 } 4848 4849 /* Current support only for SPDK_NVME_FW_COMMIT_REPLACE_IMG 4850 * and SPDK_NVME_FW_COMMIT_REPLACE_AND_ENABLE_IMG 4851 */ 4852 if ((commit_action != SPDK_NVME_FW_COMMIT_REPLACE_IMG) && 4853 (commit_action != SPDK_NVME_FW_COMMIT_REPLACE_AND_ENABLE_IMG)) { 4854 NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_update_firmware invalid command!\n"); 4855 return -1; 4856 } 4857 4858 status = calloc(1, sizeof(*status)); 4859 if (!status) { 4860 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n"); 4861 return -ENOMEM; 4862 } 4863 4864 /* Firmware download */ 4865 size_remaining = size; 4866 offset = 0; 4867 p = payload; 4868 4869 while (size_remaining > 0) { 4870 transfer = spdk_min(size_remaining, ctrlr->min_page_size); 4871 4872 memset(status, 0, sizeof(*status)); 4873 res = nvme_ctrlr_cmd_fw_image_download(ctrlr, transfer, offset, p, 4874 nvme_completion_poll_cb, 4875 status); 4876 if (res) { 4877 free(status); 4878 return res; 4879 } 4880 4881 if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) { 4882 NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_fw_image_download failed!\n"); 4883 if (!status->timed_out) { 4884 free(status); 4885 } 4886 return -ENXIO; 4887 } 4888 p += transfer; 4889 offset += transfer; 4890 size_remaining -= transfer; 4891 } 4892 4893 /* Firmware commit */ 4894 memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit)); 4895 fw_commit.fs = slot; 4896 fw_commit.ca = commit_action; 4897 4898 memset(status, 0, sizeof(*status)); 4899 res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit, nvme_completion_poll_cb, 4900 status); 4901 if (res) { 4902 free(status); 4903 return res; 4904 } 4905 4906 res = nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock); 4907 4908 memcpy(completion_status, &status->cpl.status, sizeof(struct spdk_nvme_status)); 4909 4910 if (!status->timed_out) { 4911 free(status); 4912 } 4913 4914 if (res) { 4915 if (completion_status->sct != SPDK_NVME_SCT_COMMAND_SPECIFIC || 4916 completion_status->sc != SPDK_NVME_SC_FIRMWARE_REQ_NVM_RESET) { 4917 if (completion_status->sct == SPDK_NVME_SCT_COMMAND_SPECIFIC && 4918 completion_status->sc == SPDK_NVME_SC_FIRMWARE_REQ_CONVENTIONAL_RESET) { 4919 NVME_CTRLR_NOTICELOG(ctrlr, 4920 "firmware activation requires conventional reset to be performed. !\n"); 4921 } else { 4922 NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_commit failed!\n"); 4923 } 4924 return -ENXIO; 4925 } 4926 } 4927 4928 return spdk_nvme_ctrlr_reset(ctrlr); 4929 } 4930 4931 int 4932 spdk_nvme_ctrlr_reserve_cmb(struct spdk_nvme_ctrlr *ctrlr) 4933 { 4934 int rc, size; 4935 union spdk_nvme_cmbsz_register cmbsz; 4936 4937 cmbsz = spdk_nvme_ctrlr_get_regs_cmbsz(ctrlr); 4938 4939 if (cmbsz.bits.rds == 0 || cmbsz.bits.wds == 0) { 4940 return -ENOTSUP; 4941 } 4942 4943 size = cmbsz.bits.sz * (0x1000 << (cmbsz.bits.szu * 4)); 4944 4945 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 4946 rc = nvme_transport_ctrlr_reserve_cmb(ctrlr); 4947 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 4948 4949 if (rc < 0) { 4950 return rc; 4951 } 4952 4953 return size; 4954 } 4955 4956 void * 4957 spdk_nvme_ctrlr_map_cmb(struct spdk_nvme_ctrlr *ctrlr, size_t *size) 4958 { 4959 void *buf; 4960 4961 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 4962 buf = nvme_transport_ctrlr_map_cmb(ctrlr, size); 4963 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 4964 4965 return buf; 4966 } 4967 4968 void 4969 spdk_nvme_ctrlr_unmap_cmb(struct spdk_nvme_ctrlr *ctrlr) 4970 { 4971 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 4972 nvme_transport_ctrlr_unmap_cmb(ctrlr); 4973 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 4974 } 4975 4976 int 4977 spdk_nvme_ctrlr_enable_pmr(struct spdk_nvme_ctrlr *ctrlr) 4978 { 4979 int rc; 4980 4981 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 4982 rc = nvme_transport_ctrlr_enable_pmr(ctrlr); 4983 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 4984 4985 return rc; 4986 } 4987 4988 int 4989 spdk_nvme_ctrlr_disable_pmr(struct spdk_nvme_ctrlr *ctrlr) 4990 { 4991 int rc; 4992 4993 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 4994 rc = nvme_transport_ctrlr_disable_pmr(ctrlr); 4995 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 4996 4997 return rc; 4998 } 4999 5000 void * 5001 spdk_nvme_ctrlr_map_pmr(struct spdk_nvme_ctrlr *ctrlr, size_t *size) 5002 { 5003 void *buf; 5004 5005 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 5006 buf = nvme_transport_ctrlr_map_pmr(ctrlr, size); 5007 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 5008 5009 return buf; 5010 } 5011 5012 int 5013 spdk_nvme_ctrlr_unmap_pmr(struct spdk_nvme_ctrlr *ctrlr) 5014 { 5015 int rc; 5016 5017 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 5018 rc = nvme_transport_ctrlr_unmap_pmr(ctrlr); 5019 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 5020 5021 return rc; 5022 } 5023 5024 int 5025 spdk_nvme_ctrlr_read_boot_partition_start(struct spdk_nvme_ctrlr *ctrlr, void *payload, 5026 uint32_t bprsz, uint32_t bprof, uint32_t bpid) 5027 { 5028 union spdk_nvme_bprsel_register bprsel; 5029 union spdk_nvme_bpinfo_register bpinfo; 5030 uint64_t bpmbl, bpmb_size; 5031 5032 if (ctrlr->cap.bits.bps == 0) { 5033 return -ENOTSUP; 5034 } 5035 5036 if (nvme_ctrlr_get_bpinfo(ctrlr, &bpinfo)) { 5037 NVME_CTRLR_ERRLOG(ctrlr, "get bpinfo failed\n"); 5038 return -EIO; 5039 } 5040 5041 if (bpinfo.bits.brs == SPDK_NVME_BRS_READ_IN_PROGRESS) { 5042 NVME_CTRLR_ERRLOG(ctrlr, "Boot Partition read already initiated\n"); 5043 return -EALREADY; 5044 } 5045 5046 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 5047 5048 bpmb_size = bprsz * 4096; 5049 bpmbl = spdk_vtophys(payload, &bpmb_size); 5050 if (bpmbl == SPDK_VTOPHYS_ERROR) { 5051 NVME_CTRLR_ERRLOG(ctrlr, "spdk_vtophys of bpmbl failed\n"); 5052 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 5053 return -EFAULT; 5054 } 5055 5056 if (bpmb_size != bprsz * 4096) { 5057 NVME_CTRLR_ERRLOG(ctrlr, "Boot Partition buffer is not physically contiguous\n"); 5058 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 5059 return -EFAULT; 5060 } 5061 5062 if (nvme_ctrlr_set_bpmbl(ctrlr, bpmbl)) { 5063 NVME_CTRLR_ERRLOG(ctrlr, "set_bpmbl() failed\n"); 5064 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 5065 return -EIO; 5066 } 5067 5068 bprsel.bits.bpid = bpid; 5069 bprsel.bits.bprof = bprof; 5070 bprsel.bits.bprsz = bprsz; 5071 5072 if (nvme_ctrlr_set_bprsel(ctrlr, &bprsel)) { 5073 NVME_CTRLR_ERRLOG(ctrlr, "set_bprsel() failed\n"); 5074 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 5075 return -EIO; 5076 } 5077 5078 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 5079 return 0; 5080 } 5081 5082 int 5083 spdk_nvme_ctrlr_read_boot_partition_poll(struct spdk_nvme_ctrlr *ctrlr) 5084 { 5085 int rc = 0; 5086 union spdk_nvme_bpinfo_register bpinfo; 5087 5088 if (nvme_ctrlr_get_bpinfo(ctrlr, &bpinfo)) { 5089 NVME_CTRLR_ERRLOG(ctrlr, "get bpinfo failed\n"); 5090 return -EIO; 5091 } 5092 5093 switch (bpinfo.bits.brs) { 5094 case SPDK_NVME_BRS_NO_READ: 5095 NVME_CTRLR_ERRLOG(ctrlr, "Boot Partition read not initiated\n"); 5096 rc = -EINVAL; 5097 break; 5098 case SPDK_NVME_BRS_READ_IN_PROGRESS: 5099 NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition read in progress\n"); 5100 rc = -EAGAIN; 5101 break; 5102 case SPDK_NVME_BRS_READ_ERROR: 5103 NVME_CTRLR_ERRLOG(ctrlr, "Error completing Boot Partition read\n"); 5104 rc = -EIO; 5105 break; 5106 case SPDK_NVME_BRS_READ_SUCCESS: 5107 NVME_CTRLR_INFOLOG(ctrlr, "Boot Partition read completed successfully\n"); 5108 break; 5109 default: 5110 NVME_CTRLR_ERRLOG(ctrlr, "Invalid Boot Partition read status\n"); 5111 rc = -EINVAL; 5112 } 5113 5114 return rc; 5115 } 5116 5117 static void 5118 nvme_write_boot_partition_cb(void *arg, const struct spdk_nvme_cpl *cpl) 5119 { 5120 int res; 5121 struct spdk_nvme_ctrlr *ctrlr = arg; 5122 struct spdk_nvme_fw_commit fw_commit; 5123 struct spdk_nvme_cpl err_cpl = 5124 {.status = {.sct = SPDK_NVME_SCT_GENERIC, .sc = SPDK_NVME_SC_INTERNAL_DEVICE_ERROR }}; 5125 5126 if (spdk_nvme_cpl_is_error(cpl)) { 5127 NVME_CTRLR_ERRLOG(ctrlr, "Write Boot Partition failed\n"); 5128 ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, cpl); 5129 return; 5130 } 5131 5132 if (ctrlr->bp_ws == SPDK_NVME_BP_WS_DOWNLOADING) { 5133 NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Downloading at Offset %d Success\n", ctrlr->fw_offset); 5134 ctrlr->fw_payload = (uint8_t *)ctrlr->fw_payload + ctrlr->fw_transfer_size; 5135 ctrlr->fw_offset += ctrlr->fw_transfer_size; 5136 ctrlr->fw_size_remaining -= ctrlr->fw_transfer_size; 5137 ctrlr->fw_transfer_size = spdk_min(ctrlr->fw_size_remaining, ctrlr->min_page_size); 5138 res = nvme_ctrlr_cmd_fw_image_download(ctrlr, ctrlr->fw_transfer_size, ctrlr->fw_offset, 5139 ctrlr->fw_payload, nvme_write_boot_partition_cb, ctrlr); 5140 if (res) { 5141 NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_image_download failed!\n"); 5142 ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl); 5143 return; 5144 } 5145 5146 if (ctrlr->fw_transfer_size < ctrlr->min_page_size) { 5147 ctrlr->bp_ws = SPDK_NVME_BP_WS_DOWNLOADED; 5148 } 5149 } else if (ctrlr->bp_ws == SPDK_NVME_BP_WS_DOWNLOADED) { 5150 NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Download Success\n"); 5151 memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit)); 5152 fw_commit.bpid = ctrlr->bpid; 5153 fw_commit.ca = SPDK_NVME_FW_COMMIT_REPLACE_BOOT_PARTITION; 5154 res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit, 5155 nvme_write_boot_partition_cb, ctrlr); 5156 if (res) { 5157 NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_commit failed!\n"); 5158 NVME_CTRLR_ERRLOG(ctrlr, "commit action: %d\n", fw_commit.ca); 5159 ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl); 5160 return; 5161 } 5162 5163 ctrlr->bp_ws = SPDK_NVME_BP_WS_REPLACE; 5164 } else if (ctrlr->bp_ws == SPDK_NVME_BP_WS_REPLACE) { 5165 NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Replacement Success\n"); 5166 memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit)); 5167 fw_commit.bpid = ctrlr->bpid; 5168 fw_commit.ca = SPDK_NVME_FW_COMMIT_ACTIVATE_BOOT_PARTITION; 5169 res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit, 5170 nvme_write_boot_partition_cb, ctrlr); 5171 if (res) { 5172 NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_commit failed!\n"); 5173 NVME_CTRLR_ERRLOG(ctrlr, "commit action: %d\n", fw_commit.ca); 5174 ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl); 5175 return; 5176 } 5177 5178 ctrlr->bp_ws = SPDK_NVME_BP_WS_ACTIVATE; 5179 } else if (ctrlr->bp_ws == SPDK_NVME_BP_WS_ACTIVATE) { 5180 NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Activation Success\n"); 5181 ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, cpl); 5182 } else { 5183 NVME_CTRLR_ERRLOG(ctrlr, "Invalid Boot Partition write state\n"); 5184 ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl); 5185 return; 5186 } 5187 } 5188 5189 int 5190 spdk_nvme_ctrlr_write_boot_partition(struct spdk_nvme_ctrlr *ctrlr, 5191 void *payload, uint32_t size, uint32_t bpid, 5192 spdk_nvme_cmd_cb cb_fn, void *cb_arg) 5193 { 5194 int res; 5195 5196 if (ctrlr->cap.bits.bps == 0) { 5197 return -ENOTSUP; 5198 } 5199 5200 ctrlr->bp_ws = SPDK_NVME_BP_WS_DOWNLOADING; 5201 ctrlr->bpid = bpid; 5202 ctrlr->bp_write_cb_fn = cb_fn; 5203 ctrlr->bp_write_cb_arg = cb_arg; 5204 ctrlr->fw_offset = 0; 5205 ctrlr->fw_size_remaining = size; 5206 ctrlr->fw_payload = payload; 5207 ctrlr->fw_transfer_size = spdk_min(ctrlr->fw_size_remaining, ctrlr->min_page_size); 5208 5209 res = nvme_ctrlr_cmd_fw_image_download(ctrlr, ctrlr->fw_transfer_size, ctrlr->fw_offset, 5210 ctrlr->fw_payload, nvme_write_boot_partition_cb, ctrlr); 5211 5212 return res; 5213 } 5214 5215 bool 5216 spdk_nvme_ctrlr_is_discovery(struct spdk_nvme_ctrlr *ctrlr) 5217 { 5218 assert(ctrlr); 5219 5220 return !strncmp(ctrlr->trid.subnqn, SPDK_NVMF_DISCOVERY_NQN, 5221 strlen(SPDK_NVMF_DISCOVERY_NQN)); 5222 } 5223 5224 bool 5225 spdk_nvme_ctrlr_is_fabrics(struct spdk_nvme_ctrlr *ctrlr) 5226 { 5227 assert(ctrlr); 5228 5229 return spdk_nvme_trtype_is_fabrics(ctrlr->trid.trtype); 5230 } 5231 5232 int 5233 spdk_nvme_ctrlr_security_receive(struct spdk_nvme_ctrlr *ctrlr, uint8_t secp, 5234 uint16_t spsp, uint8_t nssf, void *payload, size_t size) 5235 { 5236 struct nvme_completion_poll_status *status; 5237 int res; 5238 5239 status = calloc(1, sizeof(*status)); 5240 if (!status) { 5241 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n"); 5242 return -ENOMEM; 5243 } 5244 5245 res = spdk_nvme_ctrlr_cmd_security_receive(ctrlr, secp, spsp, nssf, payload, size, 5246 nvme_completion_poll_cb, status); 5247 if (res) { 5248 free(status); 5249 return res; 5250 } 5251 if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) { 5252 NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_cmd_security_receive failed!\n"); 5253 if (!status->timed_out) { 5254 free(status); 5255 } 5256 return -ENXIO; 5257 } 5258 free(status); 5259 5260 return 0; 5261 } 5262 5263 int 5264 spdk_nvme_ctrlr_security_send(struct spdk_nvme_ctrlr *ctrlr, uint8_t secp, 5265 uint16_t spsp, uint8_t nssf, void *payload, size_t size) 5266 { 5267 struct nvme_completion_poll_status *status; 5268 int res; 5269 5270 status = calloc(1, sizeof(*status)); 5271 if (!status) { 5272 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n"); 5273 return -ENOMEM; 5274 } 5275 5276 res = spdk_nvme_ctrlr_cmd_security_send(ctrlr, secp, spsp, nssf, payload, size, 5277 nvme_completion_poll_cb, 5278 status); 5279 if (res) { 5280 free(status); 5281 return res; 5282 } 5283 if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) { 5284 NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_cmd_security_send failed!\n"); 5285 if (!status->timed_out) { 5286 free(status); 5287 } 5288 return -ENXIO; 5289 } 5290 5291 free(status); 5292 5293 return 0; 5294 } 5295 5296 uint64_t 5297 spdk_nvme_ctrlr_get_flags(struct spdk_nvme_ctrlr *ctrlr) 5298 { 5299 return ctrlr->flags; 5300 } 5301 5302 const struct spdk_nvme_transport_id * 5303 spdk_nvme_ctrlr_get_transport_id(struct spdk_nvme_ctrlr *ctrlr) 5304 { 5305 return &ctrlr->trid; 5306 } 5307 5308 int32_t 5309 spdk_nvme_ctrlr_alloc_qid(struct spdk_nvme_ctrlr *ctrlr) 5310 { 5311 uint32_t qid; 5312 5313 assert(ctrlr->free_io_qids); 5314 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 5315 qid = spdk_bit_array_find_first_set(ctrlr->free_io_qids, 1); 5316 if (qid > ctrlr->opts.num_io_queues) { 5317 NVME_CTRLR_ERRLOG(ctrlr, "No free I/O queue IDs\n"); 5318 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 5319 return -1; 5320 } 5321 5322 spdk_bit_array_clear(ctrlr->free_io_qids, qid); 5323 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 5324 return qid; 5325 } 5326 5327 void 5328 spdk_nvme_ctrlr_free_qid(struct spdk_nvme_ctrlr *ctrlr, uint16_t qid) 5329 { 5330 assert(qid <= ctrlr->opts.num_io_queues); 5331 5332 nvme_robust_mutex_lock(&ctrlr->ctrlr_lock); 5333 5334 if (spdk_likely(ctrlr->free_io_qids)) { 5335 spdk_bit_array_set(ctrlr->free_io_qids, qid); 5336 } 5337 5338 nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock); 5339 } 5340 5341 int 5342 spdk_nvme_ctrlr_get_memory_domains(const struct spdk_nvme_ctrlr *ctrlr, 5343 struct spdk_memory_domain **domains, int array_size) 5344 { 5345 return nvme_transport_ctrlr_get_memory_domains(ctrlr, domains, array_size); 5346 } 5347