xref: /spdk/lib/nvme/nvme_ctrlr.c (revision b30d57cdad6d2bc75cc1e4e2ebbcebcb0d98dcfa)
1 /*-
2  *   BSD LICENSE
3  *
4  *   Copyright (c) Intel Corporation. All rights reserved.
5  *   Copyright (c) 2019, 2020 Mellanox Technologies LTD. All rights reserved.
6  *
7  *   Redistribution and use in source and binary forms, with or without
8  *   modification, are permitted provided that the following conditions
9  *   are met:
10  *
11  *     * Redistributions of source code must retain the above copyright
12  *       notice, this list of conditions and the following disclaimer.
13  *     * Redistributions in binary form must reproduce the above copyright
14  *       notice, this list of conditions and the following disclaimer in
15  *       the documentation and/or other materials provided with the
16  *       distribution.
17  *     * Neither the name of Intel Corporation nor the names of its
18  *       contributors may be used to endorse or promote products derived
19  *       from this software without specific prior written permission.
20  *
21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  */
33 
34 #include "spdk/stdinc.h"
35 
36 #include "nvme_internal.h"
37 #include "nvme_io_msg.h"
38 
39 #include "spdk/env.h"
40 #include "spdk/string.h"
41 
42 struct nvme_active_ns_ctx;
43 
44 static void nvme_ctrlr_destruct_namespaces(struct spdk_nvme_ctrlr *ctrlr);
45 static int nvme_ctrlr_construct_and_submit_aer(struct spdk_nvme_ctrlr *ctrlr,
46 		struct nvme_async_event_request *aer);
47 static void nvme_ctrlr_identify_active_ns_async(struct nvme_active_ns_ctx *ctx);
48 static int nvme_ctrlr_identify_ns_async(struct spdk_nvme_ns *ns);
49 static int nvme_ctrlr_identify_ns_iocs_specific_async(struct spdk_nvme_ns *ns);
50 static int nvme_ctrlr_identify_id_desc_async(struct spdk_nvme_ns *ns);
51 
52 static int
53 nvme_ctrlr_get_cc(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cc_register *cc)
54 {
55 	return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, cc.raw),
56 					      &cc->raw);
57 }
58 
59 static int
60 nvme_ctrlr_get_csts(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_csts_register *csts)
61 {
62 	return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, csts.raw),
63 					      &csts->raw);
64 }
65 
66 int
67 nvme_ctrlr_get_cap(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cap_register *cap)
68 {
69 	return nvme_transport_ctrlr_get_reg_8(ctrlr, offsetof(struct spdk_nvme_registers, cap.raw),
70 					      &cap->raw);
71 }
72 
73 int
74 nvme_ctrlr_get_vs(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_vs_register *vs)
75 {
76 	return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, vs.raw),
77 					      &vs->raw);
78 }
79 
80 static int
81 nvme_ctrlr_set_cc(struct spdk_nvme_ctrlr *ctrlr, const union spdk_nvme_cc_register *cc)
82 {
83 	return nvme_transport_ctrlr_set_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, cc.raw),
84 					      cc->raw);
85 }
86 
87 int
88 nvme_ctrlr_get_cmbsz(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cmbsz_register *cmbsz)
89 {
90 	return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, cmbsz.raw),
91 					      &cmbsz->raw);
92 }
93 
94 static int
95 nvme_ctrlr_set_nssr(struct spdk_nvme_ctrlr *ctrlr, uint32_t nssr_value)
96 {
97 	return nvme_transport_ctrlr_set_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, nssr),
98 					      nssr_value);
99 }
100 
101 bool
102 nvme_ctrlr_multi_iocs_enabled(struct spdk_nvme_ctrlr *ctrlr)
103 {
104 	return ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS &&
105 	       ctrlr->opts.command_set == SPDK_NVME_CC_CSS_IOCS;
106 }
107 
108 /* When the field in spdk_nvme_ctrlr_opts are changed and you change this function, please
109  * also update the nvme_ctrl_opts_init function in nvme_ctrlr.c
110  */
111 void
112 spdk_nvme_ctrlr_get_default_ctrlr_opts(struct spdk_nvme_ctrlr_opts *opts, size_t opts_size)
113 {
114 	char host_id_str[SPDK_UUID_STRING_LEN];
115 
116 	assert(opts);
117 
118 	opts->opts_size = opts_size;
119 
120 #define FIELD_OK(field) \
121 	offsetof(struct spdk_nvme_ctrlr_opts, field) + sizeof(opts->field) <= opts_size
122 
123 #define SET_FIELD(field, value) \
124 	if (offsetof(struct spdk_nvme_ctrlr_opts, field) + sizeof(opts->field) <= opts_size) { \
125 		opts->field = value; \
126 	} \
127 
128 	SET_FIELD(num_io_queues, DEFAULT_MAX_IO_QUEUES);
129 	SET_FIELD(use_cmb_sqs, true);
130 	SET_FIELD(no_shn_notification, false);
131 	SET_FIELD(arb_mechanism, SPDK_NVME_CC_AMS_RR);
132 	SET_FIELD(arbitration_burst, 0);
133 	SET_FIELD(low_priority_weight, 0);
134 	SET_FIELD(medium_priority_weight, 0);
135 	SET_FIELD(high_priority_weight, 0);
136 	SET_FIELD(keep_alive_timeout_ms, MIN_KEEP_ALIVE_TIMEOUT_IN_MS);
137 	SET_FIELD(transport_retry_count, SPDK_NVME_DEFAULT_RETRY_COUNT);
138 	SET_FIELD(io_queue_size, DEFAULT_IO_QUEUE_SIZE);
139 
140 	if (nvme_driver_init() == 0) {
141 		if (FIELD_OK(hostnqn)) {
142 			spdk_uuid_fmt_lower(host_id_str, sizeof(host_id_str),
143 					    &g_spdk_nvme_driver->default_extended_host_id);
144 			snprintf(opts->hostnqn, sizeof(opts->hostnqn),
145 				 "nqn.2014-08.org.nvmexpress:uuid:%s", host_id_str);
146 		}
147 
148 		if (FIELD_OK(extended_host_id)) {
149 			memcpy(opts->extended_host_id, &g_spdk_nvme_driver->default_extended_host_id,
150 			       sizeof(opts->extended_host_id));
151 		}
152 
153 	}
154 
155 	SET_FIELD(io_queue_requests, DEFAULT_IO_QUEUE_REQUESTS);
156 
157 	if (FIELD_OK(src_addr)) {
158 		memset(opts->src_addr, 0, sizeof(opts->src_addr));
159 	}
160 
161 	if (FIELD_OK(src_svcid)) {
162 		memset(opts->src_svcid, 0, sizeof(opts->src_svcid));
163 	}
164 
165 	if (FIELD_OK(host_id)) {
166 		memset(opts->host_id, 0, sizeof(opts->host_id));
167 	}
168 
169 	SET_FIELD(command_set, CHAR_BIT);
170 	SET_FIELD(admin_timeout_ms, NVME_MAX_ADMIN_TIMEOUT_IN_SECS * 1000);
171 	SET_FIELD(header_digest, false);
172 	SET_FIELD(data_digest, false);
173 	SET_FIELD(disable_error_logging, false);
174 	SET_FIELD(transport_ack_timeout, SPDK_NVME_DEFAULT_TRANSPORT_ACK_TIMEOUT);
175 	SET_FIELD(admin_queue_size, DEFAULT_ADMIN_QUEUE_SIZE);
176 	SET_FIELD(fabrics_connect_timeout_us, NVME_FABRIC_CONNECT_COMMAND_TIMEOUT);
177 
178 #undef FIELD_OK
179 #undef SET_FIELD
180 }
181 
182 /**
183  * This function will be called when the process allocates the IO qpair.
184  * Note: the ctrlr_lock must be held when calling this function.
185  */
186 static void
187 nvme_ctrlr_proc_add_io_qpair(struct spdk_nvme_qpair *qpair)
188 {
189 	struct spdk_nvme_ctrlr_process	*active_proc;
190 	struct spdk_nvme_ctrlr		*ctrlr = qpair->ctrlr;
191 
192 	active_proc = nvme_ctrlr_get_current_process(ctrlr);
193 	if (active_proc) {
194 		TAILQ_INSERT_TAIL(&active_proc->allocated_io_qpairs, qpair, per_process_tailq);
195 		qpair->active_proc = active_proc;
196 	}
197 }
198 
199 /**
200  * This function will be called when the process frees the IO qpair.
201  * Note: the ctrlr_lock must be held when calling this function.
202  */
203 static void
204 nvme_ctrlr_proc_remove_io_qpair(struct spdk_nvme_qpair *qpair)
205 {
206 	struct spdk_nvme_ctrlr_process	*active_proc;
207 	struct spdk_nvme_ctrlr		*ctrlr = qpair->ctrlr;
208 	struct spdk_nvme_qpair          *active_qpair, *tmp_qpair;
209 
210 	active_proc = nvme_ctrlr_get_current_process(ctrlr);
211 	if (!active_proc) {
212 		return;
213 	}
214 
215 	TAILQ_FOREACH_SAFE(active_qpair, &active_proc->allocated_io_qpairs,
216 			   per_process_tailq, tmp_qpair) {
217 		if (active_qpair == qpair) {
218 			TAILQ_REMOVE(&active_proc->allocated_io_qpairs,
219 				     active_qpair, per_process_tailq);
220 
221 			break;
222 		}
223 	}
224 }
225 
226 void
227 spdk_nvme_ctrlr_get_default_io_qpair_opts(struct spdk_nvme_ctrlr *ctrlr,
228 		struct spdk_nvme_io_qpair_opts *opts,
229 		size_t opts_size)
230 {
231 	assert(ctrlr);
232 
233 	assert(opts);
234 
235 	memset(opts, 0, opts_size);
236 
237 #define FIELD_OK(field) \
238 	offsetof(struct spdk_nvme_io_qpair_opts, field) + sizeof(opts->field) <= opts_size
239 
240 	if (FIELD_OK(qprio)) {
241 		opts->qprio = SPDK_NVME_QPRIO_URGENT;
242 	}
243 
244 	if (FIELD_OK(io_queue_size)) {
245 		opts->io_queue_size = ctrlr->opts.io_queue_size;
246 	}
247 
248 	if (FIELD_OK(io_queue_requests)) {
249 		opts->io_queue_requests = ctrlr->opts.io_queue_requests;
250 	}
251 
252 	if (FIELD_OK(delay_cmd_submit)) {
253 		opts->delay_cmd_submit = false;
254 	}
255 
256 	if (FIELD_OK(sq.vaddr)) {
257 		opts->sq.vaddr = NULL;
258 	}
259 
260 	if (FIELD_OK(sq.paddr)) {
261 		opts->sq.paddr = 0;
262 	}
263 
264 	if (FIELD_OK(sq.buffer_size)) {
265 		opts->sq.buffer_size = 0;
266 	}
267 
268 	if (FIELD_OK(cq.vaddr)) {
269 		opts->cq.vaddr = NULL;
270 	}
271 
272 	if (FIELD_OK(cq.paddr)) {
273 		opts->cq.paddr = 0;
274 	}
275 
276 	if (FIELD_OK(cq.buffer_size)) {
277 		opts->cq.buffer_size = 0;
278 	}
279 
280 	if (FIELD_OK(create_only)) {
281 		opts->create_only = false;
282 	}
283 
284 #undef FIELD_OK
285 }
286 
287 static struct spdk_nvme_qpair *
288 nvme_ctrlr_create_io_qpair(struct spdk_nvme_ctrlr *ctrlr,
289 			   const struct spdk_nvme_io_qpair_opts *opts)
290 {
291 	int32_t					qid;
292 	struct spdk_nvme_qpair			*qpair;
293 	union spdk_nvme_cc_register		cc;
294 
295 	if (!ctrlr) {
296 		return NULL;
297 	}
298 
299 	nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
300 	if (nvme_ctrlr_get_cc(ctrlr, &cc)) {
301 		SPDK_ERRLOG("get_cc failed\n");
302 		nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
303 		return NULL;
304 	}
305 
306 	if (opts->qprio & ~SPDK_NVME_CREATE_IO_SQ_QPRIO_MASK) {
307 		nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
308 		return NULL;
309 	}
310 
311 	/*
312 	 * Only value SPDK_NVME_QPRIO_URGENT(0) is valid for the
313 	 * default round robin arbitration method.
314 	 */
315 	if ((cc.bits.ams == SPDK_NVME_CC_AMS_RR) && (opts->qprio != SPDK_NVME_QPRIO_URGENT)) {
316 		SPDK_ERRLOG("invalid queue priority for default round robin arbitration method\n");
317 		nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
318 		return NULL;
319 	}
320 
321 	qid = spdk_nvme_ctrlr_alloc_qid(ctrlr);
322 	if (qid < 0) {
323 		nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
324 		return NULL;
325 	}
326 
327 	qpair = nvme_transport_ctrlr_create_io_qpair(ctrlr, qid, opts);
328 	if (qpair == NULL) {
329 		SPDK_ERRLOG("nvme_transport_ctrlr_create_io_qpair() failed\n");
330 		spdk_nvme_ctrlr_free_qid(ctrlr, qid);
331 		nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
332 		return NULL;
333 	}
334 
335 	TAILQ_INSERT_TAIL(&ctrlr->active_io_qpairs, qpair, tailq);
336 
337 	nvme_ctrlr_proc_add_io_qpair(qpair);
338 
339 	nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
340 
341 	return qpair;
342 }
343 
344 int
345 spdk_nvme_ctrlr_connect_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair)
346 {
347 	int rc;
348 
349 	if (nvme_qpair_get_state(qpair) != NVME_QPAIR_DISCONNECTED) {
350 		return -EISCONN;
351 	}
352 
353 	nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
354 	rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair);
355 	nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
356 
357 	if (ctrlr->quirks & NVME_QUIRK_DELAY_AFTER_QUEUE_ALLOC) {
358 		spdk_delay_us(100);
359 	}
360 
361 	return rc;
362 }
363 
364 void
365 spdk_nvme_ctrlr_disconnect_io_qpair(struct spdk_nvme_qpair *qpair)
366 {
367 	struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
368 
369 	nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
370 	nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair);
371 	nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
372 }
373 
374 struct spdk_nvme_qpair *
375 spdk_nvme_ctrlr_alloc_io_qpair(struct spdk_nvme_ctrlr *ctrlr,
376 			       const struct spdk_nvme_io_qpair_opts *user_opts,
377 			       size_t opts_size)
378 {
379 
380 	struct spdk_nvme_qpair		*qpair;
381 	struct spdk_nvme_io_qpair_opts	opts;
382 	int				rc;
383 
384 	/*
385 	 * Get the default options, then overwrite them with the user-provided options
386 	 * up to opts_size.
387 	 *
388 	 * This allows for extensions of the opts structure without breaking
389 	 * ABI compatibility.
390 	 */
391 	spdk_nvme_ctrlr_get_default_io_qpair_opts(ctrlr, &opts, sizeof(opts));
392 	if (user_opts) {
393 		memcpy(&opts, user_opts, spdk_min(sizeof(opts), opts_size));
394 
395 		/* If user passes buffers, make sure they're big enough for the requested queue size */
396 		if (opts.sq.vaddr) {
397 			if (opts.sq.buffer_size < (opts.io_queue_size * sizeof(struct spdk_nvme_cmd))) {
398 				SPDK_ERRLOG("sq buffer size %" PRIx64 " is too small for sq size %zx\n",
399 					    opts.sq.buffer_size, (opts.io_queue_size * sizeof(struct spdk_nvme_cmd)));
400 				return NULL;
401 			}
402 		}
403 		if (opts.cq.vaddr) {
404 			if (opts.cq.buffer_size < (opts.io_queue_size * sizeof(struct spdk_nvme_cpl))) {
405 				SPDK_ERRLOG("cq buffer size %" PRIx64 " is too small for cq size %zx\n",
406 					    opts.cq.buffer_size, (opts.io_queue_size * sizeof(struct spdk_nvme_cpl)));
407 				return NULL;
408 			}
409 		}
410 	}
411 
412 	qpair = nvme_ctrlr_create_io_qpair(ctrlr, &opts);
413 
414 	if (qpair == NULL || opts.create_only == true) {
415 		return qpair;
416 	}
417 
418 	rc = spdk_nvme_ctrlr_connect_io_qpair(ctrlr, qpair);
419 	if (rc != 0) {
420 		SPDK_ERRLOG("nvme_transport_ctrlr_connect_io_qpair() failed\n");
421 		TAILQ_REMOVE(&ctrlr->active_io_qpairs, qpair, tailq);
422 		nvme_transport_ctrlr_delete_io_qpair(ctrlr, qpair);
423 		return NULL;
424 	}
425 
426 	return qpair;
427 }
428 
429 int
430 spdk_nvme_ctrlr_reconnect_io_qpair(struct spdk_nvme_qpair *qpair)
431 {
432 	struct spdk_nvme_ctrlr *ctrlr;
433 	enum nvme_qpair_state qpair_state;
434 	int rc;
435 
436 	assert(qpair != NULL);
437 	assert(nvme_qpair_is_admin_queue(qpair) == false);
438 	assert(qpair->ctrlr != NULL);
439 
440 	ctrlr = qpair->ctrlr;
441 	nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
442 	qpair_state = nvme_qpair_get_state(qpair);
443 
444 	if (ctrlr->is_removed) {
445 		rc = -ENODEV;
446 		goto out;
447 	}
448 
449 	if (ctrlr->is_resetting || qpair_state == NVME_QPAIR_DISCONNECTING) {
450 		rc = -EAGAIN;
451 		goto out;
452 	}
453 
454 	if (ctrlr->is_failed || qpair_state == NVME_QPAIR_DESTROYING) {
455 		rc = -ENXIO;
456 		goto out;
457 	}
458 
459 	if (qpair_state != NVME_QPAIR_DISCONNECTED) {
460 		rc = 0;
461 		goto out;
462 	}
463 
464 	rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair);
465 	if (rc) {
466 		rc = -EAGAIN;
467 		goto out;
468 	}
469 
470 out:
471 	nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
472 	return rc;
473 }
474 
475 spdk_nvme_qp_failure_reason
476 spdk_nvme_ctrlr_get_admin_qp_failure_reason(struct spdk_nvme_ctrlr *ctrlr)
477 {
478 	return ctrlr->adminq->transport_failure_reason;
479 }
480 
481 /*
482  * This internal function will attempt to take the controller
483  * lock before calling disconnect on a controller qpair.
484  * Functions already holding the controller lock should
485  * call nvme_transport_ctrlr_disconnect_qpair directly.
486  */
487 void
488 nvme_ctrlr_disconnect_qpair(struct spdk_nvme_qpair *qpair)
489 {
490 	struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr;
491 
492 	assert(ctrlr != NULL);
493 	nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
494 	nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair);
495 	nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
496 }
497 
498 int
499 spdk_nvme_ctrlr_free_io_qpair(struct spdk_nvme_qpair *qpair)
500 {
501 	struct spdk_nvme_ctrlr *ctrlr;
502 
503 	if (qpair == NULL) {
504 		return 0;
505 	}
506 
507 	ctrlr = qpair->ctrlr;
508 
509 	if (qpair->in_completion_context) {
510 		/*
511 		 * There are many cases where it is convenient to delete an io qpair in the context
512 		 *  of that qpair's completion routine.  To handle this properly, set a flag here
513 		 *  so that the completion routine will perform an actual delete after the context
514 		 *  unwinds.
515 		 */
516 		qpair->delete_after_completion_context = 1;
517 		return 0;
518 	}
519 
520 	if (qpair->poll_group && qpair->poll_group->in_completion_context) {
521 		/* Same as above, but in a poll group. */
522 		qpair->poll_group->num_qpairs_to_delete++;
523 		qpair->delete_after_completion_context = 1;
524 		return 0;
525 	}
526 
527 	if (qpair->poll_group) {
528 		spdk_nvme_poll_group_remove(qpair->poll_group->group, qpair);
529 	}
530 
531 	/* Do not retry. */
532 	nvme_qpair_set_state(qpair, NVME_QPAIR_DESTROYING);
533 
534 	/* In the multi-process case, a process may call this function on a foreign
535 	 * I/O qpair (i.e. one that this process did not create) when that qpairs process
536 	 * exits unexpectedly.  In that case, we must not try to abort any reqs associated
537 	 * with that qpair, since the callbacks will also be foreign to this process.
538 	 */
539 	if (qpair->active_proc == nvme_ctrlr_get_current_process(ctrlr)) {
540 		nvme_qpair_abort_reqs(qpair, 1);
541 	}
542 
543 	nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
544 
545 	nvme_ctrlr_proc_remove_io_qpair(qpair);
546 
547 	TAILQ_REMOVE(&ctrlr->active_io_qpairs, qpair, tailq);
548 	spdk_nvme_ctrlr_free_qid(ctrlr, qpair->id);
549 
550 	if (nvme_transport_ctrlr_delete_io_qpair(ctrlr, qpair)) {
551 		nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
552 		return -1;
553 	}
554 
555 	nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
556 	return 0;
557 }
558 
559 static void
560 nvme_ctrlr_construct_intel_support_log_page_list(struct spdk_nvme_ctrlr *ctrlr,
561 		struct spdk_nvme_intel_log_page_directory *log_page_directory)
562 {
563 	if (log_page_directory == NULL) {
564 		return;
565 	}
566 
567 	if (ctrlr->cdata.vid != SPDK_PCI_VID_INTEL) {
568 		return;
569 	}
570 
571 	ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY] = true;
572 
573 	if (log_page_directory->read_latency_log_len ||
574 	    (ctrlr->quirks & NVME_INTEL_QUIRK_READ_LATENCY)) {
575 		ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY] = true;
576 	}
577 	if (log_page_directory->write_latency_log_len ||
578 	    (ctrlr->quirks & NVME_INTEL_QUIRK_WRITE_LATENCY)) {
579 		ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_WRITE_CMD_LATENCY] = true;
580 	}
581 	if (log_page_directory->temperature_statistics_log_len) {
582 		ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_TEMPERATURE] = true;
583 	}
584 	if (log_page_directory->smart_log_len) {
585 		ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_SMART] = true;
586 	}
587 	if (log_page_directory->marketing_description_log_len) {
588 		ctrlr->log_page_supported[SPDK_NVME_INTEL_MARKETING_DESCRIPTION] = true;
589 	}
590 }
591 
592 static int nvme_ctrlr_set_intel_support_log_pages(struct spdk_nvme_ctrlr *ctrlr)
593 {
594 	int rc = 0;
595 	struct nvme_completion_poll_status	*status;
596 	struct spdk_nvme_intel_log_page_directory *log_page_directory;
597 
598 	log_page_directory = spdk_zmalloc(sizeof(struct spdk_nvme_intel_log_page_directory),
599 					  64, NULL, SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_DMA);
600 	if (log_page_directory == NULL) {
601 		SPDK_ERRLOG("could not allocate log_page_directory\n");
602 		return -ENXIO;
603 	}
604 
605 	status = calloc(1, sizeof(*status));
606 	if (!status) {
607 		SPDK_ERRLOG("Failed to allocate status tracker\n");
608 		spdk_free(log_page_directory);
609 		return -ENOMEM;
610 	}
611 
612 	rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr, SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY,
613 					      SPDK_NVME_GLOBAL_NS_TAG, log_page_directory,
614 					      sizeof(struct spdk_nvme_intel_log_page_directory),
615 					      0, nvme_completion_poll_cb, status);
616 	if (rc != 0) {
617 		spdk_free(log_page_directory);
618 		free(status);
619 		return rc;
620 	}
621 
622 	if (nvme_wait_for_completion_timeout(ctrlr->adminq, status,
623 					     ctrlr->opts.admin_timeout_ms * 1000)) {
624 		spdk_free(log_page_directory);
625 		SPDK_WARNLOG("Intel log pages not supported on Intel drive!\n");
626 		if (!status->timed_out) {
627 			free(status);
628 		}
629 		return 0;
630 	}
631 
632 	nvme_ctrlr_construct_intel_support_log_page_list(ctrlr, log_page_directory);
633 	spdk_free(log_page_directory);
634 	free(status);
635 	return 0;
636 }
637 
638 static int
639 nvme_ctrlr_update_ana_log_page(struct spdk_nvme_ctrlr *ctrlr)
640 {
641 	struct nvme_completion_poll_status *status;
642 	int rc;
643 
644 	status = calloc(1, sizeof(*status));
645 	if (status == NULL) {
646 		SPDK_ERRLOG("Failed to allocaate status tracker\n");
647 		return -ENOMEM;
648 	}
649 
650 	rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr, SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS,
651 					      SPDK_NVME_GLOBAL_NS_TAG, ctrlr->ana_log_page,
652 					      ctrlr->ana_log_page_size, 0,
653 					      nvme_completion_poll_cb, status);
654 	if (rc != 0) {
655 		free(status);
656 		return rc;
657 	}
658 
659 	if (nvme_wait_for_completion_robust_lock_timeout(ctrlr->adminq, status, &ctrlr->ctrlr_lock,
660 			ctrlr->opts.admin_timeout_ms * 1000)) {
661 		if (!status->timed_out) {
662 			free(status);
663 		}
664 		return -EIO;
665 	}
666 
667 	free(status);
668 	return 0;
669 }
670 
671 static int
672 nvme_ctrlr_init_ana_log_page(struct spdk_nvme_ctrlr *ctrlr)
673 {
674 	uint32_t ana_log_page_size;
675 
676 	ana_log_page_size = sizeof(struct spdk_nvme_ana_page) + ctrlr->cdata.nanagrpid *
677 			    sizeof(struct spdk_nvme_ana_group_descriptor) + ctrlr->cdata.nn *
678 			    sizeof(uint32_t);
679 
680 	ctrlr->ana_log_page = spdk_zmalloc(ana_log_page_size, 64, NULL, SPDK_ENV_SOCKET_ID_ANY,
681 					   SPDK_MALLOC_DMA);
682 	if (ctrlr->ana_log_page == NULL) {
683 		SPDK_ERRLOG("could not allocate ANA log page buffer\n");
684 		return -ENXIO;
685 	}
686 	ctrlr->ana_log_page_size = ana_log_page_size;
687 
688 	ctrlr->log_page_supported[SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS] = true;
689 
690 	return nvme_ctrlr_update_ana_log_page(ctrlr);
691 }
692 
693 static int
694 nvme_ctrlr_update_ns_ana_states(const struct spdk_nvme_ana_group_descriptor *desc,
695 				void *cb_arg)
696 {
697 	struct spdk_nvme_ctrlr *ctrlr = cb_arg;
698 	struct spdk_nvme_ns *ns;
699 	uint32_t i, nsid;
700 
701 	for (i = 0; i < desc->num_of_nsid; i++) {
702 		nsid = desc->nsid[i];
703 		if (nsid == 0 || nsid > ctrlr->cdata.nn) {
704 			continue;
705 		}
706 
707 		ns = &ctrlr->ns[nsid - 1];
708 
709 		ns->ana_group_id = desc->ana_group_id;
710 		ns->ana_state = desc->ana_state;
711 	}
712 
713 	return 0;
714 }
715 
716 int
717 nvme_ctrlr_parse_ana_log_page(struct spdk_nvme_ctrlr *ctrlr,
718 			      spdk_nvme_parse_ana_log_page_cb cb_fn, void *cb_arg)
719 {
720 	struct spdk_nvme_ana_group_descriptor *desc;
721 	uint32_t i;
722 	int rc = 0;
723 
724 	if (ctrlr->ana_log_page == NULL) {
725 		return -EINVAL;
726 	}
727 
728 	desc = (void *)((uint8_t *)ctrlr->ana_log_page + sizeof(struct spdk_nvme_ana_page));
729 
730 	for (i = 0; i < ctrlr->ana_log_page->num_ana_group_desc; i++) {
731 		rc = cb_fn(desc, cb_arg);
732 		if (rc != 0) {
733 			break;
734 		}
735 		desc = (void *)((uint8_t *)desc + sizeof(struct spdk_nvme_ana_group_descriptor) +
736 				desc->num_of_nsid * sizeof(uint32_t));
737 	}
738 
739 	return rc;
740 }
741 
742 static int
743 nvme_ctrlr_set_supported_log_pages(struct spdk_nvme_ctrlr *ctrlr)
744 {
745 	int	rc = 0;
746 
747 	memset(ctrlr->log_page_supported, 0, sizeof(ctrlr->log_page_supported));
748 	/* Mandatory pages */
749 	ctrlr->log_page_supported[SPDK_NVME_LOG_ERROR] = true;
750 	ctrlr->log_page_supported[SPDK_NVME_LOG_HEALTH_INFORMATION] = true;
751 	ctrlr->log_page_supported[SPDK_NVME_LOG_FIRMWARE_SLOT] = true;
752 	if (ctrlr->cdata.lpa.celp) {
753 		ctrlr->log_page_supported[SPDK_NVME_LOG_COMMAND_EFFECTS_LOG] = true;
754 	}
755 	if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL && !(ctrlr->quirks & NVME_INTEL_QUIRK_NO_LOG_PAGES)) {
756 		rc = nvme_ctrlr_set_intel_support_log_pages(ctrlr);
757 		if (rc != 0) {
758 			goto out;
759 		}
760 	}
761 	if (ctrlr->cdata.cmic.ana_reporting) {
762 		rc = nvme_ctrlr_init_ana_log_page(ctrlr);
763 		if (rc == 0) {
764 			nvme_ctrlr_parse_ana_log_page(ctrlr, nvme_ctrlr_update_ns_ana_states,
765 						      ctrlr);
766 		}
767 	}
768 
769 out:
770 	return rc;
771 }
772 
773 static void
774 nvme_ctrlr_set_intel_supported_features(struct spdk_nvme_ctrlr *ctrlr)
775 {
776 	ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_MAX_LBA] = true;
777 	ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_NATIVE_MAX_LBA] = true;
778 	ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_POWER_GOVERNOR_SETTING] = true;
779 	ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_SMBUS_ADDRESS] = true;
780 	ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_LED_PATTERN] = true;
781 	ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_RESET_TIMED_WORKLOAD_COUNTERS] = true;
782 	ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_LATENCY_TRACKING] = true;
783 }
784 
785 static void
786 nvme_ctrlr_set_arbitration_feature(struct spdk_nvme_ctrlr *ctrlr)
787 {
788 	uint32_t cdw11;
789 	struct nvme_completion_poll_status *status;
790 
791 	if (ctrlr->opts.arbitration_burst == 0) {
792 		return;
793 	}
794 
795 	if (ctrlr->opts.arbitration_burst > 7) {
796 		SPDK_WARNLOG("Valid arbitration burst values is from 0-7\n");
797 		return;
798 	}
799 
800 	status = calloc(1, sizeof(*status));
801 	if (!status) {
802 		SPDK_ERRLOG("Failed to allocate status tracker\n");
803 		return;
804 	}
805 
806 	cdw11 = ctrlr->opts.arbitration_burst;
807 
808 	if (spdk_nvme_ctrlr_get_flags(ctrlr) & SPDK_NVME_CTRLR_WRR_SUPPORTED) {
809 		cdw11 |= (uint32_t)ctrlr->opts.low_priority_weight << 8;
810 		cdw11 |= (uint32_t)ctrlr->opts.medium_priority_weight << 16;
811 		cdw11 |= (uint32_t)ctrlr->opts.high_priority_weight << 24;
812 	}
813 
814 	if (spdk_nvme_ctrlr_cmd_set_feature(ctrlr, SPDK_NVME_FEAT_ARBITRATION,
815 					    cdw11, 0, NULL, 0,
816 					    nvme_completion_poll_cb, status) < 0) {
817 		SPDK_ERRLOG("Set arbitration feature failed\n");
818 		free(status);
819 		return;
820 	}
821 
822 	if (nvme_wait_for_completion_timeout(ctrlr->adminq, status,
823 					     ctrlr->opts.admin_timeout_ms * 1000)) {
824 		SPDK_ERRLOG("Timeout to set arbitration feature\n");
825 	}
826 
827 	if (!status->timed_out) {
828 		free(status);
829 	}
830 }
831 
832 static void
833 nvme_ctrlr_set_supported_features(struct spdk_nvme_ctrlr *ctrlr)
834 {
835 	memset(ctrlr->feature_supported, 0, sizeof(ctrlr->feature_supported));
836 	/* Mandatory features */
837 	ctrlr->feature_supported[SPDK_NVME_FEAT_ARBITRATION] = true;
838 	ctrlr->feature_supported[SPDK_NVME_FEAT_POWER_MANAGEMENT] = true;
839 	ctrlr->feature_supported[SPDK_NVME_FEAT_TEMPERATURE_THRESHOLD] = true;
840 	ctrlr->feature_supported[SPDK_NVME_FEAT_ERROR_RECOVERY] = true;
841 	ctrlr->feature_supported[SPDK_NVME_FEAT_NUMBER_OF_QUEUES] = true;
842 	ctrlr->feature_supported[SPDK_NVME_FEAT_INTERRUPT_COALESCING] = true;
843 	ctrlr->feature_supported[SPDK_NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION] = true;
844 	ctrlr->feature_supported[SPDK_NVME_FEAT_WRITE_ATOMICITY] = true;
845 	ctrlr->feature_supported[SPDK_NVME_FEAT_ASYNC_EVENT_CONFIGURATION] = true;
846 	/* Optional features */
847 	if (ctrlr->cdata.vwc.present) {
848 		ctrlr->feature_supported[SPDK_NVME_FEAT_VOLATILE_WRITE_CACHE] = true;
849 	}
850 	if (ctrlr->cdata.apsta.supported) {
851 		ctrlr->feature_supported[SPDK_NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION] = true;
852 	}
853 	if (ctrlr->cdata.hmpre) {
854 		ctrlr->feature_supported[SPDK_NVME_FEAT_HOST_MEM_BUFFER] = true;
855 	}
856 	if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL) {
857 		nvme_ctrlr_set_intel_supported_features(ctrlr);
858 	}
859 
860 	nvme_ctrlr_set_arbitration_feature(ctrlr);
861 }
862 
863 bool
864 spdk_nvme_ctrlr_is_failed(struct spdk_nvme_ctrlr *ctrlr)
865 {
866 	return ctrlr->is_failed;
867 }
868 
869 void
870 nvme_ctrlr_fail(struct spdk_nvme_ctrlr *ctrlr, bool hot_remove)
871 {
872 	/*
873 	 * Set the flag here and leave the work failure of qpairs to
874 	 * spdk_nvme_qpair_process_completions().
875 	 */
876 	if (hot_remove) {
877 		ctrlr->is_removed = true;
878 	}
879 
880 	if (ctrlr->is_failed) {
881 		SPDK_NOTICELOG("ctrlr %s is already in failed state\n", ctrlr->trid.traddr);
882 		return;
883 	}
884 
885 	ctrlr->is_failed = true;
886 	nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq);
887 	SPDK_ERRLOG("ctrlr %s in failed state.\n", ctrlr->trid.traddr);
888 }
889 
890 /**
891  * This public API function will try to take the controller lock.
892  * Any private functions being called from a thread already holding
893  * the ctrlr lock should call nvme_ctrlr_fail directly.
894  */
895 void
896 spdk_nvme_ctrlr_fail(struct spdk_nvme_ctrlr *ctrlr)
897 {
898 	nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
899 	nvme_ctrlr_fail(ctrlr, false);
900 	nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
901 }
902 
903 static void
904 nvme_ctrlr_shutdown_async(struct spdk_nvme_ctrlr *ctrlr,
905 			  struct nvme_ctrlr_detach_ctx *ctx)
906 {
907 	union spdk_nvme_cc_register	cc;
908 
909 	if (ctrlr->is_removed) {
910 		ctx->shutdown_complete = true;
911 		return;
912 	}
913 
914 	if (nvme_ctrlr_get_cc(ctrlr, &cc)) {
915 		SPDK_ERRLOG("ctrlr %s get_cc() failed\n", ctrlr->trid.traddr);
916 		ctx->shutdown_complete = true;
917 		return;
918 	}
919 
920 	cc.bits.shn = SPDK_NVME_SHN_NORMAL;
921 
922 	if (nvme_ctrlr_set_cc(ctrlr, &cc)) {
923 		SPDK_ERRLOG("ctrlr %s set_cc() failed\n", ctrlr->trid.traddr);
924 		ctx->shutdown_complete = true;
925 		return;
926 	}
927 
928 	/*
929 	 * The NVMe specification defines RTD3E to be the time between
930 	 *  setting SHN = 1 until the controller will set SHST = 10b.
931 	 * If the device doesn't report RTD3 entry latency, or if it
932 	 *  reports RTD3 entry latency less than 10 seconds, pick
933 	 *  10 seconds as a reasonable amount of time to
934 	 *  wait before proceeding.
935 	 */
936 	SPDK_DEBUGLOG(nvme, "RTD3E = %" PRIu32 " us\n", ctrlr->cdata.rtd3e);
937 	ctx->shutdown_timeout_ms = SPDK_CEIL_DIV(ctrlr->cdata.rtd3e, 1000);
938 	ctx->shutdown_timeout_ms = spdk_max(ctx->shutdown_timeout_ms, 10000);
939 	SPDK_DEBUGLOG(nvme, "shutdown timeout = %" PRIu32 " ms\n",
940 		      ctx->shutdown_timeout_ms);
941 
942 	ctx->shutdown_start_tsc = spdk_get_ticks();
943 }
944 
945 static int
946 nvme_ctrlr_shutdown_poll_async(struct spdk_nvme_ctrlr *ctrlr,
947 			       struct nvme_ctrlr_detach_ctx *ctx)
948 {
949 	union spdk_nvme_csts_register	csts;
950 	uint32_t			ms_waited;
951 
952 	ms_waited = (spdk_get_ticks() - ctx->shutdown_start_tsc) * 1000 / spdk_get_ticks_hz();
953 
954 	if (nvme_ctrlr_get_csts(ctrlr, &csts)) {
955 		SPDK_ERRLOG("ctrlr %s get_csts() failed\n", ctrlr->trid.traddr);
956 		return -EIO;
957 	}
958 
959 	if (csts.bits.shst == SPDK_NVME_SHST_COMPLETE) {
960 		SPDK_DEBUGLOG(nvme, "ctrlr %s shutdown complete in %u milliseconds\n",
961 			      ctrlr->trid.traddr, ms_waited);
962 		return 0;
963 	}
964 
965 	if (ms_waited < ctx->shutdown_timeout_ms) {
966 		return -EAGAIN;
967 	}
968 
969 	SPDK_ERRLOG("ctrlr %s did not shutdown within %u milliseconds\n",
970 		    ctrlr->trid.traddr, ctx->shutdown_timeout_ms);
971 	if (ctrlr->quirks & NVME_QUIRK_SHST_COMPLETE) {
972 		SPDK_ERRLOG("likely due to shutdown handling in the VMWare emulated NVMe SSD\n");
973 	}
974 
975 	return 0;
976 }
977 
978 static int
979 nvme_ctrlr_enable(struct spdk_nvme_ctrlr *ctrlr)
980 {
981 	union spdk_nvme_cc_register	cc;
982 	int				rc;
983 
984 	rc = nvme_transport_ctrlr_enable(ctrlr);
985 	if (rc != 0) {
986 		SPDK_ERRLOG("transport ctrlr_enable failed\n");
987 		return rc;
988 	}
989 
990 	if (nvme_ctrlr_get_cc(ctrlr, &cc)) {
991 		SPDK_ERRLOG("get_cc() failed\n");
992 		return -EIO;
993 	}
994 
995 	if (cc.bits.en != 0) {
996 		SPDK_ERRLOG("called with CC.EN = 1\n");
997 		return -EINVAL;
998 	}
999 
1000 	cc.bits.en = 1;
1001 	cc.bits.css = 0;
1002 	cc.bits.shn = 0;
1003 	cc.bits.iosqes = 6; /* SQ entry size == 64 == 2^6 */
1004 	cc.bits.iocqes = 4; /* CQ entry size == 16 == 2^4 */
1005 
1006 	/* Page size is 2 ^ (12 + mps). */
1007 	cc.bits.mps = spdk_u32log2(ctrlr->page_size) - 12;
1008 
1009 	/*
1010 	 * Since NVMe 1.0, a controller should have at least one bit set in CAP.CSS.
1011 	 * A controller that does not have any bit set in CAP.CSS is not spec compliant.
1012 	 * Try to support such a controller regardless.
1013 	 */
1014 	if (ctrlr->cap.bits.css == 0) {
1015 		SPDK_INFOLOG(nvme,
1016 			     "Drive reports no command sets supported. Assuming NVM is supported.\n");
1017 		ctrlr->cap.bits.css = SPDK_NVME_CAP_CSS_NVM;
1018 	}
1019 
1020 	/*
1021 	 * If the user did not explicitly request a command set, or supplied a value larger than
1022 	 * what can be saved in CC.CSS, use the most reasonable default.
1023 	 */
1024 	if (ctrlr->opts.command_set >= CHAR_BIT) {
1025 		if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS) {
1026 			ctrlr->opts.command_set = SPDK_NVME_CC_CSS_IOCS;
1027 		} else if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_NVM) {
1028 			ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM;
1029 		} else if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_NOIO) {
1030 			ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NOIO;
1031 		} else {
1032 			/* Invalid supported bits detected, falling back to NVM. */
1033 			ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM;
1034 		}
1035 	}
1036 
1037 	/* Verify that the selected command set is supported by the controller. */
1038 	if (!(ctrlr->cap.bits.css & (1u << ctrlr->opts.command_set))) {
1039 		SPDK_DEBUGLOG(nvme, "Requested I/O command set %u but supported mask is 0x%x\n",
1040 			      ctrlr->opts.command_set, ctrlr->cap.bits.css);
1041 		SPDK_DEBUGLOG(nvme, "Falling back to NVM. Assuming NVM is supported.\n");
1042 		ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM;
1043 	}
1044 
1045 	cc.bits.css = ctrlr->opts.command_set;
1046 
1047 	switch (ctrlr->opts.arb_mechanism) {
1048 	case SPDK_NVME_CC_AMS_RR:
1049 		break;
1050 	case SPDK_NVME_CC_AMS_WRR:
1051 		if (SPDK_NVME_CAP_AMS_WRR & ctrlr->cap.bits.ams) {
1052 			break;
1053 		}
1054 		return -EINVAL;
1055 	case SPDK_NVME_CC_AMS_VS:
1056 		if (SPDK_NVME_CAP_AMS_VS & ctrlr->cap.bits.ams) {
1057 			break;
1058 		}
1059 		return -EINVAL;
1060 	default:
1061 		return -EINVAL;
1062 	}
1063 
1064 	cc.bits.ams = ctrlr->opts.arb_mechanism;
1065 
1066 	if (nvme_ctrlr_set_cc(ctrlr, &cc)) {
1067 		SPDK_ERRLOG("set_cc() failed\n");
1068 		return -EIO;
1069 	}
1070 
1071 	return 0;
1072 }
1073 
1074 static int
1075 nvme_ctrlr_disable(struct spdk_nvme_ctrlr *ctrlr)
1076 {
1077 	union spdk_nvme_cc_register	cc;
1078 
1079 	if (nvme_ctrlr_get_cc(ctrlr, &cc)) {
1080 		SPDK_ERRLOG("get_cc() failed\n");
1081 		return -EIO;
1082 	}
1083 
1084 	if (cc.bits.en == 0) {
1085 		return 0;
1086 	}
1087 
1088 	cc.bits.en = 0;
1089 
1090 	if (nvme_ctrlr_set_cc(ctrlr, &cc)) {
1091 		SPDK_ERRLOG("set_cc() failed\n");
1092 		return -EIO;
1093 	}
1094 
1095 	return 0;
1096 }
1097 
1098 #ifdef DEBUG
1099 static const char *
1100 nvme_ctrlr_state_string(enum nvme_ctrlr_state state)
1101 {
1102 	switch (state) {
1103 	case NVME_CTRLR_STATE_INIT_DELAY:
1104 		return "delay init";
1105 	case NVME_CTRLR_STATE_INIT:
1106 		return "init";
1107 	case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1:
1108 		return "disable and wait for CSTS.RDY = 1";
1109 	case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0:
1110 		return "disable and wait for CSTS.RDY = 0";
1111 	case NVME_CTRLR_STATE_ENABLE:
1112 		return "enable controller by writing CC.EN = 1";
1113 	case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1:
1114 		return "wait for CSTS.RDY = 1";
1115 	case NVME_CTRLR_STATE_RESET_ADMIN_QUEUE:
1116 		return "reset admin queue";
1117 	case NVME_CTRLR_STATE_IDENTIFY:
1118 		return "identify controller";
1119 	case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY:
1120 		return "wait for identify controller";
1121 	case NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC:
1122 		return "identify controller iocs specific";
1123 	case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC:
1124 		return "wait for identify controller iocs specific";
1125 	case NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG:
1126 		return "get zns cmd and effects log page";
1127 	case NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG:
1128 		return "wait for get zns cmd and effects log page";
1129 	case NVME_CTRLR_STATE_SET_NUM_QUEUES:
1130 		return "set number of queues";
1131 	case NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES:
1132 		return "wait for set number of queues";
1133 	case NVME_CTRLR_STATE_CONSTRUCT_NS:
1134 		return "construct namespaces";
1135 	case NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS:
1136 		return "identify active ns";
1137 	case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS:
1138 		return "wait for identify active ns";
1139 	case NVME_CTRLR_STATE_IDENTIFY_NS:
1140 		return "identify ns";
1141 	case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS:
1142 		return "wait for identify ns";
1143 	case NVME_CTRLR_STATE_IDENTIFY_ID_DESCS:
1144 		return "identify namespace id descriptors";
1145 	case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS:
1146 		return "wait for identify namespace id descriptors";
1147 	case NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC:
1148 		return "identify ns iocs specific";
1149 	case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC:
1150 		return "wait for identify ns iocs specific";
1151 	case NVME_CTRLR_STATE_CONFIGURE_AER:
1152 		return "configure AER";
1153 	case NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER:
1154 		return "wait for configure aer";
1155 	case NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES:
1156 		return "set supported log pages";
1157 	case NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES:
1158 		return "set supported features";
1159 	case NVME_CTRLR_STATE_SET_DB_BUF_CFG:
1160 		return "set doorbell buffer config";
1161 	case NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG:
1162 		return "wait for doorbell buffer config";
1163 	case NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT:
1164 		return "set keep alive timeout";
1165 	case NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT:
1166 		return "wait for set keep alive timeout";
1167 	case NVME_CTRLR_STATE_SET_HOST_ID:
1168 		return "set host ID";
1169 	case NVME_CTRLR_STATE_WAIT_FOR_HOST_ID:
1170 		return "wait for set host ID";
1171 	case NVME_CTRLR_STATE_READY:
1172 		return "ready";
1173 	case NVME_CTRLR_STATE_ERROR:
1174 		return "error";
1175 	}
1176 	return "unknown";
1177 };
1178 #endif /* DEBUG */
1179 
1180 static void
1181 nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state,
1182 		     uint64_t timeout_in_ms)
1183 {
1184 	uint64_t ticks_per_ms, timeout_in_ticks, now_ticks;
1185 
1186 	ctrlr->state = state;
1187 	if (timeout_in_ms == NVME_TIMEOUT_INFINITE) {
1188 		goto inf;
1189 	}
1190 
1191 	ticks_per_ms = spdk_get_ticks_hz() / 1000;
1192 	if (timeout_in_ms > UINT64_MAX / ticks_per_ms) {
1193 		SPDK_ERRLOG("Specified timeout would cause integer overflow. Defaulting to no timeout.\n");
1194 		goto inf;
1195 	}
1196 
1197 	now_ticks = spdk_get_ticks();
1198 	timeout_in_ticks = timeout_in_ms * ticks_per_ms;
1199 	if (timeout_in_ticks > UINT64_MAX - now_ticks) {
1200 		SPDK_ERRLOG("Specified timeout would cause integer overflow. Defaulting to no timeout.\n");
1201 		goto inf;
1202 	}
1203 
1204 	ctrlr->state_timeout_tsc = timeout_in_ticks + now_ticks;
1205 	SPDK_DEBUGLOG(nvme, "setting state to %s (timeout %" PRIu64 " ms)\n",
1206 		      nvme_ctrlr_state_string(ctrlr->state), timeout_in_ms);
1207 	return;
1208 inf:
1209 	SPDK_DEBUGLOG(nvme, "setting state to %s (no timeout)\n",
1210 		      nvme_ctrlr_state_string(ctrlr->state));
1211 	ctrlr->state_timeout_tsc = NVME_TIMEOUT_INFINITE;
1212 }
1213 
1214 static void
1215 nvme_ctrlr_free_zns_specific_data(struct spdk_nvme_ctrlr *ctrlr)
1216 {
1217 	spdk_free(ctrlr->cdata_zns);
1218 	ctrlr->cdata_zns = NULL;
1219 }
1220 
1221 static void
1222 nvme_ctrlr_free_iocs_specific_data(struct spdk_nvme_ctrlr *ctrlr)
1223 {
1224 	nvme_ctrlr_free_zns_specific_data(ctrlr);
1225 }
1226 
1227 static void
1228 nvme_ctrlr_free_doorbell_buffer(struct spdk_nvme_ctrlr *ctrlr)
1229 {
1230 	if (ctrlr->shadow_doorbell) {
1231 		spdk_free(ctrlr->shadow_doorbell);
1232 		ctrlr->shadow_doorbell = NULL;
1233 	}
1234 
1235 	if (ctrlr->eventidx) {
1236 		spdk_free(ctrlr->eventidx);
1237 		ctrlr->eventidx = NULL;
1238 	}
1239 }
1240 
1241 static void
1242 nvme_ctrlr_set_doorbell_buffer_config_done(void *arg, const struct spdk_nvme_cpl *cpl)
1243 {
1244 	struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
1245 
1246 	if (spdk_nvme_cpl_is_error(cpl)) {
1247 		SPDK_WARNLOG("Doorbell buffer config failed\n");
1248 	} else {
1249 		SPDK_INFOLOG(nvme, "NVMe controller: %s doorbell buffer config enabled\n",
1250 			     ctrlr->trid.traddr);
1251 	}
1252 	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT,
1253 			     ctrlr->opts.admin_timeout_ms);
1254 }
1255 
1256 static int
1257 nvme_ctrlr_set_doorbell_buffer_config(struct spdk_nvme_ctrlr *ctrlr)
1258 {
1259 	int rc = 0;
1260 	uint64_t prp1, prp2, len;
1261 
1262 	if (!ctrlr->cdata.oacs.doorbell_buffer_config) {
1263 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT,
1264 				     ctrlr->opts.admin_timeout_ms);
1265 		return 0;
1266 	}
1267 
1268 	if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) {
1269 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT,
1270 				     ctrlr->opts.admin_timeout_ms);
1271 		return 0;
1272 	}
1273 
1274 	/* only 1 page size for doorbell buffer */
1275 	ctrlr->shadow_doorbell = spdk_zmalloc(ctrlr->page_size, ctrlr->page_size,
1276 					      NULL, SPDK_ENV_LCORE_ID_ANY,
1277 					      SPDK_MALLOC_DMA | SPDK_MALLOC_SHARE);
1278 	if (ctrlr->shadow_doorbell == NULL) {
1279 		rc = -ENOMEM;
1280 		goto error;
1281 	}
1282 
1283 	len = ctrlr->page_size;
1284 	prp1 = spdk_vtophys(ctrlr->shadow_doorbell, &len);
1285 	if (prp1 == SPDK_VTOPHYS_ERROR || len != ctrlr->page_size) {
1286 		rc = -EFAULT;
1287 		goto error;
1288 	}
1289 
1290 	ctrlr->eventidx = spdk_zmalloc(ctrlr->page_size, ctrlr->page_size,
1291 				       NULL, SPDK_ENV_LCORE_ID_ANY,
1292 				       SPDK_MALLOC_DMA | SPDK_MALLOC_SHARE);
1293 	if (ctrlr->eventidx == NULL) {
1294 		rc = -ENOMEM;
1295 		goto error;
1296 	}
1297 
1298 	len = ctrlr->page_size;
1299 	prp2 = spdk_vtophys(ctrlr->eventidx, &len);
1300 	if (prp2 == SPDK_VTOPHYS_ERROR || len != ctrlr->page_size) {
1301 		rc = -EFAULT;
1302 		goto error;
1303 	}
1304 
1305 	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG,
1306 			     ctrlr->opts.admin_timeout_ms);
1307 
1308 	rc = nvme_ctrlr_cmd_doorbell_buffer_config(ctrlr, prp1, prp2,
1309 			nvme_ctrlr_set_doorbell_buffer_config_done, ctrlr);
1310 	if (rc != 0) {
1311 		goto error;
1312 	}
1313 
1314 	return 0;
1315 
1316 error:
1317 	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1318 	nvme_ctrlr_free_doorbell_buffer(ctrlr);
1319 	return rc;
1320 }
1321 
1322 static void
1323 nvme_ctrlr_abort_queued_aborts(struct spdk_nvme_ctrlr *ctrlr)
1324 {
1325 	struct nvme_request	*req, *tmp;
1326 	struct spdk_nvme_cpl	cpl = {};
1327 
1328 	cpl.status.sc = SPDK_NVME_SC_ABORTED_SQ_DELETION;
1329 	cpl.status.sct = SPDK_NVME_SCT_GENERIC;
1330 
1331 	STAILQ_FOREACH_SAFE(req, &ctrlr->queued_aborts, stailq, tmp) {
1332 		STAILQ_REMOVE_HEAD(&ctrlr->queued_aborts, stailq);
1333 
1334 		nvme_complete_request(req->cb_fn, req->cb_arg, req->qpair, req, &cpl);
1335 		nvme_free_request(req);
1336 	}
1337 }
1338 
1339 int
1340 spdk_nvme_ctrlr_reset(struct spdk_nvme_ctrlr *ctrlr)
1341 {
1342 	int rc = 0, rc_tmp = 0;
1343 	struct spdk_nvme_qpair	*qpair;
1344 
1345 	nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
1346 
1347 	if (ctrlr->is_resetting || ctrlr->is_removed) {
1348 		/*
1349 		 * Controller is already resetting or has been removed. Return
1350 		 *  immediately since there is no need to kick off another
1351 		 *  reset in these cases.
1352 		 */
1353 		nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
1354 		return ctrlr->is_resetting ? 0 : -ENXIO;
1355 	}
1356 
1357 	ctrlr->is_resetting = true;
1358 	ctrlr->is_failed = false;
1359 
1360 	SPDK_NOTICELOG("resetting controller\n");
1361 
1362 	/* Abort all of the queued abort requests */
1363 	nvme_ctrlr_abort_queued_aborts(ctrlr);
1364 
1365 	nvme_transport_admin_qpair_abort_aers(ctrlr->adminq);
1366 
1367 	/* Disable all queues before disabling the controller hardware. */
1368 	TAILQ_FOREACH(qpair, &ctrlr->active_io_qpairs, tailq) {
1369 		qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL;
1370 	}
1371 
1372 	ctrlr->adminq->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL;
1373 	nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq);
1374 	rc = nvme_transport_ctrlr_connect_qpair(ctrlr, ctrlr->adminq);
1375 	if (rc != 0) {
1376 		SPDK_ERRLOG("Controller reinitialization failed.\n");
1377 		goto out;
1378 	}
1379 
1380 	/* Doorbell buffer config is invalid during reset */
1381 	nvme_ctrlr_free_doorbell_buffer(ctrlr);
1382 
1383 	/* I/O Command Set Specific Identify Controller data is invalidated during reset */
1384 	nvme_ctrlr_free_iocs_specific_data(ctrlr);
1385 
1386 	spdk_bit_array_free(&ctrlr->free_io_qids);
1387 
1388 	/* Set the state back to INIT to cause a full hardware reset. */
1389 	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE);
1390 
1391 	nvme_qpair_set_state(ctrlr->adminq, NVME_QPAIR_ENABLED);
1392 	while (ctrlr->state != NVME_CTRLR_STATE_READY) {
1393 		if (nvme_ctrlr_process_init(ctrlr) != 0) {
1394 			SPDK_ERRLOG("controller reinitialization failed\n");
1395 			rc = -1;
1396 			break;
1397 		}
1398 	}
1399 
1400 	/*
1401 	 * For PCIe controllers, the memory locations of the transport qpair
1402 	 * don't change when the controller is reset. They simply need to be
1403 	 * re-enabled with admin commands to the controller. For fabric
1404 	 * controllers we need to disconnect and reconnect the qpair on its
1405 	 * own thread outside of the context of the reset.
1406 	 */
1407 	if (rc == 0 && ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) {
1408 		/* Reinitialize qpairs */
1409 		TAILQ_FOREACH(qpair, &ctrlr->active_io_qpairs, tailq) {
1410 			assert(spdk_bit_array_get(ctrlr->free_io_qids, qpair->id));
1411 			spdk_bit_array_clear(ctrlr->free_io_qids, qpair->id);
1412 			rc_tmp = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair);
1413 			if (rc_tmp != 0) {
1414 				rc = rc_tmp;
1415 				qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL;
1416 				continue;
1417 			}
1418 		}
1419 	}
1420 
1421 out:
1422 	if (rc) {
1423 		nvme_ctrlr_fail(ctrlr, false);
1424 	}
1425 	ctrlr->is_resetting = false;
1426 
1427 	nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
1428 
1429 	if (!ctrlr->cdata.oaes.ns_attribute_notices) {
1430 		/*
1431 		 * If controller doesn't support ns_attribute_notices and
1432 		 * namespace attributes change (e.g. number of namespaces)
1433 		 * we need to update system handling device reset.
1434 		 */
1435 		nvme_io_msg_ctrlr_update(ctrlr);
1436 	}
1437 
1438 	return rc;
1439 }
1440 
1441 int
1442 spdk_nvme_ctrlr_reset_subsystem(struct spdk_nvme_ctrlr *ctrlr)
1443 {
1444 	union spdk_nvme_cap_register cap;
1445 	int rc = 0;
1446 
1447 	cap = spdk_nvme_ctrlr_get_regs_cap(ctrlr);
1448 	if (cap.bits.nssrs == 0) {
1449 		SPDK_WARNLOG("subsystem reset is not supported\n");
1450 		return -ENOTSUP;
1451 	}
1452 
1453 	SPDK_NOTICELOG("resetting subsystem\n");
1454 	nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
1455 	ctrlr->is_resetting = true;
1456 	rc = nvme_ctrlr_set_nssr(ctrlr, SPDK_NVME_NSSR_VALUE);
1457 	ctrlr->is_resetting = false;
1458 
1459 	nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
1460 	/*
1461 	 * No more cleanup at this point like in the ctrlr reset. A subsystem reset will cause
1462 	 * a hot remove for PCIe transport. The hot remove handling does all the necessary ctrlr cleanup.
1463 	 */
1464 	return rc;
1465 }
1466 
1467 int
1468 spdk_nvme_ctrlr_set_trid(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_transport_id *trid)
1469 {
1470 	int rc = 0;
1471 
1472 	nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
1473 
1474 	if (ctrlr->is_failed == false) {
1475 		rc = -EPERM;
1476 		goto out;
1477 	}
1478 
1479 	if (trid->trtype != ctrlr->trid.trtype) {
1480 		rc = -EINVAL;
1481 		goto out;
1482 	}
1483 
1484 	if (strncmp(trid->subnqn, ctrlr->trid.subnqn, SPDK_NVMF_NQN_MAX_LEN)) {
1485 		rc = -EINVAL;
1486 		goto out;
1487 	}
1488 
1489 	ctrlr->trid = *trid;
1490 
1491 out:
1492 	nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
1493 	return rc;
1494 }
1495 
1496 void
1497 spdk_nvme_ctrlr_set_remove_cb(struct spdk_nvme_ctrlr *ctrlr,
1498 			      spdk_nvme_remove_cb remove_cb, void *remove_ctx)
1499 {
1500 	if (!spdk_process_is_primary()) {
1501 		return;
1502 	}
1503 
1504 	nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
1505 	ctrlr->remove_cb = remove_cb;
1506 	ctrlr->cb_ctx = remove_ctx;
1507 	nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
1508 }
1509 
1510 static void
1511 nvme_ctrlr_identify_done(void *arg, const struct spdk_nvme_cpl *cpl)
1512 {
1513 	struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
1514 
1515 	if (spdk_nvme_cpl_is_error(cpl)) {
1516 		SPDK_ERRLOG("nvme_identify_controller failed!\n");
1517 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1518 		return;
1519 	}
1520 
1521 	/*
1522 	 * Use MDTS to ensure our default max_xfer_size doesn't exceed what the
1523 	 *  controller supports.
1524 	 */
1525 	ctrlr->max_xfer_size = nvme_transport_ctrlr_get_max_xfer_size(ctrlr);
1526 	SPDK_DEBUGLOG(nvme, "transport max_xfer_size %u\n", ctrlr->max_xfer_size);
1527 	if (ctrlr->cdata.mdts > 0) {
1528 		ctrlr->max_xfer_size = spdk_min(ctrlr->max_xfer_size,
1529 						ctrlr->min_page_size * (1 << ctrlr->cdata.mdts));
1530 		SPDK_DEBUGLOG(nvme, "MDTS max_xfer_size %u\n", ctrlr->max_xfer_size);
1531 	}
1532 
1533 	SPDK_DEBUGLOG(nvme, "CNTLID 0x%04" PRIx16 "\n", ctrlr->cdata.cntlid);
1534 	if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) {
1535 		ctrlr->cntlid = ctrlr->cdata.cntlid;
1536 	} else {
1537 		/*
1538 		 * Fabrics controllers should already have CNTLID from the Connect command.
1539 		 *
1540 		 * If CNTLID from Connect doesn't match CNTLID in the Identify Controller data,
1541 		 * trust the one from Connect.
1542 		 */
1543 		if (ctrlr->cntlid != ctrlr->cdata.cntlid) {
1544 			SPDK_DEBUGLOG(nvme,
1545 				      "Identify CNTLID 0x%04" PRIx16 " != Connect CNTLID 0x%04" PRIx16 "\n",
1546 				      ctrlr->cdata.cntlid, ctrlr->cntlid);
1547 		}
1548 	}
1549 
1550 	if (ctrlr->cdata.sgls.supported) {
1551 		assert(ctrlr->cdata.sgls.supported != 0x3);
1552 		ctrlr->flags |= SPDK_NVME_CTRLR_SGL_SUPPORTED;
1553 		if (ctrlr->cdata.sgls.supported == 0x2) {
1554 			ctrlr->flags |= SPDK_NVME_CTRLR_SGL_REQUIRES_DWORD_ALIGNMENT;
1555 		}
1556 		/*
1557 		 * Use MSDBD to ensure our max_sges doesn't exceed what the
1558 		 *  controller supports.
1559 		 */
1560 		ctrlr->max_sges = nvme_transport_ctrlr_get_max_sges(ctrlr);
1561 		if (ctrlr->cdata.nvmf_specific.msdbd != 0) {
1562 			ctrlr->max_sges = spdk_min(ctrlr->cdata.nvmf_specific.msdbd, ctrlr->max_sges);
1563 		} else {
1564 			/* A value 0 indicates no limit. */
1565 		}
1566 		SPDK_DEBUGLOG(nvme, "transport max_sges %u\n", ctrlr->max_sges);
1567 	}
1568 
1569 	if (ctrlr->cdata.oacs.security && !(ctrlr->quirks & NVME_QUIRK_OACS_SECURITY)) {
1570 		ctrlr->flags |= SPDK_NVME_CTRLR_SECURITY_SEND_RECV_SUPPORTED;
1571 	}
1572 
1573 	if (ctrlr->cdata.oacs.directives) {
1574 		ctrlr->flags |= SPDK_NVME_CTRLR_DIRECTIVES_SUPPORTED;
1575 	}
1576 
1577 	SPDK_DEBUGLOG(nvme, "fuses compare and write: %d\n", ctrlr->cdata.fuses.compare_and_write);
1578 	if (ctrlr->cdata.fuses.compare_and_write) {
1579 		ctrlr->flags |= SPDK_NVME_CTRLR_COMPARE_AND_WRITE_SUPPORTED;
1580 	}
1581 
1582 	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC,
1583 			     ctrlr->opts.admin_timeout_ms);
1584 }
1585 
1586 static int
1587 nvme_ctrlr_identify(struct spdk_nvme_ctrlr *ctrlr)
1588 {
1589 	int	rc;
1590 
1591 	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY,
1592 			     ctrlr->opts.admin_timeout_ms);
1593 
1594 	rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_CTRLR, 0, 0, 0,
1595 				     &ctrlr->cdata, sizeof(ctrlr->cdata),
1596 				     nvme_ctrlr_identify_done, ctrlr);
1597 	if (rc != 0) {
1598 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1599 		return rc;
1600 	}
1601 
1602 	return 0;
1603 }
1604 
1605 static void
1606 nvme_ctrlr_get_zns_cmd_and_effects_log_done(void *arg, const struct spdk_nvme_cpl *cpl)
1607 {
1608 	struct spdk_nvme_cmds_and_effect_log_page *log_page;
1609 	struct spdk_nvme_ctrlr *ctrlr = arg;
1610 
1611 	if (spdk_nvme_cpl_is_error(cpl)) {
1612 		SPDK_ERRLOG("nvme_ctrlr_get_zns_cmd_and_effects_log failed!\n");
1613 		spdk_free(ctrlr->tmp_ptr);
1614 		ctrlr->tmp_ptr = NULL;
1615 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1616 		return;
1617 	}
1618 
1619 	log_page = ctrlr->tmp_ptr;
1620 
1621 	if (log_page->io_cmds_supported[SPDK_NVME_OPC_ZONE_APPEND].csupp) {
1622 		ctrlr->flags |= SPDK_NVME_CTRLR_ZONE_APPEND_SUPPORTED;
1623 	}
1624 	spdk_free(ctrlr->tmp_ptr);
1625 	ctrlr->tmp_ptr = NULL;
1626 
1627 	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES, ctrlr->opts.admin_timeout_ms);
1628 }
1629 
1630 static int
1631 nvme_ctrlr_get_zns_cmd_and_effects_log(struct spdk_nvme_ctrlr *ctrlr)
1632 {
1633 	int rc;
1634 
1635 	assert(!ctrlr->tmp_ptr);
1636 	ctrlr->tmp_ptr = spdk_zmalloc(sizeof(struct spdk_nvme_cmds_and_effect_log_page), 64, NULL,
1637 				      SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE | SPDK_MALLOC_DMA);
1638 	if (!ctrlr->tmp_ptr) {
1639 		rc = -ENOMEM;
1640 		goto error;
1641 	}
1642 
1643 	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG,
1644 			     ctrlr->opts.admin_timeout_ms);
1645 
1646 	rc = spdk_nvme_ctrlr_cmd_get_log_page_ext(ctrlr, SPDK_NVME_LOG_COMMAND_EFFECTS_LOG,
1647 			0, ctrlr->tmp_ptr, sizeof(struct spdk_nvme_cmds_and_effect_log_page),
1648 			0, 0, 0, SPDK_NVME_CSI_ZNS << 24,
1649 			nvme_ctrlr_get_zns_cmd_and_effects_log_done, ctrlr);
1650 	if (rc != 0) {
1651 		goto error;
1652 	}
1653 
1654 	return 0;
1655 
1656 error:
1657 	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1658 	spdk_free(ctrlr->tmp_ptr);
1659 	ctrlr->tmp_ptr = NULL;
1660 	return rc;
1661 }
1662 
1663 static void
1664 nvme_ctrlr_identify_zns_specific_done(void *arg, const struct spdk_nvme_cpl *cpl)
1665 {
1666 	struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
1667 
1668 	if (spdk_nvme_cpl_is_error(cpl)) {
1669 		/* no need to print an error, the controller simply does not support ZNS */
1670 		nvme_ctrlr_free_zns_specific_data(ctrlr);
1671 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES,
1672 				     ctrlr->opts.admin_timeout_ms);
1673 		return;
1674 	}
1675 
1676 	/* A zero zasl value means use mdts */
1677 	if (ctrlr->cdata_zns->zasl) {
1678 		uint32_t max_append = ctrlr->min_page_size * (1 << ctrlr->cdata_zns->zasl);
1679 		ctrlr->max_zone_append_size = spdk_min(ctrlr->max_xfer_size, max_append);
1680 	} else {
1681 		ctrlr->max_zone_append_size = ctrlr->max_xfer_size;
1682 	}
1683 
1684 	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG,
1685 			     ctrlr->opts.admin_timeout_ms);
1686 }
1687 
1688 /**
1689  * This function will try to fetch the I/O Command Specific Controller data structure for
1690  * each I/O Command Set supported by SPDK.
1691  *
1692  * If an I/O Command Set is not supported by the controller, "Invalid Field in Command"
1693  * will be returned. Since we are fetching in a exploratively way, getting an error back
1694  * from the controller should not be treated as fatal.
1695  *
1696  * I/O Command Sets not supported by SPDK will be skipped (e.g. Key Value Command Set).
1697  *
1698  * I/O Command Sets without a IOCS specific data structure (i.e. a zero-filled IOCS specific
1699  * data structure) will be skipped (e.g. NVM Command Set, Key Value Command Set).
1700  */
1701 static int
1702 nvme_ctrlr_identify_iocs_specific(struct spdk_nvme_ctrlr *ctrlr)
1703 {
1704 	int	rc;
1705 
1706 	if (!nvme_ctrlr_multi_iocs_enabled(ctrlr)) {
1707 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES,
1708 				     ctrlr->opts.admin_timeout_ms);
1709 		return 0;
1710 	}
1711 
1712 	/*
1713 	 * Since SPDK currently only needs to fetch a single Command Set, keep the code here,
1714 	 * instead of creating multiple NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC substates,
1715 	 * which would require additional functions and complexity for no good reason.
1716 	 */
1717 	assert(!ctrlr->cdata_zns);
1718 	ctrlr->cdata_zns = spdk_zmalloc(sizeof(*ctrlr->cdata_zns), 64, NULL, SPDK_ENV_SOCKET_ID_ANY,
1719 					SPDK_MALLOC_SHARE | SPDK_MALLOC_DMA);
1720 	if (!ctrlr->cdata_zns) {
1721 		rc = -ENOMEM;
1722 		goto error;
1723 	}
1724 
1725 	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC,
1726 			     ctrlr->opts.admin_timeout_ms);
1727 
1728 	rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_CTRLR_IOCS, 0, 0, SPDK_NVME_CSI_ZNS,
1729 				     ctrlr->cdata_zns, sizeof(*ctrlr->cdata_zns),
1730 				     nvme_ctrlr_identify_zns_specific_done, ctrlr);
1731 	if (rc != 0) {
1732 		goto error;
1733 	}
1734 
1735 	return 0;
1736 
1737 error:
1738 	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1739 	nvme_ctrlr_free_zns_specific_data(ctrlr);
1740 	return rc;
1741 }
1742 
1743 enum nvme_active_ns_state {
1744 	NVME_ACTIVE_NS_STATE_IDLE,
1745 	NVME_ACTIVE_NS_STATE_PROCESSING,
1746 	NVME_ACTIVE_NS_STATE_DONE,
1747 	NVME_ACTIVE_NS_STATE_ERROR
1748 };
1749 
1750 typedef void (*nvme_active_ns_ctx_deleter)(struct nvme_active_ns_ctx *);
1751 
1752 struct nvme_active_ns_ctx {
1753 	struct spdk_nvme_ctrlr *ctrlr;
1754 	uint32_t page;
1755 	uint32_t num_pages;
1756 	uint32_t next_nsid;
1757 	uint32_t *new_ns_list;
1758 	nvme_active_ns_ctx_deleter deleter;
1759 
1760 	enum nvme_active_ns_state state;
1761 };
1762 
1763 static struct nvme_active_ns_ctx *
1764 nvme_active_ns_ctx_create(struct spdk_nvme_ctrlr *ctrlr, nvme_active_ns_ctx_deleter deleter)
1765 {
1766 	struct nvme_active_ns_ctx *ctx;
1767 	uint32_t num_pages = 0;
1768 	uint32_t *new_ns_list = NULL;
1769 
1770 	ctx = calloc(1, sizeof(*ctx));
1771 	if (!ctx) {
1772 		SPDK_ERRLOG("Failed to allocate nvme_active_ns_ctx!\n");
1773 		return NULL;
1774 	}
1775 
1776 	if (ctrlr->num_ns) {
1777 		/* The allocated size must be a multiple of sizeof(struct spdk_nvme_ns_list) */
1778 		num_pages = (ctrlr->num_ns * sizeof(new_ns_list[0]) - 1) / sizeof(struct spdk_nvme_ns_list) + 1;
1779 		new_ns_list = spdk_zmalloc(num_pages * sizeof(struct spdk_nvme_ns_list), ctrlr->page_size,
1780 					   NULL, SPDK_ENV_LCORE_ID_ANY, SPDK_MALLOC_DMA | SPDK_MALLOC_SHARE);
1781 		if (!new_ns_list) {
1782 			SPDK_ERRLOG("Failed to allocate active_ns_list!\n");
1783 			free(ctx);
1784 			return NULL;
1785 		}
1786 	}
1787 
1788 	ctx->num_pages = num_pages;
1789 	ctx->new_ns_list = new_ns_list;
1790 	ctx->ctrlr = ctrlr;
1791 	ctx->deleter = deleter;
1792 
1793 	return ctx;
1794 }
1795 
1796 static void
1797 nvme_active_ns_ctx_destroy(struct nvme_active_ns_ctx *ctx)
1798 {
1799 	spdk_free(ctx->new_ns_list);
1800 	free(ctx);
1801 }
1802 
1803 static void
1804 nvme_ctrlr_identify_active_ns_swap(struct spdk_nvme_ctrlr *ctrlr, uint32_t **new_ns_list)
1805 {
1806 	spdk_free(ctrlr->active_ns_list);
1807 	ctrlr->active_ns_list = *new_ns_list;
1808 	*new_ns_list = NULL;
1809 }
1810 
1811 static void
1812 nvme_ctrlr_identify_active_ns_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
1813 {
1814 	struct nvme_active_ns_ctx *ctx = arg;
1815 
1816 	if (spdk_nvme_cpl_is_error(cpl)) {
1817 		ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
1818 		goto out;
1819 	}
1820 
1821 	ctx->next_nsid = ctx->new_ns_list[1024 * ctx->page + 1023];
1822 	if (ctx->next_nsid == 0 || ++ctx->page == ctx->num_pages) {
1823 		ctx->state = NVME_ACTIVE_NS_STATE_DONE;
1824 		goto out;
1825 	}
1826 
1827 	nvme_ctrlr_identify_active_ns_async(ctx);
1828 	return;
1829 
1830 out:
1831 	if (ctx->deleter) {
1832 		ctx->deleter(ctx);
1833 	}
1834 }
1835 
1836 static void
1837 nvme_ctrlr_identify_active_ns_async(struct nvme_active_ns_ctx *ctx)
1838 {
1839 	struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
1840 	uint32_t i;
1841 	int rc;
1842 
1843 	if (ctrlr->num_ns == 0) {
1844 		ctx->state = NVME_ACTIVE_NS_STATE_DONE;
1845 		goto out;
1846 	}
1847 
1848 	/*
1849 	 * If controller doesn't support active ns list CNS 0x02 dummy up
1850 	 * an active ns list, i.e. all namespaces report as active
1851 	 */
1852 	if (ctrlr->vs.raw < SPDK_NVME_VERSION(1, 1, 0) || ctrlr->quirks & NVME_QUIRK_IDENTIFY_CNS) {
1853 		for (i = 0; i < ctrlr->num_ns; i++) {
1854 			ctx->new_ns_list[i] = i + 1;
1855 		}
1856 
1857 		ctx->state = NVME_ACTIVE_NS_STATE_DONE;
1858 		goto out;
1859 	}
1860 
1861 	ctx->state = NVME_ACTIVE_NS_STATE_PROCESSING;
1862 	rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_ACTIVE_NS_LIST, 0, ctx->next_nsid, 0,
1863 				     &ctx->new_ns_list[1024 * ctx->page], sizeof(struct spdk_nvme_ns_list),
1864 				     nvme_ctrlr_identify_active_ns_async_done, ctx);
1865 	if (rc != 0) {
1866 		ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
1867 		goto out;
1868 	}
1869 
1870 	return;
1871 
1872 out:
1873 	if (ctx->deleter) {
1874 		ctx->deleter(ctx);
1875 	}
1876 }
1877 
1878 static void
1879 _nvme_active_ns_ctx_deleter(struct nvme_active_ns_ctx *ctx)
1880 {
1881 	struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr;
1882 
1883 	if (ctx->state == NVME_ACTIVE_NS_STATE_ERROR) {
1884 		nvme_ctrlr_destruct_namespaces(ctrlr);
1885 		nvme_active_ns_ctx_destroy(ctx);
1886 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1887 		return;
1888 	}
1889 
1890 	assert(ctx->state == NVME_ACTIVE_NS_STATE_DONE);
1891 	nvme_ctrlr_identify_active_ns_swap(ctrlr, &ctx->new_ns_list);
1892 	nvme_active_ns_ctx_destroy(ctx);
1893 	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS, ctrlr->opts.admin_timeout_ms);
1894 }
1895 
1896 static void
1897 _nvme_ctrlr_identify_active_ns(struct spdk_nvme_ctrlr *ctrlr)
1898 {
1899 	struct nvme_active_ns_ctx *ctx;
1900 
1901 	ctx = nvme_active_ns_ctx_create(ctrlr, _nvme_active_ns_ctx_deleter);
1902 	if (!ctx) {
1903 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1904 		return;
1905 	}
1906 
1907 	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS,
1908 			     ctrlr->opts.admin_timeout_ms);
1909 	nvme_ctrlr_identify_active_ns_async(ctx);
1910 }
1911 
1912 int
1913 nvme_ctrlr_identify_active_ns(struct spdk_nvme_ctrlr *ctrlr)
1914 {
1915 	struct nvme_active_ns_ctx *ctx;
1916 	int rc;
1917 
1918 	ctx = nvme_active_ns_ctx_create(ctrlr, NULL);
1919 	if (!ctx) {
1920 		return -ENOMEM;
1921 	}
1922 
1923 	nvme_ctrlr_identify_active_ns_async(ctx);
1924 	while (ctx->state == NVME_ACTIVE_NS_STATE_PROCESSING) {
1925 		rc = spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
1926 		if (rc < 0) {
1927 			ctx->state = NVME_ACTIVE_NS_STATE_ERROR;
1928 			break;
1929 		}
1930 	}
1931 
1932 	if (ctx->state == NVME_ACTIVE_NS_STATE_ERROR) {
1933 		nvme_active_ns_ctx_destroy(ctx);
1934 		return -ENXIO;
1935 	}
1936 
1937 	assert(ctx->state == NVME_ACTIVE_NS_STATE_DONE);
1938 	nvme_ctrlr_identify_active_ns_swap(ctrlr, &ctx->new_ns_list);
1939 	nvme_active_ns_ctx_destroy(ctx);
1940 
1941 	return 0;
1942 }
1943 
1944 static void
1945 nvme_ctrlr_identify_ns_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
1946 {
1947 	struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg;
1948 	struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
1949 	uint32_t nsid;
1950 	int rc;
1951 
1952 	if (spdk_nvme_cpl_is_error(cpl)) {
1953 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1954 		return;
1955 	}
1956 
1957 	nvme_ns_set_identify_data(ns);
1958 
1959 	/* move on to the next active NS */
1960 	nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id);
1961 	ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
1962 	if (ns == NULL) {
1963 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ID_DESCS,
1964 				     ctrlr->opts.admin_timeout_ms);
1965 		return;
1966 	}
1967 	ns->ctrlr = ctrlr;
1968 	ns->id = nsid;
1969 
1970 	rc = nvme_ctrlr_identify_ns_async(ns);
1971 	if (rc) {
1972 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
1973 	}
1974 }
1975 
1976 static int
1977 nvme_ctrlr_identify_ns_async(struct spdk_nvme_ns *ns)
1978 {
1979 	struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
1980 	struct spdk_nvme_ns_data *nsdata;
1981 
1982 	nsdata = &ctrlr->nsdata[ns->id - 1];
1983 
1984 	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS,
1985 			     ctrlr->opts.admin_timeout_ms);
1986 	return nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS, 0, ns->id, 0,
1987 				       nsdata, sizeof(*nsdata),
1988 				       nvme_ctrlr_identify_ns_async_done, ns);
1989 }
1990 
1991 static int
1992 nvme_ctrlr_identify_namespaces(struct spdk_nvme_ctrlr *ctrlr)
1993 {
1994 	uint32_t nsid;
1995 	struct spdk_nvme_ns *ns;
1996 	int rc;
1997 
1998 	nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
1999 	ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2000 	if (ns == NULL) {
2001 		/* No active NS, move on to the next state */
2002 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CONFIGURE_AER,
2003 				     ctrlr->opts.admin_timeout_ms);
2004 		return 0;
2005 	}
2006 
2007 	ns->ctrlr = ctrlr;
2008 	ns->id = nsid;
2009 
2010 	rc = nvme_ctrlr_identify_ns_async(ns);
2011 	if (rc) {
2012 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2013 	}
2014 
2015 	return rc;
2016 }
2017 
2018 static int
2019 nvme_ctrlr_identify_namespaces_iocs_specific_next(struct spdk_nvme_ctrlr *ctrlr, uint32_t prev_nsid)
2020 {
2021 	uint32_t nsid;
2022 	struct spdk_nvme_ns *ns;
2023 	int rc;
2024 
2025 	if (!prev_nsid) {
2026 		nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
2027 	} else {
2028 		/* move on to the next active NS */
2029 		nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, prev_nsid);
2030 	}
2031 
2032 	ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2033 	if (ns == NULL) {
2034 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CONFIGURE_AER,
2035 				     ctrlr->opts.admin_timeout_ms);
2036 		return 0;
2037 	}
2038 
2039 	/* loop until we find a ns which has (supported) iocs specific data */
2040 	while (!nvme_ns_has_supported_iocs_specific_data(ns)) {
2041 		nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id);
2042 		ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2043 		if (ns == NULL) {
2044 			/* no namespace with (supported) iocs specific data found */
2045 			nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CONFIGURE_AER,
2046 					     ctrlr->opts.admin_timeout_ms);
2047 			return 0;
2048 		}
2049 	}
2050 
2051 	rc = nvme_ctrlr_identify_ns_iocs_specific_async(ns);
2052 	if (rc) {
2053 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2054 	}
2055 
2056 	return rc;
2057 }
2058 
2059 static void
2060 nvme_ctrlr_identify_ns_zns_specific_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2061 {
2062 	struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg;
2063 	struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2064 
2065 	if (spdk_nvme_cpl_is_error(cpl)) {
2066 		nvme_ns_free_zns_specific_data(ns);
2067 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2068 		return;
2069 	}
2070 
2071 	nvme_ctrlr_identify_namespaces_iocs_specific_next(ctrlr, ns->id);
2072 }
2073 
2074 static int
2075 nvme_ctrlr_identify_ns_iocs_specific_async(struct spdk_nvme_ns *ns)
2076 {
2077 	struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2078 	struct spdk_nvme_zns_ns_data **nsdata_zns;
2079 	int rc;
2080 
2081 	switch (ns->csi) {
2082 	case SPDK_NVME_CSI_ZNS:
2083 		break;
2084 	default:
2085 		/*
2086 		 * This switch must handle all cases for which
2087 		 * nvme_ns_has_supported_iocs_specific_data() returns true,
2088 		 * other cases should never happen.
2089 		 */
2090 		assert(0);
2091 	}
2092 
2093 	assert(ctrlr->nsdata_zns);
2094 	nsdata_zns = &ctrlr->nsdata_zns[ns->id - 1];
2095 	assert(!*nsdata_zns);
2096 	*nsdata_zns = spdk_zmalloc(sizeof(**nsdata_zns), 64, NULL, SPDK_ENV_SOCKET_ID_ANY,
2097 				   SPDK_MALLOC_SHARE | SPDK_MALLOC_DMA);
2098 	if (!*nsdata_zns) {
2099 		return -ENOMEM;
2100 	}
2101 
2102 	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC,
2103 			     ctrlr->opts.admin_timeout_ms);
2104 	rc = nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS_IOCS, 0, ns->id, ns->csi,
2105 				     *nsdata_zns, sizeof(**nsdata_zns),
2106 				     nvme_ctrlr_identify_ns_zns_specific_async_done, ns);
2107 	if (rc) {
2108 		nvme_ns_free_zns_specific_data(ns);
2109 	}
2110 
2111 	return rc;
2112 }
2113 
2114 static int
2115 nvme_ctrlr_identify_namespaces_iocs_specific(struct spdk_nvme_ctrlr *ctrlr)
2116 {
2117 	if (!nvme_ctrlr_multi_iocs_enabled(ctrlr)) {
2118 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CONFIGURE_AER,
2119 				     ctrlr->opts.admin_timeout_ms);
2120 		return 0;
2121 	}
2122 
2123 	return nvme_ctrlr_identify_namespaces_iocs_specific_next(ctrlr, 0);
2124 }
2125 
2126 static void
2127 nvme_ctrlr_identify_id_desc_async_done(void *arg, const struct spdk_nvme_cpl *cpl)
2128 {
2129 	struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg;
2130 	struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2131 	uint32_t nsid;
2132 	int rc;
2133 
2134 	if (spdk_nvme_cpl_is_error(cpl)) {
2135 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CONFIGURE_AER,
2136 				     ctrlr->opts.admin_timeout_ms);
2137 		return;
2138 	}
2139 
2140 	nvme_ns_set_id_desc_list_data(ns);
2141 
2142 	/* move on to the next active NS */
2143 	nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id);
2144 	ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2145 	if (ns == NULL) {
2146 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC,
2147 				     ctrlr->opts.admin_timeout_ms);
2148 		return;
2149 	}
2150 
2151 	rc = nvme_ctrlr_identify_id_desc_async(ns);
2152 	if (rc) {
2153 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2154 	}
2155 }
2156 
2157 static int
2158 nvme_ctrlr_identify_id_desc_async(struct spdk_nvme_ns *ns)
2159 {
2160 	struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr;
2161 
2162 	memset(ns->id_desc_list, 0, sizeof(ns->id_desc_list));
2163 
2164 	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS,
2165 			     ctrlr->opts.admin_timeout_ms);
2166 	return nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS_ID_DESCRIPTOR_LIST,
2167 				       0, ns->id, 0, ns->id_desc_list, sizeof(ns->id_desc_list),
2168 				       nvme_ctrlr_identify_id_desc_async_done, ns);
2169 }
2170 
2171 static int
2172 nvme_ctrlr_identify_id_desc_namespaces(struct spdk_nvme_ctrlr *ctrlr)
2173 {
2174 	uint32_t nsid;
2175 	struct spdk_nvme_ns *ns;
2176 	int rc;
2177 
2178 	if ((ctrlr->vs.raw < SPDK_NVME_VERSION(1, 3, 0) &&
2179 	     !(ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS)) ||
2180 	    (ctrlr->quirks & NVME_QUIRK_IDENTIFY_CNS)) {
2181 		SPDK_DEBUGLOG(nvme, "Version < 1.3; not attempting to retrieve NS ID Descriptor List\n");
2182 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CONFIGURE_AER,
2183 				     ctrlr->opts.admin_timeout_ms);
2184 		return 0;
2185 	}
2186 
2187 	nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr);
2188 	ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid);
2189 	if (ns == NULL) {
2190 		/* No active NS, move on to the next state */
2191 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CONFIGURE_AER,
2192 				     ctrlr->opts.admin_timeout_ms);
2193 		return 0;
2194 	}
2195 
2196 	rc = nvme_ctrlr_identify_id_desc_async(ns);
2197 	if (rc) {
2198 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2199 	}
2200 
2201 	return rc;
2202 }
2203 
2204 static void
2205 nvme_ctrlr_update_nvmf_ioccsz(struct spdk_nvme_ctrlr *ctrlr)
2206 {
2207 	if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_RDMA ||
2208 	    ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_TCP ||
2209 	    ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_FC) {
2210 		if (ctrlr->cdata.nvmf_specific.ioccsz < 4) {
2211 			SPDK_ERRLOG("Incorrect IOCCSZ %u, the minimum value should be 4\n",
2212 				    ctrlr->cdata.nvmf_specific.ioccsz);
2213 			ctrlr->cdata.nvmf_specific.ioccsz = 4;
2214 			assert(0);
2215 		}
2216 		ctrlr->ioccsz_bytes = ctrlr->cdata.nvmf_specific.ioccsz * 16 - sizeof(struct spdk_nvme_cmd);
2217 		ctrlr->icdoff = ctrlr->cdata.nvmf_specific.icdoff;
2218 	}
2219 }
2220 
2221 static void
2222 nvme_ctrlr_set_num_queues_done(void *arg, const struct spdk_nvme_cpl *cpl)
2223 {
2224 	uint32_t cq_allocated, sq_allocated, min_allocated, i;
2225 	struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2226 
2227 	if (spdk_nvme_cpl_is_error(cpl)) {
2228 		SPDK_ERRLOG("Set Features - Number of Queues failed!\n");
2229 		ctrlr->opts.num_io_queues = 0;
2230 	} else {
2231 		/*
2232 		 * Data in cdw0 is 0-based.
2233 		 * Lower 16-bits indicate number of submission queues allocated.
2234 		 * Upper 16-bits indicate number of completion queues allocated.
2235 		 */
2236 		sq_allocated = (cpl->cdw0 & 0xFFFF) + 1;
2237 		cq_allocated = (cpl->cdw0 >> 16) + 1;
2238 
2239 		/*
2240 		 * For 1:1 queue mapping, set number of allocated queues to be minimum of
2241 		 * submission and completion queues.
2242 		 */
2243 		min_allocated = spdk_min(sq_allocated, cq_allocated);
2244 
2245 		/* Set number of queues to be minimum of requested and actually allocated. */
2246 		ctrlr->opts.num_io_queues = spdk_min(min_allocated, ctrlr->opts.num_io_queues);
2247 	}
2248 
2249 	ctrlr->free_io_qids = spdk_bit_array_create(ctrlr->opts.num_io_queues + 1);
2250 	if (ctrlr->free_io_qids == NULL) {
2251 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2252 		return;
2253 	}
2254 
2255 	/* Initialize list of free I/O queue IDs. QID 0 is the admin queue (implicitly allocated). */
2256 	for (i = 1; i <= ctrlr->opts.num_io_queues; i++) {
2257 		spdk_nvme_ctrlr_free_qid(ctrlr, i);
2258 	}
2259 
2260 	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CONSTRUCT_NS,
2261 			     ctrlr->opts.admin_timeout_ms);
2262 }
2263 
2264 static int
2265 nvme_ctrlr_set_num_queues(struct spdk_nvme_ctrlr *ctrlr)
2266 {
2267 	int rc;
2268 
2269 	if (ctrlr->opts.num_io_queues > SPDK_NVME_MAX_IO_QUEUES) {
2270 		SPDK_NOTICELOG("Limiting requested num_io_queues %u to max %d\n",
2271 			       ctrlr->opts.num_io_queues, SPDK_NVME_MAX_IO_QUEUES);
2272 		ctrlr->opts.num_io_queues = SPDK_NVME_MAX_IO_QUEUES;
2273 	} else if (ctrlr->opts.num_io_queues < 1) {
2274 		SPDK_NOTICELOG("Requested num_io_queues 0, increasing to 1\n");
2275 		ctrlr->opts.num_io_queues = 1;
2276 	}
2277 
2278 	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES,
2279 			     ctrlr->opts.admin_timeout_ms);
2280 
2281 	rc = nvme_ctrlr_cmd_set_num_queues(ctrlr, ctrlr->opts.num_io_queues,
2282 					   nvme_ctrlr_set_num_queues_done, ctrlr);
2283 	if (rc != 0) {
2284 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2285 		return rc;
2286 	}
2287 
2288 	return 0;
2289 }
2290 
2291 static void
2292 nvme_ctrlr_set_keep_alive_timeout_done(void *arg, const struct spdk_nvme_cpl *cpl)
2293 {
2294 	uint32_t keep_alive_interval_us;
2295 	struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2296 
2297 	if (spdk_nvme_cpl_is_error(cpl)) {
2298 		if ((cpl->status.sct == SPDK_NVME_SCT_GENERIC) &&
2299 		    (cpl->status.sc == SPDK_NVME_SC_INVALID_FIELD)) {
2300 			SPDK_DEBUGLOG(nvme, "Keep alive timeout Get Feature is not supported\n");
2301 		} else {
2302 			SPDK_ERRLOG("Keep alive timeout Get Feature failed: SC %x SCT %x\n",
2303 				    cpl->status.sc, cpl->status.sct);
2304 			ctrlr->opts.keep_alive_timeout_ms = 0;
2305 			nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2306 			return;
2307 		}
2308 	} else {
2309 		if (ctrlr->opts.keep_alive_timeout_ms != cpl->cdw0) {
2310 			SPDK_DEBUGLOG(nvme, "Controller adjusted keep alive timeout to %u ms\n",
2311 				      cpl->cdw0);
2312 		}
2313 
2314 		ctrlr->opts.keep_alive_timeout_ms = cpl->cdw0;
2315 	}
2316 
2317 	if (ctrlr->opts.keep_alive_timeout_ms == 0) {
2318 		ctrlr->keep_alive_interval_ticks = 0;
2319 	} else {
2320 		keep_alive_interval_us = ctrlr->opts.keep_alive_timeout_ms * 1000 / 2;
2321 
2322 		SPDK_DEBUGLOG(nvme, "Sending keep alive every %u us\n", keep_alive_interval_us);
2323 
2324 		ctrlr->keep_alive_interval_ticks = (keep_alive_interval_us * spdk_get_ticks_hz()) /
2325 						   UINT64_C(1000000);
2326 
2327 		/* Schedule the first Keep Alive to be sent as soon as possible. */
2328 		ctrlr->next_keep_alive_tick = spdk_get_ticks();
2329 	}
2330 
2331 	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID,
2332 			     ctrlr->opts.admin_timeout_ms);
2333 }
2334 
2335 static int
2336 nvme_ctrlr_set_keep_alive_timeout(struct spdk_nvme_ctrlr *ctrlr)
2337 {
2338 	int rc;
2339 
2340 	if (ctrlr->opts.keep_alive_timeout_ms == 0) {
2341 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID,
2342 				     ctrlr->opts.admin_timeout_ms);
2343 		return 0;
2344 	}
2345 
2346 	if (ctrlr->cdata.kas == 0) {
2347 		SPDK_DEBUGLOG(nvme, "Controller KAS is 0 - not enabling Keep Alive\n");
2348 		ctrlr->opts.keep_alive_timeout_ms = 0;
2349 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID,
2350 				     ctrlr->opts.admin_timeout_ms);
2351 		return 0;
2352 	}
2353 
2354 	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT,
2355 			     ctrlr->opts.admin_timeout_ms);
2356 
2357 	/* Retrieve actual keep alive timeout, since the controller may have adjusted it. */
2358 	rc = spdk_nvme_ctrlr_cmd_get_feature(ctrlr, SPDK_NVME_FEAT_KEEP_ALIVE_TIMER, 0, NULL, 0,
2359 					     nvme_ctrlr_set_keep_alive_timeout_done, ctrlr);
2360 	if (rc != 0) {
2361 		SPDK_ERRLOG("Keep alive timeout Get Feature failed: %d\n", rc);
2362 		ctrlr->opts.keep_alive_timeout_ms = 0;
2363 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2364 		return rc;
2365 	}
2366 
2367 	return 0;
2368 }
2369 
2370 static void
2371 nvme_ctrlr_set_host_id_done(void *arg, const struct spdk_nvme_cpl *cpl)
2372 {
2373 	struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg;
2374 
2375 	if (spdk_nvme_cpl_is_error(cpl)) {
2376 		/*
2377 		 * Treat Set Features - Host ID failure as non-fatal, since the Host ID feature
2378 		 * is optional.
2379 		 */
2380 		SPDK_WARNLOG("Set Features - Host ID failed: SC 0x%x SCT 0x%x\n",
2381 			     cpl->status.sc, cpl->status.sct);
2382 	} else {
2383 		SPDK_DEBUGLOG(nvme, "Set Features - Host ID was successful\n");
2384 	}
2385 
2386 	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE);
2387 }
2388 
2389 static int
2390 nvme_ctrlr_set_host_id(struct spdk_nvme_ctrlr *ctrlr)
2391 {
2392 	uint8_t *host_id;
2393 	uint32_t host_id_size;
2394 	int rc;
2395 
2396 	if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) {
2397 		/*
2398 		 * NVMe-oF sends the host ID during Connect and doesn't allow
2399 		 * Set Features - Host Identifier after Connect, so we don't need to do anything here.
2400 		 */
2401 		SPDK_DEBUGLOG(nvme, "NVMe-oF transport - not sending Set Features - Host ID\n");
2402 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE);
2403 		return 0;
2404 	}
2405 
2406 	if (ctrlr->cdata.ctratt.host_id_exhid_supported) {
2407 		SPDK_DEBUGLOG(nvme, "Using 128-bit extended host identifier\n");
2408 		host_id = ctrlr->opts.extended_host_id;
2409 		host_id_size = sizeof(ctrlr->opts.extended_host_id);
2410 	} else {
2411 		SPDK_DEBUGLOG(nvme, "Using 64-bit host identifier\n");
2412 		host_id = ctrlr->opts.host_id;
2413 		host_id_size = sizeof(ctrlr->opts.host_id);
2414 	}
2415 
2416 	/* If the user specified an all-zeroes host identifier, don't send the command. */
2417 	if (spdk_mem_all_zero(host_id, host_id_size)) {
2418 		SPDK_DEBUGLOG(nvme,
2419 			      "User did not specify host ID - not sending Set Features - Host ID\n");
2420 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE);
2421 		return 0;
2422 	}
2423 
2424 	SPDK_LOGDUMP(nvme, "host_id", host_id, host_id_size);
2425 
2426 	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_HOST_ID,
2427 			     ctrlr->opts.admin_timeout_ms);
2428 
2429 	rc = nvme_ctrlr_cmd_set_host_id(ctrlr, host_id, host_id_size, nvme_ctrlr_set_host_id_done, ctrlr);
2430 	if (rc != 0) {
2431 		SPDK_ERRLOG("Set Features - Host ID failed: %d\n", rc);
2432 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2433 		return rc;
2434 	}
2435 
2436 	return 0;
2437 }
2438 
2439 static void
2440 nvme_ctrlr_destruct_namespaces(struct spdk_nvme_ctrlr *ctrlr)
2441 {
2442 	if (ctrlr->ns) {
2443 		uint32_t i, num_ns = ctrlr->num_ns;
2444 
2445 		for (i = 0; i < num_ns; i++) {
2446 			nvme_ns_destruct(&ctrlr->ns[i]);
2447 		}
2448 
2449 		spdk_free(ctrlr->ns);
2450 		ctrlr->ns = NULL;
2451 		ctrlr->num_ns = 0;
2452 	}
2453 
2454 	if (ctrlr->nsdata) {
2455 		spdk_free(ctrlr->nsdata);
2456 		ctrlr->nsdata = NULL;
2457 	}
2458 
2459 	spdk_free(ctrlr->nsdata_zns);
2460 	ctrlr->nsdata_zns = NULL;
2461 
2462 	spdk_free(ctrlr->active_ns_list);
2463 	ctrlr->active_ns_list = NULL;
2464 }
2465 
2466 static void
2467 nvme_ctrlr_update_namespaces(struct spdk_nvme_ctrlr *ctrlr)
2468 {
2469 	uint32_t i, nn = ctrlr->cdata.nn;
2470 	struct spdk_nvme_ns_data *nsdata;
2471 	bool ns_is_active;
2472 
2473 	for (i = 0; i < nn; i++) {
2474 		struct spdk_nvme_ns	*ns = &ctrlr->ns[i];
2475 		uint32_t		nsid = i + 1;
2476 
2477 		nsdata = &ctrlr->nsdata[nsid - 1];
2478 		ns_is_active = spdk_nvme_ctrlr_is_active_ns(ctrlr, nsid);
2479 
2480 		if (nsdata->ncap && ns_is_active) {
2481 			if (nvme_ns_update(ns) != 0) {
2482 				SPDK_ERRLOG("Failed to update active NS %u\n", nsid);
2483 				continue;
2484 			}
2485 		}
2486 
2487 		if ((nsdata->ncap == 0) && ns_is_active) {
2488 			if (nvme_ns_construct(ns, nsid, ctrlr) != 0) {
2489 				continue;
2490 			}
2491 		}
2492 
2493 		if (nsdata->ncap && !ns_is_active) {
2494 			nvme_ns_destruct(ns);
2495 		}
2496 	}
2497 }
2498 
2499 static int
2500 nvme_ctrlr_construct_namespaces(struct spdk_nvme_ctrlr *ctrlr)
2501 {
2502 	int rc = 0;
2503 	uint32_t i, nn = ctrlr->cdata.nn;
2504 
2505 	/* ctrlr->num_ns may be 0 (startup) or a different number of namespaces (reset),
2506 	 * so check if we need to reallocate.
2507 	 */
2508 	if (nn != ctrlr->num_ns) {
2509 		nvme_ctrlr_destruct_namespaces(ctrlr);
2510 
2511 		if (nn == 0) {
2512 			SPDK_WARNLOG("controller has 0 namespaces\n");
2513 			return 0;
2514 		}
2515 
2516 		ctrlr->ns = spdk_zmalloc(nn * sizeof(struct spdk_nvme_ns), 64, NULL,
2517 					 SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE);
2518 		if (ctrlr->ns == NULL) {
2519 			rc = -ENOMEM;
2520 			goto fail;
2521 		}
2522 
2523 		ctrlr->nsdata = spdk_zmalloc(nn * sizeof(struct spdk_nvme_ns_data), 64,
2524 					     NULL, SPDK_ENV_SOCKET_ID_ANY,
2525 					     SPDK_MALLOC_SHARE | SPDK_MALLOC_DMA);
2526 		if (ctrlr->nsdata == NULL) {
2527 			rc = -ENOMEM;
2528 			goto fail;
2529 		}
2530 
2531 		ctrlr->nsdata_zns = spdk_zmalloc(nn * sizeof(struct spdk_nvme_zns_ns_data *), 64,
2532 						 NULL, SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE);
2533 		if (ctrlr->nsdata_zns == NULL) {
2534 			rc = -ENOMEM;
2535 			goto fail;
2536 		}
2537 
2538 		ctrlr->num_ns = nn;
2539 	} else {
2540 		/*
2541 		 * The controller could have been reset with the same number of namespaces.
2542 		 * If so, we still need to free the iocs specific data, to get a clean slate.
2543 		 */
2544 		for (i = 0; i < ctrlr->num_ns; i++) {
2545 			nvme_ns_free_iocs_specific_data(&ctrlr->ns[i]);
2546 		}
2547 	}
2548 
2549 	return 0;
2550 
2551 fail:
2552 	nvme_ctrlr_destruct_namespaces(ctrlr);
2553 	return rc;
2554 }
2555 
2556 static void
2557 nvme_ctrlr_async_event_cb(void *arg, const struct spdk_nvme_cpl *cpl)
2558 {
2559 	struct nvme_async_event_request	*aer = arg;
2560 	struct spdk_nvme_ctrlr		*ctrlr = aer->ctrlr;
2561 	struct spdk_nvme_ctrlr_process	*active_proc;
2562 	union spdk_nvme_async_event_completion	event;
2563 	int					rc;
2564 
2565 	if (cpl->status.sct == SPDK_NVME_SCT_GENERIC &&
2566 	    cpl->status.sc == SPDK_NVME_SC_ABORTED_SQ_DELETION) {
2567 		/*
2568 		 *  This is simulated when controller is being shut down, to
2569 		 *  effectively abort outstanding asynchronous event requests
2570 		 *  and make sure all memory is freed.  Do not repost the
2571 		 *  request in this case.
2572 		 */
2573 		return;
2574 	}
2575 
2576 	if (cpl->status.sct == SPDK_NVME_SCT_COMMAND_SPECIFIC &&
2577 	    cpl->status.sc == SPDK_NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED) {
2578 		/*
2579 		 *  SPDK will only send as many AERs as the device says it supports,
2580 		 *  so this status code indicates an out-of-spec device.  Do not repost
2581 		 *  the request in this case.
2582 		 */
2583 		SPDK_ERRLOG("Controller appears out-of-spec for asynchronous event request\n"
2584 			    "handling.  Do not repost this AER.\n");
2585 		return;
2586 	}
2587 
2588 	event.raw = cpl->cdw0;
2589 	if ((event.bits.async_event_type == SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE) &&
2590 	    (event.bits.async_event_info == SPDK_NVME_ASYNC_EVENT_NS_ATTR_CHANGED)) {
2591 		rc = nvme_ctrlr_identify_active_ns(ctrlr);
2592 		if (rc) {
2593 			return;
2594 		}
2595 		nvme_ctrlr_update_namespaces(ctrlr);
2596 		nvme_io_msg_ctrlr_update(ctrlr);
2597 	}
2598 
2599 	if ((event.bits.async_event_type == SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE) &&
2600 	    (event.bits.async_event_info == SPDK_NVME_ASYNC_EVENT_ANA_CHANGE)) {
2601 		rc = nvme_ctrlr_update_ana_log_page(ctrlr);
2602 		if (rc) {
2603 			return;
2604 		}
2605 		nvme_ctrlr_parse_ana_log_page(ctrlr, nvme_ctrlr_update_ns_ana_states, ctrlr);
2606 	}
2607 
2608 	active_proc = nvme_ctrlr_get_current_process(ctrlr);
2609 	if (active_proc && active_proc->aer_cb_fn) {
2610 		active_proc->aer_cb_fn(active_proc->aer_cb_arg, cpl);
2611 	}
2612 
2613 	/* If the ctrlr was removed or in the destruct state, we should not send aer again */
2614 	if (ctrlr->is_removed || ctrlr->is_destructed) {
2615 		return;
2616 	}
2617 
2618 	/*
2619 	 * Repost another asynchronous event request to replace the one
2620 	 *  that just completed.
2621 	 */
2622 	if (nvme_ctrlr_construct_and_submit_aer(ctrlr, aer)) {
2623 		/*
2624 		 * We can't do anything to recover from a failure here,
2625 		 * so just print a warning message and leave the AER unsubmitted.
2626 		 */
2627 		SPDK_ERRLOG("resubmitting AER failed!\n");
2628 	}
2629 }
2630 
2631 static int
2632 nvme_ctrlr_construct_and_submit_aer(struct spdk_nvme_ctrlr *ctrlr,
2633 				    struct nvme_async_event_request *aer)
2634 {
2635 	struct nvme_request *req;
2636 
2637 	aer->ctrlr = ctrlr;
2638 	req = nvme_allocate_request_null(ctrlr->adminq, nvme_ctrlr_async_event_cb, aer);
2639 	aer->req = req;
2640 	if (req == NULL) {
2641 		return -1;
2642 	}
2643 
2644 	req->cmd.opc = SPDK_NVME_OPC_ASYNC_EVENT_REQUEST;
2645 	return nvme_ctrlr_submit_admin_request(ctrlr, req);
2646 }
2647 
2648 static void
2649 nvme_ctrlr_configure_aer_done(void *arg, const struct spdk_nvme_cpl *cpl)
2650 {
2651 	struct nvme_async_event_request		*aer;
2652 	int					rc;
2653 	uint32_t				i;
2654 	struct spdk_nvme_ctrlr *ctrlr =	(struct spdk_nvme_ctrlr *)arg;
2655 
2656 	if (spdk_nvme_cpl_is_error(cpl)) {
2657 		SPDK_NOTICELOG("nvme_ctrlr_configure_aer failed!\n");
2658 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES,
2659 				     ctrlr->opts.admin_timeout_ms);
2660 		return;
2661 	}
2662 
2663 	/* aerl is a zero-based value, so we need to add 1 here. */
2664 	ctrlr->num_aers = spdk_min(NVME_MAX_ASYNC_EVENTS, (ctrlr->cdata.aerl + 1));
2665 
2666 	for (i = 0; i < ctrlr->num_aers; i++) {
2667 		aer = &ctrlr->aer[i];
2668 		rc = nvme_ctrlr_construct_and_submit_aer(ctrlr, aer);
2669 		if (rc) {
2670 			SPDK_ERRLOG("nvme_ctrlr_construct_and_submit_aer failed!\n");
2671 			nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2672 			return;
2673 		}
2674 	}
2675 	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES,
2676 			     ctrlr->opts.admin_timeout_ms);
2677 }
2678 
2679 static int
2680 nvme_ctrlr_configure_aer(struct spdk_nvme_ctrlr *ctrlr)
2681 {
2682 	union spdk_nvme_feat_async_event_configuration	config;
2683 	int						rc;
2684 
2685 	config.raw = 0;
2686 	config.bits.crit_warn.bits.available_spare = 1;
2687 	config.bits.crit_warn.bits.temperature = 1;
2688 	config.bits.crit_warn.bits.device_reliability = 1;
2689 	config.bits.crit_warn.bits.read_only = 1;
2690 	config.bits.crit_warn.bits.volatile_memory_backup = 1;
2691 
2692 	if (ctrlr->vs.raw >= SPDK_NVME_VERSION(1, 2, 0)) {
2693 		if (ctrlr->cdata.oaes.ns_attribute_notices) {
2694 			config.bits.ns_attr_notice = 1;
2695 		}
2696 		if (ctrlr->cdata.oaes.fw_activation_notices) {
2697 			config.bits.fw_activation_notice = 1;
2698 		}
2699 		if (ctrlr->cdata.oaes.ana_change_notices) {
2700 			config.bits.ana_change_notice = 1;
2701 		}
2702 	}
2703 	if (ctrlr->vs.raw >= SPDK_NVME_VERSION(1, 3, 0) && ctrlr->cdata.lpa.telemetry) {
2704 		config.bits.telemetry_log_notice = 1;
2705 	}
2706 
2707 	nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER,
2708 			     ctrlr->opts.admin_timeout_ms);
2709 
2710 	rc = nvme_ctrlr_cmd_set_async_event_config(ctrlr, config,
2711 			nvme_ctrlr_configure_aer_done,
2712 			ctrlr);
2713 	if (rc != 0) {
2714 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE);
2715 		return rc;
2716 	}
2717 
2718 	return 0;
2719 }
2720 
2721 struct spdk_nvme_ctrlr_process *
2722 nvme_ctrlr_get_process(struct spdk_nvme_ctrlr *ctrlr, pid_t pid)
2723 {
2724 	struct spdk_nvme_ctrlr_process	*active_proc;
2725 
2726 	TAILQ_FOREACH(active_proc, &ctrlr->active_procs, tailq) {
2727 		if (active_proc->pid == pid) {
2728 			return active_proc;
2729 		}
2730 	}
2731 
2732 	return NULL;
2733 }
2734 
2735 struct spdk_nvme_ctrlr_process *
2736 nvme_ctrlr_get_current_process(struct spdk_nvme_ctrlr *ctrlr)
2737 {
2738 	return nvme_ctrlr_get_process(ctrlr, getpid());
2739 }
2740 
2741 /**
2742  * This function will be called when a process is using the controller.
2743  *  1. For the primary process, it is called when constructing the controller.
2744  *  2. For the secondary process, it is called at probing the controller.
2745  * Note: will check whether the process is already added for the same process.
2746  */
2747 int
2748 nvme_ctrlr_add_process(struct spdk_nvme_ctrlr *ctrlr, void *devhandle)
2749 {
2750 	struct spdk_nvme_ctrlr_process	*ctrlr_proc;
2751 	pid_t				pid = getpid();
2752 
2753 	/* Check whether the process is already added or not */
2754 	if (nvme_ctrlr_get_process(ctrlr, pid)) {
2755 		return 0;
2756 	}
2757 
2758 	/* Initialize the per process properties for this ctrlr */
2759 	ctrlr_proc = spdk_zmalloc(sizeof(struct spdk_nvme_ctrlr_process),
2760 				  64, NULL, SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE);
2761 	if (ctrlr_proc == NULL) {
2762 		SPDK_ERRLOG("failed to allocate memory to track the process props\n");
2763 
2764 		return -1;
2765 	}
2766 
2767 	ctrlr_proc->is_primary = spdk_process_is_primary();
2768 	ctrlr_proc->pid = pid;
2769 	STAILQ_INIT(&ctrlr_proc->active_reqs);
2770 	ctrlr_proc->devhandle = devhandle;
2771 	ctrlr_proc->ref = 0;
2772 	TAILQ_INIT(&ctrlr_proc->allocated_io_qpairs);
2773 
2774 	TAILQ_INSERT_TAIL(&ctrlr->active_procs, ctrlr_proc, tailq);
2775 
2776 	return 0;
2777 }
2778 
2779 /**
2780  * This function will be called when the process detaches the controller.
2781  * Note: the ctrlr_lock must be held when calling this function.
2782  */
2783 static void
2784 nvme_ctrlr_remove_process(struct spdk_nvme_ctrlr *ctrlr,
2785 			  struct spdk_nvme_ctrlr_process *proc)
2786 {
2787 	struct spdk_nvme_qpair	*qpair, *tmp_qpair;
2788 
2789 	assert(STAILQ_EMPTY(&proc->active_reqs));
2790 
2791 	TAILQ_FOREACH_SAFE(qpair, &proc->allocated_io_qpairs, per_process_tailq, tmp_qpair) {
2792 		spdk_nvme_ctrlr_free_io_qpair(qpair);
2793 	}
2794 
2795 	TAILQ_REMOVE(&ctrlr->active_procs, proc, tailq);
2796 
2797 	if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) {
2798 		spdk_pci_device_detach(proc->devhandle);
2799 	}
2800 
2801 	spdk_free(proc);
2802 }
2803 
2804 /**
2805  * This function will be called when the process exited unexpectedly
2806  *  in order to free any incomplete nvme request, allocated IO qpairs
2807  *  and allocated memory.
2808  * Note: the ctrlr_lock must be held when calling this function.
2809  */
2810 static void
2811 nvme_ctrlr_cleanup_process(struct spdk_nvme_ctrlr_process *proc)
2812 {
2813 	struct nvme_request	*req, *tmp_req;
2814 	struct spdk_nvme_qpair	*qpair, *tmp_qpair;
2815 
2816 	STAILQ_FOREACH_SAFE(req, &proc->active_reqs, stailq, tmp_req) {
2817 		STAILQ_REMOVE(&proc->active_reqs, req, nvme_request, stailq);
2818 
2819 		assert(req->pid == proc->pid);
2820 
2821 		nvme_free_request(req);
2822 	}
2823 
2824 	TAILQ_FOREACH_SAFE(qpair, &proc->allocated_io_qpairs, per_process_tailq, tmp_qpair) {
2825 		TAILQ_REMOVE(&proc->allocated_io_qpairs, qpair, per_process_tailq);
2826 
2827 		/*
2828 		 * The process may have been killed while some qpairs were in their
2829 		 *  completion context.  Clear that flag here to allow these IO
2830 		 *  qpairs to be deleted.
2831 		 */
2832 		qpair->in_completion_context = 0;
2833 
2834 		qpair->no_deletion_notification_needed = 1;
2835 
2836 		spdk_nvme_ctrlr_free_io_qpair(qpair);
2837 	}
2838 
2839 	spdk_free(proc);
2840 }
2841 
2842 /**
2843  * This function will be called when destructing the controller.
2844  *  1. There is no more admin request on this controller.
2845  *  2. Clean up any left resource allocation when its associated process is gone.
2846  */
2847 void
2848 nvme_ctrlr_free_processes(struct spdk_nvme_ctrlr *ctrlr)
2849 {
2850 	struct spdk_nvme_ctrlr_process	*active_proc, *tmp;
2851 
2852 	/* Free all the processes' properties and make sure no pending admin IOs */
2853 	TAILQ_FOREACH_SAFE(active_proc, &ctrlr->active_procs, tailq, tmp) {
2854 		TAILQ_REMOVE(&ctrlr->active_procs, active_proc, tailq);
2855 
2856 		assert(STAILQ_EMPTY(&active_proc->active_reqs));
2857 
2858 		spdk_free(active_proc);
2859 	}
2860 }
2861 
2862 /**
2863  * This function will be called when any other process attaches or
2864  *  detaches the controller in order to cleanup those unexpectedly
2865  *  terminated processes.
2866  * Note: the ctrlr_lock must be held when calling this function.
2867  */
2868 static int
2869 nvme_ctrlr_remove_inactive_proc(struct spdk_nvme_ctrlr *ctrlr)
2870 {
2871 	struct spdk_nvme_ctrlr_process	*active_proc, *tmp;
2872 	int				active_proc_count = 0;
2873 
2874 	TAILQ_FOREACH_SAFE(active_proc, &ctrlr->active_procs, tailq, tmp) {
2875 		if ((kill(active_proc->pid, 0) == -1) && (errno == ESRCH)) {
2876 			SPDK_ERRLOG("process %d terminated unexpected\n", active_proc->pid);
2877 
2878 			TAILQ_REMOVE(&ctrlr->active_procs, active_proc, tailq);
2879 
2880 			nvme_ctrlr_cleanup_process(active_proc);
2881 		} else {
2882 			active_proc_count++;
2883 		}
2884 	}
2885 
2886 	return active_proc_count;
2887 }
2888 
2889 void
2890 nvme_ctrlr_proc_get_ref(struct spdk_nvme_ctrlr *ctrlr)
2891 {
2892 	struct spdk_nvme_ctrlr_process	*active_proc;
2893 
2894 	nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
2895 
2896 	nvme_ctrlr_remove_inactive_proc(ctrlr);
2897 
2898 	active_proc = nvme_ctrlr_get_current_process(ctrlr);
2899 	if (active_proc) {
2900 		active_proc->ref++;
2901 	}
2902 
2903 	nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
2904 }
2905 
2906 void
2907 nvme_ctrlr_proc_put_ref(struct spdk_nvme_ctrlr *ctrlr)
2908 {
2909 	struct spdk_nvme_ctrlr_process	*active_proc;
2910 	int				proc_count;
2911 
2912 	nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
2913 
2914 	proc_count = nvme_ctrlr_remove_inactive_proc(ctrlr);
2915 
2916 	active_proc = nvme_ctrlr_get_current_process(ctrlr);
2917 	if (active_proc) {
2918 		active_proc->ref--;
2919 		assert(active_proc->ref >= 0);
2920 
2921 		/*
2922 		 * The last active process will be removed at the end of
2923 		 * the destruction of the controller.
2924 		 */
2925 		if (active_proc->ref == 0 && proc_count != 1) {
2926 			nvme_ctrlr_remove_process(ctrlr, active_proc);
2927 		}
2928 	}
2929 
2930 	nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
2931 }
2932 
2933 int
2934 nvme_ctrlr_get_ref_count(struct spdk_nvme_ctrlr *ctrlr)
2935 {
2936 	struct spdk_nvme_ctrlr_process	*active_proc;
2937 	int				ref = 0;
2938 
2939 	nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
2940 
2941 	nvme_ctrlr_remove_inactive_proc(ctrlr);
2942 
2943 	TAILQ_FOREACH(active_proc, &ctrlr->active_procs, tailq) {
2944 		ref += active_proc->ref;
2945 	}
2946 
2947 	nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
2948 
2949 	return ref;
2950 }
2951 
2952 /**
2953  *  Get the PCI device handle which is only visible to its associated process.
2954  */
2955 struct spdk_pci_device *
2956 nvme_ctrlr_proc_get_devhandle(struct spdk_nvme_ctrlr *ctrlr)
2957 {
2958 	struct spdk_nvme_ctrlr_process	*active_proc;
2959 	struct spdk_pci_device		*devhandle = NULL;
2960 
2961 	nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
2962 
2963 	active_proc = nvme_ctrlr_get_current_process(ctrlr);
2964 	if (active_proc) {
2965 		devhandle = active_proc->devhandle;
2966 	}
2967 
2968 	nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
2969 
2970 	return devhandle;
2971 }
2972 
2973 /**
2974  * This function will be called repeatedly during initialization until the controller is ready.
2975  */
2976 int
2977 nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr)
2978 {
2979 	union spdk_nvme_cc_register cc;
2980 	union spdk_nvme_csts_register csts;
2981 	uint32_t ready_timeout_in_ms;
2982 	uint64_t ticks;
2983 	int rc = 0;
2984 
2985 	ticks = spdk_get_ticks();
2986 
2987 	/*
2988 	 * May need to avoid accessing any register on the target controller
2989 	 * for a while. Return early without touching the FSM.
2990 	 * Check sleep_timeout_tsc > 0 for unit test.
2991 	 */
2992 	if ((ctrlr->sleep_timeout_tsc > 0) &&
2993 	    (ticks <= ctrlr->sleep_timeout_tsc)) {
2994 		return 0;
2995 	}
2996 	ctrlr->sleep_timeout_tsc = 0;
2997 
2998 	if (nvme_ctrlr_get_cc(ctrlr, &cc) ||
2999 	    nvme_ctrlr_get_csts(ctrlr, &csts)) {
3000 		if (!ctrlr->is_failed && ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE) {
3001 			/* While a device is resetting, it may be unable to service MMIO reads
3002 			 * temporarily. Allow for this case.
3003 			 */
3004 			SPDK_DEBUGLOG(nvme, "Get registers failed while waiting for CSTS.RDY == 0\n");
3005 			goto init_timeout;
3006 		}
3007 		SPDK_ERRLOG("Failed to read CC and CSTS in state %d\n", ctrlr->state);
3008 		return -EIO;
3009 	}
3010 
3011 	ready_timeout_in_ms = 500 * ctrlr->cap.bits.to;
3012 
3013 	/*
3014 	 * Check if the current initialization step is done or has timed out.
3015 	 */
3016 	switch (ctrlr->state) {
3017 	case NVME_CTRLR_STATE_INIT_DELAY:
3018 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, ready_timeout_in_ms);
3019 		if (ctrlr->quirks & NVME_QUIRK_DELAY_BEFORE_INIT) {
3020 			/*
3021 			 * Controller may need some delay before it's enabled.
3022 			 *
3023 			 * This is a workaround for an issue where the PCIe-attached NVMe controller
3024 			 * is not ready after VFIO reset. We delay the initialization rather than the
3025 			 * enabling itself, because this is required only for the very first enabling
3026 			 * - directly after a VFIO reset.
3027 			 */
3028 			SPDK_DEBUGLOG(nvme, "Adding 2 second delay before initializing the controller\n");
3029 			ctrlr->sleep_timeout_tsc = ticks + (2000 * spdk_get_ticks_hz() / 1000);
3030 		}
3031 		break;
3032 
3033 	case NVME_CTRLR_STATE_INIT:
3034 		/* Begin the hardware initialization by making sure the controller is disabled. */
3035 		if (cc.bits.en) {
3036 			SPDK_DEBUGLOG(nvme, "CC.EN = 1\n");
3037 			/*
3038 			 * Controller is currently enabled. We need to disable it to cause a reset.
3039 			 *
3040 			 * If CC.EN = 1 && CSTS.RDY = 0, the controller is in the process of becoming ready.
3041 			 *  Wait for the ready bit to be 1 before disabling the controller.
3042 			 */
3043 			if (csts.bits.rdy == 0) {
3044 				SPDK_DEBUGLOG(nvme, "CC.EN = 1 && CSTS.RDY = 0 - waiting for reset to complete\n");
3045 				nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1, ready_timeout_in_ms);
3046 				return 0;
3047 			}
3048 
3049 			/* CC.EN = 1 && CSTS.RDY == 1, so we can immediately disable the controller. */
3050 			SPDK_DEBUGLOG(nvme, "Setting CC.EN = 0\n");
3051 			cc.bits.en = 0;
3052 			if (nvme_ctrlr_set_cc(ctrlr, &cc)) {
3053 				SPDK_ERRLOG("set_cc() failed\n");
3054 				return -EIO;
3055 			}
3056 			nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0, ready_timeout_in_ms);
3057 
3058 			/*
3059 			 * Wait 2.5 seconds before accessing PCI registers.
3060 			 * Not using sleep() to avoid blocking other controller's initialization.
3061 			 */
3062 			if (ctrlr->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY) {
3063 				SPDK_DEBUGLOG(nvme, "Applying quirk: delay 2.5 seconds before reading registers\n");
3064 				ctrlr->sleep_timeout_tsc = ticks + (2500 * spdk_get_ticks_hz() / 1000);
3065 			}
3066 			return 0;
3067 		} else {
3068 			if (csts.bits.rdy == 1) {
3069 				SPDK_DEBUGLOG(nvme, "CC.EN = 0 && CSTS.RDY = 1 - waiting for shutdown to complete\n");
3070 			}
3071 
3072 			nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0, ready_timeout_in_ms);
3073 			return 0;
3074 		}
3075 		break;
3076 
3077 	case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1:
3078 		if (csts.bits.rdy == 1) {
3079 			SPDK_DEBUGLOG(nvme, "CC.EN = 1 && CSTS.RDY = 1 - disabling controller\n");
3080 			/* CC.EN = 1 && CSTS.RDY = 1, so we can set CC.EN = 0 now. */
3081 			SPDK_DEBUGLOG(nvme, "Setting CC.EN = 0\n");
3082 			cc.bits.en = 0;
3083 			if (nvme_ctrlr_set_cc(ctrlr, &cc)) {
3084 				SPDK_ERRLOG("set_cc() failed\n");
3085 				return -EIO;
3086 			}
3087 			nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0, ready_timeout_in_ms);
3088 			return 0;
3089 		}
3090 		break;
3091 
3092 	case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0:
3093 		if (csts.bits.rdy == 0) {
3094 			SPDK_DEBUGLOG(nvme, "CC.EN = 0 && CSTS.RDY = 0\n");
3095 			nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE, ready_timeout_in_ms);
3096 			/*
3097 			 * Delay 100us before setting CC.EN = 1.  Some NVMe SSDs miss CC.EN getting
3098 			 *  set to 1 if it is too soon after CSTS.RDY is reported as 0.
3099 			 */
3100 			spdk_delay_us(100);
3101 			return 0;
3102 		}
3103 		break;
3104 
3105 	case NVME_CTRLR_STATE_ENABLE:
3106 		SPDK_DEBUGLOG(nvme, "Setting CC.EN = 1\n");
3107 		rc = nvme_ctrlr_enable(ctrlr);
3108 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1, ready_timeout_in_ms);
3109 		return rc;
3110 
3111 	case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1:
3112 		if (csts.bits.rdy == 1) {
3113 			SPDK_DEBUGLOG(nvme, "CC.EN = 1 && CSTS.RDY = 1 - controller is ready\n");
3114 			/*
3115 			 * The controller has been enabled.
3116 			 *  Perform the rest of initialization serially.
3117 			 */
3118 			nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_RESET_ADMIN_QUEUE,
3119 					     ctrlr->opts.admin_timeout_ms);
3120 			return 0;
3121 		}
3122 		break;
3123 
3124 	case NVME_CTRLR_STATE_RESET_ADMIN_QUEUE:
3125 		nvme_transport_qpair_reset(ctrlr->adminq);
3126 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY,
3127 				     ctrlr->opts.admin_timeout_ms);
3128 		break;
3129 
3130 	case NVME_CTRLR_STATE_IDENTIFY:
3131 		rc = nvme_ctrlr_identify(ctrlr);
3132 		break;
3133 
3134 	case NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC:
3135 		rc = nvme_ctrlr_identify_iocs_specific(ctrlr);
3136 		break;
3137 
3138 	case NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG:
3139 		rc = nvme_ctrlr_get_zns_cmd_and_effects_log(ctrlr);
3140 		break;
3141 
3142 	case NVME_CTRLR_STATE_SET_NUM_QUEUES:
3143 		nvme_ctrlr_update_nvmf_ioccsz(ctrlr);
3144 		rc = nvme_ctrlr_set_num_queues(ctrlr);
3145 		break;
3146 
3147 	case NVME_CTRLR_STATE_CONSTRUCT_NS:
3148 		rc = nvme_ctrlr_construct_namespaces(ctrlr);
3149 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS,
3150 				     ctrlr->opts.admin_timeout_ms);
3151 		break;
3152 
3153 	case NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS:
3154 		_nvme_ctrlr_identify_active_ns(ctrlr);
3155 		break;
3156 
3157 	case NVME_CTRLR_STATE_IDENTIFY_NS:
3158 		rc = nvme_ctrlr_identify_namespaces(ctrlr);
3159 		break;
3160 
3161 	case NVME_CTRLR_STATE_IDENTIFY_ID_DESCS:
3162 		rc = nvme_ctrlr_identify_id_desc_namespaces(ctrlr);
3163 		break;
3164 
3165 	case NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC:
3166 		rc = nvme_ctrlr_identify_namespaces_iocs_specific(ctrlr);
3167 		break;
3168 
3169 	case NVME_CTRLR_STATE_CONFIGURE_AER:
3170 		rc = nvme_ctrlr_configure_aer(ctrlr);
3171 		break;
3172 
3173 	case NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES:
3174 		rc = nvme_ctrlr_set_supported_log_pages(ctrlr);
3175 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES,
3176 				     ctrlr->opts.admin_timeout_ms);
3177 		break;
3178 
3179 	case NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES:
3180 		nvme_ctrlr_set_supported_features(ctrlr);
3181 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_DB_BUF_CFG,
3182 				     ctrlr->opts.admin_timeout_ms);
3183 		break;
3184 
3185 	case NVME_CTRLR_STATE_SET_DB_BUF_CFG:
3186 		rc = nvme_ctrlr_set_doorbell_buffer_config(ctrlr);
3187 		break;
3188 
3189 	case NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT:
3190 		rc = nvme_ctrlr_set_keep_alive_timeout(ctrlr);
3191 		break;
3192 
3193 	case NVME_CTRLR_STATE_SET_HOST_ID:
3194 		rc = nvme_ctrlr_set_host_id(ctrlr);
3195 		break;
3196 
3197 	case NVME_CTRLR_STATE_READY:
3198 		SPDK_DEBUGLOG(nvme, "Ctrlr already in ready state\n");
3199 		return 0;
3200 
3201 	case NVME_CTRLR_STATE_ERROR:
3202 		SPDK_ERRLOG("Ctrlr %s is in error state\n", ctrlr->trid.traddr);
3203 		return -1;
3204 
3205 	case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY:
3206 	case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC:
3207 	case NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG:
3208 	case NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES:
3209 	case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS:
3210 	case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS:
3211 	case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS:
3212 	case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC:
3213 	case NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER:
3214 	case NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG:
3215 	case NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT:
3216 	case NVME_CTRLR_STATE_WAIT_FOR_HOST_ID:
3217 		spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
3218 		break;
3219 
3220 	default:
3221 		assert(0);
3222 		return -1;
3223 	}
3224 
3225 init_timeout:
3226 	/* Note: we use the ticks captured when we entered this function.
3227 	 * This covers environments where the SPDK process gets swapped out after
3228 	 * we tried to advance the state but before we check the timeout here.
3229 	 * It is not normal for this to happen, but harmless to handle it in this
3230 	 * way.
3231 	 */
3232 	if (ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE &&
3233 	    ticks > ctrlr->state_timeout_tsc) {
3234 		SPDK_ERRLOG("Initialization timed out in state %d\n", ctrlr->state);
3235 		return -1;
3236 	}
3237 
3238 	return rc;
3239 }
3240 
3241 int
3242 nvme_robust_mutex_init_recursive_shared(pthread_mutex_t *mtx)
3243 {
3244 	pthread_mutexattr_t attr;
3245 	int rc = 0;
3246 
3247 	if (pthread_mutexattr_init(&attr)) {
3248 		return -1;
3249 	}
3250 	if (pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_RECURSIVE) ||
3251 #ifndef __FreeBSD__
3252 	    pthread_mutexattr_setrobust(&attr, PTHREAD_MUTEX_ROBUST) ||
3253 	    pthread_mutexattr_setpshared(&attr, PTHREAD_PROCESS_SHARED) ||
3254 #endif
3255 	    pthread_mutex_init(mtx, &attr)) {
3256 		rc = -1;
3257 	}
3258 	pthread_mutexattr_destroy(&attr);
3259 	return rc;
3260 }
3261 
3262 int
3263 nvme_ctrlr_construct(struct spdk_nvme_ctrlr *ctrlr)
3264 {
3265 	int rc;
3266 
3267 	if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) {
3268 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT_DELAY, NVME_TIMEOUT_INFINITE);
3269 	} else {
3270 		nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE);
3271 	}
3272 
3273 	if (ctrlr->opts.admin_queue_size > SPDK_NVME_ADMIN_QUEUE_MAX_ENTRIES) {
3274 		SPDK_ERRLOG("admin_queue_size %u exceeds max defined by NVMe spec, use max value\n",
3275 			    ctrlr->opts.admin_queue_size);
3276 		ctrlr->opts.admin_queue_size = SPDK_NVME_ADMIN_QUEUE_MAX_ENTRIES;
3277 	}
3278 
3279 	if (ctrlr->opts.admin_queue_size < SPDK_NVME_ADMIN_QUEUE_MIN_ENTRIES) {
3280 		SPDK_ERRLOG("admin_queue_size %u is less than minimum defined by NVMe spec, use min value\n",
3281 			    ctrlr->opts.admin_queue_size);
3282 		ctrlr->opts.admin_queue_size = SPDK_NVME_ADMIN_QUEUE_MIN_ENTRIES;
3283 	}
3284 
3285 	ctrlr->flags = 0;
3286 	ctrlr->free_io_qids = NULL;
3287 	ctrlr->is_resetting = false;
3288 	ctrlr->is_failed = false;
3289 	ctrlr->is_destructed = false;
3290 
3291 	TAILQ_INIT(&ctrlr->active_io_qpairs);
3292 	STAILQ_INIT(&ctrlr->queued_aborts);
3293 	ctrlr->outstanding_aborts = 0;
3294 
3295 	ctrlr->ana_log_page = NULL;
3296 	ctrlr->ana_log_page_size = 0;
3297 
3298 	rc = nvme_robust_mutex_init_recursive_shared(&ctrlr->ctrlr_lock);
3299 	if (rc != 0) {
3300 		return rc;
3301 	}
3302 
3303 	TAILQ_INIT(&ctrlr->active_procs);
3304 
3305 	return rc;
3306 }
3307 
3308 /* This function should be called once at ctrlr initialization to set up constant properties. */
3309 void
3310 nvme_ctrlr_init_cap(struct spdk_nvme_ctrlr *ctrlr, const union spdk_nvme_cap_register *cap,
3311 		    const union spdk_nvme_vs_register *vs)
3312 {
3313 	ctrlr->cap = *cap;
3314 	ctrlr->vs = *vs;
3315 
3316 	if (ctrlr->cap.bits.ams & SPDK_NVME_CAP_AMS_WRR) {
3317 		ctrlr->flags |= SPDK_NVME_CTRLR_WRR_SUPPORTED;
3318 	}
3319 
3320 	ctrlr->min_page_size = 1u << (12 + ctrlr->cap.bits.mpsmin);
3321 
3322 	/* For now, always select page_size == min_page_size. */
3323 	ctrlr->page_size = ctrlr->min_page_size;
3324 
3325 	ctrlr->opts.io_queue_size = spdk_max(ctrlr->opts.io_queue_size, SPDK_NVME_IO_QUEUE_MIN_ENTRIES);
3326 	ctrlr->opts.io_queue_size = spdk_min(ctrlr->opts.io_queue_size, MAX_IO_QUEUE_ENTRIES);
3327 	ctrlr->opts.io_queue_size = spdk_min(ctrlr->opts.io_queue_size, ctrlr->cap.bits.mqes + 1u);
3328 
3329 	ctrlr->opts.io_queue_requests = spdk_max(ctrlr->opts.io_queue_requests, ctrlr->opts.io_queue_size);
3330 }
3331 
3332 void
3333 nvme_ctrlr_destruct_finish(struct spdk_nvme_ctrlr *ctrlr)
3334 {
3335 	pthread_mutex_destroy(&ctrlr->ctrlr_lock);
3336 }
3337 
3338 void
3339 nvme_ctrlr_destruct_async(struct spdk_nvme_ctrlr *ctrlr,
3340 			  struct nvme_ctrlr_detach_ctx *ctx)
3341 {
3342 	struct spdk_nvme_qpair *qpair, *tmp;
3343 
3344 	SPDK_DEBUGLOG(nvme, "Prepare to destruct SSD: %s\n", ctrlr->trid.traddr);
3345 
3346 	ctrlr->is_destructed = true;
3347 
3348 	spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
3349 
3350 	nvme_ctrlr_abort_queued_aborts(ctrlr);
3351 	nvme_transport_admin_qpair_abort_aers(ctrlr->adminq);
3352 
3353 	TAILQ_FOREACH_SAFE(qpair, &ctrlr->active_io_qpairs, tailq, tmp) {
3354 		spdk_nvme_ctrlr_free_io_qpair(qpair);
3355 	}
3356 
3357 	nvme_ctrlr_free_doorbell_buffer(ctrlr);
3358 	nvme_ctrlr_free_iocs_specific_data(ctrlr);
3359 
3360 	if (ctrlr->opts.no_shn_notification) {
3361 		SPDK_INFOLOG(nvme, "Disable SSD: %s without shutdown notification\n",
3362 			     ctrlr->trid.traddr);
3363 		nvme_ctrlr_disable(ctrlr);
3364 		ctx->shutdown_complete = true;
3365 	} else {
3366 		nvme_ctrlr_shutdown_async(ctrlr, ctx);
3367 	}
3368 }
3369 
3370 int
3371 nvme_ctrlr_destruct_poll_async(struct spdk_nvme_ctrlr *ctrlr,
3372 			       struct nvme_ctrlr_detach_ctx *ctx)
3373 {
3374 	int rc = 0;
3375 
3376 	if (!ctx->shutdown_complete) {
3377 		rc = nvme_ctrlr_shutdown_poll_async(ctrlr, ctx);
3378 		if (rc == -EAGAIN) {
3379 			return -EAGAIN;
3380 		}
3381 		/* Destruct ctrlr forcefully for any other error. */
3382 	}
3383 
3384 	if (ctx->cb_fn) {
3385 		ctx->cb_fn(ctrlr);
3386 	}
3387 
3388 	nvme_ctrlr_destruct_namespaces(ctrlr);
3389 
3390 	spdk_bit_array_free(&ctrlr->free_io_qids);
3391 
3392 	spdk_free(ctrlr->ana_log_page);
3393 	ctrlr->ana_log_page = NULL;
3394 	ctrlr->ana_log_page_size = 0;
3395 
3396 	nvme_transport_ctrlr_destruct(ctrlr);
3397 
3398 	return rc;
3399 }
3400 
3401 void
3402 nvme_ctrlr_destruct(struct spdk_nvme_ctrlr *ctrlr)
3403 {
3404 	struct nvme_ctrlr_detach_ctx ctx = {};
3405 	int rc;
3406 
3407 	nvme_ctrlr_destruct_async(ctrlr, &ctx);
3408 
3409 	while (1) {
3410 		rc = nvme_ctrlr_destruct_poll_async(ctrlr, &ctx);
3411 		if (rc != -EAGAIN) {
3412 			break;
3413 		}
3414 		nvme_delay(1000);
3415 	}
3416 }
3417 
3418 int
3419 nvme_ctrlr_submit_admin_request(struct spdk_nvme_ctrlr *ctrlr,
3420 				struct nvme_request *req)
3421 {
3422 	return nvme_qpair_submit_request(ctrlr->adminq, req);
3423 }
3424 
3425 static void
3426 nvme_keep_alive_completion(void *cb_ctx, const struct spdk_nvme_cpl *cpl)
3427 {
3428 	/* Do nothing */
3429 }
3430 
3431 /*
3432  * Check if we need to send a Keep Alive command.
3433  * Caller must hold ctrlr->ctrlr_lock.
3434  */
3435 static int
3436 nvme_ctrlr_keep_alive(struct spdk_nvme_ctrlr *ctrlr)
3437 {
3438 	uint64_t now;
3439 	struct nvme_request *req;
3440 	struct spdk_nvme_cmd *cmd;
3441 	int rc = 0;
3442 
3443 	now = spdk_get_ticks();
3444 	if (now < ctrlr->next_keep_alive_tick) {
3445 		return rc;
3446 	}
3447 
3448 	req = nvme_allocate_request_null(ctrlr->adminq, nvme_keep_alive_completion, NULL);
3449 	if (req == NULL) {
3450 		return rc;
3451 	}
3452 
3453 	cmd = &req->cmd;
3454 	cmd->opc = SPDK_NVME_OPC_KEEP_ALIVE;
3455 
3456 	rc = nvme_ctrlr_submit_admin_request(ctrlr, req);
3457 	if (rc != 0) {
3458 		SPDK_ERRLOG("Submitting Keep Alive failed\n");
3459 		rc = -ENXIO;
3460 	}
3461 
3462 	ctrlr->next_keep_alive_tick = now + ctrlr->keep_alive_interval_ticks;
3463 	return rc;
3464 }
3465 
3466 int32_t
3467 spdk_nvme_ctrlr_process_admin_completions(struct spdk_nvme_ctrlr *ctrlr)
3468 {
3469 	int32_t num_completions;
3470 	int32_t rc;
3471 
3472 	nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
3473 
3474 	if (ctrlr->keep_alive_interval_ticks) {
3475 		rc = nvme_ctrlr_keep_alive(ctrlr);
3476 		if (rc) {
3477 			nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
3478 			return rc;
3479 		}
3480 	}
3481 
3482 	rc = nvme_io_msg_process(ctrlr);
3483 	if (rc < 0) {
3484 		nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
3485 		return rc;
3486 	}
3487 	num_completions = rc;
3488 
3489 	rc = spdk_nvme_qpair_process_completions(ctrlr->adminq, 0);
3490 	nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
3491 
3492 	if (rc < 0) {
3493 		num_completions = rc;
3494 	} else {
3495 		num_completions += rc;
3496 	}
3497 
3498 	return num_completions;
3499 }
3500 
3501 const struct spdk_nvme_ctrlr_data *
3502 spdk_nvme_ctrlr_get_data(struct spdk_nvme_ctrlr *ctrlr)
3503 {
3504 	return &ctrlr->cdata;
3505 }
3506 
3507 union spdk_nvme_csts_register spdk_nvme_ctrlr_get_regs_csts(struct spdk_nvme_ctrlr *ctrlr)
3508 {
3509 	union spdk_nvme_csts_register csts;
3510 
3511 	if (nvme_ctrlr_get_csts(ctrlr, &csts)) {
3512 		csts.raw = SPDK_NVME_INVALID_REGISTER_VALUE;
3513 	}
3514 	return csts;
3515 }
3516 
3517 union spdk_nvme_cap_register spdk_nvme_ctrlr_get_regs_cap(struct spdk_nvme_ctrlr *ctrlr)
3518 {
3519 	return ctrlr->cap;
3520 }
3521 
3522 union spdk_nvme_vs_register spdk_nvme_ctrlr_get_regs_vs(struct spdk_nvme_ctrlr *ctrlr)
3523 {
3524 	return ctrlr->vs;
3525 }
3526 
3527 union spdk_nvme_cmbsz_register spdk_nvme_ctrlr_get_regs_cmbsz(struct spdk_nvme_ctrlr *ctrlr)
3528 {
3529 	union spdk_nvme_cmbsz_register cmbsz;
3530 
3531 	if (nvme_ctrlr_get_cmbsz(ctrlr, &cmbsz)) {
3532 		cmbsz.raw = 0;
3533 	}
3534 
3535 	return cmbsz;
3536 }
3537 
3538 uint32_t
3539 spdk_nvme_ctrlr_get_num_ns(struct spdk_nvme_ctrlr *ctrlr)
3540 {
3541 	return ctrlr->num_ns;
3542 }
3543 
3544 static int32_t
3545 nvme_ctrlr_active_ns_idx(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
3546 {
3547 	int32_t result = -1;
3548 
3549 	if (ctrlr->active_ns_list == NULL || nsid == 0 || nsid > ctrlr->num_ns) {
3550 		return result;
3551 	}
3552 
3553 	int32_t lower = 0;
3554 	int32_t upper = ctrlr->num_ns - 1;
3555 	int32_t mid;
3556 
3557 	while (lower <= upper) {
3558 		mid = lower + (upper - lower) / 2;
3559 		if (ctrlr->active_ns_list[mid] == nsid) {
3560 			result = mid;
3561 			break;
3562 		} else {
3563 			if (ctrlr->active_ns_list[mid] != 0 && ctrlr->active_ns_list[mid] < nsid) {
3564 				lower = mid + 1;
3565 			} else {
3566 				upper = mid - 1;
3567 			}
3568 
3569 		}
3570 	}
3571 
3572 	return result;
3573 }
3574 
3575 bool
3576 spdk_nvme_ctrlr_is_active_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
3577 {
3578 	return nvme_ctrlr_active_ns_idx(ctrlr, nsid) != -1;
3579 }
3580 
3581 uint32_t
3582 spdk_nvme_ctrlr_get_first_active_ns(struct spdk_nvme_ctrlr *ctrlr)
3583 {
3584 	return ctrlr->active_ns_list ? ctrlr->active_ns_list[0] : 0;
3585 }
3586 
3587 uint32_t
3588 spdk_nvme_ctrlr_get_next_active_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t prev_nsid)
3589 {
3590 	int32_t nsid_idx = nvme_ctrlr_active_ns_idx(ctrlr, prev_nsid);
3591 	if (ctrlr->active_ns_list && nsid_idx >= 0 && (uint32_t)nsid_idx < ctrlr->num_ns - 1) {
3592 		return ctrlr->active_ns_list[nsid_idx + 1];
3593 	}
3594 	return 0;
3595 }
3596 
3597 struct spdk_nvme_ns *
3598 spdk_nvme_ctrlr_get_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
3599 {
3600 	if (nsid < 1 || nsid > ctrlr->num_ns) {
3601 		return NULL;
3602 	}
3603 
3604 	return &ctrlr->ns[nsid - 1];
3605 }
3606 
3607 struct spdk_pci_device *
3608 spdk_nvme_ctrlr_get_pci_device(struct spdk_nvme_ctrlr *ctrlr)
3609 {
3610 	if (ctrlr == NULL) {
3611 		return NULL;
3612 	}
3613 
3614 	if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) {
3615 		return NULL;
3616 	}
3617 
3618 	return nvme_ctrlr_proc_get_devhandle(ctrlr);
3619 }
3620 
3621 uint32_t
3622 spdk_nvme_ctrlr_get_max_xfer_size(const struct spdk_nvme_ctrlr *ctrlr)
3623 {
3624 	return ctrlr->max_xfer_size;
3625 }
3626 
3627 void
3628 spdk_nvme_ctrlr_register_aer_callback(struct spdk_nvme_ctrlr *ctrlr,
3629 				      spdk_nvme_aer_cb aer_cb_fn,
3630 				      void *aer_cb_arg)
3631 {
3632 	struct spdk_nvme_ctrlr_process *active_proc;
3633 
3634 	nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
3635 
3636 	active_proc = nvme_ctrlr_get_current_process(ctrlr);
3637 	if (active_proc) {
3638 		active_proc->aer_cb_fn = aer_cb_fn;
3639 		active_proc->aer_cb_arg = aer_cb_arg;
3640 	}
3641 
3642 	nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
3643 }
3644 
3645 void
3646 spdk_nvme_ctrlr_register_timeout_callback(struct spdk_nvme_ctrlr *ctrlr,
3647 		uint64_t timeout_us, spdk_nvme_timeout_cb cb_fn, void *cb_arg)
3648 {
3649 	struct spdk_nvme_ctrlr_process	*active_proc;
3650 
3651 	nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
3652 
3653 	active_proc = nvme_ctrlr_get_current_process(ctrlr);
3654 	if (active_proc) {
3655 		active_proc->timeout_ticks = timeout_us * spdk_get_ticks_hz() / 1000000ULL;
3656 		active_proc->timeout_cb_fn = cb_fn;
3657 		active_proc->timeout_cb_arg = cb_arg;
3658 	}
3659 
3660 	ctrlr->timeout_enabled = true;
3661 
3662 	nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
3663 }
3664 
3665 bool
3666 spdk_nvme_ctrlr_is_log_page_supported(struct spdk_nvme_ctrlr *ctrlr, uint8_t log_page)
3667 {
3668 	/* No bounds check necessary, since log_page is uint8_t and log_page_supported has 256 entries */
3669 	SPDK_STATIC_ASSERT(sizeof(ctrlr->log_page_supported) == 256, "log_page_supported size mismatch");
3670 	return ctrlr->log_page_supported[log_page];
3671 }
3672 
3673 bool
3674 spdk_nvme_ctrlr_is_feature_supported(struct spdk_nvme_ctrlr *ctrlr, uint8_t feature_code)
3675 {
3676 	/* No bounds check necessary, since feature_code is uint8_t and feature_supported has 256 entries */
3677 	SPDK_STATIC_ASSERT(sizeof(ctrlr->feature_supported) == 256, "feature_supported size mismatch");
3678 	return ctrlr->feature_supported[feature_code];
3679 }
3680 
3681 int
3682 spdk_nvme_ctrlr_attach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
3683 			  struct spdk_nvme_ctrlr_list *payload)
3684 {
3685 	struct nvme_completion_poll_status	*status;
3686 	int					res;
3687 	struct spdk_nvme_ns			*ns;
3688 
3689 	status = calloc(1, sizeof(*status));
3690 	if (!status) {
3691 		SPDK_ERRLOG("Failed to allocate status tracker\n");
3692 		return -ENOMEM;
3693 	}
3694 
3695 	res = nvme_ctrlr_cmd_attach_ns(ctrlr, nsid, payload,
3696 				       nvme_completion_poll_cb, status);
3697 	if (res) {
3698 		free(status);
3699 		return res;
3700 	}
3701 	if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
3702 		SPDK_ERRLOG("spdk_nvme_ctrlr_attach_ns failed!\n");
3703 		if (!status->timed_out) {
3704 			free(status);
3705 		}
3706 		return -ENXIO;
3707 	}
3708 	free(status);
3709 
3710 	res = nvme_ctrlr_identify_active_ns(ctrlr);
3711 	if (res) {
3712 		return res;
3713 	}
3714 
3715 	ns = &ctrlr->ns[nsid - 1];
3716 	return nvme_ns_construct(ns, nsid, ctrlr);
3717 }
3718 
3719 int
3720 spdk_nvme_ctrlr_detach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
3721 			  struct spdk_nvme_ctrlr_list *payload)
3722 {
3723 	struct nvme_completion_poll_status	*status;
3724 	int					res;
3725 	struct spdk_nvme_ns			*ns;
3726 
3727 	status = calloc(1, sizeof(*status));
3728 	if (!status) {
3729 		SPDK_ERRLOG("Failed to allocate status tracker\n");
3730 		return -ENOMEM;
3731 	}
3732 
3733 	res = nvme_ctrlr_cmd_detach_ns(ctrlr, nsid, payload,
3734 				       nvme_completion_poll_cb, status);
3735 	if (res) {
3736 		free(status);
3737 		return res;
3738 	}
3739 	if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
3740 		SPDK_ERRLOG("spdk_nvme_ctrlr_detach_ns failed!\n");
3741 		if (!status->timed_out) {
3742 			free(status);
3743 		}
3744 		return -ENXIO;
3745 	}
3746 	free(status);
3747 
3748 	res = nvme_ctrlr_identify_active_ns(ctrlr);
3749 	if (res) {
3750 		return res;
3751 	}
3752 
3753 	ns = &ctrlr->ns[nsid - 1];
3754 	/* Inactive NS */
3755 	nvme_ns_destruct(ns);
3756 
3757 	return 0;
3758 }
3759 
3760 uint32_t
3761 spdk_nvme_ctrlr_create_ns(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_ns_data *payload)
3762 {
3763 	struct nvme_completion_poll_status	*status;
3764 	int					res;
3765 	uint32_t				nsid;
3766 	struct spdk_nvme_ns			*ns;
3767 
3768 	status = calloc(1, sizeof(*status));
3769 	if (!status) {
3770 		SPDK_ERRLOG("Failed to allocate status tracker\n");
3771 		return 0;
3772 	}
3773 
3774 	res = nvme_ctrlr_cmd_create_ns(ctrlr, payload, nvme_completion_poll_cb, status);
3775 	if (res) {
3776 		free(status);
3777 		return 0;
3778 	}
3779 	if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
3780 		SPDK_ERRLOG("spdk_nvme_ctrlr_create_ns failed!\n");
3781 		if (!status->timed_out) {
3782 			free(status);
3783 		}
3784 		return 0;
3785 	}
3786 
3787 	nsid = status->cpl.cdw0;
3788 	ns = &ctrlr->ns[nsid - 1];
3789 	free(status);
3790 	/* Inactive NS */
3791 	res = nvme_ns_construct(ns, nsid, ctrlr);
3792 	if (res) {
3793 		return 0;
3794 	}
3795 
3796 	/* Return the namespace ID that was created */
3797 	return nsid;
3798 }
3799 
3800 int
3801 spdk_nvme_ctrlr_delete_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid)
3802 {
3803 	struct nvme_completion_poll_status	*status;
3804 	int					res;
3805 	struct spdk_nvme_ns			*ns;
3806 
3807 	status = calloc(1, sizeof(*status));
3808 	if (!status) {
3809 		SPDK_ERRLOG("Failed to allocate status tracker\n");
3810 		return -ENOMEM;
3811 	}
3812 
3813 	res = nvme_ctrlr_cmd_delete_ns(ctrlr, nsid, nvme_completion_poll_cb, status);
3814 	if (res) {
3815 		free(status);
3816 		return res;
3817 	}
3818 	if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
3819 		SPDK_ERRLOG("spdk_nvme_ctrlr_delete_ns failed!\n");
3820 		if (!status->timed_out) {
3821 			free(status);
3822 		}
3823 		return -ENXIO;
3824 	}
3825 	free(status);
3826 
3827 	res = nvme_ctrlr_identify_active_ns(ctrlr);
3828 	if (res) {
3829 		return res;
3830 	}
3831 
3832 	ns = &ctrlr->ns[nsid - 1];
3833 	nvme_ns_destruct(ns);
3834 
3835 	return 0;
3836 }
3837 
3838 int
3839 spdk_nvme_ctrlr_format(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid,
3840 		       struct spdk_nvme_format *format)
3841 {
3842 	struct nvme_completion_poll_status	*status;
3843 	int					res;
3844 
3845 	status = calloc(1, sizeof(*status));
3846 	if (!status) {
3847 		SPDK_ERRLOG("Failed to allocate status tracker\n");
3848 		return -ENOMEM;
3849 	}
3850 
3851 	res = nvme_ctrlr_cmd_format(ctrlr, nsid, format, nvme_completion_poll_cb,
3852 				    status);
3853 	if (res) {
3854 		free(status);
3855 		return res;
3856 	}
3857 	if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
3858 		SPDK_ERRLOG("spdk_nvme_ctrlr_format failed!\n");
3859 		if (!status->timed_out) {
3860 			free(status);
3861 		}
3862 		return -ENXIO;
3863 	}
3864 	free(status);
3865 
3866 	return spdk_nvme_ctrlr_reset(ctrlr);
3867 }
3868 
3869 int
3870 spdk_nvme_ctrlr_update_firmware(struct spdk_nvme_ctrlr *ctrlr, void *payload, uint32_t size,
3871 				int slot, enum spdk_nvme_fw_commit_action commit_action, struct spdk_nvme_status *completion_status)
3872 {
3873 	struct spdk_nvme_fw_commit		fw_commit;
3874 	struct nvme_completion_poll_status	*status;
3875 	int					res;
3876 	unsigned int				size_remaining;
3877 	unsigned int				offset;
3878 	unsigned int				transfer;
3879 	void					*p;
3880 
3881 	if (!completion_status) {
3882 		return -EINVAL;
3883 	}
3884 	memset(completion_status, 0, sizeof(struct spdk_nvme_status));
3885 	if (size % 4) {
3886 		SPDK_ERRLOG("spdk_nvme_ctrlr_update_firmware invalid size!\n");
3887 		return -1;
3888 	}
3889 
3890 	/* Current support only for SPDK_NVME_FW_COMMIT_REPLACE_IMG
3891 	 * and SPDK_NVME_FW_COMMIT_REPLACE_AND_ENABLE_IMG
3892 	 */
3893 	if ((commit_action != SPDK_NVME_FW_COMMIT_REPLACE_IMG) &&
3894 	    (commit_action != SPDK_NVME_FW_COMMIT_REPLACE_AND_ENABLE_IMG)) {
3895 		SPDK_ERRLOG("spdk_nvme_ctrlr_update_firmware invalid command!\n");
3896 		return -1;
3897 	}
3898 
3899 	status = calloc(1, sizeof(*status));
3900 	if (!status) {
3901 		SPDK_ERRLOG("Failed to allocate status tracker\n");
3902 		return -ENOMEM;
3903 	}
3904 
3905 	/* Firmware download */
3906 	size_remaining = size;
3907 	offset = 0;
3908 	p = payload;
3909 
3910 	while (size_remaining > 0) {
3911 		transfer = spdk_min(size_remaining, ctrlr->min_page_size);
3912 
3913 		memset(status, 0, sizeof(*status));
3914 		res = nvme_ctrlr_cmd_fw_image_download(ctrlr, transfer, offset, p,
3915 						       nvme_completion_poll_cb,
3916 						       status);
3917 		if (res) {
3918 			free(status);
3919 			return res;
3920 		}
3921 
3922 		if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
3923 			SPDK_ERRLOG("spdk_nvme_ctrlr_fw_image_download failed!\n");
3924 			if (!status->timed_out) {
3925 				free(status);
3926 			}
3927 			return -ENXIO;
3928 		}
3929 		p += transfer;
3930 		offset += transfer;
3931 		size_remaining -= transfer;
3932 	}
3933 
3934 	/* Firmware commit */
3935 	memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit));
3936 	fw_commit.fs = slot;
3937 	fw_commit.ca = commit_action;
3938 
3939 	memset(status, 0, sizeof(*status));
3940 	res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit, nvme_completion_poll_cb,
3941 				       status);
3942 	if (res) {
3943 		free(status);
3944 		return res;
3945 	}
3946 
3947 	res = nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock);
3948 
3949 	memcpy(completion_status, &status->cpl.status, sizeof(struct spdk_nvme_status));
3950 
3951 	if (!status->timed_out) {
3952 		free(status);
3953 	}
3954 
3955 	if (res) {
3956 		if (completion_status->sct != SPDK_NVME_SCT_COMMAND_SPECIFIC ||
3957 		    completion_status->sc != SPDK_NVME_SC_FIRMWARE_REQ_NVM_RESET) {
3958 			if (completion_status->sct == SPDK_NVME_SCT_COMMAND_SPECIFIC  &&
3959 			    completion_status->sc == SPDK_NVME_SC_FIRMWARE_REQ_CONVENTIONAL_RESET) {
3960 				SPDK_NOTICELOG("firmware activation requires conventional reset to be performed. !\n");
3961 			} else {
3962 				SPDK_ERRLOG("nvme_ctrlr_cmd_fw_commit failed!\n");
3963 			}
3964 			return -ENXIO;
3965 		}
3966 	}
3967 
3968 	return spdk_nvme_ctrlr_reset(ctrlr);
3969 }
3970 
3971 int
3972 spdk_nvme_ctrlr_reserve_cmb(struct spdk_nvme_ctrlr *ctrlr)
3973 {
3974 	int rc, size;
3975 	union spdk_nvme_cmbsz_register cmbsz;
3976 
3977 	cmbsz = spdk_nvme_ctrlr_get_regs_cmbsz(ctrlr);
3978 
3979 	if (cmbsz.bits.rds == 0 || cmbsz.bits.wds == 0) {
3980 		return -ENOTSUP;
3981 	}
3982 
3983 	size = cmbsz.bits.sz * (0x1000 << (cmbsz.bits.szu * 4));
3984 
3985 	nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
3986 	rc = nvme_transport_ctrlr_reserve_cmb(ctrlr);
3987 	nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
3988 
3989 	if (rc < 0) {
3990 		return rc;
3991 	}
3992 
3993 	return size;
3994 }
3995 
3996 void *
3997 spdk_nvme_ctrlr_map_cmb(struct spdk_nvme_ctrlr *ctrlr, size_t *size)
3998 {
3999 	void *buf;
4000 
4001 	nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
4002 	buf = nvme_transport_ctrlr_map_cmb(ctrlr, size);
4003 	nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
4004 
4005 	return buf;
4006 }
4007 
4008 void
4009 spdk_nvme_ctrlr_unmap_cmb(struct spdk_nvme_ctrlr *ctrlr)
4010 {
4011 	nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
4012 	nvme_transport_ctrlr_unmap_cmb(ctrlr);
4013 	nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
4014 }
4015 
4016 bool
4017 spdk_nvme_ctrlr_is_discovery(struct spdk_nvme_ctrlr *ctrlr)
4018 {
4019 	assert(ctrlr);
4020 
4021 	return !strncmp(ctrlr->trid.subnqn, SPDK_NVMF_DISCOVERY_NQN,
4022 			strlen(SPDK_NVMF_DISCOVERY_NQN));
4023 }
4024 
4025 int
4026 spdk_nvme_ctrlr_security_receive(struct spdk_nvme_ctrlr *ctrlr, uint8_t secp,
4027 				 uint16_t spsp, uint8_t nssf, void *payload, size_t size)
4028 {
4029 	struct nvme_completion_poll_status	*status;
4030 	int					res;
4031 
4032 	status = calloc(1, sizeof(*status));
4033 	if (!status) {
4034 		SPDK_ERRLOG("Failed to allocate status tracker\n");
4035 		return -ENOMEM;
4036 	}
4037 
4038 	res = spdk_nvme_ctrlr_cmd_security_receive(ctrlr, secp, spsp, nssf, payload, size,
4039 			nvme_completion_poll_cb, status);
4040 	if (res) {
4041 		free(status);
4042 		return res;
4043 	}
4044 	if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
4045 		SPDK_ERRLOG("spdk_nvme_ctrlr_cmd_security_receive failed!\n");
4046 		if (!status->timed_out) {
4047 			free(status);
4048 		}
4049 		return -ENXIO;
4050 	}
4051 	free(status);
4052 
4053 	return 0;
4054 }
4055 
4056 int
4057 spdk_nvme_ctrlr_security_send(struct spdk_nvme_ctrlr *ctrlr, uint8_t secp,
4058 			      uint16_t spsp, uint8_t nssf, void *payload, size_t size)
4059 {
4060 	struct nvme_completion_poll_status	*status;
4061 	int					res;
4062 
4063 	status = calloc(1, sizeof(*status));
4064 	if (!status) {
4065 		SPDK_ERRLOG("Failed to allocate status tracker\n");
4066 		return -ENOMEM;
4067 	}
4068 
4069 	res = spdk_nvme_ctrlr_cmd_security_send(ctrlr, secp, spsp, nssf, payload, size,
4070 						nvme_completion_poll_cb,
4071 						status);
4072 	if (res) {
4073 		free(status);
4074 		return res;
4075 	}
4076 	if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) {
4077 		SPDK_ERRLOG("spdk_nvme_ctrlr_cmd_security_send failed!\n");
4078 		if (!status->timed_out) {
4079 			free(status);
4080 		}
4081 		return -ENXIO;
4082 	}
4083 
4084 	free(status);
4085 
4086 	return 0;
4087 }
4088 
4089 uint64_t
4090 spdk_nvme_ctrlr_get_flags(struct spdk_nvme_ctrlr *ctrlr)
4091 {
4092 	return ctrlr->flags;
4093 }
4094 
4095 const struct spdk_nvme_transport_id *
4096 spdk_nvme_ctrlr_get_transport_id(struct spdk_nvme_ctrlr *ctrlr)
4097 {
4098 	return &ctrlr->trid;
4099 }
4100 
4101 int32_t
4102 spdk_nvme_ctrlr_alloc_qid(struct spdk_nvme_ctrlr *ctrlr)
4103 {
4104 	uint32_t qid;
4105 
4106 	nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
4107 	qid = spdk_bit_array_find_first_set(ctrlr->free_io_qids, 1);
4108 	if (qid > ctrlr->opts.num_io_queues) {
4109 		SPDK_ERRLOG("No free I/O queue IDs\n");
4110 		nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
4111 		return -1;
4112 	}
4113 
4114 	spdk_bit_array_clear(ctrlr->free_io_qids, qid);
4115 	nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
4116 	return qid;
4117 }
4118 
4119 void
4120 spdk_nvme_ctrlr_free_qid(struct spdk_nvme_ctrlr *ctrlr, uint16_t qid)
4121 {
4122 	assert(qid <= ctrlr->opts.num_io_queues);
4123 
4124 	nvme_robust_mutex_lock(&ctrlr->ctrlr_lock);
4125 	spdk_bit_array_set(ctrlr->free_io_qids, qid);
4126 	nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
4127 }
4128 
4129 /* FIXME need to specify max number of iovs */
4130 int
4131 spdk_nvme_map_prps(void *prv, struct spdk_nvme_cmd *cmd, struct iovec *iovs,
4132 		   uint32_t len, size_t mps,
4133 		   void *(*gpa_to_vva)(void *prv, uint64_t addr, uint64_t len))
4134 {
4135 	uint64_t prp1, prp2;
4136 	void *vva;
4137 	uint32_t i;
4138 	uint32_t residue_len, nents;
4139 	uint64_t *prp_list;
4140 	int iovcnt;
4141 
4142 	prp1 = cmd->dptr.prp.prp1;
4143 	prp2 = cmd->dptr.prp.prp2;
4144 
4145 	/* PRP1 may started with unaligned page address */
4146 	residue_len = mps - (prp1 % mps);
4147 	residue_len = spdk_min(len, residue_len);
4148 
4149 	vva = gpa_to_vva(prv, prp1, residue_len);
4150 	if (spdk_unlikely(vva == NULL)) {
4151 		SPDK_ERRLOG("GPA to VVA failed\n");
4152 		return -1;
4153 	}
4154 	iovs[0].iov_base = vva;
4155 	iovs[0].iov_len = residue_len;
4156 	len -= residue_len;
4157 
4158 	if (len) {
4159 		if (spdk_unlikely(prp2 == 0)) {
4160 			SPDK_ERRLOG("no PRP2, %d remaining\n", len);
4161 			return -1;
4162 		}
4163 
4164 		if (len <= mps) {
4165 			/* 2 PRP used */
4166 			iovcnt = 2;
4167 			vva = gpa_to_vva(prv, prp2, len);
4168 			if (spdk_unlikely(vva == NULL)) {
4169 				SPDK_ERRLOG("no VVA for %#" PRIx64 ", len%#x\n",
4170 					    prp2, len);
4171 				return -1;
4172 			}
4173 			iovs[1].iov_base = vva;
4174 			iovs[1].iov_len = len;
4175 		} else {
4176 			/* PRP list used */
4177 			nents = (len + mps - 1) / mps;
4178 			vva = gpa_to_vva(prv, prp2, nents * sizeof(*prp_list));
4179 			if (spdk_unlikely(vva == NULL)) {
4180 				SPDK_ERRLOG("no VVA for %#" PRIx64 ", nents=%#x\n",
4181 					    prp2, nents);
4182 				return -1;
4183 			}
4184 			prp_list = vva;
4185 			i = 0;
4186 			while (len != 0) {
4187 				residue_len = spdk_min(len, mps);
4188 				vva = gpa_to_vva(prv, prp_list[i], residue_len);
4189 				if (spdk_unlikely(vva == NULL)) {
4190 					SPDK_ERRLOG("no VVA for %#" PRIx64 ", residue_len=%#x\n",
4191 						    prp_list[i], residue_len);
4192 					return -1;
4193 				}
4194 				iovs[i + 1].iov_base = vva;
4195 				iovs[i + 1].iov_len = residue_len;
4196 				len -= residue_len;
4197 				i++;
4198 			}
4199 			iovcnt = i + 1;
4200 		}
4201 	} else {
4202 		/* 1 PRP used */
4203 		iovcnt = 1;
4204 	}
4205 
4206 	return iovcnt;
4207 }
4208