1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (C) 2015 Intel Corporation. All rights reserved. 3 * Copyright (c) 2019-2021 Mellanox Technologies LTD. All rights reserved. 4 * Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 5 */ 6 7 #include "spdk/stdinc.h" 8 9 #include "nvme_internal.h" 10 #include "nvme_io_msg.h" 11 12 #include "spdk/env.h" 13 #include "spdk/string.h" 14 #include "spdk/endian.h" 15 16 struct nvme_active_ns_ctx; 17 18 static int nvme_ctrlr_construct_and_submit_aer(struct spdk_nvme_ctrlr *ctrlr, 19 struct nvme_async_event_request *aer); 20 static void nvme_ctrlr_identify_active_ns_async(struct nvme_active_ns_ctx *ctx); 21 static int nvme_ctrlr_identify_ns_async(struct spdk_nvme_ns *ns); 22 static int nvme_ctrlr_identify_ns_iocs_specific_async(struct spdk_nvme_ns *ns); 23 static int nvme_ctrlr_identify_id_desc_async(struct spdk_nvme_ns *ns); 24 static void nvme_ctrlr_init_cap(struct spdk_nvme_ctrlr *ctrlr); 25 static void nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state, 26 uint64_t timeout_in_ms); 27 28 static int 29 nvme_ns_cmp(struct spdk_nvme_ns *ns1, struct spdk_nvme_ns *ns2) 30 { 31 if (ns1->id < ns2->id) { 32 return -1; 33 } else if (ns1->id > ns2->id) { 34 return 1; 35 } else { 36 return 0; 37 } 38 } 39 40 RB_GENERATE_STATIC(nvme_ns_tree, spdk_nvme_ns, node, nvme_ns_cmp); 41 42 #define CTRLR_STRING(ctrlr) \ 43 ((ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_TCP || ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_RDMA) ? \ 44 ctrlr->trid.subnqn : ctrlr->trid.traddr) 45 46 #define NVME_CTRLR_ERRLOG(ctrlr, format, ...) \ 47 SPDK_ERRLOG("[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__); 48 49 #define NVME_CTRLR_WARNLOG(ctrlr, format, ...) \ 50 SPDK_WARNLOG("[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__); 51 52 #define NVME_CTRLR_NOTICELOG(ctrlr, format, ...) \ 53 SPDK_NOTICELOG("[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__); 54 55 #define NVME_CTRLR_INFOLOG(ctrlr, format, ...) \ 56 SPDK_INFOLOG(nvme, "[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__); 57 58 #ifdef DEBUG 59 #define NVME_CTRLR_DEBUGLOG(ctrlr, format, ...) \ 60 SPDK_DEBUGLOG(nvme, "[%s] " format, CTRLR_STRING(ctrlr), ##__VA_ARGS__); 61 #else 62 #define NVME_CTRLR_DEBUGLOG(ctrlr, ...) do { } while (0) 63 #endif 64 65 #define nvme_ctrlr_get_reg_async(ctrlr, reg, sz, cb_fn, cb_arg) \ 66 nvme_transport_ctrlr_get_reg_ ## sz ## _async(ctrlr, \ 67 offsetof(struct spdk_nvme_registers, reg), cb_fn, cb_arg) 68 69 #define nvme_ctrlr_set_reg_async(ctrlr, reg, sz, val, cb_fn, cb_arg) \ 70 nvme_transport_ctrlr_set_reg_ ## sz ## _async(ctrlr, \ 71 offsetof(struct spdk_nvme_registers, reg), val, cb_fn, cb_arg) 72 73 #define nvme_ctrlr_get_cc_async(ctrlr, cb_fn, cb_arg) \ 74 nvme_ctrlr_get_reg_async(ctrlr, cc, 4, cb_fn, cb_arg) 75 76 #define nvme_ctrlr_get_csts_async(ctrlr, cb_fn, cb_arg) \ 77 nvme_ctrlr_get_reg_async(ctrlr, csts, 4, cb_fn, cb_arg) 78 79 #define nvme_ctrlr_get_cap_async(ctrlr, cb_fn, cb_arg) \ 80 nvme_ctrlr_get_reg_async(ctrlr, cap, 8, cb_fn, cb_arg) 81 82 #define nvme_ctrlr_get_vs_async(ctrlr, cb_fn, cb_arg) \ 83 nvme_ctrlr_get_reg_async(ctrlr, vs, 4, cb_fn, cb_arg) 84 85 #define nvme_ctrlr_set_cc_async(ctrlr, value, cb_fn, cb_arg) \ 86 nvme_ctrlr_set_reg_async(ctrlr, cc, 4, value, cb_fn, cb_arg) 87 88 static int 89 nvme_ctrlr_get_cc(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cc_register *cc) 90 { 91 return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, cc.raw), 92 &cc->raw); 93 } 94 95 static int 96 nvme_ctrlr_get_csts(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_csts_register *csts) 97 { 98 return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, csts.raw), 99 &csts->raw); 100 } 101 102 int 103 nvme_ctrlr_get_cap(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cap_register *cap) 104 { 105 return nvme_transport_ctrlr_get_reg_8(ctrlr, offsetof(struct spdk_nvme_registers, cap.raw), 106 &cap->raw); 107 } 108 109 int 110 nvme_ctrlr_get_vs(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_vs_register *vs) 111 { 112 return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, vs.raw), 113 &vs->raw); 114 } 115 116 int 117 nvme_ctrlr_get_cmbsz(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_cmbsz_register *cmbsz) 118 { 119 return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, cmbsz.raw), 120 &cmbsz->raw); 121 } 122 123 int 124 nvme_ctrlr_get_pmrcap(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_pmrcap_register *pmrcap) 125 { 126 return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, pmrcap.raw), 127 &pmrcap->raw); 128 } 129 130 int 131 nvme_ctrlr_get_bpinfo(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_bpinfo_register *bpinfo) 132 { 133 return nvme_transport_ctrlr_get_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, bpinfo.raw), 134 &bpinfo->raw); 135 } 136 137 int 138 nvme_ctrlr_set_bprsel(struct spdk_nvme_ctrlr *ctrlr, union spdk_nvme_bprsel_register *bprsel) 139 { 140 return nvme_transport_ctrlr_set_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, bprsel.raw), 141 bprsel->raw); 142 } 143 144 int 145 nvme_ctrlr_set_bpmbl(struct spdk_nvme_ctrlr *ctrlr, uint64_t bpmbl_value) 146 { 147 return nvme_transport_ctrlr_set_reg_8(ctrlr, offsetof(struct spdk_nvme_registers, bpmbl), 148 bpmbl_value); 149 } 150 151 static int 152 nvme_ctrlr_set_nssr(struct spdk_nvme_ctrlr *ctrlr, uint32_t nssr_value) 153 { 154 return nvme_transport_ctrlr_set_reg_4(ctrlr, offsetof(struct spdk_nvme_registers, nssr), 155 nssr_value); 156 } 157 158 bool 159 nvme_ctrlr_multi_iocs_enabled(struct spdk_nvme_ctrlr *ctrlr) 160 { 161 return ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS && 162 ctrlr->opts.command_set == SPDK_NVME_CC_CSS_IOCS; 163 } 164 165 /* When the field in spdk_nvme_ctrlr_opts are changed and you change this function, please 166 * also update the nvme_ctrl_opts_init function in nvme_ctrlr.c 167 */ 168 void 169 spdk_nvme_ctrlr_get_default_ctrlr_opts(struct spdk_nvme_ctrlr_opts *opts, size_t opts_size) 170 { 171 assert(opts); 172 173 opts->opts_size = opts_size; 174 175 #define FIELD_OK(field) \ 176 offsetof(struct spdk_nvme_ctrlr_opts, field) + sizeof(opts->field) <= opts_size 177 178 #define SET_FIELD(field, value) \ 179 if (offsetof(struct spdk_nvme_ctrlr_opts, field) + sizeof(opts->field) <= opts_size) { \ 180 opts->field = value; \ 181 } \ 182 183 SET_FIELD(num_io_queues, DEFAULT_MAX_IO_QUEUES); 184 SET_FIELD(use_cmb_sqs, false); 185 SET_FIELD(no_shn_notification, false); 186 SET_FIELD(arb_mechanism, SPDK_NVME_CC_AMS_RR); 187 SET_FIELD(arbitration_burst, 0); 188 SET_FIELD(low_priority_weight, 0); 189 SET_FIELD(medium_priority_weight, 0); 190 SET_FIELD(high_priority_weight, 0); 191 SET_FIELD(keep_alive_timeout_ms, MIN_KEEP_ALIVE_TIMEOUT_IN_MS); 192 SET_FIELD(transport_retry_count, SPDK_NVME_DEFAULT_RETRY_COUNT); 193 SET_FIELD(io_queue_size, DEFAULT_IO_QUEUE_SIZE); 194 195 if (nvme_driver_init() == 0) { 196 if (FIELD_OK(hostnqn)) { 197 nvme_get_default_hostnqn(opts->hostnqn, sizeof(opts->hostnqn)); 198 } 199 200 if (FIELD_OK(extended_host_id)) { 201 memcpy(opts->extended_host_id, &g_spdk_nvme_driver->default_extended_host_id, 202 sizeof(opts->extended_host_id)); 203 } 204 205 } 206 207 SET_FIELD(io_queue_requests, DEFAULT_IO_QUEUE_REQUESTS); 208 209 if (FIELD_OK(src_addr)) { 210 memset(opts->src_addr, 0, sizeof(opts->src_addr)); 211 } 212 213 if (FIELD_OK(src_svcid)) { 214 memset(opts->src_svcid, 0, sizeof(opts->src_svcid)); 215 } 216 217 if (FIELD_OK(host_id)) { 218 memset(opts->host_id, 0, sizeof(opts->host_id)); 219 } 220 221 SET_FIELD(command_set, CHAR_BIT); 222 SET_FIELD(admin_timeout_ms, NVME_MAX_ADMIN_TIMEOUT_IN_SECS * 1000); 223 SET_FIELD(header_digest, false); 224 SET_FIELD(data_digest, false); 225 SET_FIELD(disable_error_logging, false); 226 SET_FIELD(transport_ack_timeout, SPDK_NVME_DEFAULT_TRANSPORT_ACK_TIMEOUT); 227 SET_FIELD(admin_queue_size, DEFAULT_ADMIN_QUEUE_SIZE); 228 SET_FIELD(fabrics_connect_timeout_us, NVME_FABRIC_CONNECT_COMMAND_TIMEOUT); 229 SET_FIELD(disable_read_ana_log_page, false); 230 SET_FIELD(disable_read_changed_ns_list_log_page, false); 231 SET_FIELD(tls_psk, NULL); 232 SET_FIELD(dhchap_key, NULL); 233 SET_FIELD(dhchap_ctrlr_key, NULL); 234 SET_FIELD(dhchap_digests, 235 SPDK_BIT(SPDK_NVMF_DHCHAP_HASH_SHA256) | 236 SPDK_BIT(SPDK_NVMF_DHCHAP_HASH_SHA384) | 237 SPDK_BIT(SPDK_NVMF_DHCHAP_HASH_SHA512)); 238 SET_FIELD(dhchap_dhgroups, 239 SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_NULL) | 240 SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_2048) | 241 SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_3072) | 242 SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_4096) | 243 SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_6144) | 244 SPDK_BIT(SPDK_NVMF_DHCHAP_DHGROUP_8192)); 245 246 if (FIELD_OK(psk)) { 247 memset(opts->psk, 0, sizeof(opts->psk)); 248 } 249 250 #undef FIELD_OK 251 #undef SET_FIELD 252 } 253 254 const struct spdk_nvme_ctrlr_opts * 255 spdk_nvme_ctrlr_get_opts(struct spdk_nvme_ctrlr *ctrlr) 256 { 257 return &ctrlr->opts; 258 } 259 260 /** 261 * This function will be called when the process allocates the IO qpair. 262 * Note: the ctrlr_lock must be held when calling this function. 263 */ 264 static void 265 nvme_ctrlr_proc_add_io_qpair(struct spdk_nvme_qpair *qpair) 266 { 267 struct spdk_nvme_ctrlr_process *active_proc; 268 struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr; 269 270 active_proc = nvme_ctrlr_get_current_process(ctrlr); 271 if (active_proc) { 272 TAILQ_INSERT_TAIL(&active_proc->allocated_io_qpairs, qpair, per_process_tailq); 273 qpair->active_proc = active_proc; 274 } 275 } 276 277 /** 278 * This function will be called when the process frees the IO qpair. 279 * Note: the ctrlr_lock must be held when calling this function. 280 */ 281 static void 282 nvme_ctrlr_proc_remove_io_qpair(struct spdk_nvme_qpair *qpair) 283 { 284 struct spdk_nvme_ctrlr_process *active_proc; 285 struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr; 286 struct spdk_nvme_qpair *active_qpair, *tmp_qpair; 287 288 active_proc = nvme_ctrlr_get_current_process(ctrlr); 289 if (!active_proc) { 290 return; 291 } 292 293 TAILQ_FOREACH_SAFE(active_qpair, &active_proc->allocated_io_qpairs, 294 per_process_tailq, tmp_qpair) { 295 if (active_qpair == qpair) { 296 TAILQ_REMOVE(&active_proc->allocated_io_qpairs, 297 active_qpair, per_process_tailq); 298 299 break; 300 } 301 } 302 } 303 304 void 305 spdk_nvme_ctrlr_get_default_io_qpair_opts(struct spdk_nvme_ctrlr *ctrlr, 306 struct spdk_nvme_io_qpair_opts *opts, 307 size_t opts_size) 308 { 309 assert(ctrlr); 310 311 assert(opts); 312 313 memset(opts, 0, opts_size); 314 315 #define FIELD_OK(field) \ 316 offsetof(struct spdk_nvme_io_qpair_opts, field) + sizeof(opts->field) <= opts_size 317 318 if (FIELD_OK(qprio)) { 319 opts->qprio = SPDK_NVME_QPRIO_URGENT; 320 } 321 322 if (FIELD_OK(io_queue_size)) { 323 opts->io_queue_size = ctrlr->opts.io_queue_size; 324 } 325 326 if (FIELD_OK(io_queue_requests)) { 327 opts->io_queue_requests = ctrlr->opts.io_queue_requests; 328 } 329 330 if (FIELD_OK(delay_cmd_submit)) { 331 opts->delay_cmd_submit = false; 332 } 333 334 if (FIELD_OK(sq.vaddr)) { 335 opts->sq.vaddr = NULL; 336 } 337 338 if (FIELD_OK(sq.paddr)) { 339 opts->sq.paddr = 0; 340 } 341 342 if (FIELD_OK(sq.buffer_size)) { 343 opts->sq.buffer_size = 0; 344 } 345 346 if (FIELD_OK(cq.vaddr)) { 347 opts->cq.vaddr = NULL; 348 } 349 350 if (FIELD_OK(cq.paddr)) { 351 opts->cq.paddr = 0; 352 } 353 354 if (FIELD_OK(cq.buffer_size)) { 355 opts->cq.buffer_size = 0; 356 } 357 358 if (FIELD_OK(create_only)) { 359 opts->create_only = false; 360 } 361 362 if (FIELD_OK(async_mode)) { 363 opts->async_mode = false; 364 } 365 366 #undef FIELD_OK 367 } 368 369 static struct spdk_nvme_qpair * 370 nvme_ctrlr_create_io_qpair(struct spdk_nvme_ctrlr *ctrlr, 371 const struct spdk_nvme_io_qpair_opts *opts) 372 { 373 int32_t qid; 374 struct spdk_nvme_qpair *qpair; 375 union spdk_nvme_cc_register cc; 376 377 if (!ctrlr) { 378 return NULL; 379 } 380 381 nvme_ctrlr_lock(ctrlr); 382 cc.raw = ctrlr->process_init_cc.raw; 383 384 if (opts->qprio & ~SPDK_NVME_CREATE_IO_SQ_QPRIO_MASK) { 385 nvme_ctrlr_unlock(ctrlr); 386 return NULL; 387 } 388 389 /* 390 * Only value SPDK_NVME_QPRIO_URGENT(0) is valid for the 391 * default round robin arbitration method. 392 */ 393 if ((cc.bits.ams == SPDK_NVME_CC_AMS_RR) && (opts->qprio != SPDK_NVME_QPRIO_URGENT)) { 394 NVME_CTRLR_ERRLOG(ctrlr, "invalid queue priority for default round robin arbitration method\n"); 395 nvme_ctrlr_unlock(ctrlr); 396 return NULL; 397 } 398 399 qid = spdk_nvme_ctrlr_alloc_qid(ctrlr); 400 if (qid < 0) { 401 nvme_ctrlr_unlock(ctrlr); 402 return NULL; 403 } 404 405 qpair = nvme_transport_ctrlr_create_io_qpair(ctrlr, qid, opts); 406 if (qpair == NULL) { 407 NVME_CTRLR_ERRLOG(ctrlr, "nvme_transport_ctrlr_create_io_qpair() failed\n"); 408 spdk_nvme_ctrlr_free_qid(ctrlr, qid); 409 nvme_ctrlr_unlock(ctrlr); 410 return NULL; 411 } 412 413 TAILQ_INSERT_TAIL(&ctrlr->active_io_qpairs, qpair, tailq); 414 415 nvme_ctrlr_proc_add_io_qpair(qpair); 416 417 nvme_ctrlr_unlock(ctrlr); 418 419 return qpair; 420 } 421 422 int 423 spdk_nvme_ctrlr_connect_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair) 424 { 425 int rc; 426 427 if (nvme_qpair_get_state(qpair) != NVME_QPAIR_DISCONNECTED) { 428 return -EISCONN; 429 } 430 431 nvme_ctrlr_lock(ctrlr); 432 rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair); 433 nvme_ctrlr_unlock(ctrlr); 434 435 if (ctrlr->quirks & NVME_QUIRK_DELAY_AFTER_QUEUE_ALLOC) { 436 spdk_delay_us(100); 437 } 438 439 return rc; 440 } 441 442 void 443 spdk_nvme_ctrlr_disconnect_io_qpair(struct spdk_nvme_qpair *qpair) 444 { 445 struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr; 446 447 nvme_ctrlr_lock(ctrlr); 448 nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair); 449 nvme_ctrlr_unlock(ctrlr); 450 } 451 452 struct spdk_nvme_qpair * 453 spdk_nvme_ctrlr_alloc_io_qpair(struct spdk_nvme_ctrlr *ctrlr, 454 const struct spdk_nvme_io_qpair_opts *user_opts, 455 size_t opts_size) 456 { 457 458 struct spdk_nvme_qpair *qpair = NULL; 459 struct spdk_nvme_io_qpair_opts opts; 460 int rc; 461 462 nvme_ctrlr_lock(ctrlr); 463 464 if (spdk_unlikely(ctrlr->state != NVME_CTRLR_STATE_READY)) { 465 /* When controller is resetting or initializing, free_io_qids is deleted or not created yet. 466 * We can't create IO qpair in that case */ 467 goto unlock; 468 } 469 470 /* 471 * Get the default options, then overwrite them with the user-provided options 472 * up to opts_size. 473 * 474 * This allows for extensions of the opts structure without breaking 475 * ABI compatibility. 476 */ 477 spdk_nvme_ctrlr_get_default_io_qpair_opts(ctrlr, &opts, sizeof(opts)); 478 if (user_opts) { 479 memcpy(&opts, user_opts, spdk_min(sizeof(opts), opts_size)); 480 481 /* If user passes buffers, make sure they're big enough for the requested queue size */ 482 if (opts.sq.vaddr) { 483 if (opts.sq.buffer_size < (opts.io_queue_size * sizeof(struct spdk_nvme_cmd))) { 484 NVME_CTRLR_ERRLOG(ctrlr, "sq buffer size %" PRIx64 " is too small for sq size %zx\n", 485 opts.sq.buffer_size, (opts.io_queue_size * sizeof(struct spdk_nvme_cmd))); 486 goto unlock; 487 } 488 } 489 if (opts.cq.vaddr) { 490 if (opts.cq.buffer_size < (opts.io_queue_size * sizeof(struct spdk_nvme_cpl))) { 491 NVME_CTRLR_ERRLOG(ctrlr, "cq buffer size %" PRIx64 " is too small for cq size %zx\n", 492 opts.cq.buffer_size, (opts.io_queue_size * sizeof(struct spdk_nvme_cpl))); 493 goto unlock; 494 } 495 } 496 } 497 498 qpair = nvme_ctrlr_create_io_qpair(ctrlr, &opts); 499 500 if (qpair == NULL || opts.create_only == true) { 501 goto unlock; 502 } 503 504 rc = spdk_nvme_ctrlr_connect_io_qpair(ctrlr, qpair); 505 if (rc != 0) { 506 NVME_CTRLR_ERRLOG(ctrlr, "nvme_transport_ctrlr_connect_io_qpair() failed\n"); 507 nvme_ctrlr_proc_remove_io_qpair(qpair); 508 TAILQ_REMOVE(&ctrlr->active_io_qpairs, qpair, tailq); 509 spdk_bit_array_set(ctrlr->free_io_qids, qpair->id); 510 nvme_transport_ctrlr_delete_io_qpair(ctrlr, qpair); 511 qpair = NULL; 512 goto unlock; 513 } 514 515 unlock: 516 nvme_ctrlr_unlock(ctrlr); 517 518 return qpair; 519 } 520 521 int 522 spdk_nvme_ctrlr_reconnect_io_qpair(struct spdk_nvme_qpair *qpair) 523 { 524 struct spdk_nvme_ctrlr *ctrlr; 525 enum nvme_qpair_state qpair_state; 526 int rc; 527 528 assert(qpair != NULL); 529 assert(nvme_qpair_is_admin_queue(qpair) == false); 530 assert(qpair->ctrlr != NULL); 531 532 ctrlr = qpair->ctrlr; 533 nvme_ctrlr_lock(ctrlr); 534 qpair_state = nvme_qpair_get_state(qpair); 535 536 if (ctrlr->is_removed) { 537 rc = -ENODEV; 538 goto out; 539 } 540 541 if (ctrlr->is_resetting || qpair_state == NVME_QPAIR_DISCONNECTING) { 542 rc = -EAGAIN; 543 goto out; 544 } 545 546 if (ctrlr->is_failed || qpair_state == NVME_QPAIR_DESTROYING) { 547 rc = -ENXIO; 548 goto out; 549 } 550 551 if (qpair_state != NVME_QPAIR_DISCONNECTED) { 552 rc = 0; 553 goto out; 554 } 555 556 rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair); 557 if (rc) { 558 rc = -EAGAIN; 559 goto out; 560 } 561 562 out: 563 nvme_ctrlr_unlock(ctrlr); 564 return rc; 565 } 566 567 spdk_nvme_qp_failure_reason 568 spdk_nvme_ctrlr_get_admin_qp_failure_reason(struct spdk_nvme_ctrlr *ctrlr) 569 { 570 return ctrlr->adminq->transport_failure_reason; 571 } 572 573 /* 574 * This internal function will attempt to take the controller 575 * lock before calling disconnect on a controller qpair. 576 * Functions already holding the controller lock should 577 * call nvme_transport_ctrlr_disconnect_qpair directly. 578 */ 579 void 580 nvme_ctrlr_disconnect_qpair(struct spdk_nvme_qpair *qpair) 581 { 582 struct spdk_nvme_ctrlr *ctrlr = qpair->ctrlr; 583 584 assert(ctrlr != NULL); 585 nvme_ctrlr_lock(ctrlr); 586 nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair); 587 nvme_ctrlr_unlock(ctrlr); 588 } 589 590 int 591 spdk_nvme_ctrlr_free_io_qpair(struct spdk_nvme_qpair *qpair) 592 { 593 struct spdk_nvme_ctrlr *ctrlr; 594 595 if (qpair == NULL) { 596 return 0; 597 } 598 599 ctrlr = qpair->ctrlr; 600 601 if (qpair->in_completion_context) { 602 /* 603 * There are many cases where it is convenient to delete an io qpair in the context 604 * of that qpair's completion routine. To handle this properly, set a flag here 605 * so that the completion routine will perform an actual delete after the context 606 * unwinds. 607 */ 608 qpair->delete_after_completion_context = 1; 609 return 0; 610 } 611 612 qpair->destroy_in_progress = 1; 613 614 nvme_transport_ctrlr_disconnect_qpair(ctrlr, qpair); 615 616 if (qpair->poll_group && (qpair->active_proc == nvme_ctrlr_get_current_process(ctrlr))) { 617 spdk_nvme_poll_group_remove(qpair->poll_group->group, qpair); 618 } 619 620 /* Do not retry. */ 621 nvme_qpair_set_state(qpair, NVME_QPAIR_DESTROYING); 622 623 /* In the multi-process case, a process may call this function on a foreign 624 * I/O qpair (i.e. one that this process did not create) when that qpairs process 625 * exits unexpectedly. In that case, we must not try to abort any reqs associated 626 * with that qpair, since the callbacks will also be foreign to this process. 627 */ 628 if (qpair->active_proc == nvme_ctrlr_get_current_process(ctrlr)) { 629 nvme_qpair_abort_all_queued_reqs(qpair); 630 } 631 632 nvme_ctrlr_lock(ctrlr); 633 634 nvme_ctrlr_proc_remove_io_qpair(qpair); 635 636 TAILQ_REMOVE(&ctrlr->active_io_qpairs, qpair, tailq); 637 spdk_nvme_ctrlr_free_qid(ctrlr, qpair->id); 638 639 nvme_transport_ctrlr_delete_io_qpair(ctrlr, qpair); 640 nvme_ctrlr_unlock(ctrlr); 641 return 0; 642 } 643 644 static void 645 nvme_ctrlr_construct_intel_support_log_page_list(struct spdk_nvme_ctrlr *ctrlr, 646 struct spdk_nvme_intel_log_page_directory *log_page_directory) 647 { 648 if (log_page_directory == NULL) { 649 return; 650 } 651 652 assert(ctrlr->cdata.vid == SPDK_PCI_VID_INTEL); 653 654 ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY] = true; 655 656 if (log_page_directory->read_latency_log_len || 657 (ctrlr->quirks & NVME_INTEL_QUIRK_READ_LATENCY)) { 658 ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_READ_CMD_LATENCY] = true; 659 } 660 if (log_page_directory->write_latency_log_len || 661 (ctrlr->quirks & NVME_INTEL_QUIRK_WRITE_LATENCY)) { 662 ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_WRITE_CMD_LATENCY] = true; 663 } 664 if (log_page_directory->temperature_statistics_log_len) { 665 ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_TEMPERATURE] = true; 666 } 667 if (log_page_directory->smart_log_len) { 668 ctrlr->log_page_supported[SPDK_NVME_INTEL_LOG_SMART] = true; 669 } 670 if (log_page_directory->marketing_description_log_len) { 671 ctrlr->log_page_supported[SPDK_NVME_INTEL_MARKETING_DESCRIPTION] = true; 672 } 673 } 674 675 struct intel_log_pages_ctx { 676 struct spdk_nvme_intel_log_page_directory log_page_directory; 677 struct spdk_nvme_ctrlr *ctrlr; 678 }; 679 680 static void 681 nvme_ctrlr_set_intel_support_log_pages_done(void *arg, const struct spdk_nvme_cpl *cpl) 682 { 683 struct intel_log_pages_ctx *ctx = arg; 684 struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr; 685 686 if (!spdk_nvme_cpl_is_error(cpl)) { 687 nvme_ctrlr_construct_intel_support_log_page_list(ctrlr, &ctx->log_page_directory); 688 } 689 690 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES, 691 ctrlr->opts.admin_timeout_ms); 692 free(ctx); 693 } 694 695 static int 696 nvme_ctrlr_set_intel_support_log_pages(struct spdk_nvme_ctrlr *ctrlr) 697 { 698 int rc = 0; 699 struct intel_log_pages_ctx *ctx; 700 701 ctx = calloc(1, sizeof(*ctx)); 702 if (!ctx) { 703 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES, 704 ctrlr->opts.admin_timeout_ms); 705 return 0; 706 } 707 708 ctx->ctrlr = ctrlr; 709 710 rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr, SPDK_NVME_INTEL_LOG_PAGE_DIRECTORY, 711 SPDK_NVME_GLOBAL_NS_TAG, &ctx->log_page_directory, 712 sizeof(struct spdk_nvme_intel_log_page_directory), 713 0, nvme_ctrlr_set_intel_support_log_pages_done, ctx); 714 if (rc != 0) { 715 free(ctx); 716 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES, 717 ctrlr->opts.admin_timeout_ms); 718 return 0; 719 } 720 721 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES, 722 ctrlr->opts.admin_timeout_ms); 723 724 return 0; 725 } 726 727 static int 728 nvme_ctrlr_alloc_ana_log_page(struct spdk_nvme_ctrlr *ctrlr) 729 { 730 uint32_t ana_log_page_size; 731 732 ana_log_page_size = sizeof(struct spdk_nvme_ana_page) + ctrlr->cdata.nanagrpid * 733 sizeof(struct spdk_nvme_ana_group_descriptor) + ctrlr->active_ns_count * 734 sizeof(uint32_t); 735 736 /* Number of active namespaces may have changed. 737 * Check if ANA log page fits into existing buffer. 738 */ 739 if (ana_log_page_size > ctrlr->ana_log_page_size) { 740 void *new_buffer; 741 742 if (ctrlr->ana_log_page) { 743 new_buffer = realloc(ctrlr->ana_log_page, ana_log_page_size); 744 } else { 745 new_buffer = calloc(1, ana_log_page_size); 746 } 747 748 if (!new_buffer) { 749 NVME_CTRLR_ERRLOG(ctrlr, "could not allocate ANA log page buffer, size %u\n", 750 ana_log_page_size); 751 return -ENXIO; 752 } 753 754 ctrlr->ana_log_page = new_buffer; 755 if (ctrlr->copied_ana_desc) { 756 new_buffer = realloc(ctrlr->copied_ana_desc, ana_log_page_size); 757 } else { 758 new_buffer = calloc(1, ana_log_page_size); 759 } 760 761 if (!new_buffer) { 762 NVME_CTRLR_ERRLOG(ctrlr, "could not allocate a buffer to parse ANA descriptor, size %u\n", 763 ana_log_page_size); 764 return -ENOMEM; 765 } 766 767 ctrlr->copied_ana_desc = new_buffer; 768 ctrlr->ana_log_page_size = ana_log_page_size; 769 } 770 771 return 0; 772 } 773 774 static int 775 nvme_ctrlr_update_ana_log_page(struct spdk_nvme_ctrlr *ctrlr) 776 { 777 struct nvme_completion_poll_status *status; 778 int rc; 779 780 rc = nvme_ctrlr_alloc_ana_log_page(ctrlr); 781 if (rc != 0) { 782 return rc; 783 } 784 785 status = calloc(1, sizeof(*status)); 786 if (status == NULL) { 787 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n"); 788 return -ENOMEM; 789 } 790 791 rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr, SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS, 792 SPDK_NVME_GLOBAL_NS_TAG, ctrlr->ana_log_page, 793 ctrlr->ana_log_page_size, 0, 794 nvme_completion_poll_cb, status); 795 if (rc != 0) { 796 free(status); 797 return rc; 798 } 799 800 if (nvme_wait_for_completion_robust_lock_timeout(ctrlr->adminq, status, &ctrlr->ctrlr_lock, 801 ctrlr->opts.admin_timeout_ms * 1000)) { 802 if (!status->timed_out) { 803 free(status); 804 } 805 return -EIO; 806 } 807 808 free(status); 809 return 0; 810 } 811 812 static int 813 nvme_ctrlr_update_ns_ana_states(const struct spdk_nvme_ana_group_descriptor *desc, 814 void *cb_arg) 815 { 816 struct spdk_nvme_ctrlr *ctrlr = cb_arg; 817 struct spdk_nvme_ns *ns; 818 uint32_t i, nsid; 819 820 for (i = 0; i < desc->num_of_nsid; i++) { 821 nsid = desc->nsid[i]; 822 if (nsid == 0 || nsid > ctrlr->cdata.nn) { 823 continue; 824 } 825 826 ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid); 827 assert(ns != NULL); 828 829 ns->ana_group_id = desc->ana_group_id; 830 ns->ana_state = desc->ana_state; 831 } 832 833 return 0; 834 } 835 836 int 837 nvme_ctrlr_parse_ana_log_page(struct spdk_nvme_ctrlr *ctrlr, 838 spdk_nvme_parse_ana_log_page_cb cb_fn, void *cb_arg) 839 { 840 struct spdk_nvme_ana_group_descriptor *copied_desc; 841 uint8_t *orig_desc; 842 uint32_t i, desc_size, copy_len; 843 int rc = 0; 844 845 if (ctrlr->ana_log_page == NULL) { 846 return -EINVAL; 847 } 848 849 copied_desc = ctrlr->copied_ana_desc; 850 851 orig_desc = (uint8_t *)ctrlr->ana_log_page + sizeof(struct spdk_nvme_ana_page); 852 copy_len = ctrlr->ana_log_page_size - sizeof(struct spdk_nvme_ana_page); 853 854 for (i = 0; i < ctrlr->ana_log_page->num_ana_group_desc; i++) { 855 memcpy(copied_desc, orig_desc, copy_len); 856 857 rc = cb_fn(copied_desc, cb_arg); 858 if (rc != 0) { 859 break; 860 } 861 862 desc_size = sizeof(struct spdk_nvme_ana_group_descriptor) + 863 copied_desc->num_of_nsid * sizeof(uint32_t); 864 orig_desc += desc_size; 865 copy_len -= desc_size; 866 } 867 868 return rc; 869 } 870 871 static int 872 nvme_ctrlr_set_supported_log_pages(struct spdk_nvme_ctrlr *ctrlr) 873 { 874 int rc = 0; 875 876 memset(ctrlr->log_page_supported, 0, sizeof(ctrlr->log_page_supported)); 877 /* Mandatory pages */ 878 ctrlr->log_page_supported[SPDK_NVME_LOG_ERROR] = true; 879 ctrlr->log_page_supported[SPDK_NVME_LOG_HEALTH_INFORMATION] = true; 880 ctrlr->log_page_supported[SPDK_NVME_LOG_FIRMWARE_SLOT] = true; 881 if (ctrlr->cdata.lpa.celp) { 882 ctrlr->log_page_supported[SPDK_NVME_LOG_COMMAND_EFFECTS_LOG] = true; 883 } 884 885 if (ctrlr->cdata.cmic.ana_reporting) { 886 ctrlr->log_page_supported[SPDK_NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS] = true; 887 if (!ctrlr->opts.disable_read_ana_log_page) { 888 rc = nvme_ctrlr_update_ana_log_page(ctrlr); 889 if (rc == 0) { 890 nvme_ctrlr_parse_ana_log_page(ctrlr, nvme_ctrlr_update_ns_ana_states, 891 ctrlr); 892 } 893 } 894 } 895 896 if (ctrlr->cdata.ctratt.bits.fdps) { 897 ctrlr->log_page_supported[SPDK_NVME_LOG_FDP_CONFIGURATIONS] = true; 898 ctrlr->log_page_supported[SPDK_NVME_LOG_RECLAIM_UNIT_HANDLE_USAGE] = true; 899 ctrlr->log_page_supported[SPDK_NVME_LOG_FDP_STATISTICS] = true; 900 ctrlr->log_page_supported[SPDK_NVME_LOG_FDP_EVENTS] = true; 901 } 902 903 if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL && 904 ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE && 905 !(ctrlr->quirks & NVME_INTEL_QUIRK_NO_LOG_PAGES)) { 906 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES, 907 ctrlr->opts.admin_timeout_ms); 908 909 } else { 910 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES, 911 ctrlr->opts.admin_timeout_ms); 912 913 } 914 915 return rc; 916 } 917 918 static void 919 nvme_ctrlr_set_intel_supported_features(struct spdk_nvme_ctrlr *ctrlr) 920 { 921 ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_MAX_LBA] = true; 922 ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_NATIVE_MAX_LBA] = true; 923 ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_POWER_GOVERNOR_SETTING] = true; 924 ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_SMBUS_ADDRESS] = true; 925 ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_LED_PATTERN] = true; 926 ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_RESET_TIMED_WORKLOAD_COUNTERS] = true; 927 ctrlr->feature_supported[SPDK_NVME_INTEL_FEAT_LATENCY_TRACKING] = true; 928 } 929 930 static void 931 nvme_ctrlr_set_arbitration_feature(struct spdk_nvme_ctrlr *ctrlr) 932 { 933 uint32_t cdw11; 934 struct nvme_completion_poll_status *status; 935 936 if (ctrlr->opts.arbitration_burst == 0) { 937 return; 938 } 939 940 if (ctrlr->opts.arbitration_burst > 7) { 941 NVME_CTRLR_WARNLOG(ctrlr, "Valid arbitration burst values is from 0-7\n"); 942 return; 943 } 944 945 status = calloc(1, sizeof(*status)); 946 if (!status) { 947 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n"); 948 return; 949 } 950 951 cdw11 = ctrlr->opts.arbitration_burst; 952 953 if (spdk_nvme_ctrlr_get_flags(ctrlr) & SPDK_NVME_CTRLR_WRR_SUPPORTED) { 954 cdw11 |= (uint32_t)ctrlr->opts.low_priority_weight << 8; 955 cdw11 |= (uint32_t)ctrlr->opts.medium_priority_weight << 16; 956 cdw11 |= (uint32_t)ctrlr->opts.high_priority_weight << 24; 957 } 958 959 if (spdk_nvme_ctrlr_cmd_set_feature(ctrlr, SPDK_NVME_FEAT_ARBITRATION, 960 cdw11, 0, NULL, 0, 961 nvme_completion_poll_cb, status) < 0) { 962 NVME_CTRLR_ERRLOG(ctrlr, "Set arbitration feature failed\n"); 963 free(status); 964 return; 965 } 966 967 if (nvme_wait_for_completion_timeout(ctrlr->adminq, status, 968 ctrlr->opts.admin_timeout_ms * 1000)) { 969 NVME_CTRLR_ERRLOG(ctrlr, "Timeout to set arbitration feature\n"); 970 } 971 972 if (!status->timed_out) { 973 free(status); 974 } 975 } 976 977 static void 978 nvme_ctrlr_set_supported_features(struct spdk_nvme_ctrlr *ctrlr) 979 { 980 memset(ctrlr->feature_supported, 0, sizeof(ctrlr->feature_supported)); 981 /* Mandatory features */ 982 ctrlr->feature_supported[SPDK_NVME_FEAT_ARBITRATION] = true; 983 ctrlr->feature_supported[SPDK_NVME_FEAT_POWER_MANAGEMENT] = true; 984 ctrlr->feature_supported[SPDK_NVME_FEAT_TEMPERATURE_THRESHOLD] = true; 985 ctrlr->feature_supported[SPDK_NVME_FEAT_ERROR_RECOVERY] = true; 986 ctrlr->feature_supported[SPDK_NVME_FEAT_NUMBER_OF_QUEUES] = true; 987 ctrlr->feature_supported[SPDK_NVME_FEAT_INTERRUPT_COALESCING] = true; 988 ctrlr->feature_supported[SPDK_NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION] = true; 989 ctrlr->feature_supported[SPDK_NVME_FEAT_WRITE_ATOMICITY] = true; 990 ctrlr->feature_supported[SPDK_NVME_FEAT_ASYNC_EVENT_CONFIGURATION] = true; 991 /* Optional features */ 992 if (ctrlr->cdata.vwc.present) { 993 ctrlr->feature_supported[SPDK_NVME_FEAT_VOLATILE_WRITE_CACHE] = true; 994 } 995 if (ctrlr->cdata.apsta.supported) { 996 ctrlr->feature_supported[SPDK_NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION] = true; 997 } 998 if (ctrlr->cdata.hmpre) { 999 ctrlr->feature_supported[SPDK_NVME_FEAT_HOST_MEM_BUFFER] = true; 1000 } 1001 if (ctrlr->cdata.vid == SPDK_PCI_VID_INTEL) { 1002 nvme_ctrlr_set_intel_supported_features(ctrlr); 1003 } 1004 1005 nvme_ctrlr_set_arbitration_feature(ctrlr); 1006 } 1007 1008 static void 1009 nvme_ctrlr_set_host_feature_done(void *arg, const struct spdk_nvme_cpl *cpl) 1010 { 1011 struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg; 1012 1013 spdk_free(ctrlr->tmp_ptr); 1014 ctrlr->tmp_ptr = NULL; 1015 1016 if (spdk_nvme_cpl_is_error(cpl)) { 1017 NVME_CTRLR_ERRLOG(ctrlr, "Set host behavior support feature failed: SC %x SCT %x\n", 1018 cpl->status.sc, cpl->status.sct); 1019 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 1020 return; 1021 } 1022 1023 ctrlr->feature_supported[SPDK_NVME_FEAT_HOST_BEHAVIOR_SUPPORT] = true; 1024 1025 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_DB_BUF_CFG, 1026 ctrlr->opts.admin_timeout_ms); 1027 } 1028 1029 /* We do not want to do add synchronous operation anymore. 1030 * We set the Host Behavior Support feature asynchronousin in different states. 1031 */ 1032 static int 1033 nvme_ctrlr_set_host_feature(struct spdk_nvme_ctrlr *ctrlr) 1034 { 1035 struct spdk_nvme_host_behavior *host; 1036 int rc; 1037 1038 if (!ctrlr->cdata.ctratt.bits.elbas) { 1039 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_DB_BUF_CFG, 1040 ctrlr->opts.admin_timeout_ms); 1041 return 0; 1042 } 1043 1044 ctrlr->tmp_ptr = spdk_dma_zmalloc(sizeof(struct spdk_nvme_host_behavior), 4096, NULL); 1045 if (!ctrlr->tmp_ptr) { 1046 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate host behavior support data\n"); 1047 rc = -ENOMEM; 1048 goto error; 1049 } 1050 1051 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_SET_HOST_FEATURE, 1052 ctrlr->opts.admin_timeout_ms); 1053 1054 host = ctrlr->tmp_ptr; 1055 1056 host->lbafee = 1; 1057 1058 rc = spdk_nvme_ctrlr_cmd_set_feature(ctrlr, SPDK_NVME_FEAT_HOST_BEHAVIOR_SUPPORT, 1059 0, 0, host, sizeof(struct spdk_nvme_host_behavior), 1060 nvme_ctrlr_set_host_feature_done, ctrlr); 1061 if (rc != 0) { 1062 NVME_CTRLR_ERRLOG(ctrlr, "Set host behavior support feature failed: %d\n", rc); 1063 goto error; 1064 } 1065 1066 return 0; 1067 1068 error: 1069 spdk_free(ctrlr->tmp_ptr); 1070 ctrlr->tmp_ptr = NULL; 1071 1072 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 1073 return rc; 1074 } 1075 1076 bool 1077 spdk_nvme_ctrlr_is_failed(struct spdk_nvme_ctrlr *ctrlr) 1078 { 1079 return ctrlr->is_failed; 1080 } 1081 1082 void 1083 nvme_ctrlr_fail(struct spdk_nvme_ctrlr *ctrlr, bool hot_remove) 1084 { 1085 /* 1086 * Set the flag here and leave the work failure of qpairs to 1087 * spdk_nvme_qpair_process_completions(). 1088 */ 1089 if (hot_remove) { 1090 ctrlr->is_removed = true; 1091 } 1092 1093 if (ctrlr->is_failed) { 1094 NVME_CTRLR_NOTICELOG(ctrlr, "already in failed state\n"); 1095 return; 1096 } 1097 1098 if (ctrlr->is_disconnecting) { 1099 NVME_CTRLR_DEBUGLOG(ctrlr, "already disconnecting\n"); 1100 return; 1101 } 1102 1103 ctrlr->is_failed = true; 1104 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 1105 nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq); 1106 NVME_CTRLR_ERRLOG(ctrlr, "in failed state.\n"); 1107 } 1108 1109 /** 1110 * This public API function will try to take the controller lock. 1111 * Any private functions being called from a thread already holding 1112 * the ctrlr lock should call nvme_ctrlr_fail directly. 1113 */ 1114 void 1115 spdk_nvme_ctrlr_fail(struct spdk_nvme_ctrlr *ctrlr) 1116 { 1117 nvme_ctrlr_lock(ctrlr); 1118 nvme_ctrlr_fail(ctrlr, false); 1119 nvme_ctrlr_unlock(ctrlr); 1120 } 1121 1122 static void 1123 nvme_ctrlr_shutdown_set_cc_done(void *_ctx, uint64_t value, const struct spdk_nvme_cpl *cpl) 1124 { 1125 struct nvme_ctrlr_detach_ctx *ctx = _ctx; 1126 struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr; 1127 1128 if (spdk_nvme_cpl_is_error(cpl)) { 1129 NVME_CTRLR_ERRLOG(ctrlr, "Failed to write CC.SHN\n"); 1130 ctx->shutdown_complete = true; 1131 return; 1132 } 1133 1134 if (ctrlr->opts.no_shn_notification) { 1135 ctx->shutdown_complete = true; 1136 return; 1137 } 1138 1139 /* 1140 * The NVMe specification defines RTD3E to be the time between 1141 * setting SHN = 1 until the controller will set SHST = 10b. 1142 * If the device doesn't report RTD3 entry latency, or if it 1143 * reports RTD3 entry latency less than 10 seconds, pick 1144 * 10 seconds as a reasonable amount of time to 1145 * wait before proceeding. 1146 */ 1147 NVME_CTRLR_DEBUGLOG(ctrlr, "RTD3E = %" PRIu32 " us\n", ctrlr->cdata.rtd3e); 1148 ctx->shutdown_timeout_ms = SPDK_CEIL_DIV(ctrlr->cdata.rtd3e, 1000); 1149 ctx->shutdown_timeout_ms = spdk_max(ctx->shutdown_timeout_ms, 10000); 1150 NVME_CTRLR_DEBUGLOG(ctrlr, "shutdown timeout = %" PRIu32 " ms\n", ctx->shutdown_timeout_ms); 1151 1152 ctx->shutdown_start_tsc = spdk_get_ticks(); 1153 ctx->state = NVME_CTRLR_DETACH_CHECK_CSTS; 1154 } 1155 1156 static void 1157 nvme_ctrlr_shutdown_get_cc_done(void *_ctx, uint64_t value, const struct spdk_nvme_cpl *cpl) 1158 { 1159 struct nvme_ctrlr_detach_ctx *ctx = _ctx; 1160 struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr; 1161 union spdk_nvme_cc_register cc; 1162 int rc; 1163 1164 if (spdk_nvme_cpl_is_error(cpl)) { 1165 NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n"); 1166 ctx->shutdown_complete = true; 1167 return; 1168 } 1169 1170 assert(value <= UINT32_MAX); 1171 cc.raw = (uint32_t)value; 1172 1173 if (ctrlr->opts.no_shn_notification) { 1174 NVME_CTRLR_INFOLOG(ctrlr, "Disable SSD without shutdown notification\n"); 1175 if (cc.bits.en == 0) { 1176 ctx->shutdown_complete = true; 1177 return; 1178 } 1179 1180 cc.bits.en = 0; 1181 } else { 1182 cc.bits.shn = SPDK_NVME_SHN_NORMAL; 1183 } 1184 1185 rc = nvme_ctrlr_set_cc_async(ctrlr, cc.raw, nvme_ctrlr_shutdown_set_cc_done, ctx); 1186 if (rc != 0) { 1187 NVME_CTRLR_ERRLOG(ctrlr, "Failed to write CC.SHN\n"); 1188 ctx->shutdown_complete = true; 1189 } 1190 } 1191 1192 static void 1193 nvme_ctrlr_shutdown_async(struct spdk_nvme_ctrlr *ctrlr, 1194 struct nvme_ctrlr_detach_ctx *ctx) 1195 { 1196 int rc; 1197 1198 if (ctrlr->is_removed) { 1199 ctx->shutdown_complete = true; 1200 return; 1201 } 1202 1203 if (ctrlr->adminq == NULL || 1204 ctrlr->adminq->transport_failure_reason != SPDK_NVME_QPAIR_FAILURE_NONE) { 1205 NVME_CTRLR_INFOLOG(ctrlr, "Adminq is not connected.\n"); 1206 ctx->shutdown_complete = true; 1207 return; 1208 } 1209 1210 ctx->state = NVME_CTRLR_DETACH_SET_CC; 1211 rc = nvme_ctrlr_get_cc_async(ctrlr, nvme_ctrlr_shutdown_get_cc_done, ctx); 1212 if (rc != 0) { 1213 NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n"); 1214 ctx->shutdown_complete = true; 1215 } 1216 } 1217 1218 static void 1219 nvme_ctrlr_shutdown_get_csts_done(void *_ctx, uint64_t value, const struct spdk_nvme_cpl *cpl) 1220 { 1221 struct nvme_ctrlr_detach_ctx *ctx = _ctx; 1222 1223 if (spdk_nvme_cpl_is_error(cpl)) { 1224 NVME_CTRLR_ERRLOG(ctx->ctrlr, "Failed to read the CSTS register\n"); 1225 ctx->shutdown_complete = true; 1226 return; 1227 } 1228 1229 assert(value <= UINT32_MAX); 1230 ctx->csts.raw = (uint32_t)value; 1231 ctx->state = NVME_CTRLR_DETACH_GET_CSTS_DONE; 1232 } 1233 1234 static int 1235 nvme_ctrlr_shutdown_poll_async(struct spdk_nvme_ctrlr *ctrlr, 1236 struct nvme_ctrlr_detach_ctx *ctx) 1237 { 1238 union spdk_nvme_csts_register csts; 1239 uint32_t ms_waited; 1240 1241 switch (ctx->state) { 1242 case NVME_CTRLR_DETACH_SET_CC: 1243 case NVME_CTRLR_DETACH_GET_CSTS: 1244 /* We're still waiting for the register operation to complete */ 1245 spdk_nvme_qpair_process_completions(ctrlr->adminq, 0); 1246 return -EAGAIN; 1247 1248 case NVME_CTRLR_DETACH_CHECK_CSTS: 1249 ctx->state = NVME_CTRLR_DETACH_GET_CSTS; 1250 if (nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_shutdown_get_csts_done, ctx)) { 1251 NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n"); 1252 return -EIO; 1253 } 1254 return -EAGAIN; 1255 1256 case NVME_CTRLR_DETACH_GET_CSTS_DONE: 1257 ctx->state = NVME_CTRLR_DETACH_CHECK_CSTS; 1258 break; 1259 1260 default: 1261 assert(0 && "Should never happen"); 1262 return -EINVAL; 1263 } 1264 1265 ms_waited = (spdk_get_ticks() - ctx->shutdown_start_tsc) * 1000 / spdk_get_ticks_hz(); 1266 csts.raw = ctx->csts.raw; 1267 1268 if (csts.bits.shst == SPDK_NVME_SHST_COMPLETE) { 1269 NVME_CTRLR_DEBUGLOG(ctrlr, "shutdown complete in %u milliseconds\n", ms_waited); 1270 return 0; 1271 } 1272 1273 if (ms_waited < ctx->shutdown_timeout_ms) { 1274 return -EAGAIN; 1275 } 1276 1277 NVME_CTRLR_ERRLOG(ctrlr, "did not shutdown within %u milliseconds\n", 1278 ctx->shutdown_timeout_ms); 1279 if (ctrlr->quirks & NVME_QUIRK_SHST_COMPLETE) { 1280 NVME_CTRLR_ERRLOG(ctrlr, "likely due to shutdown handling in the VMWare emulated NVMe SSD\n"); 1281 } 1282 1283 return 0; 1284 } 1285 1286 static inline uint64_t 1287 nvme_ctrlr_get_ready_timeout(struct spdk_nvme_ctrlr *ctrlr) 1288 { 1289 return ctrlr->cap.bits.to * 500; 1290 } 1291 1292 static void 1293 nvme_ctrlr_set_cc_en_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl) 1294 { 1295 struct spdk_nvme_ctrlr *ctrlr = ctx; 1296 1297 if (spdk_nvme_cpl_is_error(cpl)) { 1298 NVME_CTRLR_ERRLOG(ctrlr, "Failed to set the CC register\n"); 1299 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 1300 return; 1301 } 1302 1303 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1, 1304 nvme_ctrlr_get_ready_timeout(ctrlr)); 1305 } 1306 1307 static int 1308 nvme_ctrlr_enable(struct spdk_nvme_ctrlr *ctrlr) 1309 { 1310 union spdk_nvme_cc_register cc; 1311 int rc; 1312 1313 rc = nvme_transport_ctrlr_enable(ctrlr); 1314 if (rc != 0) { 1315 NVME_CTRLR_ERRLOG(ctrlr, "transport ctrlr_enable failed\n"); 1316 return rc; 1317 } 1318 1319 cc.raw = ctrlr->process_init_cc.raw; 1320 if (cc.bits.en != 0) { 1321 NVME_CTRLR_ERRLOG(ctrlr, "called with CC.EN = 1\n"); 1322 return -EINVAL; 1323 } 1324 1325 cc.bits.en = 1; 1326 cc.bits.css = 0; 1327 cc.bits.shn = 0; 1328 cc.bits.iosqes = 6; /* SQ entry size == 64 == 2^6 */ 1329 cc.bits.iocqes = 4; /* CQ entry size == 16 == 2^4 */ 1330 1331 /* Page size is 2 ^ (12 + mps). */ 1332 cc.bits.mps = spdk_u32log2(ctrlr->page_size) - 12; 1333 1334 /* 1335 * Since NVMe 1.0, a controller should have at least one bit set in CAP.CSS. 1336 * A controller that does not have any bit set in CAP.CSS is not spec compliant. 1337 * Try to support such a controller regardless. 1338 */ 1339 if (ctrlr->cap.bits.css == 0) { 1340 NVME_CTRLR_INFOLOG(ctrlr, "Drive reports no command sets supported. Assuming NVM is supported.\n"); 1341 ctrlr->cap.bits.css = SPDK_NVME_CAP_CSS_NVM; 1342 } 1343 1344 /* 1345 * If the user did not explicitly request a command set, or supplied a value larger than 1346 * what can be saved in CC.CSS, use the most reasonable default. 1347 */ 1348 if (ctrlr->opts.command_set >= CHAR_BIT) { 1349 if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS) { 1350 ctrlr->opts.command_set = SPDK_NVME_CC_CSS_IOCS; 1351 } else if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_NVM) { 1352 ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM; 1353 } else if (ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_NOIO) { 1354 ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NOIO; 1355 } else { 1356 /* Invalid supported bits detected, falling back to NVM. */ 1357 ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM; 1358 } 1359 } 1360 1361 /* Verify that the selected command set is supported by the controller. */ 1362 if (!(ctrlr->cap.bits.css & (1u << ctrlr->opts.command_set))) { 1363 NVME_CTRLR_DEBUGLOG(ctrlr, "Requested I/O command set %u but supported mask is 0x%x\n", 1364 ctrlr->opts.command_set, ctrlr->cap.bits.css); 1365 NVME_CTRLR_DEBUGLOG(ctrlr, "Falling back to NVM. Assuming NVM is supported.\n"); 1366 ctrlr->opts.command_set = SPDK_NVME_CC_CSS_NVM; 1367 } 1368 1369 cc.bits.css = ctrlr->opts.command_set; 1370 1371 switch (ctrlr->opts.arb_mechanism) { 1372 case SPDK_NVME_CC_AMS_RR: 1373 break; 1374 case SPDK_NVME_CC_AMS_WRR: 1375 if (SPDK_NVME_CAP_AMS_WRR & ctrlr->cap.bits.ams) { 1376 break; 1377 } 1378 return -EINVAL; 1379 case SPDK_NVME_CC_AMS_VS: 1380 if (SPDK_NVME_CAP_AMS_VS & ctrlr->cap.bits.ams) { 1381 break; 1382 } 1383 return -EINVAL; 1384 default: 1385 return -EINVAL; 1386 } 1387 1388 cc.bits.ams = ctrlr->opts.arb_mechanism; 1389 ctrlr->process_init_cc.raw = cc.raw; 1390 1391 if (nvme_ctrlr_set_cc_async(ctrlr, cc.raw, nvme_ctrlr_set_cc_en_done, ctrlr)) { 1392 NVME_CTRLR_ERRLOG(ctrlr, "set_cc() failed\n"); 1393 return -EIO; 1394 } 1395 1396 return 0; 1397 } 1398 1399 static const char * 1400 nvme_ctrlr_state_string(enum nvme_ctrlr_state state) 1401 { 1402 switch (state) { 1403 case NVME_CTRLR_STATE_INIT_DELAY: 1404 return "delay init"; 1405 case NVME_CTRLR_STATE_CONNECT_ADMINQ: 1406 return "connect adminq"; 1407 case NVME_CTRLR_STATE_WAIT_FOR_CONNECT_ADMINQ: 1408 return "wait for connect adminq"; 1409 case NVME_CTRLR_STATE_READ_VS: 1410 return "read vs"; 1411 case NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS: 1412 return "read vs wait for vs"; 1413 case NVME_CTRLR_STATE_READ_CAP: 1414 return "read cap"; 1415 case NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP: 1416 return "read cap wait for cap"; 1417 case NVME_CTRLR_STATE_CHECK_EN: 1418 return "check en"; 1419 case NVME_CTRLR_STATE_CHECK_EN_WAIT_FOR_CC: 1420 return "check en wait for cc"; 1421 case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1: 1422 return "disable and wait for CSTS.RDY = 1"; 1423 case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS: 1424 return "disable and wait for CSTS.RDY = 1 reg"; 1425 case NVME_CTRLR_STATE_SET_EN_0: 1426 return "set CC.EN = 0"; 1427 case NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC: 1428 return "set CC.EN = 0 wait for cc"; 1429 case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0: 1430 return "disable and wait for CSTS.RDY = 0"; 1431 case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS: 1432 return "disable and wait for CSTS.RDY = 0 reg"; 1433 case NVME_CTRLR_STATE_DISABLED: 1434 return "controller is disabled"; 1435 case NVME_CTRLR_STATE_ENABLE: 1436 return "enable controller by writing CC.EN = 1"; 1437 case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC: 1438 return "enable controller by writing CC.EN = 1 reg"; 1439 case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1: 1440 return "wait for CSTS.RDY = 1"; 1441 case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS: 1442 return "wait for CSTS.RDY = 1 reg"; 1443 case NVME_CTRLR_STATE_RESET_ADMIN_QUEUE: 1444 return "reset admin queue"; 1445 case NVME_CTRLR_STATE_IDENTIFY: 1446 return "identify controller"; 1447 case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY: 1448 return "wait for identify controller"; 1449 case NVME_CTRLR_STATE_CONFIGURE_AER: 1450 return "configure AER"; 1451 case NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER: 1452 return "wait for configure aer"; 1453 case NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT: 1454 return "set keep alive timeout"; 1455 case NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT: 1456 return "wait for set keep alive timeout"; 1457 case NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC: 1458 return "identify controller iocs specific"; 1459 case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC: 1460 return "wait for identify controller iocs specific"; 1461 case NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG: 1462 return "get zns cmd and effects log page"; 1463 case NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG: 1464 return "wait for get zns cmd and effects log page"; 1465 case NVME_CTRLR_STATE_SET_NUM_QUEUES: 1466 return "set number of queues"; 1467 case NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES: 1468 return "wait for set number of queues"; 1469 case NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS: 1470 return "identify active ns"; 1471 case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS: 1472 return "wait for identify active ns"; 1473 case NVME_CTRLR_STATE_IDENTIFY_NS: 1474 return "identify ns"; 1475 case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS: 1476 return "wait for identify ns"; 1477 case NVME_CTRLR_STATE_IDENTIFY_ID_DESCS: 1478 return "identify namespace id descriptors"; 1479 case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS: 1480 return "wait for identify namespace id descriptors"; 1481 case NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC: 1482 return "identify ns iocs specific"; 1483 case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC: 1484 return "wait for identify ns iocs specific"; 1485 case NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES: 1486 return "set supported log pages"; 1487 case NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES: 1488 return "set supported INTEL log pages"; 1489 case NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES: 1490 return "wait for supported INTEL log pages"; 1491 case NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES: 1492 return "set supported features"; 1493 case NVME_CTRLR_STATE_SET_HOST_FEATURE: 1494 return "set host behavior support feature"; 1495 case NVME_CTRLR_STATE_WAIT_FOR_SET_HOST_FEATURE: 1496 return "wait for set host behavior support feature"; 1497 case NVME_CTRLR_STATE_SET_DB_BUF_CFG: 1498 return "set doorbell buffer config"; 1499 case NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG: 1500 return "wait for doorbell buffer config"; 1501 case NVME_CTRLR_STATE_SET_HOST_ID: 1502 return "set host ID"; 1503 case NVME_CTRLR_STATE_WAIT_FOR_HOST_ID: 1504 return "wait for set host ID"; 1505 case NVME_CTRLR_STATE_TRANSPORT_READY: 1506 return "transport ready"; 1507 case NVME_CTRLR_STATE_READY: 1508 return "ready"; 1509 case NVME_CTRLR_STATE_ERROR: 1510 return "error"; 1511 case NVME_CTRLR_STATE_DISCONNECTED: 1512 return "disconnected"; 1513 } 1514 return "unknown"; 1515 }; 1516 1517 static void 1518 _nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state, 1519 uint64_t timeout_in_ms, bool quiet) 1520 { 1521 uint64_t ticks_per_ms, timeout_in_ticks, now_ticks; 1522 1523 ctrlr->state = state; 1524 if (timeout_in_ms == NVME_TIMEOUT_KEEP_EXISTING) { 1525 if (!quiet) { 1526 NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (keeping existing timeout)\n", 1527 nvme_ctrlr_state_string(ctrlr->state)); 1528 } 1529 return; 1530 } 1531 1532 if (timeout_in_ms == NVME_TIMEOUT_INFINITE) { 1533 goto inf; 1534 } 1535 1536 ticks_per_ms = spdk_get_ticks_hz() / 1000; 1537 if (timeout_in_ms > UINT64_MAX / ticks_per_ms) { 1538 NVME_CTRLR_ERRLOG(ctrlr, 1539 "Specified timeout would cause integer overflow. Defaulting to no timeout.\n"); 1540 goto inf; 1541 } 1542 1543 now_ticks = spdk_get_ticks(); 1544 timeout_in_ticks = timeout_in_ms * ticks_per_ms; 1545 if (timeout_in_ticks > UINT64_MAX - now_ticks) { 1546 NVME_CTRLR_ERRLOG(ctrlr, 1547 "Specified timeout would cause integer overflow. Defaulting to no timeout.\n"); 1548 goto inf; 1549 } 1550 1551 ctrlr->state_timeout_tsc = timeout_in_ticks + now_ticks; 1552 if (!quiet) { 1553 NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (timeout %" PRIu64 " ms)\n", 1554 nvme_ctrlr_state_string(ctrlr->state), timeout_in_ms); 1555 } 1556 return; 1557 inf: 1558 if (!quiet) { 1559 NVME_CTRLR_DEBUGLOG(ctrlr, "setting state to %s (no timeout)\n", 1560 nvme_ctrlr_state_string(ctrlr->state)); 1561 } 1562 ctrlr->state_timeout_tsc = NVME_TIMEOUT_INFINITE; 1563 } 1564 1565 static void 1566 nvme_ctrlr_set_state(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state, 1567 uint64_t timeout_in_ms) 1568 { 1569 _nvme_ctrlr_set_state(ctrlr, state, timeout_in_ms, false); 1570 } 1571 1572 static void 1573 nvme_ctrlr_set_state_quiet(struct spdk_nvme_ctrlr *ctrlr, enum nvme_ctrlr_state state, 1574 uint64_t timeout_in_ms) 1575 { 1576 _nvme_ctrlr_set_state(ctrlr, state, timeout_in_ms, true); 1577 } 1578 1579 static void 1580 nvme_ctrlr_free_zns_specific_data(struct spdk_nvme_ctrlr *ctrlr) 1581 { 1582 spdk_free(ctrlr->cdata_zns); 1583 ctrlr->cdata_zns = NULL; 1584 } 1585 1586 static void 1587 nvme_ctrlr_free_iocs_specific_data(struct spdk_nvme_ctrlr *ctrlr) 1588 { 1589 nvme_ctrlr_free_zns_specific_data(ctrlr); 1590 } 1591 1592 static void 1593 nvme_ctrlr_free_doorbell_buffer(struct spdk_nvme_ctrlr *ctrlr) 1594 { 1595 if (ctrlr->shadow_doorbell) { 1596 spdk_free(ctrlr->shadow_doorbell); 1597 ctrlr->shadow_doorbell = NULL; 1598 } 1599 1600 if (ctrlr->eventidx) { 1601 spdk_free(ctrlr->eventidx); 1602 ctrlr->eventidx = NULL; 1603 } 1604 } 1605 1606 static void 1607 nvme_ctrlr_set_doorbell_buffer_config_done(void *arg, const struct spdk_nvme_cpl *cpl) 1608 { 1609 struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg; 1610 1611 if (spdk_nvme_cpl_is_error(cpl)) { 1612 NVME_CTRLR_WARNLOG(ctrlr, "Doorbell buffer config failed\n"); 1613 } else { 1614 NVME_CTRLR_INFOLOG(ctrlr, "Doorbell buffer config enabled\n"); 1615 } 1616 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID, 1617 ctrlr->opts.admin_timeout_ms); 1618 } 1619 1620 static int 1621 nvme_ctrlr_set_doorbell_buffer_config(struct spdk_nvme_ctrlr *ctrlr) 1622 { 1623 int rc = 0; 1624 uint64_t prp1, prp2, len; 1625 1626 if (!ctrlr->cdata.oacs.doorbell_buffer_config) { 1627 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID, 1628 ctrlr->opts.admin_timeout_ms); 1629 return 0; 1630 } 1631 1632 if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) { 1633 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_ID, 1634 ctrlr->opts.admin_timeout_ms); 1635 return 0; 1636 } 1637 1638 /* only 1 page size for doorbell buffer */ 1639 ctrlr->shadow_doorbell = spdk_zmalloc(ctrlr->page_size, ctrlr->page_size, 1640 NULL, SPDK_ENV_LCORE_ID_ANY, 1641 SPDK_MALLOC_DMA | SPDK_MALLOC_SHARE); 1642 if (ctrlr->shadow_doorbell == NULL) { 1643 rc = -ENOMEM; 1644 goto error; 1645 } 1646 1647 len = ctrlr->page_size; 1648 prp1 = spdk_vtophys(ctrlr->shadow_doorbell, &len); 1649 if (prp1 == SPDK_VTOPHYS_ERROR || len != ctrlr->page_size) { 1650 rc = -EFAULT; 1651 goto error; 1652 } 1653 1654 ctrlr->eventidx = spdk_zmalloc(ctrlr->page_size, ctrlr->page_size, 1655 NULL, SPDK_ENV_LCORE_ID_ANY, 1656 SPDK_MALLOC_DMA | SPDK_MALLOC_SHARE); 1657 if (ctrlr->eventidx == NULL) { 1658 rc = -ENOMEM; 1659 goto error; 1660 } 1661 1662 len = ctrlr->page_size; 1663 prp2 = spdk_vtophys(ctrlr->eventidx, &len); 1664 if (prp2 == SPDK_VTOPHYS_ERROR || len != ctrlr->page_size) { 1665 rc = -EFAULT; 1666 goto error; 1667 } 1668 1669 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG, 1670 ctrlr->opts.admin_timeout_ms); 1671 1672 rc = nvme_ctrlr_cmd_doorbell_buffer_config(ctrlr, prp1, prp2, 1673 nvme_ctrlr_set_doorbell_buffer_config_done, ctrlr); 1674 if (rc != 0) { 1675 goto error; 1676 } 1677 1678 return 0; 1679 1680 error: 1681 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 1682 nvme_ctrlr_free_doorbell_buffer(ctrlr); 1683 return rc; 1684 } 1685 1686 void 1687 nvme_ctrlr_abort_queued_aborts(struct spdk_nvme_ctrlr *ctrlr) 1688 { 1689 struct nvme_request *req, *tmp; 1690 struct spdk_nvme_cpl cpl = {}; 1691 1692 cpl.status.sc = SPDK_NVME_SC_ABORTED_SQ_DELETION; 1693 cpl.status.sct = SPDK_NVME_SCT_GENERIC; 1694 1695 STAILQ_FOREACH_SAFE(req, &ctrlr->queued_aborts, stailq, tmp) { 1696 STAILQ_REMOVE_HEAD(&ctrlr->queued_aborts, stailq); 1697 ctrlr->outstanding_aborts++; 1698 1699 nvme_complete_request(req->cb_fn, req->cb_arg, req->qpair, req, &cpl); 1700 } 1701 } 1702 1703 static int 1704 nvme_ctrlr_disconnect(struct spdk_nvme_ctrlr *ctrlr) 1705 { 1706 if (ctrlr->is_resetting || ctrlr->is_removed) { 1707 /* 1708 * Controller is already resetting or has been removed. Return 1709 * immediately since there is no need to kick off another 1710 * reset in these cases. 1711 */ 1712 return ctrlr->is_resetting ? -EBUSY : -ENXIO; 1713 } 1714 1715 ctrlr->is_resetting = true; 1716 ctrlr->is_failed = false; 1717 ctrlr->is_disconnecting = true; 1718 ctrlr->prepare_for_reset = true; 1719 1720 NVME_CTRLR_NOTICELOG(ctrlr, "resetting controller\n"); 1721 1722 /* Disable keep-alive, it'll be re-enabled as part of the init process */ 1723 ctrlr->keep_alive_interval_ticks = 0; 1724 1725 /* Abort all of the queued abort requests */ 1726 nvme_ctrlr_abort_queued_aborts(ctrlr); 1727 1728 nvme_transport_admin_qpair_abort_aers(ctrlr->adminq); 1729 1730 ctrlr->adminq->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL; 1731 nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq); 1732 1733 return 0; 1734 } 1735 1736 static void 1737 nvme_ctrlr_disconnect_done(struct spdk_nvme_ctrlr *ctrlr) 1738 { 1739 assert(ctrlr->is_failed == false); 1740 ctrlr->is_disconnecting = false; 1741 1742 /* Doorbell buffer config is invalid during reset */ 1743 nvme_ctrlr_free_doorbell_buffer(ctrlr); 1744 1745 /* I/O Command Set Specific Identify Controller data is invalidated during reset */ 1746 nvme_ctrlr_free_iocs_specific_data(ctrlr); 1747 1748 spdk_bit_array_free(&ctrlr->free_io_qids); 1749 1750 /* Set the state back to DISCONNECTED to cause a full hardware reset. */ 1751 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISCONNECTED, NVME_TIMEOUT_INFINITE); 1752 } 1753 1754 int 1755 spdk_nvme_ctrlr_disconnect(struct spdk_nvme_ctrlr *ctrlr) 1756 { 1757 int rc; 1758 1759 nvme_ctrlr_lock(ctrlr); 1760 rc = nvme_ctrlr_disconnect(ctrlr); 1761 nvme_ctrlr_unlock(ctrlr); 1762 1763 return rc; 1764 } 1765 1766 void 1767 spdk_nvme_ctrlr_reconnect_async(struct spdk_nvme_ctrlr *ctrlr) 1768 { 1769 nvme_ctrlr_lock(ctrlr); 1770 1771 ctrlr->prepare_for_reset = false; 1772 1773 /* Set the state back to INIT to cause a full hardware reset. */ 1774 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE); 1775 1776 /* Return without releasing ctrlr_lock. ctrlr_lock will be released when 1777 * spdk_nvme_ctrlr_reset_poll_async() returns 0. 1778 */ 1779 } 1780 1781 int 1782 nvme_ctrlr_reinitialize_io_qpair(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_qpair *qpair) 1783 { 1784 bool async; 1785 int rc; 1786 1787 if (nvme_ctrlr_get_current_process(ctrlr) != qpair->active_proc || 1788 spdk_nvme_ctrlr_is_fabrics(ctrlr) || nvme_qpair_is_admin_queue(qpair)) { 1789 assert(false); 1790 return -EINVAL; 1791 } 1792 1793 /* Force a synchronous connect. */ 1794 async = qpair->async; 1795 qpair->async = false; 1796 rc = nvme_transport_ctrlr_connect_qpair(ctrlr, qpair); 1797 qpair->async = async; 1798 1799 if (rc != 0) { 1800 qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL; 1801 } 1802 1803 return rc; 1804 } 1805 1806 /** 1807 * This function will be called when the controller is being reinitialized. 1808 * Note: the ctrlr_lock must be held when calling this function. 1809 */ 1810 int 1811 spdk_nvme_ctrlr_reconnect_poll_async(struct spdk_nvme_ctrlr *ctrlr) 1812 { 1813 struct spdk_nvme_ns *ns, *tmp_ns; 1814 struct spdk_nvme_qpair *qpair; 1815 int rc = 0, rc_tmp = 0; 1816 1817 if (nvme_ctrlr_process_init(ctrlr) != 0) { 1818 NVME_CTRLR_ERRLOG(ctrlr, "controller reinitialization failed\n"); 1819 rc = -1; 1820 } 1821 if (ctrlr->state != NVME_CTRLR_STATE_READY && rc != -1) { 1822 return -EAGAIN; 1823 } 1824 1825 /* 1826 * For non-fabrics controllers, the memory locations of the transport qpair 1827 * don't change when the controller is reset. They simply need to be 1828 * re-enabled with admin commands to the controller. For fabric 1829 * controllers we need to disconnect and reconnect the qpair on its 1830 * own thread outside of the context of the reset. 1831 */ 1832 if (rc == 0 && !spdk_nvme_ctrlr_is_fabrics(ctrlr)) { 1833 /* Reinitialize qpairs */ 1834 TAILQ_FOREACH(qpair, &ctrlr->active_io_qpairs, tailq) { 1835 /* Always clear the qid bit here, even for a foreign qpair. We need 1836 * to make sure another process doesn't get the chance to grab that 1837 * qid. 1838 */ 1839 assert(spdk_bit_array_get(ctrlr->free_io_qids, qpair->id)); 1840 spdk_bit_array_clear(ctrlr->free_io_qids, qpair->id); 1841 if (nvme_ctrlr_get_current_process(ctrlr) != qpair->active_proc) { 1842 /* 1843 * We cannot reinitialize a foreign qpair. The qpair's owning 1844 * process will take care of it. Set failure reason to FAILURE_RESET 1845 * to ensure that happens. 1846 */ 1847 qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_RESET; 1848 continue; 1849 } 1850 rc_tmp = nvme_ctrlr_reinitialize_io_qpair(ctrlr, qpair); 1851 if (rc_tmp != 0) { 1852 rc = rc_tmp; 1853 } 1854 } 1855 } 1856 1857 /* 1858 * Take this opportunity to remove inactive namespaces. During a reset namespace 1859 * handles can be invalidated. 1860 */ 1861 RB_FOREACH_SAFE(ns, nvme_ns_tree, &ctrlr->ns, tmp_ns) { 1862 if (!ns->active) { 1863 RB_REMOVE(nvme_ns_tree, &ctrlr->ns, ns); 1864 spdk_free(ns); 1865 } 1866 } 1867 1868 if (rc) { 1869 nvme_ctrlr_fail(ctrlr, false); 1870 } 1871 ctrlr->is_resetting = false; 1872 1873 nvme_ctrlr_unlock(ctrlr); 1874 1875 if (!ctrlr->cdata.oaes.ns_attribute_notices) { 1876 /* 1877 * If controller doesn't support ns_attribute_notices and 1878 * namespace attributes change (e.g. number of namespaces) 1879 * we need to update system handling device reset. 1880 */ 1881 nvme_io_msg_ctrlr_update(ctrlr); 1882 } 1883 1884 return rc; 1885 } 1886 1887 /* 1888 * For PCIe transport, spdk_nvme_ctrlr_disconnect() will do a Controller Level Reset 1889 * (Change CC.EN from 1 to 0) as a operation to disconnect the admin qpair. 1890 * The following two functions are added to do a Controller Level Reset. They have 1891 * to be called under the nvme controller's lock. 1892 */ 1893 void 1894 nvme_ctrlr_disable(struct spdk_nvme_ctrlr *ctrlr) 1895 { 1896 assert(ctrlr->is_disconnecting == true); 1897 1898 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN, NVME_TIMEOUT_INFINITE); 1899 } 1900 1901 int 1902 nvme_ctrlr_disable_poll(struct spdk_nvme_ctrlr *ctrlr) 1903 { 1904 int rc = 0; 1905 1906 if (nvme_ctrlr_process_init(ctrlr) != 0) { 1907 NVME_CTRLR_ERRLOG(ctrlr, "failed to disable controller\n"); 1908 rc = -1; 1909 } 1910 1911 if (ctrlr->state != NVME_CTRLR_STATE_DISABLED && rc != -1) { 1912 return -EAGAIN; 1913 } 1914 1915 return rc; 1916 } 1917 1918 static void 1919 nvme_ctrlr_fail_io_qpairs(struct spdk_nvme_ctrlr *ctrlr) 1920 { 1921 struct spdk_nvme_qpair *qpair; 1922 1923 TAILQ_FOREACH(qpair, &ctrlr->active_io_qpairs, tailq) { 1924 qpair->transport_failure_reason = SPDK_NVME_QPAIR_FAILURE_LOCAL; 1925 } 1926 } 1927 1928 int 1929 spdk_nvme_ctrlr_reset(struct spdk_nvme_ctrlr *ctrlr) 1930 { 1931 int rc; 1932 1933 nvme_ctrlr_lock(ctrlr); 1934 1935 rc = nvme_ctrlr_disconnect(ctrlr); 1936 if (rc == 0) { 1937 nvme_ctrlr_fail_io_qpairs(ctrlr); 1938 } 1939 1940 nvme_ctrlr_unlock(ctrlr); 1941 1942 if (rc != 0) { 1943 if (rc == -EBUSY) { 1944 rc = 0; 1945 } 1946 return rc; 1947 } 1948 1949 while (1) { 1950 rc = spdk_nvme_ctrlr_process_admin_completions(ctrlr); 1951 if (rc == -ENXIO) { 1952 break; 1953 } 1954 } 1955 1956 spdk_nvme_ctrlr_reconnect_async(ctrlr); 1957 1958 while (true) { 1959 rc = spdk_nvme_ctrlr_reconnect_poll_async(ctrlr); 1960 if (rc != -EAGAIN) { 1961 break; 1962 } 1963 } 1964 1965 return rc; 1966 } 1967 1968 int 1969 spdk_nvme_ctrlr_reset_subsystem(struct spdk_nvme_ctrlr *ctrlr) 1970 { 1971 union spdk_nvme_cap_register cap; 1972 int rc = 0; 1973 1974 cap = spdk_nvme_ctrlr_get_regs_cap(ctrlr); 1975 if (cap.bits.nssrs == 0) { 1976 NVME_CTRLR_WARNLOG(ctrlr, "subsystem reset is not supported\n"); 1977 return -ENOTSUP; 1978 } 1979 1980 NVME_CTRLR_NOTICELOG(ctrlr, "resetting subsystem\n"); 1981 nvme_ctrlr_lock(ctrlr); 1982 ctrlr->is_resetting = true; 1983 rc = nvme_ctrlr_set_nssr(ctrlr, SPDK_NVME_NSSR_VALUE); 1984 ctrlr->is_resetting = false; 1985 1986 nvme_ctrlr_unlock(ctrlr); 1987 /* 1988 * No more cleanup at this point like in the ctrlr reset. A subsystem reset will cause 1989 * a hot remove for PCIe transport. The hot remove handling does all the necessary ctrlr cleanup. 1990 */ 1991 return rc; 1992 } 1993 1994 int 1995 spdk_nvme_ctrlr_set_trid(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_transport_id *trid) 1996 { 1997 int rc = 0; 1998 1999 nvme_ctrlr_lock(ctrlr); 2000 2001 if (ctrlr->is_failed == false) { 2002 rc = -EPERM; 2003 goto out; 2004 } 2005 2006 if (trid->trtype != ctrlr->trid.trtype) { 2007 rc = -EINVAL; 2008 goto out; 2009 } 2010 2011 if (strncmp(trid->subnqn, ctrlr->trid.subnqn, SPDK_NVMF_NQN_MAX_LEN)) { 2012 rc = -EINVAL; 2013 goto out; 2014 } 2015 2016 ctrlr->trid = *trid; 2017 2018 out: 2019 nvme_ctrlr_unlock(ctrlr); 2020 return rc; 2021 } 2022 2023 void 2024 spdk_nvme_ctrlr_set_remove_cb(struct spdk_nvme_ctrlr *ctrlr, 2025 spdk_nvme_remove_cb remove_cb, void *remove_ctx) 2026 { 2027 if (!spdk_process_is_primary()) { 2028 return; 2029 } 2030 2031 nvme_ctrlr_lock(ctrlr); 2032 ctrlr->remove_cb = remove_cb; 2033 ctrlr->cb_ctx = remove_ctx; 2034 nvme_ctrlr_unlock(ctrlr); 2035 } 2036 2037 static void 2038 nvme_ctrlr_identify_done(void *arg, const struct spdk_nvme_cpl *cpl) 2039 { 2040 struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg; 2041 2042 if (spdk_nvme_cpl_is_error(cpl)) { 2043 NVME_CTRLR_ERRLOG(ctrlr, "nvme_identify_controller failed!\n"); 2044 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2045 return; 2046 } 2047 2048 /* 2049 * Use MDTS to ensure our default max_xfer_size doesn't exceed what the 2050 * controller supports. 2051 */ 2052 ctrlr->max_xfer_size = nvme_transport_ctrlr_get_max_xfer_size(ctrlr); 2053 NVME_CTRLR_DEBUGLOG(ctrlr, "transport max_xfer_size %u\n", ctrlr->max_xfer_size); 2054 if (ctrlr->cdata.mdts > 0) { 2055 ctrlr->max_xfer_size = spdk_min(ctrlr->max_xfer_size, 2056 ctrlr->min_page_size * (1 << ctrlr->cdata.mdts)); 2057 NVME_CTRLR_DEBUGLOG(ctrlr, "MDTS max_xfer_size %u\n", ctrlr->max_xfer_size); 2058 } 2059 2060 NVME_CTRLR_DEBUGLOG(ctrlr, "CNTLID 0x%04" PRIx16 "\n", ctrlr->cdata.cntlid); 2061 if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) { 2062 ctrlr->cntlid = ctrlr->cdata.cntlid; 2063 } else { 2064 /* 2065 * Fabrics controllers should already have CNTLID from the Connect command. 2066 * 2067 * If CNTLID from Connect doesn't match CNTLID in the Identify Controller data, 2068 * trust the one from Connect. 2069 */ 2070 if (ctrlr->cntlid != ctrlr->cdata.cntlid) { 2071 NVME_CTRLR_DEBUGLOG(ctrlr, "Identify CNTLID 0x%04" PRIx16 " != Connect CNTLID 0x%04" PRIx16 "\n", 2072 ctrlr->cdata.cntlid, ctrlr->cntlid); 2073 } 2074 } 2075 2076 if (ctrlr->cdata.sgls.supported && !(ctrlr->quirks & NVME_QUIRK_NOT_USE_SGL)) { 2077 assert(ctrlr->cdata.sgls.supported != 0x3); 2078 ctrlr->flags |= SPDK_NVME_CTRLR_SGL_SUPPORTED; 2079 if (ctrlr->cdata.sgls.supported == 0x2) { 2080 ctrlr->flags |= SPDK_NVME_CTRLR_SGL_REQUIRES_DWORD_ALIGNMENT; 2081 } 2082 2083 ctrlr->max_sges = nvme_transport_ctrlr_get_max_sges(ctrlr); 2084 NVME_CTRLR_DEBUGLOG(ctrlr, "transport max_sges %u\n", ctrlr->max_sges); 2085 } 2086 2087 if (ctrlr->cdata.sgls.metadata_address && !(ctrlr->quirks & NVME_QUIRK_NOT_USE_SGL)) { 2088 ctrlr->flags |= SPDK_NVME_CTRLR_MPTR_SGL_SUPPORTED; 2089 } 2090 2091 if (ctrlr->cdata.oacs.security && !(ctrlr->quirks & NVME_QUIRK_OACS_SECURITY)) { 2092 ctrlr->flags |= SPDK_NVME_CTRLR_SECURITY_SEND_RECV_SUPPORTED; 2093 } 2094 2095 if (ctrlr->cdata.oacs.directives) { 2096 ctrlr->flags |= SPDK_NVME_CTRLR_DIRECTIVES_SUPPORTED; 2097 } 2098 2099 NVME_CTRLR_DEBUGLOG(ctrlr, "fuses compare and write: %d\n", 2100 ctrlr->cdata.fuses.compare_and_write); 2101 if (ctrlr->cdata.fuses.compare_and_write) { 2102 ctrlr->flags |= SPDK_NVME_CTRLR_COMPARE_AND_WRITE_SUPPORTED; 2103 } 2104 2105 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CONFIGURE_AER, 2106 ctrlr->opts.admin_timeout_ms); 2107 } 2108 2109 static int 2110 nvme_ctrlr_identify(struct spdk_nvme_ctrlr *ctrlr) 2111 { 2112 int rc; 2113 2114 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY, 2115 ctrlr->opts.admin_timeout_ms); 2116 2117 rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_CTRLR, 0, 0, 0, 2118 &ctrlr->cdata, sizeof(ctrlr->cdata), 2119 nvme_ctrlr_identify_done, ctrlr); 2120 if (rc != 0) { 2121 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2122 return rc; 2123 } 2124 2125 return 0; 2126 } 2127 2128 static void 2129 nvme_ctrlr_get_zns_cmd_and_effects_log_done(void *arg, const struct spdk_nvme_cpl *cpl) 2130 { 2131 struct spdk_nvme_cmds_and_effect_log_page *log_page; 2132 struct spdk_nvme_ctrlr *ctrlr = arg; 2133 2134 if (spdk_nvme_cpl_is_error(cpl)) { 2135 NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_get_zns_cmd_and_effects_log failed!\n"); 2136 spdk_free(ctrlr->tmp_ptr); 2137 ctrlr->tmp_ptr = NULL; 2138 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2139 return; 2140 } 2141 2142 log_page = ctrlr->tmp_ptr; 2143 2144 if (log_page->io_cmds_supported[SPDK_NVME_OPC_ZONE_APPEND].csupp) { 2145 ctrlr->flags |= SPDK_NVME_CTRLR_ZONE_APPEND_SUPPORTED; 2146 } 2147 spdk_free(ctrlr->tmp_ptr); 2148 ctrlr->tmp_ptr = NULL; 2149 2150 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES, ctrlr->opts.admin_timeout_ms); 2151 } 2152 2153 static int 2154 nvme_ctrlr_get_zns_cmd_and_effects_log(struct spdk_nvme_ctrlr *ctrlr) 2155 { 2156 int rc; 2157 2158 assert(!ctrlr->tmp_ptr); 2159 ctrlr->tmp_ptr = spdk_zmalloc(sizeof(struct spdk_nvme_cmds_and_effect_log_page), 64, NULL, 2160 SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE | SPDK_MALLOC_DMA); 2161 if (!ctrlr->tmp_ptr) { 2162 rc = -ENOMEM; 2163 goto error; 2164 } 2165 2166 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG, 2167 ctrlr->opts.admin_timeout_ms); 2168 2169 rc = spdk_nvme_ctrlr_cmd_get_log_page_ext(ctrlr, SPDK_NVME_LOG_COMMAND_EFFECTS_LOG, 2170 0, ctrlr->tmp_ptr, sizeof(struct spdk_nvme_cmds_and_effect_log_page), 2171 0, 0, 0, SPDK_NVME_CSI_ZNS << 24, 2172 nvme_ctrlr_get_zns_cmd_and_effects_log_done, ctrlr); 2173 if (rc != 0) { 2174 goto error; 2175 } 2176 2177 return 0; 2178 2179 error: 2180 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2181 spdk_free(ctrlr->tmp_ptr); 2182 ctrlr->tmp_ptr = NULL; 2183 return rc; 2184 } 2185 2186 static void 2187 nvme_ctrlr_identify_zns_specific_done(void *arg, const struct spdk_nvme_cpl *cpl) 2188 { 2189 struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg; 2190 2191 if (spdk_nvme_cpl_is_error(cpl)) { 2192 /* no need to print an error, the controller simply does not support ZNS */ 2193 nvme_ctrlr_free_zns_specific_data(ctrlr); 2194 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES, 2195 ctrlr->opts.admin_timeout_ms); 2196 return; 2197 } 2198 2199 /* A zero zasl value means use mdts */ 2200 if (ctrlr->cdata_zns->zasl) { 2201 uint32_t max_append = ctrlr->min_page_size * (1 << ctrlr->cdata_zns->zasl); 2202 ctrlr->max_zone_append_size = spdk_min(ctrlr->max_xfer_size, max_append); 2203 } else { 2204 ctrlr->max_zone_append_size = ctrlr->max_xfer_size; 2205 } 2206 2207 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG, 2208 ctrlr->opts.admin_timeout_ms); 2209 } 2210 2211 /** 2212 * This function will try to fetch the I/O Command Specific Controller data structure for 2213 * each I/O Command Set supported by SPDK. 2214 * 2215 * If an I/O Command Set is not supported by the controller, "Invalid Field in Command" 2216 * will be returned. Since we are fetching in a exploratively way, getting an error back 2217 * from the controller should not be treated as fatal. 2218 * 2219 * I/O Command Sets not supported by SPDK will be skipped (e.g. Key Value Command Set). 2220 * 2221 * I/O Command Sets without a IOCS specific data structure (i.e. a zero-filled IOCS specific 2222 * data structure) will be skipped (e.g. NVM Command Set, Key Value Command Set). 2223 */ 2224 static int 2225 nvme_ctrlr_identify_iocs_specific(struct spdk_nvme_ctrlr *ctrlr) 2226 { 2227 int rc; 2228 2229 if (!nvme_ctrlr_multi_iocs_enabled(ctrlr)) { 2230 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_NUM_QUEUES, 2231 ctrlr->opts.admin_timeout_ms); 2232 return 0; 2233 } 2234 2235 /* 2236 * Since SPDK currently only needs to fetch a single Command Set, keep the code here, 2237 * instead of creating multiple NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC substates, 2238 * which would require additional functions and complexity for no good reason. 2239 */ 2240 assert(!ctrlr->cdata_zns); 2241 ctrlr->cdata_zns = spdk_zmalloc(sizeof(*ctrlr->cdata_zns), 64, NULL, SPDK_ENV_SOCKET_ID_ANY, 2242 SPDK_MALLOC_SHARE | SPDK_MALLOC_DMA); 2243 if (!ctrlr->cdata_zns) { 2244 rc = -ENOMEM; 2245 goto error; 2246 } 2247 2248 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC, 2249 ctrlr->opts.admin_timeout_ms); 2250 2251 rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_CTRLR_IOCS, 0, 0, SPDK_NVME_CSI_ZNS, 2252 ctrlr->cdata_zns, sizeof(*ctrlr->cdata_zns), 2253 nvme_ctrlr_identify_zns_specific_done, ctrlr); 2254 if (rc != 0) { 2255 goto error; 2256 } 2257 2258 return 0; 2259 2260 error: 2261 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2262 nvme_ctrlr_free_zns_specific_data(ctrlr); 2263 return rc; 2264 } 2265 2266 enum nvme_active_ns_state { 2267 NVME_ACTIVE_NS_STATE_IDLE, 2268 NVME_ACTIVE_NS_STATE_PROCESSING, 2269 NVME_ACTIVE_NS_STATE_DONE, 2270 NVME_ACTIVE_NS_STATE_ERROR 2271 }; 2272 2273 typedef void (*nvme_active_ns_ctx_deleter)(struct nvme_active_ns_ctx *); 2274 2275 struct nvme_active_ns_ctx { 2276 struct spdk_nvme_ctrlr *ctrlr; 2277 uint32_t page_count; 2278 uint32_t next_nsid; 2279 uint32_t *new_ns_list; 2280 nvme_active_ns_ctx_deleter deleter; 2281 2282 enum nvme_active_ns_state state; 2283 }; 2284 2285 static struct nvme_active_ns_ctx * 2286 nvme_active_ns_ctx_create(struct spdk_nvme_ctrlr *ctrlr, nvme_active_ns_ctx_deleter deleter) 2287 { 2288 struct nvme_active_ns_ctx *ctx; 2289 uint32_t *new_ns_list = NULL; 2290 2291 ctx = calloc(1, sizeof(*ctx)); 2292 if (!ctx) { 2293 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate nvme_active_ns_ctx!\n"); 2294 return NULL; 2295 } 2296 2297 new_ns_list = spdk_zmalloc(sizeof(struct spdk_nvme_ns_list), ctrlr->page_size, 2298 NULL, SPDK_ENV_LCORE_ID_ANY, SPDK_MALLOC_SHARE); 2299 if (!new_ns_list) { 2300 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate active_ns_list!\n"); 2301 free(ctx); 2302 return NULL; 2303 } 2304 2305 ctx->page_count = 1; 2306 ctx->new_ns_list = new_ns_list; 2307 ctx->ctrlr = ctrlr; 2308 ctx->deleter = deleter; 2309 2310 return ctx; 2311 } 2312 2313 static void 2314 nvme_active_ns_ctx_destroy(struct nvme_active_ns_ctx *ctx) 2315 { 2316 spdk_free(ctx->new_ns_list); 2317 free(ctx); 2318 } 2319 2320 static int 2321 nvme_ctrlr_destruct_namespace(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid) 2322 { 2323 struct spdk_nvme_ns tmp, *ns; 2324 2325 assert(ctrlr != NULL); 2326 2327 tmp.id = nsid; 2328 ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp); 2329 if (ns == NULL) { 2330 return -EINVAL; 2331 } 2332 2333 nvme_ns_destruct(ns); 2334 ns->active = false; 2335 2336 return 0; 2337 } 2338 2339 static int 2340 nvme_ctrlr_construct_namespace(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid) 2341 { 2342 struct spdk_nvme_ns *ns; 2343 2344 if (nsid < 1 || nsid > ctrlr->cdata.nn) { 2345 return -EINVAL; 2346 } 2347 2348 /* Namespaces are constructed on demand, so simply request it. */ 2349 ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid); 2350 if (ns == NULL) { 2351 return -ENOMEM; 2352 } 2353 2354 ns->active = true; 2355 2356 return 0; 2357 } 2358 2359 static void 2360 nvme_ctrlr_identify_active_ns_swap(struct spdk_nvme_ctrlr *ctrlr, uint32_t *new_ns_list, 2361 size_t max_entries) 2362 { 2363 uint32_t active_ns_count = 0; 2364 size_t i; 2365 uint32_t nsid; 2366 struct spdk_nvme_ns *ns, *tmp_ns; 2367 int rc; 2368 2369 /* First, remove namespaces that no longer exist */ 2370 RB_FOREACH_SAFE(ns, nvme_ns_tree, &ctrlr->ns, tmp_ns) { 2371 nsid = new_ns_list[0]; 2372 active_ns_count = 0; 2373 while (nsid != 0) { 2374 if (nsid == ns->id) { 2375 break; 2376 } 2377 2378 nsid = new_ns_list[active_ns_count++]; 2379 } 2380 2381 if (nsid != ns->id) { 2382 /* Did not find this namespace id in the new list. */ 2383 NVME_CTRLR_DEBUGLOG(ctrlr, "Namespace %u was removed\n", ns->id); 2384 nvme_ctrlr_destruct_namespace(ctrlr, ns->id); 2385 } 2386 } 2387 2388 /* Next, add new namespaces */ 2389 active_ns_count = 0; 2390 for (i = 0; i < max_entries; i++) { 2391 nsid = new_ns_list[active_ns_count]; 2392 2393 if (nsid == 0) { 2394 break; 2395 } 2396 2397 /* If the namespace already exists, this will not construct it a second time. */ 2398 rc = nvme_ctrlr_construct_namespace(ctrlr, nsid); 2399 if (rc != 0) { 2400 /* We can't easily handle a failure here. But just move on. */ 2401 assert(false); 2402 NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to allocate a namespace object.\n"); 2403 continue; 2404 } 2405 2406 active_ns_count++; 2407 } 2408 2409 ctrlr->active_ns_count = active_ns_count; 2410 } 2411 2412 static void 2413 nvme_ctrlr_identify_active_ns_async_done(void *arg, const struct spdk_nvme_cpl *cpl) 2414 { 2415 struct nvme_active_ns_ctx *ctx = arg; 2416 uint32_t *new_ns_list = NULL; 2417 2418 if (spdk_nvme_cpl_is_error(cpl)) { 2419 ctx->state = NVME_ACTIVE_NS_STATE_ERROR; 2420 goto out; 2421 } 2422 2423 ctx->next_nsid = ctx->new_ns_list[1024 * ctx->page_count - 1]; 2424 if (ctx->next_nsid == 0) { 2425 ctx->state = NVME_ACTIVE_NS_STATE_DONE; 2426 goto out; 2427 } 2428 2429 ctx->page_count++; 2430 new_ns_list = spdk_realloc(ctx->new_ns_list, 2431 ctx->page_count * sizeof(struct spdk_nvme_ns_list), 2432 ctx->ctrlr->page_size); 2433 if (!new_ns_list) { 2434 SPDK_ERRLOG("Failed to reallocate active_ns_list!\n"); 2435 ctx->state = NVME_ACTIVE_NS_STATE_ERROR; 2436 goto out; 2437 } 2438 2439 ctx->new_ns_list = new_ns_list; 2440 nvme_ctrlr_identify_active_ns_async(ctx); 2441 return; 2442 2443 out: 2444 if (ctx->deleter) { 2445 ctx->deleter(ctx); 2446 } 2447 } 2448 2449 static void 2450 nvme_ctrlr_identify_active_ns_async(struct nvme_active_ns_ctx *ctx) 2451 { 2452 struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr; 2453 uint32_t i; 2454 int rc; 2455 2456 if (ctrlr->cdata.nn == 0) { 2457 ctx->state = NVME_ACTIVE_NS_STATE_DONE; 2458 goto out; 2459 } 2460 2461 assert(ctx->new_ns_list != NULL); 2462 2463 /* 2464 * If controller doesn't support active ns list CNS 0x02 dummy up 2465 * an active ns list, i.e. all namespaces report as active 2466 */ 2467 if (ctrlr->vs.raw < SPDK_NVME_VERSION(1, 1, 0) || ctrlr->quirks & NVME_QUIRK_IDENTIFY_CNS) { 2468 uint32_t *new_ns_list; 2469 2470 /* 2471 * Active NS list must always end with zero element. 2472 * So, we allocate for cdata.nn+1. 2473 */ 2474 ctx->page_count = spdk_divide_round_up(ctrlr->cdata.nn + 1, 2475 sizeof(struct spdk_nvme_ns_list) / sizeof(new_ns_list[0])); 2476 new_ns_list = spdk_realloc(ctx->new_ns_list, 2477 ctx->page_count * sizeof(struct spdk_nvme_ns_list), 2478 ctx->ctrlr->page_size); 2479 if (!new_ns_list) { 2480 SPDK_ERRLOG("Failed to reallocate active_ns_list!\n"); 2481 ctx->state = NVME_ACTIVE_NS_STATE_ERROR; 2482 goto out; 2483 } 2484 2485 ctx->new_ns_list = new_ns_list; 2486 ctx->new_ns_list[ctrlr->cdata.nn] = 0; 2487 for (i = 0; i < ctrlr->cdata.nn; i++) { 2488 ctx->new_ns_list[i] = i + 1; 2489 } 2490 2491 ctx->state = NVME_ACTIVE_NS_STATE_DONE; 2492 goto out; 2493 } 2494 2495 ctx->state = NVME_ACTIVE_NS_STATE_PROCESSING; 2496 rc = nvme_ctrlr_cmd_identify(ctrlr, SPDK_NVME_IDENTIFY_ACTIVE_NS_LIST, 0, ctx->next_nsid, 0, 2497 &ctx->new_ns_list[1024 * (ctx->page_count - 1)], sizeof(struct spdk_nvme_ns_list), 2498 nvme_ctrlr_identify_active_ns_async_done, ctx); 2499 if (rc != 0) { 2500 ctx->state = NVME_ACTIVE_NS_STATE_ERROR; 2501 goto out; 2502 } 2503 2504 return; 2505 2506 out: 2507 if (ctx->deleter) { 2508 ctx->deleter(ctx); 2509 } 2510 } 2511 2512 static void 2513 _nvme_active_ns_ctx_deleter(struct nvme_active_ns_ctx *ctx) 2514 { 2515 struct spdk_nvme_ctrlr *ctrlr = ctx->ctrlr; 2516 struct spdk_nvme_ns *ns; 2517 2518 if (ctx->state == NVME_ACTIVE_NS_STATE_ERROR) { 2519 nvme_active_ns_ctx_destroy(ctx); 2520 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2521 return; 2522 } 2523 2524 assert(ctx->state == NVME_ACTIVE_NS_STATE_DONE); 2525 2526 RB_FOREACH(ns, nvme_ns_tree, &ctrlr->ns) { 2527 nvme_ns_free_iocs_specific_data(ns); 2528 } 2529 2530 nvme_ctrlr_identify_active_ns_swap(ctrlr, ctx->new_ns_list, ctx->page_count * 1024); 2531 nvme_active_ns_ctx_destroy(ctx); 2532 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS, ctrlr->opts.admin_timeout_ms); 2533 } 2534 2535 static void 2536 _nvme_ctrlr_identify_active_ns(struct spdk_nvme_ctrlr *ctrlr) 2537 { 2538 struct nvme_active_ns_ctx *ctx; 2539 2540 ctx = nvme_active_ns_ctx_create(ctrlr, _nvme_active_ns_ctx_deleter); 2541 if (!ctx) { 2542 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2543 return; 2544 } 2545 2546 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS, 2547 ctrlr->opts.admin_timeout_ms); 2548 nvme_ctrlr_identify_active_ns_async(ctx); 2549 } 2550 2551 int 2552 nvme_ctrlr_identify_active_ns(struct spdk_nvme_ctrlr *ctrlr) 2553 { 2554 struct nvme_active_ns_ctx *ctx; 2555 int rc; 2556 2557 ctx = nvme_active_ns_ctx_create(ctrlr, NULL); 2558 if (!ctx) { 2559 return -ENOMEM; 2560 } 2561 2562 nvme_ctrlr_identify_active_ns_async(ctx); 2563 while (ctx->state == NVME_ACTIVE_NS_STATE_PROCESSING) { 2564 rc = spdk_nvme_qpair_process_completions(ctrlr->adminq, 0); 2565 if (rc < 0) { 2566 ctx->state = NVME_ACTIVE_NS_STATE_ERROR; 2567 break; 2568 } 2569 } 2570 2571 if (ctx->state == NVME_ACTIVE_NS_STATE_ERROR) { 2572 nvme_active_ns_ctx_destroy(ctx); 2573 return -ENXIO; 2574 } 2575 2576 assert(ctx->state == NVME_ACTIVE_NS_STATE_DONE); 2577 nvme_ctrlr_identify_active_ns_swap(ctrlr, ctx->new_ns_list, ctx->page_count * 1024); 2578 nvme_active_ns_ctx_destroy(ctx); 2579 2580 return 0; 2581 } 2582 2583 static void 2584 nvme_ctrlr_identify_ns_async_done(void *arg, const struct spdk_nvme_cpl *cpl) 2585 { 2586 struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg; 2587 struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr; 2588 uint32_t nsid; 2589 int rc; 2590 2591 if (spdk_nvme_cpl_is_error(cpl)) { 2592 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2593 return; 2594 } 2595 2596 nvme_ns_set_identify_data(ns); 2597 2598 /* move on to the next active NS */ 2599 nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id); 2600 ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid); 2601 if (ns == NULL) { 2602 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ID_DESCS, 2603 ctrlr->opts.admin_timeout_ms); 2604 return; 2605 } 2606 ns->ctrlr = ctrlr; 2607 ns->id = nsid; 2608 2609 rc = nvme_ctrlr_identify_ns_async(ns); 2610 if (rc) { 2611 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2612 } 2613 } 2614 2615 static int 2616 nvme_ctrlr_identify_ns_async(struct spdk_nvme_ns *ns) 2617 { 2618 struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr; 2619 struct spdk_nvme_ns_data *nsdata; 2620 2621 nsdata = &ns->nsdata; 2622 2623 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS, 2624 ctrlr->opts.admin_timeout_ms); 2625 return nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS, 0, ns->id, 0, 2626 nsdata, sizeof(*nsdata), 2627 nvme_ctrlr_identify_ns_async_done, ns); 2628 } 2629 2630 static int 2631 nvme_ctrlr_identify_namespaces(struct spdk_nvme_ctrlr *ctrlr) 2632 { 2633 uint32_t nsid; 2634 struct spdk_nvme_ns *ns; 2635 int rc; 2636 2637 nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr); 2638 ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid); 2639 if (ns == NULL) { 2640 /* No active NS, move on to the next state */ 2641 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ID_DESCS, 2642 ctrlr->opts.admin_timeout_ms); 2643 return 0; 2644 } 2645 2646 ns->ctrlr = ctrlr; 2647 ns->id = nsid; 2648 2649 rc = nvme_ctrlr_identify_ns_async(ns); 2650 if (rc) { 2651 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2652 } 2653 2654 return rc; 2655 } 2656 2657 static int 2658 nvme_ctrlr_identify_namespaces_iocs_specific_next(struct spdk_nvme_ctrlr *ctrlr, uint32_t prev_nsid) 2659 { 2660 uint32_t nsid; 2661 struct spdk_nvme_ns *ns; 2662 int rc; 2663 2664 if (!prev_nsid) { 2665 nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr); 2666 } else { 2667 /* move on to the next active NS */ 2668 nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, prev_nsid); 2669 } 2670 2671 ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid); 2672 if (ns == NULL) { 2673 /* No first/next active NS, move on to the next state */ 2674 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES, 2675 ctrlr->opts.admin_timeout_ms); 2676 return 0; 2677 } 2678 2679 /* loop until we find a ns which has (supported) iocs specific data */ 2680 while (!nvme_ns_has_supported_iocs_specific_data(ns)) { 2681 nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id); 2682 ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid); 2683 if (ns == NULL) { 2684 /* no namespace with (supported) iocs specific data found */ 2685 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES, 2686 ctrlr->opts.admin_timeout_ms); 2687 return 0; 2688 } 2689 } 2690 2691 rc = nvme_ctrlr_identify_ns_iocs_specific_async(ns); 2692 if (rc) { 2693 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2694 } 2695 2696 return rc; 2697 } 2698 2699 static void 2700 nvme_ctrlr_identify_ns_zns_specific_async_done(void *arg, const struct spdk_nvme_cpl *cpl) 2701 { 2702 struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg; 2703 struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr; 2704 2705 if (spdk_nvme_cpl_is_error(cpl)) { 2706 nvme_ns_free_zns_specific_data(ns); 2707 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2708 return; 2709 } 2710 2711 nvme_ctrlr_identify_namespaces_iocs_specific_next(ctrlr, ns->id); 2712 } 2713 2714 static int 2715 nvme_ctrlr_identify_ns_zns_specific_async(struct spdk_nvme_ns *ns) 2716 { 2717 struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr; 2718 int rc; 2719 2720 assert(!ns->nsdata_zns); 2721 ns->nsdata_zns = spdk_zmalloc(sizeof(*ns->nsdata_zns), 64, NULL, SPDK_ENV_SOCKET_ID_ANY, 2722 SPDK_MALLOC_SHARE); 2723 if (!ns->nsdata_zns) { 2724 return -ENOMEM; 2725 } 2726 2727 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC, 2728 ctrlr->opts.admin_timeout_ms); 2729 rc = nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS_IOCS, 0, ns->id, ns->csi, 2730 ns->nsdata_zns, sizeof(*ns->nsdata_zns), 2731 nvme_ctrlr_identify_ns_zns_specific_async_done, ns); 2732 if (rc) { 2733 nvme_ns_free_zns_specific_data(ns); 2734 } 2735 2736 return rc; 2737 } 2738 2739 static void 2740 nvme_ctrlr_identify_ns_nvm_specific_async_done(void *arg, const struct spdk_nvme_cpl *cpl) 2741 { 2742 struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg; 2743 struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr; 2744 2745 if (spdk_nvme_cpl_is_error(cpl)) { 2746 nvme_ns_free_nvm_specific_data(ns); 2747 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2748 return; 2749 } 2750 2751 nvme_ctrlr_identify_namespaces_iocs_specific_next(ctrlr, ns->id); 2752 } 2753 2754 static int 2755 nvme_ctrlr_identify_ns_nvm_specific_async(struct spdk_nvme_ns *ns) 2756 { 2757 struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr; 2758 int rc; 2759 2760 assert(!ns->nsdata_nvm); 2761 ns->nsdata_nvm = spdk_zmalloc(sizeof(*ns->nsdata_nvm), 64, NULL, SPDK_ENV_SOCKET_ID_ANY, 2762 SPDK_MALLOC_SHARE); 2763 if (!ns->nsdata_nvm) { 2764 return -ENOMEM; 2765 } 2766 2767 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC, 2768 ctrlr->opts.admin_timeout_ms); 2769 rc = nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS_IOCS, 0, ns->id, ns->csi, 2770 ns->nsdata_nvm, sizeof(*ns->nsdata_nvm), 2771 nvme_ctrlr_identify_ns_nvm_specific_async_done, ns); 2772 if (rc) { 2773 nvme_ns_free_nvm_specific_data(ns); 2774 } 2775 2776 return rc; 2777 } 2778 2779 static int 2780 nvme_ctrlr_identify_ns_iocs_specific_async(struct spdk_nvme_ns *ns) 2781 { 2782 switch (ns->csi) { 2783 case SPDK_NVME_CSI_ZNS: 2784 return nvme_ctrlr_identify_ns_zns_specific_async(ns); 2785 case SPDK_NVME_CSI_NVM: 2786 if (ns->ctrlr->cdata.ctratt.bits.elbas) { 2787 return nvme_ctrlr_identify_ns_nvm_specific_async(ns); 2788 } 2789 /* fallthrough */ 2790 default: 2791 /* 2792 * This switch must handle all cases for which 2793 * nvme_ns_has_supported_iocs_specific_data() returns true, 2794 * other cases should never happen. 2795 */ 2796 assert(0); 2797 } 2798 2799 return -EINVAL; 2800 } 2801 2802 static int 2803 nvme_ctrlr_identify_namespaces_iocs_specific(struct spdk_nvme_ctrlr *ctrlr) 2804 { 2805 if (!nvme_ctrlr_multi_iocs_enabled(ctrlr)) { 2806 /* Multi IOCS not supported/enabled, move on to the next state */ 2807 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES, 2808 ctrlr->opts.admin_timeout_ms); 2809 return 0; 2810 } 2811 2812 return nvme_ctrlr_identify_namespaces_iocs_specific_next(ctrlr, 0); 2813 } 2814 2815 static void 2816 nvme_ctrlr_identify_id_desc_async_done(void *arg, const struct spdk_nvme_cpl *cpl) 2817 { 2818 struct spdk_nvme_ns *ns = (struct spdk_nvme_ns *)arg; 2819 struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr; 2820 uint32_t nsid; 2821 int rc; 2822 2823 if (spdk_nvme_cpl_is_error(cpl)) { 2824 /* 2825 * Many controllers claim to be compatible with NVMe 1.3, however, 2826 * they do not implement NS ID Desc List. Therefore, instead of setting 2827 * the state to NVME_CTRLR_STATE_ERROR, silently ignore the completion 2828 * error and move on to the next state. 2829 * 2830 * The proper way is to create a new quirk for controllers that violate 2831 * the NVMe 1.3 spec by not supporting NS ID Desc List. 2832 * (Re-using the NVME_QUIRK_IDENTIFY_CNS quirk is not possible, since 2833 * it is too generic and was added in order to handle controllers that 2834 * violate the NVMe 1.1 spec by not supporting ACTIVE LIST). 2835 */ 2836 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC, 2837 ctrlr->opts.admin_timeout_ms); 2838 return; 2839 } 2840 2841 nvme_ns_set_id_desc_list_data(ns); 2842 2843 /* move on to the next active NS */ 2844 nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, ns->id); 2845 ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid); 2846 if (ns == NULL) { 2847 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC, 2848 ctrlr->opts.admin_timeout_ms); 2849 return; 2850 } 2851 2852 rc = nvme_ctrlr_identify_id_desc_async(ns); 2853 if (rc) { 2854 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2855 } 2856 } 2857 2858 static int 2859 nvme_ctrlr_identify_id_desc_async(struct spdk_nvme_ns *ns) 2860 { 2861 struct spdk_nvme_ctrlr *ctrlr = ns->ctrlr; 2862 2863 memset(ns->id_desc_list, 0, sizeof(ns->id_desc_list)); 2864 2865 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS, 2866 ctrlr->opts.admin_timeout_ms); 2867 return nvme_ctrlr_cmd_identify(ns->ctrlr, SPDK_NVME_IDENTIFY_NS_ID_DESCRIPTOR_LIST, 2868 0, ns->id, 0, ns->id_desc_list, sizeof(ns->id_desc_list), 2869 nvme_ctrlr_identify_id_desc_async_done, ns); 2870 } 2871 2872 static int 2873 nvme_ctrlr_identify_id_desc_namespaces(struct spdk_nvme_ctrlr *ctrlr) 2874 { 2875 uint32_t nsid; 2876 struct spdk_nvme_ns *ns; 2877 int rc; 2878 2879 if ((ctrlr->vs.raw < SPDK_NVME_VERSION(1, 3, 0) && 2880 !(ctrlr->cap.bits.css & SPDK_NVME_CAP_CSS_IOCS)) || 2881 (ctrlr->quirks & NVME_QUIRK_IDENTIFY_CNS)) { 2882 NVME_CTRLR_DEBUGLOG(ctrlr, "Version < 1.3; not attempting to retrieve NS ID Descriptor List\n"); 2883 /* NS ID Desc List not supported, move on to the next state */ 2884 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC, 2885 ctrlr->opts.admin_timeout_ms); 2886 return 0; 2887 } 2888 2889 nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr); 2890 ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid); 2891 if (ns == NULL) { 2892 /* No active NS, move on to the next state */ 2893 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC, 2894 ctrlr->opts.admin_timeout_ms); 2895 return 0; 2896 } 2897 2898 rc = nvme_ctrlr_identify_id_desc_async(ns); 2899 if (rc) { 2900 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2901 } 2902 2903 return rc; 2904 } 2905 2906 static void 2907 nvme_ctrlr_update_nvmf_ioccsz(struct spdk_nvme_ctrlr *ctrlr) 2908 { 2909 if (spdk_nvme_ctrlr_is_fabrics(ctrlr)) { 2910 if (ctrlr->cdata.nvmf_specific.ioccsz < 4) { 2911 NVME_CTRLR_ERRLOG(ctrlr, "Incorrect IOCCSZ %u, the minimum value should be 4\n", 2912 ctrlr->cdata.nvmf_specific.ioccsz); 2913 ctrlr->cdata.nvmf_specific.ioccsz = 4; 2914 assert(0); 2915 } 2916 ctrlr->ioccsz_bytes = ctrlr->cdata.nvmf_specific.ioccsz * 16 - sizeof(struct spdk_nvme_cmd); 2917 ctrlr->icdoff = ctrlr->cdata.nvmf_specific.icdoff; 2918 } 2919 } 2920 2921 static void 2922 nvme_ctrlr_set_num_queues_done(void *arg, const struct spdk_nvme_cpl *cpl) 2923 { 2924 uint32_t cq_allocated, sq_allocated, min_allocated, i; 2925 struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg; 2926 2927 if (spdk_nvme_cpl_is_error(cpl)) { 2928 NVME_CTRLR_ERRLOG(ctrlr, "Set Features - Number of Queues failed!\n"); 2929 ctrlr->opts.num_io_queues = 0; 2930 } else { 2931 /* 2932 * Data in cdw0 is 0-based. 2933 * Lower 16-bits indicate number of submission queues allocated. 2934 * Upper 16-bits indicate number of completion queues allocated. 2935 */ 2936 sq_allocated = (cpl->cdw0 & 0xFFFF) + 1; 2937 cq_allocated = (cpl->cdw0 >> 16) + 1; 2938 2939 /* 2940 * For 1:1 queue mapping, set number of allocated queues to be minimum of 2941 * submission and completion queues. 2942 */ 2943 min_allocated = spdk_min(sq_allocated, cq_allocated); 2944 2945 /* Set number of queues to be minimum of requested and actually allocated. */ 2946 ctrlr->opts.num_io_queues = spdk_min(min_allocated, ctrlr->opts.num_io_queues); 2947 } 2948 2949 ctrlr->free_io_qids = spdk_bit_array_create(ctrlr->opts.num_io_queues + 1); 2950 if (ctrlr->free_io_qids == NULL) { 2951 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2952 return; 2953 } 2954 2955 /* Initialize list of free I/O queue IDs. QID 0 is the admin queue (implicitly allocated). */ 2956 for (i = 1; i <= ctrlr->opts.num_io_queues; i++) { 2957 spdk_nvme_ctrlr_free_qid(ctrlr, i); 2958 } 2959 2960 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS, 2961 ctrlr->opts.admin_timeout_ms); 2962 } 2963 2964 static int 2965 nvme_ctrlr_set_num_queues(struct spdk_nvme_ctrlr *ctrlr) 2966 { 2967 int rc; 2968 2969 if (ctrlr->opts.num_io_queues > SPDK_NVME_MAX_IO_QUEUES) { 2970 NVME_CTRLR_NOTICELOG(ctrlr, "Limiting requested num_io_queues %u to max %d\n", 2971 ctrlr->opts.num_io_queues, SPDK_NVME_MAX_IO_QUEUES); 2972 ctrlr->opts.num_io_queues = SPDK_NVME_MAX_IO_QUEUES; 2973 } else if (ctrlr->opts.num_io_queues < 1) { 2974 NVME_CTRLR_NOTICELOG(ctrlr, "Requested num_io_queues 0, increasing to 1\n"); 2975 ctrlr->opts.num_io_queues = 1; 2976 } 2977 2978 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES, 2979 ctrlr->opts.admin_timeout_ms); 2980 2981 rc = nvme_ctrlr_cmd_set_num_queues(ctrlr, ctrlr->opts.num_io_queues, 2982 nvme_ctrlr_set_num_queues_done, ctrlr); 2983 if (rc != 0) { 2984 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 2985 return rc; 2986 } 2987 2988 return 0; 2989 } 2990 2991 static void 2992 nvme_ctrlr_set_keep_alive_timeout_done(void *arg, const struct spdk_nvme_cpl *cpl) 2993 { 2994 uint32_t keep_alive_interval_us; 2995 struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg; 2996 2997 if (spdk_nvme_cpl_is_error(cpl)) { 2998 if ((cpl->status.sct == SPDK_NVME_SCT_GENERIC) && 2999 (cpl->status.sc == SPDK_NVME_SC_INVALID_FIELD)) { 3000 NVME_CTRLR_DEBUGLOG(ctrlr, "Keep alive timeout Get Feature is not supported\n"); 3001 } else { 3002 NVME_CTRLR_ERRLOG(ctrlr, "Keep alive timeout Get Feature failed: SC %x SCT %x\n", 3003 cpl->status.sc, cpl->status.sct); 3004 ctrlr->opts.keep_alive_timeout_ms = 0; 3005 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3006 return; 3007 } 3008 } else { 3009 if (ctrlr->opts.keep_alive_timeout_ms != cpl->cdw0) { 3010 NVME_CTRLR_DEBUGLOG(ctrlr, "Controller adjusted keep alive timeout to %u ms\n", 3011 cpl->cdw0); 3012 } 3013 3014 ctrlr->opts.keep_alive_timeout_ms = cpl->cdw0; 3015 } 3016 3017 if (ctrlr->opts.keep_alive_timeout_ms == 0) { 3018 ctrlr->keep_alive_interval_ticks = 0; 3019 } else { 3020 keep_alive_interval_us = ctrlr->opts.keep_alive_timeout_ms * 1000 / 2; 3021 3022 NVME_CTRLR_DEBUGLOG(ctrlr, "Sending keep alive every %u us\n", keep_alive_interval_us); 3023 3024 ctrlr->keep_alive_interval_ticks = (keep_alive_interval_us * spdk_get_ticks_hz()) / 3025 UINT64_C(1000000); 3026 3027 /* Schedule the first Keep Alive to be sent as soon as possible. */ 3028 ctrlr->next_keep_alive_tick = spdk_get_ticks(); 3029 } 3030 3031 if (spdk_nvme_ctrlr_is_discovery(ctrlr)) { 3032 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE); 3033 } else { 3034 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC, 3035 ctrlr->opts.admin_timeout_ms); 3036 } 3037 } 3038 3039 static int 3040 nvme_ctrlr_set_keep_alive_timeout(struct spdk_nvme_ctrlr *ctrlr) 3041 { 3042 int rc; 3043 3044 if (ctrlr->opts.keep_alive_timeout_ms == 0) { 3045 if (spdk_nvme_ctrlr_is_discovery(ctrlr)) { 3046 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE); 3047 } else { 3048 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC, 3049 ctrlr->opts.admin_timeout_ms); 3050 } 3051 return 0; 3052 } 3053 3054 /* Note: Discovery controller identify data does not populate KAS according to spec. */ 3055 if (!spdk_nvme_ctrlr_is_discovery(ctrlr) && ctrlr->cdata.kas == 0) { 3056 NVME_CTRLR_DEBUGLOG(ctrlr, "Controller KAS is 0 - not enabling Keep Alive\n"); 3057 ctrlr->opts.keep_alive_timeout_ms = 0; 3058 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC, 3059 ctrlr->opts.admin_timeout_ms); 3060 return 0; 3061 } 3062 3063 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT, 3064 ctrlr->opts.admin_timeout_ms); 3065 3066 /* Retrieve actual keep alive timeout, since the controller may have adjusted it. */ 3067 rc = spdk_nvme_ctrlr_cmd_get_feature(ctrlr, SPDK_NVME_FEAT_KEEP_ALIVE_TIMER, 0, NULL, 0, 3068 nvme_ctrlr_set_keep_alive_timeout_done, ctrlr); 3069 if (rc != 0) { 3070 NVME_CTRLR_ERRLOG(ctrlr, "Keep alive timeout Get Feature failed: %d\n", rc); 3071 ctrlr->opts.keep_alive_timeout_ms = 0; 3072 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3073 return rc; 3074 } 3075 3076 return 0; 3077 } 3078 3079 static void 3080 nvme_ctrlr_set_host_id_done(void *arg, const struct spdk_nvme_cpl *cpl) 3081 { 3082 struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg; 3083 3084 if (spdk_nvme_cpl_is_error(cpl)) { 3085 /* 3086 * Treat Set Features - Host ID failure as non-fatal, since the Host ID feature 3087 * is optional. 3088 */ 3089 NVME_CTRLR_WARNLOG(ctrlr, "Set Features - Host ID failed: SC 0x%x SCT 0x%x\n", 3090 cpl->status.sc, cpl->status.sct); 3091 } else { 3092 NVME_CTRLR_DEBUGLOG(ctrlr, "Set Features - Host ID was successful\n"); 3093 } 3094 3095 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_TRANSPORT_READY, ctrlr->opts.admin_timeout_ms); 3096 } 3097 3098 static int 3099 nvme_ctrlr_set_host_id(struct spdk_nvme_ctrlr *ctrlr) 3100 { 3101 uint8_t *host_id; 3102 uint32_t host_id_size; 3103 int rc; 3104 3105 if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) { 3106 /* 3107 * NVMe-oF sends the host ID during Connect and doesn't allow 3108 * Set Features - Host Identifier after Connect, so we don't need to do anything here. 3109 */ 3110 NVME_CTRLR_DEBUGLOG(ctrlr, "NVMe-oF transport - not sending Set Features - Host ID\n"); 3111 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_TRANSPORT_READY, ctrlr->opts.admin_timeout_ms); 3112 return 0; 3113 } 3114 3115 if (ctrlr->cdata.ctratt.bits.host_id_exhid_supported) { 3116 NVME_CTRLR_DEBUGLOG(ctrlr, "Using 128-bit extended host identifier\n"); 3117 host_id = ctrlr->opts.extended_host_id; 3118 host_id_size = sizeof(ctrlr->opts.extended_host_id); 3119 } else { 3120 NVME_CTRLR_DEBUGLOG(ctrlr, "Using 64-bit host identifier\n"); 3121 host_id = ctrlr->opts.host_id; 3122 host_id_size = sizeof(ctrlr->opts.host_id); 3123 } 3124 3125 /* If the user specified an all-zeroes host identifier, don't send the command. */ 3126 if (spdk_mem_all_zero(host_id, host_id_size)) { 3127 NVME_CTRLR_DEBUGLOG(ctrlr, "User did not specify host ID - not sending Set Features - Host ID\n"); 3128 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_TRANSPORT_READY, ctrlr->opts.admin_timeout_ms); 3129 return 0; 3130 } 3131 3132 SPDK_LOGDUMP(nvme, "host_id", host_id, host_id_size); 3133 3134 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_HOST_ID, 3135 ctrlr->opts.admin_timeout_ms); 3136 3137 rc = nvme_ctrlr_cmd_set_host_id(ctrlr, host_id, host_id_size, nvme_ctrlr_set_host_id_done, ctrlr); 3138 if (rc != 0) { 3139 NVME_CTRLR_ERRLOG(ctrlr, "Set Features - Host ID failed: %d\n", rc); 3140 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3141 return rc; 3142 } 3143 3144 return 0; 3145 } 3146 3147 void 3148 nvme_ctrlr_update_namespaces(struct spdk_nvme_ctrlr *ctrlr) 3149 { 3150 uint32_t nsid; 3151 struct spdk_nvme_ns *ns; 3152 3153 for (nsid = spdk_nvme_ctrlr_get_first_active_ns(ctrlr); 3154 nsid != 0; nsid = spdk_nvme_ctrlr_get_next_active_ns(ctrlr, nsid)) { 3155 ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid); 3156 nvme_ns_construct(ns, nsid, ctrlr); 3157 } 3158 } 3159 3160 static int 3161 nvme_ctrlr_clear_changed_ns_log(struct spdk_nvme_ctrlr *ctrlr) 3162 { 3163 struct nvme_completion_poll_status *status; 3164 int rc = -ENOMEM; 3165 char *buffer = NULL; 3166 uint32_t nsid; 3167 size_t buf_size = (SPDK_NVME_MAX_CHANGED_NAMESPACES * sizeof(uint32_t)); 3168 3169 if (ctrlr->opts.disable_read_changed_ns_list_log_page) { 3170 return 0; 3171 } 3172 3173 buffer = spdk_dma_zmalloc(buf_size, 4096, NULL); 3174 if (!buffer) { 3175 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate buffer for getting " 3176 "changed ns log.\n"); 3177 return rc; 3178 } 3179 3180 status = calloc(1, sizeof(*status)); 3181 if (!status) { 3182 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n"); 3183 goto free_buffer; 3184 } 3185 3186 rc = spdk_nvme_ctrlr_cmd_get_log_page(ctrlr, 3187 SPDK_NVME_LOG_CHANGED_NS_LIST, 3188 SPDK_NVME_GLOBAL_NS_TAG, 3189 buffer, buf_size, 0, 3190 nvme_completion_poll_cb, status); 3191 3192 if (rc) { 3193 NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_cmd_get_log_page() failed: rc=%d\n", rc); 3194 free(status); 3195 goto free_buffer; 3196 } 3197 3198 rc = nvme_wait_for_completion_timeout(ctrlr->adminq, status, 3199 ctrlr->opts.admin_timeout_ms * 1000); 3200 if (!status->timed_out) { 3201 free(status); 3202 } 3203 3204 if (rc) { 3205 NVME_CTRLR_ERRLOG(ctrlr, "wait for spdk_nvme_ctrlr_cmd_get_log_page failed: rc=%d\n", rc); 3206 goto free_buffer; 3207 } 3208 3209 /* only check the case of overflow. */ 3210 nsid = from_le32(buffer); 3211 if (nsid == 0xffffffffu) { 3212 NVME_CTRLR_WARNLOG(ctrlr, "changed ns log overflowed.\n"); 3213 } 3214 3215 free_buffer: 3216 spdk_dma_free(buffer); 3217 return rc; 3218 } 3219 3220 static void 3221 nvme_ctrlr_process_async_event(struct spdk_nvme_ctrlr *ctrlr, 3222 const struct spdk_nvme_cpl *cpl) 3223 { 3224 union spdk_nvme_async_event_completion event; 3225 struct spdk_nvme_ctrlr_process *active_proc; 3226 int rc; 3227 3228 event.raw = cpl->cdw0; 3229 3230 if ((event.bits.async_event_type == SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE) && 3231 (event.bits.async_event_info == SPDK_NVME_ASYNC_EVENT_NS_ATTR_CHANGED)) { 3232 nvme_ctrlr_clear_changed_ns_log(ctrlr); 3233 3234 rc = nvme_ctrlr_identify_active_ns(ctrlr); 3235 if (rc) { 3236 return; 3237 } 3238 nvme_ctrlr_update_namespaces(ctrlr); 3239 nvme_io_msg_ctrlr_update(ctrlr); 3240 } 3241 3242 if ((event.bits.async_event_type == SPDK_NVME_ASYNC_EVENT_TYPE_NOTICE) && 3243 (event.bits.async_event_info == SPDK_NVME_ASYNC_EVENT_ANA_CHANGE)) { 3244 if (!ctrlr->opts.disable_read_ana_log_page) { 3245 rc = nvme_ctrlr_update_ana_log_page(ctrlr); 3246 if (rc) { 3247 return; 3248 } 3249 nvme_ctrlr_parse_ana_log_page(ctrlr, nvme_ctrlr_update_ns_ana_states, 3250 ctrlr); 3251 } 3252 } 3253 3254 active_proc = nvme_ctrlr_get_current_process(ctrlr); 3255 if (active_proc && active_proc->aer_cb_fn) { 3256 active_proc->aer_cb_fn(active_proc->aer_cb_arg, cpl); 3257 } 3258 } 3259 3260 static void 3261 nvme_ctrlr_queue_async_event(struct spdk_nvme_ctrlr *ctrlr, 3262 const struct spdk_nvme_cpl *cpl) 3263 { 3264 struct spdk_nvme_ctrlr_aer_completion_list *nvme_event; 3265 struct spdk_nvme_ctrlr_process *proc; 3266 3267 /* Add async event to each process objects event list */ 3268 TAILQ_FOREACH(proc, &ctrlr->active_procs, tailq) { 3269 /* Must be shared memory so other processes can access */ 3270 nvme_event = spdk_zmalloc(sizeof(*nvme_event), 0, NULL, SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE); 3271 if (!nvme_event) { 3272 NVME_CTRLR_ERRLOG(ctrlr, "Alloc nvme event failed, ignore the event\n"); 3273 return; 3274 } 3275 nvme_event->cpl = *cpl; 3276 3277 STAILQ_INSERT_TAIL(&proc->async_events, nvme_event, link); 3278 } 3279 } 3280 3281 static void 3282 nvme_ctrlr_complete_queued_async_events(struct spdk_nvme_ctrlr *ctrlr) 3283 { 3284 struct spdk_nvme_ctrlr_aer_completion_list *nvme_event, *nvme_event_tmp; 3285 struct spdk_nvme_ctrlr_process *active_proc; 3286 3287 active_proc = nvme_ctrlr_get_current_process(ctrlr); 3288 3289 STAILQ_FOREACH_SAFE(nvme_event, &active_proc->async_events, link, nvme_event_tmp) { 3290 STAILQ_REMOVE(&active_proc->async_events, nvme_event, 3291 spdk_nvme_ctrlr_aer_completion_list, link); 3292 nvme_ctrlr_process_async_event(ctrlr, &nvme_event->cpl); 3293 spdk_free(nvme_event); 3294 3295 } 3296 } 3297 3298 static void 3299 nvme_ctrlr_async_event_cb(void *arg, const struct spdk_nvme_cpl *cpl) 3300 { 3301 struct nvme_async_event_request *aer = arg; 3302 struct spdk_nvme_ctrlr *ctrlr = aer->ctrlr; 3303 3304 if (cpl->status.sct == SPDK_NVME_SCT_GENERIC && 3305 cpl->status.sc == SPDK_NVME_SC_ABORTED_SQ_DELETION) { 3306 /* 3307 * This is simulated when controller is being shut down, to 3308 * effectively abort outstanding asynchronous event requests 3309 * and make sure all memory is freed. Do not repost the 3310 * request in this case. 3311 */ 3312 return; 3313 } 3314 3315 if (cpl->status.sct == SPDK_NVME_SCT_COMMAND_SPECIFIC && 3316 cpl->status.sc == SPDK_NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED) { 3317 /* 3318 * SPDK will only send as many AERs as the device says it supports, 3319 * so this status code indicates an out-of-spec device. Do not repost 3320 * the request in this case. 3321 */ 3322 NVME_CTRLR_ERRLOG(ctrlr, "Controller appears out-of-spec for asynchronous event request\n" 3323 "handling. Do not repost this AER.\n"); 3324 return; 3325 } 3326 3327 /* Add the events to the list */ 3328 nvme_ctrlr_queue_async_event(ctrlr, cpl); 3329 3330 /* If the ctrlr was removed or in the destruct state, we should not send aer again */ 3331 if (ctrlr->is_removed || ctrlr->is_destructed) { 3332 return; 3333 } 3334 3335 /* 3336 * Repost another asynchronous event request to replace the one 3337 * that just completed. 3338 */ 3339 if (nvme_ctrlr_construct_and_submit_aer(ctrlr, aer)) { 3340 /* 3341 * We can't do anything to recover from a failure here, 3342 * so just print a warning message and leave the AER unsubmitted. 3343 */ 3344 NVME_CTRLR_ERRLOG(ctrlr, "resubmitting AER failed!\n"); 3345 } 3346 } 3347 3348 static int 3349 nvme_ctrlr_construct_and_submit_aer(struct spdk_nvme_ctrlr *ctrlr, 3350 struct nvme_async_event_request *aer) 3351 { 3352 struct nvme_request *req; 3353 3354 aer->ctrlr = ctrlr; 3355 req = nvme_allocate_request_null(ctrlr->adminq, nvme_ctrlr_async_event_cb, aer); 3356 aer->req = req; 3357 if (req == NULL) { 3358 return -1; 3359 } 3360 3361 req->cmd.opc = SPDK_NVME_OPC_ASYNC_EVENT_REQUEST; 3362 return nvme_ctrlr_submit_admin_request(ctrlr, req); 3363 } 3364 3365 static void 3366 nvme_ctrlr_configure_aer_done(void *arg, const struct spdk_nvme_cpl *cpl) 3367 { 3368 struct nvme_async_event_request *aer; 3369 int rc; 3370 uint32_t i; 3371 struct spdk_nvme_ctrlr *ctrlr = (struct spdk_nvme_ctrlr *)arg; 3372 3373 if (spdk_nvme_cpl_is_error(cpl)) { 3374 NVME_CTRLR_NOTICELOG(ctrlr, "nvme_ctrlr_configure_aer failed!\n"); 3375 ctrlr->num_aers = 0; 3376 } else { 3377 /* aerl is a zero-based value, so we need to add 1 here. */ 3378 ctrlr->num_aers = spdk_min(NVME_MAX_ASYNC_EVENTS, (ctrlr->cdata.aerl + 1)); 3379 } 3380 3381 for (i = 0; i < ctrlr->num_aers; i++) { 3382 aer = &ctrlr->aer[i]; 3383 rc = nvme_ctrlr_construct_and_submit_aer(ctrlr, aer); 3384 if (rc) { 3385 NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_construct_and_submit_aer failed!\n"); 3386 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3387 return; 3388 } 3389 } 3390 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT, ctrlr->opts.admin_timeout_ms); 3391 } 3392 3393 static int 3394 nvme_ctrlr_configure_aer(struct spdk_nvme_ctrlr *ctrlr) 3395 { 3396 union spdk_nvme_feat_async_event_configuration config; 3397 int rc; 3398 3399 config.raw = 0; 3400 3401 if (spdk_nvme_ctrlr_is_discovery(ctrlr)) { 3402 config.bits.discovery_log_change_notice = 1; 3403 } else { 3404 config.bits.crit_warn.bits.available_spare = 1; 3405 config.bits.crit_warn.bits.temperature = 1; 3406 config.bits.crit_warn.bits.device_reliability = 1; 3407 config.bits.crit_warn.bits.read_only = 1; 3408 config.bits.crit_warn.bits.volatile_memory_backup = 1; 3409 3410 if (ctrlr->vs.raw >= SPDK_NVME_VERSION(1, 2, 0)) { 3411 if (ctrlr->cdata.oaes.ns_attribute_notices) { 3412 config.bits.ns_attr_notice = 1; 3413 } 3414 if (ctrlr->cdata.oaes.fw_activation_notices) { 3415 config.bits.fw_activation_notice = 1; 3416 } 3417 if (ctrlr->cdata.oaes.ana_change_notices) { 3418 config.bits.ana_change_notice = 1; 3419 } 3420 } 3421 if (ctrlr->vs.raw >= SPDK_NVME_VERSION(1, 3, 0) && ctrlr->cdata.lpa.telemetry) { 3422 config.bits.telemetry_log_notice = 1; 3423 } 3424 } 3425 3426 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER, 3427 ctrlr->opts.admin_timeout_ms); 3428 3429 rc = nvme_ctrlr_cmd_set_async_event_config(ctrlr, config, 3430 nvme_ctrlr_configure_aer_done, 3431 ctrlr); 3432 if (rc != 0) { 3433 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3434 return rc; 3435 } 3436 3437 return 0; 3438 } 3439 3440 struct spdk_nvme_ctrlr_process * 3441 nvme_ctrlr_get_process(struct spdk_nvme_ctrlr *ctrlr, pid_t pid) 3442 { 3443 struct spdk_nvme_ctrlr_process *active_proc; 3444 3445 TAILQ_FOREACH(active_proc, &ctrlr->active_procs, tailq) { 3446 if (active_proc->pid == pid) { 3447 return active_proc; 3448 } 3449 } 3450 3451 return NULL; 3452 } 3453 3454 struct spdk_nvme_ctrlr_process * 3455 nvme_ctrlr_get_current_process(struct spdk_nvme_ctrlr *ctrlr) 3456 { 3457 return nvme_ctrlr_get_process(ctrlr, getpid()); 3458 } 3459 3460 /** 3461 * This function will be called when a process is using the controller. 3462 * 1. For the primary process, it is called when constructing the controller. 3463 * 2. For the secondary process, it is called at probing the controller. 3464 * Note: will check whether the process is already added for the same process. 3465 */ 3466 int 3467 nvme_ctrlr_add_process(struct spdk_nvme_ctrlr *ctrlr, void *devhandle) 3468 { 3469 struct spdk_nvme_ctrlr_process *ctrlr_proc; 3470 pid_t pid = getpid(); 3471 3472 /* Check whether the process is already added or not */ 3473 if (nvme_ctrlr_get_process(ctrlr, pid)) { 3474 return 0; 3475 } 3476 3477 /* Initialize the per process properties for this ctrlr */ 3478 ctrlr_proc = spdk_zmalloc(sizeof(struct spdk_nvme_ctrlr_process), 3479 64, NULL, SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE); 3480 if (ctrlr_proc == NULL) { 3481 NVME_CTRLR_ERRLOG(ctrlr, "failed to allocate memory to track the process props\n"); 3482 3483 return -1; 3484 } 3485 3486 ctrlr_proc->is_primary = spdk_process_is_primary(); 3487 ctrlr_proc->pid = pid; 3488 STAILQ_INIT(&ctrlr_proc->active_reqs); 3489 ctrlr_proc->devhandle = devhandle; 3490 ctrlr_proc->ref = 0; 3491 TAILQ_INIT(&ctrlr_proc->allocated_io_qpairs); 3492 STAILQ_INIT(&ctrlr_proc->async_events); 3493 3494 TAILQ_INSERT_TAIL(&ctrlr->active_procs, ctrlr_proc, tailq); 3495 3496 return 0; 3497 } 3498 3499 /** 3500 * This function will be called when the process detaches the controller. 3501 * Note: the ctrlr_lock must be held when calling this function. 3502 */ 3503 static void 3504 nvme_ctrlr_remove_process(struct spdk_nvme_ctrlr *ctrlr, 3505 struct spdk_nvme_ctrlr_process *proc) 3506 { 3507 struct spdk_nvme_qpair *qpair, *tmp_qpair; 3508 3509 assert(STAILQ_EMPTY(&proc->active_reqs)); 3510 3511 TAILQ_FOREACH_SAFE(qpair, &proc->allocated_io_qpairs, per_process_tailq, tmp_qpair) { 3512 spdk_nvme_ctrlr_free_io_qpair(qpair); 3513 } 3514 3515 TAILQ_REMOVE(&ctrlr->active_procs, proc, tailq); 3516 3517 if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) { 3518 spdk_pci_device_detach(proc->devhandle); 3519 } 3520 3521 spdk_free(proc); 3522 } 3523 3524 /** 3525 * This function will be called when the process exited unexpectedly 3526 * in order to free any incomplete nvme request, allocated IO qpairs 3527 * and allocated memory. 3528 * Note: the ctrlr_lock must be held when calling this function. 3529 */ 3530 static void 3531 nvme_ctrlr_cleanup_process(struct spdk_nvme_ctrlr_process *proc) 3532 { 3533 struct nvme_request *req, *tmp_req; 3534 struct spdk_nvme_qpair *qpair, *tmp_qpair; 3535 struct spdk_nvme_ctrlr_aer_completion_list *event; 3536 3537 STAILQ_FOREACH_SAFE(req, &proc->active_reqs, stailq, tmp_req) { 3538 STAILQ_REMOVE(&proc->active_reqs, req, nvme_request, stailq); 3539 3540 assert(req->pid == proc->pid); 3541 nvme_cleanup_user_req(req); 3542 nvme_free_request(req); 3543 } 3544 3545 /* Remove async event from each process objects event list */ 3546 while (!STAILQ_EMPTY(&proc->async_events)) { 3547 event = STAILQ_FIRST(&proc->async_events); 3548 STAILQ_REMOVE_HEAD(&proc->async_events, link); 3549 spdk_free(event); 3550 } 3551 3552 TAILQ_FOREACH_SAFE(qpair, &proc->allocated_io_qpairs, per_process_tailq, tmp_qpair) { 3553 TAILQ_REMOVE(&proc->allocated_io_qpairs, qpair, per_process_tailq); 3554 3555 /* 3556 * The process may have been killed while some qpairs were in their 3557 * completion context. Clear that flag here to allow these IO 3558 * qpairs to be deleted. 3559 */ 3560 qpair->in_completion_context = 0; 3561 3562 qpair->no_deletion_notification_needed = 1; 3563 3564 spdk_nvme_ctrlr_free_io_qpair(qpair); 3565 } 3566 3567 spdk_free(proc); 3568 } 3569 3570 /** 3571 * This function will be called when destructing the controller. 3572 * 1. There is no more admin request on this controller. 3573 * 2. Clean up any left resource allocation when its associated process is gone. 3574 */ 3575 void 3576 nvme_ctrlr_free_processes(struct spdk_nvme_ctrlr *ctrlr) 3577 { 3578 struct spdk_nvme_ctrlr_process *active_proc, *tmp; 3579 3580 /* Free all the processes' properties and make sure no pending admin IOs */ 3581 TAILQ_FOREACH_SAFE(active_proc, &ctrlr->active_procs, tailq, tmp) { 3582 TAILQ_REMOVE(&ctrlr->active_procs, active_proc, tailq); 3583 3584 assert(STAILQ_EMPTY(&active_proc->active_reqs)); 3585 3586 spdk_free(active_proc); 3587 } 3588 } 3589 3590 /** 3591 * This function will be called when any other process attaches or 3592 * detaches the controller in order to cleanup those unexpectedly 3593 * terminated processes. 3594 * Note: the ctrlr_lock must be held when calling this function. 3595 */ 3596 static int 3597 nvme_ctrlr_remove_inactive_proc(struct spdk_nvme_ctrlr *ctrlr) 3598 { 3599 struct spdk_nvme_ctrlr_process *active_proc, *tmp; 3600 int active_proc_count = 0; 3601 3602 TAILQ_FOREACH_SAFE(active_proc, &ctrlr->active_procs, tailq, tmp) { 3603 if ((kill(active_proc->pid, 0) == -1) && (errno == ESRCH)) { 3604 NVME_CTRLR_ERRLOG(ctrlr, "process %d terminated unexpected\n", active_proc->pid); 3605 3606 TAILQ_REMOVE(&ctrlr->active_procs, active_proc, tailq); 3607 3608 nvme_ctrlr_cleanup_process(active_proc); 3609 } else { 3610 active_proc_count++; 3611 } 3612 } 3613 3614 return active_proc_count; 3615 } 3616 3617 void 3618 nvme_ctrlr_proc_get_ref(struct spdk_nvme_ctrlr *ctrlr) 3619 { 3620 struct spdk_nvme_ctrlr_process *active_proc; 3621 3622 nvme_ctrlr_lock(ctrlr); 3623 3624 nvme_ctrlr_remove_inactive_proc(ctrlr); 3625 3626 active_proc = nvme_ctrlr_get_current_process(ctrlr); 3627 if (active_proc) { 3628 active_proc->ref++; 3629 } 3630 3631 nvme_ctrlr_unlock(ctrlr); 3632 } 3633 3634 void 3635 nvme_ctrlr_proc_put_ref(struct spdk_nvme_ctrlr *ctrlr) 3636 { 3637 struct spdk_nvme_ctrlr_process *active_proc; 3638 int proc_count; 3639 3640 nvme_ctrlr_lock(ctrlr); 3641 3642 proc_count = nvme_ctrlr_remove_inactive_proc(ctrlr); 3643 3644 active_proc = nvme_ctrlr_get_current_process(ctrlr); 3645 if (active_proc) { 3646 active_proc->ref--; 3647 assert(active_proc->ref >= 0); 3648 3649 /* 3650 * The last active process will be removed at the end of 3651 * the destruction of the controller. 3652 */ 3653 if (active_proc->ref == 0 && proc_count != 1) { 3654 nvme_ctrlr_remove_process(ctrlr, active_proc); 3655 } 3656 } 3657 3658 nvme_ctrlr_unlock(ctrlr); 3659 } 3660 3661 int 3662 nvme_ctrlr_get_ref_count(struct spdk_nvme_ctrlr *ctrlr) 3663 { 3664 struct spdk_nvme_ctrlr_process *active_proc; 3665 int ref = 0; 3666 3667 nvme_ctrlr_lock(ctrlr); 3668 3669 nvme_ctrlr_remove_inactive_proc(ctrlr); 3670 3671 TAILQ_FOREACH(active_proc, &ctrlr->active_procs, tailq) { 3672 ref += active_proc->ref; 3673 } 3674 3675 nvme_ctrlr_unlock(ctrlr); 3676 3677 return ref; 3678 } 3679 3680 /** 3681 * Get the PCI device handle which is only visible to its associated process. 3682 */ 3683 struct spdk_pci_device * 3684 nvme_ctrlr_proc_get_devhandle(struct spdk_nvme_ctrlr *ctrlr) 3685 { 3686 struct spdk_nvme_ctrlr_process *active_proc; 3687 struct spdk_pci_device *devhandle = NULL; 3688 3689 nvme_ctrlr_lock(ctrlr); 3690 3691 active_proc = nvme_ctrlr_get_current_process(ctrlr); 3692 if (active_proc) { 3693 devhandle = active_proc->devhandle; 3694 } 3695 3696 nvme_ctrlr_unlock(ctrlr); 3697 3698 return devhandle; 3699 } 3700 3701 static void 3702 nvme_ctrlr_process_init_vs_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl) 3703 { 3704 struct spdk_nvme_ctrlr *ctrlr = ctx; 3705 3706 if (spdk_nvme_cpl_is_error(cpl)) { 3707 NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the VS register\n"); 3708 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3709 return; 3710 } 3711 3712 assert(value <= UINT32_MAX); 3713 ctrlr->vs.raw = (uint32_t)value; 3714 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_CAP, NVME_TIMEOUT_INFINITE); 3715 } 3716 3717 static void 3718 nvme_ctrlr_process_init_cap_done(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl) 3719 { 3720 struct spdk_nvme_ctrlr *ctrlr = ctx; 3721 3722 if (spdk_nvme_cpl_is_error(cpl)) { 3723 NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CAP register\n"); 3724 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3725 return; 3726 } 3727 3728 ctrlr->cap.raw = value; 3729 nvme_ctrlr_init_cap(ctrlr); 3730 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN, NVME_TIMEOUT_INFINITE); 3731 } 3732 3733 static void 3734 nvme_ctrlr_process_init_check_en(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl) 3735 { 3736 struct spdk_nvme_ctrlr *ctrlr = ctx; 3737 enum nvme_ctrlr_state state; 3738 3739 if (spdk_nvme_cpl_is_error(cpl)) { 3740 NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n"); 3741 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3742 return; 3743 } 3744 3745 assert(value <= UINT32_MAX); 3746 ctrlr->process_init_cc.raw = (uint32_t)value; 3747 3748 if (ctrlr->process_init_cc.bits.en) { 3749 NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1\n"); 3750 state = NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1; 3751 } else { 3752 state = NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0; 3753 } 3754 3755 nvme_ctrlr_set_state(ctrlr, state, nvme_ctrlr_get_ready_timeout(ctrlr)); 3756 } 3757 3758 static void 3759 nvme_ctrlr_process_init_set_en_0(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl) 3760 { 3761 struct spdk_nvme_ctrlr *ctrlr = ctx; 3762 3763 if (spdk_nvme_cpl_is_error(cpl)) { 3764 NVME_CTRLR_ERRLOG(ctrlr, "Failed to write the CC register\n"); 3765 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3766 return; 3767 } 3768 3769 /* 3770 * Wait 2.5 seconds before accessing PCI registers. 3771 * Not using sleep() to avoid blocking other controller's initialization. 3772 */ 3773 if (ctrlr->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY) { 3774 NVME_CTRLR_DEBUGLOG(ctrlr, "Applying quirk: delay 2.5 seconds before reading registers\n"); 3775 ctrlr->sleep_timeout_tsc = spdk_get_ticks() + (2500 * spdk_get_ticks_hz() / 1000); 3776 } 3777 3778 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0, 3779 nvme_ctrlr_get_ready_timeout(ctrlr)); 3780 } 3781 3782 static void 3783 nvme_ctrlr_process_init_set_en_0_read_cc(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl) 3784 { 3785 struct spdk_nvme_ctrlr *ctrlr = ctx; 3786 union spdk_nvme_cc_register cc; 3787 int rc; 3788 3789 if (spdk_nvme_cpl_is_error(cpl)) { 3790 NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CC register\n"); 3791 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3792 return; 3793 } 3794 3795 assert(value <= UINT32_MAX); 3796 cc.raw = (uint32_t)value; 3797 cc.bits.en = 0; 3798 ctrlr->process_init_cc.raw = cc.raw; 3799 3800 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC, 3801 nvme_ctrlr_get_ready_timeout(ctrlr)); 3802 3803 rc = nvme_ctrlr_set_cc_async(ctrlr, cc.raw, nvme_ctrlr_process_init_set_en_0, ctrlr); 3804 if (rc != 0) { 3805 NVME_CTRLR_ERRLOG(ctrlr, "set_cc() failed\n"); 3806 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3807 } 3808 } 3809 3810 static void 3811 nvme_ctrlr_process_init_wait_for_ready_1(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl) 3812 { 3813 struct spdk_nvme_ctrlr *ctrlr = ctx; 3814 union spdk_nvme_csts_register csts; 3815 3816 if (spdk_nvme_cpl_is_error(cpl)) { 3817 /* While a device is resetting, it may be unable to service MMIO reads 3818 * temporarily. Allow for this case. 3819 */ 3820 if (!ctrlr->is_failed && ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE) { 3821 NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to read the CSTS register\n"); 3822 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1, 3823 NVME_TIMEOUT_KEEP_EXISTING); 3824 } else { 3825 NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n"); 3826 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3827 } 3828 3829 return; 3830 } 3831 3832 assert(value <= UINT32_MAX); 3833 csts.raw = (uint32_t)value; 3834 if (csts.bits.rdy == 1 || csts.bits.cfs == 1) { 3835 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_EN_0, 3836 nvme_ctrlr_get_ready_timeout(ctrlr)); 3837 } else { 3838 NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1 && CSTS.RDY = 0 - waiting for reset to complete\n"); 3839 nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1, 3840 NVME_TIMEOUT_KEEP_EXISTING); 3841 } 3842 } 3843 3844 static void 3845 nvme_ctrlr_process_init_wait_for_ready_0(void *ctx, uint64_t value, const struct spdk_nvme_cpl *cpl) 3846 { 3847 struct spdk_nvme_ctrlr *ctrlr = ctx; 3848 union spdk_nvme_csts_register csts; 3849 3850 if (spdk_nvme_cpl_is_error(cpl)) { 3851 /* While a device is resetting, it may be unable to service MMIO reads 3852 * temporarily. Allow for this case. 3853 */ 3854 if (!ctrlr->is_failed && ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE) { 3855 NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to read the CSTS register\n"); 3856 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0, 3857 NVME_TIMEOUT_KEEP_EXISTING); 3858 } else { 3859 NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n"); 3860 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3861 } 3862 3863 return; 3864 } 3865 3866 assert(value <= UINT32_MAX); 3867 csts.raw = (uint32_t)value; 3868 if (csts.bits.rdy == 0) { 3869 NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 0 && CSTS.RDY = 0\n"); 3870 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_DISABLED, 3871 nvme_ctrlr_get_ready_timeout(ctrlr)); 3872 } else { 3873 nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0, 3874 NVME_TIMEOUT_KEEP_EXISTING); 3875 } 3876 } 3877 3878 static void 3879 nvme_ctrlr_process_init_enable_wait_for_ready_1(void *ctx, uint64_t value, 3880 const struct spdk_nvme_cpl *cpl) 3881 { 3882 struct spdk_nvme_ctrlr *ctrlr = ctx; 3883 union spdk_nvme_csts_register csts; 3884 3885 if (spdk_nvme_cpl_is_error(cpl)) { 3886 /* While a device is resetting, it may be unable to service MMIO reads 3887 * temporarily. Allow for this case. 3888 */ 3889 if (!ctrlr->is_failed && ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE) { 3890 NVME_CTRLR_DEBUGLOG(ctrlr, "Failed to read the CSTS register\n"); 3891 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1, 3892 NVME_TIMEOUT_KEEP_EXISTING); 3893 } else { 3894 NVME_CTRLR_ERRLOG(ctrlr, "Failed to read the CSTS register\n"); 3895 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3896 } 3897 3898 return; 3899 } 3900 3901 assert(value <= UINT32_MAX); 3902 csts.raw = value; 3903 if (csts.bits.rdy == 1) { 3904 NVME_CTRLR_DEBUGLOG(ctrlr, "CC.EN = 1 && CSTS.RDY = 1 - controller is ready\n"); 3905 /* 3906 * The controller has been enabled. 3907 * Perform the rest of initialization serially. 3908 */ 3909 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_RESET_ADMIN_QUEUE, 3910 ctrlr->opts.admin_timeout_ms); 3911 } else { 3912 nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1, 3913 NVME_TIMEOUT_KEEP_EXISTING); 3914 } 3915 } 3916 3917 /** 3918 * This function will be called repeatedly during initialization until the controller is ready. 3919 */ 3920 int 3921 nvme_ctrlr_process_init(struct spdk_nvme_ctrlr *ctrlr) 3922 { 3923 uint32_t ready_timeout_in_ms; 3924 uint64_t ticks; 3925 int rc = 0; 3926 3927 ticks = spdk_get_ticks(); 3928 3929 /* 3930 * May need to avoid accessing any register on the target controller 3931 * for a while. Return early without touching the FSM. 3932 * Check sleep_timeout_tsc > 0 for unit test. 3933 */ 3934 if ((ctrlr->sleep_timeout_tsc > 0) && 3935 (ticks <= ctrlr->sleep_timeout_tsc)) { 3936 return 0; 3937 } 3938 ctrlr->sleep_timeout_tsc = 0; 3939 3940 ready_timeout_in_ms = nvme_ctrlr_get_ready_timeout(ctrlr); 3941 3942 /* 3943 * Check if the current initialization step is done or has timed out. 3944 */ 3945 switch (ctrlr->state) { 3946 case NVME_CTRLR_STATE_INIT_DELAY: 3947 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, ready_timeout_in_ms); 3948 if (ctrlr->quirks & NVME_QUIRK_DELAY_BEFORE_INIT) { 3949 /* 3950 * Controller may need some delay before it's enabled. 3951 * 3952 * This is a workaround for an issue where the PCIe-attached NVMe controller 3953 * is not ready after VFIO reset. We delay the initialization rather than the 3954 * enabling itself, because this is required only for the very first enabling 3955 * - directly after a VFIO reset. 3956 */ 3957 NVME_CTRLR_DEBUGLOG(ctrlr, "Adding 2 second delay before initializing the controller\n"); 3958 ctrlr->sleep_timeout_tsc = ticks + (2000 * spdk_get_ticks_hz() / 1000); 3959 } 3960 break; 3961 3962 case NVME_CTRLR_STATE_DISCONNECTED: 3963 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE); 3964 break; 3965 3966 case NVME_CTRLR_STATE_CONNECT_ADMINQ: /* synonymous with NVME_CTRLR_STATE_INIT and NVME_CTRLR_STATE_DISCONNECTED */ 3967 rc = nvme_transport_ctrlr_connect_qpair(ctrlr, ctrlr->adminq); 3968 if (rc == 0) { 3969 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_WAIT_FOR_CONNECT_ADMINQ, 3970 NVME_TIMEOUT_INFINITE); 3971 } else { 3972 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 3973 } 3974 break; 3975 3976 case NVME_CTRLR_STATE_WAIT_FOR_CONNECT_ADMINQ: 3977 spdk_nvme_qpair_process_completions(ctrlr->adminq, 0); 3978 3979 switch (nvme_qpair_get_state(ctrlr->adminq)) { 3980 case NVME_QPAIR_CONNECTING: 3981 break; 3982 case NVME_QPAIR_CONNECTED: 3983 nvme_qpair_set_state(ctrlr->adminq, NVME_QPAIR_ENABLED); 3984 /* Fall through */ 3985 case NVME_QPAIR_ENABLED: 3986 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_VS, 3987 NVME_TIMEOUT_INFINITE); 3988 /* Abort any queued requests that were sent while the adminq was connecting 3989 * to avoid stalling the init process during a reset, as requests don't get 3990 * resubmitted while the controller is resetting and subsequent commands 3991 * would get queued too. 3992 */ 3993 nvme_qpair_abort_queued_reqs(ctrlr->adminq); 3994 break; 3995 case NVME_QPAIR_DISCONNECTING: 3996 assert(ctrlr->adminq->async == true); 3997 break; 3998 case NVME_QPAIR_DISCONNECTED: 3999 /* fallthrough */ 4000 default: 4001 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 4002 break; 4003 } 4004 4005 break; 4006 4007 case NVME_CTRLR_STATE_READ_VS: 4008 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS, NVME_TIMEOUT_INFINITE); 4009 rc = nvme_ctrlr_get_vs_async(ctrlr, nvme_ctrlr_process_init_vs_done, ctrlr); 4010 break; 4011 4012 case NVME_CTRLR_STATE_READ_CAP: 4013 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP, NVME_TIMEOUT_INFINITE); 4014 rc = nvme_ctrlr_get_cap_async(ctrlr, nvme_ctrlr_process_init_cap_done, ctrlr); 4015 break; 4016 4017 case NVME_CTRLR_STATE_CHECK_EN: 4018 /* Begin the hardware initialization by making sure the controller is disabled. */ 4019 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_CHECK_EN_WAIT_FOR_CC, ready_timeout_in_ms); 4020 rc = nvme_ctrlr_get_cc_async(ctrlr, nvme_ctrlr_process_init_check_en, ctrlr); 4021 break; 4022 4023 case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1: 4024 /* 4025 * Controller is currently enabled. We need to disable it to cause a reset. 4026 * 4027 * If CC.EN = 1 && CSTS.RDY = 0, the controller is in the process of becoming ready. 4028 * Wait for the ready bit to be 1 before disabling the controller. 4029 */ 4030 nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS, 4031 NVME_TIMEOUT_KEEP_EXISTING); 4032 rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_wait_for_ready_1, ctrlr); 4033 break; 4034 4035 case NVME_CTRLR_STATE_SET_EN_0: 4036 NVME_CTRLR_DEBUGLOG(ctrlr, "Setting CC.EN = 0\n"); 4037 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC, ready_timeout_in_ms); 4038 rc = nvme_ctrlr_get_cc_async(ctrlr, nvme_ctrlr_process_init_set_en_0_read_cc, ctrlr); 4039 break; 4040 4041 case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0: 4042 nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS, 4043 NVME_TIMEOUT_KEEP_EXISTING); 4044 rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_wait_for_ready_0, ctrlr); 4045 break; 4046 4047 case NVME_CTRLR_STATE_DISABLED: 4048 if (ctrlr->is_disconnecting) { 4049 NVME_CTRLR_DEBUGLOG(ctrlr, "Ctrlr was disabled.\n"); 4050 } else { 4051 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE, ready_timeout_in_ms); 4052 4053 /* 4054 * Delay 100us before setting CC.EN = 1. Some NVMe SSDs miss CC.EN getting 4055 * set to 1 if it is too soon after CSTS.RDY is reported as 0. 4056 */ 4057 spdk_delay_us(100); 4058 } 4059 break; 4060 4061 case NVME_CTRLR_STATE_ENABLE: 4062 NVME_CTRLR_DEBUGLOG(ctrlr, "Setting CC.EN = 1\n"); 4063 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC, ready_timeout_in_ms); 4064 rc = nvme_ctrlr_enable(ctrlr); 4065 if (rc) { 4066 NVME_CTRLR_ERRLOG(ctrlr, "Ctrlr enable failed with error: %d", rc); 4067 } 4068 return rc; 4069 4070 case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1: 4071 nvme_ctrlr_set_state_quiet(ctrlr, NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS, 4072 NVME_TIMEOUT_KEEP_EXISTING); 4073 rc = nvme_ctrlr_get_csts_async(ctrlr, nvme_ctrlr_process_init_enable_wait_for_ready_1, 4074 ctrlr); 4075 break; 4076 4077 case NVME_CTRLR_STATE_RESET_ADMIN_QUEUE: 4078 nvme_transport_qpair_reset(ctrlr->adminq); 4079 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_IDENTIFY, NVME_TIMEOUT_INFINITE); 4080 break; 4081 4082 case NVME_CTRLR_STATE_IDENTIFY: 4083 rc = nvme_ctrlr_identify(ctrlr); 4084 break; 4085 4086 case NVME_CTRLR_STATE_CONFIGURE_AER: 4087 rc = nvme_ctrlr_configure_aer(ctrlr); 4088 break; 4089 4090 case NVME_CTRLR_STATE_SET_KEEP_ALIVE_TIMEOUT: 4091 rc = nvme_ctrlr_set_keep_alive_timeout(ctrlr); 4092 break; 4093 4094 case NVME_CTRLR_STATE_IDENTIFY_IOCS_SPECIFIC: 4095 rc = nvme_ctrlr_identify_iocs_specific(ctrlr); 4096 break; 4097 4098 case NVME_CTRLR_STATE_GET_ZNS_CMD_EFFECTS_LOG: 4099 rc = nvme_ctrlr_get_zns_cmd_and_effects_log(ctrlr); 4100 break; 4101 4102 case NVME_CTRLR_STATE_SET_NUM_QUEUES: 4103 nvme_ctrlr_update_nvmf_ioccsz(ctrlr); 4104 rc = nvme_ctrlr_set_num_queues(ctrlr); 4105 break; 4106 4107 case NVME_CTRLR_STATE_IDENTIFY_ACTIVE_NS: 4108 _nvme_ctrlr_identify_active_ns(ctrlr); 4109 break; 4110 4111 case NVME_CTRLR_STATE_IDENTIFY_NS: 4112 rc = nvme_ctrlr_identify_namespaces(ctrlr); 4113 break; 4114 4115 case NVME_CTRLR_STATE_IDENTIFY_ID_DESCS: 4116 rc = nvme_ctrlr_identify_id_desc_namespaces(ctrlr); 4117 break; 4118 4119 case NVME_CTRLR_STATE_IDENTIFY_NS_IOCS_SPECIFIC: 4120 rc = nvme_ctrlr_identify_namespaces_iocs_specific(ctrlr); 4121 break; 4122 4123 case NVME_CTRLR_STATE_SET_SUPPORTED_LOG_PAGES: 4124 rc = nvme_ctrlr_set_supported_log_pages(ctrlr); 4125 break; 4126 4127 case NVME_CTRLR_STATE_SET_SUPPORTED_INTEL_LOG_PAGES: 4128 rc = nvme_ctrlr_set_intel_support_log_pages(ctrlr); 4129 break; 4130 4131 case NVME_CTRLR_STATE_SET_SUPPORTED_FEATURES: 4132 nvme_ctrlr_set_supported_features(ctrlr); 4133 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_SET_HOST_FEATURE, 4134 ctrlr->opts.admin_timeout_ms); 4135 break; 4136 4137 case NVME_CTRLR_STATE_SET_HOST_FEATURE: 4138 rc = nvme_ctrlr_set_host_feature(ctrlr); 4139 break; 4140 4141 case NVME_CTRLR_STATE_SET_DB_BUF_CFG: 4142 rc = nvme_ctrlr_set_doorbell_buffer_config(ctrlr); 4143 break; 4144 4145 case NVME_CTRLR_STATE_SET_HOST_ID: 4146 rc = nvme_ctrlr_set_host_id(ctrlr); 4147 break; 4148 4149 case NVME_CTRLR_STATE_TRANSPORT_READY: 4150 rc = nvme_transport_ctrlr_ready(ctrlr); 4151 if (rc) { 4152 NVME_CTRLR_ERRLOG(ctrlr, "Transport controller ready step failed: rc %d\n", rc); 4153 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_ERROR, NVME_TIMEOUT_INFINITE); 4154 } else { 4155 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_READY, NVME_TIMEOUT_INFINITE); 4156 } 4157 break; 4158 4159 case NVME_CTRLR_STATE_READY: 4160 NVME_CTRLR_DEBUGLOG(ctrlr, "Ctrlr already in ready state\n"); 4161 return 0; 4162 4163 case NVME_CTRLR_STATE_ERROR: 4164 NVME_CTRLR_ERRLOG(ctrlr, "Ctrlr is in error state\n"); 4165 return -1; 4166 4167 case NVME_CTRLR_STATE_READ_VS_WAIT_FOR_VS: 4168 case NVME_CTRLR_STATE_READ_CAP_WAIT_FOR_CAP: 4169 case NVME_CTRLR_STATE_CHECK_EN_WAIT_FOR_CC: 4170 case NVME_CTRLR_STATE_SET_EN_0_WAIT_FOR_CC: 4171 case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS: 4172 case NVME_CTRLR_STATE_DISABLE_WAIT_FOR_READY_0_WAIT_FOR_CSTS: 4173 case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_CC: 4174 case NVME_CTRLR_STATE_ENABLE_WAIT_FOR_READY_1_WAIT_FOR_CSTS: 4175 case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY: 4176 case NVME_CTRLR_STATE_WAIT_FOR_CONFIGURE_AER: 4177 case NVME_CTRLR_STATE_WAIT_FOR_KEEP_ALIVE_TIMEOUT: 4178 case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_IOCS_SPECIFIC: 4179 case NVME_CTRLR_STATE_WAIT_FOR_GET_ZNS_CMD_EFFECTS_LOG: 4180 case NVME_CTRLR_STATE_WAIT_FOR_SET_NUM_QUEUES: 4181 case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ACTIVE_NS: 4182 case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS: 4183 case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_ID_DESCS: 4184 case NVME_CTRLR_STATE_WAIT_FOR_IDENTIFY_NS_IOCS_SPECIFIC: 4185 case NVME_CTRLR_STATE_WAIT_FOR_SUPPORTED_INTEL_LOG_PAGES: 4186 case NVME_CTRLR_STATE_WAIT_FOR_SET_HOST_FEATURE: 4187 case NVME_CTRLR_STATE_WAIT_FOR_DB_BUF_CFG: 4188 case NVME_CTRLR_STATE_WAIT_FOR_HOST_ID: 4189 /* 4190 * nvme_ctrlr_process_init() may be called from the completion context 4191 * for the admin qpair. Avoid recursive calls for this case. 4192 */ 4193 if (!ctrlr->adminq->in_completion_context) { 4194 spdk_nvme_qpair_process_completions(ctrlr->adminq, 0); 4195 } 4196 break; 4197 4198 default: 4199 assert(0); 4200 return -1; 4201 } 4202 4203 if (rc) { 4204 NVME_CTRLR_ERRLOG(ctrlr, "Ctrlr operation failed with error: %d, ctrlr state: %d (%s)\n", 4205 rc, ctrlr->state, nvme_ctrlr_state_string(ctrlr->state)); 4206 } 4207 4208 /* Note: we use the ticks captured when we entered this function. 4209 * This covers environments where the SPDK process gets swapped out after 4210 * we tried to advance the state but before we check the timeout here. 4211 * It is not normal for this to happen, but harmless to handle it in this 4212 * way. 4213 */ 4214 if (ctrlr->state_timeout_tsc != NVME_TIMEOUT_INFINITE && 4215 ticks > ctrlr->state_timeout_tsc) { 4216 NVME_CTRLR_ERRLOG(ctrlr, "Initialization timed out in state %d (%s)\n", 4217 ctrlr->state, nvme_ctrlr_state_string(ctrlr->state)); 4218 return -1; 4219 } 4220 4221 return rc; 4222 } 4223 4224 int 4225 nvme_robust_mutex_init_recursive_shared(pthread_mutex_t *mtx) 4226 { 4227 pthread_mutexattr_t attr; 4228 int rc = 0; 4229 4230 if (pthread_mutexattr_init(&attr)) { 4231 return -1; 4232 } 4233 if (pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_RECURSIVE) || 4234 #ifndef __FreeBSD__ 4235 pthread_mutexattr_setrobust(&attr, PTHREAD_MUTEX_ROBUST) || 4236 pthread_mutexattr_setpshared(&attr, PTHREAD_PROCESS_SHARED) || 4237 #endif 4238 pthread_mutex_init(mtx, &attr)) { 4239 rc = -1; 4240 } 4241 pthread_mutexattr_destroy(&attr); 4242 return rc; 4243 } 4244 4245 int 4246 nvme_ctrlr_construct(struct spdk_nvme_ctrlr *ctrlr) 4247 { 4248 int rc; 4249 4250 if (ctrlr->trid.trtype == SPDK_NVME_TRANSPORT_PCIE) { 4251 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT_DELAY, NVME_TIMEOUT_INFINITE); 4252 } else { 4253 nvme_ctrlr_set_state(ctrlr, NVME_CTRLR_STATE_INIT, NVME_TIMEOUT_INFINITE); 4254 } 4255 4256 if (ctrlr->opts.admin_queue_size > SPDK_NVME_ADMIN_QUEUE_MAX_ENTRIES) { 4257 NVME_CTRLR_ERRLOG(ctrlr, "admin_queue_size %u exceeds max defined by NVMe spec, use max value\n", 4258 ctrlr->opts.admin_queue_size); 4259 ctrlr->opts.admin_queue_size = SPDK_NVME_ADMIN_QUEUE_MAX_ENTRIES; 4260 } 4261 4262 if (ctrlr->quirks & NVME_QUIRK_MINIMUM_ADMIN_QUEUE_SIZE && 4263 (ctrlr->opts.admin_queue_size % SPDK_NVME_ADMIN_QUEUE_QUIRK_ENTRIES_MULTIPLE) != 0) { 4264 NVME_CTRLR_ERRLOG(ctrlr, 4265 "admin_queue_size %u is invalid for this NVMe device, adjust to next multiple\n", 4266 ctrlr->opts.admin_queue_size); 4267 ctrlr->opts.admin_queue_size = SPDK_ALIGN_CEIL(ctrlr->opts.admin_queue_size, 4268 SPDK_NVME_ADMIN_QUEUE_QUIRK_ENTRIES_MULTIPLE); 4269 } 4270 4271 if (ctrlr->opts.admin_queue_size < SPDK_NVME_ADMIN_QUEUE_MIN_ENTRIES) { 4272 NVME_CTRLR_ERRLOG(ctrlr, 4273 "admin_queue_size %u is less than minimum defined by NVMe spec, use min value\n", 4274 ctrlr->opts.admin_queue_size); 4275 ctrlr->opts.admin_queue_size = SPDK_NVME_ADMIN_QUEUE_MIN_ENTRIES; 4276 } 4277 4278 ctrlr->flags = 0; 4279 ctrlr->free_io_qids = NULL; 4280 ctrlr->is_resetting = false; 4281 ctrlr->is_failed = false; 4282 ctrlr->is_destructed = false; 4283 4284 TAILQ_INIT(&ctrlr->active_io_qpairs); 4285 STAILQ_INIT(&ctrlr->queued_aborts); 4286 ctrlr->outstanding_aborts = 0; 4287 4288 ctrlr->ana_log_page = NULL; 4289 ctrlr->ana_log_page_size = 0; 4290 4291 rc = nvme_robust_mutex_init_recursive_shared(&ctrlr->ctrlr_lock); 4292 if (rc != 0) { 4293 return rc; 4294 } 4295 4296 TAILQ_INIT(&ctrlr->active_procs); 4297 STAILQ_INIT(&ctrlr->register_operations); 4298 4299 RB_INIT(&ctrlr->ns); 4300 4301 return rc; 4302 } 4303 4304 static void 4305 nvme_ctrlr_init_cap(struct spdk_nvme_ctrlr *ctrlr) 4306 { 4307 if (ctrlr->cap.bits.ams & SPDK_NVME_CAP_AMS_WRR) { 4308 ctrlr->flags |= SPDK_NVME_CTRLR_WRR_SUPPORTED; 4309 } 4310 4311 ctrlr->min_page_size = 1u << (12 + ctrlr->cap.bits.mpsmin); 4312 4313 /* For now, always select page_size == min_page_size. */ 4314 ctrlr->page_size = ctrlr->min_page_size; 4315 4316 ctrlr->opts.io_queue_size = spdk_max(ctrlr->opts.io_queue_size, SPDK_NVME_IO_QUEUE_MIN_ENTRIES); 4317 ctrlr->opts.io_queue_size = spdk_min(ctrlr->opts.io_queue_size, MAX_IO_QUEUE_ENTRIES); 4318 if (ctrlr->quirks & NVME_QUIRK_MINIMUM_IO_QUEUE_SIZE && 4319 ctrlr->opts.io_queue_size == DEFAULT_IO_QUEUE_SIZE) { 4320 /* If the user specifically set an IO queue size different than the 4321 * default, use that value. Otherwise overwrite with the quirked value. 4322 * This allows this quirk to be overridden when necessary. 4323 * However, cap.mqes still needs to be respected. 4324 */ 4325 ctrlr->opts.io_queue_size = DEFAULT_IO_QUEUE_SIZE_FOR_QUIRK; 4326 } 4327 ctrlr->opts.io_queue_size = spdk_min(ctrlr->opts.io_queue_size, ctrlr->cap.bits.mqes + 1u); 4328 4329 ctrlr->opts.io_queue_requests = spdk_max(ctrlr->opts.io_queue_requests, ctrlr->opts.io_queue_size); 4330 } 4331 4332 void 4333 nvme_ctrlr_destruct_finish(struct spdk_nvme_ctrlr *ctrlr) 4334 { 4335 int rc; 4336 4337 if (ctrlr->lock_depth > 0) { 4338 SPDK_ERRLOG("lock currently held (depth=%d)!\n", ctrlr->lock_depth); 4339 assert(false); 4340 } 4341 4342 rc = pthread_mutex_destroy(&ctrlr->ctrlr_lock); 4343 if (rc) { 4344 SPDK_ERRLOG("could not destroy ctrlr_lock: %s\n", spdk_strerror(rc)); 4345 assert(false); 4346 } 4347 4348 nvme_ctrlr_free_processes(ctrlr); 4349 } 4350 4351 void 4352 nvme_ctrlr_destruct_async(struct spdk_nvme_ctrlr *ctrlr, 4353 struct nvme_ctrlr_detach_ctx *ctx) 4354 { 4355 struct spdk_nvme_qpair *qpair, *tmp; 4356 4357 NVME_CTRLR_DEBUGLOG(ctrlr, "Prepare to destruct SSD\n"); 4358 4359 ctrlr->prepare_for_reset = false; 4360 ctrlr->is_destructed = true; 4361 4362 spdk_nvme_qpair_process_completions(ctrlr->adminq, 0); 4363 4364 nvme_ctrlr_abort_queued_aborts(ctrlr); 4365 nvme_transport_admin_qpair_abort_aers(ctrlr->adminq); 4366 4367 TAILQ_FOREACH_SAFE(qpair, &ctrlr->active_io_qpairs, tailq, tmp) { 4368 spdk_nvme_ctrlr_free_io_qpair(qpair); 4369 } 4370 4371 nvme_ctrlr_free_doorbell_buffer(ctrlr); 4372 nvme_ctrlr_free_iocs_specific_data(ctrlr); 4373 4374 nvme_ctrlr_shutdown_async(ctrlr, ctx); 4375 } 4376 4377 int 4378 nvme_ctrlr_destruct_poll_async(struct spdk_nvme_ctrlr *ctrlr, 4379 struct nvme_ctrlr_detach_ctx *ctx) 4380 { 4381 struct spdk_nvme_ns *ns, *tmp_ns; 4382 int rc = 0; 4383 4384 if (!ctx->shutdown_complete) { 4385 rc = nvme_ctrlr_shutdown_poll_async(ctrlr, ctx); 4386 if (rc == -EAGAIN) { 4387 return -EAGAIN; 4388 } 4389 /* Destruct ctrlr forcefully for any other error. */ 4390 } 4391 4392 if (ctx->cb_fn) { 4393 ctx->cb_fn(ctrlr); 4394 } 4395 4396 nvme_transport_ctrlr_disconnect_qpair(ctrlr, ctrlr->adminq); 4397 4398 RB_FOREACH_SAFE(ns, nvme_ns_tree, &ctrlr->ns, tmp_ns) { 4399 nvme_ctrlr_destruct_namespace(ctrlr, ns->id); 4400 RB_REMOVE(nvme_ns_tree, &ctrlr->ns, ns); 4401 spdk_free(ns); 4402 } 4403 4404 ctrlr->active_ns_count = 0; 4405 4406 spdk_bit_array_free(&ctrlr->free_io_qids); 4407 4408 free(ctrlr->ana_log_page); 4409 free(ctrlr->copied_ana_desc); 4410 ctrlr->ana_log_page = NULL; 4411 ctrlr->copied_ana_desc = NULL; 4412 ctrlr->ana_log_page_size = 0; 4413 4414 nvme_transport_ctrlr_destruct(ctrlr); 4415 4416 return rc; 4417 } 4418 4419 void 4420 nvme_ctrlr_destruct(struct spdk_nvme_ctrlr *ctrlr) 4421 { 4422 struct nvme_ctrlr_detach_ctx ctx = { .ctrlr = ctrlr }; 4423 int rc; 4424 4425 nvme_ctrlr_destruct_async(ctrlr, &ctx); 4426 4427 while (1) { 4428 rc = nvme_ctrlr_destruct_poll_async(ctrlr, &ctx); 4429 if (rc != -EAGAIN) { 4430 break; 4431 } 4432 nvme_delay(1000); 4433 } 4434 } 4435 4436 int 4437 nvme_ctrlr_submit_admin_request(struct spdk_nvme_ctrlr *ctrlr, 4438 struct nvme_request *req) 4439 { 4440 return nvme_qpair_submit_request(ctrlr->adminq, req); 4441 } 4442 4443 static void 4444 nvme_keep_alive_completion(void *cb_ctx, const struct spdk_nvme_cpl *cpl) 4445 { 4446 /* Do nothing */ 4447 } 4448 4449 /* 4450 * Check if we need to send a Keep Alive command. 4451 * Caller must hold ctrlr->ctrlr_lock. 4452 */ 4453 static int 4454 nvme_ctrlr_keep_alive(struct spdk_nvme_ctrlr *ctrlr) 4455 { 4456 uint64_t now; 4457 struct nvme_request *req; 4458 struct spdk_nvme_cmd *cmd; 4459 int rc = 0; 4460 4461 now = spdk_get_ticks(); 4462 if (now < ctrlr->next_keep_alive_tick) { 4463 return rc; 4464 } 4465 4466 req = nvme_allocate_request_null(ctrlr->adminq, nvme_keep_alive_completion, NULL); 4467 if (req == NULL) { 4468 return rc; 4469 } 4470 4471 cmd = &req->cmd; 4472 cmd->opc = SPDK_NVME_OPC_KEEP_ALIVE; 4473 4474 rc = nvme_ctrlr_submit_admin_request(ctrlr, req); 4475 if (rc != 0) { 4476 NVME_CTRLR_ERRLOG(ctrlr, "Submitting Keep Alive failed\n"); 4477 rc = -ENXIO; 4478 } 4479 4480 ctrlr->next_keep_alive_tick = now + ctrlr->keep_alive_interval_ticks; 4481 return rc; 4482 } 4483 4484 int32_t 4485 spdk_nvme_ctrlr_process_admin_completions(struct spdk_nvme_ctrlr *ctrlr) 4486 { 4487 int32_t num_completions; 4488 int32_t rc; 4489 struct spdk_nvme_ctrlr_process *active_proc; 4490 4491 nvme_ctrlr_lock(ctrlr); 4492 4493 if (ctrlr->keep_alive_interval_ticks) { 4494 rc = nvme_ctrlr_keep_alive(ctrlr); 4495 if (rc) { 4496 nvme_ctrlr_unlock(ctrlr); 4497 return rc; 4498 } 4499 } 4500 4501 rc = nvme_io_msg_process(ctrlr); 4502 if (rc < 0) { 4503 nvme_ctrlr_unlock(ctrlr); 4504 return rc; 4505 } 4506 num_completions = rc; 4507 4508 rc = spdk_nvme_qpair_process_completions(ctrlr->adminq, 0); 4509 4510 /* Each process has an async list, complete the ones for this process object */ 4511 active_proc = nvme_ctrlr_get_current_process(ctrlr); 4512 if (active_proc) { 4513 nvme_ctrlr_complete_queued_async_events(ctrlr); 4514 } 4515 4516 if (rc == -ENXIO && ctrlr->is_disconnecting) { 4517 nvme_ctrlr_disconnect_done(ctrlr); 4518 } 4519 4520 nvme_ctrlr_unlock(ctrlr); 4521 4522 if (rc < 0) { 4523 num_completions = rc; 4524 } else { 4525 num_completions += rc; 4526 } 4527 4528 return num_completions; 4529 } 4530 4531 const struct spdk_nvme_ctrlr_data * 4532 spdk_nvme_ctrlr_get_data(struct spdk_nvme_ctrlr *ctrlr) 4533 { 4534 return &ctrlr->cdata; 4535 } 4536 4537 union spdk_nvme_csts_register spdk_nvme_ctrlr_get_regs_csts(struct spdk_nvme_ctrlr *ctrlr) 4538 { 4539 union spdk_nvme_csts_register csts; 4540 4541 if (nvme_ctrlr_get_csts(ctrlr, &csts)) { 4542 csts.raw = SPDK_NVME_INVALID_REGISTER_VALUE; 4543 } 4544 return csts; 4545 } 4546 4547 union spdk_nvme_cc_register spdk_nvme_ctrlr_get_regs_cc(struct spdk_nvme_ctrlr *ctrlr) 4548 { 4549 union spdk_nvme_cc_register cc; 4550 4551 if (nvme_ctrlr_get_cc(ctrlr, &cc)) { 4552 cc.raw = SPDK_NVME_INVALID_REGISTER_VALUE; 4553 } 4554 return cc; 4555 } 4556 4557 union spdk_nvme_cap_register spdk_nvme_ctrlr_get_regs_cap(struct spdk_nvme_ctrlr *ctrlr) 4558 { 4559 return ctrlr->cap; 4560 } 4561 4562 union spdk_nvme_vs_register spdk_nvme_ctrlr_get_regs_vs(struct spdk_nvme_ctrlr *ctrlr) 4563 { 4564 return ctrlr->vs; 4565 } 4566 4567 union spdk_nvme_cmbsz_register spdk_nvme_ctrlr_get_regs_cmbsz(struct spdk_nvme_ctrlr *ctrlr) 4568 { 4569 union spdk_nvme_cmbsz_register cmbsz; 4570 4571 if (nvme_ctrlr_get_cmbsz(ctrlr, &cmbsz)) { 4572 cmbsz.raw = 0; 4573 } 4574 4575 return cmbsz; 4576 } 4577 4578 union spdk_nvme_pmrcap_register spdk_nvme_ctrlr_get_regs_pmrcap(struct spdk_nvme_ctrlr *ctrlr) 4579 { 4580 union spdk_nvme_pmrcap_register pmrcap; 4581 4582 if (nvme_ctrlr_get_pmrcap(ctrlr, &pmrcap)) { 4583 pmrcap.raw = 0; 4584 } 4585 4586 return pmrcap; 4587 } 4588 4589 union spdk_nvme_bpinfo_register spdk_nvme_ctrlr_get_regs_bpinfo(struct spdk_nvme_ctrlr *ctrlr) 4590 { 4591 union spdk_nvme_bpinfo_register bpinfo; 4592 4593 if (nvme_ctrlr_get_bpinfo(ctrlr, &bpinfo)) { 4594 bpinfo.raw = 0; 4595 } 4596 4597 return bpinfo; 4598 } 4599 4600 uint64_t 4601 spdk_nvme_ctrlr_get_pmrsz(struct spdk_nvme_ctrlr *ctrlr) 4602 { 4603 return ctrlr->pmr_size; 4604 } 4605 4606 uint32_t 4607 spdk_nvme_ctrlr_get_num_ns(struct spdk_nvme_ctrlr *ctrlr) 4608 { 4609 return ctrlr->cdata.nn; 4610 } 4611 4612 bool 4613 spdk_nvme_ctrlr_is_active_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid) 4614 { 4615 struct spdk_nvme_ns tmp, *ns; 4616 4617 tmp.id = nsid; 4618 ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp); 4619 4620 if (ns != NULL) { 4621 return ns->active; 4622 } 4623 4624 return false; 4625 } 4626 4627 uint32_t 4628 spdk_nvme_ctrlr_get_first_active_ns(struct spdk_nvme_ctrlr *ctrlr) 4629 { 4630 struct spdk_nvme_ns *ns; 4631 4632 ns = RB_MIN(nvme_ns_tree, &ctrlr->ns); 4633 if (ns == NULL) { 4634 return 0; 4635 } 4636 4637 while (ns != NULL) { 4638 if (ns->active) { 4639 return ns->id; 4640 } 4641 4642 ns = RB_NEXT(nvme_ns_tree, &ctrlr->ns, ns); 4643 } 4644 4645 return 0; 4646 } 4647 4648 uint32_t 4649 spdk_nvme_ctrlr_get_next_active_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t prev_nsid) 4650 { 4651 struct spdk_nvme_ns tmp, *ns; 4652 4653 tmp.id = prev_nsid; 4654 ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp); 4655 if (ns == NULL) { 4656 return 0; 4657 } 4658 4659 ns = RB_NEXT(nvme_ns_tree, &ctrlr->ns, ns); 4660 while (ns != NULL) { 4661 if (ns->active) { 4662 return ns->id; 4663 } 4664 4665 ns = RB_NEXT(nvme_ns_tree, &ctrlr->ns, ns); 4666 } 4667 4668 return 0; 4669 } 4670 4671 struct spdk_nvme_ns * 4672 spdk_nvme_ctrlr_get_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid) 4673 { 4674 struct spdk_nvme_ns tmp; 4675 struct spdk_nvme_ns *ns; 4676 4677 if (nsid < 1 || nsid > ctrlr->cdata.nn) { 4678 return NULL; 4679 } 4680 4681 nvme_ctrlr_lock(ctrlr); 4682 4683 tmp.id = nsid; 4684 ns = RB_FIND(nvme_ns_tree, &ctrlr->ns, &tmp); 4685 4686 if (ns == NULL) { 4687 ns = spdk_zmalloc(sizeof(struct spdk_nvme_ns), 64, NULL, SPDK_ENV_SOCKET_ID_ANY, SPDK_MALLOC_SHARE); 4688 if (ns == NULL) { 4689 nvme_ctrlr_unlock(ctrlr); 4690 return NULL; 4691 } 4692 4693 NVME_CTRLR_DEBUGLOG(ctrlr, "Namespace %u was added\n", nsid); 4694 ns->id = nsid; 4695 RB_INSERT(nvme_ns_tree, &ctrlr->ns, ns); 4696 } 4697 4698 nvme_ctrlr_unlock(ctrlr); 4699 4700 return ns; 4701 } 4702 4703 struct spdk_pci_device * 4704 spdk_nvme_ctrlr_get_pci_device(struct spdk_nvme_ctrlr *ctrlr) 4705 { 4706 if (ctrlr == NULL) { 4707 return NULL; 4708 } 4709 4710 if (ctrlr->trid.trtype != SPDK_NVME_TRANSPORT_PCIE) { 4711 return NULL; 4712 } 4713 4714 return nvme_ctrlr_proc_get_devhandle(ctrlr); 4715 } 4716 4717 uint32_t 4718 spdk_nvme_ctrlr_get_max_xfer_size(const struct spdk_nvme_ctrlr *ctrlr) 4719 { 4720 return ctrlr->max_xfer_size; 4721 } 4722 4723 uint16_t 4724 spdk_nvme_ctrlr_get_max_sges(const struct spdk_nvme_ctrlr *ctrlr) 4725 { 4726 if (ctrlr->flags & SPDK_NVME_CTRLR_SGL_SUPPORTED) { 4727 return ctrlr->max_sges; 4728 } else { 4729 return UINT16_MAX; 4730 } 4731 } 4732 4733 void 4734 spdk_nvme_ctrlr_register_aer_callback(struct spdk_nvme_ctrlr *ctrlr, 4735 spdk_nvme_aer_cb aer_cb_fn, 4736 void *aer_cb_arg) 4737 { 4738 struct spdk_nvme_ctrlr_process *active_proc; 4739 4740 nvme_ctrlr_lock(ctrlr); 4741 4742 active_proc = nvme_ctrlr_get_current_process(ctrlr); 4743 if (active_proc) { 4744 active_proc->aer_cb_fn = aer_cb_fn; 4745 active_proc->aer_cb_arg = aer_cb_arg; 4746 } 4747 4748 nvme_ctrlr_unlock(ctrlr); 4749 } 4750 4751 void 4752 spdk_nvme_ctrlr_disable_read_changed_ns_list_log_page(struct spdk_nvme_ctrlr *ctrlr) 4753 { 4754 ctrlr->opts.disable_read_changed_ns_list_log_page = true; 4755 } 4756 4757 void 4758 spdk_nvme_ctrlr_register_timeout_callback(struct spdk_nvme_ctrlr *ctrlr, 4759 uint64_t timeout_io_us, uint64_t timeout_admin_us, 4760 spdk_nvme_timeout_cb cb_fn, void *cb_arg) 4761 { 4762 struct spdk_nvme_ctrlr_process *active_proc; 4763 4764 nvme_ctrlr_lock(ctrlr); 4765 4766 active_proc = nvme_ctrlr_get_current_process(ctrlr); 4767 if (active_proc) { 4768 active_proc->timeout_io_ticks = timeout_io_us * spdk_get_ticks_hz() / 1000000ULL; 4769 active_proc->timeout_admin_ticks = timeout_admin_us * spdk_get_ticks_hz() / 1000000ULL; 4770 active_proc->timeout_cb_fn = cb_fn; 4771 active_proc->timeout_cb_arg = cb_arg; 4772 } 4773 4774 ctrlr->timeout_enabled = true; 4775 4776 nvme_ctrlr_unlock(ctrlr); 4777 } 4778 4779 bool 4780 spdk_nvme_ctrlr_is_log_page_supported(struct spdk_nvme_ctrlr *ctrlr, uint8_t log_page) 4781 { 4782 /* No bounds check necessary, since log_page is uint8_t and log_page_supported has 256 entries */ 4783 SPDK_STATIC_ASSERT(sizeof(ctrlr->log_page_supported) == 256, "log_page_supported size mismatch"); 4784 return ctrlr->log_page_supported[log_page]; 4785 } 4786 4787 bool 4788 spdk_nvme_ctrlr_is_feature_supported(struct spdk_nvme_ctrlr *ctrlr, uint8_t feature_code) 4789 { 4790 /* No bounds check necessary, since feature_code is uint8_t and feature_supported has 256 entries */ 4791 SPDK_STATIC_ASSERT(sizeof(ctrlr->feature_supported) == 256, "feature_supported size mismatch"); 4792 return ctrlr->feature_supported[feature_code]; 4793 } 4794 4795 int 4796 spdk_nvme_ctrlr_attach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, 4797 struct spdk_nvme_ctrlr_list *payload) 4798 { 4799 struct nvme_completion_poll_status *status; 4800 struct spdk_nvme_ns *ns; 4801 int res; 4802 4803 if (nsid == 0) { 4804 return -EINVAL; 4805 } 4806 4807 status = calloc(1, sizeof(*status)); 4808 if (!status) { 4809 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n"); 4810 return -ENOMEM; 4811 } 4812 4813 res = nvme_ctrlr_cmd_attach_ns(ctrlr, nsid, payload, 4814 nvme_completion_poll_cb, status); 4815 if (res) { 4816 free(status); 4817 return res; 4818 } 4819 if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) { 4820 NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_attach_ns failed!\n"); 4821 if (!status->timed_out) { 4822 free(status); 4823 } 4824 return -ENXIO; 4825 } 4826 free(status); 4827 4828 res = nvme_ctrlr_identify_active_ns(ctrlr); 4829 if (res) { 4830 return res; 4831 } 4832 4833 ns = spdk_nvme_ctrlr_get_ns(ctrlr, nsid); 4834 if (ns == NULL) { 4835 NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_get_ns failed!\n"); 4836 return -ENXIO; 4837 } 4838 4839 return nvme_ns_construct(ns, nsid, ctrlr); 4840 } 4841 4842 int 4843 spdk_nvme_ctrlr_detach_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, 4844 struct spdk_nvme_ctrlr_list *payload) 4845 { 4846 struct nvme_completion_poll_status *status; 4847 int res; 4848 4849 if (nsid == 0) { 4850 return -EINVAL; 4851 } 4852 4853 status = calloc(1, sizeof(*status)); 4854 if (!status) { 4855 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n"); 4856 return -ENOMEM; 4857 } 4858 4859 res = nvme_ctrlr_cmd_detach_ns(ctrlr, nsid, payload, 4860 nvme_completion_poll_cb, status); 4861 if (res) { 4862 free(status); 4863 return res; 4864 } 4865 if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) { 4866 NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_detach_ns failed!\n"); 4867 if (!status->timed_out) { 4868 free(status); 4869 } 4870 return -ENXIO; 4871 } 4872 free(status); 4873 4874 return nvme_ctrlr_identify_active_ns(ctrlr); 4875 } 4876 4877 uint32_t 4878 spdk_nvme_ctrlr_create_ns(struct spdk_nvme_ctrlr *ctrlr, struct spdk_nvme_ns_data *payload) 4879 { 4880 struct nvme_completion_poll_status *status; 4881 int res; 4882 uint32_t nsid; 4883 4884 status = calloc(1, sizeof(*status)); 4885 if (!status) { 4886 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n"); 4887 return 0; 4888 } 4889 4890 res = nvme_ctrlr_cmd_create_ns(ctrlr, payload, nvme_completion_poll_cb, status); 4891 if (res) { 4892 free(status); 4893 return 0; 4894 } 4895 if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) { 4896 NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_create_ns failed!\n"); 4897 if (!status->timed_out) { 4898 free(status); 4899 } 4900 return 0; 4901 } 4902 4903 nsid = status->cpl.cdw0; 4904 free(status); 4905 4906 assert(nsid > 0); 4907 4908 /* Return the namespace ID that was created */ 4909 return nsid; 4910 } 4911 4912 int 4913 spdk_nvme_ctrlr_delete_ns(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid) 4914 { 4915 struct nvme_completion_poll_status *status; 4916 int res; 4917 4918 if (nsid == 0) { 4919 return -EINVAL; 4920 } 4921 4922 status = calloc(1, sizeof(*status)); 4923 if (!status) { 4924 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n"); 4925 return -ENOMEM; 4926 } 4927 4928 res = nvme_ctrlr_cmd_delete_ns(ctrlr, nsid, nvme_completion_poll_cb, status); 4929 if (res) { 4930 free(status); 4931 return res; 4932 } 4933 if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) { 4934 NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_delete_ns failed!\n"); 4935 if (!status->timed_out) { 4936 free(status); 4937 } 4938 return -ENXIO; 4939 } 4940 free(status); 4941 4942 return nvme_ctrlr_identify_active_ns(ctrlr); 4943 } 4944 4945 int 4946 spdk_nvme_ctrlr_format(struct spdk_nvme_ctrlr *ctrlr, uint32_t nsid, 4947 struct spdk_nvme_format *format) 4948 { 4949 struct nvme_completion_poll_status *status; 4950 int res; 4951 4952 status = calloc(1, sizeof(*status)); 4953 if (!status) { 4954 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n"); 4955 return -ENOMEM; 4956 } 4957 4958 res = nvme_ctrlr_cmd_format(ctrlr, nsid, format, nvme_completion_poll_cb, 4959 status); 4960 if (res) { 4961 free(status); 4962 return res; 4963 } 4964 if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) { 4965 NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_format failed!\n"); 4966 if (!status->timed_out) { 4967 free(status); 4968 } 4969 return -ENXIO; 4970 } 4971 free(status); 4972 4973 return spdk_nvme_ctrlr_reset(ctrlr); 4974 } 4975 4976 int 4977 spdk_nvme_ctrlr_update_firmware(struct spdk_nvme_ctrlr *ctrlr, void *payload, uint32_t size, 4978 int slot, enum spdk_nvme_fw_commit_action commit_action, struct spdk_nvme_status *completion_status) 4979 { 4980 struct spdk_nvme_fw_commit fw_commit; 4981 struct nvme_completion_poll_status *status; 4982 int res; 4983 unsigned int size_remaining; 4984 unsigned int offset; 4985 unsigned int transfer; 4986 uint8_t *p; 4987 4988 if (!completion_status) { 4989 return -EINVAL; 4990 } 4991 memset(completion_status, 0, sizeof(struct spdk_nvme_status)); 4992 if (size % 4) { 4993 NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_update_firmware invalid size!\n"); 4994 return -1; 4995 } 4996 4997 /* Current support only for SPDK_NVME_FW_COMMIT_REPLACE_IMG 4998 * and SPDK_NVME_FW_COMMIT_REPLACE_AND_ENABLE_IMG 4999 */ 5000 if ((commit_action != SPDK_NVME_FW_COMMIT_REPLACE_IMG) && 5001 (commit_action != SPDK_NVME_FW_COMMIT_REPLACE_AND_ENABLE_IMG)) { 5002 NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_update_firmware invalid command!\n"); 5003 return -1; 5004 } 5005 5006 status = calloc(1, sizeof(*status)); 5007 if (!status) { 5008 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n"); 5009 return -ENOMEM; 5010 } 5011 5012 /* Firmware download */ 5013 size_remaining = size; 5014 offset = 0; 5015 p = payload; 5016 5017 while (size_remaining > 0) { 5018 transfer = spdk_min(size_remaining, ctrlr->min_page_size); 5019 5020 memset(status, 0, sizeof(*status)); 5021 res = nvme_ctrlr_cmd_fw_image_download(ctrlr, transfer, offset, p, 5022 nvme_completion_poll_cb, 5023 status); 5024 if (res) { 5025 free(status); 5026 return res; 5027 } 5028 5029 if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) { 5030 NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_fw_image_download failed!\n"); 5031 if (!status->timed_out) { 5032 free(status); 5033 } 5034 return -ENXIO; 5035 } 5036 p += transfer; 5037 offset += transfer; 5038 size_remaining -= transfer; 5039 } 5040 5041 /* Firmware commit */ 5042 memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit)); 5043 fw_commit.fs = slot; 5044 fw_commit.ca = commit_action; 5045 5046 memset(status, 0, sizeof(*status)); 5047 res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit, nvme_completion_poll_cb, 5048 status); 5049 if (res) { 5050 free(status); 5051 return res; 5052 } 5053 5054 res = nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock); 5055 5056 memcpy(completion_status, &status->cpl.status, sizeof(struct spdk_nvme_status)); 5057 5058 if (!status->timed_out) { 5059 free(status); 5060 } 5061 5062 if (res) { 5063 if (completion_status->sct != SPDK_NVME_SCT_COMMAND_SPECIFIC || 5064 completion_status->sc != SPDK_NVME_SC_FIRMWARE_REQ_NVM_RESET) { 5065 if (completion_status->sct == SPDK_NVME_SCT_COMMAND_SPECIFIC && 5066 completion_status->sc == SPDK_NVME_SC_FIRMWARE_REQ_CONVENTIONAL_RESET) { 5067 NVME_CTRLR_NOTICELOG(ctrlr, 5068 "firmware activation requires conventional reset to be performed. !\n"); 5069 } else { 5070 NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_commit failed!\n"); 5071 } 5072 return -ENXIO; 5073 } 5074 } 5075 5076 return spdk_nvme_ctrlr_reset(ctrlr); 5077 } 5078 5079 int 5080 spdk_nvme_ctrlr_reserve_cmb(struct spdk_nvme_ctrlr *ctrlr) 5081 { 5082 int rc, size; 5083 union spdk_nvme_cmbsz_register cmbsz; 5084 5085 cmbsz = spdk_nvme_ctrlr_get_regs_cmbsz(ctrlr); 5086 5087 if (cmbsz.bits.rds == 0 || cmbsz.bits.wds == 0) { 5088 return -ENOTSUP; 5089 } 5090 5091 size = cmbsz.bits.sz * (0x1000 << (cmbsz.bits.szu * 4)); 5092 5093 nvme_ctrlr_lock(ctrlr); 5094 rc = nvme_transport_ctrlr_reserve_cmb(ctrlr); 5095 nvme_ctrlr_unlock(ctrlr); 5096 5097 if (rc < 0) { 5098 return rc; 5099 } 5100 5101 return size; 5102 } 5103 5104 void * 5105 spdk_nvme_ctrlr_map_cmb(struct spdk_nvme_ctrlr *ctrlr, size_t *size) 5106 { 5107 void *buf; 5108 5109 nvme_ctrlr_lock(ctrlr); 5110 buf = nvme_transport_ctrlr_map_cmb(ctrlr, size); 5111 nvme_ctrlr_unlock(ctrlr); 5112 5113 return buf; 5114 } 5115 5116 void 5117 spdk_nvme_ctrlr_unmap_cmb(struct spdk_nvme_ctrlr *ctrlr) 5118 { 5119 nvme_ctrlr_lock(ctrlr); 5120 nvme_transport_ctrlr_unmap_cmb(ctrlr); 5121 nvme_ctrlr_unlock(ctrlr); 5122 } 5123 5124 int 5125 spdk_nvme_ctrlr_enable_pmr(struct spdk_nvme_ctrlr *ctrlr) 5126 { 5127 int rc; 5128 5129 nvme_ctrlr_lock(ctrlr); 5130 rc = nvme_transport_ctrlr_enable_pmr(ctrlr); 5131 nvme_ctrlr_unlock(ctrlr); 5132 5133 return rc; 5134 } 5135 5136 int 5137 spdk_nvme_ctrlr_disable_pmr(struct spdk_nvme_ctrlr *ctrlr) 5138 { 5139 int rc; 5140 5141 nvme_ctrlr_lock(ctrlr); 5142 rc = nvme_transport_ctrlr_disable_pmr(ctrlr); 5143 nvme_ctrlr_unlock(ctrlr); 5144 5145 return rc; 5146 } 5147 5148 void * 5149 spdk_nvme_ctrlr_map_pmr(struct spdk_nvme_ctrlr *ctrlr, size_t *size) 5150 { 5151 void *buf; 5152 5153 nvme_ctrlr_lock(ctrlr); 5154 buf = nvme_transport_ctrlr_map_pmr(ctrlr, size); 5155 nvme_ctrlr_unlock(ctrlr); 5156 5157 return buf; 5158 } 5159 5160 int 5161 spdk_nvme_ctrlr_unmap_pmr(struct spdk_nvme_ctrlr *ctrlr) 5162 { 5163 int rc; 5164 5165 nvme_ctrlr_lock(ctrlr); 5166 rc = nvme_transport_ctrlr_unmap_pmr(ctrlr); 5167 nvme_ctrlr_unlock(ctrlr); 5168 5169 return rc; 5170 } 5171 5172 int 5173 spdk_nvme_ctrlr_read_boot_partition_start(struct spdk_nvme_ctrlr *ctrlr, void *payload, 5174 uint32_t bprsz, uint32_t bprof, uint32_t bpid) 5175 { 5176 union spdk_nvme_bprsel_register bprsel; 5177 union spdk_nvme_bpinfo_register bpinfo; 5178 uint64_t bpmbl, bpmb_size; 5179 5180 if (ctrlr->cap.bits.bps == 0) { 5181 return -ENOTSUP; 5182 } 5183 5184 if (nvme_ctrlr_get_bpinfo(ctrlr, &bpinfo)) { 5185 NVME_CTRLR_ERRLOG(ctrlr, "get bpinfo failed\n"); 5186 return -EIO; 5187 } 5188 5189 if (bpinfo.bits.brs == SPDK_NVME_BRS_READ_IN_PROGRESS) { 5190 NVME_CTRLR_ERRLOG(ctrlr, "Boot Partition read already initiated\n"); 5191 return -EALREADY; 5192 } 5193 5194 nvme_ctrlr_lock(ctrlr); 5195 5196 bpmb_size = bprsz * 4096; 5197 bpmbl = spdk_vtophys(payload, &bpmb_size); 5198 if (bpmbl == SPDK_VTOPHYS_ERROR) { 5199 NVME_CTRLR_ERRLOG(ctrlr, "spdk_vtophys of bpmbl failed\n"); 5200 nvme_ctrlr_unlock(ctrlr); 5201 return -EFAULT; 5202 } 5203 5204 if (bpmb_size != bprsz * 4096) { 5205 NVME_CTRLR_ERRLOG(ctrlr, "Boot Partition buffer is not physically contiguous\n"); 5206 nvme_ctrlr_unlock(ctrlr); 5207 return -EFAULT; 5208 } 5209 5210 if (nvme_ctrlr_set_bpmbl(ctrlr, bpmbl)) { 5211 NVME_CTRLR_ERRLOG(ctrlr, "set_bpmbl() failed\n"); 5212 nvme_ctrlr_unlock(ctrlr); 5213 return -EIO; 5214 } 5215 5216 bprsel.bits.bpid = bpid; 5217 bprsel.bits.bprof = bprof; 5218 bprsel.bits.bprsz = bprsz; 5219 5220 if (nvme_ctrlr_set_bprsel(ctrlr, &bprsel)) { 5221 NVME_CTRLR_ERRLOG(ctrlr, "set_bprsel() failed\n"); 5222 nvme_ctrlr_unlock(ctrlr); 5223 return -EIO; 5224 } 5225 5226 nvme_ctrlr_unlock(ctrlr); 5227 return 0; 5228 } 5229 5230 int 5231 spdk_nvme_ctrlr_read_boot_partition_poll(struct spdk_nvme_ctrlr *ctrlr) 5232 { 5233 int rc = 0; 5234 union spdk_nvme_bpinfo_register bpinfo; 5235 5236 if (nvme_ctrlr_get_bpinfo(ctrlr, &bpinfo)) { 5237 NVME_CTRLR_ERRLOG(ctrlr, "get bpinfo failed\n"); 5238 return -EIO; 5239 } 5240 5241 switch (bpinfo.bits.brs) { 5242 case SPDK_NVME_BRS_NO_READ: 5243 NVME_CTRLR_ERRLOG(ctrlr, "Boot Partition read not initiated\n"); 5244 rc = -EINVAL; 5245 break; 5246 case SPDK_NVME_BRS_READ_IN_PROGRESS: 5247 NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition read in progress\n"); 5248 rc = -EAGAIN; 5249 break; 5250 case SPDK_NVME_BRS_READ_ERROR: 5251 NVME_CTRLR_ERRLOG(ctrlr, "Error completing Boot Partition read\n"); 5252 rc = -EIO; 5253 break; 5254 case SPDK_NVME_BRS_READ_SUCCESS: 5255 NVME_CTRLR_INFOLOG(ctrlr, "Boot Partition read completed successfully\n"); 5256 break; 5257 default: 5258 NVME_CTRLR_ERRLOG(ctrlr, "Invalid Boot Partition read status\n"); 5259 rc = -EINVAL; 5260 } 5261 5262 return rc; 5263 } 5264 5265 static void 5266 nvme_write_boot_partition_cb(void *arg, const struct spdk_nvme_cpl *cpl) 5267 { 5268 int res; 5269 struct spdk_nvme_ctrlr *ctrlr = arg; 5270 struct spdk_nvme_fw_commit fw_commit; 5271 struct spdk_nvme_cpl err_cpl = 5272 {.status = {.sct = SPDK_NVME_SCT_GENERIC, .sc = SPDK_NVME_SC_INTERNAL_DEVICE_ERROR }}; 5273 5274 if (spdk_nvme_cpl_is_error(cpl)) { 5275 NVME_CTRLR_ERRLOG(ctrlr, "Write Boot Partition failed\n"); 5276 ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, cpl); 5277 return; 5278 } 5279 5280 if (ctrlr->bp_ws == SPDK_NVME_BP_WS_DOWNLOADING) { 5281 NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Downloading at Offset %d Success\n", ctrlr->fw_offset); 5282 ctrlr->fw_payload = (uint8_t *)ctrlr->fw_payload + ctrlr->fw_transfer_size; 5283 ctrlr->fw_offset += ctrlr->fw_transfer_size; 5284 ctrlr->fw_size_remaining -= ctrlr->fw_transfer_size; 5285 ctrlr->fw_transfer_size = spdk_min(ctrlr->fw_size_remaining, ctrlr->min_page_size); 5286 res = nvme_ctrlr_cmd_fw_image_download(ctrlr, ctrlr->fw_transfer_size, ctrlr->fw_offset, 5287 ctrlr->fw_payload, nvme_write_boot_partition_cb, ctrlr); 5288 if (res) { 5289 NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_image_download failed!\n"); 5290 ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl); 5291 return; 5292 } 5293 5294 if (ctrlr->fw_transfer_size < ctrlr->min_page_size) { 5295 ctrlr->bp_ws = SPDK_NVME_BP_WS_DOWNLOADED; 5296 } 5297 } else if (ctrlr->bp_ws == SPDK_NVME_BP_WS_DOWNLOADED) { 5298 NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Download Success\n"); 5299 memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit)); 5300 fw_commit.bpid = ctrlr->bpid; 5301 fw_commit.ca = SPDK_NVME_FW_COMMIT_REPLACE_BOOT_PARTITION; 5302 res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit, 5303 nvme_write_boot_partition_cb, ctrlr); 5304 if (res) { 5305 NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_commit failed!\n"); 5306 NVME_CTRLR_ERRLOG(ctrlr, "commit action: %d\n", fw_commit.ca); 5307 ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl); 5308 return; 5309 } 5310 5311 ctrlr->bp_ws = SPDK_NVME_BP_WS_REPLACE; 5312 } else if (ctrlr->bp_ws == SPDK_NVME_BP_WS_REPLACE) { 5313 NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Replacement Success\n"); 5314 memset(&fw_commit, 0, sizeof(struct spdk_nvme_fw_commit)); 5315 fw_commit.bpid = ctrlr->bpid; 5316 fw_commit.ca = SPDK_NVME_FW_COMMIT_ACTIVATE_BOOT_PARTITION; 5317 res = nvme_ctrlr_cmd_fw_commit(ctrlr, &fw_commit, 5318 nvme_write_boot_partition_cb, ctrlr); 5319 if (res) { 5320 NVME_CTRLR_ERRLOG(ctrlr, "nvme_ctrlr_cmd_fw_commit failed!\n"); 5321 NVME_CTRLR_ERRLOG(ctrlr, "commit action: %d\n", fw_commit.ca); 5322 ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl); 5323 return; 5324 } 5325 5326 ctrlr->bp_ws = SPDK_NVME_BP_WS_ACTIVATE; 5327 } else if (ctrlr->bp_ws == SPDK_NVME_BP_WS_ACTIVATE) { 5328 NVME_CTRLR_DEBUGLOG(ctrlr, "Boot Partition Activation Success\n"); 5329 ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, cpl); 5330 } else { 5331 NVME_CTRLR_ERRLOG(ctrlr, "Invalid Boot Partition write state\n"); 5332 ctrlr->bp_write_cb_fn(ctrlr->bp_write_cb_arg, &err_cpl); 5333 return; 5334 } 5335 } 5336 5337 int 5338 spdk_nvme_ctrlr_write_boot_partition(struct spdk_nvme_ctrlr *ctrlr, 5339 void *payload, uint32_t size, uint32_t bpid, 5340 spdk_nvme_cmd_cb cb_fn, void *cb_arg) 5341 { 5342 int res; 5343 5344 if (ctrlr->cap.bits.bps == 0) { 5345 return -ENOTSUP; 5346 } 5347 5348 ctrlr->bp_ws = SPDK_NVME_BP_WS_DOWNLOADING; 5349 ctrlr->bpid = bpid; 5350 ctrlr->bp_write_cb_fn = cb_fn; 5351 ctrlr->bp_write_cb_arg = cb_arg; 5352 ctrlr->fw_offset = 0; 5353 ctrlr->fw_size_remaining = size; 5354 ctrlr->fw_payload = payload; 5355 ctrlr->fw_transfer_size = spdk_min(ctrlr->fw_size_remaining, ctrlr->min_page_size); 5356 5357 res = nvme_ctrlr_cmd_fw_image_download(ctrlr, ctrlr->fw_transfer_size, ctrlr->fw_offset, 5358 ctrlr->fw_payload, nvme_write_boot_partition_cb, ctrlr); 5359 5360 return res; 5361 } 5362 5363 bool 5364 spdk_nvme_ctrlr_is_discovery(struct spdk_nvme_ctrlr *ctrlr) 5365 { 5366 assert(ctrlr); 5367 5368 return !strncmp(ctrlr->trid.subnqn, SPDK_NVMF_DISCOVERY_NQN, 5369 strlen(SPDK_NVMF_DISCOVERY_NQN)); 5370 } 5371 5372 bool 5373 spdk_nvme_ctrlr_is_fabrics(struct spdk_nvme_ctrlr *ctrlr) 5374 { 5375 assert(ctrlr); 5376 5377 return spdk_nvme_trtype_is_fabrics(ctrlr->trid.trtype); 5378 } 5379 5380 int 5381 spdk_nvme_ctrlr_security_receive(struct spdk_nvme_ctrlr *ctrlr, uint8_t secp, 5382 uint16_t spsp, uint8_t nssf, void *payload, size_t size) 5383 { 5384 struct nvme_completion_poll_status *status; 5385 int res; 5386 5387 status = calloc(1, sizeof(*status)); 5388 if (!status) { 5389 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n"); 5390 return -ENOMEM; 5391 } 5392 5393 res = spdk_nvme_ctrlr_cmd_security_receive(ctrlr, secp, spsp, nssf, payload, size, 5394 nvme_completion_poll_cb, status); 5395 if (res) { 5396 free(status); 5397 return res; 5398 } 5399 if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) { 5400 NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_cmd_security_receive failed!\n"); 5401 if (!status->timed_out) { 5402 free(status); 5403 } 5404 return -ENXIO; 5405 } 5406 free(status); 5407 5408 return 0; 5409 } 5410 5411 int 5412 spdk_nvme_ctrlr_security_send(struct spdk_nvme_ctrlr *ctrlr, uint8_t secp, 5413 uint16_t spsp, uint8_t nssf, void *payload, size_t size) 5414 { 5415 struct nvme_completion_poll_status *status; 5416 int res; 5417 5418 status = calloc(1, sizeof(*status)); 5419 if (!status) { 5420 NVME_CTRLR_ERRLOG(ctrlr, "Failed to allocate status tracker\n"); 5421 return -ENOMEM; 5422 } 5423 5424 res = spdk_nvme_ctrlr_cmd_security_send(ctrlr, secp, spsp, nssf, payload, size, 5425 nvme_completion_poll_cb, 5426 status); 5427 if (res) { 5428 free(status); 5429 return res; 5430 } 5431 if (nvme_wait_for_completion_robust_lock(ctrlr->adminq, status, &ctrlr->ctrlr_lock)) { 5432 NVME_CTRLR_ERRLOG(ctrlr, "spdk_nvme_ctrlr_cmd_security_send failed!\n"); 5433 if (!status->timed_out) { 5434 free(status); 5435 } 5436 return -ENXIO; 5437 } 5438 5439 free(status); 5440 5441 return 0; 5442 } 5443 5444 uint64_t 5445 spdk_nvme_ctrlr_get_flags(struct spdk_nvme_ctrlr *ctrlr) 5446 { 5447 return ctrlr->flags; 5448 } 5449 5450 const struct spdk_nvme_transport_id * 5451 spdk_nvme_ctrlr_get_transport_id(struct spdk_nvme_ctrlr *ctrlr) 5452 { 5453 return &ctrlr->trid; 5454 } 5455 5456 int32_t 5457 spdk_nvme_ctrlr_alloc_qid(struct spdk_nvme_ctrlr *ctrlr) 5458 { 5459 uint32_t qid; 5460 5461 assert(ctrlr->free_io_qids); 5462 nvme_ctrlr_lock(ctrlr); 5463 qid = spdk_bit_array_find_first_set(ctrlr->free_io_qids, 1); 5464 if (qid > ctrlr->opts.num_io_queues) { 5465 NVME_CTRLR_ERRLOG(ctrlr, "No free I/O queue IDs\n"); 5466 nvme_ctrlr_unlock(ctrlr); 5467 return -1; 5468 } 5469 5470 spdk_bit_array_clear(ctrlr->free_io_qids, qid); 5471 nvme_ctrlr_unlock(ctrlr); 5472 return qid; 5473 } 5474 5475 void 5476 spdk_nvme_ctrlr_free_qid(struct spdk_nvme_ctrlr *ctrlr, uint16_t qid) 5477 { 5478 assert(qid <= ctrlr->opts.num_io_queues); 5479 5480 nvme_ctrlr_lock(ctrlr); 5481 5482 if (spdk_likely(ctrlr->free_io_qids)) { 5483 spdk_bit_array_set(ctrlr->free_io_qids, qid); 5484 } 5485 5486 nvme_ctrlr_unlock(ctrlr); 5487 } 5488 5489 int 5490 spdk_nvme_ctrlr_get_memory_domains(const struct spdk_nvme_ctrlr *ctrlr, 5491 struct spdk_memory_domain **domains, int array_size) 5492 { 5493 return nvme_transport_ctrlr_get_memory_domains(ctrlr, domains, array_size); 5494 } 5495