1 /* 2 * Copyright (c) 2019 Mellanox Technologies, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef MLX5_IFC_H 34 #define MLX5_IFC_H 35 36 #ifdef u8 37 #undef u8 38 #endif 39 40 #define u8 uint8_t 41 42 enum mlx5_cap_mode { 43 HCA_CAP_OPMOD_GET_MAX = 0, 44 HCA_CAP_OPMOD_GET_CUR = 1, 45 }; 46 47 enum { 48 MLX5_QP_PM_ARMED = 0x0, 49 MLX5_QP_PM_REARM = 0x1, 50 MLX5_QP_PM_MIGRATED = 0x3, 51 }; 52 53 enum { 54 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 55 MLX5_CMD_OP_INIT_HCA = 0x102, 56 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 57 MLX5_CMD_OP_ENABLE_HCA = 0x104, 58 MLX5_CMD_OP_QUERY_PAGES = 0x107, 59 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 60 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 61 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 62 MLX5_CMD_OP_SET_ISSI = 0x10b, 63 MLX5_CMD_OP_CREATE_MKEY = 0x200, 64 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 65 MLX5_CMD_OP_CREATE_EQ = 0x301, 66 MLX5_CMD_OP_DESTROY_EQ = 0x302, 67 MLX5_CMD_OP_CREATE_CQ = 0x400, 68 MLX5_CMD_OP_DESTROY_CQ = 0x401, 69 MLX5_CMD_OP_CREATE_QP = 0x500, 70 MLX5_CMD_OP_DESTROY_QP = 0x501, 71 MLX5_CMD_OP_RST2INIT_QP = 0x502, 72 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 73 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 74 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 75 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 76 MLX5_CMD_OP_2ERR_QP = 0x507, 77 MLX5_CMD_OP_2RST_QP = 0x50a, 78 MLX5_CMD_OP_QUERY_QP = 0x50b, 79 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 80 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 81 MLX5_CMD_OP_CREATE_PSV = 0x600, 82 MLX5_CMD_OP_DESTROY_PSV = 0x601, 83 MLX5_CMD_OP_CREATE_SRQ = 0x700, 84 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 85 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 86 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 87 MLX5_CMD_OP_CREATE_DCT = 0x710, 88 MLX5_CMD_OP_DESTROY_DCT = 0x711, 89 MLX5_CMD_OP_QUERY_DCT = 0x713, 90 MLX5_CMD_OP_CREATE_XRQ = 0x717, 91 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 92 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 93 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 94 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 95 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 96 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 97 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 98 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 99 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 100 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 101 MLX5_CMD_OP_ALLOC_PD = 0x800, 102 MLX5_CMD_OP_DEALLOC_PD = 0x801, 103 MLX5_CMD_OP_ALLOC_UAR = 0x802, 104 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 105 MLX5_CMD_OP_ACCESS_REG = 0x805, 106 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 107 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 108 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 109 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 110 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 111 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 112 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 113 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 114 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 115 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 116 MLX5_CMD_OP_QUERY_LAG = 0x842, 117 MLX5_CMD_OP_CREATE_TIR = 0x900, 118 MLX5_CMD_OP_DESTROY_TIR = 0x902, 119 MLX5_CMD_OP_CREATE_SQ = 0x904, 120 MLX5_CMD_OP_MODIFY_SQ = 0x905, 121 MLX5_CMD_OP_DESTROY_SQ = 0x906, 122 MLX5_CMD_OP_CREATE_RQ = 0x908, 123 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 124 MLX5_CMD_OP_CREATE_RMP = 0x90c, 125 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 126 MLX5_CMD_OP_CREATE_TIS = 0x912, 127 MLX5_CMD_OP_MODIFY_TIS = 0x913, 128 MLX5_CMD_OP_DESTROY_TIS = 0x914, 129 MLX5_CMD_OP_QUERY_TIS = 0x915, 130 MLX5_CMD_OP_CREATE_RQT = 0x916, 131 MLX5_CMD_OP_DESTROY_RQT = 0x918, 132 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 133 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 134 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 135 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 136 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 137 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 138 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 139 MLX5_CMD_OP_CREATE_FLOW_COUNTER = 0x939, 140 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 141 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 142 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 143 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 144 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 145 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 146 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 147 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 148 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 149 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 150 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 151 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 152 }; 153 154 enum { 155 MLX5_CMD_STAT_OK = 0x0, 156 MLX5_CMD_STAT_INT_ERR = 0x1, 157 MLX5_CMD_STAT_BAD_OP_ERR = 0x2, 158 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, 159 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, 160 MLX5_CMD_STAT_BAD_RES_ERR = 0x5, 161 MLX5_CMD_STAT_RES_BUSY = 0x6, 162 MLX5_CMD_STAT_LIM_ERR = 0x8, 163 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, 164 MLX5_CMD_STAT_IX_ERR = 0xa, 165 MLX5_CMD_STAT_NO_RES_ERR = 0xf, 166 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, 167 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, 168 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, 169 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, 170 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, 171 }; 172 173 enum { 174 MLX5_PAGES_CANT_GIVE = 0, 175 MLX5_PAGES_GIVE = 1, 176 MLX5_PAGES_TAKE = 2, 177 }; 178 179 enum { 180 MLX5_REG_HOST_ENDIANNESS = 0x7004, 181 }; 182 183 enum { 184 MLX5_CAP_PORT_TYPE_IB = 0x0, 185 MLX5_CAP_PORT_TYPE_ETH = 0x1, 186 }; 187 188 enum mlx5_event { 189 MLX5_EVENT_TYPE_CMD = 0x0a, 190 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 191 }; 192 193 enum { 194 MLX5_EQ_DOORBEL_OFFSET = 0x40, 195 }; 196 197 enum { 198 OPCODE_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1, 199 }; 200 201 enum { 202 MLX5_DB_BLUEFLAME_BUFFER_SIZE = 0x100, 203 }; 204 205 struct mlx5_ifc_atomic_caps_bits { 206 u8 reserved_at_0[0x40]; 207 208 u8 atomic_req_8B_endianness_mode[0x2]; 209 u8 reserved_at_42[0x4]; 210 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 211 212 u8 reserved_at_47[0x19]; 213 214 u8 reserved_at_60[0x20]; 215 216 u8 reserved_at_80[0x10]; 217 u8 atomic_operations[0x10]; 218 219 u8 reserved_at_a0[0x10]; 220 u8 atomic_size_qp[0x10]; 221 222 u8 reserved_at_c0[0x10]; 223 u8 atomic_size_dc[0x10]; 224 225 u8 reserved_at_e0[0x1a0]; 226 227 u8 fetch_add_pci_atomic[0x10]; 228 u8 swap_pci_atomic[0x10]; 229 u8 compare_swap_pci_atomic[0x10]; 230 231 u8 reserved_at_2b0[0x550]; 232 }; 233 234 struct mlx5_ifc_roce_cap_bits { 235 u8 roce_apm[0x1]; 236 u8 rts2rts_primary_eth_prio[0x1]; 237 u8 roce_rx_allow_untagged[0x1]; 238 u8 rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1]; 239 u8 sw_r_roce_src_udp_port[0x01]; 240 u8 reserved[0x01]; 241 u8 fl_rc_qp_when_roce_enabled[0x01]; 242 u8 reserved_at_0[0x19]; 243 244 u8 reserved_at_32[0x60]; 245 246 u8 reserved_at_128[0xc]; 247 u8 l3_type[0x4]; 248 u8 reserved_at_144[0x8]; 249 u8 roce_version[0x8]; 250 251 u8 reserved_at_160[0x10]; 252 u8 r_roce_dest_udp_port[0x10]; 253 254 u8 r_roce_max_src_udp_port[0x10]; 255 u8 r_roce_min_src_udp_port[0x10]; 256 257 u8 reserved_at_224[0x10]; 258 u8 roce_address_table_size[0x10]; 259 260 u8 reserved_at_256[0x700]; 261 }; 262 263 enum { 264 MLX5_MULTI_PATH_FT_MAX_LEVEL = 64, 265 }; 266 267 struct mlx5_ifc_flow_table_context_bits { 268 u8 reformat_en[0x1]; 269 u8 decap_en[0x1]; 270 u8 sw_owner[0x1]; 271 u8 termination_table[0x1]; 272 u8 table_miss_action[0x4]; 273 u8 level[0x8]; 274 u8 reserved_at_10[0x8]; 275 u8 log_size[0x8]; 276 277 u8 reserved_at_20[0x8]; 278 u8 table_miss_id[0x18]; 279 280 u8 reserved_at_40[0x8]; 281 u8 lag_master_next_table_id[0x18]; 282 283 u8 reserved_at_60[0x60]; 284 285 u8 sw_owner_icm_root_1[0x40]; 286 287 u8 sw_owner_icm_root_0[0x40]; 288 }; 289 290 struct mlx5_ifc_create_flow_table_in_bits { 291 u8 opcode[0x10]; 292 u8 uid[0x10]; 293 294 u8 reserved_at_20[0x10]; 295 u8 op_mod[0x10]; 296 297 u8 other_vport[0x1]; 298 u8 reserved_at_41[0xf]; 299 u8 vport_number[0x10]; 300 301 u8 reserved_at_60[0x20]; 302 303 u8 table_type[0x8]; 304 u8 reserved_at_88[0x18]; 305 306 u8 reserved_at_a0[0x20]; 307 308 struct mlx5_ifc_flow_table_context_bits flow_table_context; 309 }; 310 311 struct mlx5_ifc_create_flow_table_out_bits { 312 u8 status[0x8]; 313 u8 icm_address_63_40[0x18]; 314 315 u8 syndrome[0x20]; 316 317 u8 icm_address_39_32[0x8]; 318 u8 table_id[0x18]; 319 320 u8 icm_address_31_0[0x20]; 321 }; 322 323 struct mlx5_ifc_destroy_flow_table_in_bits { 324 u8 opcode[0x10]; 325 u8 reserved_at_10[0x10]; 326 327 u8 reserved_at_20[0x20]; 328 329 u8 other_vport[0x1]; 330 u8 reserved_at_41[0xf]; 331 u8 vport_number[0x10]; 332 333 u8 reserved_at_60[0x20]; 334 335 u8 table_type[0x8]; 336 u8 reserved_at_88[0x18]; 337 338 u8 reserved_at_a0[0x8]; 339 u8 table_id[0x18]; 340 341 u8 reserved_at_c0[0x140]; 342 }; 343 344 struct mlx5_ifc_query_flow_table_in_bits { 345 u8 opcode[0x10]; 346 u8 reserved_at_10[0x10]; 347 348 u8 reserved_at_20[0x10]; 349 u8 op_mod[0x10]; 350 351 u8 reserved_at_40[0x40]; 352 353 u8 table_type[0x8]; 354 u8 reserved_at_88[0x18]; 355 356 u8 reserved_at_a0[0x8]; 357 u8 table_id[0x18]; 358 359 u8 reserved_at_c0[0x140]; 360 }; 361 362 struct mlx5_ifc_query_flow_table_out_bits { 363 u8 status[0x8]; 364 u8 reserved_at_8[0x18]; 365 366 u8 syndrome[0x20]; 367 368 u8 reserved_at_40[0x80]; 369 370 struct mlx5_ifc_flow_table_context_bits flow_table_context; 371 }; 372 373 struct mlx5_ifc_sync_steering_in_bits { 374 u8 opcode[0x10]; 375 u8 uid[0x10]; 376 377 u8 reserved_at_20[0x10]; 378 u8 op_mod[0x10]; 379 380 u8 reserved_at_40[0xc0]; 381 }; 382 383 struct mlx5_ifc_sync_steering_out_bits { 384 u8 status[0x8]; 385 u8 reserved_at_8[0x18]; 386 387 u8 syndrome[0x20]; 388 389 u8 reserved_at_40[0x40]; 390 }; 391 392 struct mlx5_ifc_device_mem_cap_bits { 393 u8 memic[0x1]; 394 u8 reserved_at_1[0x1f]; 395 396 u8 reserved_at_20[0xb]; 397 u8 log_min_memic_alloc_size[0x5]; 398 u8 reserved_at_30[0x8]; 399 u8 log_max_memic_addr_alignment[0x8]; 400 401 u8 memic_bar_start_addr[0x40]; 402 403 u8 memic_bar_size[0x20]; 404 405 u8 max_memic_size[0x20]; 406 407 u8 steering_sw_icm_start_address[0x40]; 408 409 u8 reserved_at_100[0x8]; 410 u8 log_header_modify_sw_icm_size[0x8]; 411 u8 reserved_at_110[0x2]; 412 u8 log_sw_icm_alloc_granularity[0x6]; 413 u8 log_steering_sw_icm_size[0x8]; 414 415 u8 log_indirect_encap_sw_icm_size[0x8]; 416 u8 reserved_at_128[0x10]; 417 u8 log_header_modify_pattern_sw_icm_size[0x8]; 418 419 u8 header_modify_sw_icm_start_address[0x40]; 420 421 u8 reserved_at_180[0x40]; 422 423 u8 header_modify_pattern_sw_icm_start_address[0x40]; 424 425 u8 reserved_at_200[0x40]; 426 427 u8 indirect_encap_sw_icm_start_address[0x40]; 428 429 u8 indirect_encap_icm_base[0x40]; 430 431 u8 reserved_at_2c0[0x540]; 432 }; 433 434 struct mlx5_ifc_flow_table_fields_supported_bits { 435 u8 outer_dmac[0x1]; 436 u8 outer_smac[0x1]; 437 u8 outer_ether_type[0x1]; 438 u8 outer_ip_version[0x1]; 439 u8 outer_first_prio[0x1]; 440 u8 outer_first_cfi[0x1]; 441 u8 outer_first_vid[0x1]; 442 u8 outer_ipv4_ttl[0x1]; 443 u8 outer_second_prio[0x1]; 444 u8 outer_second_cfi[0x1]; 445 u8 outer_second_vid[0x1]; 446 u8 outer_ipv6_flow_label[0x1]; 447 u8 outer_sip[0x1]; 448 u8 outer_dip[0x1]; 449 u8 outer_frag[0x1]; 450 u8 outer_ip_protocol[0x1]; 451 u8 outer_ip_ecn[0x1]; 452 u8 outer_ip_dscp[0x1]; 453 u8 outer_udp_sport[0x1]; 454 u8 outer_udp_dport[0x1]; 455 u8 outer_tcp_sport[0x1]; 456 u8 outer_tcp_dport[0x1]; 457 u8 outer_tcp_flags[0x1]; 458 u8 outer_gre_protocol[0x1]; 459 u8 outer_gre_key[0x1]; 460 u8 outer_vxlan_vni[0x1]; 461 u8 outer_geneve_vni[0x1]; 462 u8 outer_geneve_oam[0x1]; 463 u8 outer_geneve_protocol_type[0x1]; 464 u8 outer_geneve_opt_len[0x1]; 465 u8 source_vhca_port[0x1]; 466 u8 source_eswitch_port[0x1]; 467 468 u8 inner_dmac[0x1]; 469 u8 inner_smac[0x1]; 470 u8 inner_ether_type[0x1]; 471 u8 inner_ip_version[0x1]; 472 u8 inner_first_prio[0x1]; 473 u8 inner_first_cfi[0x1]; 474 u8 inner_first_vid[0x1]; 475 u8 inner_ipv4_ttl[0x1]; 476 u8 inner_second_prio[0x1]; 477 u8 inner_second_cfi[0x1]; 478 u8 inner_second_vid[0x1]; 479 u8 inner_ipv6_flow_label[0x1]; 480 u8 inner_sip[0x1]; 481 u8 inner_dip[0x1]; 482 u8 inner_frag[0x1]; 483 u8 inner_ip_protocol[0x1]; 484 u8 inner_ip_ecn[0x1]; 485 u8 inner_ip_dscp[0x1]; 486 u8 inner_udp_sport[0x1]; 487 u8 inner_udp_dport[0x1]; 488 u8 inner_tcp_sport[0x1]; 489 u8 inner_tcp_dport[0x1]; 490 u8 inner_tcp_flags[0x1]; 491 u8 reserved_at_37[0x7]; 492 u8 metadata_reg_b[0x1]; 493 u8 metadata_reg_a[0x1]; 494 495 u8 geneve_tlv_option_0_data[0x1]; 496 u8 geneve_tlv_option_0_exist[0x1]; 497 u8 reserved_at_42[0x3]; 498 u8 outer_first_mpls_over_udp_ttl[0x1]; 499 u8 outer_first_mpls_over_udp_s_bos[0x1]; 500 u8 outer_first_mpls_over_udp_exp[0x1]; 501 u8 outer_first_mpls_over_udp_label[0x1]; 502 u8 outer_first_mpls_over_gre_ttl[0x1]; 503 u8 outer_first_mpls_over_gre_s_bos[0x1]; 504 u8 outer_first_mpls_over_gre_exp[0x1]; 505 u8 outer_first_mpls_over_gre_label[0x1]; 506 u8 inner_first_mpls_ttl[0x1]; 507 u8 inner_first_mpls_s_bos[0x1]; 508 u8 inner_first_mpls_exp[0x1]; 509 u8 inner_first_mpls_label[0x1]; 510 u8 outer_first_mpls_ttl[0x1]; 511 u8 outer_first_mpls_s_bos[0x1]; 512 u8 outer_first_mpls_exp[0x1]; 513 u8 outer_first_mpls_label[0x1]; 514 u8 outer_emd_tag[0x1]; 515 u8 inner_esp_spi[0x1]; 516 u8 outer_esp_spi[0x1]; 517 u8 inner_ipv6_hop_limit[0x1]; 518 u8 outer_ipv6_hop_limit[0x1]; 519 u8 bth_dst_qp[0x1]; 520 u8 inner_first_svlan[0x1]; 521 u8 inner_second_svlan[0x1]; 522 u8 outer_first_svlan[0x1]; 523 u8 outer_second_svlan[0x1]; 524 u8 source_sqn[0x1]; 525 526 u8 reserved_at_60[0x20]; 527 }; 528 529 struct mlx5_ifc_dr_match_spec_bits { 530 u8 smac_47_16[0x20]; 531 532 u8 smac_15_0[0x10]; 533 u8 ethertype[0x10]; 534 535 u8 dmac_47_16[0x20]; 536 537 u8 dmac_15_0[0x10]; 538 u8 first_prio[0x3]; 539 u8 first_cfi[0x1]; 540 u8 first_vid[0xc]; 541 542 u8 ip_protocol[0x8]; 543 u8 ip_dscp[0x6]; 544 u8 ip_ecn[0x2]; 545 u8 cvlan_tag[0x1]; 546 u8 svlan_tag[0x1]; 547 u8 frag[0x1]; 548 u8 ip_version[0x4]; 549 u8 tcp_flags[0x9]; 550 551 u8 tcp_sport[0x10]; 552 u8 tcp_dport[0x10]; 553 554 u8 reserved_at_c0[0x10]; 555 u8 ipv4_ihl[0x4]; 556 u8 l3_ok[0x1]; 557 u8 l4_ok[0x1]; 558 u8 ipv4_checksum_ok[0x1]; 559 u8 l4_checksum_ok[0x1]; 560 u8 ip_ttl_hoplimit[0x8]; 561 562 u8 udp_sport[0x10]; 563 u8 udp_dport[0x10]; 564 565 u8 src_ip_127_96[0x20]; 566 567 u8 src_ip_95_64[0x20]; 568 569 u8 src_ip_63_32[0x20]; 570 571 u8 src_ip_31_0[0x20]; 572 573 u8 dst_ip_127_96[0x20]; 574 575 u8 dst_ip_95_64[0x20]; 576 577 u8 dst_ip_63_32[0x20]; 578 579 u8 dst_ip_31_0[0x20]; 580 }; 581 582 struct mlx5_ifc_dr_match_set_misc_bits { 583 u8 gre_c_present[0x1]; 584 u8 bth_a[0x1]; 585 u8 gre_k_present[0x1]; 586 u8 gre_s_present[0x1]; 587 u8 source_vhca_port[0x4]; 588 u8 source_sqn[0x18]; 589 590 u8 source_eswitch_owner_vhca_id[0x10]; 591 u8 source_port[0x10]; 592 593 u8 outer_second_prio[0x3]; 594 u8 outer_second_cfi[0x1]; 595 u8 outer_second_vid[0xc]; 596 u8 inner_second_prio[0x3]; 597 u8 inner_second_cfi[0x1]; 598 u8 inner_second_vid[0xc]; 599 600 u8 outer_second_cvlan_tag[0x1]; 601 u8 inner_second_cvlan_tag[0x1]; 602 u8 outer_second_svlan_tag[0x1]; 603 u8 inner_second_svlan_tag[0x1]; 604 u8 outer_emd_tag[0x1]; 605 u8 reserved_at_65[0xb]; 606 u8 gre_protocol[0x10]; 607 608 u8 gre_key_h[0x18]; 609 u8 gre_key_l[0x8]; 610 611 u8 vxlan_vni[0x18]; 612 u8 bth_opcode[0x8]; 613 614 u8 geneve_vni[0x18]; 615 u8 reserved_at_e4[0x6]; 616 u8 geneve_tlv_option_0_exist[0x1]; 617 u8 geneve_oam[0x1]; 618 619 u8 reserved_at_ec[0xc]; 620 u8 outer_ipv6_flow_label[0x14]; 621 622 u8 reserved_at_100[0xc]; 623 u8 inner_ipv6_flow_label[0x14]; 624 625 u8 reserved_at_120[0xa]; 626 u8 geneve_opt_len[0x6]; 627 u8 geneve_protocol_type[0x10]; 628 629 u8 reserved_at_140[0x8]; 630 u8 bth_dst_qp[0x18]; 631 632 u8 inner_esp_spi[0x20]; 633 634 u8 outer_esp_spi[0x20]; 635 636 u8 reserved_at_1a0[0x20]; 637 u8 reserved_at_1c0[0x20]; 638 u8 reserved_at_1e0[0x20]; 639 }; 640 641 struct mlx5_ifc_dr_match_set_misc2_bits { 642 u8 outer_first_mpls_label[0x14]; 643 u8 outer_first_mpls_exp[0x3]; 644 u8 outer_first_mpls_s_bos[0x1]; 645 u8 outer_first_mpls_ttl[0x8]; 646 647 u8 inner_first_mpls_label[0x14]; 648 u8 inner_first_mpls_exp[0x3]; 649 u8 inner_first_mpls_s_bos[0x1]; 650 u8 inner_first_mpls_ttl[0x8]; 651 652 u8 outer_first_mpls_over_gre_label[0x14]; 653 u8 outer_first_mpls_over_gre_exp[0x3]; 654 u8 outer_first_mpls_over_gre_s_bos[0x1]; 655 u8 outer_first_mpls_over_gre_ttl[0x8]; 656 657 u8 outer_first_mpls_over_udp_label[0x14]; 658 u8 outer_first_mpls_over_udp_exp[0x3]; 659 u8 outer_first_mpls_over_udp_s_bos[0x1]; 660 u8 outer_first_mpls_over_udp_ttl[0x8]; 661 662 u8 metadata_reg_c_7[0x20]; 663 u8 metadata_reg_c_6[0x20]; 664 u8 metadata_reg_c_5[0x20]; 665 u8 metadata_reg_c_4[0x20]; 666 u8 metadata_reg_c_3[0x20]; 667 u8 metadata_reg_c_2[0x20]; 668 u8 metadata_reg_c_1[0x20]; 669 u8 metadata_reg_c_0[0x20]; 670 671 u8 metadata_reg_a[0x20]; 672 673 u8 reserved_at_1a0[0x20]; 674 u8 reserved_at_1c0[0x20]; 675 u8 reserved_at_1e0[0x20]; 676 }; 677 678 struct mlx5_ifc_dr_match_set_misc3_bits { 679 u8 inner_tcp_seq_num[0x20]; 680 681 u8 outer_tcp_seq_num[0x20]; 682 683 u8 inner_tcp_ack_num[0x20]; 684 685 u8 outer_tcp_ack_num[0x20]; 686 687 u8 reserved_at_80[0x8]; 688 u8 outer_vxlan_gpe_vni[0x18]; 689 690 u8 outer_vxlan_gpe_next_protocol[0x8]; 691 u8 outer_vxlan_gpe_flags[0x8]; 692 u8 reserved_at_b0[0x10]; 693 694 u8 icmp_header_data[0x20]; 695 696 u8 icmpv6_header_data[0x20]; 697 698 u8 icmp_type[0x8]; 699 u8 icmp_code[0x8]; 700 u8 icmpv6_type[0x8]; 701 u8 icmpv6_code[0x8]; 702 703 u8 geneve_tlv_option_0_data[0x20]; 704 705 u8 gtpu_teid[0x20]; 706 707 u8 gtpu_msg_type[0x8]; 708 u8 gtpu_msg_flags[0x8]; 709 u8 reserved_at_170[0x10]; 710 711 u8 gtpu_dw_2[0x20]; 712 713 u8 gtpu_first_ext_dw_0[0x20]; 714 715 u8 gtpu_dw_0[0x20]; 716 717 u8 reserved_at_1e0[0x20]; 718 }; 719 720 struct mlx5_ifc_dr_match_set_misc4_bits { 721 u8 prog_sample_field_value_0[0x20]; 722 723 u8 prog_sample_field_id_0[0x20]; 724 725 u8 prog_sample_field_value_1[0x20]; 726 727 u8 prog_sample_field_id_1[0x20]; 728 729 u8 prog_sample_field_value_2[0x20]; 730 731 u8 prog_sample_field_id_2[0x20]; 732 733 u8 prog_sample_field_value_3[0x20]; 734 735 u8 prog_sample_field_id_3[0x20]; 736 737 u8 prog_sample_field_value_4[0x20]; 738 739 u8 prog_sample_field_id_4[0x20]; 740 741 u8 prog_sample_field_value_5[0x20]; 742 743 u8 prog_sample_field_id_5[0x20]; 744 745 u8 prog_sample_field_value_6[0x20]; 746 747 u8 prog_sample_field_id_6[0x20]; 748 749 u8 prog_sample_field_value_7[0x20]; 750 751 u8 prog_sample_field_id_7[0x20]; 752 }; 753 754 struct mlx5_ifc_dr_match_set_misc5_bits { 755 u8 macsec_tag_0[0x20]; 756 757 u8 macsec_tag_1[0x20]; 758 759 u8 macsec_tag_2[0x20]; 760 761 u8 macsec_tag_3[0x20]; 762 763 u8 tunnel_header_0[0x20]; 764 765 u8 tunnel_header_1[0x20]; 766 767 u8 tunnel_header_2[0x20]; 768 769 u8 tunnel_header_3[0x20]; 770 771 u8 reserved_at_100[0x20]; 772 773 u8 reserved_at_120[0x20]; 774 775 u8 reserved_at_140[0x20]; 776 777 u8 reserved_at_160[0x20]; 778 779 u8 reserved_at_180[0x20]; 780 781 u8 reserved_at_1a0[0x20]; 782 783 u8 reserved_at_1c0[0x20]; 784 785 u8 reserved_at_1e0[0x20]; 786 }; 787 788 struct mlx5_ifc_dr_match_param_bits { 789 struct mlx5_ifc_dr_match_spec_bits outer; 790 struct mlx5_ifc_dr_match_set_misc_bits misc; 791 struct mlx5_ifc_dr_match_spec_bits inner; 792 struct mlx5_ifc_dr_match_set_misc2_bits misc2; 793 struct mlx5_ifc_dr_match_set_misc3_bits misc3; 794 struct mlx5_ifc_dr_match_set_misc4_bits misc4; 795 struct mlx5_ifc_dr_match_set_misc5_bits misc5; 796 }; 797 798 struct mlx5_ifc_flow_table_prop_layout_bits { 799 u8 ft_support[0x1]; 800 u8 flow_tag[0x1]; 801 u8 flow_counter[0x1]; 802 u8 flow_modify_en[0x1]; 803 u8 modify_root[0x1]; 804 u8 identified_miss_table[0x1]; 805 u8 flow_table_modify[0x1]; 806 u8 reformat[0x1]; 807 u8 decap[0x1]; 808 u8 reset_root_to_default[0x1]; 809 u8 pop_vlan[0x1]; 810 u8 push_vlan[0x1]; 811 u8 fpga_vendor_acceleration[0x1]; 812 u8 pop_vlan_2[0x1]; 813 u8 push_vlan_2[0x1]; 814 u8 reformat_and_vlan_action[0x1]; 815 u8 modify_and_vlan_action[0x1]; 816 u8 sw_owner[0x1]; 817 u8 reformat_l3_tunnel_to_l2[0x1]; 818 u8 reformat_l2_to_l3_tunnel[0x1]; 819 u8 reformat_and_modify_action[0x1]; 820 u8 reserved_at_15[0x9]; 821 u8 sw_owner_v2[0x1]; 822 u8 reserved_at_1f[0x1]; 823 824 u8 reserved_at_20[0x2]; 825 u8 log_max_ft_size[0x6]; 826 u8 log_max_modify_header_context[0x8]; 827 u8 max_modify_header_actions[0x8]; 828 u8 max_ft_level[0x8]; 829 830 u8 reserved_at_40[0x10]; 831 u8 metadata_reg_b_width[0x8]; 832 u8 metadata_reg_a_width[0x8]; 833 834 u8 reserved_at_60[0x18]; 835 u8 log_max_ft_num[0x8]; 836 837 u8 reserved_at_80[0x10]; 838 u8 log_max_flow_counter[0x8]; 839 u8 log_max_destination[0x8]; 840 841 u8 reserved_at_a0[0x18]; 842 u8 log_max_flow[0x8]; 843 844 u8 reserved_at_c0[0x40]; 845 846 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 847 848 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 849 }; 850 851 enum { 852 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 853 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 854 mlx5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 855 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 856 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 857 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 858 MLX5_FLEX_PARSER_GENEVE_OPT_0_ENABLED = 1 << 10, 859 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 860 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 861 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 862 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 863 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 864 }; 865 866 enum mlx5_ifc_steering_format_version { 867 MLX5_HW_CONNECTX_5 = 0x0, 868 MLX5_HW_CONNECTX_6DX = 0x1, 869 MLX5_HW_CONNECTX_7 = 0x2, 870 }; 871 872 enum mlx5_ifc_ste_v1_modify_hdr_offset { 873 MLX5_MODIFY_HEADER_V1_QW_OFFSET = 0x20, 874 }; 875 876 struct mlx5_ifc_cmd_hca_cap_bits { 877 u8 access_other_hca_roce[0x1]; 878 u8 reserved_at_1[0x1e]; 879 u8 vhca_resource_manager[0x1]; 880 881 u8 hca_cap_2[0x1]; 882 u8 reserved_at_21[0xf]; 883 u8 vhca_id[0x10]; 884 885 u8 reserved_at_40[0x20]; 886 887 u8 reserved_at_60[0x2]; 888 u8 qp_data_in_order[0x1]; 889 u8 reserved_at_63[0x8]; 890 u8 log_dma_mmo_max_size[0x5]; 891 u8 relaxed_ordering_write_pci_enabled[0x1]; 892 u8 reserved_at_77[0xf]; 893 894 u8 log_max_srq_sz[0x8]; 895 u8 log_max_qp_sz[0x8]; 896 u8 reserved_at_90[0x3]; 897 u8 isolate_vl_tc_new[0x1]; 898 u8 reserved_at_94[0x4]; 899 u8 prio_tag_required[0x1]; 900 u8 reserved_at_99[0x2]; 901 u8 log_max_qp[0x5]; 902 903 u8 reserved_at_a0[0xb]; 904 u8 log_max_srq[0x5]; 905 u8 reserved_at_b0[0x10]; 906 907 u8 reserved_at_c0[0x8]; 908 u8 log_max_cq_sz[0x8]; 909 u8 relaxed_ordering_write_umr[0x1]; 910 u8 relaxed_ordering_read_umr[0x1]; 911 u8 reserved_at_d2[0x9]; 912 u8 log_max_cq[0x5]; 913 914 u8 log_max_eq_sz[0x8]; 915 u8 relaxed_ordering_write[0x1]; 916 u8 relaxed_ordering_read[0x1]; 917 u8 log_max_mkey[0x6]; 918 u8 tunneled_atomic[0x1]; 919 u8 as_notify[0x1]; 920 u8 m_pci_port[0x1]; 921 u8 m_vhca_mk[0x1]; 922 u8 cmd_on_behalf[0x1]; 923 u8 device_emulation_manager[0x1]; 924 u8 terminate_scatter_list_mkey[0x1]; 925 u8 repeated_mkey[0x1]; 926 u8 dump_fill_mkey[0x1]; 927 u8 reserved_at_f9[0x1]; 928 u8 resources_on_nvme_emulation_manager[0x1]; 929 u8 reserved_at_fb[0x1]; 930 u8 log_max_eq[0x4]; 931 932 u8 max_indirection[0x8]; 933 u8 fixed_buffer_size[0x1]; 934 u8 log_max_mrw_sz[0x7]; 935 u8 force_teardown[0x1]; 936 u8 fast_teardown[0x1]; 937 u8 log_max_bsf_list_size[0x6]; 938 u8 umr_extended_translation_offset[0x1]; 939 u8 null_mkey[0x1]; 940 u8 log_max_klm_list_size[0x6]; 941 942 u8 reserved_at_120[0x2]; 943 u8 qpc_extension[0x1]; 944 u8 reserved_at_123[0x7]; 945 u8 log_max_ra_req_dc[0x6]; 946 u8 reserved_at_130[0xa]; 947 u8 log_max_ra_res_dc[0x6]; 948 949 u8 reserved_at_140[0x7]; 950 u8 sig_crc64_xp10[0x1]; 951 u8 sig_crc32c[0x1]; 952 u8 reserved_at_149[0x1]; 953 u8 log_max_ra_req_qp[0x6]; 954 u8 reserved_at_150[0x1]; 955 u8 rts2rts_qp_udp_sport[0x1]; 956 u8 rts2rts_lag_tx_port_affinity[0x1]; 957 u8 dma_mmo_sq[0x1]; 958 u8 reserved_at_154[0x6]; 959 u8 log_max_ra_res_qp[0x6]; 960 961 u8 end_pad[0x1]; 962 u8 cc_query_allowed[0x1]; 963 u8 cc_modify_allowed[0x1]; 964 u8 start_pad[0x1]; 965 u8 cache_line_128byte[0x1]; 966 u8 gid_table_size_ro[0x1]; 967 u8 pkey_table_size_ro[0x1]; 968 u8 reserved_at_167[0x1]; 969 u8 rnr_nak_q_counters[0x1]; 970 u8 rts2rts_qp_counters_set_id[0x1]; 971 u8 rts2rts_qp_dscp[0x1]; 972 u8 reserved_at_16b[0x4]; 973 u8 qcam_reg[0x1]; 974 u8 gid_table_size[0x10]; 975 976 u8 out_of_seq_cnt[0x1]; 977 u8 vport_counters[0x1]; 978 u8 retransmission_q_counters[0x1]; 979 u8 debug[0x1]; 980 u8 modify_rq_counters_set_id[0x1]; 981 u8 rq_delay_drop[0x1]; 982 u8 max_qp_cnt[0xa]; 983 u8 pkey_table_size[0x10]; 984 985 u8 vport_group_manager[0x1]; 986 u8 vhca_group_manager[0x1]; 987 u8 ib_virt[0x1]; 988 u8 eth_virt[0x1]; 989 u8 vnic_env_queue_counters[0x1]; 990 u8 ets[0x1]; 991 u8 nic_flow_table[0x1]; 992 u8 eswitch_manager[0x1]; 993 u8 device_memory[0x1]; 994 u8 mcam_reg[0x1]; 995 u8 pcam_reg[0x1]; 996 u8 local_ca_ack_delay[0x5]; 997 u8 port_module_event[0x1]; 998 u8 enhanced_retransmission_q_counters[0x1]; 999 u8 port_checks[0x1]; 1000 u8 pulse_gen_control[0x1]; 1001 u8 disable_link_up_by_init_hca[0x1]; 1002 u8 beacon_led[0x1]; 1003 u8 port_type[0x2]; 1004 u8 num_ports[0x8]; 1005 1006 u8 reserved_at_1c0[0x1]; 1007 u8 pps[0x1]; 1008 u8 pps_modify[0x1]; 1009 u8 log_max_msg[0x5]; 1010 u8 multi_path_xrc_rdma[0x1]; 1011 u8 multi_path_dc_rdma[0x1]; 1012 u8 multi_path_rc_rdma[0x1]; 1013 u8 traffic_fast_control[0x1]; 1014 u8 max_tc[0x4]; 1015 u8 temp_warn_event[0x1]; 1016 u8 dcbx[0x1]; 1017 u8 general_notification_event[0x1]; 1018 u8 multi_prio_sq[0x1]; 1019 u8 afu_owner[0x1]; 1020 u8 fpga[0x1]; 1021 u8 rol_s[0x1]; 1022 u8 rol_g[0x1]; 1023 u8 ib_port_sniffer[0x1]; 1024 u8 wol_s[0x1]; 1025 u8 wol_g[0x1]; 1026 u8 wol_a[0x1]; 1027 u8 wol_b[0x1]; 1028 u8 wol_m[0x1]; 1029 u8 wol_u[0x1]; 1030 u8 wol_p[0x1]; 1031 1032 u8 stat_rate_support[0x10]; 1033 u8 sig_block_4048[0x1]; 1034 u8 reserved_at_1f1[0xb]; 1035 u8 cqe_version[0x4]; 1036 1037 u8 compact_address_vector[0x1]; 1038 u8 eth_striding_wq[0x1]; 1039 u8 reserved_at_202[0x1]; 1040 u8 ipoib_enhanced_offloads[0x1]; 1041 u8 ipoib_basic_offloads[0x1]; 1042 u8 ib_striding_wq[0x1]; 1043 u8 repeated_block_disabled[0x1]; 1044 u8 umr_modify_entity_size_disabled[0x1]; 1045 u8 umr_modify_atomic_disabled[0x1]; 1046 u8 umr_indirect_mkey_disabled[0x1]; 1047 u8 umr_fence[0x2]; 1048 u8 dc_req_sctr_data_cqe[0x1]; 1049 u8 dc_connect_qp[0x1]; 1050 u8 dc_cnak_trace[0x1]; 1051 u8 drain_sigerr[0x1]; 1052 u8 cmdif_checksum[0x2]; 1053 u8 sigerr_cqe[0x1]; 1054 u8 reserved_at_213[0x1]; 1055 u8 wq_signature[0x1]; 1056 u8 sctr_data_cqe[0x1]; 1057 u8 reserved_at_216[0x1]; 1058 u8 sho[0x1]; 1059 u8 tph[0x1]; 1060 u8 rf[0x1]; 1061 u8 dct[0x1]; 1062 u8 qos[0x1]; 1063 u8 eth_net_offloads[0x1]; 1064 u8 roce[0x1]; 1065 u8 atomic[0x1]; 1066 u8 extended_retry_count[0x1]; 1067 1068 u8 cq_oi[0x1]; 1069 u8 cq_resize[0x1]; 1070 u8 cq_moderation[0x1]; 1071 u8 cq_period_mode_modify[0x1]; 1072 u8 cq_invalidate[0x1]; 1073 u8 reserved_at_225[0x1]; 1074 u8 cq_eq_remap[0x1]; 1075 u8 pg[0x1]; 1076 u8 block_lb_mc[0x1]; 1077 u8 exponential_backoff[0x1]; 1078 u8 scqe_break_moderation[0x1]; 1079 u8 cq_period_start_from_cqe[0x1]; 1080 u8 cd[0x1]; 1081 u8 atm[0x1]; 1082 u8 apm[0x1]; 1083 u8 vector_calc[0x1]; 1084 u8 umr_ptr_rlkey[0x1]; 1085 u8 imaicl[0x1]; 1086 u8 qp_packet_based[0x1]; 1087 u8 reserved_at_233[0x1]; 1088 u8 ipoib_enhanced_pkey_change[0x1]; 1089 u8 initiator_src_dct_in_cqe[0x1]; 1090 u8 qkv[0x1]; 1091 u8 pkv[0x1]; 1092 u8 set_deth_sqpn[0x1]; 1093 u8 rts2rts_primary_sl[0x1]; 1094 u8 initiator_src_dct[0x1]; 1095 u8 dc_v2[0x1]; 1096 u8 xrc[0x1]; 1097 u8 ud[0x1]; 1098 u8 uc[0x1]; 1099 u8 rc[0x1]; 1100 1101 u8 uar_4k[0x1]; 1102 u8 reserved_at_241[0x7]; 1103 u8 fl_rc_qp_when_roce_disabled[0x1]; 1104 u8 reserved_at_249[0x1]; 1105 u8 uar_sz[0x6]; 1106 u8 reserved_at_250[0x2]; 1107 u8 umem_uid_0[0x1]; 1108 u8 log_max_dc_cnak_qps[0x5]; 1109 u8 log_pg_sz[0x8]; 1110 1111 u8 bf[0x1]; 1112 u8 driver_version[0x1]; 1113 u8 pad_tx_eth_packet[0x1]; 1114 u8 query_driver_version[0x1]; 1115 u8 max_qp_retry_freq[0x1]; 1116 u8 qp_by_name[0x1]; 1117 u8 mkey_by_name[0x1]; 1118 u8 reserved_at_267[0x1]; 1119 u8 suspend_qp_uc[0x1]; 1120 u8 suspend_qp_ud[0x1]; 1121 u8 suspend_qp_rc[0x1]; 1122 u8 log_bf_reg_size[0x5]; 1123 u8 reserved_at_270[0x6]; 1124 u8 lag_dct[0x2]; 1125 u8 lag_tx_port_affinity[0x1]; 1126 u8 reserved_at_279[0x2]; 1127 u8 lag_master[0x1]; 1128 u8 num_lag_ports[0x4]; 1129 1130 u8 num_of_diagnostic_counters[0x10]; 1131 u8 max_wqe_sz_sq[0x10]; 1132 1133 u8 reserved_at_2a0[0x10]; 1134 u8 max_wqe_sz_rq[0x10]; 1135 1136 u8 max_flow_counter_31_16[0x10]; 1137 u8 max_wqe_sz_sq_dc[0x10]; 1138 1139 u8 reserved_at_2e0[0x7]; 1140 u8 max_qp_mcg[0x19]; 1141 1142 u8 mlnx_tag_ethertype[0x10]; 1143 u8 reserved_at_310[0x8]; 1144 u8 log_max_mcg[0x8]; 1145 1146 u8 reserved_at_320[0x3]; 1147 u8 log_max_transport_domain[0x5]; 1148 u8 reserved_at_328[0x3]; 1149 u8 log_max_pd[0x5]; 1150 u8 reserved_at_330[0xb]; 1151 u8 log_max_xrcd[0x5]; 1152 1153 u8 nic_receive_steering_discard[0x1]; 1154 u8 receive_discard_vport_down[0x1]; 1155 u8 transmit_discard_vport_down[0x1]; 1156 u8 eq_overrun_count[0x1]; 1157 u8 nic_receive_steering_depth[0x1]; 1158 u8 invalid_command_count[0x1]; 1159 u8 quota_exceeded_count[0x1]; 1160 u8 reserved_at_347[0x1]; 1161 u8 log_max_flow_counter_bulk[0x8]; 1162 u8 max_flow_counter_15_0[0x10]; 1163 1164 u8 modify_tis[0x1]; 1165 u8 reserved_at_361[0x2]; 1166 u8 log_max_rq[0x5]; 1167 u8 reserved_at_368[0x3]; 1168 u8 log_max_sq[0x5]; 1169 u8 reserved_at_370[0x3]; 1170 u8 log_max_tir[0x5]; 1171 u8 reserved_at_378[0x3]; 1172 u8 log_max_tis[0x5]; 1173 1174 u8 basic_cyclic_rcv_wqe[0x1]; 1175 u8 reserved_at_381[0x2]; 1176 u8 log_max_rmp[0x5]; 1177 u8 reserved_at_388[0x3]; 1178 u8 log_max_rqt[0x5]; 1179 u8 reserved_at_390[0x3]; 1180 u8 log_max_rqt_size[0x5]; 1181 u8 reserved_at_398[0x3]; 1182 u8 log_max_tis_per_sq[0x5]; 1183 1184 u8 ext_stride_num_range[0x1]; 1185 u8 reserved_at_3a1[0x2]; 1186 u8 log_max_stride_sz_rq[0x5]; 1187 u8 reserved_at_3a8[0x3]; 1188 u8 log_min_stride_sz_rq[0x5]; 1189 u8 reserved_at_3b0[0x3]; 1190 u8 log_max_stride_sz_sq[0x5]; 1191 u8 reserved_at_3b8[0x3]; 1192 u8 log_min_stride_sz_sq[0x5]; 1193 1194 u8 hairpin[0x1]; 1195 u8 reserved_at_3c1[0x2]; 1196 u8 log_max_hairpin_queues[0x5]; 1197 u8 reserved_at_3c8[0x3]; 1198 u8 log_max_hairpin_wq_data_sz[0x5]; 1199 u8 reserved_at_3d0[0x3]; 1200 u8 log_max_hairpin_num_packets[0x5]; 1201 u8 reserved_at_3d8[0x3]; 1202 u8 log_max_wq_sz[0x5]; 1203 1204 u8 nic_vport_change_event[0x1]; 1205 u8 disable_local_lb_uc[0x1]; 1206 u8 disable_local_lb_mc[0x1]; 1207 u8 log_min_hairpin_wq_data_sz[0x5]; 1208 u8 reserved_at_3e8[0x3]; 1209 u8 log_max_vlan_list[0x5]; 1210 u8 reserved_at_3f0[0x1]; 1211 u8 aes_xts_single_block_le_tweak[0x1]; 1212 u8 aes_xts_multi_block_be_tweak[0x1]; 1213 u8 log_max_current_mc_list[0x5]; 1214 u8 reserved_at_3f8[0x3]; 1215 u8 log_max_current_uc_list[0x5]; 1216 1217 u8 general_obj_types[0x40]; 1218 1219 u8 sq_ts_format[0x2]; 1220 u8 rq_ts_format[0x2]; 1221 u8 steering_format_version[0x4]; 1222 u8 create_qp_start_hint[0x18]; 1223 1224 u8 reserved_at_460[0x8]; 1225 u8 aes_xts_multi_block_le_tweak[0x1]; 1226 u8 crypto[0x1]; 1227 u8 reserved_at_46a[0x6]; 1228 u8 max_num_eqs[0x10]; 1229 1230 u8 sigerr_domain_and_sig_type[0x1]; 1231 u8 reserved_at_481[0x2]; 1232 u8 log_max_l2_table[0x5]; 1233 u8 reserved_at_488[0x8]; 1234 u8 log_uar_page_sz[0x10]; 1235 1236 u8 reserved_at_4a0[0x20]; 1237 1238 u8 device_frequency_mhz[0x20]; 1239 1240 u8 device_frequency_khz[0x20]; 1241 1242 u8 capi[0x1]; 1243 u8 create_pec[0x1]; 1244 u8 nvmf_target_offload[0x1]; 1245 u8 capi_invalidate[0x1]; 1246 u8 reserved_at_504[0x17]; 1247 u8 log_max_pasid[0x5]; 1248 1249 u8 num_of_uars_per_page[0x20]; 1250 1251 u8 flex_parser_protocols[0x20]; 1252 1253 u8 reserved_at_560[0x10]; 1254 u8 flex_parser_header_modify[0x1]; 1255 u8 reserved_at_571[0x2]; 1256 u8 log_max_guaranteed_connections[0x5]; 1257 u8 reserved_at_578[0x3]; 1258 u8 log_max_dct_connections[0x5]; 1259 1260 u8 log_max_atomic_size_qp[0x8]; 1261 u8 reserved_at_588[0x10]; 1262 u8 log_max_atomic_size_dc[0x8]; 1263 1264 u8 reserved_at_5a0[0x1c]; 1265 u8 mini_cqe_resp_stride_index[0x1]; 1266 u8 cqe_128_always[0x1]; 1267 u8 cqe_compression_128b[0x1]; 1268 u8 cqe_compression[0x1]; 1269 1270 u8 cqe_compression_timeout[0x10]; 1271 u8 cqe_compression_max_num[0x10]; 1272 1273 u8 reserved_at_5e0[0x8]; 1274 u8 flex_parser_id_gtpu_dw_0[0x4]; 1275 u8 log_max_tm_offloaded_op_size[0x4]; 1276 u8 tag_matching[0x1]; 1277 u8 rndv_offload_rc[0x1]; 1278 u8 rndv_offload_dc[0x1]; 1279 u8 log_tag_matching_list_sz[0x5]; 1280 u8 reserved_at_5f8[0x3]; 1281 u8 log_max_xrq[0x5]; 1282 1283 u8 affiliate_nic_vport_criteria[0x8]; 1284 u8 native_port_num[0x8]; 1285 u8 num_vhca_ports[0x8]; 1286 u8 flex_parser_id_gtpu_teid[0x4]; 1287 u8 reserved_at_61c[0x1]; 1288 u8 trusted_vnic_vhca[0x1]; 1289 u8 sw_owner_id[0x1]; 1290 u8 reserve_not_to_use[0x1]; 1291 u8 reserved_at_620[0x60]; 1292 u8 sf[0x1]; 1293 u8 reserved_at_682[0x43]; 1294 u8 flex_parser_id_geneve_opt_0[0x4]; 1295 u8 flex_parser_id_icmp_dw1[0x4]; 1296 u8 flex_parser_id_icmp_dw0[0x4]; 1297 u8 flex_parser_id_icmpv6_dw1[0x4]; 1298 u8 flex_parser_id_icmpv6_dw0[0x4]; 1299 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1300 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1301 1302 u8 reserved_at_6e0[0x20]; 1303 1304 u8 flex_parser_id_gtpu_dw_2[0x4]; 1305 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1306 u8 reserved_at_708[0x18]; 1307 1308 u8 reserved_at_720[0x20]; 1309 1310 u8 reserved_at_740[0x8]; 1311 u8 dma_mmo_qp[0x1]; 1312 u8 reserved_at_749[0x17]; 1313 1314 u8 reserved_at_760[0x3]; 1315 u8 log_max_num_header_modify_argument[0x5]; 1316 u8 reserved_at_768[0x4]; 1317 u8 log_header_modify_argument_granularity[0x4]; 1318 u8 reserved_at_770[0x3]; 1319 u8 log_header_modify_argument_max_alloc[0x5]; 1320 u8 reserved_at_778[0x8]; 1321 1322 u8 reserved_at_780[0x40]; 1323 1324 u8 match_definer_format_supported[0x40]; 1325 }; 1326 1327 struct mlx5_ifc_header_modify_cap_properties_bits { 1328 struct mlx5_ifc_flow_table_fields_supported_bits set_action_field_support; 1329 1330 u8 reserved_at_80[0x80]; 1331 1332 struct mlx5_ifc_flow_table_fields_supported_bits add_action_field_support; 1333 1334 u8 reserved_at_180[0x80]; 1335 1336 u8 copy_action_field_support[8][0x20]; 1337 1338 u8 reserved_at_300[0x100]; 1339 }; 1340 1341 struct mlx5_ifc_flow_table_fields_supported_2_bits { 1342 u8 reserved_at_0[0xf]; 1343 u8 tunnel_header_2_3[0x1]; 1344 u8 tunnel_header_0_1[0x1]; 1345 u8 reserved_at_11[0x6]; 1346 u8 inner_l3_ok[0x1]; 1347 u8 inner_l4_ok[0x1]; 1348 u8 outer_l3_ok[0x1]; 1349 u8 outer_l4_ok[0x1]; 1350 u8 psp_header[0x1]; 1351 u8 inner_ipv4_checksum_ok[0x1]; 1352 u8 inner_l4_checksum_ok[0x1]; 1353 u8 outer_ipv4_checksum_ok[0x1]; 1354 u8 outer_l4_checksum_ok[0x1]; 1355 1356 u8 reserved_at_20[0x60]; 1357 }; 1358 1359 struct mlx5_ifc_flow_table_nic_cap_bits { 1360 u8 nic_rx_multi_path_tirs[0x1]; 1361 u8 nic_rx_multi_path_tirs_fts[0x1]; 1362 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 1363 u8 reserved_at_3[0x1]; 1364 u8 nic_rx_flow_tag_multipath_en[0x1]; 1365 u8 reserved_at_5[0x13]; 1366 u8 nic_receive_max_steering_depth[0x8]; 1367 1368 u8 encap_general_header[0x1]; 1369 u8 reserved_at_21[0xa]; 1370 u8 log_max_packet_reformat_context[0x5]; 1371 u8 reserved_at_30[0x6]; 1372 u8 max_encap_header_size[0xa]; 1373 1374 u8 reserved_at_40[0x1c0]; 1375 1376 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 1377 1378 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 1379 1380 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 1381 1382 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 1383 1384 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 1385 1386 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 1387 1388 u8 reserved_at_e00[0x200]; 1389 1390 struct mlx5_ifc_header_modify_cap_properties_bits header_modify_nic_receive; 1391 1392 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive; 1393 1394 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_nic_receive; 1395 1396 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 1397 1398 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_nic_receive_rdma; 1399 1400 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_sniffer; 1401 1402 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_nic_receive_sniffer; 1403 1404 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit; 1405 1406 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_nic_transmit; 1407 1408 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 1409 1410 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_nic_transmit_rdma; 1411 1412 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_sniffer; 1413 1414 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_nic_transmit_sniffer; 1415 1416 u8 reserved_at_1400[0x200]; 1417 1418 struct mlx5_ifc_header_modify_cap_properties_bits header_modify_nic_transmit; 1419 1420 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 1421 1422 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 1423 1424 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 1425 1426 u8 reserved_at_20c0[0x5f40]; 1427 }; 1428 1429 struct mlx5_ifc_flow_table_eswitch_cap_bits { 1430 u8 reserved_at_0[0x1c]; 1431 u8 fdb_multi_path_to_table[0x1]; 1432 u8 reserved_at_1d[0x1e3]; 1433 1434 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 1435 1436 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 1437 1438 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 1439 1440 u8 reserved_at_800[0x1000]; 1441 1442 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 1443 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 1444 u8 sw_steering_uplink_icm_address_rx[0x40]; 1445 u8 sw_steering_uplink_icm_address_tx[0x40]; 1446 1447 u8 reserved_at_1900[0x6700]; 1448 }; 1449 1450 struct mlx5_ifc_odp_per_transport_service_cap_bits { 1451 u8 send[0x1]; 1452 u8 receive[0x1]; 1453 u8 write[0x1]; 1454 u8 read[0x1]; 1455 u8 atomic[0x1]; 1456 u8 srq_receive[0x1]; 1457 u8 reserved_at_6[0x1a]; 1458 }; 1459 1460 struct mlx5_ifc_odp_cap_bits { 1461 u8 reserved_at_0[0x40]; 1462 1463 u8 sig[0x1]; 1464 u8 reserved_at_41[0x1f]; 1465 1466 u8 reserved_at_60[0x20]; 1467 1468 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1469 1470 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1471 1472 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1473 1474 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1475 1476 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1477 1478 u8 reserved_at_120[0x6e0]; 1479 }; 1480 1481 struct mlx5_ifc_e_switch_cap_bits { 1482 u8 reserved_at_0[0x4b]; 1483 u8 log_max_esw_sf[0x5]; 1484 u8 esw_sf_base_id[0x10]; 1485 1486 u8 esw_manager_vport_number_valid[0x1]; 1487 u8 reserved_at_61[0xf]; 1488 u8 esw_manager_vport_number[0x10]; 1489 1490 u8 reserved_at_80[0x780]; 1491 }; 1492 1493 enum { 1494 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 1495 ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP = 1 << 4, 1496 }; 1497 1498 enum { 1499 TSAR_TYPE_CAP_MASK_DWRR = 1 << 0, 1500 }; 1501 1502 struct mlx5_ifc_qos_cap_bits { 1503 u8 reserved_at_0[0x8]; 1504 u8 nic_sq_scheduling[0x1]; 1505 u8 nic_bw_share[0x1]; 1506 u8 nic_rate_limit[0x1]; 1507 u8 reserved_at_b[0x15]; 1508 1509 u8 reserved_at_20[0x1]; 1510 u8 nic_qp_scheduling[0x1]; 1511 u8 reserved_at_22[0x1e]; 1512 1513 u8 reserved_at_40[0xc0]; 1514 1515 u8 nic_element_type[0x10]; 1516 u8 nic_tsar_type[0x10]; 1517 1518 u8 reserved_at_120[0x6e0]; 1519 }; 1520 1521 struct mlx5_ifc_cmd_hca_cap_2_bits { 1522 u8 reserved_at_0[0x80]; 1523 1524 u8 reserved_at_80[0x13]; 1525 u8 log_reserved_qpn_granularity[0x5]; 1526 u8 reserved_at_98[0x8]; 1527 1528 u8 reserved_at_a0[0x760]; 1529 }; 1530 1531 enum { 1532 MLX5_CRYPTO_CAPS_WRAPPED_IMPORT_METHOD_AES = 0x4, 1533 }; 1534 1535 struct mlx5_ifc_crypto_caps_bits { 1536 u8 wrapped_crypto_operational[0x1]; 1537 u8 wrapped_crypto_going_to_commissioning[0x1]; 1538 u8 reserved_at_2[0x16]; 1539 u8 wrapped_import_method[0x8]; 1540 1541 u8 reserved_at_20[0xb]; 1542 u8 log_max_num_deks[0x5]; 1543 u8 reserved_at_30[0x3]; 1544 u8 log_max_num_import_keks[0x5]; 1545 u8 reserved_at_38[0x3]; 1546 u8 log_max_num_creds[0x5]; 1547 1548 u8 failed_selftests[0x10]; 1549 u8 num_nv_import_keks[0x8]; 1550 u8 num_nv_credentials[0x8]; 1551 1552 u8 reserved_at_60[0x7a0]; 1553 }; 1554 1555 union mlx5_ifc_hca_cap_union_bits { 1556 struct mlx5_ifc_atomic_caps_bits atomic_caps; 1557 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 1558 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 1559 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 1560 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 1561 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 1562 struct mlx5_ifc_odp_cap_bits odp_cap; 1563 struct mlx5_ifc_roce_cap_bits roce_caps; 1564 struct mlx5_ifc_qos_cap_bits qos_caps; 1565 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 1566 struct mlx5_ifc_crypto_caps_bits crypto_caps; 1567 u8 reserved_at_0[0x8000]; 1568 }; 1569 1570 struct mlx5_ifc_query_hca_cap_out_bits { 1571 u8 status[0x8]; 1572 u8 reserved_at_8[0x18]; 1573 1574 u8 syndrome[0x20]; 1575 1576 u8 reserved_at_40[0x40]; 1577 1578 union mlx5_ifc_hca_cap_union_bits capability; 1579 }; 1580 1581 struct mlx5_ifc_query_hca_cap_in_bits { 1582 u8 opcode[0x10]; 1583 u8 reserved_at_10[0x10]; 1584 1585 u8 reserved_at_20[0x10]; 1586 u8 op_mod[0x10]; 1587 1588 u8 other_function[0x1]; 1589 u8 reserved_at_41[0xf]; 1590 u8 function_id[0x10]; 1591 1592 u8 reserved_at_60[0x20]; 1593 }; 1594 1595 enum mlx5_cap_type { 1596 MLX5_CAP_GENERAL = 0, 1597 MLX5_CAP_ODP = 2, 1598 MLX5_CAP_ATOMIC = 3, 1599 MLX5_CAP_ROCE, 1600 MLX5_CAP_NUM, 1601 }; 1602 1603 enum { 1604 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1, 1605 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1, 1606 MLX5_SET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1, 1607 MLX5_SET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE = 0x8 << 1, 1608 MLX5_SET_HCA_CAP_OP_MOD_QOS = 0xc << 1, 1609 MLX5_SET_HCA_CAP_OP_MOD_ESW = 0x9 << 1, 1610 MLX5_SET_HCA_CAP_OP_MOD_DEVICE_MEMORY = 0xf << 1, 1611 MLX5_SET_HCA_CAP_OP_MOD_CRYPTO = 0x1a << 1, 1612 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE_CAP_2 = 0x20 << 1, 1613 }; 1614 1615 enum { 1616 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 1617 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 1618 MLX5_MKC_ACCESS_MODE_KLMFBS = 0x3, 1619 }; 1620 1621 struct mlx5_ifc_klm_bits { 1622 u8 byte_count[0x20]; 1623 u8 mkey[0x20]; 1624 u8 address[0x40]; 1625 }; 1626 1627 struct mlx5_ifc_mkc_bits { 1628 u8 reserved_at_0[0x1]; 1629 u8 free[0x1]; 1630 u8 reserved_at_2[0x1]; 1631 u8 access_mode_4_2[0x3]; 1632 u8 reserved_at_6[0x7]; 1633 u8 relaxed_ordering_write[0x1]; 1634 u8 reserved_at_e[0x1]; 1635 u8 small_fence_on_rdma_read_response[0x1]; 1636 u8 umr_en[0x1]; 1637 u8 a[0x1]; 1638 u8 rw[0x1]; 1639 u8 rr[0x1]; 1640 u8 lw[0x1]; 1641 u8 lr[0x1]; 1642 u8 access_mode_1_0[0x2]; 1643 u8 reserved_at_18[0x8]; 1644 1645 u8 qpn[0x18]; 1646 u8 mkey_7_0[0x8]; 1647 1648 u8 reserved_at_40[0x20]; 1649 1650 u8 length64[0x1]; 1651 u8 bsf_en[0x1]; 1652 u8 sync_umr[0x1]; 1653 u8 reserved_at_63[0x2]; 1654 u8 expected_sigerr_count[0x1]; 1655 u8 reserved_at_66[0x1]; 1656 u8 en_rinval[0x1]; 1657 u8 pd[0x18]; 1658 1659 u8 start_addr[0x40]; 1660 1661 u8 len[0x40]; 1662 1663 u8 bsf_octword_size[0x20]; 1664 1665 u8 reserved_at_120[0x80]; 1666 1667 u8 translations_octword_size[0x20]; 1668 1669 u8 reserved_at_1c0[0x19]; 1670 u8 relaxed_ordering_read[0x1]; 1671 u8 reserved_at_1d9[0x1]; 1672 u8 log_page_size[0x5]; 1673 1674 u8 reserved_at_1e0[0x3]; 1675 u8 crypto_en[0x2]; 1676 u8 reserved_at_1e5[0x1b]; 1677 }; 1678 1679 struct mlx5_ifc_create_mkey_out_bits { 1680 u8 status[0x8]; 1681 u8 reserved_at_8[0x18]; 1682 1683 u8 syndrome[0x20]; 1684 1685 u8 reserved_at_40[0x8]; 1686 u8 mkey_index[0x18]; 1687 1688 u8 reserved_at_60[0x20]; 1689 }; 1690 1691 struct mlx5_ifc_create_mkey_in_bits { 1692 u8 opcode[0x10]; 1693 u8 reserved_at_10[0x10]; 1694 1695 u8 reserved_at_20[0x10]; 1696 u8 op_mod[0x10]; 1697 1698 u8 reserved_at_40[0x20]; 1699 1700 u8 pg_access[0x1]; 1701 u8 mkey_umem_valid[0x1]; 1702 u8 reserved_at_62[0x1e]; 1703 1704 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 1705 1706 u8 reserved_at_280[0x80]; 1707 1708 u8 translations_octword_actual_size[0x20]; 1709 1710 u8 reserved_at_320[0x560]; 1711 1712 u8 klm_pas_mtt[0][0x20]; 1713 }; 1714 1715 struct mlx5_ifc_destroy_mkey_out_bits { 1716 u8 status[0x8]; 1717 u8 reserved_at_8[0x18]; 1718 1719 u8 syndrome[0x20]; 1720 1721 u8 reserved_at_40[0x40]; 1722 }; 1723 1724 struct mlx5_ifc_destroy_mkey_in_bits { 1725 u8 opcode[0x10]; 1726 u8 uid[0x10]; 1727 1728 u8 reserved_at_20[0x10]; 1729 u8 op_mod[0x10]; 1730 1731 u8 reserved_at_40[0x8]; 1732 u8 mkey_index[0x18]; 1733 1734 u8 reserved_at_60[0x20]; 1735 }; 1736 1737 struct mlx5_ifc_l2_hdr_bits { 1738 u8 dmac_47_16[0x20]; 1739 u8 dmac_15_0[0x10]; 1740 u8 smac_47_32[0x10]; 1741 u8 smac_31_0[0x20]; 1742 u8 ethertype[0x10]; 1743 u8 vlan_type[0x10]; 1744 u8 vlan[0x10]; 1745 }; 1746 1747 enum { 1748 FS_FT_NIC_RX = 0x0, 1749 FS_FT_NIC_TX = 0x1, 1750 FS_FT_ESW_EGRESS_ACL = 0x2, 1751 FS_FT_ESW_INGRESS_ACL = 0x3, 1752 FS_FT_FDB = 0X4, 1753 FS_FT_SNIFFER_RX = 0X5, 1754 FS_FT_SNIFFER_TX = 0X6, 1755 }; 1756 1757 struct mlx5_ifc_ste_general_bits { 1758 u8 entry_type[0x4]; 1759 u8 reserved_at_4[0x4]; 1760 u8 entry_sub_type[0x8]; 1761 u8 byte_mask[0x10]; 1762 u8 next_table_base_63_48[0x10]; 1763 u8 next_lu_type[0x8]; 1764 u8 next_table_base_39_32_size[0x8]; 1765 u8 next_table_base_31_5_size[0x1b]; 1766 u8 linear_hash_enable[0x1]; 1767 u8 reserved_at_5c[0x2]; 1768 u8 next_table_rank[0x2]; 1769 u8 reserved_at_60[0xa0]; 1770 u8 tag_value[0x60]; 1771 u8 bit_mask[0x60]; 1772 }; 1773 1774 struct mlx5_ifc_ste_sx_transmit_bits { 1775 u8 entry_type[0x4]; 1776 u8 reserved_at_4[0x4]; 1777 u8 entry_sub_type[0x8]; 1778 u8 byte_mask[0x10]; 1779 1780 u8 next_table_base_63_48[0x10]; 1781 u8 next_lu_type[0x8]; 1782 u8 next_table_base_39_32_size[0x8]; 1783 1784 u8 next_table_base_31_5_size[0x1b]; 1785 u8 linear_hash_enable[0x1]; 1786 u8 reserved_at_5c[0x2]; 1787 u8 next_table_rank[0x2]; 1788 1789 u8 sx_wire[0x1]; 1790 u8 sx_func_lb[0x1]; 1791 u8 sx_sniffer[0x1]; 1792 u8 sx_wire_enable[0x1]; 1793 u8 sx_func_lb_enable[0x1]; 1794 u8 sx_sniffer_enable[0x1]; 1795 u8 action_type[0x3]; 1796 u8 reserved_at_69[0x1]; 1797 u8 action_description[0x6]; 1798 u8 gvmi[0x10]; 1799 1800 u8 encap_pointer_vlan_data[0x20]; 1801 1802 u8 loopback_syndome_en[0x8]; 1803 u8 loopback_syndome[0x8]; 1804 u8 counter_trigger[0x10]; 1805 1806 u8 miss_address_63_48[0x10]; 1807 u8 counter_trigger_23_16[0x8]; 1808 u8 miss_address_39_32[0x8]; 1809 1810 u8 miss_address_31_6[0x1a]; 1811 u8 learning_point[0x1]; 1812 u8 go_back[0x1]; 1813 u8 match_polarity[0x1]; 1814 u8 mask_mode[0x1]; 1815 u8 miss_rank[0x2]; 1816 }; 1817 1818 struct mlx5_ifc_ste_rx_steering_mult_bits { 1819 u8 entry_type[0x4]; 1820 u8 reserved_at_4[0x4]; 1821 u8 entry_sub_type[0x8]; 1822 u8 byte_mask[0x10]; 1823 1824 u8 next_table_base_63_48[0x10]; 1825 u8 next_lu_type[0x8]; 1826 u8 next_table_base_39_32_size[0x8]; 1827 1828 u8 next_table_base_31_5_size[0x1b]; 1829 u8 linear_hash_enable[0x1]; 1830 u8 reserved_at_5c[0x2]; 1831 u8 next_table_rank[0x2]; 1832 1833 u8 member_count[0x10]; 1834 u8 gvmi[0x10]; 1835 1836 u8 qp_list_pointer[0x20]; 1837 1838 u8 reserved_at_a0[0x1]; 1839 u8 tunneling_action[0x3]; 1840 u8 action_description[0x4]; 1841 u8 reserved_at_a8[0x8]; 1842 u8 counter_trigger_15_0[0x10]; 1843 1844 u8 miss_address_63_48[0x10]; 1845 u8 counter_trigger_23_16[0x08]; 1846 u8 miss_address_39_32[0x8]; 1847 1848 u8 miss_address_31_6[0x1a]; 1849 u8 learning_point[0x1]; 1850 u8 fail_on_error[0x1]; 1851 u8 match_polarity[0x1]; 1852 u8 mask_mode[0x1]; 1853 u8 miss_rank[0x2]; 1854 }; 1855 1856 struct mlx5_ifc_ste_modify_packet_bits { 1857 u8 entry_type[0x4]; 1858 u8 reserved_at_4[0x4]; 1859 u8 entry_sub_type[0x8]; 1860 u8 byte_mask[0x10]; 1861 1862 u8 next_table_base_63_48[0x10]; 1863 u8 next_lu_type[0x8]; 1864 u8 next_table_base_39_32_size[0x8]; 1865 1866 u8 next_table_base_31_5_size[0x1b]; 1867 u8 linear_hash_enable[0x1]; 1868 u8 reserved_at_5c[0x2]; 1869 u8 next_table_rank[0x2]; 1870 1871 u8 number_of_re_write_actions[0x10]; 1872 u8 gvmi[0x10]; 1873 1874 u8 header_re_write_actions_pointer[0x20]; 1875 1876 u8 reserved_at_a0[0x1]; 1877 u8 tunneling_action[0x3]; 1878 u8 action_description[0x4]; 1879 u8 reserved_at_a8[0x8]; 1880 u8 counter_trigger_15_0[0x10]; 1881 1882 u8 miss_address_63_48[0x10]; 1883 u8 counter_trigger_23_16[0x08]; 1884 u8 miss_address_39_32[0x8]; 1885 1886 u8 miss_address_31_6[0x1a]; 1887 u8 learning_point[0x1]; 1888 u8 fail_on_error[0x1]; 1889 u8 match_polarity[0x1]; 1890 u8 mask_mode[0x1]; 1891 u8 miss_rank[0x2]; 1892 }; 1893 1894 struct mlx5_ifc_ste_single_action_flow_tag_v1_bits { 1895 u8 action_id[0x8]; 1896 u8 flow_tag[0x18]; 1897 }; 1898 1899 struct mlx5_ifc_ste_single_action_modify_list_v1_bits { 1900 u8 action_id[0x8]; 1901 u8 num_of_modify_actions[0x8]; 1902 u8 modify_actions_ptr[0x10]; 1903 }; 1904 1905 struct mlx5_ifc_ste_single_action_remove_header_v1_bits { 1906 u8 action_id[0x8]; 1907 u8 reserved_at_8[0x2]; 1908 u8 start_anchor[0x6]; 1909 u8 reserved_at_10[0x2]; 1910 u8 end_anchor[0x6]; 1911 u8 reserved_at_18[0x4]; 1912 u8 decap[0x1]; 1913 u8 vni_to_cqe[0x1]; 1914 u8 qos_profile[0x2]; 1915 }; 1916 1917 struct mlx5_ifc_ste_single_action_remove_header_size_v1_bits { 1918 u8 action_id[0x8]; 1919 u8 reserved_at_8[0x2]; 1920 u8 start_anchor[0x6]; 1921 u8 outer_l4_remove[0x1]; 1922 u8 reserved_at_11[0x1]; 1923 u8 start_offset[0x7]; 1924 u8 reserved_at_18[0x1]; 1925 u8 remove_size[0x6]; 1926 }; 1927 1928 struct mlx5_ifc_ste_double_action_copy_v1_bits { 1929 u8 action_id[0x8]; 1930 u8 destination_dw_offset[0x8]; 1931 u8 reserved_at_10[0x2]; 1932 u8 destination_left_shifter[0x6]; 1933 u8 reserved_at_18[0x2]; 1934 u8 destination_length[0x6]; 1935 1936 u8 reserved_at_20[0x8]; 1937 u8 source_dw_offset[0x8]; 1938 u8 reserved_at_30[0x2]; 1939 u8 source_right_shifter[0x6]; 1940 u8 reserved_at_38[0x8]; 1941 }; 1942 1943 struct mlx5_ifc_ste_double_action_set_v1_bits { 1944 u8 action_id[0x8]; 1945 u8 destination_dw_offset[0x8]; 1946 u8 reserved_at_10[0x2]; 1947 u8 destination_left_shifter[0x6]; 1948 u8 reserved_at_18[0x2]; 1949 u8 destination_length[0x6]; 1950 1951 u8 inline_data[0x20]; 1952 }; 1953 1954 struct mlx5_ifc_ste_double_action_add_v1_bits { 1955 u8 action_id[0x8]; 1956 u8 destination_dw_offset[0x8]; 1957 u8 reserved_at_10[0x2]; 1958 u8 destination_left_shifter[0x6]; 1959 u8 reserved_at_18[0x2]; 1960 u8 destination_length[0x6]; 1961 1962 u8 add_value[0x20]; 1963 }; 1964 1965 struct mlx5_ifc_ste_double_action_insert_with_inline_v1_bits { 1966 u8 action_id[0x8]; 1967 u8 reserved_at_8[0x2]; 1968 u8 start_anchor[0x6]; 1969 u8 start_offset[0x7]; 1970 u8 reserved_at_17[0x9]; 1971 1972 u8 inline_data[0x20]; 1973 }; 1974 1975 struct mlx5_ifc_ste_double_action_insert_with_ptr_v1_bits { 1976 u8 action_id[0x8]; 1977 u8 reserved_at_8[0x2]; 1978 u8 start_anchor[0x6]; 1979 u8 start_offset[0x7]; 1980 u8 size[0x6]; 1981 u8 attributes[0x3]; 1982 1983 u8 pointer[0x20]; 1984 }; 1985 1986 struct mlx5_ifc_ste_double_action_accelerated_modify_action_list_v1_bits { 1987 u8 action_id[0x8]; 1988 u8 modify_actions_pattern_pointer[0x18]; 1989 1990 u8 number_of_modify_actions[0x8]; 1991 u8 modify_actions_argument_pointer[0x18]; 1992 }; 1993 1994 enum { 1995 MLX5_IFC_ASO_FLOW_METER_INITIAL_COLOR_RED = 0x0, 1996 MLX5_IFC_ASO_FLOW_METER_INITIAL_COLOR_YELLOW = 0x1, 1997 MLX5_IFC_ASO_FLOW_METER_INITIAL_COLOR_GREEN = 0x2, 1998 MLX5_IFC_ASO_FLOW_METER_INITIAL_COLOR_UNDEFINED = 0x3, 1999 }; 2000 2001 enum { 2002 MLX5_IFC_ASO_CT_DIRECTION_INITIATOR = 0x0, 2003 MLX5_IFC_ASO_CT_DIRECTION_RESPONDER = 0x1, 2004 }; 2005 2006 struct mlx5_ifc_ste_aso_first_hit_action_v1_bits { 2007 u8 reserved_at_0[0x6]; 2008 u8 set[0x1]; 2009 u8 line_id[0x9]; 2010 }; 2011 2012 struct mlx5_ifc_ste_aso_flow_meter_action_v1_bits { 2013 u8 reserved_at_0[0xc]; 2014 u8 action[0x1]; 2015 u8 initial_color[0x2]; 2016 u8 line_id[0x1]; 2017 }; 2018 2019 struct mlx5_ifc_ste_aso_ct_action_v1_bits { 2020 u8 reserved_at_0[0xf]; 2021 u8 direction[0x1]; 2022 }; 2023 2024 struct mlx5_ifc_ste_double_action_aso_v1_bits { 2025 u8 action_id[0x8]; 2026 u8 aso_context_number[0x18]; 2027 2028 u8 dest_reg_id[0x2]; 2029 u8 change_ordering_tag[0x1]; 2030 u8 aso_check_ordering[0x1]; 2031 u8 aso_context_type[0x4]; 2032 u8 reserved_at_28[0x8]; 2033 union { 2034 u8 aso_fields[0x10]; 2035 struct mlx5_ifc_ste_aso_first_hit_action_v1_bits first_hit; 2036 struct mlx5_ifc_ste_aso_flow_meter_action_v1_bits flow_meter; 2037 struct mlx5_ifc_ste_aso_ct_action_v1_bits ct; 2038 }; 2039 }; 2040 2041 struct mlx5_ifc_ste_match_bwc_v1_bits { 2042 u8 entry_format[0x8]; 2043 u8 counter_id[0x18]; 2044 2045 u8 miss_address_63_48[0x10]; 2046 u8 match_definer_ctx_idx[0x8]; 2047 u8 miss_address_39_32[0x8]; 2048 2049 u8 miss_address_31_6[0x1a]; 2050 u8 reserved_at_5a[0x1]; 2051 u8 match_polarity[0x1]; 2052 u8 reparse[0x1]; 2053 u8 reserved_at_5d[0x3]; 2054 2055 u8 next_table_base_63_48[0x10]; 2056 u8 hash_definer_ctx_idx[0x8]; 2057 u8 next_table_base_39_32_size[0x8]; 2058 2059 u8 next_table_base_31_5_size[0x1b]; 2060 u8 hash_type[0x2]; 2061 u8 hash_after_actions[0x1]; 2062 u8 reserved_at_9e[0x2]; 2063 2064 u8 byte_mask[0x10]; 2065 u8 next_entry_format[0x1]; 2066 u8 mask_mode[0x1]; 2067 u8 gvmi[0xe]; 2068 2069 u8 action[0x40]; 2070 }; 2071 2072 struct mlx5_ifc_ste_mask_and_match_v1_bits { 2073 u8 entry_format[0x8]; 2074 u8 counter_id[0x18]; 2075 2076 u8 miss_address_63_48[0x10]; 2077 u8 match_definer_ctx_idx[0x8]; 2078 u8 miss_address_39_32[0x8]; 2079 2080 u8 miss_address_31_6[0x1a]; 2081 u8 reserved_at_5a[0x1]; 2082 u8 match_polarity[0x1]; 2083 u8 reparse[0x1]; 2084 u8 reserved_at_5d[0x3]; 2085 2086 u8 next_table_base_63_48[0x10]; 2087 u8 hash_definer_ctx_idx[0x8]; 2088 u8 next_table_base_39_32_size[0x8]; 2089 2090 u8 next_table_base_31_5_size[0x1b]; 2091 u8 hash_type[0x2]; 2092 u8 hash_after_actions[0x1]; 2093 u8 reserved_at_9e[0x2]; 2094 2095 u8 action[0x60]; 2096 }; 2097 2098 struct mlx5_ifc_ste_eth_l2_src_bits { 2099 u8 smac_47_16[0x20]; 2100 2101 u8 smac_15_0[0x10]; 2102 u8 l3_ethertype[0x10]; 2103 2104 u8 qp_type[0x2]; 2105 u8 ethertype_filter[0x1]; 2106 u8 reserved_at_43[0x1]; 2107 u8 sx_sniffer[0x1]; 2108 u8 force_lb[0x1]; 2109 u8 functional_lb[0x1]; 2110 u8 port[0x1]; 2111 u8 reserved_at_48[0x4]; 2112 u8 first_priority[0x3]; 2113 u8 first_cfi[0x1]; 2114 u8 first_vlan_qualifier[0x2]; 2115 u8 reserved_at_52[0x2]; 2116 u8 first_vlan_id[0xc]; 2117 2118 u8 ip_fragmented[0x1]; 2119 u8 tcp_syn[0x1]; 2120 u8 encp_type[0x2]; 2121 u8 l3_type[0x2]; 2122 u8 l4_type[0x2]; 2123 u8 reserved_at_68[0x4]; 2124 u8 second_priority[0x3]; 2125 u8 second_cfi[0x1]; 2126 u8 second_vlan_qualifier[0x2]; 2127 u8 reserved_at_72[0x2]; 2128 u8 second_vlan_id[0xc]; 2129 }; 2130 2131 struct mlx5_ifc_ste_eth_l2_src_v1_bits { 2132 u8 reserved_at_0[0x1]; 2133 u8 sx_sniffer[0x1]; 2134 u8 functional_loopback[0x1]; 2135 u8 ip_fragmented[0x1]; 2136 u8 qp_type[0x2]; 2137 u8 encapsulation_type[0x2]; 2138 u8 port[0x2]; 2139 u8 l3_type[0x2]; 2140 u8 l4_type[0x2]; 2141 u8 first_vlan_qualifier[0x2]; 2142 u8 first_priority[0x3]; 2143 u8 first_cfi[0x1]; 2144 u8 first_vlan_id[0xc]; 2145 2146 u8 smac_47_16[0x20]; 2147 2148 u8 smac_15_0[0x10]; 2149 u8 l3_ethertype[0x10]; 2150 2151 u8 reserved_at_60[0x6]; 2152 u8 tcp_syn[0x1]; 2153 u8 reserved_at_67[0x3]; 2154 u8 force_loopback[0x1]; 2155 u8 l2_ok[0x1]; 2156 u8 l3_ok[0x1]; 2157 u8 l4_ok[0x1]; 2158 u8 second_vlan_qualifier[0x2]; 2159 u8 second_priority[0x3]; 2160 u8 second_cfi[0x1]; 2161 u8 second_vlan_id[0xc]; 2162 }; 2163 2164 struct mlx5_ifc_ste_eth_l2_dst_bits { 2165 u8 dmac_47_16[0x20]; 2166 2167 u8 dmac_15_0[0x10]; 2168 u8 l3_ethertype[0x10]; 2169 2170 u8 qp_type[0x2]; 2171 u8 ethertype_filter[0x1]; 2172 u8 reserved_at_43[0x1]; 2173 u8 sx_sniffer[0x1]; 2174 u8 force_lb[0x1]; 2175 u8 functional_lb[0x1]; 2176 u8 port[0x1]; 2177 u8 reserved_at_48[0x4]; 2178 u8 first_priority[0x3]; 2179 u8 first_cfi[0x1]; 2180 u8 first_vlan_qualifier[0x2]; 2181 u8 reserved_at_52[0x2]; 2182 u8 first_vlan_id[0xc]; 2183 2184 u8 ip_fragmented[0x1]; 2185 u8 tcp_syn[0x1]; 2186 u8 encp_type[0x2]; 2187 u8 l3_type[0x2]; 2188 u8 l4_type[0x2]; 2189 u8 reserved_at_68[0x4]; 2190 u8 second_priority[0x3]; 2191 u8 second_cfi[0x1]; 2192 u8 second_vlan_qualifier[0x2]; 2193 u8 reserved_at_72[0x2]; 2194 u8 second_vlan_id[0xc]; 2195 }; 2196 2197 struct mlx5_ifc_ste_eth_l2_dst_v1_bits { 2198 u8 reserved_at_0[0x1]; 2199 u8 sx_sniffer[0x1]; 2200 u8 functional_lb[0x1]; 2201 u8 ip_fragmented[0x1]; 2202 u8 qp_type[0x2]; 2203 u8 encapsulation_type[0x2]; 2204 u8 port[0x2]; 2205 u8 l3_type[0x2]; 2206 u8 l4_type[0x2]; 2207 u8 first_vlan_qualifier[0x2]; 2208 u8 first_priority[0x3]; 2209 u8 first_cfi[0x1]; 2210 u8 first_vlan_id[0xc]; 2211 2212 u8 dmac_47_16[0x20]; 2213 2214 u8 dmac_15_0[0x10]; 2215 u8 l3_ethertype[0x10]; 2216 2217 u8 reserved_at_60[0x6]; 2218 u8 tcp_syn[0x1]; 2219 u8 reserved_at_67[0x3]; 2220 u8 force_lb[0x1]; 2221 u8 l2_ok[0x1]; 2222 u8 l3_ok[0x1]; 2223 u8 l4_ok[0x1]; 2224 u8 second_vlan_qualifier[0x2]; 2225 u8 second_priority[0x3]; 2226 u8 second_cfi[0x1]; 2227 u8 second_vlan_id[0xc]; 2228 }; 2229 2230 struct mlx5_ifc_ste_eth_l2_src_dst_bits { 2231 u8 dmac_47_16[0x20]; 2232 2233 u8 dmac_15_0[0x10]; 2234 u8 smac_47_32[0x10]; 2235 2236 u8 smac_31_0[0x20]; 2237 2238 u8 sx_sniffer[0x1]; 2239 u8 force_lb[0x1]; 2240 u8 functional_lb[0x1]; 2241 u8 port[0x1]; 2242 u8 l3_type[0x2]; 2243 u8 reserved_at_66[0x6]; 2244 u8 first_priority[0x3]; 2245 u8 first_cfi[0x1]; 2246 u8 first_vlan_qualifier[0x2]; 2247 u8 reserved_at_72[0x2]; 2248 u8 first_vlan_id[0xc]; 2249 }; 2250 2251 struct mlx5_ifc_ste_eth_l2_src_dst_v1_bits { 2252 u8 dmac_47_16[0x20]; 2253 2254 u8 smac_47_16[0x20]; 2255 2256 u8 dmac_15_0[0x10]; 2257 u8 reserved_at_50[0x2]; 2258 u8 functional_lb[0x1]; 2259 u8 reserved_at_53[0x5]; 2260 u8 port[0x2]; 2261 u8 l3_type[0x2]; 2262 u8 reserved_at_5c[0x2]; 2263 u8 first_vlan_qualifier[0x2]; 2264 2265 u8 first_priority[0x3]; 2266 u8 first_cfi[0x1]; 2267 u8 first_vlan_id[0xc]; 2268 u8 smac_15_0[0x10]; 2269 }; 2270 2271 struct mlx5_ifc_ste_eth_l3_ipv4_5_tuple_bits { 2272 u8 destination_address[0x20]; 2273 2274 u8 source_address[0x20]; 2275 2276 u8 source_port[0x10]; 2277 u8 destination_port[0x10]; 2278 2279 u8 fragmented[0x1]; 2280 u8 first_fragment[0x1]; 2281 u8 reserved_at_62[0x2]; 2282 u8 reserved_at_64[0x1]; 2283 u8 ecn[0x2]; 2284 u8 tcp_ns[0x1]; 2285 u8 tcp_cwr[0x1]; 2286 u8 tcp_ece[0x1]; 2287 u8 tcp_urg[0x1]; 2288 u8 tcp_ack[0x1]; 2289 u8 tcp_psh[0x1]; 2290 u8 tcp_rst[0x1]; 2291 u8 tcp_syn[0x1]; 2292 u8 tcp_fin[0x1]; 2293 u8 dscp[0x6]; 2294 u8 reserved_at_76[0x2]; 2295 u8 protocol[0x8]; 2296 }; 2297 2298 struct mlx5_ifc_ste_eth_l3_ipv4_5_tuple_v1_bits { 2299 u8 source_address[0x20]; 2300 2301 u8 destination_address[0x20]; 2302 2303 u8 source_port[0x10]; 2304 u8 destination_port[0x10]; 2305 2306 u8 reserved_at_60[0x4]; 2307 u8 l4_ok[0x1]; 2308 u8 l3_ok[0x1]; 2309 u8 fragmented[0x1]; 2310 u8 tcp_ns[0x1]; 2311 u8 tcp_cwr[0x1]; 2312 u8 tcp_ece[0x1]; 2313 u8 tcp_urg[0x1]; 2314 u8 tcp_ack[0x1]; 2315 u8 tcp_psh[0x1]; 2316 u8 tcp_rst[0x1]; 2317 u8 tcp_syn[0x1]; 2318 u8 tcp_fin[0x1]; 2319 u8 dscp[0x6]; 2320 u8 ecn[0x2]; 2321 u8 protocol[0x8]; 2322 }; 2323 2324 struct mlx5_ifc_ste_eth_l3_ipv6_dst_bits { 2325 u8 dst_ip_127_96[0x20]; 2326 2327 u8 dst_ip_95_64[0x20]; 2328 2329 u8 dst_ip_63_32[0x20]; 2330 2331 u8 dst_ip_31_0[0x20]; 2332 }; 2333 2334 struct mlx5_ifc_ste_eth_l2_tnl_bits { 2335 u8 dmac_47_16[0x20]; 2336 2337 u8 dmac_15_0[0x10]; 2338 u8 l3_ethertype[0x10]; 2339 2340 u8 l2_tunneling_network_id[0x20]; 2341 2342 u8 ip_fragmented[0x1]; 2343 u8 tcp_syn[0x1]; 2344 u8 encp_type[0x2]; 2345 u8 l3_type[0x2]; 2346 u8 l4_type[0x2]; 2347 u8 first_priority[0x3]; 2348 u8 first_cfi[0x1]; 2349 u8 reserved_at_6c[0x3]; 2350 u8 gre_key_flag[0x1]; 2351 u8 first_vlan_qualifier[0x2]; 2352 u8 reserved_at_72[0x2]; 2353 u8 first_vlan_id[0xc]; 2354 }; 2355 2356 struct mlx5_ifc_ste_eth_l2_tnl_v1_bits { 2357 u8 l2_tunneling_network_id[0x20]; 2358 2359 u8 dmac_47_16[0x20]; 2360 2361 u8 dmac_15_0[0x10]; 2362 u8 l3_ethertype[0x10]; 2363 2364 u8 reserved_at_60[0x3]; 2365 u8 ip_fragmented[0x1]; 2366 u8 reserved_at_64[0x2]; 2367 u8 encp_type[0x2]; 2368 u8 reserved_at_68[0x2]; 2369 u8 l3_type[0x2]; 2370 u8 l4_type[0x2]; 2371 u8 first_vlan_qualifier[0x2]; 2372 u8 first_priority[0x3]; 2373 u8 first_cfi[0x1]; 2374 u8 first_vlan_id[0xc]; 2375 }; 2376 2377 struct mlx5_ifc_ste_eth_l3_ipv6_src_bits { 2378 u8 src_ip_127_96[0x20]; 2379 2380 u8 src_ip_95_64[0x20]; 2381 2382 u8 src_ip_63_32[0x20]; 2383 2384 u8 src_ip_31_0[0x20]; 2385 }; 2386 2387 struct mlx5_ifc_ste_eth_l3_ipv4_misc_bits { 2388 u8 version[0x4]; 2389 u8 ihl[0x4]; 2390 u8 reserved_at_8[0x8]; 2391 u8 total_length[0x10]; 2392 2393 u8 identification[0x10]; 2394 u8 flags[0x3]; 2395 u8 fragment_offset[0xd]; 2396 2397 u8 time_to_live[0x8]; 2398 u8 reserved_at_48[0x8]; 2399 u8 checksum[0x10]; 2400 2401 u8 reserved_at_60[0x20]; 2402 }; 2403 2404 struct mlx5_ifc_ste_eth_l3_ipv4_misc_v1_bits { 2405 u8 identification[0x10]; 2406 u8 flags[0x3]; 2407 u8 fragment_offset[0xd]; 2408 2409 u8 total_length[0x10]; 2410 u8 checksum[0x10]; 2411 2412 u8 version[0x4]; 2413 u8 ihl[0x4]; 2414 u8 time_to_live[0x8]; 2415 u8 reserved_at_50[0x10]; 2416 2417 u8 reserved_at_60[0x1c]; 2418 u8 voq_internal_prio[0x4]; 2419 }; 2420 2421 struct mlx5_ifc_ste_eth_l4_bits { 2422 u8 fragmented[0x1]; 2423 u8 first_fragment[0x1]; 2424 u8 reserved_at_2[0x6]; 2425 u8 protocol[0x8]; 2426 u8 dst_port[0x10]; 2427 2428 u8 ipv6_version[0x4]; 2429 u8 reserved_at_24[0x1]; 2430 u8 ecn[0x2]; 2431 u8 tcp_ns[0x1]; 2432 u8 tcp_cwr[0x1]; 2433 u8 tcp_ece[0x1]; 2434 u8 tcp_urg[0x1]; 2435 u8 tcp_ack[0x1]; 2436 u8 tcp_psh[0x1]; 2437 u8 tcp_rst[0x1]; 2438 u8 tcp_syn[0x1]; 2439 u8 tcp_fin[0x1]; 2440 u8 src_port[0x10]; 2441 2442 u8 ipv6_payload_length[0x10]; 2443 u8 ipv6_hop_limit[0x8]; 2444 u8 dscp[0x6]; 2445 u8 reserved_at_5e[0x2]; 2446 2447 u8 tcp_data_offset[0x4]; 2448 u8 reserved_at_64[0x8]; 2449 u8 flow_label[0x14]; 2450 }; 2451 2452 struct mlx5_ifc_ste_eth_l4_v1_bits { 2453 u8 ipv6_version[0x4]; 2454 u8 reserved_at_4[0x4]; 2455 u8 dscp[0x6]; 2456 u8 ecn[0x2]; 2457 u8 ipv6_hop_limit[0x8]; 2458 u8 protocol[0x8]; 2459 2460 u8 src_port[0x10]; 2461 u8 dst_port[0x10]; 2462 2463 u8 first_fragment[0x1]; 2464 u8 reserved_at_41[0xb]; 2465 u8 flow_label[0x14]; 2466 2467 u8 tcp_data_offset[0x4]; 2468 u8 l4_ok[0x1]; 2469 u8 l3_ok[0x1]; 2470 u8 fragmented[0x1]; 2471 u8 tcp_ns[0x1]; 2472 u8 tcp_cwr[0x1]; 2473 u8 tcp_ece[0x1]; 2474 u8 tcp_urg[0x1]; 2475 u8 tcp_ack[0x1]; 2476 u8 tcp_psh[0x1]; 2477 u8 tcp_rst[0x1]; 2478 u8 tcp_syn[0x1]; 2479 u8 tcp_fin[0x1]; 2480 u8 ipv6_paylen[0x10]; 2481 }; 2482 2483 struct mlx5_ifc_ste_eth_l4_misc_bits { 2484 u8 checksum[0x10]; 2485 u8 length[0x10]; 2486 2487 u8 seq_num[0x20]; 2488 2489 u8 ack_num[0x20]; 2490 2491 u8 urgent_pointer[0x10]; 2492 u8 window_size[0x10]; 2493 }; 2494 2495 struct mlx5_ifc_ste_eth_l4_misc_v1_bits { 2496 u8 window_size[0x10]; 2497 u8 urgent_pointer[0x10]; 2498 2499 u8 ack_num[0x20]; 2500 2501 u8 seq_num[0x20]; 2502 2503 u8 length[0x10]; 2504 u8 checksum[0x10]; 2505 }; 2506 2507 struct mlx5_ifc_ste_mpls_bits { 2508 u8 mpls0_label[0x14]; 2509 u8 mpls0_exp[0x3]; 2510 u8 mpls0_s_bos[0x1]; 2511 u8 mpls0_ttl[0x8]; 2512 2513 u8 mpls1_label[0x20]; 2514 2515 u8 mpls2_label[0x20]; 2516 2517 u8 reserved_at_60[0x16]; 2518 u8 mpls4_s_bit[0x1]; 2519 u8 mpls4_qualifier[0x1]; 2520 u8 mpls3_s_bit[0x1]; 2521 u8 mpls3_qualifier[0x1]; 2522 u8 mpls2_s_bit[0x1]; 2523 u8 mpls2_qualifier[0x1]; 2524 u8 mpls1_s_bit[0x1]; 2525 u8 mpls1_qualifier[0x1]; 2526 u8 mpls0_s_bit[0x1]; 2527 u8 mpls0_qualifier[0x1]; 2528 }; 2529 2530 struct mlx5_ifc_ste_mpls_v1_bits { 2531 u8 reserved_at_0[0x15]; 2532 u8 mpls_ok[0x1]; 2533 u8 mpls4_s_bit[0x1]; 2534 u8 mpls4_qualifier[0x1]; 2535 u8 mpls3_s_bit[0x1]; 2536 u8 mpls3_qualifier[0x1]; 2537 u8 mpls2_s_bit[0x1]; 2538 u8 mpls2_qualifier[0x1]; 2539 u8 mpls1_s_bit[0x1]; 2540 u8 mpls1_qualifier[0x1]; 2541 u8 mpls0_s_bit[0x1]; 2542 u8 mpls0_qualifier[0x1]; 2543 2544 u8 mpls0_label[0x14]; 2545 u8 mpls0_exp[0x3]; 2546 u8 mpls0_s_bos[0x1]; 2547 u8 mpls0_ttl[0x8]; 2548 2549 u8 mpls1_label[0x20]; 2550 2551 u8 mpls2_label[0x20]; 2552 }; 2553 2554 struct mlx5_ifc_ste_register_0_bits { 2555 u8 register_0_h[0x20]; 2556 2557 u8 register_0_l[0x20]; 2558 2559 u8 register_1_h[0x20]; 2560 2561 u8 register_1_l[0x20]; 2562 }; 2563 2564 struct mlx5_ifc_ste_register_1_bits { 2565 u8 register_2_h[0x20]; 2566 2567 u8 register_2_l[0x20]; 2568 2569 u8 register_3_h[0x20]; 2570 2571 u8 register_3_l[0x20]; 2572 }; 2573 2574 struct mlx5_ifc_ste_gre_bits { 2575 u8 gre_c_present[0x1]; 2576 u8 reserved_at_1[0x1]; 2577 u8 gre_k_present[0x1]; 2578 u8 gre_s_present[0x1]; 2579 u8 strict_src_route[0x1]; 2580 u8 recur[0x3]; 2581 u8 flags[0x5]; 2582 u8 version[0x3]; 2583 u8 gre_protocol[0x10]; 2584 2585 u8 checksum[0x10]; 2586 u8 offset[0x10]; 2587 2588 u8 gre_key_h[0x18]; 2589 u8 gre_key_l[0x8]; 2590 2591 u8 seq_num[0x20]; 2592 }; 2593 2594 struct mlx5_ifc_ste_gre_v1_bits { 2595 u8 gre_c_present[0x1]; 2596 u8 reserved_at_1[0x1]; 2597 u8 gre_k_present[0x1]; 2598 u8 gre_s_present[0x1]; 2599 u8 strict_src_route[0x1]; 2600 u8 recur[0x3]; 2601 u8 flags[0x5]; 2602 u8 version[0x3]; 2603 u8 gre_protocol[0x10]; 2604 2605 u8 reserved_at_20[0x20]; 2606 2607 u8 gre_key_h[0x18]; 2608 u8 gre_key_l[0x8]; 2609 2610 u8 reserved_at_60[0x20]; 2611 }; 2612 2613 struct mlx5_ifc_ste_flex_parser_0_bits { 2614 u8 flex_parser_3[0x20]; 2615 2616 u8 flex_parser_2[0x20]; 2617 2618 u8 flex_parser_1[0x20]; 2619 2620 u8 flex_parser_0[0x20]; 2621 }; 2622 2623 struct mlx5_ifc_ste_flex_parser_1_bits { 2624 u8 flex_parser_7[0x20]; 2625 2626 u8 flex_parser_6[0x20]; 2627 2628 u8 flex_parser_5[0x20]; 2629 2630 u8 flex_parser_4[0x20]; 2631 }; 2632 2633 struct mlx5_ifc_ste_flex_parser_ok_bits { 2634 u8 flex_parser_3[0x20]; 2635 2636 u8 flex_parser_2[0x20]; 2637 2638 u8 flex_parsers_ok[0x8]; 2639 u8 reserved_at_48[0x18]; 2640 2641 u8 flex_parser_0[0x20]; 2642 }; 2643 2644 struct mlx5_ifc_ste_tunnel_header_bits { 2645 u8 tunnel_header_dw0[0x20]; 2646 2647 u8 tunnel_header_dw1[0x20]; 2648 2649 u8 reserved_at_40[0x40]; 2650 }; 2651 2652 struct mlx5_ifc_ste_tunnel_header_v1_bits { 2653 u8 tunnel_header_0[0x20]; 2654 2655 u8 tunnel_header_1[0x20]; 2656 2657 u8 tunnel_header_2[0x20]; 2658 2659 u8 tunnel_header_3[0x20]; 2660 }; 2661 2662 struct mlx5_ifc_ste_flex_parser_tnl_vxlan_gpe_bits { 2663 u8 outer_vxlan_gpe_flags[0x8]; 2664 u8 reserved_at_8[0x10]; 2665 u8 outer_vxlan_gpe_next_protocol[0x8]; 2666 2667 u8 outer_vxlan_gpe_vni[0x18]; 2668 u8 reserved_at_38[0x8]; 2669 2670 u8 reserved_at_40[0x40]; 2671 }; 2672 2673 struct mlx5_ifc_ste_flex_parser_tnl_geneve_bits { 2674 u8 reserved_at_0[0x2]; 2675 u8 geneve_opt_len[0x6]; 2676 u8 geneve_oam[0x1]; 2677 u8 reserved_at_9[0x7]; 2678 u8 geneve_protocol_type[0x10]; 2679 2680 u8 geneve_vni[0x18]; 2681 u8 reserved_at_38[0x8]; 2682 2683 u8 reserved_at_40[0x40]; 2684 }; 2685 2686 struct mlx5_ifc_ste_flex_parser_tnl_gtpu_bits { 2687 u8 gtpu_msg_flags[0x8]; 2688 u8 gtpu_msg_type[0x8]; 2689 u8 reserved_at_10[0x10]; 2690 2691 u8 gtpu_teid[0x20]; 2692 2693 u8 reserved_at_40[0x40]; 2694 }; 2695 2696 struct mlx5_ifc_ste_general_purpose_bits { 2697 u8 general_purpose_lookup_field[0x20]; 2698 2699 u8 reserved_at_20[0x20]; 2700 2701 u8 reserved_at_40[0x20]; 2702 2703 u8 reserved_at_60[0x20]; 2704 }; 2705 2706 struct mlx5_ifc_ste_src_gvmi_qp_bits { 2707 u8 loopback_syndrome[0x8]; 2708 u8 reserved_at_8[0x8]; 2709 u8 source_gvmi[0x10]; 2710 2711 u8 reserved_at_20[0x5]; 2712 u8 force_lb[0x1]; 2713 u8 functional_lb[0x1]; 2714 u8 source_is_requestor[0x1]; 2715 u8 source_qp[0x18]; 2716 2717 u8 reserved_at_40[0x20]; 2718 2719 u8 reserved_at_60[0x20]; 2720 }; 2721 2722 struct mlx5_ifc_ste_src_gvmi_qp_v1_bits { 2723 u8 loopback_synd[0x8]; 2724 u8 reserved_at_8[0x7]; 2725 u8 functional_lb[0x1]; 2726 u8 source_gvmi[0x10]; 2727 2728 u8 force_lb[0x1]; 2729 u8 reserved_at_21[0x1]; 2730 u8 source_is_requestor[0x1]; 2731 u8 reserved_at_23[0x5]; 2732 u8 source_qp[0x18]; 2733 2734 u8 reserved_at_40[0x20]; 2735 2736 u8 reserved_at_60[0x20]; 2737 }; 2738 2739 struct mlx5_ifc_ste_icmp_v1_bits { 2740 u8 icmp_payload_data[0x20]; 2741 2742 u8 icmp_header_data[0x20]; 2743 2744 u8 icmp_type[0x8]; 2745 u8 icmp_code[0x8]; 2746 u8 reserved_at_50[0x10]; 2747 2748 u8 reserved_at_60[0x20]; 2749 }; 2750 2751 struct mlx5_ifc_ste_ib_l4_bits { 2752 u8 opcode[0x8]; 2753 u8 qp[0x18]; 2754 2755 u8 se[0x1]; 2756 u8 migreg[0x1]; 2757 u8 ackreq[0x1]; 2758 u8 fecn[0x1]; 2759 u8 becn[0x1]; 2760 u8 bth[0x1]; 2761 u8 deth[0x1]; 2762 u8 dcceth[0x1]; 2763 u8 reserved_at_28[0x2]; 2764 u8 pad_count[0x2]; 2765 u8 tver[0x4]; 2766 u8 pkey[0x10]; 2767 2768 u8 reserved_at_40[0x8]; 2769 u8 deth_source_qp[0x18]; 2770 2771 u8 reserved_at_60[0x20]; 2772 }; 2773 2774 struct mlx5_ifc_ste_def0_v1_bits { 2775 u8 metadata_reg_c_0[0x20]; 2776 2777 u8 metadata_reg_c_1[0x20]; 2778 2779 u8 dmac_47_16[0x20]; 2780 2781 u8 dmac_15_0[0x10]; 2782 u8 ethertype[0x10]; 2783 2784 u8 reserved_at_60[0x1]; 2785 u8 sx_sniffer[0x1]; 2786 u8 functional_loopback[0x1]; 2787 u8 ip_frag[0x1]; 2788 u8 qp_type[0x2]; 2789 u8 encapsulation_type[0x2]; 2790 u8 port[0x2]; 2791 u8 outer_l3_type[0x2]; 2792 u8 outer_l4_type[0x2]; 2793 u8 first_vlan_qualifier[0x2]; 2794 u8 first_priority[0x3]; 2795 u8 first_cfi[0x1]; 2796 u8 first_vlan_id[0xc]; 2797 2798 u8 reserved_at_80[0xa]; 2799 u8 force_loopback[0x1]; 2800 u8 reserved_at_8b[0x3]; 2801 u8 second_vlan_qualifier[0x2]; 2802 u8 second_priority[0x3]; 2803 u8 second_cfi[0x1]; 2804 u8 second_vlan_id[0xc]; 2805 2806 u8 smac_47_16[0x20]; 2807 2808 u8 smac_15_0[0x10]; 2809 u8 inner_ipv4_checksum_ok[0x1]; 2810 u8 inner_l4_checksum_ok[0x1]; 2811 u8 outer_ipv4_checksum_ok[0x1]; 2812 u8 outer_l4_checksum_ok[0x1]; 2813 u8 inner_l3_ok[0x1]; 2814 u8 inner_l4_ok[0x1]; 2815 u8 outer_l3_ok[0x1]; 2816 u8 outer_l4_ok[0x1]; 2817 u8 tcp_cwr[0x1]; 2818 u8 tcp_ece[0x1]; 2819 u8 tcp_urg[0x1]; 2820 u8 tcp_ack[0x1]; 2821 u8 tcp_psh[0x1]; 2822 u8 tcp_rst[0x1]; 2823 u8 tcp_syn[0x1]; 2824 u8 tcp_fin[0x1]; 2825 }; 2826 2827 struct mlx5_ifc_ste_def2_v1_bits { 2828 u8 metadata_reg_a[0x20]; 2829 2830 u8 outer_ip_version[0x4]; 2831 u8 outer_ip_ihl[0x4]; 2832 u8 outer_ip_dscp[0x6]; 2833 u8 outer_ip_ecn[0x2]; 2834 u8 outer_ip_ttl[0x8]; 2835 u8 outer_ip_protocol[0x8]; 2836 2837 u8 outer_ip_identification[0x10]; 2838 u8 outer_ip_flags[0x3]; 2839 u8 outer_ip_fragment_offset[0xd]; 2840 2841 u8 outer_ip_total_length[0x10]; 2842 u8 outer_ip_checksum[0x10]; 2843 2844 u8 reserved_180[0xc]; 2845 u8 outer_ip_flow_label[0x14]; 2846 2847 u8 outer_eth_packet_length[0x10]; 2848 u8 outer_ip_payload_length[0x10]; 2849 2850 u8 outer_l4_sport[0x10]; 2851 u8 outer_l4_dport[0x10]; 2852 2853 u8 outer_data_offset[0x4]; 2854 u8 reserved_1e4[0x2]; 2855 u8 outer_ip_frag[0x1]; 2856 u8 tcp_ns[0x1]; 2857 u8 tcp_cwr[0x1]; 2858 u8 tcp_ece[0x1]; 2859 u8 tcp_urg[0x1]; 2860 u8 tcp_ack[0x1]; 2861 u8 tcp_psh[0x1]; 2862 u8 tcp_rst[0x1]; 2863 u8 tcp_syn[0x1]; 2864 u8 tcp_fin[0x1]; 2865 u8 outer_ip_frag_first[0x1]; 2866 u8 reserved_1f0[0x7]; 2867 u8 inner_ipv4_checksum_ok[0x1]; 2868 u8 inner_l4_checksum_ok[0x1]; 2869 u8 outer_ipv4_checksum_ok[0x1]; 2870 u8 outer_l4_checksum_ok[0x1]; 2871 u8 inner_l3_ok[0x1]; 2872 u8 inner_l4_ok[0x1]; 2873 u8 outer_l3_ok[0x1]; 2874 u8 outer_l4_ok[0x1]; 2875 }; 2876 2877 struct mlx5_ifc_ste_def6_v1_bits { 2878 u8 dst_ipv6_127_96[0x20]; 2879 2880 u8 dst_ipv6_95_64[0x20]; 2881 2882 u8 dst_ipv6_63_32[0x20]; 2883 2884 u8 dst_ipv6_31_0[0x20]; 2885 2886 u8 reserved_at_80[0x40]; 2887 2888 u8 outer_l4_sport[0x10]; 2889 u8 outer_l4_dport[0x10]; 2890 2891 u8 reserved_e0[0x4]; 2892 u8 l4_ok[0x1]; 2893 u8 l3_ok[0x1]; 2894 u8 ip_frag[0x1]; 2895 u8 tcp_ns[0x1]; 2896 u8 tcp_cwr[0x1]; 2897 u8 tcp_ece[0x1]; 2898 u8 tcp_urg[0x1]; 2899 u8 tcp_ack[0x1]; 2900 u8 tcp_psh[0x1]; 2901 u8 tcp_rst[0x1]; 2902 u8 tcp_syn[0x1]; 2903 u8 tcp_fin[0x1]; 2904 u8 reserved_f0[0x10]; 2905 }; 2906 2907 struct mlx5_ifc_ste_def16_v1_bits { 2908 u8 tunnel_header_0[0x20]; 2909 2910 u8 tunnel_header_1[0x20]; 2911 2912 u8 tunnel_header_2[0x20]; 2913 2914 u8 tunnel_header_3[0x20]; 2915 2916 u8 random_number[0x10]; 2917 u8 reserved_90[0x10]; 2918 2919 u8 metadata_reg_a[0x20]; 2920 2921 u8 reserved_c0[0x8]; 2922 u8 outer_l3_type[0x2]; 2923 u8 outer_l4_type[0x2]; 2924 u8 outer_first_vlan_type[0x2]; 2925 u8 reserved_ce[0x1]; 2926 u8 functional_lb[0x1]; 2927 u8 source_gvmi[0x10]; 2928 2929 u8 force_lb[0x1]; 2930 u8 outer_ip_frag[0x1]; 2931 u8 source_is_requester[0x1]; 2932 u8 reserved_e3[0x5]; 2933 u8 source_sqn[0x18]; 2934 }; 2935 2936 struct mlx5_ifc_ste_def22_v1_bits { 2937 u8 outer_ip_src_addr[0x20]; 2938 2939 u8 outer_ip_dst_addr[0x20]; 2940 2941 u8 outer_l4_sport[0x10]; 2942 u8 outer_l4_dport[0x10]; 2943 2944 u8 reserved_at_40[0x1]; 2945 u8 sx_sniffer[0x1]; 2946 u8 functional_loopback[0x1]; 2947 u8 outer_ip_frag[0x1]; 2948 u8 qp_type[0x2]; 2949 u8 encapsulation_type[0x2]; 2950 u8 port[0x2]; 2951 u8 outer_l3_type[0x2]; 2952 u8 outer_l4_type[0x2]; 2953 u8 first_vlan_qualifier[0x2]; 2954 u8 first_priority[0x3]; 2955 u8 first_cfi[0x1]; 2956 u8 first_vlan_id[0xc]; 2957 2958 u8 metadata_reg_c_0[0x20]; 2959 2960 u8 outer_dmac_47_16[0x20]; 2961 2962 u8 outer_smac_47_16[0x20]; 2963 2964 u8 outer_smac_15_0[0x10]; 2965 u8 outer_dmac_15_0[0x10]; 2966 }; 2967 2968 struct mlx5_ifc_ste_def24_v1_bits { 2969 u8 metadata_reg_c_2[0x20]; 2970 2971 u8 metadata_reg_c_3[0x20]; 2972 2973 u8 metadata_reg_c_0[0x20]; 2974 2975 u8 metadata_reg_c_1[0x20]; 2976 2977 u8 outer_ip_src_addr[0x20]; 2978 2979 u8 outer_ip_dst_addr[0x20]; 2980 2981 u8 outer_l4_sport[0x10]; 2982 u8 outer_l4_dport[0x10]; 2983 2984 u8 inner_ip_protocol[0x8]; 2985 u8 inner_l3_type[0x2]; 2986 u8 inner_l4_type[0x2]; 2987 u8 inner_first_vlan_type[0x2]; 2988 u8 inner_ip_frag[0x1]; 2989 u8 functional_lb[0x1]; 2990 u8 outer_ip_protocol[0x8]; 2991 u8 outer_l3_type[0x2]; 2992 u8 outer_l4_type[0x2]; 2993 u8 outer_first_vlan_type[0x2]; 2994 u8 outer_ip_frag[0x1]; 2995 u8 functional_lb_dup[0x1]; 2996 }; 2997 2998 struct mlx5_ifc_ste_def25_v1_bits { 2999 u8 inner_ip_src_addr[0x20]; 3000 3001 u8 inner_ip_dst_addr[0x20]; 3002 3003 u8 inner_l4_sport[0x10]; 3004 u8 inner_l4_dport[0x10]; 3005 3006 u8 tunnel_header_0[0x20]; 3007 3008 u8 tunnel_header_1[0x20]; 3009 3010 u8 reserved_at_a0[0x20]; 3011 3012 u8 port_number_dup[0x2]; 3013 u8 inner_l3_type[0x2]; 3014 u8 inner_l4_type[0x2]; 3015 u8 inner_first_vlan_type[0x2]; 3016 u8 port_number[0x2]; 3017 u8 outer_l3_type[0x2]; 3018 u8 outer_l4_type[0x2]; 3019 u8 outer_first_vlan_type[0x2]; 3020 u8 outer_l4_dport[0x10]; 3021 3022 u8 reserved_at_e0[0x20]; 3023 }; 3024 3025 struct mlx5_ifc_ste_def26_v1_bits { 3026 u8 src_ipv6_127_96[0x20]; 3027 3028 u8 src_ipv6_95_64[0x20]; 3029 3030 u8 src_ipv6_63_32[0x20]; 3031 3032 u8 src_ipv6_31_0[0x20]; 3033 3034 u8 reserved_at_80[0x3]; 3035 u8 ip_frag[0x1]; 3036 u8 reserved_at_84[0x6]; 3037 u8 l3_type[0x2]; 3038 u8 l4_type[0x2]; 3039 u8 first_vlan_type[0x2]; 3040 u8 first_priority[0x3]; 3041 u8 first_cfi[0x1]; 3042 u8 first_vlan_id[0xc]; 3043 3044 u8 reserved_at_a0[0xb]; 3045 u8 l2_ok[0x1]; 3046 u8 l3_ok[0x1]; 3047 u8 l4_ok[0x1]; 3048 u8 second_vlan_type[0x2]; 3049 u8 second_priority[0x3]; 3050 u8 second_cfi[0x1]; 3051 u8 second_vlan_id[0xc]; 3052 3053 u8 smac_47_16[0x20]; 3054 3055 u8 smac_15_0[0x10]; 3056 u8 ip_porotcol[0x8]; 3057 u8 tcp_cwr[0x1]; 3058 u8 tcp_ece[0x1]; 3059 u8 tcp_urg[0x1]; 3060 u8 tcp_ack[0x1]; 3061 u8 tcp_psh[0x1]; 3062 u8 tcp_rst[0x1]; 3063 u8 tcp_syn[0x1]; 3064 u8 tcp_fin[0x1]; 3065 }; 3066 3067 struct mlx5_ifc_ste_def28_v1_bits { 3068 u8 inner_l4_sport[0x10]; 3069 u8 inner_l4_dport[0x10]; 3070 3071 u8 flex_gtpu_teid[0x20]; 3072 3073 u8 inner_ip_src_addr[0x20]; 3074 3075 u8 inner_ip_dst_addr[0x20]; 3076 3077 u8 outer_ip_src_addr[0x20]; 3078 3079 u8 outer_ip_dst_addr[0x20]; 3080 3081 u8 outer_l4_sport[0x10]; 3082 u8 outer_l4_dport[0x10]; 3083 3084 u8 inner_ip_protocol[0x8]; 3085 u8 inner_l3_type[0x2]; 3086 u8 inner_l4_type[0x2]; 3087 u8 inner_first_vlan_type[0x2]; 3088 u8 inner_ip_frag[0x1]; 3089 u8 functional_lb[0x1]; 3090 u8 outer_ip_protocol[0x8]; 3091 u8 outer_l3_type[0x2]; 3092 u8 outer_l4_type[0x2]; 3093 u8 outer_first_vlan_type[0x2]; 3094 u8 outer_ip_frag[0x1]; 3095 u8 functional_lb_dup[0x1]; 3096 }; 3097 3098 struct mlx5_ifc_ste_def33_v1_bits { 3099 u8 outer_ip_src_addr[0x20]; 3100 3101 u8 outer_ip_dst_addr[0x20]; 3102 3103 u8 outer_l4_sport[0x10]; 3104 u8 outer_l4_dport[0x10]; 3105 3106 u8 reserved_at_60[0x1]; 3107 u8 sx_sniffer[0x1]; 3108 u8 functional_loopback[0x1]; 3109 u8 outer_ip_frag[0x1]; 3110 u8 qp_type[0x2]; 3111 u8 encapsulation_type[0x2]; 3112 u8 port[0x2]; 3113 u8 outer_l3_type[0x2]; 3114 u8 outer_l4_type[0x2]; 3115 u8 outer_first_vlan_type[0x2]; 3116 u8 outer_first_vlan_prio[0x3]; 3117 u8 outer_first_vlan_cfi[0x1]; 3118 u8 outer_first_vlan_vid[0xc]; 3119 3120 u8 reserved_at_80[0x20]; 3121 3122 u8 reserved_at_a0[0x20]; 3123 3124 u8 reserved_at_c0[0x20]; 3125 3126 u8 outer_ip_version[0x4]; 3127 u8 outer_ip_ihl[0x4]; 3128 u8 inner_ipv4_checksum_ok[0x1]; 3129 u8 inner_l4_checksum_ok[0x1]; 3130 u8 outer_ipv4_checksum_ok[0x1]; 3131 u8 outer_l4_checksum_ok[0x1]; 3132 u8 inner_l3_ok[0x1]; 3133 u8 inner_l4_ok[0x1]; 3134 u8 outer_l3_ok[0x1]; 3135 u8 outer_l4_ok[0x1]; 3136 u8 outer_ip_ttl[0x8]; 3137 u8 outer_ip_protocol[0x8]; 3138 }; 3139 3140 struct mlx5_ifc_set_action_in_bits { 3141 u8 action_type[0x4]; 3142 u8 field[0xc]; 3143 u8 reserved_at_10[0x3]; 3144 u8 offset[0x5]; 3145 u8 reserved_at_18[0x3]; 3146 u8 length[0x5]; 3147 3148 u8 data[0x20]; 3149 }; 3150 3151 struct mlx5_ifc_add_action_in_bits { 3152 u8 action_type[0x4]; 3153 u8 field[0xc]; 3154 u8 reserved_at_10[0x10]; 3155 3156 u8 data[0x20]; 3157 }; 3158 3159 struct mlx5_ifc_copy_action_in_bits { 3160 u8 action_type[0x4]; 3161 u8 src_field[0xc]; 3162 u8 reserved_at_10[0x3]; 3163 u8 src_offset[0x5]; 3164 u8 reserved_at_18[0x3]; 3165 u8 length[0x5]; 3166 3167 u8 reserved_at_20[0x4]; 3168 u8 dst_field[0xc]; 3169 u8 reserved_at_30[0x3]; 3170 u8 dst_offset[0x5]; 3171 u8 reserved_at_38[0x8]; 3172 }; 3173 3174 enum { 3175 MLX5_ACTION_TYPE_SET = 0x1, 3176 MLX5_ACTION_TYPE_ADD = 0x2, 3177 MLX5_ACTION_TYPE_COPY = 0x3, 3178 }; 3179 3180 enum { 3181 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 3182 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 3183 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 3184 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 3185 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 3186 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 3187 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 3188 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 3189 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 3190 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 3191 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 3192 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 3193 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 3194 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 3195 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 3196 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 3197 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 3198 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 3199 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 3200 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 3201 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 3202 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 3203 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 3204 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 3205 MLX5_ACTION_IN_FIELD_OUT_METADATA_REGA = 0x49, 3206 MLX5_ACTION_IN_FIELD_OUT_METADATA_REGB = 0x50, 3207 MLX5_ACTION_IN_FIELD_OUT_METADATA_REGC_0 = 0x51, 3208 MLX5_ACTION_IN_FIELD_OUT_METADATA_REGC_1 = 0x52, 3209 MLX5_ACTION_IN_FIELD_OUT_METADATA_REGC_2 = 0x53, 3210 MLX5_ACTION_IN_FIELD_OUT_METADATA_REGC_3 = 0x54, 3211 MLX5_ACTION_IN_FIELD_OUT_METADATA_REGC_4 = 0x55, 3212 MLX5_ACTION_IN_FIELD_OUT_METADATA_REGC_5 = 0x56, 3213 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 3214 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 3215 MLX5_ACTION_IN_FIELD_OUT_GTPU_TEID = 0x6E, 3216 MLX5_ACTION_IN_FIELD_OUT_IP_ECN = 0x73, 3217 }; 3218 3219 struct mlx5_ifc_dctc_bits { 3220 u8 reserved_at_0[0x1d]; 3221 u8 data_in_order[0x1]; 3222 u8 reserved_at_1e[0x362]; 3223 }; 3224 3225 struct mlx5_ifc_packet_reformat_context_in_bits { 3226 u8 reserved_at_0[0x5]; 3227 u8 reformat_type[0x3]; 3228 u8 reserved_at_8[0xe]; 3229 u8 reformat_data_size[0xa]; 3230 3231 u8 reserved_at_20[0x10]; 3232 u8 reformat_data[2][0x8]; 3233 3234 u8 more_reformat_data[0][0x8]; 3235 }; 3236 3237 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 3238 u8 opcode[0x10]; 3239 u8 reserved_at_10[0x10]; 3240 3241 u8 reserved_at_20[0x10]; 3242 u8 op_mod[0x10]; 3243 3244 u8 reserved_at_40[0xa0]; 3245 3246 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 3247 }; 3248 3249 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 3250 u8 status[0x8]; 3251 u8 reserved_at_8[0x18]; 3252 3253 u8 syndrome[0x20]; 3254 3255 u8 packet_reformat_id[0x20]; 3256 3257 u8 reserved_at_60[0x20]; 3258 }; 3259 3260 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 3261 u8 opcode[0x10]; 3262 u8 reserved_at_10[0x10]; 3263 3264 u8 reserved_20[0x10]; 3265 u8 op_mod[0x10]; 3266 3267 u8 packet_reformat_id[0x20]; 3268 3269 u8 reserved_60[0x20]; 3270 }; 3271 3272 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 3273 u8 status[0x8]; 3274 u8 reserved_at_8[0x18]; 3275 3276 u8 syndrome[0x20]; 3277 3278 u8 reserved_at_40[0x40]; 3279 }; 3280 3281 enum reformat_type { 3282 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 3283 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 3284 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 3285 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 3286 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 3287 }; 3288 3289 struct mlx5_ifc_alloc_flow_counter_in_bits { 3290 u8 opcode[0x10]; 3291 u8 uid[0x10]; 3292 3293 u8 reserved_at_20[0x10]; 3294 u8 op_mod[0x10]; 3295 3296 u8 reserved_at_40[0x40]; 3297 }; 3298 3299 struct mlx5_ifc_alloc_flow_counter_out_bits { 3300 u8 status[0x8]; 3301 u8 reserved_at_8[0x18]; 3302 3303 u8 syndrome[0x20]; 3304 3305 u8 flow_counter_id[0x20]; 3306 3307 u8 reserved_at_60[0x20]; 3308 }; 3309 3310 struct mlx5_ifc_dealloc_flow_counter_in_bits { 3311 u8 opcode[0x10]; 3312 u8 reserved_at_10[0x10]; 3313 3314 u8 reserved_at_20[0x20]; 3315 3316 u8 flow_counter_id[0x20]; 3317 3318 u8 reserved_at_60[0x20]; 3319 }; 3320 3321 enum { 3322 MLX5_OBJ_TYPE_FLOW_METER = 0x000a, 3323 MLX5_OBJ_TYPE_DEK = 0x000C, 3324 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 3325 MLX5_OBJ_TYPE_CRYPTO_LOGIN = 0x001F, 3326 MLX5_OBJ_TYPE_FLOW_SAMPLER = 0x0020, 3327 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x0023, 3328 MLX5_OBJ_TYPE_ASO_FLOW_METER = 0x0024, 3329 MLX5_OBJ_TYPE_ASO_FIRST_HIT = 0x0025, 3330 MLX5_OBJ_TYPE_SCHEDULING_ELEMENT = 0x0026, 3331 MLX5_OBJ_TYPE_RESERVED_QPN = 0x002C, 3332 MLX5_OBJ_TYPE_ASO_CT = 0x0031, 3333 MLX5_OBJ_TYPE_AV_QP_MAPPING = 0x003A, 3334 }; 3335 3336 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 3337 u8 opcode[0x10]; 3338 u8 uid[0x10]; 3339 3340 u8 reserved_at_20[0x10]; 3341 u8 obj_type[0x10]; 3342 3343 u8 obj_id[0x20]; 3344 3345 u8 reserved_at_60[0x3]; 3346 u8 log_obj_range[0x5]; 3347 u8 reserved_at_68[0x18]; 3348 }; 3349 3350 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 3351 u8 status[0x8]; 3352 u8 reserved_at_8[0x18]; 3353 3354 u8 syndrome[0x20]; 3355 3356 u8 obj_id[0x20]; 3357 3358 u8 reserved_at_60[0x20]; 3359 }; 3360 3361 struct mlx5_ifc_flow_meter_bits { 3362 u8 modify_field_select[0x40]; 3363 3364 u8 active[0x1]; 3365 u8 reserved_at_41[0x3]; 3366 u8 return_reg_id[0x4]; 3367 u8 table_type[0x8]; 3368 u8 reserved_at_50[0x10]; 3369 3370 u8 reserved_at_60[0x8]; 3371 u8 destination_table_id[0x18]; 3372 3373 u8 reserved_at_80[0x80]; 3374 3375 u8 flow_meter_params[0x100]; 3376 3377 u8 reserved_at_180[0x180]; 3378 3379 u8 sw_steering_icm_address_rx[0x40]; 3380 u8 sw_steering_icm_address_tx[0x40]; 3381 }; 3382 3383 struct mlx5_ifc_create_flow_meter_in_bits { 3384 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3385 struct mlx5_ifc_flow_meter_bits meter; 3386 }; 3387 3388 struct mlx5_ifc_query_flow_meter_out_bits { 3389 struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr; 3390 struct mlx5_ifc_flow_meter_bits obj; 3391 }; 3392 3393 struct mlx5_ifc_flow_sampler_bits { 3394 u8 modify_field_select[0x40]; 3395 3396 u8 table_type[0x8]; 3397 u8 level[0x8]; 3398 u8 reserved_at_50[0xf]; 3399 u8 ignore_flow_level[0x1]; 3400 3401 u8 sample_ratio[0x20]; 3402 3403 u8 reserved_at_80[0x8]; 3404 u8 sample_table_id[0x18]; 3405 3406 u8 reserved_at_a0[0x8]; 3407 u8 default_table_id[0x18]; 3408 3409 u8 sw_steering_icm_address_rx[0x40]; 3410 u8 sw_steering_icm_address_tx[0x40]; 3411 }; 3412 3413 struct mlx5_ifc_create_flow_sampler_in_bits { 3414 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3415 struct mlx5_ifc_flow_sampler_bits sampler; 3416 }; 3417 3418 struct mlx5_ifc_query_flow_sampler_out_bits { 3419 struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr; 3420 struct mlx5_ifc_flow_sampler_bits obj; 3421 }; 3422 3423 struct mlx5_ifc_modify_header_arg_bits { 3424 u8 reserved_at_0[0x80]; 3425 3426 u8 reserved_at_80[0x8]; 3427 u8 access_pd[0x18]; 3428 }; 3429 3430 struct mlx5_ifc_create_modify_header_arg_in_bits { 3431 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3432 struct mlx5_ifc_modify_header_arg_bits arg; 3433 }; 3434 3435 struct mlx5_ifc_definer_bits { 3436 u8 modify_field_select[0x40]; 3437 3438 u8 reserved_at_40[0x40]; 3439 3440 u8 reserved_at_80[0x10]; 3441 u8 format_id[0x10]; 3442 3443 u8 reserved_at_60[0x160]; 3444 3445 u8 ctrl[0xA0]; 3446 u8 match_mask_dw_11_8[0x60]; 3447 u8 match_mask_dw_7_0[0x100]; 3448 }; 3449 3450 struct mlx5_ifc_create_definer_in_bits { 3451 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3452 struct mlx5_ifc_definer_bits definer; 3453 }; 3454 3455 struct mlx5_ifc_esw_vport_context_bits { 3456 u8 reserved_at_0[0x3]; 3457 u8 vport_svlan_strip[0x1]; 3458 u8 vport_cvlan_strip[0x1]; 3459 u8 vport_svlan_insert[0x1]; 3460 u8 vport_cvlan_insert[0x2]; 3461 u8 reserved_at_8[0x18]; 3462 3463 u8 reserved_at_20[0x20]; 3464 3465 u8 svlan_cfi[0x1]; 3466 u8 svlan_pcp[0x3]; 3467 u8 svlan_id[0xc]; 3468 u8 cvlan_cfi[0x1]; 3469 u8 cvlan_pcp[0x3]; 3470 u8 cvlan_id[0xc]; 3471 3472 u8 reserved_at_40[0x720]; 3473 u8 sw_steering_vport_icm_address_rx[0x40]; 3474 u8 sw_steering_vport_icm_address_tx[0x40]; 3475 }; 3476 3477 struct mlx5_ifc_query_esw_vport_context_out_bits { 3478 u8 status[0x8]; 3479 u8 reserved_at_8[0x18]; 3480 3481 u8 syndrome[0x20]; 3482 3483 u8 reserved_at_40[0x40]; 3484 3485 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 3486 }; 3487 3488 struct mlx5_ifc_query_esw_vport_context_in_bits { 3489 u8 opcode[0x10]; 3490 u8 reserved_at_10[0x10]; 3491 3492 u8 reserved_at_20[0x10]; 3493 u8 op_mod[0x10]; 3494 3495 u8 other_vport[0x1]; 3496 u8 reserved_at_41[0xf]; 3497 u8 vport_number[0x10]; 3498 3499 u8 reserved_at_60[0x20]; 3500 }; 3501 3502 struct mlx5_ifc_nic_vport_context_bits { 3503 u8 reserved_at_0[0x1f]; 3504 u8 roce_en[0x1]; 3505 3506 u8 reserved_at_20[0x7e0]; 3507 }; 3508 3509 struct mlx5_ifc_query_nic_vport_context_out_bits { 3510 u8 status[0x8]; 3511 u8 reserved_at_8[0x18]; 3512 3513 u8 syndrome[0x20]; 3514 3515 u8 reserved_at_40[0x40]; 3516 3517 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 3518 }; 3519 3520 struct mlx5_ifc_query_nic_vport_context_in_bits { 3521 u8 opcode[0x10]; 3522 u8 reserved_at_10[0x10]; 3523 3524 u8 reserved_at_20[0x10]; 3525 u8 op_mod[0x10]; 3526 3527 u8 reserved_at_40[0x40]; 3528 }; 3529 3530 enum { 3531 MLX5_QPC_ST_RC = 0x0, 3532 }; 3533 3534 enum { 3535 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3536 }; 3537 3538 struct mlx5_ifc_ud_av_bits { 3539 u8 reserved_at_0[0x60]; 3540 3541 u8 reserved_at_60[0x4]; 3542 u8 sl_or_eth_prio[0x4]; 3543 u8 reserved_at_68[0x18]; 3544 3545 u8 reserved_at_80[0x60]; 3546 3547 u8 reserved_at_e0[0x4]; 3548 u8 src_addr_index[0x8]; 3549 u8 reserved_at_ec[0x14]; 3550 3551 u8 rgid_or_rip[16][0x8]; 3552 }; 3553 3554 struct mlx5_ifc_ads_bits { 3555 u8 fl[0x1]; 3556 u8 free_ar[0x1]; 3557 u8 reserved_at_2[0xe]; 3558 u8 pkey_index[0x10]; 3559 3560 u8 reserved_at_20[0x8]; 3561 u8 grh[0x1]; 3562 u8 mlid[0x7]; 3563 u8 rlid[0x10]; 3564 3565 u8 ack_timeout[0x5]; 3566 u8 reserved_at_45[0x3]; 3567 u8 src_addr_index[0x8]; 3568 u8 reserved_at_50[0x4]; 3569 u8 stat_rate[0x4]; 3570 u8 hop_limit[0x8]; 3571 3572 u8 reserved_at_60[0x4]; 3573 u8 tclass[0x8]; 3574 u8 flow_label[0x14]; 3575 3576 u8 rgid_rip[16][0x8]; 3577 3578 u8 reserved_at_100[0x4]; 3579 u8 f_dscp[0x1]; 3580 u8 f_ecn[0x1]; 3581 u8 reserved_at_106[0x1]; 3582 u8 f_eth_prio[0x1]; 3583 u8 ecn[0x2]; 3584 u8 dscp[0x6]; 3585 u8 udp_sport[0x10]; 3586 3587 u8 dei_cfi[0x1]; 3588 u8 eth_prio[0x3]; 3589 u8 sl[0x4]; 3590 u8 vhca_port_num[0x8]; 3591 u8 rmac_47_32[0x10]; 3592 3593 u8 rmac_31_0[0x20]; 3594 }; 3595 3596 enum { 3597 MLX5_QPC_STATE_SQDRAINED = 0x5, 3598 }; 3599 3600 enum { 3601 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3602 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3603 MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3604 }; 3605 3606 struct mlx5_ifc_qpc_bits { 3607 u8 state[0x4]; 3608 u8 lag_tx_port_affinity[0x4]; 3609 u8 st[0x8]; 3610 u8 reserved_at_10[0x2]; 3611 u8 isolate_vl_tc[0x1]; 3612 u8 pm_state[0x2]; 3613 u8 reserved_at_15[0x1]; 3614 u8 req_e2e_credit_mode[0x2]; 3615 u8 offload_type[0x4]; 3616 u8 end_padding_mode[0x2]; 3617 u8 reserved_at_1e[0x2]; 3618 3619 u8 wq_signature[0x1]; 3620 u8 block_lb_mc[0x1]; 3621 u8 atomic_like_write_en[0x1]; 3622 u8 latency_sensitive[0x1]; 3623 u8 reserved_at_24[0x1]; 3624 u8 drain_sigerr[0x1]; 3625 u8 reserved_at_26[0x2]; 3626 u8 pd[0x18]; 3627 3628 u8 mtu[0x3]; 3629 u8 log_msg_max[0x5]; 3630 u8 reserved_at_48[0x1]; 3631 u8 log_rq_size[0x4]; 3632 u8 log_rq_stride[0x3]; 3633 u8 no_sq[0x1]; 3634 u8 log_sq_size[0x4]; 3635 u8 reserved_at_55[0x3]; 3636 u8 ts_format[0x2]; 3637 u8 data_in_order[0x1]; 3638 u8 rlky[0x1]; 3639 u8 ulp_stateless_offload_mode[0x4]; 3640 3641 u8 counter_set_id[0x8]; 3642 u8 uar_page[0x18]; 3643 3644 u8 reserved_at_80[0x8]; 3645 u8 user_index[0x18]; 3646 3647 u8 reserved_at_a0[0x3]; 3648 u8 log_page_size[0x5]; 3649 u8 remote_qpn[0x18]; 3650 3651 struct mlx5_ifc_ads_bits primary_address_path; 3652 3653 struct mlx5_ifc_ads_bits secondary_address_path; 3654 3655 u8 log_ack_req_freq[0x4]; 3656 u8 reserved_at_384[0x4]; 3657 u8 log_sra_max[0x3]; 3658 u8 reserved_at_38b[0x2]; 3659 u8 retry_count[0x3]; 3660 u8 rnr_retry[0x3]; 3661 u8 reserved_at_393[0x1]; 3662 u8 fre[0x1]; 3663 u8 cur_rnr_retry[0x3]; 3664 u8 cur_retry_count[0x3]; 3665 u8 reserved_at_39b[0x5]; 3666 3667 u8 reserved_at_3a0[0x20]; 3668 3669 u8 reserved_at_3c0[0x8]; 3670 u8 next_send_psn[0x18]; 3671 3672 u8 reserved_at_3e0[0x8]; 3673 u8 cqn_snd[0x18]; 3674 3675 u8 reserved_at_400[0x8]; 3676 u8 deth_sqpn[0x18]; 3677 3678 u8 reserved_at_420[0x20]; 3679 3680 u8 reserved_at_440[0x8]; 3681 u8 last_acked_psn[0x18]; 3682 3683 u8 reserved_at_460[0x8]; 3684 u8 ssn[0x18]; 3685 3686 u8 reserved_at_480[0x8]; 3687 u8 log_rra_max[0x3]; 3688 u8 reserved_at_48b[0x1]; 3689 u8 atomic_mode[0x4]; 3690 u8 rre[0x1]; 3691 u8 rwe[0x1]; 3692 u8 rae[0x1]; 3693 u8 reserved_at_493[0x1]; 3694 u8 page_offset[0x6]; 3695 u8 reserved_at_49a[0x3]; 3696 u8 cd_slave_receive[0x1]; 3697 u8 cd_slave_send[0x1]; 3698 u8 cd_master[0x1]; 3699 3700 u8 reserved_at_4a0[0x3]; 3701 u8 min_rnr_nak[0x5]; 3702 u8 next_rcv_psn[0x18]; 3703 3704 u8 reserved_at_4c0[0x8]; 3705 u8 xrcd[0x18]; 3706 3707 u8 reserved_at_4e0[0x8]; 3708 u8 cqn_rcv[0x18]; 3709 3710 u8 dbr_addr[0x40]; 3711 3712 u8 q_key[0x20]; 3713 3714 u8 reserved_at_560[0x5]; 3715 u8 rq_type[0x3]; 3716 u8 srqn_rmpn_xrqn[0x18]; 3717 3718 u8 reserved_at_580[0x8]; 3719 u8 rmsn[0x18]; 3720 3721 u8 hw_sq_wqebb_counter[0x10]; 3722 u8 sw_sq_wqebb_counter[0x10]; 3723 3724 u8 hw_rq_counter[0x20]; 3725 3726 u8 sw_rq_counter[0x20]; 3727 3728 u8 reserved_at_600[0x20]; 3729 3730 u8 reserved_at_620[0xf]; 3731 u8 cgs[0x1]; 3732 u8 cs_req[0x8]; 3733 u8 cs_res[0x8]; 3734 3735 u8 dc_access_key[0x40]; 3736 3737 u8 reserved_at_680[0x3]; 3738 u8 dbr_umem_valid[0x1]; 3739 3740 u8 reserved_at_684[0x9c]; 3741 3742 u8 dbr_umem_id[0x20]; 3743 }; 3744 3745 struct mlx5_ifc_qpc_ext_bits { 3746 u8 reserved_at_0[0x2]; 3747 u8 mmo[0x1]; 3748 u8 reserved_at_3[0xd]; 3749 u8 dci_stream_channel_id[0x10]; 3750 3751 u8 qos_queue_group_id_requester[0x20]; 3752 3753 u8 qos_queue_group_id_responder[0x20]; 3754 3755 u8 reserved_at_60[0x5a0]; 3756 }; 3757 3758 struct mlx5_ifc_create_tir_out_bits { 3759 u8 status[0x8]; 3760 u8 icm_address_63_40[0x18]; 3761 3762 u8 syndrome[0x20]; 3763 3764 u8 icm_address_39_32[0x8]; 3765 u8 tirn[0x18]; 3766 3767 u8 icm_address_31_0[0x20]; 3768 }; 3769 3770 struct mlx5_ifc_destroy_tir_in_bits { 3771 u8 opcode[0x10]; 3772 u8 uid[0x10]; 3773 3774 u8 reserved_at_20[0x20]; 3775 3776 u8 reserved_at_40[0x8]; 3777 u8 tirn[0x18]; 3778 3779 u8 reserved_at_60[0x20]; 3780 }; 3781 3782 struct mlx5_ifc_create_qp_out_bits { 3783 u8 status[0x8]; 3784 u8 reserved_at_8[0x18]; 3785 3786 u8 syndrome[0x20]; 3787 3788 u8 reserved_at_40[0x8]; 3789 u8 qpn[0x18]; 3790 3791 u8 reserved_at_60[0x20]; 3792 }; 3793 3794 struct mlx5_ifc_create_qp_in_bits { 3795 u8 opcode[0x10]; 3796 u8 uid[0x10]; 3797 3798 u8 reserved_at_20[0x10]; 3799 u8 op_mod[0x10]; 3800 3801 u8 reserved_at_40[0x40]; 3802 3803 u8 opt_param_mask[0x20]; 3804 3805 u8 reserved_at_a0[0x20]; 3806 3807 struct mlx5_ifc_qpc_bits qpc; 3808 3809 u8 reserved_at_800[0x40]; 3810 3811 u8 wq_umem_id[0x20]; 3812 3813 u8 wq_umem_valid[0x1]; 3814 u8 reserved_at_861[0x1f]; 3815 3816 u8 pas[0][0x40]; 3817 }; 3818 3819 struct mlx5_ifc_destroy_qp_in_bits { 3820 u8 opcode[0x10]; 3821 u8 uid[0x10]; 3822 3823 u8 reserved_at_20[0x20]; 3824 3825 u8 reserved_at_40[0x8]; 3826 u8 qpn[0x18]; 3827 3828 u8 reserved_at_60[0x20]; 3829 }; 3830 3831 enum mlx5_qpc_opt_mask_32 { 3832 MLX5_QPC_OPT_MASK_32_DCI_STREAM_CHANNEL_ID = 1 << 0, 3833 MLX5_QPC_OPT_MASK_32_QOS_QUEUE_GROUP_ID = 1 << 1, 3834 MLX5_QPC_OPT_MASK_32_UDP_SPORT = 1 << 2, 3835 MLX5_QPC_OPT_MASK_32_INIT2INIT_MMO = 1 << 3, 3836 }; 3837 3838 enum mlx5_qpc_opt_mask { 3839 MLX5_QPC_OPT_MASK_INIT2INIT_DRAIN_SIGERR = 1 << 11, 3840 MLX5_QPC_OPT_MASK_RTS2RTS_LAG_TX_PORT_AFFINITY = 1 << 15, 3841 }; 3842 3843 struct mlx5_ifc_init2init_qp_out_bits { 3844 u8 status[0x8]; 3845 u8 reserved_at_8[0x18]; 3846 3847 u8 syndrome[0x20]; 3848 3849 u8 reserved_at_40[0x40]; 3850 }; 3851 3852 struct mlx5_ifc_init2init_qp_in_bits { 3853 u8 opcode[0x10]; 3854 u8 uid[0x10]; 3855 3856 u8 reserved_at_20[0x10]; 3857 u8 op_mod[0x10]; 3858 3859 u8 qpc_ext[0x1]; 3860 u8 reserved_at_41[0x7]; 3861 u8 qpn[0x18]; 3862 3863 u8 reserved_at_60[0x20]; 3864 3865 u8 opt_param_mask[0x20]; 3866 3867 u8 reserved_at_a0[0x20]; 3868 3869 struct mlx5_ifc_qpc_bits qpc; 3870 3871 u8 reserved_at_800[0x40]; 3872 3873 u8 opt_param_mask_95_32[0x40]; 3874 3875 struct mlx5_ifc_qpc_ext_bits qpc_data_ext; 3876 }; 3877 3878 struct mlx5_ifc_init2rtr_qp_out_bits { 3879 u8 status[0x8]; 3880 u8 reserved_at_8[0x18]; 3881 3882 u8 syndrome[0x20]; 3883 3884 u8 reserved_at_40[0x40]; 3885 }; 3886 3887 struct mlx5_ifc_init2rtr_qp_in_bits { 3888 u8 opcode[0x10]; 3889 u8 uid[0x10]; 3890 3891 u8 reserved_at_20[0x10]; 3892 u8 op_mod[0x10]; 3893 3894 u8 reserved_at_40[0x8]; 3895 u8 qpn[0x18]; 3896 3897 u8 reserved_at_60[0x20]; 3898 3899 u8 opt_param_mask[0x20]; 3900 3901 u8 reserved_at_a0[0x20]; 3902 3903 struct mlx5_ifc_qpc_bits qpc; 3904 3905 u8 reserved_at_800[0x80]; 3906 }; 3907 3908 struct mlx5_ifc_rtr2rts_qp_out_bits { 3909 u8 status[0x8]; 3910 u8 reserved_at_8[0x18]; 3911 3912 u8 syndrome[0x20]; 3913 3914 u8 reserved_at_40[0x40]; 3915 }; 3916 3917 struct mlx5_ifc_rtr2rts_qp_in_bits { 3918 u8 opcode[0x10]; 3919 u8 uid[0x10]; 3920 3921 u8 reserved_at_20[0x10]; 3922 u8 op_mod[0x10]; 3923 3924 u8 reserved_at_40[0x8]; 3925 u8 qpn[0x18]; 3926 3927 u8 reserved_at_60[0x20]; 3928 3929 u8 opt_param_mask[0x20]; 3930 3931 u8 reserved_at_a0[0x20]; 3932 3933 struct mlx5_ifc_qpc_bits qpc; 3934 3935 u8 reserved_at_800[0x80]; 3936 }; 3937 3938 struct mlx5_ifc_rst2init_qp_out_bits { 3939 u8 status[0x8]; 3940 u8 reserved_at_8[0x18]; 3941 3942 u8 syndrome[0x20]; 3943 3944 u8 reserved_at_40[0x40]; 3945 }; 3946 3947 struct mlx5_ifc_rst2init_qp_in_bits { 3948 u8 opcode[0x10]; 3949 u8 uid[0x10]; 3950 3951 u8 reserved_at_20[0x10]; 3952 u8 op_mod[0x10]; 3953 3954 u8 reserved_at_40[0x8]; 3955 u8 qpn[0x18]; 3956 3957 u8 reserved_at_60[0x20]; 3958 3959 u8 opt_param_mask[0x20]; 3960 3961 u8 reserved_at_a0[0x20]; 3962 3963 struct mlx5_ifc_qpc_bits qpc; 3964 3965 u8 reserved_at_800[0x80]; 3966 }; 3967 3968 struct mlx5_ifc_rts2rts_qp_out_bits { 3969 u8 status[0x8]; 3970 u8 reserved_at_8[0x18]; 3971 3972 u8 syndrome[0x20]; 3973 3974 u8 reserved_at_40[0x40]; 3975 }; 3976 3977 struct mlx5_ifc_rts2rts_qp_in_bits { 3978 u8 opcode[0x10]; 3979 u8 uid[0x10]; 3980 3981 u8 reserved_at_20[0x10]; 3982 u8 op_mod[0x10]; 3983 3984 u8 qpc_ext[0x1]; 3985 u8 reserved_at_41[0x7]; 3986 u8 qpn[0x18]; 3987 3988 u8 reserved_at_60[0x20]; 3989 3990 u8 opt_param_mask[0x20]; 3991 3992 u8 reserved_at_a0[0x20]; 3993 3994 struct mlx5_ifc_qpc_bits qpc; 3995 3996 u8 reserved_at_800[0x40]; 3997 3998 u8 opt_param_mask_95_32[0x40]; 3999 4000 struct mlx5_ifc_qpc_ext_bits qpc_data_ext; 4001 }; 4002 4003 struct mlx5_ifc_query_qp_out_bits { 4004 u8 status[0x8]; 4005 u8 reserved_at_8[0x18]; 4006 4007 u8 syndrome[0x20]; 4008 4009 u8 reserved_at_40[0x40]; 4010 4011 u8 opt_param_mask[0x20]; 4012 4013 u8 reserved_at_a0[0x20]; 4014 4015 struct mlx5_ifc_qpc_bits qpc; 4016 4017 u8 reserved_at_800[0x80]; 4018 4019 u8 pas[0][0x40]; 4020 }; 4021 4022 struct mlx5_ifc_query_qp_in_bits { 4023 u8 opcode[0x10]; 4024 u8 reserved_at_10[0x10]; 4025 4026 u8 reserved_at_20[0x10]; 4027 u8 op_mod[0x10]; 4028 4029 u8 reserved_at_40[0x8]; 4030 u8 qpn[0x18]; 4031 4032 u8 reserved_at_60[0x20]; 4033 }; 4034 4035 struct mlx5_ifc_query_dct_out_bits { 4036 u8 status[0x8]; 4037 u8 reserved_at_8[0x18]; 4038 4039 u8 syndrome[0x20]; 4040 4041 u8 reserved_at_40[0x40]; 4042 4043 struct mlx5_ifc_dctc_bits dctc; 4044 }; 4045 4046 struct mlx5_ifc_query_dct_in_bits { 4047 u8 opcode[0x10]; 4048 u8 reserved_at_10[0x10]; 4049 4050 u8 reserved_at_20[0x10]; 4051 u8 op_mod[0x10]; 4052 4053 u8 reserved_at_40[0x8]; 4054 u8 dctn[0x18]; 4055 4056 u8 reserved_at_60[0x20]; 4057 }; 4058 4059 struct mlx5_ifc_tisc_bits { 4060 u8 strict_lag_tx_port_affinity[0x1]; 4061 u8 tls_en[0x1]; 4062 u8 reserved_at_2[0x2]; 4063 u8 lag_tx_port_affinity[0x04]; 4064 4065 u8 reserved_at_8[0x4]; 4066 u8 prio[0x4]; 4067 u8 reserved_at_10[0x10]; 4068 4069 u8 reserved_at_20[0x100]; 4070 4071 u8 reserved_at_120[0x8]; 4072 u8 transport_domain[0x18]; 4073 4074 u8 reserved_at_140[0x8]; 4075 u8 underlay_qpn[0x18]; 4076 4077 u8 reserved_at_160[0x8]; 4078 u8 pd[0x18]; 4079 4080 u8 reserved_at_180[0x380]; 4081 }; 4082 4083 struct mlx5_ifc_query_tis_out_bits { 4084 u8 status[0x8]; 4085 u8 reserved_at_8[0x18]; 4086 4087 u8 syndrome[0x20]; 4088 4089 u8 reserved_at_40[0x40]; 4090 4091 struct mlx5_ifc_tisc_bits tis_context; 4092 }; 4093 4094 struct mlx5_ifc_query_tis_in_bits { 4095 u8 opcode[0x10]; 4096 u8 reserved_at_10[0x10]; 4097 4098 u8 reserved_at_20[0x10]; 4099 u8 op_mod[0x10]; 4100 4101 u8 reserved_at_40[0x8]; 4102 u8 tisn[0x18]; 4103 4104 u8 reserved_at_60[0x20]; 4105 }; 4106 4107 struct mlx5_ifc_lagc_bits { 4108 u8 reserved_at_0[0x1d]; 4109 u8 lag_state[0x3]; 4110 4111 u8 reserved_at_20[0x14]; 4112 u8 tx_remap_affinity_2[0x4]; 4113 u8 reserved_at_38[0x4]; 4114 u8 tx_remap_affinity_1[0x4]; 4115 }; 4116 4117 struct mlx5_ifc_query_lag_out_bits { 4118 u8 status[0x8]; 4119 u8 reserved_at_8[0x18]; 4120 4121 u8 syndrome[0x20]; 4122 4123 struct mlx5_ifc_lagc_bits ctx; 4124 }; 4125 4126 struct mlx5_ifc_query_lag_in_bits { 4127 u8 opcode[0x10]; 4128 u8 reserved_at_10[0x10]; 4129 4130 u8 reserved_at_20[0x10]; 4131 u8 op_mod[0x10]; 4132 4133 u8 reserved_at_40[0x40]; 4134 }; 4135 4136 struct mlx5_ifc_av_qp_mapping_bits { 4137 u8 modify_field_select[0x40]; 4138 4139 u8 reserved_at_40[0x20]; 4140 4141 u8 qpn[0x20]; 4142 4143 struct mlx5_ifc_ud_av_bits remote_address_vector; 4144 }; 4145 4146 struct mlx5_ifc_create_av_qp_mapping_in_bits { 4147 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 4148 struct mlx5_ifc_av_qp_mapping_bits mapping; 4149 }; 4150 4151 struct mlx5_ifc_query_av_qp_mapping_out_bits { 4152 struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr; 4153 struct mlx5_ifc_av_qp_mapping_bits obj; 4154 }; 4155 4156 4157 struct mlx5_ifc_modify_tis_out_bits { 4158 u8 status[0x8]; 4159 u8 reserved_at_8[0x18]; 4160 4161 u8 syndrome[0x20]; 4162 4163 u8 reserved_at_40[0x40]; 4164 }; 4165 4166 struct mlx5_ifc_modify_tis_bitmask_bits { 4167 u8 reserved_at_0[0x20]; 4168 4169 u8 reserved_at_20[0x1d]; 4170 u8 lag_tx_port_affinity[0x1]; 4171 u8 strict_lag_tx_port_affinity[0x1]; 4172 u8 prio[0x1]; 4173 }; 4174 4175 struct mlx5_ifc_modify_tis_in_bits { 4176 u8 opcode[0x10]; 4177 u8 uid[0x10]; 4178 4179 u8 reserved_at_20[0x10]; 4180 u8 op_mod[0x10]; 4181 4182 u8 reserved_at_40[0x8]; 4183 u8 tisn[0x18]; 4184 4185 u8 reserved_at_60[0x20]; 4186 4187 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 4188 4189 u8 reserved_at_c0[0x40]; 4190 4191 struct mlx5_ifc_tisc_bits ctx; 4192 }; 4193 4194 enum roce_version { 4195 MLX5_ROCE_VERSION_1 = 0, 4196 MLX5_ROCE_VERSION_2 = 2, 4197 }; 4198 4199 struct mlx5_ifc_roce_addr_layout_bits { 4200 u8 source_l3_address[16][0x8]; 4201 4202 u8 reserved_at_80[0x3]; 4203 u8 vlan_valid[0x1]; 4204 u8 vlan_id[0xc]; 4205 u8 source_mac_47_32[0x10]; 4206 4207 u8 source_mac_31_0[0x20]; 4208 4209 u8 reserved_at_c0[0x14]; 4210 u8 roce_l3_type[0x4]; 4211 u8 roce_version[0x8]; 4212 4213 u8 reserved_at_e0[0x20]; 4214 }; 4215 4216 struct mlx5_ifc_query_roce_address_out_bits { 4217 u8 status[0x8]; 4218 u8 reserved_at_8[0x18]; 4219 4220 u8 syndrome[0x20]; 4221 4222 u8 reserved_at_40[0x40]; 4223 4224 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4225 }; 4226 4227 struct mlx5_ifc_query_roce_address_in_bits { 4228 u8 opcode[0x10]; 4229 u8 reserved_at_10[0x10]; 4230 4231 u8 reserved_at_20[0x10]; 4232 u8 op_mod[0x10]; 4233 4234 u8 roce_address_index[0x10]; 4235 u8 reserved_at_50[0xc]; 4236 u8 vhca_port_num[0x4]; 4237 4238 u8 reserved_at_60[0x20]; 4239 }; 4240 4241 /* Both HW set and HW add share the same HW format with different opcodes */ 4242 struct mlx5_ifc_dr_action_hw_set_bits { 4243 u8 opcode[0x8]; 4244 u8 destination_field_code[0x8]; 4245 u8 reserved_at_10[0x2]; 4246 u8 destination_left_shifter[0x6]; 4247 u8 reserved_at_18[0x3]; 4248 u8 destination_length[0x5]; 4249 4250 u8 inline_data[0x20]; 4251 }; 4252 4253 struct mlx5_ifc_dr_action_hw_copy_bits { 4254 u8 opcode[0x8]; 4255 u8 destination_field_code[0x8]; 4256 u8 reserved_at_10[0x2]; 4257 u8 destination_left_shifter[0x6]; 4258 u8 reserved_at_18[0x2]; 4259 u8 destination_length[0x6]; 4260 4261 u8 reserved_at_20[0x8]; 4262 u8 source_field_code[0x8]; 4263 u8 reserved_at_30[0x2]; 4264 u8 source_left_shifter[0x6]; 4265 u8 reserved_at_38[0x8]; 4266 }; 4267 4268 struct mlx5_ifc_host_params_context_bits { 4269 u8 host_number[0x8]; 4270 u8 reserved_at_8[0x6]; 4271 u8 host_pf_vhca_id_valid[0x1]; 4272 u8 host_pf_disabled[0x1]; 4273 u8 host_num_of_vfs[0x10]; 4274 4275 u8 host_total_vfs[0x10]; 4276 u8 host_pci_bus[0x10]; 4277 4278 u8 host_pf_vhca_id[0x10]; 4279 u8 host_pci_device[0x10]; 4280 4281 u8 reserved_at_60[0x10]; 4282 u8 host_pci_function[0x10]; 4283 4284 u8 reserved_at_80[0x180]; 4285 }; 4286 4287 struct mlx5_ifc_query_esw_functions_in_bits { 4288 u8 opcode[0x10]; 4289 u8 reserved_at_10[0x10]; 4290 4291 u8 reserved_at_20[0x10]; 4292 u8 op_mod[0x10]; 4293 4294 u8 reserved_at_40[0x40]; 4295 }; 4296 4297 struct mlx5_ifc_query_esw_functions_out_bits { 4298 u8 status[0x8]; 4299 u8 reserved_at_8[0x18]; 4300 4301 u8 syndrome[0x20]; 4302 4303 u8 reserved_at_40[0x40]; 4304 4305 struct mlx5_ifc_host_params_context_bits host_params_context; 4306 4307 u8 reserved_at_280[0x180]; 4308 u8 host_sf_enable[0][0x40]; 4309 }; 4310 4311 struct mlx5_ifc_create_flow_group_in_bits { 4312 u8 opcode[0x10]; 4313 u8 reserved_at_10[0x10]; 4314 4315 u8 reserved_at_20[0x20]; 4316 4317 u8 other_vport[0x1]; 4318 u8 reserved_at_41[0xf]; 4319 u8 vport_number[0x10]; 4320 4321 u8 reserved_at_60[0x20]; 4322 4323 u8 table_type[0x8]; 4324 u8 reserved_at_88[0x18]; 4325 4326 u8 reserved_at_a0[0x8]; 4327 u8 table_id[0x18]; 4328 4329 u8 reserved_at_c0[0x1f40]; 4330 }; 4331 4332 struct mlx5_ifc_create_flow_group_out_bits { 4333 u8 status[0x8]; 4334 u8 reserved_at_8[0x18]; 4335 4336 u8 syndrome[0x20]; 4337 4338 u8 reserved_at_40[0x8]; 4339 u8 group_id[0x18]; 4340 4341 u8 reserved_at_60[0x20]; 4342 }; 4343 4344 struct mlx5_ifc_destroy_flow_group_in_bits { 4345 u8 opcode[0x10]; 4346 u8 reserved_at_10[0x10]; 4347 4348 u8 reserved_at_20[0x20]; 4349 4350 u8 other_vport[0x1]; 4351 u8 reserved_at_41[0xf]; 4352 u8 vport_number[0x10]; 4353 4354 u8 reserved_at_60[0x20]; 4355 4356 u8 table_type[0x8]; 4357 u8 reserved_at_88[0x18]; 4358 4359 u8 reserved_at_a0[0x8]; 4360 u8 table_id[0x18]; 4361 4362 u8 group_id[0x20]; 4363 4364 u8 reserved_at_e0[0x120]; 4365 }; 4366 4367 struct mlx5_ifc_dest_format_bits { 4368 u8 destination_type[0x8]; 4369 u8 destination_id[0x18]; 4370 4371 u8 reserved_at_20[0x1]; 4372 u8 packet_reformat[0x1]; 4373 u8 reserved_at_22[0x1e]; 4374 }; 4375 4376 struct mlx5_ifc_extended_dest_format_bits { 4377 struct mlx5_ifc_dest_format_bits destination_entry; 4378 4379 u8 packet_reformat_id[0x20]; 4380 4381 u8 reserved_at_60[0x20]; 4382 }; 4383 4384 struct mlx5_ifc_flow_counter_list_bits { 4385 u8 flow_counter_id[0x20]; 4386 4387 u8 reserved_at_20[0x20]; 4388 }; 4389 4390 union mlx5_ifc_dest_format_flow_counter_list_auto_bits { 4391 struct mlx5_ifc_dest_format_bits dest_format; 4392 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 4393 u8 reserved_at_0[0x40]; 4394 }; 4395 4396 struct mlx5_ifc_flow_context_bits { 4397 u8 reserved_at_00[0x20]; 4398 4399 u8 group_id[0x20]; 4400 4401 u8 reserved_at_40[0x8]; 4402 u8 flow_tag[0x18]; 4403 4404 u8 reserved_at_60[0x10]; 4405 u8 action[0x10]; 4406 4407 u8 extended_destination[0x1]; 4408 u8 reserved_at_81[0x7]; 4409 u8 destination_list_size[0x18]; 4410 4411 u8 reserved_at_a0[0x8]; 4412 u8 flow_counter_list_size[0x18]; 4413 4414 u8 reserved_at_c0[0x1740]; 4415 4416 union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[0]; 4417 }; 4418 4419 struct mlx5_ifc_set_fte_in_bits { 4420 u8 opcode[0x10]; 4421 u8 reserved_at_10[0x10]; 4422 4423 u8 reserved_at_20[0x10]; 4424 u8 op_mod[0x10]; 4425 4426 u8 other_vport[0x1]; 4427 u8 reserved_at_41[0xf]; 4428 u8 vport_number[0x10]; 4429 4430 u8 reserved_at_60[0x20]; 4431 4432 u8 table_type[0x8]; 4433 u8 reserved_at_88[0x18]; 4434 4435 u8 reserved_at_a0[0x8]; 4436 u8 table_id[0x18]; 4437 4438 u8 reserved_at_c0[0x40]; 4439 u8 flow_index[0x20]; 4440 4441 u8 reserved_at_120[0xe0]; 4442 struct mlx5_ifc_flow_context_bits flow_context; 4443 }; 4444 4445 struct mlx5_ifc_set_fte_out_bits { 4446 u8 status[0x8]; 4447 u8 reserved_at_8[0x18]; 4448 4449 u8 syndrome[0x20]; 4450 4451 u8 reserved_at_40[0x40]; 4452 }; 4453 4454 enum dr_devx_flow_dest_type { 4455 MLX5_FLOW_DEST_TYPE_VPORT = 0x0, 4456 MLX5_FLOW_DEST_TYPE_FT = 0x1, 4457 MLX5_FLOW_DEST_TYPE_TIR = 0x2, 4458 4459 MLX5_FLOW_DEST_TYPE_COUNTER = 0x100, 4460 }; 4461 4462 enum { 4463 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 4464 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 4465 }; 4466 4467 enum { 4468 MLX5_QPC_PAGE_OFFSET_QUANTA = 64, 4469 }; 4470 4471 enum { 4472 MLX5_ASO_FIRST_HIT_NUM_PER_OBJ = 512, 4473 MLX5_ASO_FLOW_METER_NUM_PER_OBJ = 2, 4474 MLX5_ASO_CT_NUM_PER_OBJ = 1, 4475 }; 4476 4477 enum mlx5_sched_hierarchy_type { 4478 MLX5_SCHED_HIERARCHY_NIC = 3, 4479 }; 4480 4481 enum mlx5_sched_elem_type { 4482 MLX5_SCHED_ELEM_TYPE_TSAR = 0x0, 4483 MLX5_SCHED_ELEM_TYPE_VPORT = 0x1, 4484 MLX5_SCHED_ELEM_TYPE_VPORT_TC = 0x2, 4485 MLX5_SCHED_ELEM_TYPE_PARA_VPORT_TC = 0x3, 4486 MLX5_SCHED_ELEM_TYPE_QUEUE_GROUP = 0x4, 4487 }; 4488 4489 enum mlx5_sched_tsar_type { 4490 MLX5_SCHED_TSAR_TYPE_DWRR = 0x0, 4491 MLX5_SCHED_TSAR_TYPE_ROUND_ROBIN = 0x1, 4492 MLX5_SCHED_TSAR_TYPE_ETS = 0x2, 4493 }; 4494 4495 struct mlx5_ifc_sched_elem_attr_tsar_bits { 4496 u8 reserved_at_0[0x8]; 4497 u8 tsar_type[0x8]; 4498 u8 reserved_at_10[0x10]; 4499 }; 4500 4501 union mlx5_ifc_sched_elem_attr_bits { 4502 struct mlx5_ifc_sched_elem_attr_tsar_bits tsar; 4503 }; 4504 4505 struct mlx5_ifc_sched_context_bits { 4506 u8 element_type[0x8]; 4507 u8 reserved_at_8[0x18]; 4508 4509 union mlx5_ifc_sched_elem_attr_bits sched_elem_attr; 4510 4511 u8 parent_element_id[0x20]; 4512 4513 u8 reserved_at_60[0x40]; 4514 4515 u8 bw_share[0x20]; 4516 4517 u8 max_average_bw[0x20]; 4518 4519 u8 reserved_at_e0[0x120]; 4520 }; 4521 4522 struct mlx5_ifc_sched_elem_bits { 4523 u8 modify_field_select[0x40]; 4524 4525 u8 scheduling_hierarchy[0x8]; 4526 u8 reserved_at_48[0x18]; 4527 4528 u8 reserved_at_60[0xa0]; 4529 4530 struct mlx5_ifc_sched_context_bits sched_context; 4531 4532 u8 reserved_at_300[0x100]; 4533 }; 4534 4535 struct mlx5_ifc_create_sched_elem_in_bits { 4536 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 4537 struct mlx5_ifc_sched_elem_bits sched_elem; 4538 }; 4539 4540 struct mlx5_ifc_create_modify_elem_in_bits { 4541 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 4542 struct mlx5_ifc_sched_elem_bits sched_elem; 4543 }; 4544 4545 enum { 4546 MLX5_SQC_STATE_RDY = 0x1, 4547 }; 4548 4549 struct mlx5_ifc_sqc_bits { 4550 u8 reserved_at_0[0x8]; 4551 u8 state[0x4]; 4552 u8 reserved_at_c[0x14]; 4553 4554 u8 reserved_at_20[0xe0]; 4555 4556 u8 reserved_at_100[0x10]; 4557 u8 qos_queue_group_id[0x10]; 4558 4559 u8 reserved_at_120[0x660]; 4560 }; 4561 4562 enum { 4563 MLX5_MODIFY_SQ_BITMASK_QOS_QUEUE_GROUP_ID = 1 << 2, 4564 }; 4565 4566 struct mlx5_ifc_modify_sq_out_bits { 4567 u8 status[0x8]; 4568 u8 reserved_at_8[0x18]; 4569 4570 u8 syndrome[0x20]; 4571 4572 u8 reserved_at_40[0x40]; 4573 }; 4574 4575 struct mlx5_ifc_modify_sq_in_bits { 4576 u8 opcode[0x10]; 4577 u8 uid[0x10]; 4578 4579 u8 reserved_at_20[0x10]; 4580 u8 op_mod[0x10]; 4581 4582 u8 sq_state[0x4]; 4583 u8 reserved_at_44[0x4]; 4584 u8 sqn[0x18]; 4585 4586 u8 reserved_at_60[0x20]; 4587 4588 u8 modify_bitmask[0x40]; 4589 4590 u8 reserved_at_c0[0x40]; 4591 4592 struct mlx5_ifc_sqc_bits sq_context; 4593 }; 4594 4595 struct mlx5_ifc_reserved_qpn_bits { 4596 u8 reserved_at_0[0x80]; 4597 }; 4598 4599 struct mlx5_ifc_create_reserved_qpn_in_bits { 4600 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 4601 struct mlx5_ifc_reserved_qpn_bits rqpns; 4602 }; 4603 4604 struct mlx5_ifc_create_psv_out_bits { 4605 u8 status[0x8]; 4606 u8 reserved_at_8[0x18]; 4607 4608 u8 syndrome[0x20]; 4609 4610 u8 reserved_at_40[0x40]; 4611 4612 u8 reserved_at_80[0x8]; 4613 u8 psv0_index[0x18]; 4614 4615 u8 reserved_at_a0[0x8]; 4616 u8 psv1_index[0x18]; 4617 4618 u8 reserved_at_c0[0x8]; 4619 u8 psv2_index[0x18]; 4620 4621 u8 reserved_at_e0[0x8]; 4622 u8 psv3_index[0x18]; 4623 }; 4624 4625 struct mlx5_ifc_create_psv_in_bits { 4626 u8 opcode[0x10]; 4627 u8 reserved_at_10[0x10]; 4628 4629 u8 reserved_at_20[0x10]; 4630 u8 op_mod[0x10]; 4631 4632 u8 num_psv[0x4]; 4633 u8 reserved_at_44[0x4]; 4634 u8 pd[0x18]; 4635 4636 u8 reserved_at_60[0x20]; 4637 }; 4638 4639 struct mlx5_ifc_destroy_psv_in_bits { 4640 u8 opcode[0x10]; 4641 u8 reserved_at_10[0x10]; 4642 4643 u8 reserved_at_20[0x20]; 4644 4645 u8 reserved_at_40[0x8]; 4646 u8 psvn[0x18]; 4647 4648 u8 reserved_at_60[0x20]; 4649 }; 4650 4651 struct mlx5_ifc_mbox_out_bits { 4652 u8 status[0x8]; 4653 u8 reserved_at_8[0x18]; 4654 4655 u8 syndrome[0x20]; 4656 4657 u8 reserved_at_40[0x40]; 4658 }; 4659 4660 struct mlx5_ifc_mbox_in_bits { 4661 u8 opcode[0x10]; 4662 u8 uid[0x10]; 4663 4664 u8 reserved_at_20[0x10]; 4665 u8 op_mod[0x10]; 4666 4667 u8 reserved_at_40[0x40]; 4668 }; 4669 4670 struct mlx5_ifc_enable_hca_in_bits { 4671 u8 opcode[0x10]; 4672 u8 reserved_at_10[0x10]; 4673 4674 u8 reserved_at_20[0x10]; 4675 u8 op_mod[0x10]; 4676 4677 u8 reserved_at_40[0x10]; 4678 u8 function_id[0x10]; 4679 4680 u8 reserved_at_60[0x20]; 4681 }; 4682 4683 struct mlx5_ifc_enable_hca_out_bits { 4684 u8 status[0x8]; 4685 u8 reserved_at_8[0x18]; 4686 4687 u8 syndrome[0x20]; 4688 4689 u8 reserved_at_40[0x20]; 4690 }; 4691 4692 struct mlx5_ifc_query_issi_out_bits { 4693 u8 status[0x8]; 4694 u8 reserved_at_8[0x18]; 4695 4696 u8 syndrome[0x20]; 4697 4698 u8 reserved_at_40[0x10]; 4699 u8 current_issi[0x10]; 4700 4701 u8 reserved_at_60[0xa0]; 4702 4703 u8 reserved_at_100[76][0x8]; 4704 u8 supported_issi_dw0[0x20]; 4705 }; 4706 4707 struct mlx5_ifc_query_issi_in_bits { 4708 u8 opcode[0x10]; 4709 u8 reserved_at_10[0x10]; 4710 4711 u8 reserved_at_20[0x10]; 4712 u8 op_mod[0x10]; 4713 4714 u8 reserved_at_40[0x40]; 4715 }; 4716 4717 struct mlx5_ifc_set_issi_out_bits { 4718 u8 status[0x8]; 4719 u8 reserved_at_8[0x18]; 4720 4721 u8 syndrome[0x20]; 4722 4723 u8 reserved_at_40[0x40]; 4724 }; 4725 4726 struct mlx5_ifc_set_issi_in_bits { 4727 u8 opcode[0x10]; 4728 u8 reserved_at_10[0x10]; 4729 4730 u8 reserved_at_20[0x10]; 4731 u8 op_mod[0x10]; 4732 4733 u8 reserved_at_40[0x10]; 4734 u8 current_issi[0x10]; 4735 4736 u8 reserved_at_60[0x20]; 4737 }; 4738 4739 struct mlx5_ifc_query_pages_out_bits { 4740 u8 status[0x8]; 4741 u8 reserved_at_8[0x18]; 4742 4743 u8 syndrome[0x20]; 4744 4745 u8 embedded_cpu_function[0x01]; 4746 u8 reserved_bits[0x0f]; 4747 u8 function_id[0x10]; 4748 4749 u8 num_pages[0x20]; 4750 }; 4751 4752 struct mlx5_ifc_query_pages_in_bits { 4753 u8 opcode[0x10]; 4754 u8 reserved_at_10[0x10]; 4755 4756 u8 reserved_at_20[0x10]; 4757 u8 op_mod[0x10]; 4758 4759 u8 reserved_at_40[0x10]; 4760 u8 function_id[0x10]; 4761 4762 u8 reserved_at_60[0x20]; 4763 }; 4764 4765 struct mlx5_ifc_manage_pages_out_bits { 4766 u8 status[0x8]; 4767 u8 reserved_at_8[0x18]; 4768 4769 u8 syndrome[0x20]; 4770 4771 u8 output_num_entries[0x20]; 4772 4773 u8 reserved_at_60[0x20]; 4774 4775 u8 pas[][0x40]; 4776 }; 4777 4778 struct mlx5_ifc_manage_pages_in_bits { 4779 u8 opcode[0x10]; 4780 u8 reserved_at_10[0x10]; 4781 4782 u8 reserved_at_20[0x10]; 4783 u8 op_mod[0x10]; 4784 4785 u8 embedded_cpu_function[0x1]; 4786 u8 reserved_at_41[0xf]; 4787 u8 function_id[0x10]; 4788 4789 u8 input_num_entries[0x20]; 4790 4791 u8 pas[][0x40]; 4792 }; 4793 4794 enum { 4795 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4796 }; 4797 4798 struct mlx5_ifc_teardown_hca_out_bits { 4799 u8 status[0x8]; 4800 u8 reserved_at_8[0x18]; 4801 4802 u8 syndrome[0x20]; 4803 4804 u8 reserved_at_40[0x3f]; 4805 4806 u8 state[0x1]; 4807 }; 4808 4809 enum { 4810 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4811 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4812 }; 4813 4814 struct mlx5_ifc_teardown_hca_in_bits { 4815 u8 opcode[0x10]; 4816 u8 reserved_at_10[0x10]; 4817 4818 u8 reserved_at_20[0x10]; 4819 u8 op_mod[0x10]; 4820 4821 u8 reserved_at_40[0x10]; 4822 u8 profile[0x10]; 4823 4824 u8 reserved_at_60[0x20]; 4825 }; 4826 4827 struct mlx5_ifc_init_hca_out_bits { 4828 u8 status[0x8]; 4829 u8 reserved_at_8[0x18]; 4830 4831 u8 syndrome[0x20]; 4832 4833 u8 reserved_at_40[0x40]; 4834 }; 4835 4836 struct mlx5_ifc_init_hca_in_bits { 4837 u8 opcode[0x10]; 4838 u8 reserved_at_10[0x10]; 4839 4840 u8 reserved_at_20[0x10]; 4841 u8 op_mod[0x10]; 4842 4843 u8 reserved_at_40[0x40]; 4844 }; 4845 4846 struct mlx5_ifc_access_register_out_bits { 4847 u8 status[0x8]; 4848 u8 reserved_at_8[0x18]; 4849 4850 u8 syndrome[0x20]; 4851 4852 u8 reserved_at_40[0x40]; 4853 4854 u8 register_data[][0x20]; 4855 }; 4856 4857 struct mlx5_ifc_access_register_in_bits { 4858 u8 opcode[0x10]; 4859 u8 reserved_at_10[0x10]; 4860 4861 u8 reserved_at_20[0x10]; 4862 u8 op_mod[0x10]; 4863 4864 u8 reserved_at_40[0x10]; 4865 u8 register_id[0x10]; 4866 4867 u8 argument[0x20]; 4868 4869 u8 register_data[][0x20]; 4870 }; 4871 4872 struct mlx5_ifc_modify_nic_vport_context_out_bits { 4873 u8 status[0x8]; 4874 u8 reserved_at_8[0x18]; 4875 4876 u8 syndrome[0x20]; 4877 4878 u8 reserved_at_40[0x40]; 4879 }; 4880 4881 struct mlx5_ifc_modify_nic_vport_field_select_bits { 4882 u8 reserved_at_0[0x12]; 4883 u8 affiliation[0x1]; 4884 u8 reserved_at_13[0x1]; 4885 u8 disable_uc_local_lb[0x1]; 4886 u8 disable_mc_local_lb[0x1]; 4887 u8 node_guid[0x1]; 4888 u8 port_guid[0x1]; 4889 u8 min_inline[0x1]; 4890 u8 mtu[0x1]; 4891 u8 change_event[0x1]; 4892 u8 promisc[0x1]; 4893 u8 permanent_address[0x1]; 4894 u8 addresses_list[0x1]; 4895 u8 roce_en[0x1]; 4896 u8 reserved_at_1f[0x1]; 4897 }; 4898 4899 struct mlx5_ifc_modify_nic_vport_context_in_bits { 4900 u8 opcode[0x10]; 4901 u8 reserved_at_10[0x10]; 4902 4903 u8 reserved_at_20[0x10]; 4904 u8 op_mod[0x10]; 4905 4906 u8 other_vport[0x1]; 4907 u8 reserved_at_41[0xf]; 4908 u8 vport_number[0x10]; 4909 4910 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 4911 4912 u8 reserved_at_80[0x780]; 4913 4914 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4915 }; 4916 4917 struct mlx5_ifc_set_hca_cap_out_bits { 4918 u8 status[0x8]; 4919 u8 reserved_at_8[0x18]; 4920 4921 u8 syndrome[0x20]; 4922 4923 u8 reserved_at_40[0x40]; 4924 }; 4925 4926 struct mlx5_ifc_set_hca_cap_in_bits { 4927 u8 opcode[0x10]; 4928 u8 reserved_at_10[0x10]; 4929 4930 u8 reserved_at_20[0x10]; 4931 u8 op_mod[0x10]; 4932 4933 u8 other_function[0x1]; 4934 u8 reserved_at_41[0xf]; 4935 u8 function_id[0x10]; 4936 4937 u8 reserved_at_60[0x20]; 4938 4939 union mlx5_ifc_hca_cap_union_bits capability; 4940 }; 4941 4942 struct mlx5_ifc_alloc_uar_out_bits { 4943 u8 status[0x8]; 4944 u8 reserved_at_8[0x18]; 4945 4946 u8 syndrome[0x20]; 4947 4948 u8 reserved_at_40[0x8]; 4949 u8 uar[0x18]; 4950 4951 u8 reserved_at_60[0x20]; 4952 }; 4953 4954 struct mlx5_ifc_alloc_uar_in_bits { 4955 u8 opcode[0x10]; 4956 u8 reserved_at_10[0x10]; 4957 4958 u8 reserved_at_20[0x10]; 4959 u8 op_mod[0x10]; 4960 4961 u8 reserved_at_40[0x40]; 4962 }; 4963 4964 struct mlx5_ifc_dealloc_uar_out_bits { 4965 u8 status[0x8]; 4966 u8 reserved_at_8[0x18]; 4967 4968 u8 syndrome[0x20]; 4969 4970 u8 reserved_at_40[0x40]; 4971 }; 4972 4973 struct mlx5_ifc_dealloc_uar_in_bits { 4974 u8 opcode[0x10]; 4975 u8 reserved_at_10[0x10]; 4976 4977 u8 reserved_at_20[0x10]; 4978 u8 op_mod[0x10]; 4979 4980 u8 reserved_at_40[0x8]; 4981 u8 uar[0x18]; 4982 4983 u8 reserved_at_60[0x20]; 4984 }; 4985 4986 struct mlx5_ifc_eqc_bits { 4987 u8 status[0x4]; 4988 u8 reserved_at_4[0x9]; 4989 u8 ec[0x1]; 4990 u8 oi[0x1]; 4991 u8 reserved_at_f[0x5]; 4992 u8 st[0x4]; 4993 u8 reserved_at_18[0x8]; 4994 4995 u8 reserved_at_20[0x20]; 4996 4997 u8 reserved_at_40[0x14]; 4998 u8 page_offset[0x6]; 4999 u8 reserved_at_5a[0x6]; 5000 5001 u8 reserved_at_60[0x3]; 5002 u8 log_eq_size[0x5]; 5003 u8 uar_page[0x18]; 5004 5005 u8 reserved_at_80[0x20]; 5006 5007 u8 reserved_at_a0[0x18]; 5008 u8 intr[0x8]; 5009 5010 u8 reserved_at_c0[0x3]; 5011 u8 log_page_size[0x5]; 5012 u8 reserved_at_c8[0x18]; 5013 5014 u8 reserved_at_e0[0x60]; 5015 5016 u8 reserved_at_140[0x8]; 5017 u8 consumer_counter[0x18]; 5018 5019 u8 reserved_at_160[0x8]; 5020 u8 producer_counter[0x18]; 5021 5022 u8 reserved_at_180[0x80]; 5023 }; 5024 5025 struct mlx5_ifc_create_eq_out_bits { 5026 u8 status[0x8]; 5027 u8 reserved_at_8[0x18]; 5028 5029 u8 syndrome[0x20]; 5030 5031 u8 reserved_at_40[0x18]; 5032 u8 eq_number[0x8]; 5033 5034 u8 reserved_at_60[0x20]; 5035 }; 5036 5037 struct mlx5_ifc_create_eq_in_bits { 5038 u8 opcode[0x10]; 5039 u8 uid[0x10]; 5040 5041 u8 reserved_at_20[0x10]; 5042 u8 op_mod[0x10]; 5043 5044 u8 reserved_at_40[0x40]; 5045 5046 struct mlx5_ifc_eqc_bits eq_context_entry; 5047 5048 u8 reserved_at_280[0x40]; 5049 5050 u8 event_bitmask[4][0x40]; 5051 5052 u8 reserved_at_3c0[0x4c0]; 5053 5054 u8 pas[][0x40]; 5055 }; 5056 5057 struct mlx5_ifc_destroy_eq_out_bits { 5058 u8 status[0x8]; 5059 u8 reserved_at_8[0x18]; 5060 5061 u8 syndrome[0x20]; 5062 5063 u8 reserved_at_40[0x40]; 5064 }; 5065 5066 struct mlx5_ifc_destroy_eq_in_bits { 5067 u8 opcode[0x10]; 5068 u8 reserved_at_10[0x10]; 5069 5070 u8 reserved_at_20[0x10]; 5071 u8 op_mod[0x10]; 5072 5073 u8 reserved_at_40[0x18]; 5074 u8 eq_number[0x8]; 5075 5076 u8 reserved_at_60[0x20]; 5077 }; 5078 5079 struct mlx5_ifc_alloc_pd_out_bits { 5080 u8 status[0x8]; 5081 u8 reserved_at_8[0x18]; 5082 5083 u8 syndrome[0x20]; 5084 5085 u8 reserved_at_40[0x8]; 5086 u8 pd[0x18]; 5087 5088 u8 reserved_at_60[0x20]; 5089 }; 5090 5091 struct mlx5_ifc_alloc_pd_in_bits { 5092 u8 opcode[0x10]; 5093 u8 uid[0x10]; 5094 5095 u8 reserved_at_20[0x10]; 5096 u8 op_mod[0x10]; 5097 5098 u8 reserved_at_40[0x40]; 5099 }; 5100 5101 struct mlx5_ifc_dealloc_pd_out_bits { 5102 u8 status[0x8]; 5103 u8 reserved_at_8[0x18]; 5104 5105 u8 syndrome[0x20]; 5106 5107 u8 reserved_at_40[0x40]; 5108 }; 5109 5110 struct mlx5_ifc_dealloc_pd_in_bits { 5111 u8 opcode[0x10]; 5112 u8 uid[0x10]; 5113 5114 u8 reserved_at_20[0x10]; 5115 u8 op_mod[0x10]; 5116 5117 u8 reserved_at_40[0x8]; 5118 u8 pd[0x18]; 5119 5120 u8 reserved_at_60[0x20]; 5121 }; 5122 5123 struct mlx5_ifc_mtt_bits { 5124 u8 ptag_63_32[0x20]; 5125 5126 u8 ptag_31_8[0x18]; 5127 u8 reserved_at_38[0x6]; 5128 u8 wr_en[0x1]; 5129 u8 rd_en[0x1]; 5130 }; 5131 5132 struct mlx5_ifc_umem_bits { 5133 u8 reserved_at_0[0x80]; 5134 5135 u8 reserved_at_80[0x1b]; 5136 u8 log_page_size[0x5]; 5137 5138 u8 page_offset[0x20]; 5139 5140 u8 num_of_mtt[0x40]; 5141 5142 struct mlx5_ifc_mtt_bits mtt[]; 5143 }; 5144 5145 struct mlx5_ifc_create_umem_in_bits { 5146 u8 opcode[0x10]; 5147 u8 uid[0x10]; 5148 5149 u8 reserved_at_20[0x10]; 5150 u8 op_mod[0x10]; 5151 5152 u8 reserved_at_40[0x40]; 5153 5154 struct mlx5_ifc_umem_bits umem; 5155 }; 5156 5157 struct mlx5_ifc_create_umem_out_bits { 5158 u8 status[0x8]; 5159 u8 reserved_at_8[0x18]; 5160 5161 u8 syndrome[0x20]; 5162 5163 u8 reserved_at_40[0x8]; 5164 u8 umem_id[0x18]; 5165 5166 u8 reserved_at_60[0x20]; 5167 }; 5168 5169 struct mlx5_ifc_destroy_umem_in_bits { 5170 u8 opcode[0x10]; 5171 u8 uid[0x10]; 5172 5173 u8 reserved_at_20[0x10]; 5174 u8 op_mod[0x10]; 5175 5176 u8 reserved_at_40[0x8]; 5177 u8 umem_id[0x18]; 5178 5179 u8 reserved_at_60[0x20]; 5180 }; 5181 5182 struct mlx5_ifc_destroy_umem_out_bits { 5183 u8 status[0x8]; 5184 u8 reserved_at_8[0x18]; 5185 5186 u8 syndrome[0x20]; 5187 5188 u8 reserved_at_40[0x40]; 5189 }; 5190 5191 struct mlx5_ifc_delete_fte_in_bits { 5192 u8 opcode[0x10]; 5193 u8 reserved_at_10[0x10]; 5194 5195 u8 reserved_at_20[0x20]; 5196 5197 u8 other_vport[0x1]; 5198 u8 reserved_at_41[0xf]; 5199 u8 vport_number[0x10]; 5200 5201 u8 reserved_at_60[0x20]; 5202 5203 u8 table_type[0x8]; 5204 u8 reserved_at_88[0x18]; 5205 5206 u8 reserved_at_a0[0x8]; 5207 u8 table_id[0x18]; 5208 5209 u8 reserved_at_c0[0x40]; 5210 5211 u8 flow_index[0x20]; 5212 5213 u8 reserved_at_120[0xe0]; 5214 }; 5215 5216 struct mlx5_ifc_create_cq_out_bits { 5217 u8 reserved_at_0[0x40]; 5218 5219 u8 reserved_at_40[0x8]; 5220 u8 cqn[0x18]; 5221 5222 u8 reserved_at_60[0x20]; 5223 }; 5224 5225 struct mlx5_ifc_destroy_cq_in_bits { 5226 u8 opcode[0x10]; 5227 u8 uid[0x10]; 5228 5229 u8 reserved_at_20[0x20]; 5230 5231 u8 reserved_at_40[0x8]; 5232 u8 cqn[0x18]; 5233 5234 u8 reserved_at_60[0x20]; 5235 }; 5236 5237 struct mlx5_ifc_alloc_transport_domain_out_bits { 5238 u8 reserved_at_0[0x40]; 5239 5240 u8 reserved_at_40[0x8]; 5241 u8 transport_domain[0x18]; 5242 5243 u8 reserved_at_60[0x20]; 5244 }; 5245 5246 struct mlx5_ifc_dealloc_transport_domain_in_bits { 5247 u8 opcode[0x10]; 5248 u8 uid[0x10]; 5249 5250 u8 reserved_at_20[0x20]; 5251 5252 u8 reserved_at_40[0x8]; 5253 u8 transport_domain[0x18]; 5254 5255 u8 reserved_at_60[0x20]; 5256 }; 5257 5258 struct mlx5_ifc_create_rmp_out_bits { 5259 u8 reserved_at_0[0x40]; 5260 5261 u8 reserved_at_40[0x8]; 5262 u8 rmpn[0x18]; 5263 5264 u8 reserved_at_60[0x20]; 5265 }; 5266 5267 struct mlx5_ifc_destroy_rmp_in_bits { 5268 u8 opcode[0x10]; 5269 u8 uid[0x10]; 5270 5271 u8 reserved_at_20[0x20]; 5272 5273 u8 reserved_at_40[0x8]; 5274 u8 rmpn[0x18]; 5275 5276 u8 reserved_at_60[0x20]; 5277 }; 5278 5279 struct mlx5_ifc_create_sq_out_bits { 5280 u8 reserved_at_0[0x40]; 5281 5282 u8 reserved_at_40[0x8]; 5283 u8 sqn[0x18]; 5284 5285 u8 reserved_at_60[0x20]; 5286 }; 5287 5288 struct mlx5_ifc_destroy_sq_in_bits { 5289 u8 opcode[0x10]; 5290 u8 uid[0x10]; 5291 5292 u8 reserved_at_20[0x20]; 5293 5294 u8 reserved_at_40[0x8]; 5295 u8 sqn[0x18]; 5296 5297 u8 reserved_at_60[0x20]; 5298 }; 5299 5300 struct mlx5_ifc_create_rq_out_bits { 5301 u8 reserved_at_0[0x40]; 5302 5303 u8 reserved_at_40[0x8]; 5304 u8 rqn[0x18]; 5305 5306 u8 reserved_at_60[0x20]; 5307 }; 5308 5309 struct mlx5_ifc_destroy_rq_in_bits { 5310 u8 opcode[0x10]; 5311 u8 uid[0x10]; 5312 5313 u8 reserved_at_20[0x20]; 5314 5315 u8 reserved_at_40[0x8]; 5316 u8 rqn[0x18]; 5317 5318 u8 reserved_at_60[0x20]; 5319 }; 5320 5321 struct mlx5_ifc_create_rqt_out_bits { 5322 u8 reserved_at_0[0x40]; 5323 5324 u8 reserved_at_40[0x8]; 5325 u8 rqtn[0x18]; 5326 5327 u8 reserved_at_60[0x20]; 5328 }; 5329 5330 struct mlx5_ifc_destroy_rqt_in_bits { 5331 u8 opcode[0x10]; 5332 u8 uid[0x10]; 5333 5334 u8 reserved_at_20[0x20]; 5335 5336 u8 reserved_at_40[0x8]; 5337 u8 rqtn[0x18]; 5338 5339 u8 reserved_at_60[0x20]; 5340 }; 5341 5342 struct mlx5_ifc_create_tis_out_bits { 5343 u8 reserved_at_0[0x40]; 5344 5345 u8 reserved_at_40[0x8]; 5346 u8 tisn[0x18]; 5347 5348 u8 reserved_at_60[0x20]; 5349 }; 5350 5351 struct mlx5_ifc_destroy_tis_in_bits { 5352 u8 opcode[0x10]; 5353 u8 uid[0x10]; 5354 5355 u8 reserved_at_20[0x20]; 5356 5357 u8 reserved_at_40[0x8]; 5358 u8 tisn[0x18]; 5359 5360 u8 reserved_at_60[0x20]; 5361 }; 5362 5363 struct mlx5_ifc_alloc_q_counter_out_bits { 5364 u8 reserved_at_0[0x40]; 5365 5366 u8 reserved_at_40[0x18]; 5367 u8 counter_set_id[0x8]; 5368 5369 u8 reserved_at_60[0x20]; 5370 }; 5371 5372 struct mlx5_ifc_dealloc_q_counter_in_bits { 5373 u8 opcode[0x10]; 5374 u8 reserved_at_10[0x10]; 5375 5376 u8 reserved_at_20[0x20]; 5377 5378 u8 reserved_at_40[0x18]; 5379 u8 counter_set_id[0x8]; 5380 5381 u8 reserved_at_60[0x20]; 5382 }; 5383 5384 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5385 u8 reserved_at_0[0x40]; 5386 5387 u8 modify_header_id[0x20]; 5388 5389 u8 reserved_at_60[0x20]; 5390 }; 5391 5392 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5393 u8 opcode[0x10]; 5394 u8 reserved_at_10[0x10]; 5395 5396 u8 reserved_at_20[0x20]; 5397 5398 u8 modify_header_id[0x20]; 5399 5400 u8 reserved_at_60[0x20]; 5401 }; 5402 5403 struct mlx5_ifc_create_scheduling_element_out_bits { 5404 u8 reserved_at_0[0x80]; 5405 5406 u8 scheduling_element_id[0x20]; 5407 5408 u8 reserved_at_a0[0x160]; 5409 }; 5410 5411 struct mlx5_ifc_create_scheduling_element_in_bits { 5412 u8 opcode[0x10]; 5413 u8 reserved_at_10[0x10]; 5414 5415 u8 reserved_at_20[0x20]; 5416 5417 u8 scheduling_hierarchy[0x8]; 5418 u8 reserved_at_48[0x18]; 5419 5420 u8 reserved_at_60[0x3a0]; 5421 }; 5422 5423 struct mlx5_ifc_destroy_scheduling_element_in_bits { 5424 u8 opcode[0x10]; 5425 u8 reserved_at_10[0x10]; 5426 5427 u8 reserved_at_20[0x20]; 5428 5429 u8 scheduling_hierarchy[0x8]; 5430 u8 reserved_at_48[0x18]; 5431 5432 u8 scheduling_element_id[0x20]; 5433 5434 u8 reserved_at_80[0x180]; 5435 }; 5436 5437 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 5438 u8 reserved_at_0[0x60]; 5439 5440 u8 reserved_at_60[0x10]; 5441 u8 vxlan_udp_port[0x10]; 5442 }; 5443 5444 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 5445 u8 opcode[0x10]; 5446 u8 reserved_at_10[0x10]; 5447 5448 u8 reserved_at_20[0x40]; 5449 5450 u8 reserved_at_60[0x10]; 5451 u8 vxlan_udp_port[0x10]; 5452 }; 5453 5454 struct mlx5_ifc_set_l2_table_entry_in_bits { 5455 u8 reserved_at_0[0xa0]; 5456 5457 u8 reserved_at_a0[0x8]; 5458 u8 table_index[0x18]; 5459 5460 u8 reserved_at_c0[0x140]; 5461 5462 }; 5463 5464 struct mlx5_ifc_delete_l2_table_entry_in_bits { 5465 u8 opcode[0x10]; 5466 u8 reserved_at_10[0x10]; 5467 5468 u8 reserved_at_20[0x80]; 5469 5470 u8 reserved_at_a0[0x8]; 5471 u8 table_index[0x18]; 5472 5473 u8 reserved_at_c0[0x140]; 5474 }; 5475 5476 struct mlx5_ifc_create_srq_out_bits { 5477 u8 reserved_at_0[0x40]; 5478 5479 u8 reserved_at_40[0x8]; 5480 u8 srqn[0x18]; 5481 5482 u8 reserved_at_60[0x20]; 5483 }; 5484 5485 struct mlx5_ifc_destroy_srq_in_bits { 5486 u8 opcode[0x10]; 5487 u8 uid[0x10]; 5488 5489 u8 reserved_at_20[0x20]; 5490 5491 u8 reserved_at_40[0x8]; 5492 u8 srqn[0x18]; 5493 5494 u8 reserved_at_60[0x20]; 5495 }; 5496 5497 struct mlx5_ifc_create_xrc_srq_out_bits { 5498 u8 reserved_at_0[0x40]; 5499 5500 u8 reserved_at_40[0x8]; 5501 u8 xrc_srqn[0x18]; 5502 5503 u8 reserved_at_60[0x20]; 5504 }; 5505 5506 struct mlx5_ifc_destroy_xrc_srq_in_bits { 5507 u8 opcode[0x10]; 5508 u8 uid[0x10]; 5509 5510 u8 reserved_at_20[0x20]; 5511 5512 u8 reserved_at_40[0x8]; 5513 u8 xrc_srqn[0x18]; 5514 5515 u8 reserved_at_60[0x20]; 5516 }; 5517 5518 struct mlx5_ifc_create_dct_out_bits { 5519 u8 reserved_at_0[0x40]; 5520 5521 u8 reserved_at_40[0x8]; 5522 u8 dctn[0x18]; 5523 5524 u8 ece[0x20]; 5525 }; 5526 5527 struct mlx5_ifc_destroy_dct_in_bits { 5528 u8 opcode[0x10]; 5529 u8 uid[0x10]; 5530 5531 u8 reserved_at_20[0x20]; 5532 5533 u8 reserved_at_40[0x8]; 5534 u8 dctn[0x18]; 5535 5536 u8 reserved_at_60[0x20]; 5537 }; 5538 5539 struct mlx5_ifc_create_xrq_out_bits { 5540 u8 reserved_at_0[0x40]; 5541 5542 u8 reserved_at_40[0x8]; 5543 u8 xrqn[0x18]; 5544 5545 u8 reserved_at_60[0x20]; 5546 }; 5547 5548 struct mlx5_ifc_destroy_xrq_in_bits { 5549 u8 opcode[0x10]; 5550 u8 uid[0x10]; 5551 5552 u8 reserved_at_20[0x20]; 5553 5554 u8 reserved_at_40[0x8]; 5555 u8 xrqn[0x18]; 5556 5557 u8 reserved_at_60[0x20]; 5558 }; 5559 5560 struct mlx5_ifc_attach_to_mcg_in_bits { 5561 u8 reserved_at_0[0x40]; 5562 5563 u8 reserved_at_40[0x8]; 5564 u8 qpn[0x18]; 5565 5566 u8 reserved_at_60[0x20]; 5567 5568 u8 multicast_gid[16][0x8]; 5569 }; 5570 5571 struct mlx5_ifc_detach_from_mcg_in_bits { 5572 u8 opcode[0x10]; 5573 u8 uid[0x10]; 5574 5575 u8 reserved_at_20[0x20]; 5576 5577 u8 reserved_at_40[0x8]; 5578 u8 qpn[0x18]; 5579 5580 u8 reserved_at_60[0x20]; 5581 5582 u8 multicast_gid[16][0x8]; 5583 }; 5584 5585 struct mlx5_ifc_alloc_xrcd_out_bits { 5586 u8 reserved_at_0[0x40]; 5587 5588 u8 reserved_at_40[0x8]; 5589 u8 xrcd[0x18]; 5590 5591 u8 reserved_at_60[0x20]; 5592 }; 5593 5594 struct mlx5_ifc_dealloc_xrcd_in_bits { 5595 u8 opcode[0x10]; 5596 u8 uid[0x10]; 5597 5598 u8 reserved_at_20[0x20]; 5599 5600 u8 reserved_at_40[0x8]; 5601 u8 xrcd[0x18]; 5602 5603 u8 reserved_at_60[0x20]; 5604 }; 5605 5606 enum { 5607 MLX5_CRYPTO_LOGIN_OBJ_STATE_VALID = 0x0, 5608 MLX5_CRYPTO_LOGIN_OBJ_STATE_INVALID = 0x1, 5609 }; 5610 5611 struct mlx5_ifc_crypto_login_obj_bits { 5612 u8 modify_field_select[0x40]; 5613 5614 u8 reserved_at_40[0x40]; 5615 5616 u8 reserved_at_80[0x4]; 5617 u8 state[0x4]; 5618 u8 credential_pointer[0x18]; 5619 5620 u8 reserved_at_a0[0x8]; 5621 u8 session_import_kek_ptr[0x18]; 5622 5623 u8 reserved_at_c0[0x140]; 5624 5625 u8 credential[12][0x20]; 5626 5627 u8 reserved_at_380[0x480]; 5628 }; 5629 5630 struct mlx5_ifc_create_crypto_login_obj_in_bits { 5631 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 5632 struct mlx5_ifc_crypto_login_obj_bits login_obj; 5633 }; 5634 5635 struct mlx5_ifc_query_crypto_login_obj_out_bits { 5636 struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr; 5637 struct mlx5_ifc_crypto_login_obj_bits obj; 5638 }; 5639 5640 enum { 5641 MLX5_ENCRYPTION_KEY_OBJ_STATE_READY = 0x0, 5642 MLX5_ENCRYPTION_KEY_OBJ_STATE_ERROR = 0x1, 5643 }; 5644 5645 enum { 5646 MLX5_ENCRYPTION_KEY_OBJ_KEY_SIZE_SIZE_128 = 0x0, 5647 MLX5_ENCRYPTION_KEY_OBJ_KEY_SIZE_SIZE_256 = 0x1, 5648 }; 5649 5650 enum { 5651 MLX5_ENCRYPTION_KEY_OBJ_KEY_PURPOSE_AES_XTS = 0x3, 5652 }; 5653 5654 struct mlx5_ifc_encryption_key_obj_bits { 5655 u8 modify_field_select[0x40]; 5656 5657 u8 state[0x8]; 5658 u8 reserved_at_48[0xc]; 5659 u8 key_size[0x4]; 5660 u8 has_keytag[0x1]; 5661 u8 reserved_at_59[0x3]; 5662 u8 key_purpose[0x4]; 5663 5664 u8 reserved_at_60[0x8]; 5665 u8 pd[0x18]; 5666 5667 u8 reserved_at_80[0x100]; 5668 5669 u8 opaque[0x40]; 5670 5671 u8 reserved_at_1c0[0x40]; 5672 5673 u8 key[32][0x20]; 5674 5675 u8 reserved_at_600[0x200]; 5676 }; 5677 5678 struct mlx5_ifc_create_encryption_key_obj_in_bits { 5679 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 5680 struct mlx5_ifc_encryption_key_obj_bits key_obj; 5681 }; 5682 5683 struct mlx5_ifc_query_encryption_key_obj_out_bits { 5684 struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr; 5685 struct mlx5_ifc_encryption_key_obj_bits obj; 5686 }; 5687 5688 enum { 5689 MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0, 5690 MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1, 5691 MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2, 5692 MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3, 5693 }; 5694 5695 enum { 5696 MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0, 5697 }; 5698 5699 #endif /* MLX5_IFC_H */ 5700