1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) Intel Corporation. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /** 35 * \file 36 * IDXD specification definitions 37 */ 38 39 #ifndef SPDK_IDXD_SPEC_H 40 #define SPDK_IDXD_SPEC_H 41 42 #include "spdk/stdinc.h" 43 #include "spdk/assert.h" 44 45 #ifdef __cplusplus 46 extern "C" { 47 #endif 48 49 #define IDXD_MMIO_BAR 0 50 #define IDXD_WQ_BAR 2 51 #define PORTAL_SIZE 0x1000 52 #define WQ_TOTAL_PORTAL_SIZE (PORTAL_SIZE * 4) 53 #define PORTAL_STRIDE 0x40 54 #define PORTAL_MASK (PORTAL_SIZE - 1) 55 #define WQCFG_SHIFT 5 56 57 #define IDXD_TABLE_OFFSET_MULT 0x100 58 59 #define IDXD_CLEAR_CRC_FLAGS 0xFFFFu 60 61 #define IDXD_FLAG_FENCE (1 << 0) 62 #define IDXD_FLAG_COMPLETION_ADDR_VALID (1 << 2) 63 #define IDXD_FLAG_REQUEST_COMPLETION (1 << 3) 64 #define IDXD_FLAG_CACHE_CONTROL (1 << 8) 65 #define IDXD_FLAG_DEST_STEERING_TAG (1 << 15) 66 #define IDXD_FLAG_CRC_READ_CRC_SEED (1 << 16) 67 68 /* 69 * IDXD is a family of devices, DSA is the only currently 70 * supported one. 71 */ 72 enum dsa_completion_status { 73 IDXD_COMP_NONE = 0, 74 IDXD_COMP_SUCCESS = 1, 75 IDXD_COMP_SUCCESS_PRED = 2, 76 IDXD_COMP_PAGE_FAULT_NOBOF = 3, 77 IDXD_COMP_PAGE_FAULT_IR = 4, 78 IDXD_COMP_BATCH_FAIL = 5, 79 IDXD_COMP_BATCH_PAGE_FAULT = 6, 80 IDXD_COMP_DR_OFFSET_NOINC = 7, 81 IDXD_COMP_DR_OFFSET_ERANGE = 8, 82 IDXD_COMP_DIF_ERR = 9, 83 IDXD_COMP_BAD_OPCODE = 16, 84 IDXD_COMP_INVALID_FLAGS = 17, 85 IDXD_COMP_NOZERO_RESERVE = 18, 86 IDXD_COMP_XFER_ERANGE = 19, 87 IDXD_COMP_DESC_CNT_ERANGE = 20, 88 IDXD_COMP_DR_ERANGE = 21, 89 IDXD_COMP_OVERLAP_BUFFERS = 22, 90 IDXD_COMP_DCAST_ERR = 23, 91 IDXD_COMP_DESCLIST_ALIGN = 24, 92 IDXD_COMP_INT_HANDLE_INVAL = 25, 93 IDXD_COMP_CRA_XLAT = 26, 94 IDXD_COMP_CRA_ALIGN = 27, 95 IDXD_COMP_ADDR_ALIGN = 28, 96 IDXD_COMP_PRIV_BAD = 29, 97 IDXD_COMP_TRAFFIC_CLASS_CONF = 30, 98 IDXD_COMP_PFAULT_RDBA = 31, 99 IDXD_COMP_HW_ERR1 = 32, 100 IDXD_COMP_HW_ERR_DRB = 33, 101 IDXD_COMP_TRANSLATION_FAIL = 34, 102 }; 103 104 enum idxd_wq_state { 105 WQ_DISABLED = 0, 106 WQ_ENABLED = 1, 107 }; 108 109 enum idxd_wq_flag { 110 WQ_FLAG_DEDICATED = 0, 111 WQ_FLAG_BOF = 1, 112 }; 113 114 enum idxd_wq_type { 115 WQT_NONE = 0, 116 WQT_KERNEL = 1, 117 WQT_USER = 2, 118 WQT_MDEV = 3, 119 }; 120 121 enum idxd_dev_state { 122 IDXD_DEVICE_STATE_DISABLED = 0, 123 IDXD_DEVICE_STATE_ENABLED = 1, 124 IDXD_DEVICE_STATE_DRAIN = 2, 125 IDXD_DEVICE_STATE_HALT = 3, 126 }; 127 128 enum idxd_device_reset_type { 129 IDXD_DEVICE_RESET_SOFTWARE = 0, 130 IDXD_DEVICE_RESET_FLR = 1, 131 IDXD_DEVICE_RESET_WARM = 2, 132 IDXD_DEVICE_RESET_COLD = 3, 133 }; 134 135 enum idxd_cmds { 136 IDXD_ENABLE_DEV = 1, 137 IDXD_DISABLE_DEV = 2, 138 IDXD_DRAIN_ALL = 3, 139 IDXD_ABORT_ALL = 4, 140 IDXD_RESET_DEVICE = 5, 141 IDXD_ENABLE_WQ = 6, 142 IDXD_DISABLE_WQ = 7, 143 IDXD_DRAIN_WQ = 8, 144 IDXD_ABORT_WQ = 9, 145 IDXD_RESET_WQ = 10, 146 }; 147 148 enum idxd_cmdsts_err { 149 IDXD_CMDSTS_SUCCESS = 0, 150 IDXD_CMDSTS_INVAL_CMD = 1, 151 IDXD_CMDSTS_INVAL_WQIDX = 2, 152 IDXD_CMDSTS_HW_ERR = 3, 153 IDXD_CMDSTS_ERR_DEV_ENABLED = 16, 154 IDXD_CMDSTS_ERR_CONFIG = 17, 155 IDXD_CMDSTS_ERR_BUSMASTER_EN = 18, 156 IDXD_CMDSTS_ERR_PASID_INVAL = 19, 157 IDXD_CMDSTS_ERR_WQ_SIZE_ERANGE = 20, 158 IDXD_CMDSTS_ERR_GRP_CONFIG = 21, 159 IDXD_CMDSTS_ERR_GRP_CONFIG2 = 22, 160 IDXD_CMDSTS_ERR_GRP_CONFIG3 = 23, 161 IDXD_CMDSTS_ERR_GRP_CONFIG4 = 24, 162 IDXD_CMDSTS_ERR_DEV_NOTEN = 32, 163 IDXD_CMDSTS_ERR_WQ_ENABLED = 33, 164 IDXD_CMDSTS_ERR_WQ_SIZE = 34, 165 IDXD_CMDSTS_ERR_WQ_PRIOR = 35, 166 IDXD_CMDSTS_ERR_WQ_MODE = 36, 167 IDXD_CMDSTS_ERR_BOF_EN = 37, 168 IDXD_CMDSTS_ERR_PASID_EN = 38, 169 IDXD_CMDSTS_ERR_MAX_BATCH_SIZE = 39, 170 IDXD_CMDSTS_ERR_MAX_XFER_SIZE = 40, 171 IDXD_CMDSTS_ERR_DIS_DEV_EN = 49, 172 IDXD_CMDSTS_ERR_DEV_NOT_EN = 50, 173 IDXD_CMDSTS_ERR_INVAL_INT_IDX = 65, 174 IDXD_CMDSTS_ERR_NO_HANDLE = 66, 175 }; 176 177 enum idxd_wq_hw_state { 178 IDXD_WQ_DEV_DISABLED = 0, 179 IDXD_WQ_DEV_ENABLED = 1, 180 IDXD_WQ_DEV_BUSY = 2, 181 }; 182 183 struct idxd_hw_desc { 184 uint32_t pasid: 20; 185 uint32_t rsvd: 11; 186 uint32_t priv: 1; 187 uint32_t flags: 24; 188 uint32_t opcode: 8; 189 uint64_t completion_addr; 190 union { 191 uint64_t src_addr; 192 uint64_t readback_addr; 193 uint64_t pattern; 194 uint64_t desc_list_addr; 195 }; 196 union { 197 uint64_t dst_addr; 198 uint64_t readback_addr2; 199 uint64_t src2_addr; 200 uint64_t comp_pattern; 201 }; 202 union { 203 uint32_t xfer_size; 204 uint32_t desc_count; 205 }; 206 uint16_t int_handle; 207 uint16_t rsvd1; 208 union { 209 uint8_t expected_res; 210 struct { 211 uint64_t addr; 212 uint32_t max_size; 213 } delta; 214 uint32_t delta_rec_size; 215 uint64_t dest2; 216 struct { 217 uint32_t seed; 218 uint32_t rsvd; 219 uint64_t addr; 220 } crc32c; 221 struct { 222 uint8_t src_flags; 223 uint8_t rsvd1; 224 uint8_t flags; 225 uint8_t rsvd2[5]; 226 uint32_t ref_tag_seed; 227 uint16_t app_tag_mask; 228 uint16_t app_tag_seed; 229 } dif_chk; 230 struct { 231 uint8_t rsvd1; 232 uint8_t dest_flag; 233 uint8_t flags; 234 uint8_t rsvd2[13]; 235 uint32_t ref_tag_seed; 236 uint16_t app_tag_mask; 237 uint16_t app_tag_seed; 238 } dif_ins; 239 struct { 240 uint8_t src_flags; 241 uint8_t dest_flags; 242 uint8_t flags; 243 uint8_t rsvd[5]; 244 uint32_t src_ref_tag_seed; 245 uint16_t src_app_tag_mask; 246 uint16_t src_app_tag_seed; 247 uint32_t dest_ref_tag_seed; 248 uint16_t dest_app_tag_mask; 249 uint16_t dest_app_tag_seed; 250 } dif_upd; 251 uint8_t op_specific[24]; 252 }; 253 } __attribute((aligned(64))); 254 SPDK_STATIC_ASSERT(sizeof(struct idxd_hw_desc) == 64, "size mismatch"); 255 256 struct idxd_hw_comp_record { 257 volatile uint8_t status; 258 union { 259 uint8_t result; 260 uint8_t dif_status; 261 }; 262 uint16_t rsvd; 263 uint32_t bytes_completed; 264 uint64_t fault_addr; 265 union { 266 uint32_t delta_rec_size; 267 uint32_t crc32c_val; 268 struct { 269 uint32_t dif_chk_ref_tag; 270 uint16_t dif_chk_app_tag_mask; 271 uint16_t dif_chk_app_tag; 272 }; 273 struct { 274 uint64_t rsvd; 275 uint32_t ref_tag; 276 uint16_t app_tag_mask; 277 uint16_t app_tag; 278 } dif_ins_comp; 279 struct { 280 uint32_t src_ref_tag; 281 uint16_t src_app_tag_mask; 282 uint16_t src_app_tag; 283 uint32_t dest_ref_tag; 284 uint16_t dest_app_tag_mask; 285 uint16_t dest_app_tag; 286 } dif_upd_comp; 287 uint8_t op_specific[16]; 288 }; 289 }; 290 SPDK_STATIC_ASSERT(sizeof(struct idxd_hw_comp_record) == 32, "size mismatch"); 291 292 union idxd_gencap_register { 293 struct { 294 uint64_t block_on_fault: 1; 295 uint64_t overlap_copy: 1; 296 uint64_t cache_control_mem: 1; 297 uint64_t cache_control_cache: 1; 298 uint64_t command_cap: 1; 299 uint64_t rsvd: 3; 300 uint64_t dest_readback: 1; 301 uint64_t drain_readback: 1; 302 uint64_t rsvd2: 6; 303 uint64_t max_xfer_shift: 5; 304 uint64_t max_batch_shift: 4; 305 uint64_t max_ims_mult: 6; 306 uint64_t config_support: 1; 307 uint64_t rsvd3: 32; 308 }; 309 uint64_t raw; 310 }; 311 SPDK_STATIC_ASSERT(sizeof(union idxd_gencap_register) == 8, "size mismatch"); 312 313 union idxd_wqcap_register { 314 struct { 315 uint64_t total_wq_size: 16; 316 uint64_t num_wqs: 8; 317 uint64_t wqcfg_size: 4; 318 uint64_t rsvd: 20; 319 uint64_t shared_mode: 1; 320 uint64_t dedicated_mode: 1; 321 uint64_t ats_support: 1; 322 uint64_t priority: 1; 323 uint64_t occupancy: 1; 324 uint64_t occupancy_int: 1; 325 uint64_t rsvd1: 10; 326 }; 327 uint64_t raw; 328 }; 329 SPDK_STATIC_ASSERT(sizeof(union idxd_wqcap_register) == 8, "size mismatch"); 330 331 union idxd_groupcap_register { 332 struct { 333 uint64_t num_groups: 8; 334 uint64_t read_bufs: 8; 335 uint64_t read_bufs_ctrl: 1; 336 uint64_t read_bus_limit: 1; 337 uint64_t rsvd: 46; 338 }; 339 uint64_t raw; 340 }; 341 SPDK_STATIC_ASSERT(sizeof(union idxd_groupcap_register) == 8, "size mismatch"); 342 343 union idxd_enginecap_register { 344 struct { 345 uint64_t num_engines: 8; 346 uint64_t rsvd: 56; 347 }; 348 uint64_t raw; 349 }; 350 SPDK_STATIC_ASSERT(sizeof(union idxd_enginecap_register) == 8, "size mismatch"); 351 352 struct idxd_opcap_register { 353 uint64_t raw[4]; 354 }; 355 SPDK_STATIC_ASSERT(sizeof(struct idxd_opcap_register) == 32, "size mismatch"); 356 357 union idxd_offsets_register { 358 struct { 359 uint64_t grpcfg: 16; 360 uint64_t wqcfg: 16; 361 uint64_t msix_perm: 16; 362 uint64_t ims: 16; 363 uint64_t perfmon: 16; 364 uint64_t rsvd: 48; 365 }; 366 uint64_t raw[2]; 367 }; 368 SPDK_STATIC_ASSERT(sizeof(union idxd_offsets_register) == 16, "size mismatch"); 369 370 union idxd_gencfg_register { 371 struct { 372 uint8_t global_read_buf_limit; 373 uint8_t reserved0 : 4; 374 uint8_t user_mode_int_enabled : 1; 375 uint8_t reserved1 : 3; 376 uint16_t reserved2; 377 }; 378 uint32_t raw; 379 }; 380 SPDK_STATIC_ASSERT(sizeof(union idxd_gencfg_register) == 4, "size mismatch"); 381 382 union idxd_genctrl_register { 383 struct { 384 uint32_t sw_err_int_enable : 1; 385 uint32_t halt_state_int_enable : 1; 386 uint32_t reserved : 30; 387 }; 388 uint32_t raw; 389 }; 390 SPDK_STATIC_ASSERT(sizeof(union idxd_genctrl_register) == 4, "size mismatch"); 391 392 union idxd_gensts_register { 393 struct { 394 uint32_t state: 2; 395 uint32_t reset_type: 2; 396 uint32_t rsvd: 28; 397 }; 398 uint32_t raw; 399 }; 400 SPDK_STATIC_ASSERT(sizeof(union idxd_gensts_register) == 4, "size mismatch"); 401 402 union idxd_intcause_register { 403 struct { 404 uint32_t software_err : 1; 405 uint32_t command_completion : 1; 406 uint32_t wq_occupancy_below_limit : 1; 407 uint32_t perfmon_counter_overflow : 1; 408 uint32_t halt_state : 1; 409 uint32_t reserved : 26; 410 uint32_t int_handles_revoked : 1; 411 }; 412 uint32_t raw; 413 }; 414 SPDK_STATIC_ASSERT(sizeof(union idxd_intcause_register) == 4, "size mismatch"); 415 416 union idxd_cmd_register { 417 struct { 418 uint32_t operand : 20; 419 uint32_t command_code : 5; 420 uint32_t reserved : 6; 421 uint32_t request_completion_interrupt : 1; 422 }; 423 uint32_t raw; 424 }; 425 SPDK_STATIC_ASSERT(sizeof(union idxd_cmd_register) == 4, "size mismatch"); 426 427 union idxd_cmdsts_register { 428 struct { 429 uint32_t err : 8; 430 uint32_t result : 16; 431 uint32_t rsvd: 7; 432 uint32_t active: 1; 433 }; 434 uint32_t raw; 435 }; 436 SPDK_STATIC_ASSERT(sizeof(union idxd_cmdsts_register) == 4, "size mismatch"); 437 438 union idxd_cmdcap_register { 439 struct { 440 uint32_t reserved0 : 1; 441 uint32_t enable_device : 1; 442 uint32_t disable_device : 1; 443 uint32_t drain_all : 1; 444 uint32_t abort_all : 1; 445 uint32_t reset_device : 1; 446 uint32_t enable_wq : 1; 447 uint32_t disable_wq : 1; 448 uint32_t drain_wq : 1; 449 uint32_t abort_wq : 1; 450 uint32_t reset_wq : 1; 451 uint32_t drain_pasid : 1; 452 uint32_t abort_pasid : 1; 453 uint32_t request_int_handle : 1; 454 uint32_t release_int_handle : 1; 455 uint32_t reserved1 : 17; 456 }; 457 uint32_t raw; 458 }; 459 SPDK_STATIC_ASSERT(sizeof(union idxd_cmdcap_register) == 4, "size mismatch"); 460 461 union idxd_swerr_register { 462 struct { 463 uint64_t valid: 1; 464 uint64_t overflow: 1; 465 uint64_t desc_valid: 1; 466 uint64_t wq_idx_valid: 1; 467 uint64_t batch: 1; 468 uint64_t fault_rw: 1; 469 uint64_t priv: 1; 470 uint64_t rsvd: 1; 471 uint64_t error: 8; 472 uint64_t wq_idx: 8; 473 uint64_t rsvd2: 8; 474 uint64_t operation: 8; 475 uint64_t pasid: 20; 476 uint64_t rsvd3: 4; 477 uint64_t batch_idx: 16; 478 uint64_t rsvd4: 16; 479 uint64_t invalid_flags: 32; 480 uint64_t fault_addr; 481 uint64_t rsvd5; 482 }; 483 uint64_t raw[4]; 484 }; 485 SPDK_STATIC_ASSERT(sizeof(union idxd_swerr_register) == 32, "size mismatch"); 486 487 struct idxd_registers { 488 uint32_t version; 489 uint32_t reserved0; 490 uint64_t reserved1; 491 union idxd_gencap_register gencap; 492 uint64_t reserved2; 493 union idxd_wqcap_register wqcap; 494 uint64_t reserved3; 495 union idxd_groupcap_register groupcap; 496 union idxd_enginecap_register enginecap; 497 struct idxd_opcap_register opcap; 498 union idxd_offsets_register offsets; 499 uint64_t reserved4[2]; 500 union idxd_gencfg_register gencfg; 501 uint32_t reserved5; 502 union idxd_genctrl_register genctrl; 503 uint32_t reserved6; 504 union idxd_gensts_register gensts; 505 uint32_t reserved7; 506 union idxd_intcause_register intcause; 507 uint32_t reserved8; 508 union idxd_cmd_register cmd; 509 uint32_t reserved9; 510 union idxd_cmdsts_register cmdsts; 511 uint32_t reserved10; 512 union idxd_cmdcap_register cmdcap; 513 uint32_t reserved11; 514 uint64_t reserved12; 515 union idxd_swerr_register sw_err; 516 }; 517 SPDK_STATIC_ASSERT(sizeof(struct idxd_registers) == 0xE0, "size mismatch"); 518 519 union idxd_group_flags { 520 struct { 521 uint32_t tc_a : 3; 522 uint32_t tc_b : 3; 523 uint32_t reserved0 : 1; 524 uint32_t global_read_buffer_limit: 1; 525 uint32_t read_buffers_reserved : 8; 526 uint32_t reserved1: 4; 527 uint32_t read_buffers_allowed : 8; 528 uint32_t reserved2 : 4; 529 }; 530 uint32_t raw; 531 }; 532 SPDK_STATIC_ASSERT(sizeof(union idxd_group_flags) == 4, "size mismatch"); 533 534 struct idxd_grpcfg { 535 uint64_t wqs[4]; 536 uint64_t engines; 537 union idxd_group_flags flags; 538 539 /* This is not part of the definition, but in practice the stride in the table 540 * is 64 bytes. */ 541 uint32_t reserved0; 542 uint64_t reserved1[2]; 543 }; 544 SPDK_STATIC_ASSERT(sizeof(struct idxd_grpcfg) == 64, "size mismatch"); 545 546 struct idxd_grptbl { 547 struct idxd_grpcfg group[1]; 548 }; 549 550 union idxd_wqcfg { 551 struct { 552 uint16_t wq_size; 553 uint16_t rsvd; 554 uint16_t wq_thresh; 555 uint16_t rsvd1; 556 uint32_t mode: 1; 557 uint32_t bof: 1; 558 uint32_t wq_ats_disable: 1; 559 uint32_t rsvd2: 1; 560 uint32_t priority: 4; 561 uint32_t pasid: 20; 562 uint32_t pasid_en: 1; 563 uint32_t priv: 1; 564 uint32_t rsvd3: 2; 565 uint32_t max_xfer_shift: 5; 566 uint32_t max_batch_shift: 4; 567 uint32_t rsvd4: 23; 568 uint16_t occupancy_inth; 569 uint16_t occupancy_table_sel: 1; 570 uint16_t rsvd5: 15; 571 uint16_t occupancy_limit; 572 uint16_t occupancy_int_en: 1; 573 uint16_t rsvd6: 15; 574 uint16_t occupancy; 575 uint16_t occupancy_int: 1; 576 uint16_t rsvd7: 12; 577 uint16_t mode_support: 1; 578 uint16_t wq_state: 2; 579 uint32_t rsvd8; 580 }; 581 uint32_t raw[8]; 582 }; 583 SPDK_STATIC_ASSERT(sizeof(union idxd_wqcfg) == 32, "size mismatch"); 584 585 #ifdef __cplusplus 586 } 587 #endif 588 589 #endif /* SPDK_IDXD_SPEC_H */ 590