1*3de6a9c0SDavid du Colombier /* override default macros from ../port/usb.h */ 2*3de6a9c0SDavid du Colombier #undef dprint 3*3de6a9c0SDavid du Colombier #undef ddprint 4*3de6a9c0SDavid du Colombier #undef deprint 5*3de6a9c0SDavid du Colombier #undef ddeprint 6*3de6a9c0SDavid du Colombier #define dprint if(ehcidebug)print 7*3de6a9c0SDavid du Colombier #define ddprint if(ehcidebug>1)print 8*3de6a9c0SDavid du Colombier #define deprint if(ehcidebug || ep->debug)print 9*3de6a9c0SDavid du Colombier #define ddeprint if(ehcidebug>1 || ep->debug>1)print 10*3de6a9c0SDavid du Colombier 11*3de6a9c0SDavid du Colombier typedef struct Ctlr Ctlr; 12*3de6a9c0SDavid du Colombier typedef struct Eopio Eopio; 13*3de6a9c0SDavid du Colombier typedef struct Isoio Isoio; 14*3de6a9c0SDavid du Colombier typedef struct Poll Poll; 15*3de6a9c0SDavid du Colombier typedef struct Qh Qh; 16*3de6a9c0SDavid du Colombier typedef struct Qtree Qtree; 17*3de6a9c0SDavid du Colombier 18*3de6a9c0SDavid du Colombier #pragma incomplete Ctlr; 19*3de6a9c0SDavid du Colombier #pragma incomplete Eopio; 20*3de6a9c0SDavid du Colombier #pragma incomplete Isoio; 21*3de6a9c0SDavid du Colombier #pragma incomplete Poll; 22*3de6a9c0SDavid du Colombier #pragma incomplete Qh; 23*3de6a9c0SDavid du Colombier #pragma incomplete Qtree; 24*3de6a9c0SDavid du Colombier 25*3de6a9c0SDavid du Colombier struct Poll 26*3de6a9c0SDavid du Colombier { 27*3de6a9c0SDavid du Colombier Lock; 28*3de6a9c0SDavid du Colombier Rendez; 29*3de6a9c0SDavid du Colombier int must; 30*3de6a9c0SDavid du Colombier int does; 31*3de6a9c0SDavid du Colombier }; 32*3de6a9c0SDavid du Colombier 33*3de6a9c0SDavid du Colombier struct Ctlr 34*3de6a9c0SDavid du Colombier { 35*3de6a9c0SDavid du Colombier Rendez; /* for waiting to async advance doorbell */ 36*3de6a9c0SDavid du Colombier Lock; /* for ilock. qh lists and basic ctlr I/O */ 37*3de6a9c0SDavid du Colombier QLock portlck; /* for port resets/enable... (and doorbell) */ 38*3de6a9c0SDavid du Colombier int active; /* in use or not */ 39*3de6a9c0SDavid du Colombier Ecapio* capio; /* Capability i/o regs */ 40*3de6a9c0SDavid du Colombier Eopio* opio; /* Operational i/o regs */ 41*3de6a9c0SDavid du Colombier 42*3de6a9c0SDavid du Colombier int nframes; /* 1024, 512, or 256 frames in the list */ 43*3de6a9c0SDavid du Colombier ulong* frames; /* periodic frame list (hw) */ 44*3de6a9c0SDavid du Colombier Qh* qhs; /* async Qh circular list for bulk/ctl */ 45*3de6a9c0SDavid du Colombier Qtree* tree; /* tree of Qhs for the periodic list */ 46*3de6a9c0SDavid du Colombier int ntree; /* number of dummy qhs in tree */ 47*3de6a9c0SDavid du Colombier Qh* intrqhs; /* list of (not dummy) qhs in tree */ 48*3de6a9c0SDavid du Colombier Isoio* iso; /* list of active Iso I/O */ 49*3de6a9c0SDavid du Colombier ulong load; 50*3de6a9c0SDavid du Colombier ulong isoload; 51*3de6a9c0SDavid du Colombier int nintr; /* number of interrupts attended */ 52*3de6a9c0SDavid du Colombier int ntdintr; /* number of intrs. with something to do */ 53*3de6a9c0SDavid du Colombier int nqhintr; /* number of async td intrs. */ 54*3de6a9c0SDavid du Colombier int nisointr; /* number of periodic td intrs. */ 55*3de6a9c0SDavid du Colombier int nreqs; 56*3de6a9c0SDavid du Colombier Poll poll; 57*3de6a9c0SDavid du Colombier }; 58*3de6a9c0SDavid du Colombier 59*3de6a9c0SDavid du Colombier /* 60*3de6a9c0SDavid du Colombier * Operational registers (hw) 61*3de6a9c0SDavid du Colombier */ 62*3de6a9c0SDavid du Colombier struct Eopio 63*3de6a9c0SDavid du Colombier { 64*3de6a9c0SDavid du Colombier ulong cmd; /* 00 command */ 65*3de6a9c0SDavid du Colombier ulong sts; /* 04 status */ 66*3de6a9c0SDavid du Colombier ulong intr; /* 08 interrupt enable */ 67*3de6a9c0SDavid du Colombier ulong frno; /* 0c frame index */ 68*3de6a9c0SDavid du Colombier ulong seg; /* 10 bits 63:32 of EHCI datastructs (unused) */ 69*3de6a9c0SDavid du Colombier ulong frbase; /* 14 frame list base addr, 4096-byte boundary */ 70*3de6a9c0SDavid du Colombier ulong link; /* 18 link for async list */ 71*3de6a9c0SDavid du Colombier uchar d2c[0x40-0x1c]; /* 1c dummy */ 72*3de6a9c0SDavid du Colombier ulong config; /* 40 1: all ports default-routed to this HC */ 73*3de6a9c0SDavid du Colombier ulong portsc[3]; /* 44 Port status and control, one per port */ 74*3de6a9c0SDavid du Colombier 75*3de6a9c0SDavid du Colombier /* defined for omap35 ehci at least */ 76*3de6a9c0SDavid du Colombier uchar _pad0[0x80 - 0x50]; 77*3de6a9c0SDavid du Colombier ulong insn[6]; /* implementation-specific */ 78*3de6a9c0SDavid du Colombier }; 79*3de6a9c0SDavid du Colombier 80*3de6a9c0SDavid du Colombier extern Ecapio *ehcidebugcapio; 81*3de6a9c0SDavid du Colombier extern int ehcidebugport; 82*3de6a9c0SDavid du Colombier 83*3de6a9c0SDavid du Colombier extern int ehcidebug; 84*3de6a9c0SDavid du Colombier 85*3de6a9c0SDavid du Colombier void ehcilinkage(Hci *hp); 86*3de6a9c0SDavid du Colombier void ehcimeminit(Ctlr *ctlr); 87*3de6a9c0SDavid du Colombier void ehcirun(Ctlr *ctlr, int on); 88