1*84860c5dSDavid du Colombier /* override default macros from ../port/usb.h */ 2*84860c5dSDavid du Colombier #undef dprint 3*84860c5dSDavid du Colombier #undef ddprint 4*84860c5dSDavid du Colombier #undef deprint 5*84860c5dSDavid du Colombier #undef ddeprint 6*84860c5dSDavid du Colombier #define dprint if(ehcidebug)print 7*84860c5dSDavid du Colombier #define ddprint if(ehcidebug>1)print 8*84860c5dSDavid du Colombier #define deprint if(ehcidebug || ep->debug)print 9*84860c5dSDavid du Colombier #define ddeprint if(ehcidebug>1 || ep->debug>1)print 10*84860c5dSDavid du Colombier 11*84860c5dSDavid du Colombier typedef struct Ctlr Ctlr; 12*84860c5dSDavid du Colombier typedef struct Eopio Eopio; 13*84860c5dSDavid du Colombier typedef struct Isoio Isoio; 14*84860c5dSDavid du Colombier typedef struct Poll Poll; 15*84860c5dSDavid du Colombier typedef struct Qh Qh; 16*84860c5dSDavid du Colombier typedef struct Qtree Qtree; 17*84860c5dSDavid du Colombier 18*84860c5dSDavid du Colombier #pragma incomplete Ctlr; 19*84860c5dSDavid du Colombier #pragma incomplete Eopio; 20*84860c5dSDavid du Colombier #pragma incomplete Isoio; 21*84860c5dSDavid du Colombier #pragma incomplete Poll; 22*84860c5dSDavid du Colombier #pragma incomplete Qh; 23*84860c5dSDavid du Colombier #pragma incomplete Qtree; 24083ba878SDavid du Colombier 25*84860c5dSDavid du Colombier struct Poll 26*84860c5dSDavid du Colombier { 27*84860c5dSDavid du Colombier Lock; 28*84860c5dSDavid du Colombier Rendez; 29*84860c5dSDavid du Colombier int must; 30*84860c5dSDavid du Colombier int does; 31*84860c5dSDavid du Colombier }; 32*84860c5dSDavid du Colombier 33*84860c5dSDavid du Colombier struct Ctlr 34*84860c5dSDavid du Colombier { 35*84860c5dSDavid du Colombier Rendez; /* for waiting to async advance doorbell */ 36*84860c5dSDavid du Colombier Lock; /* for ilock. qh lists and basic ctlr I/O */ 37*84860c5dSDavid du Colombier QLock portlck; /* for port resets/enable... (and doorbell) */ 38*84860c5dSDavid du Colombier int active; /* in use or not */ 39*84860c5dSDavid du Colombier Pcidev* pcidev; 40*84860c5dSDavid du Colombier Ecapio* capio; /* Capability i/o regs */ 41*84860c5dSDavid du Colombier Eopio* opio; /* Operational i/o regs */ 42*84860c5dSDavid du Colombier 43*84860c5dSDavid du Colombier int nframes; /* 1024, 512, or 256 frames in the list */ 44*84860c5dSDavid du Colombier ulong* frames; /* periodic frame list (hw) */ 45*84860c5dSDavid du Colombier Qh* qhs; /* async Qh circular list for bulk/ctl */ 46*84860c5dSDavid du Colombier Qtree* tree; /* tree of Qhs for the periodic list */ 47*84860c5dSDavid du Colombier int ntree; /* number of dummy qhs in tree */ 48*84860c5dSDavid du Colombier Qh* intrqhs; /* list of (not dummy) qhs in tree */ 49*84860c5dSDavid du Colombier Isoio* iso; /* list of active Iso I/O */ 50*84860c5dSDavid du Colombier ulong load; 51*84860c5dSDavid du Colombier ulong isoload; 52*84860c5dSDavid du Colombier int nintr; /* number of interrupts attended */ 53*84860c5dSDavid du Colombier int ntdintr; /* number of intrs. with something to do */ 54*84860c5dSDavid du Colombier int nqhintr; /* number of async td intrs. */ 55*84860c5dSDavid du Colombier int nisointr; /* number of periodic td intrs. */ 56*84860c5dSDavid du Colombier int nreqs; 57*84860c5dSDavid du Colombier Poll poll; 58*84860c5dSDavid du Colombier }; 59*84860c5dSDavid du Colombier 60*84860c5dSDavid du Colombier /* 61083ba878SDavid du Colombier * Operational registers (hw) 62083ba878SDavid du Colombier */ 63083ba878SDavid du Colombier struct Eopio 64083ba878SDavid du Colombier { 65083ba878SDavid du Colombier ulong cmd; /* 00 command */ 66083ba878SDavid du Colombier ulong sts; /* 04 status */ 67083ba878SDavid du Colombier ulong intr; /* 08 interrupt enable */ 68083ba878SDavid du Colombier ulong frno; /* 0c frame index */ 69083ba878SDavid du Colombier ulong seg; /* 10 bits 63:32 of EHCI datastructs (unused) */ 70083ba878SDavid du Colombier ulong frbase; /* 14 frame list base addr, 4096-byte boundary */ 71083ba878SDavid du Colombier ulong link; /* 18 link for async list */ 72083ba878SDavid du Colombier uchar d2c[0x40-0x1c]; /* 1c dummy */ 73083ba878SDavid du Colombier ulong config; /* 40 1: all ports default-routed to this HC */ 74083ba878SDavid du Colombier ulong portsc[1]; /* 44 Port status and control, one per port */ 75083ba878SDavid du Colombier }; 76083ba878SDavid du Colombier 77*84860c5dSDavid du Colombier extern int ehcidebug; 7839dc1420SDavid du Colombier extern Ecapio *ehcidebugcapio; 7939dc1420SDavid du Colombier extern int ehcidebugport; 80*84860c5dSDavid du Colombier 81*84860c5dSDavid du Colombier void ehcilinkage(Hci *hp); 82*84860c5dSDavid du Colombier void ehcimeminit(Ctlr *ctlr); 83*84860c5dSDavid du Colombier void ehcirun(Ctlr *ctlr, int on); 84