1 /* 2 * Intel Gigabit Ethernet PCI-Express Controllers. 3 * 8256[36], 8257[12], 82573[ev] 4 * 82575eb 5 * Pretty basic, does not use many of the chip smarts. 6 * The interrupt mitigation tuning for each chip variant 7 * is probably different. The reset/initialisation 8 * sequence needs straightened out. Doubt the PHY code 9 * for the 82575eb is right. 10 */ 11 #include "u.h" 12 #include "../port/lib.h" 13 #include "mem.h" 14 #include "dat.h" 15 #include "fns.h" 16 #include "io.h" 17 #include "../port/error.h" 18 #include "../port/netif.h" 19 20 #include "etherif.h" 21 22 /* 23 * these are in the order they appear in the manual, not numeric order. 24 * It was too hard to find them in the book. Ref 21489, rev 2.6 25 */ 26 27 enum { 28 /* General */ 29 30 Ctrl = 0x0000, /* Device Control */ 31 Status = 0x0008, /* Device Status */ 32 Eec = 0x0010, /* EEPROM/Flash Control/Data */ 33 Eerd = 0x0014, /* EEPROM Read */ 34 Ctrlext = 0x0018, /* Extended Device Control */ 35 Fla = 0x001c, /* Flash Access */ 36 Mdic = 0x0020, /* MDI Control */ 37 Seresctl = 0x0024, /* Serdes ana */ 38 Fcal = 0x0028, /* Flow Control Address Low */ 39 Fcah = 0x002C, /* Flow Control Address High */ 40 Fct = 0x0030, /* Flow Control Type */ 41 Kumctrlsta = 0x0034, /* MAC-PHY Interface */ 42 Vet = 0x0038, /* VLAN EtherType */ 43 Fcttv = 0x0170, /* Flow Control Transmit Timer Value */ 44 Txcw = 0x0178, /* Transmit Configuration Word */ 45 Rxcw = 0x0180, /* Receive Configuration Word */ 46 Ledctl = 0x0E00, /* LED control */ 47 Pba = 0x1000, /* Packet Buffer Allocation */ 48 Pbs = 0x1008, /* Packet Buffer Size */ 49 50 /* Interrupt */ 51 52 Icr = 0x00C0, /* Interrupt Cause Read */ 53 Itr = 0x00c4, /* Interrupt Throttling Rate */ 54 Ics = 0x00C8, /* Interrupt Cause Set */ 55 Ims = 0x00D0, /* Interrupt Mask Set/Read */ 56 Imc = 0x00D8, /* Interrupt mask Clear */ 57 Iam = 0x00E0, /* Interrupt acknowledge Auto Mask */ 58 59 /* Receive */ 60 61 Rctl = 0x0100, /* Control */ 62 Ert = 0x2008, /* Early Receive Threshold (573[EVL] only) */ 63 Fcrtl = 0x2160, /* Flow Control RX Threshold Low */ 64 Fcrth = 0x2168, /* Flow Control Rx Threshold High */ 65 Psrctl = 0x2170, /* Packet Split Receive Control */ 66 Rdbal = 0x2800, /* Rdesc Base Address Low Queue 0 */ 67 Rdbah = 0x2804, /* Rdesc Base Address High Queue 0 */ 68 Rdlen = 0x2808, /* Descriptor Length Queue 0 */ 69 Rdh = 0x2810, /* Descriptor Head Queue 0 */ 70 Rdt = 0x2818, /* Descriptor Tail Queue 0 */ 71 Rdtr = 0x2820, /* Descriptor Timer Ring */ 72 Rxdctl = 0x2828, /* Descriptor Control */ 73 Radv = 0x282C, /* Interrupt Absolute Delay Timer */ 74 Rdbal1 = 0x2900, /* Rdesc Base Address Low Queue 1 */ 75 Rdbah1 = 0x2804, /* Rdesc Base Address High Queue 1 */ 76 Rdlen1 = 0x2908, /* Descriptor Length Queue 1 */ 77 Rdh1 = 0x2910, /* Descriptor Head Queue 1 */ 78 Rdt1 = 0x2918, /* Descriptor Tail Queue 1 */ 79 Rxdctl1 = 0x2928, /* Descriptor Control Queue 1 */ 80 Rsrpd = 0x2c00, /* Small Packet Detect */ 81 Raid = 0x2c08, /* ACK interrupt delay */ 82 Cpuvec = 0x2c10, /* CPU Vector */ 83 Rxcsum = 0x5000, /* Checksum Control */ 84 Rfctl = 0x5008, /* Filter Control */ 85 Mta = 0x5200, /* Multicast Table Array */ 86 Ral = 0x5400, /* Receive Address Low */ 87 Rah = 0x5404, /* Receive Address High */ 88 Vfta = 0x5600, /* VLAN Filter Table Array */ 89 Mrqc = 0x5818, /* Multiple Receive Queues Command */ 90 Rssim = 0x5864, /* RSS Interrupt Mask */ 91 Rssir = 0x5868, /* RSS Interrupt Request */ 92 Reta = 0x5c00, /* Redirection Table */ 93 Rssrk = 0x5c80, /* RSS Random Key */ 94 95 /* Transmit */ 96 97 Tctl = 0x0400, /* Transmit Control */ 98 Tipg = 0x0410, /* Transmit IPG */ 99 Tkabgtxd = 0x3004, /* glci afe band gap transmit ref data, or something */ 100 Tdbal = 0x3800, /* Tdesc Base Address Low */ 101 Tdbah = 0x3804, /* Tdesc Base Address High */ 102 Tdlen = 0x3808, /* Descriptor Length */ 103 Tdh = 0x3810, /* Descriptor Head */ 104 Tdt = 0x3818, /* Descriptor Tail */ 105 Tidv = 0x3820, /* Interrupt Delay Value */ 106 Txdctl = 0x3828, /* Descriptor Control */ 107 Tadv = 0x382C, /* Interrupt Absolute Delay Timer */ 108 Tarc0 = 0x3840, /* Arbitration Counter Queue 0 */ 109 Tdbal1 = 0x3900, /* Descriptor Base Low Queue 1 */ 110 Tdbah1 = 0x3904, /* Descriptor Base High Queue 1 */ 111 Tdlen1 = 0x3908, /* Descriptor Length Queue 1 */ 112 Tdh1 = 0x3910, /* Descriptor Head Queue 1 */ 113 Tdt1 = 0x3918, /* Descriptor Tail Queue 1 */ 114 Txdctl1 = 0x3928, /* Descriptor Control 1 */ 115 Tarc1 = 0x3940, /* Arbitration Counter Queue 1 */ 116 117 /* Statistics */ 118 119 Statistics = 0x4000, /* Start of Statistics Area */ 120 Gorcl = 0x88/4, /* Good Octets Received Count */ 121 Gotcl = 0x90/4, /* Good Octets Transmitted Count */ 122 Torl = 0xC0/4, /* Total Octets Received */ 123 Totl = 0xC8/4, /* Total Octets Transmitted */ 124 Nstatistics = 0x124/4, 125 }; 126 127 enum { /* Ctrl */ 128 GIOmd = 1<<2, /* BIO master disable */ 129 Lrst = 1<<3, /* link reset */ 130 Slu = 1<<6, /* Set Link Up */ 131 SspeedMASK = 3<<8, /* Speed Selection */ 132 SspeedSHIFT = 8, 133 Sspeed10 = 0x00000000, /* 10Mb/s */ 134 Sspeed100 = 0x00000100, /* 100Mb/s */ 135 Sspeed1000 = 0x00000200, /* 1000Mb/s */ 136 Frcspd = 1<<11, /* Force Speed */ 137 Frcdplx = 1<<12, /* Force Duplex */ 138 SwdpinsloMASK = 0x003C0000, /* Software Defined Pins - lo nibble */ 139 SwdpinsloSHIFT = 18, 140 SwdpioloMASK = 0x03C00000, /* Software Defined Pins - I or O */ 141 SwdpioloSHIFT = 22, 142 Devrst = 1<<26, /* Device Reset */ 143 Rfce = 1<<27, /* Receive Flow Control Enable */ 144 Tfce = 1<<28, /* Transmit Flow Control Enable */ 145 Vme = 1<<30, /* VLAN Mode Enable */ 146 Phyrst = 1<<31, /* Phy Reset */ 147 }; 148 149 enum { /* Status */ 150 Lu = 1<<1, /* Link Up */ 151 Lanid = 3<<2, /* mask for Lan ID. */ 152 Txoff = 1<<4, /* Transmission Paused */ 153 Tbimode = 1<<5, /* TBI Mode Indication */ 154 Phyra = 1<<10, /* PHY Reset Asserted */ 155 GIOme = 1<<19, /* GIO Master Enable Status */ 156 }; 157 158 enum { /* Eerd */ 159 EEstart = 1<<0, /* Start Read */ 160 EEdone = 1<<1, /* Read done */ 161 }; 162 163 enum { /* Ctrlext */ 164 Asdchk = 1<<12, /* ASD Check */ 165 Eerst = 1<<13, /* EEPROM Reset */ 166 Spdbyps = 1<<15, /* Speed Select Bypass */ 167 }; 168 169 enum { /* EEPROM content offsets */ 170 Ea = 0x00, /* Ethernet Address */ 171 Cf = 0x03, /* Compatibility Field */ 172 Icw1 = 0x0A, /* Initialization Control Word 1 */ 173 Sid = 0x0B, /* Subsystem ID */ 174 Svid = 0x0C, /* Subsystem Vendor ID */ 175 Did = 0x0D, /* Device ID */ 176 Vid = 0x0E, /* Vendor ID */ 177 Icw2 = 0x0F, /* Initialization Control Word 2 */ 178 }; 179 180 enum { /* Mdic */ 181 MDIdMASK = 0x0000FFFF, /* Data */ 182 MDIdSHIFT = 0, 183 MDIrMASK = 0x001F0000, /* PHY Register Address */ 184 MDIrSHIFT = 16, 185 MDIpMASK = 0x03E00000, /* PHY Address */ 186 MDIpSHIFT = 21, 187 MDIwop = 0x04000000, /* Write Operation */ 188 MDIrop = 0x08000000, /* Read Operation */ 189 MDIready = 0x10000000, /* End of Transaction */ 190 MDIie = 0x20000000, /* Interrupt Enable */ 191 MDIe = 0x40000000, /* Error */ 192 }; 193 194 enum { /* phy interface registers */ 195 Phyctl = 0, /* phy ctl */ 196 Physsr = 17, /* phy secondary status */ 197 Phyier = 18, /* 82573 phy interrupt enable */ 198 Phyisr = 19, /* 82563 phy interrupt status */ 199 Phylhr = 19, /* 8257[12] link health */ 200 201 Rtlink = 1<<10, /* realtime link status */ 202 Phyan = 1<<11, /* phy has auto-negotiated */ 203 204 /* Phyctl bits */ 205 Ran = 1<<9, /* restart auto-negotiation */ 206 Ean = 1<<12, /* enable auto-negotiation */ 207 208 /* 82573 Phyier bits */ 209 Lscie = 1<<10, /* link status changed ie */ 210 Ancie = 1<<11, /* auto-negotiation complete ie */ 211 Spdie = 1<<14, /* speed changed ie */ 212 Panie = 1<<15, /* phy auto-negotiation error ie */ 213 214 /* Phylhr/Phyisr bits */ 215 Anf = 1<<6, /* lhr: auto-negotiation fault */ 216 Ane = 1<<15, /* isr: auto-negotiation error */ 217 }; 218 219 enum { /* Icr, Ics, Ims, Imc */ 220 Txdw = 0x00000001, /* Transmit Descriptor Written Back */ 221 Txqe = 0x00000002, /* Transmit Queue Empty */ 222 Lsc = 0x00000004, /* Link Status Change */ 223 Rxseq = 0x00000008, /* Receive Sequence Error */ 224 Rxdmt0 = 0x00000010, /* Rdesc Minimum Threshold Reached */ 225 Rxo = 0x00000040, /* Receiver Overrun */ 226 Rxt0 = 0x00000080, /* Receiver Timer Interrupt */ 227 Mdac = 0x00000200, /* MDIO Access Completed */ 228 Rxcfg = 0x00000400, /* Receiving /C/ ordered sets */ 229 Gpi0 = 0x00000800, /* General Purpose Interrupts */ 230 Gpi1 = 0x00001000, 231 Gpi2 = 0x00002000, 232 Gpi3 = 0x00004000, 233 Ack = 0x00020000, /* Receive ACK frame */ 234 }; 235 236 enum { /* Txcw */ 237 TxcwFd = 0x00000020, /* Full Duplex */ 238 TxcwHd = 0x00000040, /* Half Duplex */ 239 TxcwPauseMASK = 0x00000180, /* Pause */ 240 TxcwPauseSHIFT = 7, 241 TxcwPs = 1<<TxcwPauseSHIFT, /* Pause Supported */ 242 TxcwAs = 2<<TxcwPauseSHIFT, /* Asymmetric FC desired */ 243 TxcwRfiMASK = 0x00003000, /* Remote Fault Indication */ 244 TxcwRfiSHIFT = 12, 245 TxcwNpr = 0x00008000, /* Next Page Request */ 246 TxcwConfig = 0x40000000, /* Transmit Config Control */ 247 TxcwAne = 0x80000000, /* Auto-Negotiation Enable */ 248 }; 249 250 enum { /* Rctl */ 251 Rrst = 0x00000001, /* Receiver Software Reset */ 252 Ren = 0x00000002, /* Receiver Enable */ 253 Sbp = 0x00000004, /* Store Bad Packets */ 254 Upe = 0x00000008, /* Unicast Promiscuous Enable */ 255 Mpe = 0x00000010, /* Multicast Promiscuous Enable */ 256 Lpe = 0x00000020, /* Long Packet Reception Enable */ 257 LbmMASK = 0x000000C0, /* Loopback Mode */ 258 LbmOFF = 0x00000000, /* No Loopback */ 259 LbmTBI = 0x00000040, /* TBI Loopback */ 260 LbmMII = 0x00000080, /* GMII/MII Loopback */ 261 LbmXCVR = 0x000000C0, /* Transceiver Loopback */ 262 RdtmsMASK = 0x00000300, /* Rdesc Minimum Threshold Size */ 263 RdtmsHALF = 0x00000000, /* Threshold is 1/2 Rdlen */ 264 RdtmsQUARTER = 0x00000100, /* Threshold is 1/4 Rdlen */ 265 RdtmsEIGHTH = 0x00000200, /* Threshold is 1/8 Rdlen */ 266 MoMASK = 0x00003000, /* Multicast Offset */ 267 Bam = 0x00008000, /* Broadcast Accept Mode */ 268 BsizeMASK = 0x00030000, /* Receive Buffer Size */ 269 Bsize16384 = 0x00010000, /* Bsex = 1 */ 270 Bsize8192 = 0x00020000, /* Bsex = 1 */ 271 Bsize2048 = 0x00000000, 272 Bsize1024 = 0x00010000, 273 Bsize512 = 0x00020000, 274 Bsize256 = 0x00030000, 275 BsizeFlex = 0x08000000, /* Flexible Bsize in 1KB increments */ 276 Vfe = 0x00040000, /* VLAN Filter Enable */ 277 Cfien = 0x00080000, /* Canonical Form Indicator Enable */ 278 Cfi = 0x00100000, /* Canonical Form Indicator value */ 279 Dpf = 0x00400000, /* Discard Pause Frames */ 280 Pmcf = 0x00800000, /* Pass MAC Control Frames */ 281 Bsex = 0x02000000, /* Buffer Size Extension */ 282 Secrc = 0x04000000, /* Strip CRC from incoming packet */ 283 }; 284 285 enum { /* Tctl */ 286 Trst = 0x00000001, /* Transmitter Software Reset */ 287 Ten = 0x00000002, /* Transmit Enable */ 288 Psp = 0x00000008, /* Pad Short Packets */ 289 Mulr = 0x10000000, /* Allow multiple concurrent requests */ 290 CtMASK = 0x00000FF0, /* Collision Threshold */ 291 CtSHIFT = 4, 292 ColdMASK = 0x003FF000, /* Collision Distance */ 293 ColdSHIFT = 12, 294 Swxoff = 0x00400000, /* Sofware XOFF Transmission */ 295 Pbe = 0x00800000, /* Packet Burst Enable */ 296 Rtlc = 0x01000000, /* Re-transmit on Late Collision */ 297 Nrtu = 0x02000000, /* No Re-transmit on Underrrun */ 298 }; 299 300 enum { /* [RT]xdctl */ 301 PthreshMASK = 0x0000003F, /* Prefetch Threshold */ 302 PthreshSHIFT = 0, 303 HthreshMASK = 0x00003F00, /* Host Threshold */ 304 HthreshSHIFT = 8, 305 WthreshMASK = 0x003F0000, /* Writeback Threshold */ 306 WthreshSHIFT = 16, 307 Gran = 0x01000000, /* Granularity */ 308 Qenable = 0x02000000, /* Queue Enable (82575) */ 309 }; 310 311 enum { /* Rxcsum */ 312 PcssMASK = 0x00FF, /* Packet Checksum Start */ 313 PcssSHIFT = 0, 314 Ipofl = 0x0100, /* IP Checksum Off-load Enable */ 315 Tuofl = 0x0200, /* TCP/UDP Checksum Off-load Enable */ 316 }; 317 318 enum { /* Receive Delay Timer Ring */ 319 DelayMASK = 0xFFFF, /* delay timer in 1.024nS increments */ 320 DelaySHIFT = 0, 321 Fpd = 0x80000000, /* Flush partial Descriptor Block */ 322 }; 323 324 typedef struct Rd { /* Receive Descriptor */ 325 u32int addr[2]; 326 u16int length; 327 u16int checksum; 328 u8int status; 329 u8int errors; 330 u16int special; 331 } Rd; 332 333 enum { /* Rd status */ 334 Rdd = 0x01, /* Descriptor Done */ 335 Reop = 0x02, /* End of Packet */ 336 Ixsm = 0x04, /* Ignore Checksum Indication */ 337 Vp = 0x08, /* Packet is 802.1Q (matched VET) */ 338 Tcpcs = 0x20, /* TCP Checksum Calculated on Packet */ 339 Ipcs = 0x40, /* IP Checksum Calculated on Packet */ 340 Pif = 0x80, /* Passed in-exact filter */ 341 }; 342 343 enum { /* Rd errors */ 344 Ce = 0x01, /* CRC Error or Alignment Error */ 345 Se = 0x02, /* Symbol Error */ 346 Seq = 0x04, /* Sequence Error */ 347 Cxe = 0x10, /* Carrier Extension Error */ 348 Tcpe = 0x20, /* TCP/UDP Checksum Error */ 349 Ipe = 0x40, /* IP Checksum Error */ 350 Rxe = 0x80, /* RX Data Error */ 351 }; 352 353 typedef struct { /* Transmit Descriptor */ 354 u32int addr[2]; /* Data */ 355 u32int control; 356 u32int status; 357 } Td; 358 359 enum { /* Tdesc control */ 360 LenMASK = 0x000FFFFF, /* Data/Packet Length Field */ 361 LenSHIFT = 0, 362 DtypeCD = 0x00000000, /* Data Type 'Context Descriptor' */ 363 DtypeDD = 0x00100000, /* Data Type 'Data Descriptor' */ 364 PtypeTCP = 0x01000000, /* TCP/UDP Packet Type (CD) */ 365 Teop = 0x01000000, /* End of Packet (DD) */ 366 PtypeIP = 0x02000000, /* IP Packet Type (CD) */ 367 Ifcs = 0x02000000, /* Insert FCS (DD) */ 368 Tse = 0x04000000, /* TCP Segmentation Enable */ 369 Rs = 0x08000000, /* Report Status */ 370 Rps = 0x10000000, /* Report Status Sent */ 371 Dext = 0x20000000, /* Descriptor Extension */ 372 Vle = 0x40000000, /* VLAN Packet Enable */ 373 Ide = 0x80000000, /* Interrupt Delay Enable */ 374 }; 375 376 enum { /* Tdesc status */ 377 Tdd = 0x0001, /* Descriptor Done */ 378 Ec = 0x0002, /* Excess Collisions */ 379 Lc = 0x0004, /* Late Collision */ 380 Tu = 0x0008, /* Transmit Underrun */ 381 CssMASK = 0xFF00, /* Checksum Start Field */ 382 CssSHIFT = 8, 383 }; 384 385 typedef struct { 386 u16int *reg; 387 u32int *reg32; 388 int sz; 389 } Flash; 390 391 enum { 392 /* 16 and 32-bit flash registers for ich flash parts */ 393 Bfpr = 0x00/4, /* flash base 0:12; lim 16:28 */ 394 Fsts = 0x04/2, /* flash status; Hsfsts */ 395 Fctl = 0x06/2, /* flash control; Hsfctl */ 396 Faddr = 0x08/4, /* flash address to r/w */ 397 Fdata = 0x10/4, /* data @ address */ 398 399 /* status register */ 400 Fdone = 1<<0, /* flash cycle done */ 401 Fcerr = 1<<1, /* cycle error; write 1 to clear */ 402 Ael = 1<<2, /* direct access error log; 1 to clear */ 403 Scip = 1<<5, /* spi cycle in progress */ 404 Fvalid = 1<<14, /* flash descriptor valid */ 405 406 /* control register */ 407 Fgo = 1<<0, /* start cycle */ 408 Flcycle = 1<<1, /* two bits: r=0; w=2 */ 409 Fdbc = 1<<8, /* bytes to read; 5 bits */ 410 }; 411 412 enum { 413 Nrd = 256, /* power of two */ 414 Ntd = 128, /* power of two */ 415 Nrb = 1024, /* private receive buffers per Ctlr */ 416 }; 417 418 enum { 419 Iany, 420 i82563, 421 i82566, 422 i82567, 423 i82571, 424 i82572, 425 i82573, 426 i82575, 427 }; 428 429 static int rbtab[] = { 430 0, 431 9014, 432 1514, 433 1514, 434 9234, 435 9234, 436 8192, /* terrible performance above 8k */ 437 1514, 438 }; 439 440 static char *tname[] = { 441 "any", 442 "i82563", 443 "i82566", 444 "i82567", 445 "i82571", 446 "i82572", 447 "i82573", 448 "i82575", 449 }; 450 451 typedef struct Ctlr Ctlr; 452 struct Ctlr { 453 int port; 454 Pcidev *pcidev; 455 Ctlr *next; 456 Ether *edev; 457 int active; 458 int type; 459 ushort eeprom[0x40]; 460 461 QLock alock; /* attach */ 462 int attached; 463 int nrd; 464 int ntd; 465 int nrb; /* how many this Ctlr has in the pool */ 466 unsigned rbsz; /* unsigned for % and / by 1024 */ 467 468 int *nic; 469 Lock imlock; 470 int im; /* interrupt mask */ 471 472 Rendez lrendez; 473 int lim; 474 475 QLock slock; 476 uint statistics[Nstatistics]; 477 uint lsleep; 478 uint lintr; 479 uint rsleep; 480 uint rintr; 481 uint txdw; 482 uint tintr; 483 uint ixsm; 484 uint ipcs; 485 uint tcpcs; 486 uint speeds[4]; 487 488 uchar ra[Eaddrlen]; /* receive address */ 489 ulong mta[128]; /* multicast table array */ 490 491 Rendez rrendez; 492 int rim; 493 int rdfree; 494 Rd *rdba; /* receive descriptor base address */ 495 Block **rb; /* receive buffers */ 496 int rdh; /* receive descriptor head */ 497 int rdt; /* receive descriptor tail */ 498 int rdtr; /* receive delay timer ring value */ 499 int radv; /* receive interrupt absolute delay timer */ 500 501 Rendez trendez; 502 QLock tlock; 503 int tbusy; 504 Td *tdba; /* transmit descriptor base address */ 505 Block **tb; /* transmit buffers */ 506 int tdh; /* transmit descriptor head */ 507 int tdt; /* transmit descriptor tail */ 508 509 int fcrtl; 510 int fcrth; 511 512 uint pba; /* packet buffer allocation */ 513 }; 514 515 #define csr32r(c, r) (*((c)->nic+((r)/4))) 516 #define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v)) 517 518 static Ctlr* i82563ctlrhead; 519 static Ctlr* i82563ctlrtail; 520 521 static Lock i82563rblock; /* free receive Blocks */ 522 static Block* i82563rbpool; 523 524 static char* statistics[] = { 525 "CRC Error", 526 "Alignment Error", 527 "Symbol Error", 528 "RX Error", 529 "Missed Packets", 530 "Single Collision", 531 "Excessive Collisions", 532 "Multiple Collision", 533 "Late Collisions", 534 nil, 535 "Collision", 536 "Transmit Underrun", 537 "Defer", 538 "Transmit - No CRS", 539 "Sequence Error", 540 "Carrier Extension Error", 541 "Receive Error Length", 542 nil, 543 "XON Received", 544 "XON Transmitted", 545 "XOFF Received", 546 "XOFF Transmitted", 547 "FC Received Unsupported", 548 "Packets Received (64 Bytes)", 549 "Packets Received (65-127 Bytes)", 550 "Packets Received (128-255 Bytes)", 551 "Packets Received (256-511 Bytes)", 552 "Packets Received (512-1023 Bytes)", 553 "Packets Received (1024-mtu Bytes)", 554 "Good Packets Received", 555 "Broadcast Packets Received", 556 "Multicast Packets Received", 557 "Good Packets Transmitted", 558 nil, 559 "Good Octets Received", 560 nil, 561 "Good Octets Transmitted", 562 nil, 563 nil, 564 nil, 565 "Receive No Buffers", 566 "Receive Undersize", 567 "Receive Fragment", 568 "Receive Oversize", 569 "Receive Jabber", 570 "Management Packets Rx", 571 "Management Packets Drop", 572 "Management Packets Tx", 573 "Total Octets Received", 574 nil, 575 "Total Octets Transmitted", 576 nil, 577 "Total Packets Received", 578 "Total Packets Transmitted", 579 "Packets Transmitted (64 Bytes)", 580 "Packets Transmitted (65-127 Bytes)", 581 "Packets Transmitted (128-255 Bytes)", 582 "Packets Transmitted (256-511 Bytes)", 583 "Packets Transmitted (512-1023 Bytes)", 584 "Packets Transmitted (1024-mtu Bytes)", 585 "Multicast Packets Transmitted", 586 "Broadcast Packets Transmitted", 587 "TCP Segmentation Context Transmitted", 588 "TCP Segmentation Context Fail", 589 "Interrupt Assertion", 590 "Interrupt Rx Pkt Timer", 591 "Interrupt Rx Abs Timer", 592 "Interrupt Tx Pkt Timer", 593 "Interrupt Tx Abs Timer", 594 "Interrupt Tx Queue Empty", 595 "Interrupt Tx Desc Low", 596 "Interrupt Rx Min", 597 "Interrupt Rx Overrun", 598 }; 599 600 static long 601 i82563ifstat(Ether* edev, void* a, long n, ulong offset) 602 { 603 Ctlr *ctlr; 604 char *s, *p, *e, *stat; 605 int i, r; 606 uvlong tuvl, ruvl; 607 608 ctlr = edev->ctlr; 609 qlock(&ctlr->slock); 610 p = s = malloc(READSTR); 611 e = p + READSTR; 612 613 for(i = 0; i < Nstatistics; i++){ 614 r = csr32r(ctlr, Statistics + i*4); 615 if((stat = statistics[i]) == nil) 616 continue; 617 switch(i){ 618 case Gorcl: 619 case Gotcl: 620 case Torl: 621 case Totl: 622 ruvl = r; 623 ruvl += (uvlong)csr32r(ctlr, Statistics+(i+1)*4) << 32; 624 tuvl = ruvl; 625 tuvl += ctlr->statistics[i]; 626 tuvl += (uvlong)ctlr->statistics[i+1] << 32; 627 if(tuvl == 0) 628 continue; 629 ctlr->statistics[i] = tuvl; 630 ctlr->statistics[i+1] = tuvl >> 32; 631 p = seprint(p, e, "%s: %llud %llud\n", stat, tuvl, ruvl); 632 i++; 633 break; 634 635 default: 636 ctlr->statistics[i] += r; 637 if(ctlr->statistics[i] == 0) 638 continue; 639 p = seprint(p, e, "%s: %ud %ud\n", stat, 640 ctlr->statistics[i], r); 641 break; 642 } 643 } 644 645 p = seprint(p, e, "lintr: %ud %ud\n", ctlr->lintr, ctlr->lsleep); 646 p = seprint(p, e, "rintr: %ud %ud\n", ctlr->rintr, ctlr->rsleep); 647 p = seprint(p, e, "tintr: %ud %ud\n", ctlr->tintr, ctlr->txdw); 648 p = seprint(p, e, "ixcs: %ud %ud %ud\n", ctlr->ixsm, ctlr->ipcs, ctlr->tcpcs); 649 p = seprint(p, e, "rdtr: %ud\n", ctlr->rdtr); 650 p = seprint(p, e, "radv: %ud\n", ctlr->radv); 651 p = seprint(p, e, "ctrl: %.8ux\n", csr32r(ctlr, Ctrl)); 652 p = seprint(p, e, "ctrlext: %.8ux\n", csr32r(ctlr, Ctrlext)); 653 p = seprint(p, e, "status: %.8ux\n", csr32r(ctlr, Status)); 654 p = seprint(p, e, "txcw: %.8ux\n", csr32r(ctlr, Txcw)); 655 p = seprint(p, e, "txdctl: %.8ux\n", csr32r(ctlr, Txdctl)); 656 p = seprint(p, e, "pba: %.8ux\n", ctlr->pba); 657 658 p = seprint(p, e, "speeds: 10:%ud 100:%ud 1000:%ud ?:%ud\n", 659 ctlr->speeds[0], ctlr->speeds[1], ctlr->speeds[2], ctlr->speeds[3]); 660 p = seprint(p, e, "type: %s\n", tname[ctlr->type]); 661 662 // p = seprint(p, e, "eeprom:"); 663 // for(i = 0; i < 0x40; i++){ 664 // if(i && ((i & 7) == 0)) 665 // p = seprint(p, e, "\n "); 666 // p = seprint(p, e, " %4.4ux", ctlr->eeprom[i]); 667 // } 668 // p = seprint(p, e, "\n"); 669 670 USED(p); 671 n = readstr(offset, a, n, s); 672 free(s); 673 qunlock(&ctlr->slock); 674 675 return n; 676 } 677 678 enum { 679 CMrdtr, 680 CMradv, 681 }; 682 683 static Cmdtab i82563ctlmsg[] = { 684 CMrdtr, "rdtr", 2, 685 CMradv, "radv", 2, 686 }; 687 688 static long 689 i82563ctl(Ether* edev, void* buf, long n) 690 { 691 ulong v; 692 char *p; 693 Ctlr *ctlr; 694 Cmdbuf *cb; 695 Cmdtab *ct; 696 697 if((ctlr = edev->ctlr) == nil) 698 error(Enonexist); 699 700 cb = parsecmd(buf, n); 701 if(waserror()){ 702 free(cb); 703 nexterror(); 704 } 705 706 ct = lookupcmd(cb, i82563ctlmsg, nelem(i82563ctlmsg)); 707 switch(ct->index){ 708 case CMrdtr: 709 v = strtoul(cb->f[1], &p, 0); 710 if(p == cb->f[1] || v > 0xFFFF) 711 error(Ebadarg); 712 ctlr->rdtr = v; 713 csr32w(ctlr, Rdtr, v); 714 break; 715 case CMradv: 716 v = strtoul(cb->f[1], &p, 0); 717 if(p == cb->f[1] || v > 0xFFFF) 718 error(Ebadarg); 719 ctlr->radv = v; 720 csr32w(ctlr, Radv, v); 721 } 722 free(cb); 723 poperror(); 724 725 return n; 726 } 727 728 static void 729 i82563promiscuous(void* arg, int on) 730 { 731 int rctl; 732 Ctlr *ctlr; 733 Ether *edev; 734 735 edev = arg; 736 ctlr = edev->ctlr; 737 738 rctl = csr32r(ctlr, Rctl); 739 rctl &= ~MoMASK; 740 if(on) 741 rctl |= Upe|Mpe; 742 else 743 rctl &= ~(Upe|Mpe); 744 csr32w(ctlr, Rctl, rctl); 745 } 746 747 static void 748 i82563multicast(void* arg, uchar* addr, int on) 749 { 750 int bit, x; 751 Ctlr *ctlr; 752 Ether *edev; 753 754 edev = arg; 755 ctlr = edev->ctlr; 756 757 x = addr[5]>>1; 758 if(ctlr->type == i82566 || ctlr->type == i82567) 759 x &= 31; 760 bit = ((addr[5] & 1)<<4)|(addr[4]>>4); 761 /* 762 * multiple ether addresses can hash to the same filter bit, 763 * so it's never safe to clear a filter bit. 764 * if we want to clear filter bits, we need to keep track of 765 * all the multicast addresses in use, clear all the filter bits, 766 * then set the ones corresponding to in-use addresses. 767 */ 768 if(on) 769 ctlr->mta[x] |= 1<<bit; 770 // else 771 // ctlr->mta[x] &= ~(1<<bit); 772 773 csr32w(ctlr, Mta+x*4, ctlr->mta[x]); 774 } 775 776 static Block* 777 i82563rballoc(void) 778 { 779 Block *bp; 780 781 ilock(&i82563rblock); 782 if((bp = i82563rbpool) != nil){ 783 i82563rbpool = bp->next; 784 bp->next = nil; 785 _xinc(&bp->ref); /* prevent bp from being freed */ 786 } 787 iunlock(&i82563rblock); 788 789 return bp; 790 } 791 792 static void 793 i82563rbfree(Block* b) 794 { 795 b->rp = b->wp = (uchar*)PGROUND((uintptr)b->base); 796 ilock(&i82563rblock); 797 b->next = i82563rbpool; 798 i82563rbpool = b; 799 iunlock(&i82563rblock); 800 } 801 802 static void 803 i82563im(Ctlr* ctlr, int im) 804 { 805 ilock(&ctlr->imlock); 806 ctlr->im |= im; 807 csr32w(ctlr, Ims, ctlr->im); 808 iunlock(&ctlr->imlock); 809 } 810 811 static void 812 i82563txinit(Ctlr* ctlr) 813 { 814 int i, r; 815 Block *bp; 816 817 csr32w(ctlr, Tctl, 0x0F<<CtSHIFT | Psp | 66<<ColdSHIFT | Mulr); 818 csr32w(ctlr, Tipg, 6<<20 | 8<<10 | 8); /* yb sez: 0x702008 */ 819 csr32w(ctlr, Tdbal, PCIWADDR(ctlr->tdba)); 820 csr32w(ctlr, Tdbah, 0); 821 csr32w(ctlr, Tdlen, ctlr->ntd * sizeof(Td)); 822 ctlr->tdh = PREV(0, ctlr->ntd); 823 csr32w(ctlr, Tdh, 0); 824 ctlr->tdt = 0; 825 csr32w(ctlr, Tdt, 0); 826 for(i = 0; i < ctlr->ntd; i++){ 827 if((bp = ctlr->tb[i]) != nil){ 828 ctlr->tb[i] = nil; 829 freeb(bp); 830 } 831 memset(&ctlr->tdba[i], 0, sizeof(Td)); 832 } 833 csr32w(ctlr, Tidv, 128); 834 r = csr32r(ctlr, Txdctl); 835 r &= ~(WthreshMASK|PthreshSHIFT); 836 r |= 4<<WthreshSHIFT | 4<<PthreshSHIFT; 837 if(ctlr->type == i82575) 838 r |= Qenable; 839 csr32w(ctlr, Tadv, 64); 840 csr32w(ctlr, Txdctl, r); 841 r = csr32r(ctlr, Tctl); 842 r |= Ten; 843 csr32w(ctlr, Tctl, r); 844 // if(ctlr->type == i82671) 845 // csr32w(ctlr, Tarc0, csr32r(ctlr, Tarc0) | 7<<24); /* yb sez? */ 846 } 847 848 #define Next(x, m) (((x)+1) & (m)) 849 850 static int 851 i82563cleanup(Ctlr *c) 852 { 853 Block *b; 854 int tdh, m, n; 855 856 tdh = c->tdh; 857 m = c->ntd-1; 858 while(c->tdba[n = Next(tdh, m)].status & Tdd){ 859 tdh = n; 860 if((b = c->tb[tdh]) != nil){ 861 c->tb[tdh] = nil; 862 freeb(b); 863 }else 864 iprint("82563 tx underrun!\n"); 865 c->tdba[tdh].status = 0; 866 } 867 868 return c->tdh = tdh; 869 } 870 871 static void 872 i82563transmit(Ether* edev) 873 { 874 Td *td; 875 Block *bp; 876 Ctlr *ctlr; 877 int tdh, tdt, m; 878 879 ctlr = edev->ctlr; 880 881 qlock(&ctlr->tlock); 882 883 /* 884 * Free any completed packets 885 */ 886 tdh = i82563cleanup(ctlr); 887 888 /* 889 * Try to fill the ring back up. 890 */ 891 tdt = ctlr->tdt; 892 m = ctlr->ntd-1; 893 for(;;){ 894 if(Next(tdt, m) == tdh){ 895 ctlr->txdw++; 896 i82563im(ctlr, Txdw); 897 break; 898 } 899 if((bp = qget(edev->oq)) == nil) 900 break; 901 td = &ctlr->tdba[tdt]; 902 td->addr[0] = PCIWADDR(bp->rp); 903 td->control = Ide|Rs|Ifcs|Teop|BLEN(bp); 904 ctlr->tb[tdt] = bp; 905 tdt = Next(tdt, m); 906 } 907 if(ctlr->tdt != tdt){ 908 ctlr->tdt = tdt; 909 csr32w(ctlr, Tdt, tdt); 910 } 911 qunlock(&ctlr->tlock); 912 } 913 914 static void 915 i82563replenish(Ctlr* ctlr) 916 { 917 Rd *rd; 918 int rdt, m; 919 Block *bp; 920 921 rdt = ctlr->rdt; 922 m = ctlr->nrd-1; 923 while(Next(rdt, m) != ctlr->rdh){ 924 rd = &ctlr->rdba[rdt]; 925 if(ctlr->rb[rdt] != nil){ 926 iprint("82563: tx overrun\n"); 927 break; 928 } 929 bp = i82563rballoc(); 930 if(bp == nil){ 931 vlong now; 932 static vlong lasttime; 933 934 /* don't flood the console */ 935 now = tk2ms(MACHP(0)->ticks); 936 if (now - lasttime > 2000) 937 iprint("#l%d: 82563: all %d rx buffers in use\n", 938 ctlr->edev->ctlrno, ctlr->nrb); 939 lasttime = now; 940 break; 941 } 942 ctlr->rb[rdt] = bp; 943 rd->addr[0] = PCIWADDR(bp->rp); 944 // rd->addr[1] = 0; 945 rd->status = 0; 946 ctlr->rdfree++; 947 rdt = Next(rdt, m); 948 } 949 ctlr->rdt = rdt; 950 csr32w(ctlr, Rdt, rdt); 951 } 952 953 static void 954 i82563rxinit(Ctlr* ctlr) 955 { 956 Block *bp; 957 int i, r, rctl; 958 959 if(ctlr->rbsz <= 2048) 960 rctl = Dpf|Bsize2048|Bam|RdtmsHALF; 961 else if(ctlr->rbsz <= 8192) 962 rctl = Lpe|Dpf|Bsize8192|Bsex|Bam|RdtmsHALF|Secrc; 963 else if(ctlr->rbsz <= 12*1024){ 964 i = ctlr->rbsz / 1024; 965 if(ctlr->rbsz % 1024) 966 i++; 967 rctl = Lpe|Dpf|BsizeFlex*i|Bam|RdtmsHALF|Secrc; 968 } 969 else 970 rctl = Lpe|Dpf|Bsize16384|Bsex|Bam|RdtmsHALF|Secrc; 971 972 if(ctlr->type == i82575){ 973 /* 974 * Setting Qenable in Rxdctl does not 975 * appear to stick unless Ren is on. 976 */ 977 csr32w(ctlr, Rctl, Ren|rctl); 978 r = csr32r(ctlr, Rxdctl); 979 r |= Qenable; 980 csr32w(ctlr, Rxdctl, r); 981 } 982 csr32w(ctlr, Rctl, rctl); 983 984 if(ctlr->type == i82573) 985 csr32w(ctlr, Ert, 1024/8); 986 987 if(ctlr->type == i82566 || ctlr->type == i82567) 988 csr32w(ctlr, Pbs, 16); 989 990 csr32w(ctlr, Rdbal, PCIWADDR(ctlr->rdba)); 991 csr32w(ctlr, Rdbah, 0); 992 csr32w(ctlr, Rdlen, ctlr->nrd * sizeof(Rd)); 993 ctlr->rdh = 0; 994 csr32w(ctlr, Rdh, 0); 995 ctlr->rdt = 0; 996 csr32w(ctlr, Rdt, 0); 997 /* to hell with interrupt moderation, we've got fast cpus */ 998 // ctlr->rdtr = 25; /* µs units? */ 999 // ctlr->radv = 500; /* µs units? */ 1000 ctlr->radv = ctlr->rdtr = 0; 1001 csr32w(ctlr, Rdtr, ctlr->rdtr); 1002 csr32w(ctlr, Radv, ctlr->radv); 1003 1004 for(i = 0; i < ctlr->nrd; i++){ 1005 if((bp = ctlr->rb[i]) != nil){ 1006 ctlr->rb[i] = nil; 1007 freeb(bp); 1008 } 1009 } 1010 i82563replenish(ctlr); 1011 1012 if(ctlr->type != i82575){ 1013 /* 1014 * See comment above for Qenable. 1015 * Could shuffle the code? 1016 */ 1017 r = csr32r(ctlr, Rxdctl); 1018 r &= ~(WthreshSHIFT|PthreshSHIFT); 1019 r |= (2<<WthreshSHIFT)|(2<<PthreshSHIFT); 1020 csr32w(ctlr, Rxdctl, r); 1021 } 1022 1023 /* 1024 * Don't enable checksum offload. In practice, it interferes with 1025 * tftp booting on at least the 82575. 1026 */ 1027 // csr32w(ctlr, Rxcsum, Tuofl | Ipofl | ETHERHDRSIZE<<PcssSHIFT); 1028 csr32w(ctlr, Rxcsum, 0); 1029 } 1030 1031 static int 1032 i82563rim(void* ctlr) 1033 { 1034 return ((Ctlr*)ctlr)->rim != 0; 1035 } 1036 1037 static void 1038 i82563rproc(void* arg) 1039 { 1040 Rd *rd; 1041 Block *bp; 1042 Ctlr *ctlr; 1043 int r, m, rdh, rim; 1044 Ether *edev; 1045 1046 edev = arg; 1047 ctlr = edev->ctlr; 1048 1049 i82563rxinit(ctlr); 1050 r = csr32r(ctlr, Rctl); 1051 r |= Ren; 1052 csr32w(ctlr, Rctl, r); 1053 m = ctlr->nrd-1; 1054 1055 for(;;){ 1056 i82563im(ctlr, Rxt0|Rxo|Rxdmt0|Rxseq|Ack); 1057 ctlr->rsleep++; 1058 // coherence(); 1059 sleep(&ctlr->rrendez, i82563rim, ctlr); 1060 1061 rdh = ctlr->rdh; 1062 for(;;){ 1063 rd = &ctlr->rdba[rdh]; 1064 rim = ctlr->rim; 1065 ctlr->rim = 0; 1066 if(!(rd->status & Rdd)) 1067 break; 1068 1069 /* 1070 * Accept eop packets with no errors. 1071 * With no errors and the Ixsm bit set, 1072 * the descriptor status Tpcs and Ipcs bits give 1073 * an indication of whether the checksums were 1074 * calculated and valid. 1075 */ 1076 bp = ctlr->rb[rdh]; 1077 if((rd->status & Reop) && rd->errors == 0){ 1078 bp->wp += rd->length; 1079 bp->lim = bp->wp; /* lie like a dog. */ 1080 if(!(rd->status & Ixsm)){ 1081 ctlr->ixsm++; 1082 if(rd->status & Ipcs){ 1083 /* 1084 * IP checksum calculated 1085 * (and valid as errors == 0). 1086 */ 1087 ctlr->ipcs++; 1088 bp->flag |= Bipck; 1089 } 1090 if(rd->status & Tcpcs){ 1091 /* 1092 * TCP/UDP checksum calculated 1093 * (and valid as errors == 0). 1094 */ 1095 ctlr->tcpcs++; 1096 bp->flag |= Btcpck|Budpck; 1097 } 1098 bp->checksum = rd->checksum; 1099 bp->flag |= Bpktck; 1100 } 1101 etheriq(edev, bp, 1); 1102 } else if (rd->status & Reop && rd->errors) 1103 print("%s: input packet error %#ux\n", 1104 tname[ctlr->type], rd->errors); 1105 else 1106 freeb(bp); 1107 ctlr->rb[rdh] = nil; 1108 1109 rd->status = 0; 1110 ctlr->rdfree--; 1111 ctlr->rdh = rdh = Next(rdh, m); 1112 if(ctlr->nrd-ctlr->rdfree >= 32 || (rim & Rxdmt0)) 1113 i82563replenish(ctlr); 1114 } 1115 } 1116 } 1117 1118 static int 1119 i82563lim(void* c) 1120 { 1121 return ((Ctlr*)c)->lim != 0; 1122 } 1123 1124 static int speedtab[] = { 1125 10, 100, 1000, 0 1126 }; 1127 1128 static uint 1129 phyread(Ctlr *c, int reg) 1130 { 1131 uint phy, i; 1132 1133 csr32w(c, Mdic, MDIrop | 1<<MDIpSHIFT | reg<<MDIrSHIFT); 1134 phy = 0; 1135 for(i = 0; i < 64; i++){ 1136 phy = csr32r(c, Mdic); 1137 if(phy & (MDIe|MDIready)) 1138 break; 1139 microdelay(1); 1140 } 1141 if((phy & (MDIe|MDIready)) != MDIready) 1142 return ~0; 1143 return phy & 0xffff; 1144 } 1145 1146 static uint 1147 phywrite(Ctlr *c, int reg, ushort val) 1148 { 1149 uint phy, i; 1150 1151 csr32w(c, Mdic, MDIwop | 1<<MDIpSHIFT | reg<<MDIrSHIFT | val); 1152 phy = 0; 1153 for(i = 0; i < 64; i++){ 1154 phy = csr32r(c, Mdic); 1155 if(phy & (MDIe|MDIready)) 1156 break; 1157 microdelay(1); 1158 } 1159 if((phy & (MDIe|MDIready)) != MDIready) 1160 return ~0; 1161 return 0; 1162 } 1163 1164 /* 1165 * watch for changes of link state 1166 */ 1167 static void 1168 i82563lproc(void *v) 1169 { 1170 uint phy, i, a; 1171 Ctlr *c; 1172 Ether *e; 1173 1174 e = v; 1175 c = e->ctlr; 1176 1177 if(c->type == i82573 && (phy = phyread(c, Phyier)) != ~0) 1178 phywrite(c, Phyier, phy | Lscie | Ancie | Spdie | Panie); 1179 for(;;){ 1180 phy = phyread(c, Physsr); 1181 if(phy == ~0) 1182 goto next; 1183 i = (phy>>14) & 3; 1184 1185 switch(c->type){ 1186 case i82563: 1187 a = phyread(c, Phyisr) & Ane; 1188 break; 1189 case i82571: 1190 case i82572: 1191 a = phyread(c, Phylhr) & Anf; 1192 i = (i-1) & 3; 1193 break; 1194 default: 1195 a = 0; 1196 break; 1197 } 1198 if(a) 1199 phywrite(c, Phyctl, phyread(c, Phyctl) | Ran | Ean); 1200 e->link = (phy & Rtlink) != 0; 1201 if(e->link){ 1202 c->speeds[i]++; 1203 if (speedtab[i]) 1204 e->mbps = speedtab[i]; 1205 } 1206 next: 1207 c->lim = 0; 1208 i82563im(c, Lsc); 1209 c->lsleep++; 1210 sleep(&c->lrendez, i82563lim, c); 1211 } 1212 } 1213 1214 static void 1215 i82563tproc(void *v) 1216 { 1217 Ether *e; 1218 Ctlr *c; 1219 1220 e = v; 1221 c = e->ctlr; 1222 for(;;){ 1223 sleep(&c->trendez, return0, 0); 1224 i82563transmit(e); 1225 } 1226 } 1227 1228 static void 1229 i82563attach(Ether* edev) 1230 { 1231 Block *bp; 1232 Ctlr *ctlr; 1233 char name[KNAMELEN]; 1234 1235 ctlr = edev->ctlr; 1236 ctlr->edev = edev; /* point back to Ether* */ 1237 qlock(&ctlr->alock); 1238 if(ctlr->attached){ 1239 qunlock(&ctlr->alock); 1240 return; 1241 } 1242 1243 ctlr->nrd = Nrd; 1244 ctlr->ntd = Ntd; 1245 1246 if(waserror()){ 1247 while(ctlr->nrb > 0){ 1248 bp = i82563rballoc(); 1249 bp->free = nil; 1250 freeb(bp); 1251 ctlr->nrb--; 1252 } 1253 free(ctlr->tb); 1254 ctlr->tb = nil; 1255 free(ctlr->rb); 1256 ctlr->rb = nil; 1257 free(ctlr->tdba); 1258 ctlr->tdba = nil; 1259 free(ctlr->rdba); 1260 ctlr->rdba = nil; 1261 qunlock(&ctlr->alock); 1262 nexterror(); 1263 } 1264 1265 if((ctlr->rdba = mallocalign(ctlr->nrd*sizeof(Rd), 128, 0, 0)) == nil) 1266 error(Enomem); 1267 if((ctlr->tdba = mallocalign(ctlr->ntd*sizeof(Td), 128, 0, 0)) == nil) 1268 error(Enomem); 1269 if((ctlr->rb = malloc(ctlr->nrd*sizeof(Block*))) == nil) 1270 error(Enomem); 1271 if((ctlr->tb = malloc(ctlr->ntd*sizeof(Block*))) == nil) 1272 error(Enomem); 1273 1274 for(ctlr->nrb = 0; ctlr->nrb < Nrb; ctlr->nrb++){ 1275 if((bp = allocb(ctlr->rbsz + BY2PG)) == nil) 1276 break; 1277 bp->free = i82563rbfree; 1278 freeb(bp); 1279 } 1280 1281 ctlr->attached = 1; 1282 1283 snprint(name, sizeof name, "#l%dl", edev->ctlrno); 1284 kproc(name, i82563lproc, edev); 1285 1286 snprint(name, sizeof name, "#l%dr", edev->ctlrno); 1287 kproc(name, i82563rproc, edev); 1288 1289 snprint(name, sizeof name, "#l%dt", edev->ctlrno); 1290 kproc(name, i82563tproc, edev); 1291 1292 i82563txinit(ctlr); 1293 1294 qunlock(&ctlr->alock); 1295 poperror(); 1296 } 1297 1298 static void 1299 i82563interrupt(Ureg*, void* arg) 1300 { 1301 Ctlr *ctlr; 1302 Ether *edev; 1303 int icr, im; 1304 1305 edev = arg; 1306 ctlr = edev->ctlr; 1307 1308 ilock(&ctlr->imlock); 1309 csr32w(ctlr, Imc, ~0); 1310 im = ctlr->im; 1311 1312 for(icr = csr32r(ctlr, Icr); icr & ctlr->im; icr = csr32r(ctlr, Icr)){ 1313 if(icr & Lsc){ 1314 im &= ~Lsc; 1315 ctlr->lim = icr & Lsc; 1316 wakeup(&ctlr->lrendez); 1317 ctlr->lintr++; 1318 } 1319 if(icr & (Rxt0|Rxo|Rxdmt0|Rxseq|Ack)){ 1320 ctlr->rim = icr & (Rxt0|Rxo|Rxdmt0|Rxseq|Ack); 1321 im &= ~(Rxt0|Rxo|Rxdmt0|Rxseq|Ack); 1322 wakeup(&ctlr->rrendez); 1323 ctlr->rintr++; 1324 } 1325 if(icr & Txdw){ 1326 im &= ~Txdw; 1327 ctlr->tintr++; 1328 wakeup(&ctlr->trendez); 1329 } 1330 } 1331 1332 ctlr->im = im; 1333 csr32w(ctlr, Ims, im); 1334 iunlock(&ctlr->imlock); 1335 } 1336 1337 /* assume misrouted interrupts and check all controllers */ 1338 static void 1339 i82575interrupt(Ureg*, void *) 1340 { 1341 Ctlr *ctlr; 1342 1343 for (ctlr = i82563ctlrhead; ctlr != nil; ctlr = ctlr->next) 1344 i82563interrupt(nil, ctlr->edev); 1345 } 1346 1347 static int 1348 i82563detach(Ctlr* ctlr) 1349 { 1350 int r, timeo; 1351 1352 /* 1353 * Perform a device reset to get the chip back to the 1354 * power-on state, followed by an EEPROM reset to read 1355 * the defaults for some internal registers. 1356 */ 1357 csr32w(ctlr, Imc, ~0); 1358 csr32w(ctlr, Rctl, 0); 1359 csr32w(ctlr, Tctl, 0); 1360 1361 delay(10); 1362 1363 r = csr32r(ctlr, Ctrl); 1364 if(ctlr->type == i82566 || ctlr->type == i82567) 1365 r |= Phyrst; 1366 csr32w(ctlr, Ctrl, Devrst | r); 1367 delay(1); 1368 for(timeo = 0; timeo < 1000; timeo++){ 1369 if(!(csr32r(ctlr, Ctrl) & Devrst)) 1370 break; 1371 delay(1); 1372 } 1373 if(csr32r(ctlr, Ctrl) & Devrst) 1374 return -1; 1375 1376 r = csr32r(ctlr, Ctrlext); 1377 csr32w(ctlr, Ctrlext, r|Eerst); 1378 delay(1); 1379 for(timeo = 0; timeo < 1000; timeo++){ 1380 if(!(csr32r(ctlr, Ctrlext) & Eerst)) 1381 break; 1382 delay(1); 1383 } 1384 if(csr32r(ctlr, Ctrlext) & Eerst) 1385 return -1; 1386 1387 csr32w(ctlr, Imc, ~0); 1388 delay(1); 1389 for(timeo = 0; timeo < 1000; timeo++){ 1390 if(!csr32r(ctlr, Icr)) 1391 break; 1392 delay(1); 1393 } 1394 if(csr32r(ctlr, Icr)) 1395 return -1; 1396 1397 /* 1398 * Balance Rx/Tx packet buffer. 1399 * No need to set PBA register unless using jumbo, defaults to 32KB 1400 * for receive. If it is changed, then have to do a MAC reset, 1401 * and need to do that at the the right time as it will wipe stuff. 1402 */ 1403 if(ctlr->rbsz > 8192 && (ctlr->type == i82563 || ctlr->type == i82571 || 1404 ctlr->type == i82572)){ 1405 ctlr->pba = csr32r(ctlr, Pba); 1406 r = ctlr->pba >> 16; 1407 r += ctlr->pba & 0xffff; 1408 r >>= 1; 1409 csr32w(ctlr, Pba, r); 1410 } else if(ctlr->type == i82573 && ctlr->rbsz > 1514) 1411 csr32w(ctlr, Pba, 14); 1412 ctlr->pba = csr32r(ctlr, Pba); 1413 1414 r = csr32r(ctlr, Ctrl); 1415 csr32w(ctlr, Ctrl, Slu|r); 1416 1417 return 0; 1418 } 1419 1420 static void 1421 i82563shutdown(Ether* ether) 1422 { 1423 i82563detach(ether->ctlr); 1424 } 1425 1426 static ushort 1427 eeread(Ctlr *ctlr, int adr) 1428 { 1429 csr32w(ctlr, Eerd, EEstart | adr << 2); 1430 while ((csr32r(ctlr, Eerd) & EEdone) == 0) 1431 ; 1432 return csr32r(ctlr, Eerd) >> 16; 1433 } 1434 1435 static int 1436 eeload(Ctlr *ctlr) 1437 { 1438 ushort sum; 1439 int data, adr; 1440 1441 sum = 0; 1442 for (adr = 0; adr < 0x40; adr++) { 1443 data = eeread(ctlr, adr); 1444 ctlr->eeprom[adr] = data; 1445 sum += data; 1446 } 1447 return sum; 1448 } 1449 1450 static int 1451 fcycle(Ctlr *, Flash *f) 1452 { 1453 ushort s, i; 1454 1455 s = f->reg[Fsts]; 1456 if((s&Fvalid) == 0) 1457 return -1; 1458 f->reg[Fsts] |= Fcerr | Ael; 1459 for(i = 0; i < 10; i++){ 1460 if((s&Scip) == 0) 1461 return 0; 1462 delay(1); 1463 s = f->reg[Fsts]; 1464 } 1465 return -1; 1466 } 1467 1468 static int 1469 fread(Ctlr *c, Flash *f, int ladr) 1470 { 1471 ushort s; 1472 1473 delay(1); 1474 if(fcycle(c, f) == -1) 1475 return -1; 1476 f->reg[Fsts] |= Fdone; 1477 f->reg32[Faddr] = ladr; 1478 1479 /* setup flash control register */ 1480 s = f->reg[Fctl]; 1481 s &= ~(0x1f << 8); 1482 s |= (2-1) << 8; /* 2 bytes */ 1483 s &= ~(2*Flcycle); /* read */ 1484 f->reg[Fctl] = s | Fgo; 1485 1486 while((f->reg[Fsts] & Fdone) == 0) 1487 ; 1488 if(f->reg[Fsts] & (Fcerr|Ael)) 1489 return -1; 1490 return f->reg32[Fdata] & 0xffff; 1491 } 1492 1493 static int 1494 fload(Ctlr *c) 1495 { 1496 ulong data, io, r, adr; 1497 ushort sum; 1498 Flash f; 1499 1500 io = c->pcidev->mem[1].bar & ~0x0f; 1501 f.reg = vmap(io, c->pcidev->mem[1].size); 1502 if(f.reg == nil) 1503 return -1; 1504 f.reg32 = (void*)f.reg; 1505 f.sz = f.reg32[Bfpr]; 1506 r = f.sz & 0x1fff; 1507 if(csr32r(c, Eec) & (1<<22)) 1508 ++r; 1509 r <<= 12; 1510 1511 sum = 0; 1512 for (adr = 0; adr < 0x40; adr++) { 1513 data = fread(c, &f, r + adr*2); 1514 if(data == -1) 1515 break; 1516 c->eeprom[adr] = data; 1517 sum += data; 1518 } 1519 vunmap(f.reg, c->pcidev->mem[1].size); 1520 return sum; 1521 } 1522 1523 static int 1524 i82563reset(Ctlr *ctlr) 1525 { 1526 int i, r; 1527 1528 if(i82563detach(ctlr)) 1529 return -1; 1530 if(ctlr->type == i82566 || ctlr->type == i82567) 1531 r = fload(ctlr); 1532 else 1533 r = eeload(ctlr); 1534 if (r != 0 && r != 0xBABA){ 1535 print("%s: bad EEPROM checksum - %#.4ux\n", 1536 tname[ctlr->type], r); 1537 return -1; 1538 } 1539 1540 for(i = 0; i < Eaddrlen/2; i++){ 1541 ctlr->ra[2*i] = ctlr->eeprom[Ea+i]; 1542 ctlr->ra[2*i+1] = ctlr->eeprom[Ea+i] >> 8; 1543 } 1544 r = (csr32r(ctlr, Status) & Lanid) >> 2; 1545 ctlr->ra[5] += r; /* ea ctlr[1] = ea ctlr[0]+1 */ 1546 1547 r = ctlr->ra[3]<<24 | ctlr->ra[2]<<16 | ctlr->ra[1]<<8 | ctlr->ra[0]; 1548 csr32w(ctlr, Ral, r); 1549 r = 0x80000000 | ctlr->ra[5]<<8 | ctlr->ra[4]; 1550 csr32w(ctlr, Rah, r); 1551 for(i = 1; i < 16; i++){ 1552 csr32w(ctlr, Ral+i*8, 0); 1553 csr32w(ctlr, Rah+i*8, 0); 1554 } 1555 memset(ctlr->mta, 0, sizeof(ctlr->mta)); 1556 for(i = 0; i < 128; i++) 1557 csr32w(ctlr, Mta + i*4, 0); 1558 1559 /* 1560 * Does autonegotiation affect this manual setting? 1561 * The correct values here should depend on the PBA value 1562 * and maximum frame length, no? 1563 * ctlr->fcrt[lh] are never set, so default to 0. 1564 */ 1565 csr32w(ctlr, Fcal, 0x00C28001); 1566 csr32w(ctlr, Fcah, 0x0100); 1567 csr32w(ctlr, Fct, 0x8808); 1568 csr32w(ctlr, Fcttv, 0x0100); 1569 1570 ctlr->fcrtl = ctlr->fcrth = 0; 1571 // ctlr->fcrtl = 0x00002000; 1572 // ctlr->fcrth = 0x00004000; 1573 csr32w(ctlr, Fcrtl, ctlr->fcrtl); 1574 csr32w(ctlr, Fcrth, ctlr->fcrth); 1575 1576 return 0; 1577 } 1578 1579 static void 1580 i82563pci(void) 1581 { 1582 int type; 1583 ulong io; 1584 void *mem; 1585 Pcidev *p; 1586 Ctlr *ctlr; 1587 1588 p = nil; 1589 while(p = pcimatch(p, 0x8086, 0)){ 1590 switch(p->did){ 1591 default: 1592 continue; 1593 case 0x1096: 1594 case 0x10ba: 1595 type = i82563; 1596 break; 1597 case 0x1049: /* mm */ 1598 case 0x104a: /* dm */ 1599 case 0x104d: /* v */ 1600 case 0x10bd: /* dm */ 1601 type = i82566; 1602 break; 1603 case 0x10cd: /* lf */ 1604 type = i82567; 1605 break; 1606 case 0x10a4: 1607 case 0x105e: 1608 type = i82571; 1609 break; 1610 case 0x10b9: /* sic, 82572 */ 1611 type = i82572; 1612 break; 1613 case 0x108b: /* e */ 1614 case 0x108c: /* e (iamt) */ 1615 case 0x109a: /* l */ 1616 type = i82573; 1617 break; 1618 case 0x10a7: /* 82575eb: one of a pair of controllers */ 1619 type = i82575; 1620 break; 1621 } 1622 1623 io = p->mem[0].bar & ~0x0F; 1624 mem = vmap(io, p->mem[0].size); 1625 if(mem == nil){ 1626 print("%s: can't map %.8lux\n", tname[type], io); 1627 continue; 1628 } 1629 ctlr = malloc(sizeof(Ctlr)); 1630 ctlr->port = io; 1631 ctlr->pcidev = p; 1632 ctlr->type = type; 1633 ctlr->rbsz = rbtab[type]; 1634 ctlr->nic = mem; 1635 1636 if(i82563reset(ctlr)){ 1637 vunmap(mem, p->mem[0].size); 1638 free(ctlr); 1639 continue; 1640 } 1641 pcisetbme(p); 1642 1643 if(i82563ctlrhead != nil) 1644 i82563ctlrtail->next = ctlr; 1645 else 1646 i82563ctlrhead = ctlr; 1647 i82563ctlrtail = ctlr; 1648 } 1649 } 1650 1651 static int 1652 pnp(Ether* edev, int type) 1653 { 1654 Ctlr *ctlr; 1655 static int done; 1656 1657 if(!done) { 1658 i82563pci(); 1659 done = 1; 1660 } 1661 1662 /* 1663 * Any adapter matches if no edev->port is supplied, 1664 * otherwise the ports must match. 1665 */ 1666 for(ctlr = i82563ctlrhead; ctlr != nil; ctlr = ctlr->next){ 1667 if(ctlr->active) 1668 continue; 1669 if(type != Iany && ctlr->type != type) 1670 continue; 1671 if(edev->port == 0 || edev->port == ctlr->port){ 1672 ctlr->active = 1; 1673 break; 1674 } 1675 } 1676 if(ctlr == nil) 1677 return -1; 1678 1679 edev->ctlr = ctlr; 1680 ctlr->edev = edev; /* point back to Ether* */ 1681 edev->port = ctlr->port; 1682 edev->irq = ctlr->pcidev->intl; 1683 edev->tbdf = ctlr->pcidev->tbdf; 1684 edev->mbps = 1000; 1685 edev->maxmtu = ctlr->rbsz; 1686 memmove(edev->ea, ctlr->ra, Eaddrlen); 1687 1688 /* 1689 * Linkage to the generic ethernet driver. 1690 */ 1691 edev->attach = i82563attach; 1692 edev->transmit = i82563transmit; 1693 edev->interrupt = (ctlr->type == i82575? 1694 i82575interrupt: i82563interrupt); 1695 edev->ifstat = i82563ifstat; 1696 edev->ctl = i82563ctl; 1697 1698 edev->arg = edev; 1699 edev->promiscuous = i82563promiscuous; 1700 edev->shutdown = i82563shutdown; 1701 edev->multicast = i82563multicast; 1702 1703 return 0; 1704 } 1705 1706 static int 1707 anypnp(Ether *e) 1708 { 1709 return pnp(e, Iany); 1710 } 1711 1712 static int 1713 i82563pnp(Ether *e) 1714 { 1715 return pnp(e, i82563); 1716 } 1717 1718 static int 1719 i82566pnp(Ether *e) 1720 { 1721 return pnp(e, i82566); 1722 } 1723 1724 static int 1725 i82571pnp(Ether *e) 1726 { 1727 return pnp(e, i82571); 1728 } 1729 1730 static int 1731 i82572pnp(Ether *e) 1732 { 1733 return pnp(e, i82572); 1734 } 1735 1736 static int 1737 i82573pnp(Ether *e) 1738 { 1739 return pnp(e, i82573); 1740 } 1741 1742 static int 1743 i82575pnp(Ether *e) 1744 { 1745 return pnp(e, i82575); 1746 } 1747 1748 void 1749 ether82563link(void) 1750 { 1751 /* recognise lots of model numbers for debugging assistance */ 1752 addethercard("i82563", i82563pnp); 1753 addethercard("i82566", i82566pnp); 1754 addethercard("i82571", i82571pnp); 1755 addethercard("i82572", i82572pnp); 1756 addethercard("i82573", i82573pnp); 1757 addethercard("i82575", i82575pnp); 1758 addethercard("igbepcie", anypnp); 1759 } 1760