1 /* 2 * Program Status Registers 3 */ 4 #define PsrMusr 0x00000010 /* mode */ 5 #define PsrMfiq 0x00000011 6 #define PsrMirq 0x00000012 7 #define PsrMsvc 0x00000013 8 #define PsrMabt 0x00000017 9 #define PsrMund 0x0000001B 10 #define PsrMsys 0x0000001F 11 #define PsrMask 0x0000001F 12 13 #define PsrDfiq 0x00000040 /* disable FIQ interrupts */ 14 #define PsrDirq 0x00000080 /* disable IRQ interrupts */ 15 16 #define PsrV 0x10000000 /* overflow */ 17 #define PsrC 0x20000000 /* carry/borrow/extend */ 18 #define PsrZ 0x40000000 /* zero */ 19 #define PsrN 0x80000000 /* negative/less than */ 20 21 /* 22 * Coprocessors 23 */ 24 #define CpSC 15 /* System Control */ 25 26 /* 27 * opcode 1 28 */ 29 #define CpDef 0 /* default */ 30 #define CpL2 1 /* L2 cache operations */ 31 32 /* 33 * Primary (CRn) CpSC registers. 34 */ 35 #define CpID 0 /* ID and cache type */ 36 #define CpCONTROL 1 /* miscellaneous control */ 37 #define CpTTB 2 /* Translation Table Base */ 38 #define CpDAC 3 /* Domain Access Control */ 39 #define CpFSR 5 /* Fault Status */ 40 #define CpFAR 6 /* Fault Address */ 41 #define CpCACHE 7 /* cache/write buffer control */ 42 #define CpTLB 8 /* TLB control */ 43 #define CpCLD 9 /* Cache Lockdown */ 44 #define CpTLD 10 /* TLB Lockdown */ 45 #define CpPID 13 /* Process ID */ 46 #define CpTESTCFG 15 /* test config. (arm926) */ 47 48 /* 49 * CpID opcode2 fields. 50 */ 51 #define CpIDid 0 /* main ID */ 52 #define CpIDct 1 /* cache type */ 53 54 /* 55 * CpCONTROL 56 */ 57 #define CpCmmu 0x00000001 /* M: MMU enable */ 58 #define CpCalign 0x00000002 /* A: alignment fault enable */ 59 #define CpCdcache 0x00000004 /* C: data cache on */ 60 #define CpCwb 0x00000008 /* W: write buffer turned on */ 61 #define CpCi32 0x00000010 /* P: 32-bit program space */ 62 #define CpCd32 0x00000020 /* D: 32-bit data space */ 63 #define CpCbe 0x00000080 /* B: big-endian operation */ 64 #define CpCsystem 0x00000100 /* S: system permission */ 65 #define CpCrom 0x00000200 /* R: ROM permission */ 66 #define CpCicache 0x00001000 /* I: instruction cache on */ 67 #define CpChv 0x00002000 /* V: high vectors */ 68 69 /* 70 * CpCACHE Secondary (CRm) registers and opcode2 fields. 71 * In ARM-speak, 'flush' means invalidate and 'clean' means writeback. 72 */ 73 #define CpCACHEintr 0 /* interrupt */ 74 #define CpCACHEinvi 5 /* instruction */ 75 #define CpCACHEinvd 6 /* data */ 76 #define CpCACHEinvu 7 /* unified */ 77 #define CpCACHEwb 10 /* writeback */ 78 #define CpCACHEwbi 14 /* writeback+invalidate */ 79 80 #define CpCACHEall 0 /* entire */ 81 #define CpCACHEse 1 /* single entry */ 82 #define CpCACHEsi 2 /* set/index */ 83 #define CpCACHEtest 3 /* test loop */ 84 #define CpCACHEwait 4 /* wait */ 85 86 /* 87 * CpTLB Secondary (CRm) registers and opcode2 fields. 88 */ 89 #define CpTLBinvi 5 /* instruction */ 90 #define CpTLBinvd 6 /* data */ 91 #define CpTLBinvu 7 /* unified */ 92 93 #define CpTLBinv 0 /* invalidate all */ 94 #define CpTLBinvse 1 /* invalidate single entry */ 95 96 /* 97 * CpTESTCFG Secondary (CRm) registers and opcode2 fields; sheeva only. 98 */ 99 #define CpTCl2cfg 1 100 #define CpTCl2flush 9 101 #define CpTCl2waylck 10 102 #define CpTCl2inv 11 103 #define CpTCl2perfctl 12 104 #define CpTCl2perfcnt 13 105 106 /* CpTCl2cfg */ 107 #define CpTCl2conf 0 108 109 /* CpTCl2flush & CpTCl2inv */ 110 #define CpTCl2all 0 111 #define CpTCl2seva 1 112 #define CpTCl2way 2 113 #define CpTCl2sepa 3 114 #define CpTCl2valow 4 115 #define CpTCl2vahigh 5 /* also triggers flush or inv */ 116 117 /* CpTCl2flush 118 #define CpTCecccnt 6 /* ecc error count */ 119 #define CpTCeccthr 7 /* ecc error threshold */ 120 121 /* CpTCwaylck */ 122 #define CpTCwaylock 7 123 124 /* CpTCl2inv */ 125 #define CpTCl2erraddr 7 /* ecc error address */ 126 127 /* CpTCl2perfctl */ 128 #define CpTCl2perf0ctl 0 129 #define CpTCl2perf1ctl 1 130 131 /* CpTCl2perfcnt */ 132 #define CpTCl2perf0low 0 133 #define CpTCl2perf0high 1 134 #define CpTCl2perf1low 2 135 #define CpTCl2perf1high 3 136 137 /* 138 * MMU. 139 */ 140 141 #define Fault 0x00000000u /* L[12] */ 142 143 /* in pre-armv7 only, the 0x10 bit must be on */ 144 #define Coarse 0x00000011u /* L1 */ 145 #define Section 0x00000012u /* L1 1MB */ 146 #define Fine 0x00000013u /* L1 */ 147 148 #define Large 0x00000001u /* L2 64KB */ 149 #define Small 0x00000002u /* L2 4KB */ 150 #define Tiny 0x00000003u /* L2 1KB */ 151 #define Buffered 0x00000004u /* L[12] */ 152 #define Cached 0x00000008u /* L[12] */ 153 154 #define Dom0 0 155 #define Noaccess 0 /* AP, DAC */ 156 #define Krw 1 /* AP */ 157 #define Uro 2 /* AP */ 158 #define Urw 3 /* AP */ 159 #define Client 1 /* DAC */ 160 #define Manager 3 /* DAC */ 161 162 #define AP(n, v) F((v), ((n)*2)+4, 2) 163 #define L1AP(ap) (AP(3, (ap))) 164 #define L2AP(ap) (AP(3, (ap))|AP(2, (ap))|AP(1, (ap))|AP(0, (ap))) /* pre-armv7 */ 165 #define DAC(n, v) F((v), (n)*2, 2) 166 167 #define HVECTORS 0xffff0000 /* physical addr of vectors */ 168