1 #include "l.h" 2 3 #define OPVCC(o,xo,oe,rc) (((o)<<26)|((xo)<<1)|((oe)<<10)|((rc)&1)) 4 #define OPCC(o,xo,rc) OPVCC((o),(xo),0,(rc)) 5 #define OP(o,xo) OPVCC((o),(xo),0,0) 6 7 /* the order is dest, a/s, b/imm for both arithmetic and logical operations */ 8 #define AOP_RRR(op,d,a,b) ((op)|(((d)&31L)<<21)|(((a)&31L)<<16)|(((b)&31L)<<11)) 9 #define AOP_IRR(op,d,a,simm) ((op)|(((d)&31L)<<21)|(((a)&31L)<<16)|((simm)&0xFFFF)) 10 #define LOP_RRR(op,a,s,b) ((op)|(((s)&31L)<<21)|(((a)&31L)<<16)|(((b)&31L)<<11)) 11 #define LOP_IRR(op,a,s,uimm) ((op)|(((s)&31L)<<21)|(((a)&31L)<<16)|((uimm)&0xFFFF)) 12 #define OP_BR(op,li,aa) ((op)|((li)&0x03FFFFFC)|((aa)<<1)) 13 #define OP_BC(op,bo,bi,bd,aa) ((op)|(((bo)&0x1F)<<21)|(((bi)&0x1F)<<16)|((bd)&0xFFFC)|((aa)<<1)) 14 #define OP_BCR(op,bo,bi) ((op)|(((bo)&0x1F)<<21)|(((bi)&0x1F)<<16)) 15 #define OP_RLW(op,a,s,sh,mb,me) ((op)|(((s)&31L)<<21)|(((a)&31L)<<16)|(((sh)&31L)<<11)|\ 16 (((mb)&31L)<<6)|(((me)&31L)<<1)) 17 18 #define OP_ADD OPVCC(31,266,0,0) 19 #define OP_ADDI OPVCC(14,0,0,0) 20 #define OP_ADDIS OPVCC(15,0,0,0) 21 #define OP_ANDI OPVCC(28,0,0,0) 22 #define OP_EXTSB OPVCC(31,954,0,0) 23 #define OP_EXTSH OPVCC(31,922,0,0) 24 #define OP_MCRF OPVCC(19,0,0,0) 25 #define OP_MCRFS OPVCC(63,64,0,0) 26 #define OP_MCRXR OPVCC(31,512,0,0) 27 #define OP_MFCR OPVCC(31,19,0,0) 28 #define OP_MFFS OPVCC(63,583,0,0) 29 #define OP_MFMSR OPVCC(31,83,0,0) 30 #define OP_MFSPR OPVCC(31,339,0,0) 31 #define OP_MFSR OPVCC(31,595,0,0) 32 #define OP_MFSRIN OPVCC(31,659,0,0) 33 #define OP_MTCRF OPVCC(31,144,0,0) 34 #define OP_MTFSF OPVCC(63,711,0,0) 35 #define OP_MTFSFI OPVCC(63,134,0,0) 36 #define OP_MTMSR OPVCC(31,146,0,0) 37 #define OP_MTSPR OPVCC(31,467,0,0) 38 #define OP_MTSR OPVCC(31,210,0,0) 39 #define OP_MTSRIN OPVCC(31,242,0,0) 40 #define OP_MULLW OPVCC(31,235,0,0) 41 #define OP_OR OPVCC(31,444,0,0) 42 #define OP_ORI OPVCC(24,0,0,0) 43 #define OP_RLWINM OPVCC(21,0,0,0) 44 #define OP_SUBF OPVCC(31,40,0,0) 45 46 #define oclass(v) ((v).class-1) 47 48 long oprrr(int), opirr(int), opload(int), opstore(int), oploadx(int), opstorex(int); 49 50 int 51 getmask(uchar *m, ulong v) 52 { 53 int i; 54 55 m[0] = m[1] = 0; 56 if(v != ~0L && v & (1<<31) && v & 1){ /* MB > ME */ 57 if(getmask(m, ~v)){ 58 i = m[0]; m[0] = m[1]+1; m[1] = i-1; 59 return 1; 60 } 61 return 0; 62 } 63 for(i=0; i<32; i++) 64 if(v & (1<<(31-i))){ 65 m[0] = i; 66 do { 67 m[1] = i; 68 } while(++i<32 && (v & (1<<(31-i))) != 0); 69 for(; i<32; i++) 70 if(v & (1<<(31-i))) 71 return 0; 72 return 1; 73 } 74 return 0; 75 } 76 77 void 78 maskgen(Prog *p, uchar *m, ulong v) 79 { 80 if(!getmask(m, v)) 81 diag("cannot generate mask #%lux\n%P", v, p); 82 } 83 84 int 85 asmout(Prog *p, Optab *o, int aflag) 86 { 87 long o1, o2, o3, o4, o5, v; 88 Prog *ct; 89 int r, a; 90 uchar mask[2]; 91 92 o1 = 0; 93 o2 = 0; 94 o3 = 0; 95 o4 = 0; 96 o5 = 0; 97 switch(o->type) { 98 default: 99 if(aflag) 100 return 0; 101 diag("unknown type %d", o->type); 102 if(!debug['a']) 103 prasm(p); 104 break; 105 106 case 0: /* pseudo ops */ 107 if(aflag) { 108 if(p->link) { 109 if(p->as == ATEXT) { 110 ct = curtext; 111 o2 = autosize; 112 curtext = p; 113 autosize = p->to.offset + 4; 114 o1 = asmout(p->link, oplook(p->link), aflag); 115 curtext = ct; 116 autosize = o2; 117 } else 118 o1 = asmout(p->link, oplook(p->link), aflag); 119 } 120 return o1; 121 } 122 break; 123 124 case 1: /* mov r1,r2 ==> OR Rs,Rs,Ra */ 125 o1 = LOP_RRR(OP_OR, p->to.reg, p->from.reg, p->from.reg); 126 break; 127 128 case 2: /* int/cr/fp op Rb,[Ra],Rd */ 129 r = p->reg; 130 if(r == NREG) 131 r = p->to.reg; 132 o1 = AOP_RRR(oprrr(p->as), p->to.reg, r, p->from.reg); 133 break; 134 135 case 3: /* mov $soreg/addcon/ucon, r ==> addis/addi $i,reg',r */ 136 v = regoff(&p->from); 137 r = p->from.reg; 138 if(r == NREG) 139 r = o->param; 140 a = OP_ADDI; 141 if(o->a1 == C_UCON) { 142 a = OP_ADDIS; 143 v >>= 16; 144 } 145 o1 = AOP_IRR(a, p->to.reg, r, v); 146 break; 147 148 case 4: /* add/mul $scon,[r1],r2 */ 149 v = regoff(&p->from); 150 r = p->reg; 151 if(r == NREG) 152 r = p->to.reg; 153 else if(p->as == AADD && r == 0) 154 diag("literal operation on R0\n%P", p); 155 o1 = AOP_IRR(opirr(p->as), p->to.reg, r, v); 156 break; 157 158 case 5: /* syscall */ 159 if(aflag) 160 return 0; 161 o1 = oprrr(p->as); 162 break; 163 164 case 6: /* logical op Rb,[Rs,]Ra; no literal */ 165 r = p->reg; 166 if(r == NREG) 167 r = p->to.reg; 168 o1 = LOP_RRR(oprrr(p->as), p->to.reg, r, p->from.reg); 169 break; 170 171 case 7: /* mov r, soreg ==> stw o(r) */ 172 r = p->to.reg; 173 if(r == NREG) 174 r = o->param; 175 v = regoff(&p->to); 176 if(p->to.type == D_OREG && p->reg != NREG) { 177 if(v) 178 diag("illegal indexed instruction\n%P", p); 179 o1 = AOP_RRR(opstorex(p->as), p->from.reg, p->reg, r); 180 } else 181 o1 = AOP_IRR(opstore(p->as), p->from.reg, r, v); 182 break; 183 184 case 8: /* mov soreg, r ==> lbz/lhz/lwz o(r) */ 185 r = p->from.reg; 186 if(r == NREG) 187 r = o->param; 188 v = regoff(&p->from); 189 if(p->from.type == D_OREG && p->reg != NREG) { 190 if(v) 191 diag("illegal indexed instruction\n%P", p); 192 o1 = AOP_RRR(oploadx(p->as), p->to.reg, p->reg, r); 193 } else 194 o1 = AOP_IRR(opload(p->as), p->to.reg, r, v); 195 break; 196 197 case 9: /* movb soreg, r ==> lbz o(r),r2; extsb r2,r2 */ 198 r = p->from.reg; 199 if(r == NREG) 200 r = o->param; 201 v = regoff(&p->from); 202 if(p->from.type == D_OREG && p->reg != NREG) { 203 if(v) 204 diag("illegal indexed instruction\n%P", p); 205 o1 = AOP_RRR(oploadx(p->as), p->to.reg, p->reg, r); 206 } else 207 o1 = AOP_IRR(opload(p->as), p->to.reg, r, v); 208 o2 = LOP_RRR(OP_EXTSB, p->to.reg, p->to.reg, 0); 209 break; 210 211 case 10: /* sub Ra,[Rb],Rd => subf Rd,Ra,Rb */ 212 r = p->reg; 213 if(r == NREG) 214 r = p->to.reg; 215 o1 = AOP_RRR(oprrr(p->as), p->to.reg, p->from.reg, r); 216 break; 217 218 case 11: /* br/bl lbra */ 219 if(aflag) 220 return 0; 221 v = 0; 222 if(p->cond) 223 v = p->cond->pc - p->pc; 224 if(v & 03) { 225 diag("odd branch target address\n%P", p); 226 v &= ~03; 227 } 228 if(v < -(1L<<25) || v >= (1L<<25)) 229 diag("branch too far\n%P", p); 230 o1 = OP_BR(opirr(p->as), v, 0); 231 break; 232 233 case 12: /* movb r,r (signed); extsb is on PowerPC but not POWER */ 234 o1 = LOP_RRR(OP_EXTSB, p->to.reg, p->from.reg, 0); 235 break; 236 237 case 13: /* mov[bh]z r,r; uses rlwinm not andi. to avoid changing CC */ 238 if(p->as == AMOVBZ) 239 o1 = OP_RLW(OP_RLWINM, p->to.reg, p->from.reg, 0, 24, 31); 240 else if(p->as == AMOVH) 241 o1 = LOP_RRR(OP_EXTSH, p->to.reg, p->from.reg, 0); 242 else if(p->as == AMOVHZ) 243 o1 = OP_RLW(OP_RLWINM, p->to.reg, p->from.reg, 0, 16, 31); 244 else 245 diag("internal: bad mov[bh]z\n%P", p); 246 break; 247 248 /*14 */ 249 250 case 17: /* bc bo,bi,lbra (same for now) */ 251 case 16: /* bc bo,bi,sbra */ 252 if(aflag) 253 return 0; 254 a = 0; 255 if(p->from.type == D_CONST) 256 a = regoff(&p->from); 257 r = p->reg; 258 if(r == NREG) 259 r = 0; 260 v = 0; 261 if(p->cond) 262 v = p->cond->pc - p->pc; 263 if(v & 03) { 264 diag("odd branch target address\n%P", p); 265 v &= ~03; 266 } 267 if(v < -(1L<<16) || v >= (1L<<16)) 268 diag("branch too far\n%P", p); 269 o1 = OP_BC(opirr(p->as), a, r, v, 0); 270 break; 271 272 case 15: /* br/bl (r) => mov r,lr; br/bl (lr) */ 273 if(aflag) 274 return 0; 275 if(p->as == ABC || p->as == ABCL) 276 v = regoff(&p->to)&31L; 277 else 278 v = 20; /* unconditional */ 279 r = p->reg; 280 if(r == NREG) 281 r = 0; 282 o1 = AOP_RRR(OP_MTSPR, p->to.reg, 0, 0) | ((D_LR&0x1f)<<16) | (((D_LR>>5)&0x1f)<<11); 283 o2 = OPVCC(19, 16, 0, 0); 284 if(p->as == ABL || p->as == ABCL) 285 o2 |= 1; 286 o2 = OP_BCR(o2, v, r); 287 break; 288 289 case 18: /* br/bl (lr/ctr); bc/bcl bo,bi,(lr/ctr) */ 290 if(aflag) 291 return 0; 292 if(p->as == ABC || p->as == ABCL) 293 v = regoff(&p->from)&31L; 294 else 295 v = 20; /* unconditional */ 296 r = p->reg; 297 if(r == NREG) 298 r = 0; 299 switch(oclass(p->to)) { 300 case C_CTR: 301 o1 = OPVCC(19, 528, 0, 0); 302 break; 303 case C_LR: 304 o1 = OPVCC(19, 16, 0, 0); 305 break; 306 default: 307 diag("bad optab entry (18): %d\n%P", p->to.class, p); 308 v = 0; 309 } 310 if(p->as == ABL || p->as == ABCL) 311 o1 |= 1; 312 o1 = OP_BCR(o1, v, r); 313 break; 314 315 case 19: /* mov $lcon,r ==> cau+or */ 316 v = regoff(&p->from); 317 o1 = AOP_IRR(OP_ADDIS, p->to.reg, REGZERO, v>>16); 318 o2 = LOP_IRR(OP_ORI, p->to.reg, p->to.reg, v); 319 break; 320 321 case 20: /* add $ucon,,r */ 322 v = regoff(&p->from); 323 r = p->reg; 324 if(r == NREG) 325 r = p->to.reg; 326 if(p->as == AADD && r == 0) 327 diag("literal operation on R0\n%P", p); 328 o1 = AOP_IRR(opirr(p->as+AEND), p->to.reg, r, v>>16); 329 break; 330 331 case 22: /* add $lcon,r1,r2 ==> cau+or+add */ /* could do add/sub more efficiently */ 332 v = regoff(&p->from); 333 if(p->to.reg == REGTMP || p->reg == REGTMP) 334 diag("cant synthesize large constant\n%P", p); 335 o1 = AOP_IRR(OP_ADDIS, REGTMP, REGZERO, v>>16); 336 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, v); 337 r = p->reg; 338 if(r == NREG) 339 r = p->to.reg; 340 o3 = AOP_RRR(oprrr(p->as), p->to.reg, REGTMP, r); 341 break; 342 343 case 23: /* and $lcon,r1,r2 ==> cau+or+and */ /* masks could be done using rlnm etc. */ 344 v = regoff(&p->from); 345 if(p->to.reg == REGTMP || p->reg == REGTMP) 346 diag("cant synthesize large constant\n%P", p); 347 o1 = AOP_IRR(OP_ADDIS, REGTMP, REGZERO, v>>16); 348 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, v); 349 r = p->reg; 350 if(r == NREG) 351 r = p->to.reg; 352 o3 = LOP_RRR(oprrr(p->as), p->to.reg, REGTMP, r); 353 break; 354 /*24*/ 355 356 case 26: /* mov $lsext/auto/oreg,,r2 ==> cau+add */ 357 v = regoff(&p->from); 358 if(v & 0x8000L) 359 v += 0x10000L; 360 if(p->to.reg == REGTMP) 361 diag("can't synthesize large constant\n%P", p); 362 r = p->from.reg; 363 if(r == NREG) 364 r = o->param; 365 o1 = AOP_IRR(OP_ADDIS, REGTMP, r, v>>16); 366 o2 = AOP_IRR(OP_ADDI, p->to.reg, REGTMP, v); 367 break; 368 369 case 27: /* subc ra,$simm,rd => subfic rd,ra,$simm */ 370 v = regoff(&p->from3); 371 r = p->from.reg; 372 o1 = AOP_IRR(opirr(p->as), p->to.reg, r, v); 373 break; 374 375 case 28: /* subc r1,$lcon,r2 ==> cau+or+subfc */ 376 v = regoff(&p->from3); 377 if(p->to.reg == REGTMP || p->from.reg == REGTMP) 378 diag("can't synthesize large constant\n%P", p); 379 o1 = AOP_IRR(OP_ADDIS, REGTMP, REGZERO, v>>16); 380 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, v); 381 o3 = AOP_RRR(oprrr(p->as), p->to.reg, p->from.reg, REGTMP); 382 break; 383 384 /*29, 30, 31 */ 385 386 case 32: /* fmul frc,fra,frd */ 387 r = p->reg; 388 if(r == NREG) 389 r = p->to.reg; 390 o1 = AOP_RRR(oprrr(p->as), p->to.reg, r, 0)|((p->from.reg&31L)<<6); 391 break; 392 393 case 33: /* fabs [frb,]frd; fmr. frb,frd */ 394 r = p->from.reg; 395 if(oclass(p->from) == C_NONE) 396 r = p->to.reg; 397 o1 = AOP_RRR(oprrr(p->as), p->to.reg, 0, r); 398 break; 399 400 case 34: /* FMADDx fra,frb,frc,frd (d=a*b+c) */ 401 o1 = AOP_RRR(oprrr(p->as), p->to.reg, p->from.reg, p->reg)|((p->from3.reg&31L)<<6); 402 break; 403 404 case 35: /* mov r,lext/lauto/loreg ==> cau $(v>>16),sb,r'; store o(r') */ 405 v = regoff(&p->to); 406 if(v & 0x8000L) 407 v += 0x10000L; 408 r = p->to.reg; 409 if(r == NREG) 410 r = o->param; 411 o1 = AOP_IRR(OP_ADDIS, REGTMP, r, v>>16); 412 o2 = AOP_IRR(opstore(p->as), p->from.reg, REGTMP, v); 413 break; 414 415 case 36: /* mov bz/h/hz lext/lauto/lreg,r ==> lbz/lha/lhz etc */ 416 v = regoff(&p->from); 417 if(v & 0x8000L) 418 v += 0x10000L; 419 r = p->from.reg; 420 if(r == NREG) 421 r = o->param; 422 o1 = AOP_IRR(OP_ADDIS, REGTMP, r, v>>16); 423 o2 = AOP_IRR(opload(p->as), p->to.reg, REGTMP, v); 424 break; 425 426 case 37: /* movb lext/lauto/lreg,r ==> lbz o(reg),r; extsb r */ 427 v = regoff(&p->from); 428 if(v & 0x8000L) 429 v += 0x10000L; 430 r = p->from.reg; 431 if(r == NREG) 432 r = o->param; 433 o1 = AOP_IRR(OP_ADDIS, REGTMP, r, v>>16); 434 o2 = AOP_IRR(opload(p->as), p->to.reg, REGTMP, v); 435 o3 = LOP_RRR(OP_EXTSB, p->to.reg, p->to.reg, 0); 436 break; 437 438 case 40: /* word */ 439 if(aflag) 440 return 0; 441 o1 = regoff(&p->from); 442 break; 443 444 case 41: /* stswi */ 445 o1 = AOP_RRR(opirr(p->as), p->from.reg, p->to.reg, 0) | ((regoff(&p->from3)&0x7F)<<11); 446 break; 447 448 case 42: /* lswi */ 449 o1 = AOP_RRR(opirr(p->as), p->to.reg, p->from.reg, 0) | ((regoff(&p->from3)&0x7F)<<11); 450 break; 451 452 case 43: /* unary indexed source: dcbf (b); dcbf (a+b) */ 453 r = p->reg; 454 if(r == NREG) 455 r = 0; 456 o1 = AOP_RRR(oprrr(p->as), 0, r, p->from.reg); 457 break; 458 459 case 44: /* indexed store */ 460 r = p->reg; 461 if(r == NREG) 462 r = 0; 463 o1 = AOP_RRR(opstorex(p->as), p->from.reg, r, p->to.reg); 464 break; 465 case 45: /* indexed load */ 466 r = p->reg; 467 if(r == NREG) 468 r = 0; 469 o1 = AOP_RRR(oploadx(p->as), p->to.reg, r, p->from.reg); 470 break; 471 472 case 46: /* plain op */ 473 o1 = oprrr(p->as); 474 break; 475 476 case 47: /* op Ra, Rd; also op [Ra,] Rd */ 477 r = p->from.reg; 478 if(r == NREG) 479 r = p->to.reg; 480 o1 = AOP_RRR(oprrr(p->as), p->to.reg, r, 0); 481 break; 482 483 case 48: /* op Rs, Ra */ 484 r = p->from.reg; 485 if(r == NREG) 486 r = p->to.reg; 487 o1 = LOP_RRR(oprrr(p->as), p->to.reg, r, 0); 488 break; 489 490 case 49: /* op Rb */ 491 o1 = AOP_RRR(oprrr(p->as), 0, 0, p->from.reg); 492 break; 493 494 /*50*/ 495 496 case 51: /* rem[u] r1[,r2],r3 */ 497 r = p->reg; 498 if(r == NREG) 499 r = p->to.reg; 500 o1 = AOP_RRR(oprrr(p->as), REGTMP, r, p->from.reg); 501 o2 = AOP_RRR(OP_MULLW, REGTMP, REGTMP, p->from.reg); 502 o3 = AOP_RRR(OP_SUBF, p->to.reg, REGTMP, r); /* BUG: check V, CC */ 503 break; 504 505 case 52: /* mtfsbNx cr(n) */ 506 v = regoff(&p->from)&31L; 507 o1 = AOP_RRR(oprrr(p->as), v, 0, 0); 508 break; 509 510 case 53: /* mffsX ,fr1 */ 511 o1 = AOP_RRR(OP_MFFS, p->to.reg, 0, 0); 512 break; 513 514 case 54: /* mov msr,r1; mov r1, msr*/ 515 if(oclass(p->from) == C_REG) 516 o1 = AOP_RRR(OP_MTMSR, p->from.reg, 0, 0); 517 else 518 o1 = AOP_RRR(OP_MFMSR, p->to.reg, 0, 0); 519 break; 520 521 case 55: /* mov sreg,r1; mov r1,sreg */ 522 v = 0; 523 if(p->from.type == D_SREG) { 524 r = p->from.reg; 525 o1 = OP_MFSR; 526 if(r == NREG && p->reg != NREG) { 527 r = 0; 528 v = p->reg; 529 o1 = OP_MFSRIN; 530 } 531 o1 = AOP_RRR(o1, p->to.reg, r&15L, v); 532 } else { 533 r = p->to.reg; 534 o1 = OP_MTSR; 535 if(r == NREG && p->reg != NREG) { 536 r = 0; 537 v = p->reg; 538 o1 = OP_MTSRIN; 539 } 540 o1 = AOP_RRR(o1, p->from.reg, r&15L, v); 541 } 542 if(r == NREG) 543 diag("illegal move indirect to/from segment register\n%P", p); 544 break; 545 546 case 56: /* sra $sh,[s,]a */ 547 v = regoff(&p->from); 548 r = p->reg; 549 if(r == NREG) 550 r = p->to.reg; 551 o1 = AOP_RRR(opirr(p->as), r, p->to.reg, v&31L); 552 break; 553 554 case 57: /* slw $sh,[s,]a -> rlwinm ... */ 555 v = regoff(&p->from); 556 r = p->reg; 557 if(r == NREG) 558 r = p->to.reg; 559 if(v < 0 || v > 31) 560 diag("illegal shift %ld\n%P", v, p); 561 if(v < 0) 562 v = 0; 563 else if(v > 32) 564 v = 32; 565 if(p->as == ASRW || p->as == ASRWCC) { /* shift right */ 566 mask[0] = v; 567 mask[1] = 31; 568 v = 32-v; 569 } else { 570 mask[0] = 0; 571 mask[1] = 31-v; 572 } 573 o1 = OP_RLW(OP_RLWINM, p->to.reg, r, v, mask[0], mask[1]); 574 if(p->as == ASLWCC || p->as == ASRWCC) 575 o1 |= 1; /* Rc */ 576 break; 577 578 case 58: /* logical $andcon,[s],a */ 579 v = regoff(&p->from); 580 r = p->reg; 581 if(r == NREG) 582 r = p->to.reg; 583 o1 = LOP_IRR(opirr(p->as), p->to.reg, r, v); 584 break; 585 586 case 59: /* or/and $ucon,,r */ 587 v = regoff(&p->from); 588 r = p->reg; 589 if(r == NREG) 590 r = p->to.reg; 591 o1 = LOP_IRR(opirr(p->as+AEND), p->to.reg, r, v>>16); /* oris, xoris, andis */ 592 break; 593 594 case 60: /* tw to,a,b */ 595 r = regoff(&p->from)&31L; 596 o1 = AOP_RRR(oprrr(p->as), r, p->reg, p->to.reg); 597 break; 598 599 case 61: /* tw to,a,$simm */ 600 r = regoff(&p->from)&31L; 601 v = regoff(&p->to); 602 o1 = AOP_IRR(opirr(p->as), r, p->reg, v); 603 break; 604 605 case 62: /* rlwmi $sh,s,$mask,a */ 606 v = regoff(&p->from); 607 maskgen(p, mask, regoff(&p->from3)); 608 o1 = AOP_RRR(opirr(p->as), p->reg, p->to.reg, v); 609 o1 |= ((mask[0]&31L)<<6)|((mask[1]&31L)<<1); 610 break; 611 612 case 63: /* rlwmi b,s,$mask,a */ 613 maskgen(p, mask, regoff(&p->from3)); 614 o1 = AOP_RRR(opirr(p->as), p->reg, p->to.reg, p->from.reg); 615 o1 |= ((mask[0]&31L)<<6)|((mask[1]&31L)<<1); 616 break; 617 618 case 64: /* mtfsf fr[, $m] {,fpcsr} */ 619 if(p->from3.type != D_NONE) 620 v = regoff(&p->from3)&255L; 621 else 622 v = 255; 623 o1 = OP_MTFSF | (v<<17) | (p->from.reg<<11); 624 break; 625 626 case 65: /* MOVFL $imm,FPSCR(n) => mtfsfi crfd,imm */ 627 if(p->to.reg == NREG) 628 diag("must specify FPSCR(n)\n%P", p); 629 o1 = OP_MTFSFI | ((p->to.reg&15L)<<23) | ((regoff(&p->from)&31L)<<12); 630 break; 631 632 case 66: /* mov spr,r1; mov r1,spr */ 633 if(p->from.type == D_REG) { 634 r = p->from.reg; 635 v = p->to.offset; 636 o1 = OPVCC(31,467,0,0); /* mtspr */ 637 } else { 638 r = p->to.reg; 639 v = p->from.offset; 640 o1 = OPVCC(31,339,0,0); /* mfspr */ 641 } 642 o1 = AOP_RRR(o1, r, 0, 0) | ((v&0x1f)<<16) | (((v>>5)&0x1f)<<11); 643 break; 644 645 case 67: /* mcrf crfD,crfS */ 646 if(p->from.type != D_CREG || p->from.reg == NREG || 647 p->to.type != D_CREG || p->to.reg == NREG) 648 diag("illegal CR field number\n%P", p); 649 o1 = AOP_RRR(OP_MCRF, ((p->to.reg&7L)<<2), ((p->from.reg&7)<<2), 0); 650 break; 651 652 case 68: /* mfcr rD */ 653 if(p->from.type == D_CREG && p->from.reg != NREG) 654 diag("must move whole CR to register\n%P", p); 655 o1 = AOP_RRR(OP_MFCR, p->to.reg, 0, 0); 656 break; 657 658 case 69: /* mtcrf CRM,rS */ 659 if(p->from3.type != D_NONE) { 660 if(p->to.reg != NREG) 661 diag("can't use both mask and CR(n)\n%P", p); 662 v = regoff(&p->from3) & 0xff; 663 } else { 664 if(p->to.reg == NREG) 665 v = 0xff; /* CR */ 666 else 667 v = 1<<(7-(p->to.reg&7)); /* CR(n) */ 668 } 669 o1 = AOP_RRR(OP_MTCRF, p->from.reg, 0, 0) | (v<<12); 670 break; 671 672 case 70: /* [f]cmp r,r,cr*/ 673 if(p->reg == NREG) 674 r = 0; 675 else 676 r = (p->reg&7)<<2; 677 o1 = AOP_RRR(oprrr(p->as), r, p->from.reg, p->to.reg); 678 break; 679 680 case 71: /* cmp[l] r,i,cr*/ 681 if(p->reg == NREG) 682 r = 0; 683 else 684 r = (p->reg&7)<<2; 685 o1 = AOP_RRR(opirr(p->as), r, p->from.reg, 0) | (regoff(&p->to)&0xffff); 686 break; 687 688 case 72: /* mcrxr crfD */ 689 if(p->to.reg == NREG) 690 diag("must move XER to CR(n)\n%P", p); 691 o1 = AOP_RRR(OP_MCRXR, ((p->to.reg&7L)<<2), 0, 0); 692 break; 693 694 case 73: /* mcrfs crfD,crfS */ 695 if(p->from.type != D_FPSCR || p->from.reg == NREG || 696 p->to.type != D_CREG || p->to.reg == NREG) 697 diag("illegal FPSCR/CR field number\n%P", p); 698 o1 = AOP_RRR(OP_MCRFS, ((p->to.reg&7L)<<2), ((p->from.reg&7)<<2), 0); 699 break; 700 701 } 702 if(aflag) 703 return o1; 704 v = p->pc; 705 switch(o->size) { 706 default: 707 if(debug['a']) 708 Bprint(&bso, " %.8lux:\t\t%P\n", v, p); 709 break; 710 case 4: 711 if(debug['a']) 712 Bprint(&bso, " %.8lux: %.8lux\t%P\n", v, o1, p); 713 lput(o1); 714 break; 715 case 8: 716 if(debug['a']) 717 Bprint(&bso, " %.8lux: %.8lux %.8lux%P\n", v, o1, o2, p); 718 lput(o1); 719 lput(o2); 720 break; 721 case 12: 722 if(debug['a']) 723 Bprint(&bso, " %.8lux: %.8lux %.8lux %.8lux%P\n", v, o1, o2, o3, p); 724 lput(o1); 725 lput(o2); 726 lput(o3); 727 break; 728 case 16: 729 if(debug['a']) 730 Bprint(&bso, " %.8lux: %.8lux %.8lux %.8lux %.8lux%P\n", 731 v, o1, o2, o3, o4, p); 732 lput(o1); 733 lput(o2); 734 lput(o3); 735 lput(o4); 736 break; 737 case 20: 738 if(debug['a']) 739 Bprint(&bso, " %.8lux: %.8lux %.8lux %.8lux %.8lux %.8lux%P\n", 740 v, o1, o2, o3, o4, o5, p); 741 lput(o1); 742 lput(o2); 743 lput(o3); 744 lput(o4); 745 lput(o5); 746 break; 747 } 748 return 0; 749 } 750 751 long 752 oprrr(int a) 753 { 754 switch(a) { 755 case AADD: return OPVCC(31,266,0,0); 756 case AADDCC: return OPVCC(31,266,0,1); 757 case AADDV: return OPVCC(31,266,1,0); 758 case AADDVCC: return OPVCC(31,266,1,1); 759 case AADDC: return OPVCC(31,10,0,0); 760 case AADDCCC: return OPVCC(31,10,0,1); 761 case AADDCV: return OPVCC(31,10,1,0); 762 case AADDCVCC: return OPVCC(31,10,1,1); 763 case AADDE: return OPVCC(31,138,0,0); 764 case AADDECC: return OPVCC(31,138,0,1); 765 case AADDEV: return OPVCC(31,138,1,0); 766 case AADDEVCC: return OPVCC(31,138,1,1); 767 case AADDME: return OPVCC(31,234,0,0); 768 case AADDMECC: return OPVCC(31,234,0,1); 769 case AADDMEV: return OPVCC(31,234,1,0); 770 case AADDMEVCC: return OPVCC(31,234,1,1); 771 case AADDZE: return OPVCC(31,202,0,0); 772 case AADDZECC: return OPVCC(31,202,0,1); 773 case AADDZEV: return OPVCC(31,202,1,0); 774 case AADDZEVCC: return OPVCC(31,202,1,1); 775 776 case AAND: return OPVCC(31,28,0,0); 777 case AANDCC: return OPVCC(31,28,0,1); 778 case AANDN: return OPVCC(31,60,0,0); 779 case AANDNCC: return OPVCC(31,60,0,1); 780 781 case ACMP: return OPVCC(31,0,0,0); 782 case ACMPU: return OPVCC(31,32,0,0); 783 784 case ACNTLZW: return OPVCC(31,26,0,0); 785 case ACNTLZWCC: return OPVCC(31,26,0,1); 786 787 case ACRAND: return OPVCC(19,257,0,0); 788 case ACRANDN: return OPVCC(19,129,0,0); 789 case ACREQV: return OPVCC(19,289,0,0); 790 case ACRNAND: return OPVCC(19,225,0,0); 791 case ACRNOR: return OPVCC(19,33,0,0); 792 case ACROR: return OPVCC(19,449,0,0); 793 case ACRORN: return OPVCC(19,417,0,0); 794 case ACRXOR: return OPVCC(19,193,0,0); 795 796 case ADCBF: return OPVCC(31,86,0,0); 797 case ADCBI: return OPVCC(31,470,0,0); 798 case ADCBST: return OPVCC(31,54,0,0); 799 case ADCBT: return OPVCC(31,278,0,0); 800 case ADCBTST: return OPVCC(31,246,0,0); 801 case ADCBZ: return OPVCC(31,1014,0,0); 802 803 case AREM: 804 case ADIVW: return OPVCC(31,491,0,0); 805 case AREMCC: 806 case ADIVWCC: return OPVCC(31,491,0,1); 807 case AREMV: 808 case ADIVWV: return OPVCC(31,491,1,0); 809 case AREMVCC: 810 case ADIVWVCC: return OPVCC(31,491,1,1); 811 case AREMU: 812 case ADIVWU: return OPVCC(31,459,0,0); 813 case AREMUCC: 814 case ADIVWUCC: return OPVCC(31,459,0,1); 815 case AREMUV: 816 case ADIVWUV: return OPVCC(31,459,1,0); 817 case AREMUVCC: 818 case ADIVWUVCC: return OPVCC(31,459,1,1); 819 820 case AEIEIO: return OPVCC(31,854,0,0); 821 822 case AEQV: return OPVCC(31,284,0,0); 823 case AEQVCC: return OPVCC(31,284,0,1); 824 825 case AEXTSB: return OPVCC(31,954,0,0); 826 case AEXTSBCC: return OPVCC(31,954,0,1); 827 case AEXTSH: return OPVCC(31,922,0,0); 828 case AEXTSHCC: return OPVCC(31,922,0,1); 829 830 case AFABS: return OPVCC(63,264,0,0); 831 case AFABSCC: return OPVCC(63,264,0,1); 832 case AFADD: return OPVCC(63,21,0,0); 833 case AFADDCC: return OPVCC(63,21,0,1); 834 case AFADDS: return OPVCC(59,21,0,0); 835 case AFADDSCC: return OPVCC(59,21,0,1); 836 case AFCMPO: return OPVCC(63,32,0,0); 837 case AFCMPU: return OPVCC(63,0,0,0); 838 case AFCTIW: return OPVCC(63,14,0,0); 839 case AFCTIWCC: return OPVCC(63,14,0,1); 840 case AFCTIWZ: return OPVCC(63,15,0,0); 841 case AFCTIWZCC: return OPVCC(63,15,0,1); 842 case AFDIV: return OPVCC(63,18,0,0); 843 case AFDIVCC: return OPVCC(63,18,0,1); 844 case AFDIVS: return OPVCC(59,18,0,0); 845 case AFDIVSCC: return OPVCC(59,18,0,1); 846 case AFMADD: return OPVCC(63,29,0,0); 847 case AFMADDCC: return OPVCC(63,29,0,1); 848 case AFMADDS: return OPVCC(59,29,0,0); 849 case AFMADDSCC: return OPVCC(59,29,0,1); 850 case AFMOVS: 851 case AFMOVD: return OPVCC(63,72,0,0); /* load */ 852 case AFMOVDCC: return OPVCC(63,72,0,1); 853 case AFMSUB: return OPVCC(63,28,0,0); 854 case AFMSUBCC: return OPVCC(63,28,0,1); 855 case AFMSUBS: return OPVCC(59,28,0,0); 856 case AFMSUBSCC: return OPVCC(59,28,0,1); 857 case AFMUL: return OPVCC(63,25,0,0); 858 case AFMULCC: return OPVCC(63,25,0,1); 859 case AFMULS: return OPVCC(59,25,0,0); 860 case AFMULSCC: return OPVCC(59,25,0,1); 861 case AFNABS: return OPVCC(63,136,0,0); 862 case AFNABSCC: return OPVCC(63,136,0,1); 863 case AFNEG: return OPVCC(63,40,0,0); 864 case AFNEGCC: return OPVCC(63,40,0,1); 865 case AFNMADD: return OPVCC(63,31,0,0); 866 case AFNMADDCC: return OPVCC(63,31,0,1); 867 case AFNMADDS: return OPVCC(59,31,0,0); 868 case AFNMADDSCC: return OPVCC(59,31,0,1); 869 case AFNMSUB: return OPVCC(63,30,0,0); 870 case AFNMSUBCC: return OPVCC(63,30,0,1); 871 case AFNMSUBS: return OPVCC(59,30,0,0); 872 case AFNMSUBSCC: return OPVCC(59,30,0,1); 873 case AFRSP: return OPVCC(63,12,0,0); 874 case AFRSPCC: return OPVCC(63,12,0,1); 875 case AFSUB: return OPVCC(63,20,0,0); 876 case AFSUBCC: return OPVCC(63,20,0,1); 877 case AFSUBS: return OPVCC(59,20,0,0); 878 case AFSUBSCC: return OPVCC(59,20,0,1); 879 880 case AICBI: return OPVCC(31,982,0,0); 881 case AISYNC: return OPVCC(19,150,0,0); 882 883 /* lscb etc are not PowerPC instructions */ 884 885 case AMTFSB0: return OPVCC(63,70,0,0); 886 case AMTFSB0CC: return OPVCC(63,70,0,1); 887 case AMTFSB1: return OPVCC(63,38,0,0); 888 case AMTFSB1CC: return OPVCC(63,38,0,1); 889 890 case AMULHW: return OPVCC(31,75,0,0); 891 case AMULHWCC: return OPVCC(31,75,0,1); 892 case AMULHWU: return OPVCC(31,11,0,0); 893 case AMULHWUCC: return OPVCC(31,11,0,1); 894 case AMULLW: return OPVCC(31,235,0,0); 895 case AMULLWCC: return OPVCC(31,235,0,1); 896 case AMULLWV: return OPVCC(31,235,1,0); 897 case AMULLWVCC: return OPVCC(31,235,1,1); 898 899 case ANAND: return OPVCC(31,476,0,0); 900 case ANANDCC: return OPVCC(31,476,0,1); 901 case ANEG: return OPVCC(31,104,0,0); 902 case ANEGCC: return OPVCC(31,104,0,1); 903 case ANEGV: return OPVCC(31,104,1,0); 904 case ANEGVCC: return OPVCC(31,104,1,1); 905 case ANOR: return OPVCC(31,124,0,0); 906 case ANORCC: return OPVCC(31,124,0,1); 907 case AOR: return OPVCC(31,444,0,0); 908 case AORCC: return OPVCC(31,444,0,1); 909 case AORN: return OPVCC(31,412,0,0); 910 case AORNCC: return OPVCC(31,412,0,1); 911 912 case ARFI: return OPVCC(19,50,0,0); 913 914 case ARLWMI: return OPVCC(20,0,0,0); 915 case ARLWMICC: return OPVCC(20,0,0,1); 916 case ARLWNM: return OPVCC(23,0,0,0); 917 case ARLWNMCC: return OPVCC(23,0,0,1); 918 919 case ASYSCALL: return OPVCC(17,1,0,0); 920 921 case ASLW: return OPVCC(31,24,0,0); 922 case ASLWCC: return OPVCC(31,24,0,1); 923 924 case ASRAW: return OPVCC(31,792,0,0); 925 case ASRAWCC: return OPVCC(31,792,0,1); 926 927 case ASRW: return OPVCC(31,536,0,0); 928 case ASRWCC: return OPVCC(31,536,0,1); 929 930 case ASUB: return OPVCC(31,40,0,0); 931 case ASUBCC: return OPVCC(31,40,0,1); 932 case ASUBV: return OPVCC(31,40,1,0); 933 case ASUBVCC: return OPVCC(31,40,1,1); 934 case ASUBC: return OPVCC(31,8,0,0); 935 case ASUBCCC: return OPVCC(31,8,0,1); 936 case ASUBCV: return OPVCC(31,8,1,0); 937 case ASUBCVCC: return OPVCC(31,8,1,1); 938 case ASUBE: return OPVCC(31,136,0,0); 939 case ASUBECC: return OPVCC(31,136,0,1); 940 case ASUBEV: return OPVCC(31,136,1,0); 941 case ASUBEVCC: return OPVCC(31,136,1,1); 942 case ASUBME: return OPVCC(31,232,0,0); 943 case ASUBMECC: return OPVCC(31,232,0,1); 944 case ASUBMEV: return OPVCC(31,232,1,0); 945 case ASUBMEVCC: return OPVCC(31,232,1,1); 946 case ASUBZE: return OPVCC(31,200,0,0); 947 case ASUBZECC: return OPVCC(31,200,0,1); 948 case ASUBZEV: return OPVCC(31,200,1,0); 949 case ASUBZEVCC: return OPVCC(31,200,1,1); 950 951 case ASYNC: return OPVCC(31,598,0,0); 952 case ATLBIE: return OPVCC(31,306,0,0); 953 case ATW: return OPVCC(31,4,0,0); 954 955 case AXOR: return OPVCC(31,316,0,0); 956 } 957 diag("bad r/r opcode %A", a); 958 return 0; 959 } 960 961 long 962 opirr(int a) 963 { 964 switch(a) { 965 case AADD: return OPVCC(14,0,0,0); 966 case AADDC: return OPVCC(12,0,0,0); 967 case AADDCCC: return OPVCC(13,0,0,0); 968 case AADD+AEND: return OPVCC(15,0,0,0); /* ADDIS/CAU */ 969 970 case AANDCC: return OPVCC(28,0,0,0); 971 case AANDCC+AEND: return OPVCC(29,0,0,0); /* ANDIS./ANDIU. */ 972 973 case ABR: return OPVCC(18,0,0,0); 974 case ABL: return OPVCC(18,0,0,0) | 1; 975 case ABC: return OPVCC(16,0,0,0); 976 case ABCL: return OPVCC(16,0,0,0) | 1; 977 978 case ABEQ: return AOP_RRR(16<<26,12,2,0); 979 case ABGE: return AOP_RRR(16<<26,4,0,0); 980 case ABGT: return AOP_RRR(16<<26,12,1,0); 981 case ABLE: return AOP_RRR(16<<26,4,1,0); 982 case ABLT: return AOP_RRR(16<<26,12,0,0); 983 case ABNE: return AOP_RRR(16<<26,4,2,0); 984 case ABVC: return AOP_RRR(16<<26,4,3,0); 985 case ABVS: return AOP_RRR(16<<26,12,3,0); 986 987 case ACMP: return OPVCC(11,0,0,0); 988 case ACMPU: return OPVCC(10,0,0,0); 989 case ALSW: return OPVCC(31,597,0,0); 990 991 case AMULLW: return OPVCC(7,0,0,0); 992 993 case AOR: return OPVCC(24,0,0,0); 994 case AOR+AEND: return OPVCC(25,0,0,0); /* ORIS/ORIU */ 995 996 case ARLWMI: return OPVCC(20,0,0,0); /* rlwimi */ 997 case ARLWMICC: return OPVCC(20,0,0,1); 998 999 case ARLWNM: return OPVCC(21,0,0,0); /* rlwinm */ 1000 case ARLWNMCC: return OPVCC(21,0,0,1); 1001 1002 case ASRAW: return OPVCC(31,824,0,0); 1003 case ASRAWCC: return OPVCC(31,824,0,1); 1004 1005 case ASTSW: return OPVCC(31,725,0,0); 1006 1007 case ASUBC: return OPVCC(8,0,0,0); 1008 1009 case ATW: return OPVCC(3,0,0,0); 1010 1011 case AXOR: return OPVCC(26,0,0,0); /* XORIL */ 1012 case AXOR+AEND: return OPVCC(27,0,0,0); /* XORIU */ 1013 } 1014 diag("bad opcode i/r %A", a); 1015 return 0; 1016 } 1017 1018 /* 1019 * load o(a),d 1020 */ 1021 long 1022 opload(int a) 1023 { 1024 switch(a) { 1025 case AMOVW: return OPVCC(32,0,0,0); /* lwz */ 1026 case AMOVWU: return OPVCC(33,0,0,0); /* lwzu */ 1027 case AMOVB: 1028 case AMOVBZ: return OPVCC(34,0,0,0); /* load */ 1029 case AMOVBU: 1030 case AMOVBZU: return OPVCC(35,0,0,0); 1031 case AFMOVD: return OPVCC(50,0,0,0); 1032 case AFMOVDU: return OPVCC(51,0,0,0); 1033 case AFMOVS: return OPVCC(48,0,0,0); 1034 case AFMOVSU: return OPVCC(49,0,0,0); 1035 case AMOVH: return OPVCC(42,0,0,0); 1036 case AMOVHU: return OPVCC(43,0,0,0); 1037 case AMOVHZ: return OPVCC(40,0,0,0); 1038 case AMOVHZU: return OPVCC(41,0,0,0); 1039 case AMOVMW: return OPVCC(46,0,0,0); /* lmw */ 1040 } 1041 diag("bad load opcode %A", a); 1042 return 0; 1043 } 1044 1045 /* 1046 * indexed load a(b),d 1047 */ 1048 long 1049 oploadx(int a) 1050 { 1051 switch(a) { 1052 case AMOVW: return OPVCC(31,23,0,0); /* lwzx */ 1053 case AMOVWU: return OPVCC(31,55,0,0); /* lwzux */ 1054 case AMOVB: 1055 case AMOVBZ: return OPVCC(31,87,0,0); /* lbzx */ 1056 case AMOVBU: 1057 case AMOVBZU: return OPVCC(31,119,0,0); /* lbzux */ 1058 case AFMOVD: return OPVCC(31,599,0,0); /* lfdx */ 1059 case AFMOVDU: return OPVCC(31,631,0,0); /* lfdux */ 1060 case AFMOVS: return OPVCC(31,535,0,0); /* lfsx */ 1061 case AFMOVSU: return OPVCC(31,567,0,0); /* lfsux */ 1062 case AMOVH: return OPVCC(31,343,0,0); /* lhax */ 1063 case AMOVHU: return OPVCC(31,375,0,0); /* lhaux */ 1064 case AMOVHBR: return OPVCC(31,790,0,0); /* lhbrx */ 1065 case AMOVWBR: return OPVCC(31,534,0,0); /* lwbrx */ 1066 case AMOVHZ: return OPVCC(31,279,0,0); /* lhzx */ 1067 case AMOVHZU: return OPVCC(31,311,0,0); /* lhzux */ 1068 case AECIWX: return OPVCC(31,310,0,0); /* eciwx */ 1069 case ALWAR: return OPVCC(31,20,0,0); /* lwarx */ 1070 case ALSW: return OPVCC(31,533,0,0); /* lswx */ 1071 } 1072 diag("bad loadx opcode %A", a); 1073 return 0; 1074 } 1075 1076 /* 1077 * store s,o(d) 1078 */ 1079 long 1080 opstore(int a) 1081 { 1082 switch(a) { 1083 case AMOVB: 1084 case AMOVBZ: return OPVCC(38,0,0,0); /* stb */ 1085 case AMOVBU: 1086 case AMOVBZU: return OPVCC(39,0,0,0); /* stbu */ 1087 case AFMOVD: return OPVCC(54,0,0,0); /* stfd */ 1088 case AFMOVDU: return OPVCC(55,0,0,0); /* stfdu */ 1089 case AFMOVS: return OPVCC(52,0,0,0); /* stfs */ 1090 case AFMOVSU: return OPVCC(53,0,0,0); /* stfsu */ 1091 case AMOVHZ: 1092 case AMOVH: return OPVCC(44,0,0,0); /* sth */ 1093 case AMOVHZU: 1094 case AMOVHU: return OPVCC(45,0,0,0); /* sthu */ 1095 case AMOVMW: return OPVCC(47,0,0,0); /* stmw */ 1096 case ASTSW: return OPVCC(31,725,0,0); /* stswi */ 1097 case AMOVW: return OPVCC(36,0,0,0); /* stw */ 1098 case AMOVWU: return OPVCC(37,0,0,0); /* stwu */ 1099 } 1100 diag("unknown store opcode %A", a); 1101 return 0; 1102 } 1103 1104 /* 1105 * indexed store s,a(b) 1106 */ 1107 long 1108 opstorex(int a) 1109 { 1110 switch(a) { 1111 case AMOVB: 1112 case AMOVBZ: return OPVCC(31,215,0,0); /* stbx */ 1113 case AMOVBU: 1114 case AMOVBZU: return OPVCC(31,247,0,0); /* stbux */ 1115 case AFMOVD: return OPVCC(31,727,0,0); /* stfdx */ 1116 case AFMOVDU: return OPVCC(31,759,0,0); /* stfdux */ 1117 case AFMOVS: return OPVCC(31,663,0,0); /* stfsx */ 1118 case AFMOVSU: return OPVCC(31,695,0,0); /* stfsux */ 1119 case AMOVHZ: 1120 case AMOVH: return OPVCC(31,407,0,0); /* sthx */ 1121 case AMOVHBR: return OPVCC(31,918,0,0); /* sthbrx */ 1122 case AMOVHZU: 1123 case AMOVHU: return OPVCC(31,439,0,0); /* sthux */ 1124 case AMOVW: return OPVCC(31,151,0,0); /* stwx */ 1125 case AMOVWU: return OPVCC(31,183,0,0); /* stwux */ 1126 case ASTSW: return OPVCC(31,661,0,0); /* stswx */ 1127 case AMOVWBR: return OPVCC(31,662,0,0); /* stwbrx */ 1128 case ASTWCCC: return OPVCC(31,150,0,1); /* stwcx. */ 1129 case AECOWX: return OPVCC(31,438,0,0); /* ecowx */ 1130 } 1131 diag("unknown storex opcode %A", a); 1132 return 0; 1133 } 1134