1*7d9195a7SDavid du Colombierunits 2*7d9195a7SDavid du Colombier branch 3*7d9195a7SDavid du Colombier integer 4*7d9195a7SDavid du Colombier floating point 5*7d9195a7SDavid du Colombieron 601 6*7d9195a7SDavid du Colombier issue at most one per unit per cycle 7*7d9195a7SDavid du Colombier eight entry instruction queue 8*7d9195a7SDavid du Colombier can fill queue from cache in one clock cycle 9*7d9195a7SDavid du Colombier loads from requested address to end of cache block 10*7d9195a7SDavid du Colombierpipeline 11*7d9195a7SDavid du Colombier prefetch 12*7d9195a7SDavid du Colombier includes ins. cache access cycles 13*7d9195a7SDavid du Colombier decode 14*7d9195a7SDavid du Colombier execute 15*7d9195a7SDavid du Colombier writeback 16*7d9195a7SDavid du Colombier 17*7d9195a7SDavid du Colombierfpu 18*7d9195a7SDavid du Colombier IQ[3210] → fpu buffer/decode [≥1 cycle] → execute 1 → execute 2 → writeback 19*7d9195a7SDavid du Colombieriu 20*7d9195a7SDavid du Colombier IQ0/decode → buffer [if exec busy] → execute [hold for dependency] → 21*7d9195a7SDavid du Colombier circulate in load/store 22*7d9195a7SDavid du Colombier writeback 23*7d9195a7SDavid du Colombierbpu 24*7d9195a7SDavid du Colombier IQ[3210] → decode/execute → writeback 25*7d9195a7SDavid du Colombier 26*7d9195a7SDavid du Colombiernotes 27*7d9195a7SDavid du Colombier address calculation must complete before stored value enters write buffer 28