1*9ef1f84bSDavid du Colombier /* 2*9ef1f84bSDavid du Colombier * There are 2 flavours of APIC, Local APIC and IOAPIC, 3*9ef1f84bSDavid du Colombier * which don't necessarily share one APIC ID space. 4*9ef1f84bSDavid du Colombier * Each IOAPIC has a unique address, Local APICs are all 5*9ef1f84bSDavid du Colombier * at the same address as they can only be accessed by 6*9ef1f84bSDavid du Colombier * the local CPU. 7*9ef1f84bSDavid du Colombier To do: probably split this into 2 structs, Apic and IOApic; 8*9ef1f84bSDavid du Colombier x2APIC... 9*9ef1f84bSDavid du Colombier */ 10*9ef1f84bSDavid du Colombier typedef struct { 11*9ef1f84bSDavid du Colombier int useable; /* en */ 12*9ef1f84bSDavid du Colombier 13*9ef1f84bSDavid du Colombier Lock; /* IOAPIC: register access */ 14*9ef1f84bSDavid du Colombier u32int* addr; /* IOAPIC: register base */ 15*9ef1f84bSDavid du Colombier int nrdt; /* IOAPIC: size of RDT */ 16*9ef1f84bSDavid du Colombier int gsib; /* IOAPIC: global RDT index */ 17*9ef1f84bSDavid du Colombier 18*9ef1f84bSDavid du Colombier int machno; /* APIC */ 19*9ef1f84bSDavid du Colombier u32int lvt[10]; 20*9ef1f84bSDavid du Colombier int nlvt; 21*9ef1f84bSDavid du Colombier int ver; /* unused */ 22*9ef1f84bSDavid du Colombier 23*9ef1f84bSDavid du Colombier vlong hz; /* APIC Timer frequency */ 24*9ef1f84bSDavid du Colombier vlong max; 25*9ef1f84bSDavid du Colombier vlong min; 26*9ef1f84bSDavid du Colombier vlong div; 27*9ef1f84bSDavid du Colombier } Apic; 28*9ef1f84bSDavid du Colombier 29*9ef1f84bSDavid du Colombier enum { 30*9ef1f84bSDavid du Colombier Nbus = 256, 31*9ef1f84bSDavid du Colombier Napic = 254, /* xAPIC architectural limit */ 32*9ef1f84bSDavid du Colombier Nrdt = 64, 33*9ef1f84bSDavid du Colombier }; 34*9ef1f84bSDavid du Colombier 35*9ef1f84bSDavid du Colombier /* 36*9ef1f84bSDavid du Colombier * Common bits for 37*9ef1f84bSDavid du Colombier * IOAPIC Redirection Table Entry (RDT); 38*9ef1f84bSDavid du Colombier * APIC Local Vector Table Entry (LVT); 39*9ef1f84bSDavid du Colombier * APIC Interrupt Command Register (ICR). 40*9ef1f84bSDavid du Colombier * [10:8] Message Type 41*9ef1f84bSDavid du Colombier * [11] Destination Mode (RW) 42*9ef1f84bSDavid du Colombier * [12] Delivery Status (RO) 43*9ef1f84bSDavid du Colombier * [13] Interrupt Input Pin Polarity (RW) 44*9ef1f84bSDavid du Colombier * [14] Remote IRR (RO) 45*9ef1f84bSDavid du Colombier * [15] Trigger Mode (RW) 46*9ef1f84bSDavid du Colombier * [16] Interrupt Mask 47*9ef1f84bSDavid du Colombier */ 48*9ef1f84bSDavid du Colombier enum { 49*9ef1f84bSDavid du Colombier MTf = 0x00000000, /* Fixed */ 50*9ef1f84bSDavid du Colombier MTlp = 0x00000100, /* Lowest Priority */ 51*9ef1f84bSDavid du Colombier MTsmi = 0x00000200, /* SMI */ 52*9ef1f84bSDavid du Colombier MTrr = 0x00000300, /* Remote Read */ 53*9ef1f84bSDavid du Colombier MTnmi = 0x00000400, /* NMI */ 54*9ef1f84bSDavid du Colombier MTir = 0x00000500, /* INIT/RESET */ 55*9ef1f84bSDavid du Colombier MTsipi = 0x00000600, /* Startup IPI */ 56*9ef1f84bSDavid du Colombier MTei = 0x00000700, /* ExtINT */ 57*9ef1f84bSDavid du Colombier 58*9ef1f84bSDavid du Colombier Pm = 0x00000000, /* Physical Mode */ 59*9ef1f84bSDavid du Colombier Lm = 0x00000800, /* Logical Mode */ 60*9ef1f84bSDavid du Colombier 61*9ef1f84bSDavid du Colombier Ds = 0x00001000, /* Delivery Status */ 62*9ef1f84bSDavid du Colombier IPhigh = 0x00000000, /* IIPP High */ 63*9ef1f84bSDavid du Colombier IPlow = 0x00002000, /* IIPP Low */ 64*9ef1f84bSDavid du Colombier Rirr = 0x00004000, /* Remote IRR Status */ 65*9ef1f84bSDavid du Colombier TMedge = 0x00000000, /* Trigger Mode Edge */ 66*9ef1f84bSDavid du Colombier TMlevel = 0x00008000, /* Trigger Mode Level */ 67*9ef1f84bSDavid du Colombier Im = 0x00010000, /* Interrupt Mask */ 68*9ef1f84bSDavid du Colombier }; 69*9ef1f84bSDavid du Colombier 70*9ef1f84bSDavid du Colombier Apic xapic[Napic]; 71*9ef1f84bSDavid du Colombier Apic ioapic[Napic]; 72*9ef1f84bSDavid du Colombier 73*9ef1f84bSDavid du Colombier #define l16get(p) (((p)[1]<<8)|(p)[0]) 74*9ef1f84bSDavid du Colombier #define l32get(p) (((u32int)l16get(p+2)<<16)|l16get(p)) 75*9ef1f84bSDavid du Colombier #define l64get(p) (((u64int)l32get(p+4)<<32)|l32get(p)) 76*9ef1f84bSDavid du Colombier 77*9ef1f84bSDavid du Colombier extern void apicdump(void); 78*9ef1f84bSDavid du Colombier extern void ioapicdump(void); 79