1 /* 2 * Intel 8254[340]NN Gigabit Ethernet Controller 3 * as found on the Intel PRO/1000 series of adapters: 4 * 82543GC Intel PRO/1000 T 5 * 82544EI Intel PRO/1000 XT 6 * 82540EM Intel PRO/1000 MT 7 * 82541[GP]I 8 * 82547GI 9 * 82546GB 10 * 82546EB 11 * To Do: 12 * finish autonegotiation code; 13 * integrate fiber stuff back in (this ONLY handles 14 * the CAT5 cards at the moment); 15 * add checksum-offload; 16 * add tuning control via ctl file; 17 * this driver is little-endian specific. 18 */ 19 #include "u.h" 20 #include "../port/lib.h" 21 #include "mem.h" 22 #include "dat.h" 23 #include "fns.h" 24 #include "io.h" 25 #include "../port/error.h" 26 #include "../port/netif.h" 27 28 #include "etherif.h" 29 #include "ethermii.h" 30 31 enum { 32 i82542 = (0x1000<<16)|0x8086, 33 i82543gc = (0x1004<<16)|0x8086, 34 i82544ei = (0x1008<<16)|0x8086, 35 i82547ei = (0x1019<<16)|0x8086, 36 i82540em = (0x100E<<16)|0x8086, 37 i82540eplp = (0x101E<<16)|0x8086, 38 i82545gmc = (0x1026<<16)|0x8086, 39 i82547gi = (0x1075<<16)|0x8086, 40 i82541gi = (0x1076<<16)|0x8086, 41 i82541gi2 = (0x1077<<16)|0x8086, 42 i82546gb = (0x1079<<16)|0x8086, 43 i82541pi = (0x107c<<16)|0x8086, 44 i82546eb = (0x1010<<16)|0x8086, 45 }; 46 47 enum { 48 Ctrl = 0x00000000, /* Device Control */ 49 Ctrldup = 0x00000004, /* Device Control Duplicate */ 50 Status = 0x00000008, /* Device Status */ 51 Eecd = 0x00000010, /* EEPROM/Flash Control/Data */ 52 Ctrlext = 0x00000018, /* Extended Device Control */ 53 Mdic = 0x00000020, /* MDI Control */ 54 Fcal = 0x00000028, /* Flow Control Address Low */ 55 Fcah = 0x0000002C, /* Flow Control Address High */ 56 Fct = 0x00000030, /* Flow Control Type */ 57 Icr = 0x000000C0, /* Interrupt Cause Read */ 58 Ics = 0x000000C8, /* Interrupt Cause Set */ 59 Ims = 0x000000D0, /* Interrupt Mask Set/Read */ 60 Imc = 0x000000D8, /* Interrupt mask Clear */ 61 Rctl = 0x00000100, /* Receive Control */ 62 Fcttv = 0x00000170, /* Flow Control Transmit Timer Value */ 63 Txcw = 0x00000178, /* Transmit Configuration Word */ 64 Rxcw = 0x00000180, /* Receive Configuration Word */ 65 Tctl = 0x00000400, /* Transmit Control */ 66 Tipg = 0x00000410, /* Transmit IPG */ 67 Tbt = 0x00000448, /* Transmit Burst Timer */ 68 Ait = 0x00000458, /* Adaptive IFS Throttle */ 69 Fcrtl = 0x00002160, /* Flow Control RX Threshold Low */ 70 Fcrth = 0x00002168, /* Flow Control Rx Threshold High */ 71 Rdfh = 0x00002410, /* Receive data fifo head */ 72 Rdft = 0x00002418, /* Receive data fifo tail */ 73 Rdfhs = 0x00002420, /* Receive data fifo head saved */ 74 Rdfts = 0x00002428, /* Receive data fifo tail saved */ 75 Rdfpc = 0x00002430, /* Receive data fifo packet count */ 76 Rdbal = 0x00002800, /* Rd Base Address Low */ 77 Rdbah = 0x00002804, /* Rd Base Address High */ 78 Rdlen = 0x00002808, /* Receive Descriptor Length */ 79 Rdh = 0x00002810, /* Receive Descriptor Head */ 80 Rdt = 0x00002818, /* Receive Descriptor Tail */ 81 Rdtr = 0x00002820, /* Receive Descriptor Timer Ring */ 82 Rxdctl = 0x00002828, /* Receive Descriptor Control */ 83 Radv = 0x0000282C, /* Receive Interrupt Absolute Delay Timer */ 84 Txdmac = 0x00003000, /* Transfer DMA Control */ 85 Ett = 0x00003008, /* Early Transmit Control */ 86 Tdfh = 0x00003410, /* Transmit data fifo head */ 87 Tdft = 0x00003418, /* Transmit data fifo tail */ 88 Tdfhs = 0x00003420, /* Transmit data Fifo Head saved */ 89 Tdfts = 0x00003428, /* Transmit data fifo tail saved */ 90 Tdfpc = 0x00003430, /* Trasnmit data Fifo packet count */ 91 Tdbal = 0x00003800, /* Td Base Address Low */ 92 Tdbah = 0x00003804, /* Td Base Address High */ 93 Tdlen = 0x00003808, /* Transmit Descriptor Length */ 94 Tdh = 0x00003810, /* Transmit Descriptor Head */ 95 Tdt = 0x00003818, /* Transmit Descriptor Tail */ 96 Tidv = 0x00003820, /* Transmit Interrupt Delay Value */ 97 Txdctl = 0x00003828, /* Transmit Descriptor Control */ 98 Tadv = 0x0000382C, /* Transmit Interrupt Absolute Delay Timer */ 99 100 Statistics = 0x00004000, /* Start of Statistics Area */ 101 Gorcl = 0x88/4, /* Good Octets Received Count */ 102 Gotcl = 0x90/4, /* Good Octets Transmitted Count */ 103 Torl = 0xC0/4, /* Total Octets Received */ 104 Totl = 0xC8/4, /* Total Octets Transmitted */ 105 Nstatistics = 64, 106 107 Rxcsum = 0x00005000, /* Receive Checksum Control */ 108 Mta = 0x00005200, /* Multicast Table Array */ 109 Ral = 0x00005400, /* Receive Address Low */ 110 Rah = 0x00005404, /* Receive Address High */ 111 Manc = 0x00005820, /* Management Control */ 112 }; 113 114 enum { /* Ctrl */ 115 Bem = 0x00000002, /* Big Endian Mode */ 116 Prior = 0x00000004, /* Priority on the PCI bus */ 117 Lrst = 0x00000008, /* Link Reset */ 118 Asde = 0x00000020, /* Auto-Speed Detection Enable */ 119 Slu = 0x00000040, /* Set Link Up */ 120 Ilos = 0x00000080, /* Invert Loss of Signal (LOS) */ 121 SspeedMASK = 0x00000300, /* Speed Selection */ 122 SspeedSHIFT = 8, 123 Sspeed10 = 0x00000000, /* 10Mb/s */ 124 Sspeed100 = 0x00000100, /* 100Mb/s */ 125 Sspeed1000 = 0x00000200, /* 1000Mb/s */ 126 Frcspd = 0x00000800, /* Force Speed */ 127 Frcdplx = 0x00001000, /* Force Duplex */ 128 SwdpinsloMASK = 0x003C0000, /* Software Defined Pins - lo nibble */ 129 SwdpinsloSHIFT = 18, 130 SwdpioloMASK = 0x03C00000, /* Software Defined Pins - I or O */ 131 SwdpioloSHIFT = 22, 132 Devrst = 0x04000000, /* Device Reset */ 133 Rfce = 0x08000000, /* Receive Flow Control Enable */ 134 Tfce = 0x10000000, /* Transmit Flow Control Enable */ 135 Vme = 0x40000000, /* VLAN Mode Enable */ 136 }; 137 138 enum { /* Status */ 139 Lu = 0x00000002, /* Link Up */ 140 Tckok = 0x00000004, /* Transmit clock is running */ 141 Rbcok = 0x00000008, /* Receive clock is running */ 142 Txoff = 0x00000010, /* Transmission Paused */ 143 Tbimode = 0x00000020, /* TBI Mode Indication */ 144 LspeedMASK = 0x000000C0, /* Link Speed Setting */ 145 LspeedSHIFT = 6, 146 Lspeed10 = 0x00000000, /* 10Mb/s */ 147 Lspeed100 = 0x00000040, /* 100Mb/s */ 148 Lspeed1000 = 0x00000080, /* 1000Mb/s */ 149 Mtxckok = 0x00000400, /* MTX clock is running */ 150 Pci66 = 0x00000800, /* PCI Bus speed indication */ 151 Bus64 = 0x00001000, /* PCI Bus width indication */ 152 Pcixmode = 0x00002000, /* PCI-X mode */ 153 PcixspeedMASK = 0x0000C000, /* PCI-X bus speed */ 154 PcixspeedSHIFT = 14, 155 Pcix66 = 0x00000000, /* 50-66MHz */ 156 Pcix100 = 0x00004000, /* 66-100MHz */ 157 Pcix133 = 0x00008000, /* 100-133MHz */ 158 }; 159 160 enum { /* Ctrl and Status */ 161 Fd = 0x00000001, /* Full-Duplex */ 162 AsdvMASK = 0x00000300, 163 AsdvSHIFT = 8, 164 Asdv10 = 0x00000000, /* 10Mb/s */ 165 Asdv100 = 0x00000100, /* 100Mb/s */ 166 Asdv1000 = 0x00000200, /* 1000Mb/s */ 167 }; 168 169 enum { /* Eecd */ 170 Sk = 0x00000001, /* Clock input to the EEPROM */ 171 Cs = 0x00000002, /* Chip Select */ 172 Di = 0x00000004, /* Data Input to the EEPROM */ 173 Do = 0x00000008, /* Data Output from the EEPROM */ 174 Areq = 0x00000040, /* EEPROM Access Request */ 175 Agnt = 0x00000080, /* EEPROM Access Grant */ 176 Eepresent = 0x00000100, /* EEPROM Present */ 177 Eesz256 = 0x00000200, /* EEPROM is 256 words not 64 */ 178 Eeszaddr = 0x00000400, /* EEPROM size for 8254[17] */ 179 Spi = 0x00002000, /* EEPROM is SPI not Microwire */ 180 }; 181 182 enum { /* Ctrlext */ 183 Gpien = 0x0000000F, /* General Purpose Interrupt Enables */ 184 SwdpinshiMASK = 0x000000F0, /* Software Defined Pins - hi nibble */ 185 SwdpinshiSHIFT = 4, 186 SwdpiohiMASK = 0x00000F00, /* Software Defined Pins - I or O */ 187 SwdpiohiSHIFT = 8, 188 Asdchk = 0x00001000, /* ASD Check */ 189 Eerst = 0x00002000, /* EEPROM Reset */ 190 Ips = 0x00004000, /* Invert Power State */ 191 Spdbyps = 0x00008000, /* Speed Select Bypass */ 192 }; 193 194 enum { /* EEPROM content offsets */ 195 Ea = 0x00, /* Ethernet Address */ 196 Cf = 0x03, /* Compatibility Field */ 197 Pba = 0x08, /* Printed Board Assembly number */ 198 Icw1 = 0x0A, /* Initialization Control Word 1 */ 199 Sid = 0x0B, /* Subsystem ID */ 200 Svid = 0x0C, /* Subsystem Vendor ID */ 201 Did = 0x0D, /* Device ID */ 202 Vid = 0x0E, /* Vendor ID */ 203 Icw2 = 0x0F, /* Initialization Control Word 2 */ 204 }; 205 206 enum { /* Mdic */ 207 MDIdMASK = 0x0000FFFF, /* Data */ 208 MDIdSHIFT = 0, 209 MDIrMASK = 0x001F0000, /* PHY Register Address */ 210 MDIrSHIFT = 16, 211 MDIpMASK = 0x03E00000, /* PHY Address */ 212 MDIpSHIFT = 21, 213 MDIwop = 0x04000000, /* Write Operation */ 214 MDIrop = 0x08000000, /* Read Operation */ 215 MDIready = 0x10000000, /* End of Transaction */ 216 MDIie = 0x20000000, /* Interrupt Enable */ 217 MDIe = 0x40000000, /* Error */ 218 }; 219 220 enum { /* Icr, Ics, Ims, Imc */ 221 Txdw = 0x00000001, /* Transmit Descriptor Written Back */ 222 Txqe = 0x00000002, /* Transmit Queue Empty */ 223 Lsc = 0x00000004, /* Link Status Change */ 224 Rxseq = 0x00000008, /* Receive Sequence Error */ 225 Rxdmt0 = 0x00000010, /* Rd Minimum Threshold Reached */ 226 Rxo = 0x00000040, /* Receiver Overrun */ 227 Rxt0 = 0x00000080, /* Receiver Timer Interrupt */ 228 Mdac = 0x00000200, /* MDIO Access Completed */ 229 Rxcfg = 0x00000400, /* Receiving /C/ ordered sets */ 230 Gpi0 = 0x00000800, /* General Purpose Interrupts */ 231 Gpi1 = 0x00001000, 232 Gpi2 = 0x00002000, 233 Gpi3 = 0x00004000, 234 }; 235 236 /* 237 * The Mdic register isn't implemented on the 82543GC, 238 * the software defined pins are used instead. 239 * These definitions work for the Intel PRO/1000 T Server Adapter. 240 * The direction pin bits are read from the EEPROM. 241 */ 242 enum { 243 Mdd = ((1<<2)<<SwdpinsloSHIFT), /* data */ 244 Mddo = ((1<<2)<<SwdpioloSHIFT), /* pin direction */ 245 Mdc = ((1<<3)<<SwdpinsloSHIFT), /* clock */ 246 Mdco = ((1<<3)<<SwdpioloSHIFT), /* pin direction */ 247 Mdr = ((1<<0)<<SwdpinshiSHIFT), /* reset */ 248 Mdro = ((1<<0)<<SwdpiohiSHIFT), /* pin direction */ 249 }; 250 251 enum { /* Txcw */ 252 TxcwFd = 0x00000020, /* Full Duplex */ 253 TxcwHd = 0x00000040, /* Half Duplex */ 254 TxcwPauseMASK = 0x00000180, /* Pause */ 255 TxcwPauseSHIFT = 7, 256 TxcwPs = (1<<TxcwPauseSHIFT), /* Pause Supported */ 257 TxcwAs = (2<<TxcwPauseSHIFT), /* Asymmetric FC desired */ 258 TxcwRfiMASK = 0x00003000, /* Remote Fault Indication */ 259 TxcwRfiSHIFT = 12, 260 TxcwNpr = 0x00008000, /* Next Page Request */ 261 TxcwConfig = 0x40000000, /* Transmit COnfig Control */ 262 TxcwAne = 0x80000000, /* Auto-Negotiation Enable */ 263 }; 264 265 enum { /* Rxcw */ 266 Rxword = 0x0000FFFF, /* Data from auto-negotiation process */ 267 Rxnocarrier = 0x04000000, /* Carrier Sense indication */ 268 Rxinvalid = 0x08000000, /* Invalid Symbol during configuration */ 269 Rxchange = 0x10000000, /* Change to the Rxword indication */ 270 Rxconfig = 0x20000000, /* /C/ order set reception indication */ 271 Rxsync = 0x40000000, /* Lost bit synchronization indication */ 272 Anc = 0x80000000, /* Auto Negotiation Complete */ 273 }; 274 275 enum { /* Rctl */ 276 Rrst = 0x00000001, /* Receiver Software Reset */ 277 Ren = 0x00000002, /* Receiver Enable */ 278 Sbp = 0x00000004, /* Store Bad Packets */ 279 Upe = 0x00000008, /* Unicast Promiscuous Enable */ 280 Mpe = 0x00000010, /* Multicast Promiscuous Enable */ 281 Lpe = 0x00000020, /* Long Packet Reception Enable */ 282 LbmMASK = 0x000000C0, /* Loopback Mode */ 283 LbmOFF = 0x00000000, /* No Loopback */ 284 LbmTBI = 0x00000040, /* TBI Loopback */ 285 LbmMII = 0x00000080, /* GMII/MII Loopback */ 286 LbmXCVR = 0x000000C0, /* Transceiver Loopback */ 287 RdtmsMASK = 0x00000300, /* Rd Minimum Threshold Size */ 288 RdtmsHALF = 0x00000000, /* Threshold is 1/2 Rdlen */ 289 RdtmsQUARTER = 0x00000100, /* Threshold is 1/4 Rdlen */ 290 RdtmsEIGHTH = 0x00000200, /* Threshold is 1/8 Rdlen */ 291 MoMASK = 0x00003000, /* Multicast Offset */ 292 Mo47b36 = 0x00000000, /* bits [47:36] of received address */ 293 Mo46b35 = 0x00001000, /* bits [46:35] of received address */ 294 Mo45b34 = 0x00002000, /* bits [45:34] of received address */ 295 Mo43b32 = 0x00003000, /* bits [43:32] of received address */ 296 Bam = 0x00008000, /* Broadcast Accept Mode */ 297 BsizeMASK = 0x00030000, /* Receive Buffer Size */ 298 Bsize2048 = 0x00000000, /* Bsex = 0 */ 299 Bsize1024 = 0x00010000, /* Bsex = 0 */ 300 Bsize512 = 0x00020000, /* Bsex = 0 */ 301 Bsize256 = 0x00030000, /* Bsex = 0 */ 302 Bsize16384 = 0x00010000, /* Bsex = 1 */ 303 Vfe = 0x00040000, /* VLAN Filter Enable */ 304 Cfien = 0x00080000, /* Canonical Form Indicator Enable */ 305 Cfi = 0x00100000, /* Canonical Form Indicator value */ 306 Dpf = 0x00400000, /* Discard Pause Frames */ 307 Pmcf = 0x00800000, /* Pass MAC Control Frames */ 308 Bsex = 0x02000000, /* Buffer Size Extension */ 309 Secrc = 0x04000000, /* Strip CRC from incoming packet */ 310 }; 311 312 enum { /* Tctl */ 313 Trst = 0x00000001, /* Transmitter Software Reset */ 314 Ten = 0x00000002, /* Transmit Enable */ 315 Psp = 0x00000008, /* Pad Short Packets */ 316 CtMASK = 0x00000FF0, /* Collision Threshold */ 317 CtSHIFT = 4, 318 ColdMASK = 0x003FF000, /* Collision Distance */ 319 ColdSHIFT = 12, 320 Swxoff = 0x00400000, /* Sofware XOFF Transmission */ 321 Pbe = 0x00800000, /* Packet Burst Enable */ 322 Rtlc = 0x01000000, /* Re-transmit on Late Collision */ 323 Nrtu = 0x02000000, /* No Re-transmit on Underrrun */ 324 }; 325 326 enum { /* [RT]xdctl */ 327 PthreshMASK = 0x0000003F, /* Prefetch Threshold */ 328 PthreshSHIFT = 0, 329 HthreshMASK = 0x00003F00, /* Host Threshold */ 330 HthreshSHIFT = 8, 331 WthreshMASK = 0x003F0000, /* Writeback Threshold */ 332 WthreshSHIFT = 16, 333 Gran = 0x01000000, /* Granularity */ 334 LthreshMASK = 0xFE000000, /* Low Threshold */ 335 LthreshSHIFT = 25, 336 }; 337 338 enum { /* Rxcsum */ 339 PcssMASK = 0x000000FF, /* Packet Checksum Start */ 340 PcssSHIFT = 0, 341 Ipofl = 0x00000100, /* IP Checksum Off-load Enable */ 342 Tuofl = 0x00000200, /* TCP/UDP Checksum Off-load Enable */ 343 }; 344 345 enum { /* Manc */ 346 Arpen = 0x00002000, /* Enable ARP Request Filtering */ 347 }; 348 349 enum { /* Receive Delay Timer Ring */ 350 DelayMASK = 0x0000FFFF, /* delay timer in 1.024nS increments */ 351 DelaySHIFT = 0, 352 Fpd = 0x80000000, /* Flush partial Descriptor Block */ 353 }; 354 355 typedef struct Rd { /* Receive Descriptor */ 356 uint addr[2]; 357 ushort length; 358 ushort checksum; 359 uchar status; 360 uchar errors; 361 ushort special; 362 } Rd; 363 364 enum { /* Rd status */ 365 Rdd = 0x01, /* Descriptor Done */ 366 Reop = 0x02, /* End of Packet */ 367 Ixsm = 0x04, /* Ignore Checksum Indication */ 368 Vp = 0x08, /* Packet is 802.1Q (matched VET) */ 369 Tcpcs = 0x20, /* TCP Checksum Calculated on Packet */ 370 Ipcs = 0x40, /* IP Checksum Calculated on Packet */ 371 Pif = 0x80, /* Passed in-exact filter */ 372 }; 373 374 enum { /* Rd errors */ 375 Ce = 0x01, /* CRC Error or Alignment Error */ 376 Se = 0x02, /* Symbol Error */ 377 Seq = 0x04, /* Sequence Error */ 378 Cxe = 0x10, /* Carrier Extension Error */ 379 Tcpe = 0x20, /* TCP/UDP Checksum Error */ 380 Ipe = 0x40, /* IP Checksum Error */ 381 Rxe = 0x80, /* RX Data Error */ 382 }; 383 384 typedef struct Td Td; 385 struct Td { /* Transmit Descriptor */ 386 union { 387 uint addr[2]; /* Data */ 388 struct { /* Context */ 389 uchar ipcss; 390 uchar ipcso; 391 ushort ipcse; 392 uchar tucss; 393 uchar tucso; 394 ushort tucse; 395 }; 396 }; 397 uint control; 398 uint status; 399 }; 400 401 enum { /* Td control */ 402 LenMASK = 0x000FFFFF, /* Data/Packet Length Field */ 403 LenSHIFT = 0, 404 DtypeCD = 0x00000000, /* Data Type 'Context Descriptor' */ 405 DtypeDD = 0x00100000, /* Data Type 'Data Descriptor' */ 406 PtypeTCP = 0x01000000, /* TCP/UDP Packet Type (CD) */ 407 Teop = 0x01000000, /* End of Packet (DD) */ 408 PtypeIP = 0x02000000, /* IP Packet Type (CD) */ 409 Ifcs = 0x02000000, /* Insert FCS (DD) */ 410 Tse = 0x04000000, /* TCP Segmentation Enable */ 411 Rs = 0x08000000, /* Report Status */ 412 Rps = 0x10000000, /* Report Status Sent */ 413 Dext = 0x20000000, /* Descriptor Extension */ 414 Vle = 0x40000000, /* VLAN Packet Enable */ 415 Ide = 0x80000000, /* Interrupt Delay Enable */ 416 }; 417 418 enum { /* Td status */ 419 Tdd = 0x00000001, /* Descriptor Done */ 420 Ec = 0x00000002, /* Excess Collisions */ 421 Lc = 0x00000004, /* Late Collision */ 422 Tu = 0x00000008, /* Transmit Underrun */ 423 Iixsm = 0x00000100, /* Insert IP Checksum */ 424 Itxsm = 0x00000200, /* Insert TCP/UDP Checksum */ 425 HdrlenMASK = 0x0000FF00, /* Header Length (Tse) */ 426 HdrlenSHIFT = 8, 427 VlanMASK = 0x0FFF0000, /* VLAN Identifier */ 428 VlanSHIFT = 16, 429 Tcfi = 0x10000000, /* Canonical Form Indicator */ 430 PriMASK = 0xE0000000, /* User Priority */ 431 PriSHIFT = 29, 432 MssMASK = 0xFFFF0000, /* Maximum Segment Size (Tse) */ 433 MssSHIFT = 16, 434 }; 435 436 enum { 437 Nrd = 256, /* multiple of 8 */ 438 Ntd = 64, /* multiple of 8 */ 439 Nrb = 1024, /* private receive buffers per Ctlr */ 440 Rbsz = 2048, 441 }; 442 443 typedef struct Ctlr Ctlr; 444 typedef struct Ctlr { 445 int port; 446 Pcidev* pcidev; 447 Ctlr* next; 448 Ether* edev; 449 int active; 450 int started; 451 int id; 452 int cls; 453 ushort eeprom[0x40]; 454 455 QLock alock; /* attach */ 456 void* alloc; /* receive/transmit descriptors */ 457 int nrd; 458 int ntd; 459 int nrb; /* how many this Ctlr has in the pool */ 460 461 int* nic; 462 Lock imlock; 463 int im; /* interrupt mask */ 464 465 Mii* mii; 466 Rendez lrendez; 467 int lim; 468 469 int link; 470 471 QLock slock; 472 uint statistics[Nstatistics]; 473 uint lsleep; 474 uint lintr; 475 uint rsleep; 476 uint rintr; 477 uint txdw; 478 uint tintr; 479 uint ixsm; 480 uint ipcs; 481 uint tcpcs; 482 483 uchar ra[Eaddrlen]; /* receive address */ 484 ulong mta[128]; /* multicast table array */ 485 486 Rendez rrendez; 487 int rim; 488 int rdfree; 489 Rd* rdba; /* receive descriptor base address */ 490 Block** rb; /* receive buffers */ 491 int rdh; /* receive descriptor head */ 492 int rdt; /* receive descriptor tail */ 493 int rdtr; /* receive delay timer ring value */ 494 495 Lock tlock; 496 int tbusy; 497 int tdfree; 498 Td* tdba; /* transmit descriptor base address */ 499 Block** tb; /* transmit buffers */ 500 int tdh; /* transmit descriptor head */ 501 int tdt; /* transmit descriptor tail */ 502 503 int txcw; 504 int fcrtl; 505 int fcrth; 506 } Ctlr; 507 508 #define csr32r(c, r) (*((c)->nic+((r)/4))) 509 #define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v)) 510 511 static Ctlr* igbectlrhead; 512 static Ctlr* igbectlrtail; 513 514 static Lock igberblock; /* free receive Blocks */ 515 static Block* igberbpool; /* receive Blocks for all igbe controllers */ 516 517 static char* statistics[Nstatistics] = { 518 "CRC Error", 519 "Alignment Error", 520 "Symbol Error", 521 "RX Error", 522 "Missed Packets", 523 "Single Collision", 524 "Excessive Collisions", 525 "Multiple Collision", 526 "Late Collisions", 527 nil, 528 "Collision", 529 "Transmit Underrun", 530 "Defer", 531 "Transmit - No CRS", 532 "Sequence Error", 533 "Carrier Extension Error", 534 "Receive Error Length", 535 nil, 536 "XON Received", 537 "XON Transmitted", 538 "XOFF Received", 539 "XOFF Transmitted", 540 "FC Received Unsupported", 541 "Packets Received (64 Bytes)", 542 "Packets Received (65-127 Bytes)", 543 "Packets Received (128-255 Bytes)", 544 "Packets Received (256-511 Bytes)", 545 "Packets Received (512-1023 Bytes)", 546 "Packets Received (1024-1522 Bytes)", 547 "Good Packets Received", 548 "Broadcast Packets Received", 549 "Multicast Packets Received", 550 "Good Packets Transmitted", 551 nil, 552 "Good Octets Received", 553 nil, 554 "Good Octets Transmitted", 555 nil, 556 nil, 557 nil, 558 "Receive No Buffers", 559 "Receive Undersize", 560 "Receive Fragment", 561 "Receive Oversize", 562 "Receive Jabber", 563 nil, 564 nil, 565 nil, 566 "Total Octets Received", 567 nil, 568 "Total Octets Transmitted", 569 nil, 570 "Total Packets Received", 571 "Total Packets Transmitted", 572 "Packets Transmitted (64 Bytes)", 573 "Packets Transmitted (65-127 Bytes)", 574 "Packets Transmitted (128-255 Bytes)", 575 "Packets Transmitted (256-511 Bytes)", 576 "Packets Transmitted (512-1023 Bytes)", 577 "Packets Transmitted (1024-1522 Bytes)", 578 "Multicast Packets Transmitted", 579 "Broadcast Packets Transmitted", 580 "TCP Segmentation Context Transmitted", 581 "TCP Segmentation Context Fail", 582 }; 583 584 static long 585 igbeifstat(Ether* edev, void* a, long n, ulong offset) 586 { 587 Ctlr *ctlr; 588 char *p, *s; 589 int i, l, r; 590 uvlong tuvl, ruvl; 591 592 ctlr = edev->ctlr; 593 qlock(&ctlr->slock); 594 p = malloc(2*READSTR); 595 l = 0; 596 for(i = 0; i < Nstatistics; i++){ 597 r = csr32r(ctlr, Statistics+i*4); 598 if((s = statistics[i]) == nil) 599 continue; 600 switch(i){ 601 case Gorcl: 602 case Gotcl: 603 case Torl: 604 case Totl: 605 ruvl = r; 606 ruvl += ((uvlong)csr32r(ctlr, Statistics+(i+1)*4))<<32; 607 tuvl = ruvl; 608 tuvl += ctlr->statistics[i]; 609 tuvl += ((uvlong)ctlr->statistics[i+1])<<32; 610 if(tuvl == 0) 611 continue; 612 ctlr->statistics[i] = tuvl; 613 ctlr->statistics[i+1] = tuvl>>32; 614 l += snprint(p+l, 2*READSTR-l, "%s: %llud %llud\n", 615 s, tuvl, ruvl); 616 i++; 617 break; 618 619 default: 620 ctlr->statistics[i] += r; 621 if(ctlr->statistics[i] == 0) 622 continue; 623 l += snprint(p+l, 2*READSTR-l, "%s: %ud %ud\n", 624 s, ctlr->statistics[i], r); 625 break; 626 } 627 } 628 629 l += snprint(p+l, 2*READSTR-l, "lintr: %ud %ud\n", 630 ctlr->lintr, ctlr->lsleep); 631 l += snprint(p+l, 2*READSTR-l, "rintr: %ud %ud\n", 632 ctlr->rintr, ctlr->rsleep); 633 l += snprint(p+l, 2*READSTR-l, "tintr: %ud %ud\n", 634 ctlr->tintr, ctlr->txdw); 635 l += snprint(p+l, 2*READSTR-l, "ixcs: %ud %ud %ud\n", 636 ctlr->ixsm, ctlr->ipcs, ctlr->tcpcs); 637 l += snprint(p+l, 2*READSTR-l, "rdtr: %ud\n", ctlr->rdtr); 638 l += snprint(p+l, 2*READSTR-l, "Ctrlext: %08x\n", csr32r(ctlr, Ctrlext)); 639 640 l += snprint(p+l, 2*READSTR-l, "eeprom:"); 641 for(i = 0; i < 0x40; i++){ 642 if(i && ((i & 0x07) == 0)) 643 l += snprint(p+l, 2*READSTR-l, "\n "); 644 l += snprint(p+l, 2*READSTR-l, " %4.4uX", ctlr->eeprom[i]); 645 } 646 l += snprint(p+l, 2*READSTR-l, "\n"); 647 648 if(ctlr->mii != nil && ctlr->mii->curphy != nil){ 649 l += snprint(p+l, 2*READSTR, "phy: "); 650 for(i = 0; i < NMiiPhyr; i++){ 651 if(i && ((i & 0x07) == 0)) 652 l += snprint(p+l, 2*READSTR-l, "\n "); 653 r = miimir(ctlr->mii, i); 654 l += snprint(p+l, 2*READSTR-l, " %4.4uX", r); 655 } 656 snprint(p+l, 2*READSTR-l, "\n"); 657 } 658 n = readstr(offset, a, n, p); 659 free(p); 660 qunlock(&ctlr->slock); 661 662 return n; 663 } 664 665 enum { 666 CMrdtr, 667 }; 668 669 static Cmdtab igbectlmsg[] = { 670 CMrdtr, "rdtr", 2, 671 }; 672 673 static long 674 igbectl(Ether* edev, void* buf, long n) 675 { 676 int v; 677 char *p; 678 Ctlr *ctlr; 679 Cmdbuf *cb; 680 Cmdtab *ct; 681 682 if((ctlr = edev->ctlr) == nil) 683 error(Enonexist); 684 685 cb = parsecmd(buf, n); 686 if(waserror()){ 687 free(cb); 688 nexterror(); 689 } 690 691 ct = lookupcmd(cb, igbectlmsg, nelem(igbectlmsg)); 692 switch(ct->index){ 693 case CMrdtr: 694 v = strtol(cb->f[1], &p, 0); 695 if(v < 0 || p == cb->f[1] || v > 0xFFFF) 696 error(Ebadarg); 697 ctlr->rdtr = v;; 698 csr32w(ctlr, Rdtr, Fpd|v); 699 break; 700 } 701 free(cb); 702 poperror(); 703 704 return n; 705 } 706 707 static void 708 igbepromiscuous(void* arg, int on) 709 { 710 int rctl; 711 Ctlr *ctlr; 712 Ether *edev; 713 714 edev = arg; 715 ctlr = edev->ctlr; 716 717 rctl = csr32r(ctlr, Rctl); 718 rctl &= ~MoMASK; 719 rctl |= Mo47b36; 720 if(on) 721 rctl |= Upe|Mpe; 722 else 723 rctl &= ~(Upe|Mpe); 724 csr32w(ctlr, Rctl, rctl); 725 } 726 727 static void 728 igbemulticast(void* arg, uchar* addr, int on) 729 { 730 int bit, x; 731 Ctlr *ctlr; 732 Ether *edev; 733 734 edev = arg; 735 ctlr = edev->ctlr; 736 737 x = addr[5]>>1; 738 bit = ((addr[5] & 1)<<4)|(addr[4]>>4); 739 if(on) 740 ctlr->mta[x] |= 1<<bit; 741 else 742 ctlr->mta[x] &= ~(1<<bit); 743 744 csr32w(ctlr, Mta+x*4, ctlr->mta[x]); 745 } 746 747 static Block* 748 igberballoc(void) 749 { 750 Block *bp; 751 752 ilock(&igberblock); 753 if((bp = igberbpool) != nil){ 754 igberbpool = bp->next; 755 bp->next = nil; 756 } 757 iunlock(&igberblock); 758 759 return bp; 760 } 761 762 static void 763 igberbfree(Block* bp) 764 { 765 bp->rp = bp->lim - Rbsz; 766 bp->wp = bp->rp; 767 768 ilock(&igberblock); 769 bp->next = igberbpool; 770 igberbpool = bp; 771 iunlock(&igberblock); 772 } 773 774 static void 775 igbeim(Ctlr* ctlr, int im) 776 { 777 ilock(&ctlr->imlock); 778 ctlr->im |= im; 779 csr32w(ctlr, Ims, ctlr->im); 780 iunlock(&ctlr->imlock); 781 } 782 783 static int 784 igbelim(void* ctlr) 785 { 786 return ((Ctlr*)ctlr)->lim != 0; 787 } 788 789 static void 790 igbelproc(void* arg) 791 { 792 Ctlr *ctlr; 793 Ether *edev; 794 MiiPhy *phy; 795 int ctrl, r; 796 797 edev = arg; 798 ctlr = edev->ctlr; 799 for(;;){ 800 if(ctlr->mii == nil || ctlr->mii->curphy == nil) 801 continue; 802 803 /* 804 * To do: 805 * logic to manage status change, 806 * this is incomplete but should work 807 * one time to set up the hardware. 808 * 809 * MiiPhy.speed, etc. should be in Mii. 810 */ 811 if(miistatus(ctlr->mii) < 0) 812 //continue; 813 goto enable; 814 815 phy = ctlr->mii->curphy; 816 ctrl = csr32r(ctlr, Ctrl); 817 818 switch(ctlr->id){ 819 case i82543gc: 820 case i82544ei: 821 default: 822 if(!(ctrl & Asde)){ 823 ctrl &= ~(SspeedMASK|Ilos|Fd); 824 ctrl |= Frcdplx|Frcspd; 825 if(phy->speed == 1000) 826 ctrl |= Sspeed1000; 827 else if(phy->speed == 100) 828 ctrl |= Sspeed100; 829 if(phy->fd) 830 ctrl |= Fd; 831 } 832 break; 833 834 case i82540em: 835 case i82540eplp: 836 case i82547gi: 837 case i82541gi: 838 case i82541gi2: 839 case i82541pi: 840 break; 841 } 842 843 /* 844 * Collision Distance. 845 */ 846 r = csr32r(ctlr, Tctl); 847 r &= ~ColdMASK; 848 if(phy->fd) 849 r |= 64<<ColdSHIFT; 850 else 851 r |= 512<<ColdSHIFT; 852 csr32w(ctlr, Tctl, r); 853 854 /* 855 * Flow control. 856 */ 857 if(phy->rfc) 858 ctrl |= Rfce; 859 if(phy->tfc) 860 ctrl |= Tfce; 861 csr32w(ctlr, Ctrl, ctrl); 862 863 enable: 864 ctlr->lim = 0; 865 igbeim(ctlr, Lsc); 866 867 ctlr->lsleep++; 868 sleep(&ctlr->lrendez, igbelim, ctlr); 869 } 870 } 871 872 static void 873 igbetxinit(Ctlr* ctlr) 874 { 875 int i, r; 876 Block *bp; 877 878 csr32w(ctlr, Tctl, (0x0F<<CtSHIFT)|Psp|(66<<ColdSHIFT)); 879 switch(ctlr->id){ 880 default: 881 r = 6; 882 break; 883 case i82543gc: 884 case i82544ei: 885 case i82547ei: 886 case i82540em: 887 case i82540eplp: 888 case i82541gi: 889 case i82541gi2: 890 case i82541pi: 891 case i82545gmc: 892 case i82546gb: 893 case i82546eb: 894 case i82547gi: 895 r = 8; 896 break; 897 } 898 csr32w(ctlr, Tipg, (6<<20)|(8<<10)|r); 899 csr32w(ctlr, Ait, 0); 900 csr32w(ctlr, Txdmac, 0); 901 902 csr32w(ctlr, Tdbal, PCIWADDR(ctlr->tdba)); 903 csr32w(ctlr, Tdbah, 0); 904 csr32w(ctlr, Tdlen, ctlr->ntd*sizeof(Td)); 905 ctlr->tdh = PREV(0, ctlr->ntd); 906 csr32w(ctlr, Tdh, 0); 907 ctlr->tdt = 0; 908 csr32w(ctlr, Tdt, 0); 909 910 for(i = 0; i < ctlr->ntd; i++){ 911 if((bp = ctlr->tb[i]) != nil){ 912 ctlr->tb[i] = nil; 913 freeb(bp); 914 } 915 memset(&ctlr->tdba[i], 0, sizeof(Td)); 916 } 917 ctlr->tdfree = ctlr->ntd; 918 919 csr32w(ctlr, Tidv, 128); 920 r = (4<<WthreshSHIFT)|(4<<HthreshSHIFT)|(8<<PthreshSHIFT); 921 922 switch(ctlr->id){ 923 default: 924 break; 925 case i82540em: 926 case i82540eplp: 927 case i82547gi: 928 case i82545gmc: 929 case i82546gb: 930 case i82546eb: 931 case i82541gi: 932 case i82541gi2: 933 case i82541pi: 934 r = csr32r(ctlr, Txdctl); 935 r &= ~WthreshMASK; 936 r |= Gran|(4<<WthreshSHIFT); 937 938 csr32w(ctlr, Tadv, 64); 939 break; 940 } 941 942 csr32w(ctlr, Txdctl, r); 943 944 r = csr32r(ctlr, Tctl); 945 r |= Ten; 946 csr32w(ctlr, Tctl, r); 947 } 948 949 static void 950 igbetransmit(Ether* edev) 951 { 952 Td *td; 953 Block *bp; 954 Ctlr *ctlr; 955 int tdh, tdt; 956 957 ctlr = edev->ctlr; 958 959 ilock(&ctlr->tlock); 960 961 /* 962 * Free any completed packets 963 */ 964 tdh = ctlr->tdh; 965 while(NEXT(tdh, ctlr->ntd) != csr32r(ctlr, Tdh)){ 966 if((bp = ctlr->tb[tdh]) != nil){ 967 ctlr->tb[tdh] = nil; 968 freeb(bp); 969 } 970 memset(&ctlr->tdba[tdh], 0, sizeof(Td)); 971 tdh = NEXT(tdh, ctlr->ntd); 972 } 973 ctlr->tdh = tdh; 974 975 /* 976 * Try to fill the ring back up. 977 */ 978 tdt = ctlr->tdt; 979 while(NEXT(tdt, ctlr->ntd) != tdh){ 980 if((bp = qget(edev->oq)) == nil) 981 break; 982 td = &ctlr->tdba[tdt]; 983 td->addr[0] = PCIWADDR(bp->rp); 984 td->control = ((BLEN(bp) & LenMASK)<<LenSHIFT); 985 td->control |= Dext|Ifcs|Teop|DtypeDD; 986 ctlr->tb[tdt] = bp; 987 tdt = NEXT(tdt, ctlr->ntd); 988 if(NEXT(tdt, ctlr->ntd) == tdh){ 989 td->control |= Rs; 990 ctlr->txdw++; 991 ctlr->tdt = tdt; 992 csr32w(ctlr, Tdt, tdt); 993 igbeim(ctlr, Txdw); 994 break; 995 } 996 ctlr->tdt = tdt; 997 csr32w(ctlr, Tdt, tdt); 998 } 999 1000 iunlock(&ctlr->tlock); 1001 } 1002 1003 static void 1004 igbereplenish(Ctlr* ctlr) 1005 { 1006 Rd *rd; 1007 int rdt; 1008 Block *bp; 1009 1010 rdt = ctlr->rdt; 1011 while(NEXT(rdt, ctlr->nrd) != ctlr->rdh){ 1012 rd = &ctlr->rdba[rdt]; 1013 if(ctlr->rb[rdt] == nil){ 1014 bp = igberballoc(); 1015 if(bp == nil){ 1016 iprint("#l%d: igbereplenish: no available buffers\n", 1017 ctlr->edev->ctlrno); 1018 break; 1019 } 1020 ctlr->rb[rdt] = bp; 1021 rd->addr[0] = PCIWADDR(bp->rp); 1022 rd->addr[1] = 0; 1023 } 1024 coherence(); 1025 rd->status = 0; 1026 rdt = NEXT(rdt, ctlr->nrd); 1027 ctlr->rdfree++; 1028 } 1029 ctlr->rdt = rdt; 1030 csr32w(ctlr, Rdt, rdt); 1031 } 1032 1033 static void 1034 igberxinit(Ctlr* ctlr) 1035 { 1036 int i; 1037 Block *bp; 1038 1039 csr32w(ctlr, Rctl, Dpf|Bsize2048|Bam|RdtmsHALF); 1040 1041 csr32w(ctlr, Rdbal, PCIWADDR(ctlr->rdba)); 1042 csr32w(ctlr, Rdbah, 0); 1043 csr32w(ctlr, Rdlen, ctlr->nrd*sizeof(Rd)); 1044 ctlr->rdh = 0; 1045 csr32w(ctlr, Rdh, 0); 1046 ctlr->rdt = 0; 1047 csr32w(ctlr, Rdt, 0); 1048 ctlr->rdtr = 0; 1049 csr32w(ctlr, Rdtr, Fpd|0); 1050 1051 for(i = 0; i < ctlr->nrd; i++){ 1052 if((bp = ctlr->rb[i]) != nil){ 1053 ctlr->rb[i] = nil; 1054 freeb(bp); 1055 } 1056 } 1057 igbereplenish(ctlr); 1058 1059 switch(ctlr->id){ 1060 case i82540em: 1061 case i82540eplp: 1062 case i82541gi: 1063 case i82541gi2: 1064 case i82541pi: 1065 case i82545gmc: 1066 case i82546gb: 1067 case i82546eb: 1068 case i82547gi: 1069 csr32w(ctlr, Radv, 64); 1070 break; 1071 } 1072 csr32w(ctlr, Rxdctl, (8<<WthreshSHIFT)|(8<<HthreshSHIFT)|4); 1073 1074 /* 1075 * Enable checksum offload. 1076 */ 1077 csr32w(ctlr, Rxcsum, Tuofl|Ipofl|(ETHERHDRSIZE<<PcssSHIFT)); 1078 } 1079 1080 static int 1081 igberim(void* ctlr) 1082 { 1083 return ((Ctlr*)ctlr)->rim != 0; 1084 } 1085 1086 static void 1087 igberproc(void* arg) 1088 { 1089 Rd *rd; 1090 Block *bp; 1091 Ctlr *ctlr; 1092 int r, rdh; 1093 Ether *edev; 1094 1095 edev = arg; 1096 ctlr = edev->ctlr; 1097 1098 igberxinit(ctlr); 1099 r = csr32r(ctlr, Rctl); 1100 r |= Ren; 1101 csr32w(ctlr, Rctl, r); 1102 1103 for(;;){ 1104 ctlr->rim = 0; 1105 igbeim(ctlr, Rxt0|Rxo|Rxdmt0|Rxseq); 1106 ctlr->rsleep++; 1107 sleep(&ctlr->rrendez, igberim, ctlr); 1108 1109 rdh = ctlr->rdh; 1110 for(;;){ 1111 rd = &ctlr->rdba[rdh]; 1112 1113 if(!(rd->status & Rdd)) 1114 break; 1115 1116 /* 1117 * Accept eop packets with no errors. 1118 * With no errors and the Ixsm bit set, 1119 * the descriptor status Tpcs and Ipcs bits give 1120 * an indication of whether the checksums were 1121 * calculated and valid. 1122 */ 1123 if((rd->status & Reop) && rd->errors == 0){ 1124 bp = ctlr->rb[rdh]; 1125 ctlr->rb[rdh] = nil; 1126 bp->wp += rd->length; 1127 bp->next = nil; 1128 if(!(rd->status & Ixsm)){ 1129 ctlr->ixsm++; 1130 if(rd->status & Ipcs){ 1131 /* 1132 * IP checksum calculated 1133 * (and valid as errors == 0). 1134 */ 1135 ctlr->ipcs++; 1136 bp->flag |= Bipck; 1137 } 1138 if(rd->status & Tcpcs){ 1139 /* 1140 * TCP/UDP checksum calculated 1141 * (and valid as errors == 0). 1142 */ 1143 ctlr->tcpcs++; 1144 bp->flag |= Btcpck|Budpck; 1145 } 1146 bp->checksum = rd->checksum; 1147 bp->flag |= Bpktck; 1148 } 1149 etheriq(edev, bp, 1); 1150 } 1151 else if(ctlr->rb[rdh] != nil){ 1152 freeb(ctlr->rb[rdh]); 1153 ctlr->rb[rdh] = nil; 1154 } 1155 1156 memset(rd, 0, sizeof(Rd)); 1157 coherence(); 1158 ctlr->rdfree--; 1159 rdh = NEXT(rdh, ctlr->nrd); 1160 } 1161 ctlr->rdh = rdh; 1162 1163 if(ctlr->rdfree < ctlr->nrd/2 || (ctlr->rim & Rxdmt0)) 1164 igbereplenish(ctlr); 1165 } 1166 } 1167 1168 static void 1169 igbeattach(Ether* edev) 1170 { 1171 Block *bp; 1172 Ctlr *ctlr; 1173 char name[KNAMELEN]; 1174 1175 ctlr = edev->ctlr; 1176 ctlr->edev = edev; /* point back to Ether* */ 1177 qlock(&ctlr->alock); 1178 if(ctlr->alloc != nil){ 1179 qunlock(&ctlr->alock); 1180 return; 1181 } 1182 1183 ctlr->nrd = ROUND(Nrd, 8); 1184 ctlr->ntd = ROUND(Ntd, 8); 1185 ctlr->alloc = malloc(ctlr->nrd*sizeof(Rd)+ctlr->ntd*sizeof(Td) + 127); 1186 if(ctlr->alloc == nil){ 1187 qunlock(&ctlr->alock); 1188 return; 1189 } 1190 ctlr->rdba = (Rd*)ROUNDUP((uintptr)ctlr->alloc, 128); 1191 ctlr->tdba = (Td*)(ctlr->rdba+ctlr->nrd); 1192 1193 ctlr->rb = malloc(ctlr->nrd*sizeof(Block*)); 1194 ctlr->tb = malloc(ctlr->ntd*sizeof(Block*)); 1195 1196 if(waserror()){ 1197 while(ctlr->nrb > 0){ 1198 bp = igberballoc(); 1199 bp->free = nil; 1200 freeb(bp); 1201 ctlr->nrb--; 1202 } 1203 free(ctlr->tb); 1204 ctlr->tb = nil; 1205 free(ctlr->rb); 1206 ctlr->rb = nil; 1207 free(ctlr->alloc); 1208 ctlr->alloc = nil; 1209 qunlock(&ctlr->alock); 1210 nexterror(); 1211 } 1212 1213 for(ctlr->nrb = 0; ctlr->nrb < Nrb; ctlr->nrb++){ 1214 if((bp = allocb(Rbsz)) == nil) 1215 break; 1216 bp->free = igberbfree; 1217 freeb(bp); 1218 } 1219 1220 snprint(name, KNAMELEN, "#l%dlproc", edev->ctlrno); 1221 kproc(name, igbelproc, edev); 1222 1223 snprint(name, KNAMELEN, "#l%drproc", edev->ctlrno); 1224 kproc(name, igberproc, edev); 1225 1226 igbetxinit(ctlr); 1227 1228 qunlock(&ctlr->alock); 1229 poperror(); 1230 } 1231 1232 static void 1233 igbeinterrupt(Ureg*, void* arg) 1234 { 1235 Ctlr *ctlr; 1236 Ether *edev; 1237 int icr, im, txdw; 1238 1239 edev = arg; 1240 ctlr = edev->ctlr; 1241 1242 ilock(&ctlr->imlock); 1243 csr32w(ctlr, Imc, ~0); 1244 im = ctlr->im; 1245 txdw = 0; 1246 1247 while((icr = csr32r(ctlr, Icr) & ctlr->im) != 0){ 1248 if(icr & Lsc){ 1249 im &= ~Lsc; 1250 ctlr->lim = icr & Lsc; 1251 wakeup(&ctlr->lrendez); 1252 ctlr->lintr++; 1253 } 1254 if(icr & (Rxt0|Rxo|Rxdmt0|Rxseq)){ 1255 im &= ~(Rxt0|Rxo|Rxdmt0|Rxseq); 1256 ctlr->rim = icr & (Rxt0|Rxo|Rxdmt0|Rxseq); 1257 wakeup(&ctlr->rrendez); 1258 ctlr->rintr++; 1259 } 1260 if(icr & Txdw){ 1261 im &= ~Txdw; 1262 txdw++; 1263 ctlr->tintr++; 1264 } 1265 } 1266 1267 ctlr->im = im; 1268 csr32w(ctlr, Ims, im); 1269 iunlock(&ctlr->imlock); 1270 1271 if(txdw) 1272 igbetransmit(edev); 1273 } 1274 1275 static int 1276 i82543mdior(Ctlr* ctlr, int n) 1277 { 1278 int ctrl, data, i, r; 1279 1280 /* 1281 * Read n bits from the Management Data I/O Interface. 1282 */ 1283 ctrl = csr32r(ctlr, Ctrl); 1284 r = (ctrl & ~Mddo)|Mdco; 1285 data = 0; 1286 for(i = n-1; i >= 0; i--){ 1287 if(csr32r(ctlr, Ctrl) & Mdd) 1288 data |= (1<<i); 1289 csr32w(ctlr, Ctrl, Mdc|r); 1290 csr32w(ctlr, Ctrl, r); 1291 } 1292 csr32w(ctlr, Ctrl, ctrl); 1293 1294 return data; 1295 } 1296 1297 static int 1298 i82543mdiow(Ctlr* ctlr, int bits, int n) 1299 { 1300 int ctrl, i, r; 1301 1302 /* 1303 * Write n bits to the Management Data I/O Interface. 1304 */ 1305 ctrl = csr32r(ctlr, Ctrl); 1306 r = Mdco|Mddo|ctrl; 1307 for(i = n-1; i >= 0; i--){ 1308 if(bits & (1<<i)) 1309 r |= Mdd; 1310 else 1311 r &= ~Mdd; 1312 csr32w(ctlr, Ctrl, Mdc|r); 1313 csr32w(ctlr, Ctrl, r); 1314 } 1315 csr32w(ctlr, Ctrl, ctrl); 1316 1317 return 0; 1318 } 1319 1320 static int 1321 i82543miimir(Mii* mii, int pa, int ra) 1322 { 1323 int data; 1324 Ctlr *ctlr; 1325 1326 ctlr = mii->ctlr; 1327 1328 /* 1329 * MII Management Interface Read. 1330 * 1331 * Preamble; 1332 * ST+OP+PHYAD+REGAD; 1333 * TA + 16 data bits. 1334 */ 1335 i82543mdiow(ctlr, 0xFFFFFFFF, 32); 1336 i82543mdiow(ctlr, 0x1800|(pa<<5)|ra, 14); 1337 data = i82543mdior(ctlr, 18); 1338 1339 if(data & 0x10000) 1340 return -1; 1341 1342 return data & 0xFFFF; 1343 } 1344 1345 static int 1346 i82543miimiw(Mii* mii, int pa, int ra, int data) 1347 { 1348 Ctlr *ctlr; 1349 1350 ctlr = mii->ctlr; 1351 1352 /* 1353 * MII Management Interface Write. 1354 * 1355 * Preamble; 1356 * ST+OP+PHYAD+REGAD+TA + 16 data bits; 1357 * Z. 1358 */ 1359 i82543mdiow(ctlr, 0xFFFFFFFF, 32); 1360 data &= 0xFFFF; 1361 data |= (0x05<<(5+5+2+16))|(pa<<(5+2+16))|(ra<<(2+16))|(0x02<<16); 1362 i82543mdiow(ctlr, data, 32); 1363 1364 return 0; 1365 } 1366 1367 static int 1368 igbemiimir(Mii* mii, int pa, int ra) 1369 { 1370 Ctlr *ctlr; 1371 int mdic, timo; 1372 1373 ctlr = mii->ctlr; 1374 1375 csr32w(ctlr, Mdic, MDIrop|(pa<<MDIpSHIFT)|(ra<<MDIrSHIFT)); 1376 mdic = 0; 1377 for(timo = 64; timo; timo--){ 1378 mdic = csr32r(ctlr, Mdic); 1379 if(mdic & (MDIe|MDIready)) 1380 break; 1381 microdelay(1); 1382 } 1383 1384 if((mdic & (MDIe|MDIready)) == MDIready) 1385 return mdic & 0xFFFF; 1386 return -1; 1387 } 1388 1389 static int 1390 igbemiimiw(Mii* mii, int pa, int ra, int data) 1391 { 1392 Ctlr *ctlr; 1393 int mdic, timo; 1394 1395 ctlr = mii->ctlr; 1396 1397 data &= MDIdMASK; 1398 csr32w(ctlr, Mdic, MDIwop|(pa<<MDIpSHIFT)|(ra<<MDIrSHIFT)|data); 1399 mdic = 0; 1400 for(timo = 64; timo; timo--){ 1401 mdic = csr32r(ctlr, Mdic); 1402 if(mdic & (MDIe|MDIready)) 1403 break; 1404 microdelay(1); 1405 } 1406 if((mdic & (MDIe|MDIready)) == MDIready) 1407 return 0; 1408 return -1; 1409 } 1410 1411 static int 1412 igbemii(Ctlr* ctlr) 1413 { 1414 MiiPhy *phy; 1415 int ctrl, p, r; 1416 1417 r = csr32r(ctlr, Status); 1418 if(r & Tbimode) 1419 return -1; 1420 if((ctlr->mii = malloc(sizeof(Mii))) == nil) 1421 return -1; 1422 ctlr->mii->ctlr = ctlr; 1423 1424 ctrl = csr32r(ctlr, Ctrl); 1425 ctrl |= Slu; 1426 1427 switch(ctlr->id){ 1428 case i82543gc: 1429 ctrl |= Frcdplx|Frcspd; 1430 csr32w(ctlr, Ctrl, ctrl); 1431 1432 /* 1433 * The reset pin direction (Mdro) should already 1434 * be set from the EEPROM load. 1435 * If it's not set this configuration is unexpected 1436 * so bail. 1437 */ 1438 r = csr32r(ctlr, Ctrlext); 1439 if(!(r & Mdro)) 1440 return -1; 1441 csr32w(ctlr, Ctrlext, r); 1442 delay(20); 1443 r = csr32r(ctlr, Ctrlext); 1444 r &= ~Mdr; 1445 csr32w(ctlr, Ctrlext, r); 1446 delay(20); 1447 r = csr32r(ctlr, Ctrlext); 1448 r |= Mdr; 1449 csr32w(ctlr, Ctrlext, r); 1450 delay(20); 1451 1452 ctlr->mii->mir = i82543miimir; 1453 ctlr->mii->miw = i82543miimiw; 1454 break; 1455 case i82544ei: 1456 case i82547ei: 1457 case i82540em: 1458 case i82540eplp: 1459 case i82547gi: 1460 case i82541gi: 1461 case i82541gi2: 1462 case i82541pi: 1463 case i82545gmc: 1464 case i82546gb: 1465 case i82546eb: 1466 ctrl &= ~(Frcdplx|Frcspd); 1467 csr32w(ctlr, Ctrl, ctrl); 1468 ctlr->mii->mir = igbemiimir; 1469 ctlr->mii->miw = igbemiimiw; 1470 break; 1471 default: 1472 free(ctlr->mii); 1473 ctlr->mii = nil; 1474 return -1; 1475 } 1476 1477 if(mii(ctlr->mii, ~0) == 0 || (phy = ctlr->mii->curphy) == nil){ 1478 free(ctlr->mii); 1479 ctlr->mii = nil; 1480 return -1; 1481 } 1482 USED(phy); 1483 // print("oui %X phyno %d\n", phy->oui, phy->phyno); 1484 1485 /* 1486 * 8254X-specific PHY registers not in 802.3: 1487 * 0x10 PHY specific control 1488 * 0x14 extended PHY specific control 1489 * Set appropriate values then reset the PHY to have 1490 * changes noted. 1491 */ 1492 switch(ctlr->id){ 1493 case i82547gi: 1494 case i82541gi: 1495 case i82541gi2: 1496 case i82541pi: 1497 case i82545gmc: 1498 case i82546gb: 1499 case i82546eb: 1500 break; 1501 default: 1502 r = miimir(ctlr->mii, 16); 1503 r |= 0x0800; /* assert CRS on Tx */ 1504 r |= 0x0060; /* auto-crossover all speeds */ 1505 r |= 0x0002; /* polarity reversal enabled */ 1506 miimiw(ctlr->mii, 16, r); 1507 1508 r = miimir(ctlr->mii, 20); 1509 r |= 0x0070; /* +25MHz clock */ 1510 r &= ~0x0F00; 1511 r |= 0x0100; /* 1x downshift */ 1512 miimiw(ctlr->mii, 20, r); 1513 1514 miireset(ctlr->mii); 1515 p = 0; 1516 if(ctlr->txcw & TxcwPs) 1517 p |= AnaP; 1518 if(ctlr->txcw & TxcwAs) 1519 p |= AnaAP; 1520 miiane(ctlr->mii, ~0, p, ~0); 1521 break; 1522 } 1523 return 0; 1524 } 1525 1526 static int 1527 at93c46io(Ctlr* ctlr, char* op, int data) 1528 { 1529 char *lp, *p; 1530 int i, loop, eecd, r; 1531 1532 eecd = csr32r(ctlr, Eecd); 1533 1534 r = 0; 1535 loop = -1; 1536 lp = nil; 1537 for(p = op; *p != '\0'; p++){ 1538 switch(*p){ 1539 default: 1540 return -1; 1541 case ' ': 1542 continue; 1543 case ':': /* start of loop */ 1544 loop = strtol(p+1, &lp, 0)-1; 1545 lp--; 1546 if(p == lp) 1547 loop = 7; 1548 p = lp; 1549 continue; 1550 case ';': /* end of loop */ 1551 if(lp == nil) 1552 return -1; 1553 loop--; 1554 if(loop >= 0) 1555 p = lp; 1556 else 1557 lp = nil; 1558 continue; 1559 case 'C': /* assert clock */ 1560 eecd |= Sk; 1561 break; 1562 case 'c': /* deassert clock */ 1563 eecd &= ~Sk; 1564 break; 1565 case 'D': /* next bit in 'data' byte */ 1566 if(loop < 0) 1567 return -1; 1568 if(data & (1<<loop)) 1569 eecd |= Di; 1570 else 1571 eecd &= ~Di; 1572 break; 1573 case 'O': /* collect data output */ 1574 i = (csr32r(ctlr, Eecd) & Do) != 0; 1575 if(loop >= 0) 1576 r |= (i<<loop); 1577 else 1578 r = i; 1579 continue; 1580 case 'I': /* assert data input */ 1581 eecd |= Di; 1582 break; 1583 case 'i': /* deassert data input */ 1584 eecd &= ~Di; 1585 break; 1586 case 'S': /* enable chip select */ 1587 eecd |= Cs; 1588 break; 1589 case 's': /* disable chip select */ 1590 eecd &= ~Cs; 1591 break; 1592 } 1593 csr32w(ctlr, Eecd, eecd); 1594 microdelay(50); 1595 } 1596 if(loop >= 0) 1597 return -1; 1598 return r; 1599 } 1600 1601 static int 1602 at93c46r(Ctlr* ctlr) 1603 { 1604 ushort sum; 1605 char rop[20]; 1606 int addr, areq, bits, data, eecd, i; 1607 1608 eecd = csr32r(ctlr, Eecd); 1609 if(eecd & Spi){ 1610 print("igbe: SPI EEPROM access not implemented\n"); 1611 return 0; 1612 } 1613 if(eecd & (Eeszaddr|Eesz256)) 1614 bits = 8; 1615 else 1616 bits = 6; 1617 1618 sum = 0; 1619 1620 switch(ctlr->id){ 1621 default: 1622 areq = 0; 1623 break; 1624 case i82541gi: 1625 case i82547gi: 1626 case i82540em: 1627 case i82540eplp: 1628 case i82541pi: 1629 case i82541gi2: 1630 case i82545gmc: 1631 case i82546gb: 1632 case i82546eb: 1633 areq = 1; 1634 csr32w(ctlr, Eecd, eecd|Areq); 1635 for(i = 0; i < 1000; i++){ 1636 if((eecd = csr32r(ctlr, Eecd)) & Agnt) 1637 break; 1638 microdelay(5); 1639 } 1640 if(!(eecd & Agnt)){ 1641 print("igbe: not granted EEPROM access\n"); 1642 goto release; 1643 } 1644 break; 1645 } 1646 snprint(rop, sizeof(rop), "S :%dDCc;", bits+3); 1647 1648 for(addr = 0; addr < 0x40; addr++){ 1649 /* 1650 * Read a word at address 'addr' from the Atmel AT93C46 1651 * 3-Wire Serial EEPROM or compatible. The EEPROM access is 1652 * controlled by 4 bits in Eecd. See the AT93C46 datasheet 1653 * for protocol details. 1654 */ 1655 if(at93c46io(ctlr, rop, (0x06<<bits)|addr) != 0){ 1656 print("igbe: can't set EEPROM address 0x%2.2X\n", addr); 1657 goto release; 1658 } 1659 data = at93c46io(ctlr, ":16COc;", 0); 1660 at93c46io(ctlr, "sic", 0); 1661 ctlr->eeprom[addr] = data; 1662 sum += data; 1663 } 1664 1665 release: 1666 if(areq) 1667 csr32w(ctlr, Eecd, eecd & ~Areq); 1668 return sum; 1669 } 1670 1671 static int 1672 igbedetach(Ctlr* ctlr) 1673 { 1674 int r, timeo; 1675 1676 /* 1677 * Perform a device reset to get the chip back to the 1678 * power-on state, followed by an EEPROM reset to read 1679 * the defaults for some internal registers. 1680 */ 1681 csr32w(ctlr, Imc, ~0); 1682 csr32w(ctlr, Rctl, 0); 1683 csr32w(ctlr, Tctl, 0); 1684 1685 delay(10); 1686 1687 csr32w(ctlr, Ctrl, Devrst); 1688 delay(1); 1689 for(timeo = 0; timeo < 1000; timeo++){ 1690 if(!(csr32r(ctlr, Ctrl) & Devrst)) 1691 break; 1692 delay(1); 1693 } 1694 if(csr32r(ctlr, Ctrl) & Devrst) 1695 return -1; 1696 r = csr32r(ctlr, Ctrlext); 1697 csr32w(ctlr, Ctrlext, r|Eerst); 1698 delay(1); 1699 for(timeo = 0; timeo < 1000; timeo++){ 1700 if(!(csr32r(ctlr, Ctrlext) & Eerst)) 1701 break; 1702 delay(1); 1703 } 1704 if(csr32r(ctlr, Ctrlext) & Eerst) 1705 return -1; 1706 1707 switch(ctlr->id){ 1708 default: 1709 break; 1710 case i82540em: 1711 case i82540eplp: 1712 case i82541gi: 1713 case i82541pi: 1714 case i82547gi: 1715 case i82541gi2: 1716 case i82545gmc: 1717 case i82546gb: 1718 case i82546eb: 1719 r = csr32r(ctlr, Manc); 1720 r &= ~Arpen; 1721 csr32w(ctlr, Manc, r); 1722 break; 1723 } 1724 1725 csr32w(ctlr, Imc, ~0); 1726 delay(1); 1727 for(timeo = 0; timeo < 1000; timeo++){ 1728 if(!csr32r(ctlr, Icr)) 1729 break; 1730 delay(1); 1731 } 1732 if(csr32r(ctlr, Icr)) 1733 return -1; 1734 1735 return 0; 1736 } 1737 1738 static void 1739 igbeshutdown(Ether* ether) 1740 { 1741 igbedetach(ether->ctlr); 1742 } 1743 1744 static int 1745 igbereset(Ctlr* ctlr) 1746 { 1747 int ctrl, i, pause, r, swdpio, txcw; 1748 1749 if(igbedetach(ctlr)) 1750 return -1; 1751 1752 /* 1753 * Read the EEPROM, validate the checksum 1754 * then get the device back to a power-on state. 1755 */ 1756 if((r = at93c46r(ctlr)) != 0xBABA){ 1757 print("igbe: bad EEPROM checksum - 0x%4.4uX\n", r); 1758 return -1; 1759 } 1760 1761 /* 1762 * Snarf and set up the receive addresses. 1763 * There are 16 addresses. The first should be the MAC address. 1764 * The others are cleared and not marked valid (MS bit of Rah). 1765 */ 1766 if ((ctlr->id == i82546gb || ctlr->id == i82546eb) && 1767 BUSFNO(ctlr->pcidev->tbdf) == 1) 1768 ctlr->eeprom[Ea+2] += 0x100; /* second interface */ 1769 for(i = Ea; i < Eaddrlen/2; i++){ 1770 if(i == Ea && ctlr->id == i82541gi && ctlr->eeprom[i] == 0xFFFF) 1771 ctlr->eeprom[i] = 0xD000; 1772 ctlr->ra[2*i] = ctlr->eeprom[i]; 1773 ctlr->ra[2*i+1] = ctlr->eeprom[i]>>8; 1774 } 1775 r = (ctlr->ra[3]<<24)|(ctlr->ra[2]<<16)|(ctlr->ra[1]<<8)|ctlr->ra[0]; 1776 csr32w(ctlr, Ral, r); 1777 r = 0x80000000|(ctlr->ra[5]<<8)|ctlr->ra[4]; 1778 csr32w(ctlr, Rah, r); 1779 for(i = 1; i < 16; i++){ 1780 csr32w(ctlr, Ral+i*8, 0); 1781 csr32w(ctlr, Rah+i*8, 0); 1782 } 1783 1784 /* 1785 * Clear the Multicast Table Array. 1786 * It's a 4096 bit vector accessed as 128 32-bit registers. 1787 */ 1788 memset(ctlr->mta, 0, sizeof(ctlr->mta)); 1789 for(i = 0; i < 128; i++) 1790 csr32w(ctlr, Mta+i*4, 0); 1791 1792 /* 1793 * Just in case the Eerst didn't load the defaults 1794 * (doesn't appear to fully on the 82543GC), do it manually. 1795 */ 1796 if (ctlr->id == i82543gc) { 1797 txcw = csr32r(ctlr, Txcw); 1798 txcw &= ~(TxcwAne|TxcwPauseMASK|TxcwFd); 1799 ctrl = csr32r(ctlr, Ctrl); 1800 ctrl &= ~(SwdpioloMASK|Frcspd|Ilos|Lrst|Fd); 1801 1802 if(ctlr->eeprom[Icw1] & 0x0400){ 1803 ctrl |= Fd; 1804 txcw |= TxcwFd; 1805 } 1806 if(ctlr->eeprom[Icw1] & 0x0200) 1807 ctrl |= Lrst; 1808 if(ctlr->eeprom[Icw1] & 0x0010) 1809 ctrl |= Ilos; 1810 if(ctlr->eeprom[Icw1] & 0x0800) 1811 ctrl |= Frcspd; 1812 swdpio = (ctlr->eeprom[Icw1] & 0x01E0)>>5; 1813 ctrl |= swdpio<<SwdpioloSHIFT; 1814 csr32w(ctlr, Ctrl, ctrl); 1815 1816 ctrl = csr32r(ctlr, Ctrlext); 1817 ctrl &= ~(Ips|SwdpiohiMASK); 1818 swdpio = (ctlr->eeprom[Icw2] & 0x00F0)>>4; 1819 if(ctlr->eeprom[Icw1] & 0x1000) 1820 ctrl |= Ips; 1821 ctrl |= swdpio<<SwdpiohiSHIFT; 1822 csr32w(ctlr, Ctrlext, ctrl); 1823 1824 if(ctlr->eeprom[Icw2] & 0x0800) 1825 txcw |= TxcwAne; 1826 pause = (ctlr->eeprom[Icw2] & 0x3000)>>12; 1827 txcw |= pause<<TxcwPauseSHIFT; 1828 switch(pause){ 1829 default: 1830 ctlr->fcrtl = 0x00002000; 1831 ctlr->fcrth = 0x00004000; 1832 txcw |= TxcwAs|TxcwPs; 1833 break; 1834 case 0: 1835 ctlr->fcrtl = 0x00002000; 1836 ctlr->fcrth = 0x00004000; 1837 break; 1838 case 2: 1839 ctlr->fcrtl = 0; 1840 ctlr->fcrth = 0; 1841 txcw |= TxcwAs; 1842 break; 1843 } 1844 ctlr->txcw = txcw; 1845 csr32w(ctlr, Txcw, txcw); 1846 } 1847 1848 1849 /* 1850 * Flow control - values from the datasheet. 1851 */ 1852 csr32w(ctlr, Fcal, 0x00C28001); 1853 csr32w(ctlr, Fcah, 0x00000100); 1854 csr32w(ctlr, Fct, 0x00008808); 1855 csr32w(ctlr, Fcttv, 0x00000100); 1856 1857 csr32w(ctlr, Fcrtl, ctlr->fcrtl); 1858 csr32w(ctlr, Fcrth, ctlr->fcrth); 1859 1860 if(!(csr32r(ctlr, Status) & Tbimode) && igbemii(ctlr) < 0) 1861 return -1; 1862 1863 return 0; 1864 } 1865 1866 static void 1867 igbepci(void) 1868 { 1869 int cls; 1870 Pcidev *p; 1871 Ctlr *ctlr; 1872 void *mem; 1873 1874 p = nil; 1875 while(p = pcimatch(p, 0, 0)){ 1876 if(p->ccrb != 0x02 || p->ccru != 0) 1877 continue; 1878 1879 switch((p->did<<16)|p->vid){ 1880 default: 1881 continue; 1882 case i82543gc: 1883 case i82544ei: 1884 case i82547ei: 1885 case i82540em: 1886 case i82540eplp: 1887 case i82541gi: 1888 case i82547gi: 1889 case i82541gi2: 1890 case i82541pi: 1891 case i82545gmc: 1892 case i82546gb: 1893 case i82546eb: 1894 break; 1895 } 1896 1897 mem = vmap(p->mem[0].bar & ~0x0F, p->mem[0].size); 1898 if(mem == nil){ 1899 print("igbe: can't map %8.8luX\n", p->mem[0].bar); 1900 continue; 1901 } 1902 cls = pcicfgr8(p, PciCLS); 1903 switch(cls){ 1904 default: 1905 print("igbe: unexpected CLS - %d\n", cls*4); 1906 break; 1907 case 0x00: 1908 case 0xFF: 1909 print("igbe: unusable CLS\n"); 1910 continue; 1911 case 0x08: 1912 case 0x10: 1913 break; 1914 } 1915 ctlr = malloc(sizeof(Ctlr)); 1916 ctlr->port = p->mem[0].bar & ~0x0F; 1917 ctlr->pcidev = p; 1918 ctlr->id = (p->did<<16)|p->vid; 1919 ctlr->cls = cls*4; 1920 ctlr->nic = mem; 1921 1922 if(igbereset(ctlr)){ 1923 free(ctlr); 1924 vunmap(mem, p->mem[0].size); 1925 continue; 1926 } 1927 pcisetbme(p); 1928 1929 if(igbectlrhead != nil) 1930 igbectlrtail->next = ctlr; 1931 else 1932 igbectlrhead = ctlr; 1933 igbectlrtail = ctlr; 1934 } 1935 } 1936 1937 static int 1938 igbepnp(Ether* edev) 1939 { 1940 Ctlr *ctlr; 1941 1942 if(igbectlrhead == nil) 1943 igbepci(); 1944 1945 /* 1946 * Any adapter matches if no edev->port is supplied, 1947 * otherwise the ports must match. 1948 */ 1949 for(ctlr = igbectlrhead; ctlr != nil; ctlr = ctlr->next){ 1950 if(ctlr->active) 1951 continue; 1952 if(edev->port == 0 || edev->port == ctlr->port){ 1953 ctlr->active = 1; 1954 break; 1955 } 1956 } 1957 if(ctlr == nil) 1958 return -1; 1959 1960 edev->ctlr = ctlr; 1961 edev->port = ctlr->port; 1962 edev->irq = ctlr->pcidev->intl; 1963 edev->tbdf = ctlr->pcidev->tbdf; 1964 edev->mbps = 1000; 1965 memmove(edev->ea, ctlr->ra, Eaddrlen); 1966 1967 /* 1968 * Linkage to the generic ethernet driver. 1969 */ 1970 edev->attach = igbeattach; 1971 edev->transmit = igbetransmit; 1972 edev->interrupt = igbeinterrupt; 1973 edev->ifstat = igbeifstat; 1974 edev->ctl = igbectl; 1975 1976 edev->arg = edev; 1977 edev->promiscuous = igbepromiscuous; 1978 edev->shutdown = igbeshutdown; 1979 edev->multicast = igbemulticast; 1980 1981 return 0; 1982 } 1983 1984 void 1985 etherigbelink(void) 1986 { 1987 addethercard("i82543", igbepnp); 1988 addethercard("igbe", igbepnp); 1989 } 1990 1991