1 /* 2 * Intel 82557 Fast Ethernet PCI Bus LAN Controller 3 * as found on the Intel EtherExpress PRO/100B. This chip is full 4 * of smarts, unfortunately they're not all in the right place. 5 * To do: 6 * the PCI scanning code could be made common to other adapters; 7 * auto-negotiation, full-duplex; 8 * optionally use memory-mapped registers; 9 * detach for PCI reset problems (also towards loadable drivers). 10 */ 11 #include "u.h" 12 #include "../port/lib.h" 13 #include "mem.h" 14 #include "dat.h" 15 #include "fns.h" 16 #include "io.h" 17 #include "../port/error.h" 18 #include "../port/netif.h" 19 20 #include "etherif.h" 21 22 enum { 23 Nrfd = 64, /* receive frame area */ 24 Ncb = 64, /* maximum control blocks queued */ 25 26 NullPointer = 0xFFFFFFFF, /* 82557 NULL pointer */ 27 }; 28 29 enum { /* CSR */ 30 Status = 0x00, /* byte or word (word includes Ack) */ 31 Ack = 0x01, /* byte */ 32 CommandR = 0x02, /* byte or word (word includes Interrupt) */ 33 Interrupt = 0x03, /* byte */ 34 General = 0x04, /* dword */ 35 Port = 0x08, /* dword */ 36 Fcr = 0x0C, /* Flash control register */ 37 Ecr = 0x0E, /* EEPROM control register */ 38 Mcr = 0x10, /* MDI control register */ 39 Gstatus = 0x1D, /* General status register */ 40 }; 41 42 enum { /* Status */ 43 RUidle = 0x0000, 44 RUsuspended = 0x0004, 45 RUnoresources = 0x0008, 46 RUready = 0x0010, 47 RUrbd = 0x0020, /* bit */ 48 RUstatus = 0x003F, /* mask */ 49 50 CUidle = 0x0000, 51 CUsuspended = 0x0040, 52 CUactive = 0x0080, 53 CUstatus = 0x00C0, /* mask */ 54 55 StatSWI = 0x0400, /* SoftWare generated Interrupt */ 56 StatMDI = 0x0800, /* MDI r/w done */ 57 StatRNR = 0x1000, /* Receive unit Not Ready */ 58 StatCNA = 0x2000, /* Command unit Not Active (Active->Idle) */ 59 StatFR = 0x4000, /* Finished Receiving */ 60 StatCX = 0x8000, /* Command eXecuted */ 61 StatTNO = 0x8000, /* Transmit NOT OK */ 62 }; 63 64 enum { /* Command (byte) */ 65 CUnop = 0x00, 66 CUstart = 0x10, 67 CUresume = 0x20, 68 LoadDCA = 0x40, /* Load Dump Counters Address */ 69 DumpSC = 0x50, /* Dump Statistical Counters */ 70 LoadCUB = 0x60, /* Load CU Base */ 71 ResetSA = 0x70, /* Dump and Reset Statistical Counters */ 72 73 RUstart = 0x01, 74 RUresume = 0x02, 75 RUabort = 0x04, 76 LoadHDS = 0x05, /* Load Header Data Size */ 77 LoadRUB = 0x06, /* Load RU Base */ 78 RBDresume = 0x07, /* Resume frame reception */ 79 }; 80 81 enum { /* Interrupt (byte) */ 82 InterruptM = 0x01, /* interrupt Mask */ 83 InterruptSI = 0x02, /* Software generated Interrupt */ 84 }; 85 86 enum { /* Ecr */ 87 EEsk = 0x01, /* serial clock */ 88 EEcs = 0x02, /* chip select */ 89 EEdi = 0x04, /* serial data in */ 90 EEdo = 0x08, /* serial data out */ 91 92 EEstart = 0x04, /* start bit */ 93 EEread = 0x02, /* read opcode */ 94 }; 95 96 enum { /* Mcr */ 97 MDIread = 0x08000000, /* read opcode */ 98 MDIwrite = 0x04000000, /* write opcode */ 99 MDIready = 0x10000000, /* ready bit */ 100 MDIie = 0x20000000, /* interrupt enable */ 101 }; 102 103 typedef struct Rfd { 104 int field; 105 ulong link; 106 ulong rbd; 107 ushort count; 108 ushort size; 109 110 uchar data[1700]; 111 } Rfd; 112 113 enum { /* field */ 114 RfdCollision = 0x00000001, 115 RfdIA = 0x00000002, /* IA match */ 116 RfdRxerr = 0x00000010, /* PHY character error */ 117 RfdType = 0x00000020, /* Type frame */ 118 RfdRunt = 0x00000080, 119 RfdOverrun = 0x00000100, 120 RfdBuffer = 0x00000200, 121 RfdAlignment = 0x00000400, 122 RfdCRC = 0x00000800, 123 124 RfdOK = 0x00002000, /* frame received OK */ 125 RfdC = 0x00008000, /* reception Complete */ 126 RfdSF = 0x00080000, /* Simplified or Flexible (1) Rfd */ 127 RfdH = 0x00100000, /* Header RFD */ 128 129 RfdI = 0x20000000, /* Interrupt after completion */ 130 RfdS = 0x40000000, /* Suspend after completion */ 131 RfdEL = 0x80000000, /* End of List */ 132 }; 133 134 enum { /* count */ 135 RfdF = 0x4000, 136 RfdEOF = 0x8000, 137 }; 138 139 typedef struct Cb Cb; 140 typedef struct Cb { 141 ushort status; 142 ushort command; 143 ulong link; 144 union { 145 uchar data[24]; /* CbIAS + CbConfigure */ 146 struct { 147 ulong tbd; 148 ushort count; 149 uchar threshold; 150 uchar number; 151 152 ulong tba; 153 ushort tbasz; 154 ushort pad; 155 }; 156 }; 157 158 Block* bp; 159 Cb* next; 160 } Cb; 161 162 enum { /* action command */ 163 CbU = 0x1000, /* transmit underrun */ 164 CbOK = 0x2000, /* DMA completed OK */ 165 CbC = 0x8000, /* execution Complete */ 166 167 CbNOP = 0x0000, 168 CbIAS = 0x0001, /* Individual Address Setup */ 169 CbConfigure = 0x0002, 170 CbMAS = 0x0003, /* Multicast Address Setup */ 171 CbTransmit = 0x0004, 172 CbDump = 0x0006, 173 CbDiagnose = 0x0007, 174 CbCommand = 0x0007, /* mask */ 175 176 CbSF = 0x0008, /* Flexible-mode CbTransmit */ 177 178 CbI = 0x2000, /* Interrupt after completion */ 179 CbS = 0x4000, /* Suspend after completion */ 180 CbEL = 0x8000, /* End of List */ 181 }; 182 183 enum { /* CbTransmit count */ 184 CbEOF = 0x8000, 185 }; 186 187 typedef struct Ctlr Ctlr; 188 typedef struct Ctlr { 189 Lock slock; /* attach */ 190 int state; 191 192 int port; 193 Pcidev* pcidev; 194 Ctlr* next; 195 int active; 196 197 int eepromsz; /* address size in bits */ 198 ushort* eeprom; 199 200 Lock miilock; 201 202 int tick; 203 204 Lock rlock; /* registers */ 205 int command; /* last command issued */ 206 207 Block* rfdhead; /* receive side */ 208 Block* rfdtail; 209 int nrfd; 210 211 Lock cblock; /* transmit side */ 212 int action; 213 int nop; 214 uchar configdata[24]; 215 int threshold; 216 int ncb; 217 Cb* cbr; 218 Cb* cbhead; 219 Cb* cbtail; 220 int cbq; 221 int cbqmax; 222 int cbqmaxhw; 223 224 Lock dlock; /* dump statistical counters */ 225 ulong dump[17]; 226 } Ctlr; 227 228 static Ctlr* ctlrhead; 229 static Ctlr* ctlrtail; 230 231 static uchar configdata[24] = { 232 0x16, /* byte count */ 233 0x08, /* Rx/Tx FIFO limit */ 234 0x00, /* adaptive IFS */ 235 0x00, 236 0x00, /* Rx DMA maximum byte count */ 237 // 0x80, /* Tx DMA maximum byte count */ 238 0x00, /* Tx DMA maximum byte count */ 239 0x32, /* !late SCB, CNA interrupts */ 240 0x03, /* discard short Rx frames */ 241 0x00, /* 503/MII */ 242 243 0x00, 244 0x2E, /* normal operation, NSAI */ 245 0x00, /* linear priority */ 246 0x60, /* inter-frame spacing */ 247 0x00, 248 0xF2, 249 0xC8, /* 503, promiscuous mode off */ 250 0x00, 251 0x40, 252 0xF3, /* transmit padding enable */ 253 0x80, /* full duplex pin enable */ 254 0x3F, /* no Multi IA */ 255 0x05, /* no Multi Cast ALL */ 256 }; 257 258 #define csr8r(c, r) (inb((c)->port+(r))) 259 #define csr16r(c, r) (ins((c)->port+(r))) 260 #define csr32r(c, r) (inl((c)->port+(r))) 261 #define csr8w(c, r, b) (outb((c)->port+(r), (int)(b))) 262 #define csr16w(c, r, w) (outs((c)->port+(r), (ushort)(w))) 263 #define csr32w(c, r, l) (outl((c)->port+(r), (ulong)(l))) 264 265 static void 266 command(Ctlr* ctlr, int c, int v) 267 { 268 int timeo; 269 270 ilock(&ctlr->rlock); 271 272 /* 273 * Only back-to-back CUresume can be done 274 * without waiting for any previous command to complete. 275 * This should be the common case. 276 * Unfortunately there's a chip errata where back-to-back 277 * CUresumes can be lost, the fix is to always wait. 278 if(c == CUresume && ctlr->command == CUresume){ 279 csr8w(ctlr, CommandR, c); 280 iunlock(&ctlr->rlock); 281 return; 282 } 283 */ 284 285 for(timeo = 0; timeo < 100; timeo++){ 286 if(!csr8r(ctlr, CommandR)) 287 break; 288 microdelay(1); 289 } 290 if(timeo >= 100){ 291 ctlr->command = -1; 292 iunlock(&ctlr->rlock); 293 iprint("i82557: command %#ux %#ux timeout\n", c, v); 294 return; 295 } 296 297 switch(c){ 298 299 case CUstart: 300 case LoadDCA: 301 case LoadCUB: 302 case RUstart: 303 case LoadHDS: 304 case LoadRUB: 305 csr32w(ctlr, General, v); 306 break; 307 308 /* 309 case CUnop: 310 case CUresume: 311 case DumpSC: 312 case ResetSA: 313 case RUresume: 314 case RUabort: 315 */ 316 default: 317 break; 318 } 319 csr8w(ctlr, CommandR, c); 320 ctlr->command = c; 321 322 iunlock(&ctlr->rlock); 323 } 324 325 static Block* 326 rfdalloc(ulong link) 327 { 328 Block *bp; 329 Rfd *rfd; 330 331 if(bp = iallocb(sizeof(Rfd))){ 332 rfd = (Rfd*)bp->rp; 333 rfd->field = 0; 334 rfd->link = link; 335 rfd->rbd = NullPointer; 336 rfd->count = 0; 337 rfd->size = sizeof(Etherpkt); 338 } 339 340 return bp; 341 } 342 343 static void 344 ethwatchdog(void* arg) 345 { 346 Ether *ether; 347 Ctlr *ctlr; 348 static void txstart(Ether*); 349 350 ether = arg; 351 for(;;){ 352 tsleep(&up->sleep, return0, 0, 4000); 353 354 /* 355 * Hmmm. This doesn't seem right. Currently 356 * the device can't be disabled but it may be in 357 * the future. 358 */ 359 ctlr = ether->ctlr; 360 if(ctlr == nil || ctlr->state == 0){ 361 print("%s: exiting\n", up->text); 362 pexit("disabled", 0); 363 } 364 365 ilock(&ctlr->cblock); 366 if(ctlr->tick++){ 367 ctlr->action = CbMAS; 368 txstart(ether); 369 } 370 iunlock(&ctlr->cblock); 371 } 372 } 373 374 static void 375 attach(Ether* ether) 376 { 377 Ctlr *ctlr; 378 char name[KNAMELEN]; 379 380 ctlr = ether->ctlr; 381 lock(&ctlr->slock); 382 if(ctlr->state == 0){ 383 ilock(&ctlr->rlock); 384 csr8w(ctlr, Interrupt, 0); 385 iunlock(&ctlr->rlock); 386 command(ctlr, RUstart, PADDR(ctlr->rfdhead->rp)); 387 ctlr->state = 1; 388 389 /* 390 * Start the watchdog timer for the receive lockup errata 391 * unless the EEPROM compatibility word indicates it may be 392 * omitted. 393 */ 394 if((ctlr->eeprom[0x03] & 0x0003) != 0x0003){ 395 snprint(name, KNAMELEN, "#l%dwatchdog", ether->ctlrno); 396 kproc(name, ethwatchdog, ether); 397 } 398 } 399 unlock(&ctlr->slock); 400 } 401 402 static long 403 ifstat(Ether* ether, void* a, long n, ulong offset) 404 { 405 char *p; 406 int i, len, phyaddr; 407 Ctlr *ctlr; 408 ulong dump[17]; 409 410 ctlr = ether->ctlr; 411 lock(&ctlr->dlock); 412 413 /* 414 * Start the command then 415 * wait for completion status, 416 * should be 0xA005. 417 */ 418 ctlr->dump[16] = 0; 419 command(ctlr, DumpSC, 0); 420 while(ctlr->dump[16] == 0) 421 ; 422 423 ether->oerrs = ctlr->dump[1]+ctlr->dump[2]+ctlr->dump[3]; 424 ether->crcs = ctlr->dump[10]; 425 ether->frames = ctlr->dump[11]; 426 ether->buffs = ctlr->dump[12]+ctlr->dump[15]; 427 ether->overflows = ctlr->dump[13]; 428 429 if(n == 0){ 430 unlock(&ctlr->dlock); 431 return 0; 432 } 433 434 memmove(dump, ctlr->dump, sizeof(dump)); 435 unlock(&ctlr->dlock); 436 437 p = malloc(READSTR); 438 if(p == nil) 439 error(Enomem); 440 len = snprint(p, READSTR, "transmit good frames: %lud\n", dump[0]); 441 len += snprint(p+len, READSTR-len, "transmit maximum collisions errors: %lud\n", dump[1]); 442 len += snprint(p+len, READSTR-len, "transmit late collisions errors: %lud\n", dump[2]); 443 len += snprint(p+len, READSTR-len, "transmit underrun errors: %lud\n", dump[3]); 444 len += snprint(p+len, READSTR-len, "transmit lost carrier sense: %lud\n", dump[4]); 445 len += snprint(p+len, READSTR-len, "transmit deferred: %lud\n", dump[5]); 446 len += snprint(p+len, READSTR-len, "transmit single collisions: %lud\n", dump[6]); 447 len += snprint(p+len, READSTR-len, "transmit multiple collisions: %lud\n", dump[7]); 448 len += snprint(p+len, READSTR-len, "transmit total collisions: %lud\n", dump[8]); 449 len += snprint(p+len, READSTR-len, "receive good frames: %lud\n", dump[9]); 450 len += snprint(p+len, READSTR-len, "receive CRC errors: %lud\n", dump[10]); 451 len += snprint(p+len, READSTR-len, "receive alignment errors: %lud\n", dump[11]); 452 len += snprint(p+len, READSTR-len, "receive resource errors: %lud\n", dump[12]); 453 len += snprint(p+len, READSTR-len, "receive overrun errors: %lud\n", dump[13]); 454 len += snprint(p+len, READSTR-len, "receive collision detect errors: %lud\n", dump[14]); 455 len += snprint(p+len, READSTR-len, "receive short frame errors: %lud\n", dump[15]); 456 len += snprint(p+len, READSTR-len, "nop: %d\n", ctlr->nop); 457 if(ctlr->cbqmax > ctlr->cbqmaxhw) 458 ctlr->cbqmaxhw = ctlr->cbqmax; 459 len += snprint(p+len, READSTR-len, "cbqmax: %d\n", ctlr->cbqmax); 460 ctlr->cbqmax = 0; 461 len += snprint(p+len, READSTR-len, "threshold: %d\n", ctlr->threshold); 462 463 len += snprint(p+len, READSTR-len, "eeprom:"); 464 for(i = 0; i < (1<<ctlr->eepromsz); i++){ 465 if(i && ((i & 0x07) == 0)) 466 len += snprint(p+len, READSTR-len, "\n "); 467 len += snprint(p+len, READSTR-len, " %4.4ux", ctlr->eeprom[i]); 468 } 469 470 if((ctlr->eeprom[6] & 0x1F00) && !(ctlr->eeprom[6] & 0x8000)){ 471 phyaddr = ctlr->eeprom[6] & 0x00FF; 472 len += snprint(p+len, READSTR-len, "\nphy %2d:", phyaddr); 473 for(i = 0; i < 6; i++){ 474 static int miir(Ctlr*, int, int); 475 476 len += snprint(p+len, READSTR-len, " %4.4ux", 477 miir(ctlr, phyaddr, i)); 478 } 479 } 480 481 snprint(p+len, READSTR-len, "\n"); 482 n = readstr(offset, a, n, p); 483 free(p); 484 485 return n; 486 } 487 488 static void 489 txstart(Ether* ether) 490 { 491 Ctlr *ctlr; 492 Block *bp; 493 Cb *cb; 494 495 ctlr = ether->ctlr; 496 while(ctlr->cbq < (ctlr->ncb-1)){ 497 cb = ctlr->cbhead->next; 498 if(ctlr->action == 0){ 499 bp = qget(ether->oq); 500 if(bp == nil) 501 break; 502 503 cb->command = CbS|CbSF|CbTransmit; 504 cb->tbd = PADDR(&cb->tba); 505 cb->count = 0; 506 cb->threshold = ctlr->threshold; 507 cb->number = 1; 508 cb->tba = PADDR(bp->rp); 509 cb->bp = bp; 510 cb->tbasz = BLEN(bp); 511 } 512 else if(ctlr->action == CbConfigure){ 513 cb->command = CbS|CbConfigure; 514 memmove(cb->data, ctlr->configdata, sizeof(ctlr->configdata)); 515 ctlr->action = 0; 516 } 517 else if(ctlr->action == CbIAS){ 518 cb->command = CbS|CbIAS; 519 memmove(cb->data, ether->ea, Eaddrlen); 520 ctlr->action = 0; 521 } 522 else if(ctlr->action == CbMAS){ 523 cb->command = CbS|CbMAS; 524 memset(cb->data, 0, sizeof(cb->data)); 525 ctlr->action = 0; 526 } 527 else{ 528 print("#l%d: action %#ux\n", ether->ctlrno, ctlr->action); 529 ctlr->action = 0; 530 break; 531 } 532 cb->status = 0; 533 534 coherence(); 535 ctlr->cbhead->command &= ~CbS; 536 ctlr->cbhead = cb; 537 ctlr->cbq++; 538 } 539 540 /* 541 * Workaround for some broken HUB chips 542 * when connected at 10Mb/s half-duplex. 543 */ 544 if(ctlr->nop){ 545 command(ctlr, CUnop, 0); 546 microdelay(1); 547 } 548 command(ctlr, CUresume, 0); 549 550 if(ctlr->cbq > ctlr->cbqmax) 551 ctlr->cbqmax = ctlr->cbq; 552 } 553 554 static void 555 configure(Ether* ether, int promiscuous) 556 { 557 Ctlr *ctlr; 558 559 ctlr = ether->ctlr; 560 ilock(&ctlr->cblock); 561 if(promiscuous){ 562 ctlr->configdata[6] |= 0x80; /* Save Bad Frames */ 563 //ctlr->configdata[6] &= ~0x40; /* !Discard Overrun Rx Frames */ 564 ctlr->configdata[7] &= ~0x01; /* !Discard Short Rx Frames */ 565 ctlr->configdata[15] |= 0x01; /* Promiscuous mode */ 566 ctlr->configdata[18] &= ~0x01; /* (!Padding enable?), !stripping enable */ 567 ctlr->configdata[21] |= 0x08; /* Multi Cast ALL */ 568 } 569 else{ 570 ctlr->configdata[6] &= ~0x80; 571 //ctlr->configdata[6] |= 0x40; 572 ctlr->configdata[7] |= 0x01; 573 ctlr->configdata[15] &= ~0x01; 574 ctlr->configdata[18] |= 0x01; /* 0x03? */ 575 ctlr->configdata[21] &= ~0x08; 576 } 577 ctlr->action = CbConfigure; 578 txstart(ether); 579 iunlock(&ctlr->cblock); 580 } 581 582 static void 583 promiscuous(void* arg, int on) 584 { 585 configure(arg, on); 586 } 587 588 static void 589 multicast(void* ether, uchar *addr, int add) 590 { 591 USED(addr); 592 /* 593 * TODO: if (add) add addr to list of mcast addrs in controller 594 * else remove addr from list of mcast addrs in controller 595 * enable multicast input (see CbMAS) instead of promiscuous mode. 596 */ 597 if (add) 598 configure(ether, 1); 599 } 600 601 static void 602 transmit(Ether* ether) 603 { 604 Ctlr *ctlr; 605 606 ctlr = ether->ctlr; 607 ilock(&ctlr->cblock); 608 txstart(ether); 609 iunlock(&ctlr->cblock); 610 } 611 612 static void 613 receive(Ether* ether) 614 { 615 Rfd *rfd; 616 Ctlr *ctlr; 617 int count; 618 Block *bp, *pbp, *xbp; 619 620 ctlr = ether->ctlr; 621 bp = ctlr->rfdhead; 622 for(rfd = (Rfd*)bp->rp; rfd->field & RfdC; rfd = (Rfd*)bp->rp){ 623 /* 624 * If it's an OK receive frame 625 * 1) save the count 626 * 2) if it's small, try to allocate a block and copy 627 * the data, then adjust the necessary fields for reuse; 628 * 3) if it's big, try to allocate a new Rfd and if 629 * successful 630 * adjust the received buffer pointers for the 631 * actual data received; 632 * initialise the replacement buffer to point to 633 * the next in the ring; 634 * initialise bp to point to the replacement; 635 * 4) if there's a good packet, pass it on for disposal. 636 */ 637 if(rfd->field & RfdOK){ 638 pbp = nil; 639 count = rfd->count & 0x3FFF; 640 if((count < ETHERMAXTU/4) && (pbp = iallocb(count))){ 641 memmove(pbp->rp, bp->rp+offsetof(Rfd, data[0]), count); 642 pbp->wp = pbp->rp + count; 643 644 rfd->count = 0; 645 rfd->field = 0; 646 } 647 else if(xbp = rfdalloc(rfd->link)){ 648 bp->rp += offsetof(Rfd, data[0]); 649 bp->wp = bp->rp + count; 650 651 xbp->next = bp->next; 652 bp->next = 0; 653 654 pbp = bp; 655 bp = xbp; 656 } 657 if(pbp != nil) 658 etheriq(ether, pbp, 1); 659 } 660 else{ 661 rfd->count = 0; 662 rfd->field = 0; 663 } 664 665 /* 666 * The ring tail pointer follows the head with with one 667 * unused buffer in between to defeat hardware prefetch; 668 * once the tail pointer has been bumped on to the next 669 * and the new tail has the Suspend bit set, it can be 670 * removed from the old tail buffer. 671 * As a replacement for the current head buffer may have 672 * been allocated above, ensure that the new tail points 673 * to it (next and link). 674 */ 675 rfd = (Rfd*)ctlr->rfdtail->rp; 676 ctlr->rfdtail = ctlr->rfdtail->next; 677 ctlr->rfdtail->next = bp; 678 ((Rfd*)ctlr->rfdtail->rp)->link = PADDR(bp->rp); 679 ((Rfd*)ctlr->rfdtail->rp)->field |= RfdS; 680 coherence(); 681 rfd->field &= ~RfdS; 682 683 /* 684 * Finally done with the current (possibly replaced) 685 * head, move on to the next and maintain the sentinel 686 * between tail and head. 687 */ 688 ctlr->rfdhead = bp->next; 689 bp = ctlr->rfdhead; 690 } 691 } 692 693 static void 694 interrupt(Ureg*, void* arg) 695 { 696 Cb* cb; 697 Ctlr *ctlr; 698 Ether *ether; 699 int status; 700 701 ether = arg; 702 ctlr = ether->ctlr; 703 704 for(;;){ 705 ilock(&ctlr->rlock); 706 status = csr16r(ctlr, Status); 707 csr8w(ctlr, Ack, (status>>8) & 0xFF); 708 iunlock(&ctlr->rlock); 709 710 if(!(status & (StatCX|StatFR|StatCNA|StatRNR|StatMDI|StatSWI))) 711 break; 712 713 /* 714 * If the watchdog timer for the receiver lockup errata is running, 715 * let it know the receiver is active. 716 */ 717 if(status & (StatFR|StatRNR)){ 718 ilock(&ctlr->cblock); 719 ctlr->tick = 0; 720 iunlock(&ctlr->cblock); 721 } 722 723 if(status & StatFR){ 724 receive(ether); 725 status &= ~StatFR; 726 } 727 728 if(status & StatRNR){ 729 command(ctlr, RUresume, 0); 730 status &= ~StatRNR; 731 } 732 733 if(status & StatCNA){ 734 ilock(&ctlr->cblock); 735 736 cb = ctlr->cbtail; 737 while(ctlr->cbq){ 738 if(!(cb->status & CbC)) 739 break; 740 if(cb->bp){ 741 freeb(cb->bp); 742 cb->bp = nil; 743 } 744 if((cb->status & CbU) && ctlr->threshold < 0xE0) 745 ctlr->threshold++; 746 747 ctlr->cbq--; 748 cb = cb->next; 749 } 750 ctlr->cbtail = cb; 751 752 txstart(ether); 753 iunlock(&ctlr->cblock); 754 755 status &= ~StatCNA; 756 } 757 758 if(status & (StatCX|StatFR|StatCNA|StatRNR|StatMDI|StatSWI)) 759 panic("#l%d: status %#ux\n", ether->ctlrno, status); 760 } 761 } 762 763 static void 764 ctlrinit(Ctlr* ctlr) 765 { 766 int i; 767 Block *bp; 768 Rfd *rfd; 769 ulong link; 770 771 /* 772 * Create the Receive Frame Area (RFA) as a ring of allocated 773 * buffers. 774 * A sentinel buffer is maintained between the last buffer in 775 * the ring (marked with RfdS) and the head buffer to defeat the 776 * hardware prefetch of the next RFD and allow dynamic buffer 777 * allocation. 778 */ 779 link = NullPointer; 780 for(i = 0; i < Nrfd; i++){ 781 bp = rfdalloc(link); 782 if(ctlr->rfdhead == nil) 783 ctlr->rfdtail = bp; 784 bp->next = ctlr->rfdhead; 785 ctlr->rfdhead = bp; 786 link = PADDR(bp->rp); 787 } 788 ctlr->rfdtail->next = ctlr->rfdhead; 789 rfd = (Rfd*)ctlr->rfdtail->rp; 790 rfd->link = PADDR(ctlr->rfdhead->rp); 791 rfd->field |= RfdS; 792 ctlr->rfdhead = ctlr->rfdhead->next; 793 794 /* 795 * Create a ring of control blocks for the 796 * transmit side. 797 */ 798 ilock(&ctlr->cblock); 799 ctlr->cbr = malloc(ctlr->ncb*sizeof(Cb)); 800 if(ctlr->cbr == nil) { 801 iunlock(&ctlr->cblock); 802 error(Enomem); 803 } 804 for(i = 0; i < ctlr->ncb; i++){ 805 ctlr->cbr[i].status = CbC|CbOK; 806 ctlr->cbr[i].command = CbS|CbNOP; 807 ctlr->cbr[i].link = PADDR(&ctlr->cbr[NEXT(i, ctlr->ncb)].status); 808 ctlr->cbr[i].next = &ctlr->cbr[NEXT(i, ctlr->ncb)]; 809 } 810 ctlr->cbhead = ctlr->cbr; 811 ctlr->cbtail = ctlr->cbr; 812 ctlr->cbq = 0; 813 814 memmove(ctlr->configdata, configdata, sizeof(configdata)); 815 ctlr->threshold = 80; 816 ctlr->tick = 0; 817 818 iunlock(&ctlr->cblock); 819 } 820 821 static int 822 miir(Ctlr* ctlr, int phyadd, int regadd) 823 { 824 int mcr, timo; 825 826 lock(&ctlr->miilock); 827 csr32w(ctlr, Mcr, MDIread|(phyadd<<21)|(regadd<<16)); 828 mcr = 0; 829 for(timo = 64; timo; timo--){ 830 mcr = csr32r(ctlr, Mcr); 831 if(mcr & MDIready) 832 break; 833 microdelay(1); 834 } 835 unlock(&ctlr->miilock); 836 837 if(mcr & MDIready) 838 return mcr & 0xFFFF; 839 840 return -1; 841 } 842 843 static int 844 miiw(Ctlr* ctlr, int phyadd, int regadd, int data) 845 { 846 int mcr, timo; 847 848 lock(&ctlr->miilock); 849 csr32w(ctlr, Mcr, MDIwrite|(phyadd<<21)|(regadd<<16)|(data & 0xFFFF)); 850 mcr = 0; 851 for(timo = 64; timo; timo--){ 852 mcr = csr32r(ctlr, Mcr); 853 if(mcr & MDIready) 854 break; 855 microdelay(1); 856 } 857 unlock(&ctlr->miilock); 858 859 if(mcr & MDIready) 860 return 0; 861 862 return -1; 863 } 864 865 static int 866 hy93c46r(Ctlr* ctlr, int r) 867 { 868 int data, i, op, size; 869 870 /* 871 * Hyundai HY93C46 or equivalent serial EEPROM. 872 * This sequence for reading a 16-bit register 'r' 873 * in the EEPROM is taken straight from Section 874 * 3.3.4.2 of the Intel 82557 User's Guide. 875 */ 876 reread: 877 csr16w(ctlr, Ecr, EEcs); 878 op = EEstart|EEread; 879 for(i = 2; i >= 0; i--){ 880 data = (((op>>i) & 0x01)<<2)|EEcs; 881 csr16w(ctlr, Ecr, data); 882 csr16w(ctlr, Ecr, data|EEsk); 883 microdelay(1); 884 csr16w(ctlr, Ecr, data); 885 microdelay(1); 886 } 887 888 /* 889 * First time through must work out the EEPROM size. 890 */ 891 if((size = ctlr->eepromsz) == 0) 892 size = 8; 893 894 for(size = size-1; size >= 0; size--){ 895 data = (((r>>size) & 0x01)<<2)|EEcs; 896 csr16w(ctlr, Ecr, data); 897 csr16w(ctlr, Ecr, data|EEsk); 898 delay(1); 899 csr16w(ctlr, Ecr, data); 900 microdelay(1); 901 if(!(csr16r(ctlr, Ecr) & EEdo)) 902 break; 903 } 904 905 data = 0; 906 for(i = 15; i >= 0; i--){ 907 csr16w(ctlr, Ecr, EEcs|EEsk); 908 microdelay(1); 909 if(csr16r(ctlr, Ecr) & EEdo) 910 data |= (1<<i); 911 csr16w(ctlr, Ecr, EEcs); 912 microdelay(1); 913 } 914 915 csr16w(ctlr, Ecr, 0); 916 917 if(ctlr->eepromsz == 0){ 918 ctlr->eepromsz = 8-size; 919 ctlr->eeprom = malloc((1<<ctlr->eepromsz)*sizeof(ushort)); 920 if(ctlr->eeprom == nil) 921 error(Enomem); 922 goto reread; 923 } 924 925 return data; 926 } 927 928 static void 929 i82557pci(void) 930 { 931 Pcidev *p; 932 Ctlr *ctlr; 933 int i, nop, port; 934 935 p = nil; 936 nop = 0; 937 while(p = pcimatch(p, 0x8086, 0)){ 938 switch(p->did){ 939 default: 940 continue; 941 case 0x1031: /* Intel 82562EM */ 942 case 0x103B: /* Intel 82562EM */ 943 case 0x103C: /* Intel 82562EM */ 944 case 0x1050: /* Intel 82562EZ */ 945 case 0x1039: /* Intel 82801BD PRO/100 VE */ 946 case 0x103A: /* Intel 82562 PRO/100 VE */ 947 case 0x103D: /* Intel 82562 PRO/100 VE */ 948 case 0x1064: /* Intel 82562 PRO/100 VE */ 949 case 0x2449: /* Intel 82562ET */ 950 case 0x27DC: /* Intel 82801G PRO/100 VE */ 951 nop = 1; 952 /*FALLTHROUGH*/ 953 case 0x1209: /* Intel 82559ER */ 954 case 0x1229: /* Intel 8255[789] */ 955 case 0x1030: /* Intel 82559 InBusiness 10/100 */ 956 break; 957 } 958 959 if(pcigetpms(p) > 0){ 960 pcisetpms(p, 0); 961 962 for(i = 0; i < 6; i++) 963 pcicfgw32(p, PciBAR0+i*4, p->mem[i].bar); 964 pcicfgw8(p, PciINTL, p->intl); 965 pcicfgw8(p, PciLTR, p->ltr); 966 pcicfgw8(p, PciCLS, p->cls); 967 pcicfgw16(p, PciPCR, p->pcr); 968 } 969 970 /* 971 * bar[0] is the memory-mapped register address (4KB), 972 * bar[1] is the I/O port register address (32 bytes) and 973 * bar[2] is for the flash ROM (1MB). 974 */ 975 port = p->mem[1].bar & ~0x01; 976 if(ioalloc(port, p->mem[1].size, 0, "i82557") < 0){ 977 print("i82557: port %#ux in use\n", port); 978 continue; 979 } 980 981 ctlr = malloc(sizeof(Ctlr)); 982 if(ctlr == nil) 983 error(Enomem); 984 ctlr->port = port; 985 ctlr->pcidev = p; 986 ctlr->nop = nop; 987 988 if(ctlrhead != nil) 989 ctlrtail->next = ctlr; 990 else 991 ctlrhead = ctlr; 992 ctlrtail = ctlr; 993 994 pcisetbme(p); 995 } 996 } 997 998 static char* mediatable[9] = { 999 "10BASE-T", /* TP */ 1000 "10BASE-2", /* BNC */ 1001 "10BASE-5", /* AUI */ 1002 "100BASE-TX", 1003 "10BASE-TFD", 1004 "100BASE-TXFD", 1005 "100BASE-T4", 1006 "100BASE-FX", 1007 "100BASE-FXFD", 1008 }; 1009 1010 static int 1011 scanphy(Ctlr* ctlr) 1012 { 1013 int i, oui, x; 1014 1015 for(i = 0; i < 32; i++){ 1016 if((oui = miir(ctlr, i, 2)) == -1 || oui == 0 || oui == 0xFFFF) 1017 continue; 1018 oui <<= 6; 1019 x = miir(ctlr, i, 3); 1020 oui |= x>>10; 1021 //print("phy%d: oui %#ux reg1 %#ux\n", i, oui, miir(ctlr, i, 1)); 1022 1023 ctlr->eeprom[6] = i; 1024 if(oui == 0xAA00) 1025 ctlr->eeprom[6] |= 0x07<<8; 1026 else if(oui == 0x80017){ 1027 if(x & 0x01) 1028 ctlr->eeprom[6] |= 0x0A<<8; 1029 else 1030 ctlr->eeprom[6] |= 0x04<<8; 1031 } 1032 return i; 1033 } 1034 return -1; 1035 } 1036 1037 static void 1038 shutdown(Ether* ether) 1039 { 1040 Ctlr *ctlr = ether->ctlr; 1041 1042 print("ether82557 shutting down\n"); 1043 csr32w(ctlr, Port, 0); 1044 delay(1); 1045 csr8w(ctlr, Interrupt, InterruptM); 1046 } 1047 1048 1049 static int 1050 reset(Ether* ether) 1051 { 1052 int anar, anlpar, bmcr, bmsr, i, k, medium, phyaddr, x; 1053 unsigned short sum; 1054 uchar ea[Eaddrlen]; 1055 Ctlr *ctlr; 1056 1057 if(ctlrhead == nil) 1058 i82557pci(); 1059 1060 /* 1061 * Any adapter matches if no ether->port is supplied, 1062 * otherwise the ports must match. 1063 */ 1064 for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){ 1065 if(ctlr->active) 1066 continue; 1067 if(ether->port == 0 || ether->port == ctlr->port){ 1068 ctlr->active = 1; 1069 break; 1070 } 1071 } 1072 if(ctlr == nil) 1073 return -1; 1074 1075 /* 1076 * Initialise the Ctlr structure. 1077 * Perform a software reset after which should ensure busmastering 1078 * is still enabled. The EtherExpress PRO/100B appears to leave 1079 * the PCI configuration alone (see the 'To do' list above) so punt 1080 * for now. 1081 * Load the RUB and CUB registers for linear addressing (0). 1082 */ 1083 ether->ctlr = ctlr; 1084 ether->port = ctlr->port; 1085 ether->irq = ctlr->pcidev->intl; 1086 ether->tbdf = ctlr->pcidev->tbdf; 1087 1088 ilock(&ctlr->rlock); 1089 csr32w(ctlr, Port, 0); 1090 delay(1); 1091 csr8w(ctlr, Interrupt, InterruptM); 1092 iunlock(&ctlr->rlock); 1093 1094 command(ctlr, LoadRUB, 0); 1095 command(ctlr, LoadCUB, 0); 1096 command(ctlr, LoadDCA, PADDR(ctlr->dump)); 1097 1098 /* 1099 * Initialise the receive frame, transmit ring and configuration areas. 1100 */ 1101 ctlr->ncb = Ncb; 1102 ctlrinit(ctlr); 1103 1104 /* 1105 * Read the EEPROM. 1106 * Do a dummy read first to get the size 1107 * and allocate ctlr->eeprom. 1108 */ 1109 hy93c46r(ctlr, 0); 1110 sum = 0; 1111 for(i = 0; i < (1<<ctlr->eepromsz); i++){ 1112 x = hy93c46r(ctlr, i); 1113 ctlr->eeprom[i] = x; 1114 sum += x; 1115 } 1116 if(sum != 0xBABA) 1117 print("#l%d: EEPROM checksum - %#4.4ux\n", ether->ctlrno, sum); 1118 1119 /* 1120 * Eeprom[6] indicates whether there is a PHY and whether 1121 * it's not 10Mb-only, in which case use the given PHY address 1122 * to set any PHY specific options and determine the speed. 1123 * Unfortunately, sometimes the EEPROM is blank except for 1124 * the ether address and checksum; in this case look at the 1125 * controller type and if it's am 82558 or 82559 it has an 1126 * embedded PHY so scan for that. 1127 * If no PHY, assume 82503 (serial) operation. 1128 */ 1129 if((ctlr->eeprom[6] & 0x1F00) && !(ctlr->eeprom[6] & 0x8000)) 1130 phyaddr = ctlr->eeprom[6] & 0x00FF; 1131 else 1132 switch(ctlr->pcidev->rid){ 1133 case 0x01: /* 82557 A-step */ 1134 case 0x02: /* 82557 B-step */ 1135 case 0x03: /* 82557 C-step */ 1136 default: 1137 phyaddr = -1; 1138 break; 1139 case 0x04: /* 82558 A-step */ 1140 case 0x05: /* 82558 B-step */ 1141 case 0x06: /* 82559 A-step */ 1142 case 0x07: /* 82559 B-step */ 1143 case 0x08: /* 82559 C-step */ 1144 case 0x09: /* 82559ER A-step */ 1145 phyaddr = scanphy(ctlr); 1146 break; 1147 } 1148 if(phyaddr >= 0){ 1149 /* 1150 * Resolve the highest common ability of the two 1151 * link partners. In descending order: 1152 * 0x0100 100BASE-TX Full Duplex 1153 * 0x0200 100BASE-T4 1154 * 0x0080 100BASE-TX 1155 * 0x0040 10BASE-T Full Duplex 1156 * 0x0020 10BASE-T 1157 */ 1158 anar = miir(ctlr, phyaddr, 0x04); 1159 anlpar = miir(ctlr, phyaddr, 0x05) & 0x03E0; 1160 anar &= anlpar; 1161 bmcr = 0; 1162 if(anar & 0x380) 1163 bmcr = 0x2000; 1164 if(anar & 0x0140) 1165 bmcr |= 0x0100; 1166 1167 switch((ctlr->eeprom[6]>>8) & 0x001F){ 1168 1169 case 0x04: /* DP83840 */ 1170 case 0x0A: /* DP83840A */ 1171 /* 1172 * The DP83840[A] requires some tweaking for 1173 * reliable operation. 1174 * The manual says bit 10 should be unconditionally 1175 * set although it supposedly only affects full-duplex 1176 * operation (an & 0x0140). 1177 */ 1178 x = miir(ctlr, phyaddr, 0x17) & ~0x0520; 1179 x |= 0x0420; 1180 for(i = 0; i < ether->nopt; i++){ 1181 if(cistrcmp(ether->opt[i], "congestioncontrol")) 1182 continue; 1183 x |= 0x0100; 1184 break; 1185 } 1186 miiw(ctlr, phyaddr, 0x17, x); 1187 1188 /* 1189 * If the link partner can't autonegotiate, determine 1190 * the speed from elsewhere. 1191 */ 1192 if(anlpar == 0){ 1193 miir(ctlr, phyaddr, 0x01); 1194 bmsr = miir(ctlr, phyaddr, 0x01); 1195 x = miir(ctlr, phyaddr, 0x19); 1196 if((bmsr & 0x0004) && !(x & 0x0040)) 1197 bmcr = 0x2000; 1198 } 1199 break; 1200 1201 case 0x07: /* Intel 82555 */ 1202 /* 1203 * Auto-negotiation may fail if the other end is 1204 * a DP83840A and the cable is short. 1205 */ 1206 miir(ctlr, phyaddr, 0x01); 1207 bmsr = miir(ctlr, phyaddr, 0x01); 1208 if((miir(ctlr, phyaddr, 0) & 0x1000) && !(bmsr & 0x0020)){ 1209 miiw(ctlr, phyaddr, 0x1A, 0x2010); 1210 x = miir(ctlr, phyaddr, 0); 1211 miiw(ctlr, phyaddr, 0, 0x0200|x); 1212 for(i = 0; i < 3000; i++){ 1213 delay(1); 1214 if(miir(ctlr, phyaddr, 0x01) & 0x0020) 1215 break; 1216 } 1217 miiw(ctlr, phyaddr, 0x1A, 0x2000); 1218 1219 anar = miir(ctlr, phyaddr, 0x04); 1220 anlpar = miir(ctlr, phyaddr, 0x05) & 0x03E0; 1221 anar &= anlpar; 1222 bmcr = 0; 1223 if(anar & 0x380) 1224 bmcr = 0x2000; 1225 if(anar & 0x0140) 1226 bmcr |= 0x0100; 1227 } 1228 break; 1229 } 1230 1231 /* 1232 * Force speed and duplex if no auto-negotiation. 1233 */ 1234 if(anlpar == 0){ 1235 medium = -1; 1236 for(i = 0; i < ether->nopt; i++){ 1237 for(k = 0; k < nelem(mediatable); k++){ 1238 if(cistrcmp(mediatable[k], ether->opt[i])) 1239 continue; 1240 medium = k; 1241 break; 1242 } 1243 1244 switch(medium){ 1245 default: 1246 break; 1247 1248 case 0x00: /* 10BASE-T */ 1249 case 0x01: /* 10BASE-2 */ 1250 case 0x02: /* 10BASE-5 */ 1251 bmcr &= ~(0x2000|0x0100); 1252 ctlr->configdata[19] &= ~0x40; 1253 break; 1254 1255 case 0x03: /* 100BASE-TX */ 1256 case 0x06: /* 100BASE-T4 */ 1257 case 0x07: /* 100BASE-FX */ 1258 ctlr->configdata[19] &= ~0x40; 1259 bmcr |= 0x2000; 1260 break; 1261 1262 case 0x04: /* 10BASE-TFD */ 1263 bmcr = (bmcr & ~0x2000)|0x0100; 1264 ctlr->configdata[19] |= 0x40; 1265 break; 1266 1267 case 0x05: /* 100BASE-TXFD */ 1268 case 0x08: /* 100BASE-FXFD */ 1269 bmcr |= 0x2000|0x0100; 1270 ctlr->configdata[19] |= 0x40; 1271 break; 1272 } 1273 } 1274 if(medium != -1) 1275 miiw(ctlr, phyaddr, 0x00, bmcr); 1276 } 1277 1278 if(bmcr & 0x2000) 1279 ether->mbps = 100; 1280 1281 ctlr->configdata[8] = 1; 1282 ctlr->configdata[15] &= ~0x80; 1283 } 1284 else{ 1285 ctlr->configdata[8] = 0; 1286 ctlr->configdata[15] |= 0x80; 1287 } 1288 1289 /* 1290 * Workaround for some broken HUB chips when connected at 10Mb/s 1291 * half-duplex. 1292 * This is a band-aid, but as there's no dynamic auto-negotiation 1293 * code at the moment, only deactivate the workaround code in txstart 1294 * if the link is 100Mb/s. 1295 */ 1296 if(ether->mbps != 10) 1297 ctlr->nop = 0; 1298 1299 /* 1300 * Load the chip configuration and start it off. 1301 */ 1302 if(ether->oq == 0) 1303 ether->oq = qopen(64*1024, Qmsg, 0, 0); 1304 configure(ether, 0); 1305 command(ctlr, CUstart, PADDR(&ctlr->cbr->status)); 1306 1307 /* 1308 * Check if the adapter's station address is to be overridden. 1309 * If not, read it from the EEPROM and set in ether->ea prior to loading 1310 * the station address with the Individual Address Setup command. 1311 */ 1312 memset(ea, 0, Eaddrlen); 1313 if(memcmp(ea, ether->ea, Eaddrlen) == 0){ 1314 for(i = 0; i < Eaddrlen/2; i++){ 1315 x = ctlr->eeprom[i]; 1316 ether->ea[2*i] = x; 1317 ether->ea[2*i+1] = x>>8; 1318 } 1319 } 1320 1321 ilock(&ctlr->cblock); 1322 ctlr->action = CbIAS; 1323 txstart(ether); 1324 iunlock(&ctlr->cblock); 1325 1326 /* 1327 * Linkage to the generic ethernet driver. 1328 */ 1329 ether->attach = attach; 1330 ether->transmit = transmit; 1331 ether->interrupt = interrupt; 1332 ether->ifstat = ifstat; 1333 ether->shutdown = shutdown; 1334 1335 ether->promiscuous = promiscuous; 1336 ether->multicast = multicast; 1337 ether->arg = ether; 1338 1339 return 0; 1340 } 1341 1342 void 1343 ether82557link(void) 1344 { 1345 addethercard("i82557", reset); 1346 } 1347