1 /* $OpenBSD: pci.c,v 1.27 2018/07/12 10:15:44 mlarkin Exp $ */ 2 3 /* 4 * Copyright (c) 2015 Mike Larkin <mlarkin@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include <sys/types.h> 20 21 #include <dev/pci/pcireg.h> 22 #include <dev/pci/pcidevs.h> 23 #include <dev/pv/virtioreg.h> 24 #include <machine/vmmvar.h> 25 26 #include <string.h> 27 #include <unistd.h> 28 #include "vmd.h" 29 #include "pci.h" 30 #include "vmm.h" 31 #include "i8259.h" 32 #include "atomicio.h" 33 34 struct pci pci; 35 36 extern char *__progname; 37 38 /* PIC IRQs, assigned to devices in order */ 39 const uint8_t pci_pic_irqs[PCI_MAX_PIC_IRQS] = {3, 5, 6, 7, 9, 10, 11, 12, 40 14, 15}; 41 42 /* 43 * pci_add_bar 44 * 45 * Adds a BAR for the PCI device 'id'. On access, 'barfn' will be 46 * called, and passed 'cookie' as an identifier. 47 * 48 * BARs are fixed size, meaning all I/O BARs requested have the 49 * same size and all MMIO BARs have the same size. 50 * 51 * Parameters: 52 * id: PCI device to add the BAR to (local count, eg if id == 4, 53 * this BAR is to be added to the VM's 5th PCI device) 54 * type: type of the BAR to add (PCI_MAPREG_TYPE_xxx) 55 * barfn: callback function invoked on BAR access 56 * cookie: cookie passed to barfn on access 57 * 58 * Returns 0 if the BAR was added successfully, 1 otherwise. 59 */ 60 int 61 pci_add_bar(uint8_t id, uint32_t type, void *barfn, void *cookie) 62 { 63 uint8_t bar_reg_idx, bar_ct; 64 65 /* Check id */ 66 if (id >= pci.pci_dev_ct) 67 return (1); 68 69 /* Can only add PCI_MAX_BARS BARs to any device */ 70 bar_ct = pci.pci_devices[id].pd_bar_ct; 71 if (bar_ct >= PCI_MAX_BARS) 72 return (1); 73 74 /* Compute BAR address and add */ 75 bar_reg_idx = (PCI_MAPREG_START + (bar_ct * 4)) / 4; 76 if (type == PCI_MAPREG_TYPE_MEM) { 77 if (pci.pci_next_mmio_bar >= VMM_PCI_MMIO_BAR_END) 78 return (1); 79 80 pci.pci_devices[id].pd_cfg_space[bar_reg_idx] = 81 PCI_MAPREG_MEM_ADDR(pci.pci_next_mmio_bar); 82 pci.pci_next_mmio_bar += VMM_PCI_MMIO_BAR_SIZE; 83 pci.pci_devices[id].pd_barfunc[bar_ct] = barfn; 84 pci.pci_devices[id].pd_bar_cookie[bar_ct] = cookie; 85 pci.pci_devices[id].pd_bartype[bar_ct] = PCI_BAR_TYPE_MMIO; 86 pci.pci_devices[id].pd_barsize[bar_ct] = VMM_PCI_MMIO_BAR_SIZE; 87 pci.pci_devices[id].pd_bar_ct++; 88 } else if (type == PCI_MAPREG_TYPE_IO) { 89 if (pci.pci_next_io_bar >= VMM_PCI_IO_BAR_END) 90 return (1); 91 92 pci.pci_devices[id].pd_cfg_space[bar_reg_idx] = 93 PCI_MAPREG_IO_ADDR(pci.pci_next_io_bar) | 94 PCI_MAPREG_TYPE_IO; 95 pci.pci_next_io_bar += VMM_PCI_IO_BAR_SIZE; 96 pci.pci_devices[id].pd_barfunc[bar_ct] = barfn; 97 pci.pci_devices[id].pd_bar_cookie[bar_ct] = cookie; 98 DPRINTF("%s: adding pci bar cookie for dev %d bar %d = %p", 99 __progname, id, bar_ct, cookie); 100 pci.pci_devices[id].pd_bartype[bar_ct] = PCI_BAR_TYPE_IO; 101 pci.pci_devices[id].pd_barsize[bar_ct] = VMM_PCI_IO_BAR_SIZE; 102 pci.pci_devices[id].pd_bar_ct++; 103 } 104 105 return (0); 106 } 107 108 int 109 pci_set_bar_fn(uint8_t id, uint8_t bar_ct, void *barfn, void *cookie) 110 { 111 /* Check id */ 112 if (id >= pci.pci_dev_ct) 113 return (1); 114 115 if (bar_ct >= PCI_MAX_BARS) 116 return (1); 117 118 pci.pci_devices[id].pd_barfunc[bar_ct] = barfn; 119 pci.pci_devices[id].pd_bar_cookie[bar_ct] = cookie; 120 121 return (0); 122 } 123 124 /* 125 * pci_get_dev_irq 126 * 127 * Returns the IRQ for the specified PCI device 128 * 129 * Parameters: 130 * id: PCI device id to return IRQ for 131 * 132 * Return values: 133 * The IRQ for the device, or 0xff if no device IRQ assigned 134 */ 135 uint8_t 136 pci_get_dev_irq(uint8_t id) 137 { 138 if (pci.pci_devices[id].pd_int) 139 return pci.pci_devices[id].pd_irq; 140 else 141 return 0xFF; 142 } 143 144 /* 145 * pci_add_device 146 * 147 * Adds a PCI device to the guest VM defined by the supplied parameters. 148 * 149 * Parameters: 150 * id: the new PCI device ID (0 .. PCI_CONFIG_MAX_DEV) 151 * vid: PCI VID of the new device 152 * pid: PCI PID of the new device 153 * class: PCI 'class' of the new device 154 * subclass: PCI 'subclass' of the new device 155 * subsys_vid: subsystem VID of the new device 156 * subsys_id: subsystem ID of the new device 157 * irq_needed: 1 if an IRQ should be assigned to this PCI device, 0 otherwise 158 * csfunc: PCI config space callback function when the guest VM accesses 159 * CS of this PCI device 160 * 161 * Return values: 162 * 0: the PCI device was added successfully. The PCI device ID is in 'id'. 163 * 1: the PCI device addition failed. 164 */ 165 int 166 pci_add_device(uint8_t *id, uint16_t vid, uint16_t pid, uint8_t class, 167 uint8_t subclass, uint16_t subsys_vid, uint16_t subsys_id, 168 uint8_t irq_needed, pci_cs_fn_t csfunc) 169 { 170 /* Exceeded max devices? */ 171 if (pci.pci_dev_ct >= PCI_CONFIG_MAX_DEV) 172 return (1); 173 174 /* Exceeded max IRQs? */ 175 /* XXX we could share IRQs ... */ 176 if (pci.pci_next_pic_irq >= PCI_MAX_PIC_IRQS && irq_needed) 177 return (1); 178 179 *id = pci.pci_dev_ct; 180 181 pci.pci_devices[*id].pd_vid = vid; 182 pci.pci_devices[*id].pd_did = pid; 183 pci.pci_devices[*id].pd_class = class; 184 pci.pci_devices[*id].pd_subclass = subclass; 185 pci.pci_devices[*id].pd_subsys_vid = subsys_vid; 186 pci.pci_devices[*id].pd_subsys_id = subsys_id; 187 188 pci.pci_devices[*id].pd_csfunc = csfunc; 189 190 if (irq_needed) { 191 pci.pci_devices[*id].pd_irq = 192 pci_pic_irqs[pci.pci_next_pic_irq]; 193 pci.pci_devices[*id].pd_int = 1; 194 pci.pci_next_pic_irq++; 195 DPRINTF("assigned irq %d to pci dev %d", 196 pci.pci_devices[*id].pd_irq, *id); 197 pic_set_elcr(pci.pci_devices[*id].pd_irq, 1); 198 } 199 200 pci.pci_dev_ct ++; 201 202 return (0); 203 } 204 205 /* 206 * pci_init 207 * 208 * Initializes the PCI subsystem for the VM by adding a PCI host bridge 209 * as the first PCI device. 210 */ 211 void 212 pci_init(void) 213 { 214 uint8_t id; 215 216 memset(&pci, 0, sizeof(pci)); 217 pci.pci_next_mmio_bar = VMM_PCI_MMIO_BAR_BASE; 218 pci.pci_next_io_bar = VMM_PCI_IO_BAR_BASE; 219 220 if (pci_add_device(&id, PCI_VENDOR_OPENBSD, PCI_PRODUCT_OPENBSD_PCHB, 221 PCI_CLASS_BRIDGE, PCI_SUBCLASS_BRIDGE_HOST, 222 PCI_VENDOR_OPENBSD, 0, 0, NULL)) { 223 log_warnx("%s: can't add PCI host bridge", __progname); 224 return; 225 } 226 } 227 228 void 229 pci_handle_address_reg(struct vm_run_params *vrp) 230 { 231 struct vm_exit *vei = vrp->vrp_exit; 232 233 /* 234 * vei_dir == VEI_DIR_OUT : out instruction 235 * 236 * The guest wrote to the address register. 237 */ 238 if (vei->vei.vei_dir == VEI_DIR_OUT) { 239 get_input_data(vei, &pci.pci_addr_reg); 240 } else { 241 /* 242 * vei_dir == VEI_DIR_IN : in instruction 243 * 244 * The guest read the address register 245 */ 246 set_return_data(vei, pci.pci_addr_reg); 247 } 248 } 249 250 uint8_t 251 pci_handle_io(struct vm_run_params *vrp) 252 { 253 int i, j, k, l; 254 uint16_t reg, b_hi, b_lo; 255 pci_iobar_fn_t fn; 256 struct vm_exit *vei = vrp->vrp_exit; 257 uint8_t intr, dir; 258 259 k = -1; 260 l = -1; 261 reg = vei->vei.vei_port; 262 dir = vei->vei.vei_dir; 263 intr = 0xFF; 264 265 for (i = 0 ; i < pci.pci_dev_ct ; i++) { 266 for (j = 0 ; j < pci.pci_devices[i].pd_bar_ct; j++) { 267 b_lo = PCI_MAPREG_IO_ADDR(pci.pci_devices[i].pd_bar[j]); 268 b_hi = b_lo + VMM_PCI_IO_BAR_SIZE; 269 if (reg >= b_lo && reg < b_hi) { 270 if (pci.pci_devices[i].pd_barfunc[j]) { 271 k = j; 272 l = i; 273 } 274 } 275 } 276 } 277 278 if (k >= 0 && l >= 0) { 279 fn = (pci_iobar_fn_t)pci.pci_devices[l].pd_barfunc[k]; 280 if (fn(vei->vei.vei_dir, reg - 281 PCI_MAPREG_IO_ADDR(pci.pci_devices[l].pd_bar[k]), 282 &vei->vei.vei_data, &intr, 283 pci.pci_devices[l].pd_bar_cookie[k], 284 vei->vei.vei_size)) { 285 log_warnx("%s: pci i/o access function failed", 286 __progname); 287 } 288 } else { 289 log_warnx("%s: no pci i/o function for reg 0x%llx", 290 __progname, (uint64_t)reg); 291 /* Reads from undefined ports return 0xFF */ 292 if (dir == VEI_DIR_IN) 293 set_return_data(vei, 0xFFFFFFFF); 294 } 295 296 if (intr != 0xFF) { 297 intr = pci.pci_devices[l].pd_irq; 298 } 299 300 return (intr); 301 } 302 303 void 304 pci_handle_data_reg(struct vm_run_params *vrp) 305 { 306 struct vm_exit *vei = vrp->vrp_exit; 307 uint8_t b, d, f, o, baridx, ofs, sz; 308 int ret; 309 pci_cs_fn_t csfunc; 310 311 /* abort if the address register is wack */ 312 if (!(pci.pci_addr_reg & PCI_MODE1_ENABLE)) { 313 /* if read, return FFs */ 314 if (vei->vei.vei_dir == VEI_DIR_IN) 315 set_return_data(vei, 0xFFFFFFFF); 316 log_warnx("invalid address register during pci read: " 317 "0x%llx", (uint64_t)pci.pci_addr_reg); 318 return; 319 } 320 321 /* I/Os to 0xCFC..0xCFF are permitted */ 322 ofs = vei->vei.vei_port - 0xCFC; 323 sz = vei->vei.vei_size; 324 325 b = (pci.pci_addr_reg >> 16) & 0xff; 326 d = (pci.pci_addr_reg >> 11) & 0x1f; 327 f = (pci.pci_addr_reg >> 8) & 0x7; 328 o = (pci.pci_addr_reg & 0xfc); 329 330 csfunc = pci.pci_devices[d].pd_csfunc; 331 if (csfunc != NULL) { 332 ret = csfunc(vei->vei.vei_dir, (o / 4), &vei->vei.vei_data); 333 if (ret) 334 log_warnx("cfg space access function failed for " 335 "pci device %d", d); 336 return; 337 } 338 339 /* No config space function, fallback to default simple r/w impl. */ 340 341 o += ofs; 342 343 /* 344 * vei_dir == VEI_DIR_OUT : out instruction 345 * 346 * The guest wrote to the config space location denoted by the current 347 * value in the address register. 348 */ 349 if (vei->vei.vei_dir == VEI_DIR_OUT) { 350 if ((o >= 0x10 && o <= 0x24) && 351 vei->vei.vei_data == 0xffffffff) { 352 /* 353 * Compute BAR index: 354 * o = 0x10 -> baridx = 0 355 * o = 0x14 -> baridx = 1 356 * o = 0x18 -> baridx = 2 357 * o = 0x1c -> baridx = 3 358 * o = 0x20 -> baridx = 4 359 * o = 0x24 -> baridx = 5 360 */ 361 baridx = (o / 4) - 4; 362 if (baridx < pci.pci_devices[d].pd_bar_ct) 363 vei->vei.vei_data = 0xfffff000; 364 else 365 vei->vei.vei_data = 0; 366 } 367 368 /* IOBAR registers must have bit 0 set */ 369 if (o >= 0x10 && o <= 0x24) { 370 baridx = (o / 4) - 4; 371 if (baridx < pci.pci_devices[d].pd_bar_ct && 372 pci.pci_devices[d].pd_bartype[baridx] == 373 PCI_BAR_TYPE_IO) 374 vei->vei.vei_data |= 1; 375 } 376 377 /* 378 * Discard writes to "option rom base address" as none of our 379 * emulated devices have PCI option roms. Accept any other 380 * writes and copy data to config space registers. 381 */ 382 if (o != PCI_EXROMADDR_0) 383 get_input_data(vei, 384 &pci.pci_devices[d].pd_cfg_space[o / 4]); 385 } else { 386 /* 387 * vei_dir == VEI_DIR_IN : in instruction 388 * 389 * The guest read from the config space location determined by 390 * the current value in the address register. 391 */ 392 if (d > pci.pci_dev_ct || b > 0 || f > 0) 393 set_return_data(vei, 0xFFFFFFFF); 394 else { 395 switch (sz) { 396 case 4: 397 set_return_data(vei, 398 pci.pci_devices[d].pd_cfg_space[o / 4]); 399 break; 400 case 2: 401 if (ofs == 0) 402 set_return_data(vei, pci.pci_devices[d]. 403 pd_cfg_space[o / 4]); 404 else 405 set_return_data(vei, pci.pci_devices[d]. 406 pd_cfg_space[o / 4] >> 16); 407 break; 408 case 1: 409 set_return_data(vei, pci.pci_devices[d]. 410 pd_cfg_space[o / 4] >> (ofs * 8)); 411 break; 412 } 413 } 414 } 415 } 416 417 int 418 pci_dump(int fd) 419 { 420 log_debug("%s: sending pci", __func__); 421 if (atomicio(vwrite, fd, &pci, sizeof(pci)) != sizeof(pci)) { 422 log_warnx("%s: error writing pci to fd", __func__); 423 return (-1); 424 } 425 return (0); 426 } 427 428 int 429 pci_restore(int fd) 430 { 431 log_debug("%s: receiving pci", __func__); 432 if (atomicio(read, fd, &pci, sizeof(pci)) != sizeof(pci)) { 433 log_warnx("%s: error reading pci from fd", __func__); 434 return (-1); 435 } 436 return (0); 437 } 438