1 /* $OpenBSD: ohci.c,v 1.104 2011/07/03 15:47:17 matthew Exp $ */ 2 /* $NetBSD: ohci.c,v 1.139 2003/02/22 05:24:16 tsutsui Exp $ */ 3 /* $FreeBSD: src/sys/dev/usb/ohci.c,v 1.22 1999/11/17 22:33:40 n_hibma Exp $ */ 4 5 /* 6 * Copyright (c) 1998 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by Lennart Augustsson (lennart@augustsson.net) at 11 * Carlstedt Research & Technology. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * USB Open Host Controller driver. 37 * 38 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 39 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/device.h> 47 #include <sys/selinfo.h> 48 #include <sys/proc.h> 49 #include <sys/queue.h> 50 51 #include <machine/bus.h> 52 #include <machine/endian.h> 53 54 #include <dev/usb/usb.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdivar.h> 57 #include <dev/usb/usb_mem.h> 58 #include <dev/usb/usb_quirks.h> 59 60 #include <dev/usb/ohcireg.h> 61 #include <dev/usb/ohcivar.h> 62 63 struct cfdriver ohci_cd = { 64 NULL, "ohci", DV_DULL 65 }; 66 67 #ifdef OHCI_DEBUG 68 #define DPRINTF(x) do { if (ohcidebug) printf x; } while (0) 69 #define DPRINTFN(n,x) do { if (ohcidebug>(n)) printf x; } while (0) 70 int ohcidebug = 0; 71 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 72 #else 73 #define DPRINTF(x) 74 #define DPRINTFN(n,x) 75 #endif 76 77 #define mstohz(ms) ((ms) * hz / 1000) 78 79 /* 80 * The OHCI controller is little endian, so on big endian machines 81 * the data stored in memory needs to be swapped. 82 */ 83 84 struct ohci_pipe; 85 86 ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 87 void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 88 89 ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 90 void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 91 92 ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 93 void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 94 95 #if 0 96 void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 97 ohci_soft_td_t *); 98 #endif 99 usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 100 ohci_softc_t *, u_int, int, usbd_xfer_handle, 101 ohci_soft_td_t *, ohci_soft_td_t **); 102 103 void ohci_shutdown(void *v); 104 usbd_status ohci_open(usbd_pipe_handle); 105 void ohci_poll(struct usbd_bus *); 106 void ohci_softintr(void *); 107 void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle); 108 void ohci_add_done(ohci_softc_t *, ohci_physaddr_t); 109 void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle); 110 111 usbd_status ohci_device_request(usbd_xfer_handle xfer); 112 void ohci_add_ed(ohci_soft_ed_t *, ohci_soft_ed_t *); 113 void ohci_rem_ed(ohci_soft_ed_t *, ohci_soft_ed_t *); 114 void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 115 void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 116 ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 117 void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 118 void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 119 ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 120 121 usbd_status ohci_setup_isoc(usbd_pipe_handle pipe); 122 void ohci_device_isoc_enter(usbd_xfer_handle); 123 124 usbd_status ohci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 125 void ohci_freem(struct usbd_bus *, usb_dma_t *); 126 127 usbd_xfer_handle ohci_allocx(struct usbd_bus *); 128 void ohci_freex(struct usbd_bus *, usbd_xfer_handle); 129 130 usbd_status ohci_root_ctrl_transfer(usbd_xfer_handle); 131 usbd_status ohci_root_ctrl_start(usbd_xfer_handle); 132 void ohci_root_ctrl_abort(usbd_xfer_handle); 133 void ohci_root_ctrl_close(usbd_pipe_handle); 134 void ohci_root_ctrl_done(usbd_xfer_handle); 135 136 usbd_status ohci_root_intr_transfer(usbd_xfer_handle); 137 usbd_status ohci_root_intr_start(usbd_xfer_handle); 138 void ohci_root_intr_abort(usbd_xfer_handle); 139 void ohci_root_intr_close(usbd_pipe_handle); 140 void ohci_root_intr_done(usbd_xfer_handle); 141 142 usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle); 143 usbd_status ohci_device_ctrl_start(usbd_xfer_handle); 144 void ohci_device_ctrl_abort(usbd_xfer_handle); 145 void ohci_device_ctrl_close(usbd_pipe_handle); 146 void ohci_device_ctrl_done(usbd_xfer_handle); 147 148 usbd_status ohci_device_bulk_transfer(usbd_xfer_handle); 149 usbd_status ohci_device_bulk_start(usbd_xfer_handle); 150 void ohci_device_bulk_abort(usbd_xfer_handle); 151 void ohci_device_bulk_close(usbd_pipe_handle); 152 void ohci_device_bulk_done(usbd_xfer_handle); 153 154 usbd_status ohci_device_intr_transfer(usbd_xfer_handle); 155 usbd_status ohci_device_intr_start(usbd_xfer_handle); 156 void ohci_device_intr_abort(usbd_xfer_handle); 157 void ohci_device_intr_close(usbd_pipe_handle); 158 void ohci_device_intr_done(usbd_xfer_handle); 159 160 usbd_status ohci_device_isoc_transfer(usbd_xfer_handle); 161 usbd_status ohci_device_isoc_start(usbd_xfer_handle); 162 void ohci_device_isoc_abort(usbd_xfer_handle); 163 void ohci_device_isoc_close(usbd_pipe_handle); 164 void ohci_device_isoc_done(usbd_xfer_handle); 165 166 usbd_status ohci_device_setintr(ohci_softc_t *sc, 167 struct ohci_pipe *pipe, int ival); 168 169 int ohci_str(usb_string_descriptor_t *, int, const char *); 170 171 void ohci_timeout(void *); 172 void ohci_timeout_task(void *); 173 void ohci_rhsc_able(ohci_softc_t *, int); 174 void ohci_rhsc_enable(void *); 175 176 void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *); 177 void ohci_abort_xfer(usbd_xfer_handle, usbd_status); 178 179 void ohci_device_clear_toggle(usbd_pipe_handle pipe); 180 void ohci_noop(usbd_pipe_handle pipe); 181 182 #ifdef OHCI_DEBUG 183 void ohci_dumpregs(ohci_softc_t *); 184 void ohci_dump_tds(ohci_soft_td_t *); 185 void ohci_dump_td(ohci_soft_td_t *); 186 void ohci_dump_ed(ohci_soft_ed_t *); 187 void ohci_dump_itd(ohci_soft_itd_t *); 188 void ohci_dump_itds(ohci_soft_itd_t *); 189 #endif 190 191 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 192 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 193 #define OWRITE1(sc, r, x) \ 194 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 195 #define OWRITE2(sc, r, x) \ 196 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 197 #define OWRITE4(sc, r, x) \ 198 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 199 200 static __inline u_int8_t 201 OREAD1(ohci_softc_t *sc, bus_size_t r) 202 { 203 OBARR(sc); 204 return bus_space_read_1(sc->iot, sc->ioh, r); 205 } 206 207 static __inline u_int16_t 208 OREAD2(ohci_softc_t *sc, bus_size_t r) 209 { 210 OBARR(sc); 211 return bus_space_read_2(sc->iot, sc->ioh, r); 212 } 213 214 static __inline u_int32_t 215 OREAD4(ohci_softc_t *sc, bus_size_t r) 216 { 217 OBARR(sc); 218 return bus_space_read_4(sc->iot, sc->ioh, r); 219 } 220 221 /* Reverse the bits in a value 0 .. 31 */ 222 u_int8_t revbits[OHCI_NO_INTRS] = 223 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 224 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 225 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 226 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 227 228 struct ohci_pipe { 229 struct usbd_pipe pipe; 230 ohci_soft_ed_t *sed; 231 union { 232 ohci_soft_td_t *td; 233 ohci_soft_itd_t *itd; 234 } tail; 235 /* Info needed for different pipe kinds. */ 236 union { 237 /* Control pipe */ 238 struct { 239 usb_dma_t reqdma; 240 u_int length; 241 ohci_soft_td_t *setup, *data, *stat; 242 } ctl; 243 /* Interrupt pipe */ 244 struct { 245 int nslots; 246 int pos; 247 } intr; 248 /* Bulk pipe */ 249 struct { 250 u_int length; 251 int isread; 252 } bulk; 253 /* Iso pipe */ 254 struct iso { 255 int next, inuse; 256 } iso; 257 } u; 258 }; 259 260 #define OHCI_INTR_ENDPT 1 261 262 struct usbd_bus_methods ohci_bus_methods = { 263 ohci_open, 264 ohci_softintr, 265 ohci_poll, 266 ohci_allocm, 267 ohci_freem, 268 ohci_allocx, 269 ohci_freex, 270 }; 271 272 struct usbd_pipe_methods ohci_root_ctrl_methods = { 273 ohci_root_ctrl_transfer, 274 ohci_root_ctrl_start, 275 ohci_root_ctrl_abort, 276 ohci_root_ctrl_close, 277 ohci_noop, 278 ohci_root_ctrl_done, 279 }; 280 281 struct usbd_pipe_methods ohci_root_intr_methods = { 282 ohci_root_intr_transfer, 283 ohci_root_intr_start, 284 ohci_root_intr_abort, 285 ohci_root_intr_close, 286 ohci_noop, 287 ohci_root_intr_done, 288 }; 289 290 struct usbd_pipe_methods ohci_device_ctrl_methods = { 291 ohci_device_ctrl_transfer, 292 ohci_device_ctrl_start, 293 ohci_device_ctrl_abort, 294 ohci_device_ctrl_close, 295 ohci_noop, 296 ohci_device_ctrl_done, 297 }; 298 299 struct usbd_pipe_methods ohci_device_intr_methods = { 300 ohci_device_intr_transfer, 301 ohci_device_intr_start, 302 ohci_device_intr_abort, 303 ohci_device_intr_close, 304 ohci_device_clear_toggle, 305 ohci_device_intr_done, 306 }; 307 308 struct usbd_pipe_methods ohci_device_bulk_methods = { 309 ohci_device_bulk_transfer, 310 ohci_device_bulk_start, 311 ohci_device_bulk_abort, 312 ohci_device_bulk_close, 313 ohci_device_clear_toggle, 314 ohci_device_bulk_done, 315 }; 316 317 struct usbd_pipe_methods ohci_device_isoc_methods = { 318 ohci_device_isoc_transfer, 319 ohci_device_isoc_start, 320 ohci_device_isoc_abort, 321 ohci_device_isoc_close, 322 ohci_noop, 323 ohci_device_isoc_done, 324 }; 325 326 int 327 ohci_activate(struct device *self, int act) 328 { 329 struct ohci_softc *sc = (struct ohci_softc *)self; 330 u_int32_t reg; 331 int rv = 0; 332 333 switch (act) { 334 case DVACT_SUSPEND: 335 sc->sc_bus.use_polling++; 336 reg = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 337 if (sc->sc_control == 0) { 338 /* 339 * Preserve register values, in case that APM BIOS 340 * does not recover them. 341 */ 342 sc->sc_control = reg; 343 sc->sc_intre = OREAD4(sc, OHCI_INTERRUPT_ENABLE); 344 sc->sc_ival = OHCI_GET_IVAL(OREAD4(sc, 345 OHCI_FM_INTERVAL)); 346 } 347 reg |= OHCI_HCFS_SUSPEND; 348 OWRITE4(sc, OHCI_CONTROL, reg); 349 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 350 sc->sc_bus.use_polling--; 351 break; 352 case DVACT_RESUME: 353 sc->sc_bus.use_polling++; 354 355 /* Some broken BIOSes do not recover these values */ 356 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 357 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 358 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 359 if (sc->sc_intre) 360 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, 361 sc->sc_intre & (OHCI_ALL_INTRS | OHCI_MIE)); 362 if (sc->sc_control) 363 reg = sc->sc_control; 364 else 365 reg = OREAD4(sc, OHCI_CONTROL); 366 reg |= OHCI_HCFS_RESUME; 367 OWRITE4(sc, OHCI_CONTROL, reg); 368 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 369 reg = (reg & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 370 OWRITE4(sc, OHCI_CONTROL, reg); 371 372 reg = (OREAD4(sc, OHCI_FM_REMAINING) & OHCI_FIT) ^ OHCI_FIT; 373 reg |= OHCI_FSMPS(sc->sc_ival) | sc->sc_ival; 374 OWRITE4(sc, OHCI_FM_INTERVAL, reg); 375 OWRITE4(sc, OHCI_PERIODIC_START, OHCI_PERIODIC(sc->sc_ival)); 376 377 /* Fiddle the No OverCurrent Protection to avoid a chip bug */ 378 reg = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 379 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, reg | OHCI_NOCP); 380 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 381 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 382 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, reg); 383 384 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 385 sc->sc_control = sc->sc_intre = sc->sc_ival = 0; 386 sc->sc_bus.use_polling--; 387 break; 388 case DVACT_DEACTIVATE: 389 if (sc->sc_child != NULL) 390 rv = config_deactivate(sc->sc_child); 391 sc->sc_bus.dying = 1; 392 break; 393 } 394 return (rv); 395 } 396 397 int 398 ohci_detach(struct ohci_softc *sc, int flags) 399 { 400 int rv = 0; 401 402 if (sc->sc_child != NULL) 403 rv = config_detach(sc->sc_child, flags); 404 405 if (rv != 0) 406 return (rv); 407 408 timeout_del(&sc->sc_tmo_rhsc); 409 410 if (sc->sc_shutdownhook != NULL) 411 shutdownhook_disestablish(sc->sc_shutdownhook); 412 413 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 414 415 /* free data structures XXX */ 416 417 return (rv); 418 } 419 420 ohci_soft_ed_t * 421 ohci_alloc_sed(ohci_softc_t *sc) 422 { 423 ohci_soft_ed_t *sed; 424 usbd_status err; 425 int i, offs; 426 usb_dma_t dma; 427 428 if (sc->sc_freeeds == NULL) { 429 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 430 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 431 OHCI_ED_ALIGN, &dma); 432 if (err) 433 return (0); 434 for(i = 0; i < OHCI_SED_CHUNK; i++) { 435 offs = i * OHCI_SED_SIZE; 436 sed = KERNADDR(&dma, offs); 437 sed->physaddr = DMAADDR(&dma, offs); 438 sed->next = sc->sc_freeeds; 439 sc->sc_freeeds = sed; 440 } 441 } 442 sed = sc->sc_freeeds; 443 sc->sc_freeeds = sed->next; 444 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 445 sed->next = 0; 446 return (sed); 447 } 448 449 void 450 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 451 { 452 sed->next = sc->sc_freeeds; 453 sc->sc_freeeds = sed; 454 } 455 456 ohci_soft_td_t * 457 ohci_alloc_std(ohci_softc_t *sc) 458 { 459 ohci_soft_td_t *std; 460 usbd_status err; 461 int i, offs; 462 usb_dma_t dma; 463 int s; 464 465 if (sc->sc_freetds == NULL) { 466 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 467 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 468 OHCI_TD_ALIGN, &dma); 469 if (err) 470 return (NULL); 471 s = splusb(); 472 for(i = 0; i < OHCI_STD_CHUNK; i++) { 473 offs = i * OHCI_STD_SIZE; 474 std = KERNADDR(&dma, offs); 475 std->physaddr = DMAADDR(&dma, offs); 476 std->nexttd = sc->sc_freetds; 477 sc->sc_freetds = std; 478 } 479 splx(s); 480 } 481 482 s = splusb(); 483 std = sc->sc_freetds; 484 sc->sc_freetds = std->nexttd; 485 memset(&std->td, 0, sizeof(ohci_td_t)); 486 std->nexttd = NULL; 487 std->xfer = NULL; 488 ohci_hash_add_td(sc, std); 489 splx(s); 490 491 return (std); 492 } 493 494 void 495 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 496 { 497 int s; 498 499 s = splusb(); 500 ohci_hash_rem_td(sc, std); 501 std->nexttd = sc->sc_freetds; 502 sc->sc_freetds = std; 503 splx(s); 504 } 505 506 usbd_status 507 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 508 u_int alen, int rd, usbd_xfer_handle xfer, 509 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 510 { 511 ohci_soft_td_t *next, *cur; 512 ohci_physaddr_t dataphys, dataphysend; 513 u_int32_t tdflags; 514 u_int len, curlen; 515 usb_dma_t *dma = &xfer->dmabuf; 516 u_int16_t flags = xfer->flags; 517 518 DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%u\n", alen)); 519 520 len = alen; 521 cur = sp; 522 dataphys = DMAADDR(dma, 0); 523 dataphysend = OHCI_PAGE(dataphys + len - 1); 524 tdflags = htole32( 525 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 526 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 527 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 528 529 for (;;) { 530 next = ohci_alloc_std(sc); 531 if (next == NULL) 532 goto nomem; 533 534 /* The OHCI hardware can handle at most one page crossing. */ 535 if (OHCI_PAGE(dataphys) == dataphysend || 536 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 537 /* we can handle it in this TD */ 538 curlen = len; 539 } else { 540 /* must use multiple TDs, fill as much as possible. */ 541 curlen = 2 * OHCI_PAGE_SIZE - 542 (dataphys & (OHCI_PAGE_SIZE-1)); 543 /* the length must be a multiple of the max size */ 544 curlen -= curlen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize); 545 #ifdef DIAGNOSTIC 546 if (curlen == 0) 547 panic("ohci_alloc_std: curlen == 0"); 548 #endif 549 } 550 DPRINTFN(4,("ohci_alloc_std_chain: dataphys=0x%08x " 551 "dataphysend=0x%08x len=%u curlen=%u\n", 552 dataphys, dataphysend, 553 len, curlen)); 554 len -= curlen; 555 556 cur->td.td_flags = tdflags; 557 cur->td.td_cbp = htole32(dataphys); 558 cur->nexttd = next; 559 cur->td.td_nexttd = htole32(next->physaddr); 560 cur->td.td_be = htole32(dataphys + curlen - 1); 561 cur->len = curlen; 562 cur->flags = OHCI_ADD_LEN; 563 cur->xfer = xfer; 564 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n", 565 dataphys, dataphys + curlen - 1)); 566 if (len == 0) 567 break; 568 DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n")); 569 dataphys += curlen; 570 cur = next; 571 } 572 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 573 alen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize) == 0) { 574 /* Force a 0 length transfer at the end. */ 575 576 cur = next; 577 next = ohci_alloc_std(sc); 578 if (next == NULL) 579 goto nomem; 580 581 cur->td.td_flags = tdflags; 582 cur->td.td_cbp = 0; /* indicate 0 length packet */ 583 cur->nexttd = next; 584 cur->td.td_nexttd = htole32(next->physaddr); 585 cur->td.td_be = ~0; 586 cur->len = 0; 587 cur->flags = 0; 588 cur->xfer = xfer; 589 DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n")); 590 } 591 *ep = cur; 592 593 return (USBD_NORMAL_COMPLETION); 594 595 nomem: 596 /* XXX free chain */ 597 return (USBD_NOMEM); 598 } 599 600 #if 0 601 void 602 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 603 ohci_soft_td_t *stdend) 604 { 605 ohci_soft_td_t *p; 606 607 for (; std != stdend; std = p) { 608 p = std->nexttd; 609 ohci_free_std(sc, std); 610 } 611 } 612 #endif 613 614 ohci_soft_itd_t * 615 ohci_alloc_sitd(ohci_softc_t *sc) 616 { 617 ohci_soft_itd_t *sitd; 618 usbd_status err; 619 int i, s, offs; 620 usb_dma_t dma; 621 622 if (sc->sc_freeitds == NULL) { 623 DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n")); 624 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 625 OHCI_ITD_ALIGN, &dma); 626 if (err) 627 return (NULL); 628 s = splusb(); 629 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 630 offs = i * OHCI_SITD_SIZE; 631 sitd = KERNADDR(&dma, offs); 632 sitd->physaddr = DMAADDR(&dma, offs); 633 sitd->nextitd = sc->sc_freeitds; 634 sc->sc_freeitds = sitd; 635 } 636 splx(s); 637 } 638 639 s = splusb(); 640 sitd = sc->sc_freeitds; 641 sc->sc_freeitds = sitd->nextitd; 642 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 643 sitd->nextitd = NULL; 644 sitd->xfer = NULL; 645 ohci_hash_add_itd(sc, sitd); 646 splx(s); 647 648 #ifdef DIAGNOSTIC 649 sitd->isdone = 0; 650 #endif 651 652 return (sitd); 653 } 654 655 void 656 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 657 { 658 int s; 659 660 DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd)); 661 662 #ifdef DIAGNOSTIC 663 if (!sitd->isdone) { 664 panic("ohci_free_sitd: sitd=%p not done", sitd); 665 return; 666 } 667 /* Warn double free */ 668 sitd->isdone = 0; 669 #endif 670 671 s = splusb(); 672 ohci_hash_rem_itd(sc, sitd); 673 sitd->nextitd = sc->sc_freeitds; 674 sc->sc_freeitds = sitd; 675 splx(s); 676 } 677 678 usbd_status 679 ohci_checkrev(ohci_softc_t *sc) 680 { 681 u_int32_t rev; 682 683 printf(","); 684 rev = OREAD4(sc, OHCI_REVISION); 685 printf(" version %d.%d%s\n", OHCI_REV_HI(rev), OHCI_REV_LO(rev), 686 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 687 688 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 689 printf("%s: unsupported OHCI revision\n", 690 sc->sc_bus.bdev.dv_xname); 691 sc->sc_bus.usbrev = USBREV_UNKNOWN; 692 return (USBD_INVAL); 693 } 694 sc->sc_bus.usbrev = USBREV_1_0; 695 696 return (USBD_NORMAL_COMPLETION); 697 } 698 699 usbd_status 700 ohci_handover(ohci_softc_t *sc) 701 { 702 u_int32_t s, ctl; 703 int i; 704 705 ctl = OREAD4(sc, OHCI_CONTROL); 706 if (ctl & OHCI_IR) { 707 /* SMM active, request change */ 708 DPRINTF(("ohci_handover: SMM active, request owner change\n")); 709 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 710 (OHCI_OC | OHCI_MIE)) 711 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 712 s = OREAD4(sc, OHCI_COMMAND_STATUS); 713 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 714 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 715 usb_delay_ms(&sc->sc_bus, 1); 716 ctl = OREAD4(sc, OHCI_CONTROL); 717 } 718 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 719 if (ctl & OHCI_IR) { 720 printf("%s: SMM does not respond, will reset\n", 721 sc->sc_bus.bdev.dv_xname); 722 } 723 } 724 725 return (USBD_NORMAL_COMPLETION); 726 } 727 728 usbd_status 729 ohci_init(ohci_softc_t *sc) 730 { 731 ohci_soft_ed_t *sed, *psed; 732 usbd_status err; 733 int i; 734 u_int32_t ctl, rwc, ival, hcr, fm, per, desca, descb; 735 736 DPRINTF(("ohci_init: start\n")); 737 738 for (i = 0; i < OHCI_HASH_SIZE; i++) 739 LIST_INIT(&sc->sc_hash_tds[i]); 740 for (i = 0; i < OHCI_HASH_SIZE; i++) 741 LIST_INIT(&sc->sc_hash_itds[i]); 742 743 SIMPLEQ_INIT(&sc->sc_free_xfers); 744 745 /* XXX determine alignment by R/W */ 746 /* Allocate the HCCA area. */ 747 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 748 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 749 if (err) 750 return (err); 751 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 752 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 753 754 sc->sc_eintrs = OHCI_NORMAL_INTRS; 755 756 /* Allocate dummy ED that starts the control list. */ 757 sc->sc_ctrl_head = ohci_alloc_sed(sc); 758 if (sc->sc_ctrl_head == NULL) { 759 err = USBD_NOMEM; 760 goto bad1; 761 } 762 sc->sc_ctrl_head->ed.ed_flags |= htole32(OHCI_ED_SKIP); 763 764 /* Allocate dummy ED that starts the bulk list. */ 765 sc->sc_bulk_head = ohci_alloc_sed(sc); 766 if (sc->sc_bulk_head == NULL) { 767 err = USBD_NOMEM; 768 goto bad2; 769 } 770 sc->sc_bulk_head->ed.ed_flags |= htole32(OHCI_ED_SKIP); 771 772 /* Allocate dummy ED that starts the isochronous list. */ 773 sc->sc_isoc_head = ohci_alloc_sed(sc); 774 if (sc->sc_isoc_head == NULL) { 775 err = USBD_NOMEM; 776 goto bad3; 777 } 778 sc->sc_isoc_head->ed.ed_flags |= htole32(OHCI_ED_SKIP); 779 780 /* Allocate all the dummy EDs that make up the interrupt tree. */ 781 for (i = 0; i < OHCI_NO_EDS; i++) { 782 sed = ohci_alloc_sed(sc); 783 if (sed == NULL) { 784 while (--i >= 0) 785 ohci_free_sed(sc, sc->sc_eds[i]); 786 err = USBD_NOMEM; 787 goto bad4; 788 } 789 /* All ED fields are set to 0. */ 790 sc->sc_eds[i] = sed; 791 sed->ed.ed_flags |= htole32(OHCI_ED_SKIP); 792 if (i != 0) 793 psed = sc->sc_eds[(i-1) / 2]; 794 else 795 psed= sc->sc_isoc_head; 796 sed->next = psed; 797 sed->ed.ed_nexted = htole32(psed->physaddr); 798 } 799 /* 800 * Fill HCCA interrupt table. The bit reversal is to get 801 * the tree set up properly to spread the interrupts. 802 */ 803 for (i = 0; i < OHCI_NO_INTRS; i++) 804 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 805 htole32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 806 807 #ifdef OHCI_DEBUG 808 if (ohcidebug > 15) { 809 for (i = 0; i < OHCI_NO_EDS; i++) { 810 printf("ed#%d ", i); 811 ohci_dump_ed(sc->sc_eds[i]); 812 } 813 printf("iso "); 814 ohci_dump_ed(sc->sc_isoc_head); 815 } 816 #endif 817 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 818 ctl = OREAD4(sc, OHCI_CONTROL); 819 rwc = ctl & OHCI_RWC; 820 fm = OREAD4(sc, OHCI_FM_INTERVAL); 821 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 822 descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 823 824 /* Determine in what context we are running. */ 825 if (ctl & OHCI_IR) { 826 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 827 goto reset; 828 #if 0 829 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 830 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 831 /* BIOS started controller. */ 832 DPRINTF(("ohci_init: BIOS active\n")); 833 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 834 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 835 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 836 } 837 #endif 838 } else { 839 DPRINTF(("ohci_init: cold started\n")); 840 reset: 841 /* Controller was cold started. */ 842 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 843 } 844 845 /* 846 * This reset should not be necessary according to the OHCI spec, but 847 * without it some controllers do not start. 848 */ 849 DPRINTF(("%s: resetting\n", sc->sc_bus.bdev.dv_xname)); 850 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 851 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 852 853 /* We now own the host controller and the bus has been reset. */ 854 855 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 856 /* Nominal time for a reset is 10 us. */ 857 for (i = 0; i < 10; i++) { 858 delay(10); 859 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 860 if (!hcr) 861 break; 862 } 863 if (hcr) { 864 printf("%s: reset timeout\n", sc->sc_bus.bdev.dv_xname); 865 err = USBD_IOERROR; 866 goto bad5; 867 } 868 #ifdef OHCI_DEBUG 869 if (ohcidebug > 15) 870 ohci_dumpregs(sc); 871 #endif 872 873 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 874 875 /* Set up HC registers. */ 876 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 877 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 878 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 879 /* disable all interrupts and then switch on all desired interrupts */ 880 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 881 /* switch on desired functional features */ 882 ctl = OREAD4(sc, OHCI_CONTROL); 883 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 884 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 885 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 886 /* And finally start it! */ 887 OWRITE4(sc, OHCI_CONTROL, ctl); 888 889 /* 890 * The controller is now OPERATIONAL. Set a some final 891 * registers that should be set earlier, but that the 892 * controller ignores when in the SUSPEND state. 893 */ 894 ival = OHCI_GET_IVAL(fm); 895 fm = (OREAD4(sc, OHCI_FM_REMAINING) & OHCI_FIT) ^ OHCI_FIT; 896 fm |= OHCI_FSMPS(ival) | ival; 897 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 898 per = OHCI_PERIODIC(ival); /* 90% periodic */ 899 OWRITE4(sc, OHCI_PERIODIC_START, per); 900 901 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 902 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 903 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 904 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 905 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 906 OWRITE4(sc, OHCI_RH_DESCRIPTOR_B, descb); 907 usb_delay_ms(&sc->sc_bus, OHCI_GET_POTPGT(desca) * UHD_PWRON_FACTOR); 908 909 /* 910 * The AMD756 requires a delay before re-reading the register, 911 * otherwise it will occasionally report 0 ports. 912 */ 913 sc->sc_noport = 0; 914 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 915 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 916 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 917 } 918 919 #ifdef OHCI_DEBUG 920 if (ohcidebug > 5) 921 ohci_dumpregs(sc); 922 #endif 923 924 /* Set up the bus struct. */ 925 sc->sc_bus.methods = &ohci_bus_methods; 926 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 927 928 sc->sc_control = sc->sc_intre = 0; 929 sc->sc_shutdownhook = shutdownhook_establish(ohci_shutdown, sc); 930 931 timeout_set(&sc->sc_tmo_rhsc, ohci_rhsc_enable, sc); 932 933 /* Finally, turn on interrupts. */ 934 DPRINTFN(1,("ohci_init: enabling\n")); 935 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 936 937 return (USBD_NORMAL_COMPLETION); 938 939 bad5: 940 for (i = 0; i < OHCI_NO_EDS; i++) 941 ohci_free_sed(sc, sc->sc_eds[i]); 942 bad4: 943 ohci_free_sed(sc, sc->sc_isoc_head); 944 bad3: 945 ohci_free_sed(sc, sc->sc_bulk_head); 946 bad2: 947 ohci_free_sed(sc, sc->sc_ctrl_head); 948 bad1: 949 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 950 return (err); 951 } 952 953 usbd_status 954 ohci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 955 { 956 struct ohci_softc *sc = (struct ohci_softc *)bus; 957 958 return (usb_allocmem(&sc->sc_bus, size, 0, dma)); 959 } 960 961 void 962 ohci_freem(struct usbd_bus *bus, usb_dma_t *dma) 963 { 964 struct ohci_softc *sc = (struct ohci_softc *)bus; 965 966 usb_freemem(&sc->sc_bus, dma); 967 } 968 969 usbd_xfer_handle 970 ohci_allocx(struct usbd_bus *bus) 971 { 972 struct ohci_softc *sc = (struct ohci_softc *)bus; 973 usbd_xfer_handle xfer; 974 975 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 976 if (xfer != NULL) { 977 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 978 #ifdef DIAGNOSTIC 979 if (xfer->busy_free != XFER_FREE) { 980 printf("ohci_allocx: xfer=%p not free, 0x%08x\n", xfer, 981 xfer->busy_free); 982 } 983 #endif 984 } else { 985 xfer = malloc(sizeof(struct ohci_xfer), M_USB, M_NOWAIT); 986 } 987 if (xfer != NULL) { 988 memset(xfer, 0, sizeof (struct ohci_xfer)); 989 #ifdef DIAGNOSTIC 990 xfer->busy_free = XFER_BUSY; 991 #endif 992 } 993 return (xfer); 994 } 995 996 void 997 ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 998 { 999 struct ohci_softc *sc = (struct ohci_softc *)bus; 1000 1001 #ifdef DIAGNOSTIC 1002 if (xfer->busy_free != XFER_BUSY) { 1003 printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1004 xfer->busy_free); 1005 return; 1006 } 1007 xfer->busy_free = XFER_FREE; 1008 #endif 1009 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1010 } 1011 1012 /* 1013 * Shut down the controller when the system is going down. 1014 */ 1015 void 1016 ohci_shutdown(void *v) 1017 { 1018 ohci_softc_t *sc = v; 1019 1020 DPRINTF(("ohci_shutdown: stopping the HC\n")); 1021 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1022 } 1023 1024 #ifdef OHCI_DEBUG 1025 void 1026 ohci_dumpregs(ohci_softc_t *sc) 1027 { 1028 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 1029 OREAD4(sc, OHCI_REVISION), 1030 OREAD4(sc, OHCI_CONTROL), 1031 OREAD4(sc, OHCI_COMMAND_STATUS))); 1032 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 1033 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1034 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1035 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 1036 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 1037 OREAD4(sc, OHCI_HCCA), 1038 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1039 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 1040 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 1041 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1042 OREAD4(sc, OHCI_BULK_HEAD_ED), 1043 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 1044 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 1045 OREAD4(sc, OHCI_DONE_HEAD), 1046 OREAD4(sc, OHCI_FM_INTERVAL), 1047 OREAD4(sc, OHCI_FM_REMAINING))); 1048 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 1049 OREAD4(sc, OHCI_FM_NUMBER), 1050 OREAD4(sc, OHCI_PERIODIC_START), 1051 OREAD4(sc, OHCI_LS_THRESHOLD))); 1052 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 1053 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1054 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1055 OREAD4(sc, OHCI_RH_STATUS))); 1056 DPRINTF((" port1=0x%08x port2=0x%08x\n", 1057 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1058 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 1059 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 1060 letoh32(sc->sc_hcca->hcca_frame_number), 1061 letoh32(sc->sc_hcca->hcca_done_head))); 1062 } 1063 #endif 1064 1065 int ohci_intr1(ohci_softc_t *); 1066 1067 int 1068 ohci_intr(void *p) 1069 { 1070 ohci_softc_t *sc = p; 1071 1072 if (sc == NULL || sc->sc_bus.dying) 1073 return (0); 1074 1075 /* If we get an interrupt while polling, then just ignore it. */ 1076 if (!cold && sc->sc_bus.use_polling) { 1077 #ifdef DIAGNOSTIC 1078 static struct timeval ohci_intr_tv; 1079 if ((OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) && 1080 usbd_ratecheck(&ohci_intr_tv)) 1081 DPRINTFN(16, 1082 ("ohci_intr: ignored interrupt while polling\n")); 1083 #endif 1084 return (0); 1085 } 1086 1087 return (ohci_intr1(sc)); 1088 } 1089 1090 int 1091 ohci_intr1(ohci_softc_t *sc) 1092 { 1093 u_int32_t intrs, eintrs; 1094 ohci_physaddr_t done; 1095 1096 DPRINTFN(14,("ohci_intr1: enter\n")); 1097 1098 /* In case the interrupt occurs before initialization has completed. */ 1099 if (sc == NULL || sc->sc_hcca == NULL) { 1100 #ifdef DIAGNOSTIC 1101 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1102 #endif 1103 return (0); 1104 } 1105 1106 intrs = 0; 1107 done = letoh32(sc->sc_hcca->hcca_done_head); 1108 if (done != 0) { 1109 if (done & ~OHCI_DONE_INTRS) 1110 intrs = OHCI_WDH; 1111 if (done & OHCI_DONE_INTRS) 1112 intrs |= OREAD4(sc, OHCI_INTERRUPT_STATUS); 1113 sc->sc_hcca->hcca_done_head = 0; 1114 } else { 1115 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1116 /* If we've flushed out a WDH then reread */ 1117 if (intrs & OHCI_WDH) { 1118 done = letoh32(sc->sc_hcca->hcca_done_head); 1119 sc->sc_hcca->hcca_done_head = 0; 1120 } 1121 } 1122 1123 if (intrs == 0xffffffff) { 1124 sc->sc_bus.dying = 1; 1125 return (0); 1126 } 1127 1128 if (!intrs) 1129 return (0); 1130 1131 intrs &= ~OHCI_MIE; 1132 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs); /* Acknowledge */ 1133 eintrs = intrs & sc->sc_eintrs; 1134 if (!eintrs) 1135 return (0); 1136 1137 sc->sc_bus.intr_context++; 1138 sc->sc_bus.no_intrs++; 1139 DPRINTFN(7, ("ohci_intr: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 1140 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 1141 (u_int)eintrs)); 1142 1143 if (eintrs & OHCI_SO) { 1144 sc->sc_overrun_cnt++; 1145 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1146 printf("%s: %u scheduling overruns\n", 1147 sc->sc_bus.bdev.dv_xname, sc->sc_overrun_cnt); 1148 sc->sc_overrun_cnt = 0; 1149 } 1150 /* XXX do what */ 1151 eintrs &= ~OHCI_SO; 1152 } 1153 if (eintrs & OHCI_WDH) { 1154 ohci_add_done(sc, done &~ OHCI_DONE_INTRS); 1155 usb_schedsoftintr(&sc->sc_bus); 1156 eintrs &= ~OHCI_WDH; 1157 } 1158 if (eintrs & OHCI_RD) { 1159 printf("%s: resume detect\n", sc->sc_bus.bdev.dv_xname); 1160 /* XXX process resume detect */ 1161 } 1162 if (eintrs & OHCI_UE) { 1163 printf("%s: unrecoverable error, controller halted\n", 1164 sc->sc_bus.bdev.dv_xname); 1165 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1166 /* XXX what else */ 1167 } 1168 if (eintrs & OHCI_RHSC) { 1169 ohci_rhsc(sc, sc->sc_intrxfer); 1170 /* 1171 * Disable RHSC interrupt for now, because it will be 1172 * on until the port has been reset. 1173 */ 1174 ohci_rhsc_able(sc, 0); 1175 DPRINTFN(2, ("%s: rhsc interrupt disabled\n", 1176 sc->sc_bus.bdev.dv_xname)); 1177 1178 /* Do not allow RHSC interrupts > 1 per second */ 1179 timeout_add_sec(&sc->sc_tmo_rhsc, 1); 1180 eintrs &= ~OHCI_RHSC; 1181 } 1182 1183 sc->sc_bus.intr_context--; 1184 1185 if (eintrs != 0) { 1186 /* Block unprocessed interrupts. XXX */ 1187 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1188 sc->sc_eintrs &= ~eintrs; 1189 printf("%s: blocking intrs 0x%x\n", 1190 sc->sc_bus.bdev.dv_xname, eintrs); 1191 } 1192 1193 return (1); 1194 } 1195 1196 void 1197 ohci_rhsc_able(ohci_softc_t *sc, int on) 1198 { 1199 DPRINTFN(4, ("ohci_rhsc_able: on=%d\n", on)); 1200 if (on) { 1201 sc->sc_eintrs |= OHCI_RHSC; 1202 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1203 } else { 1204 sc->sc_eintrs &= ~OHCI_RHSC; 1205 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC); 1206 } 1207 } 1208 1209 void 1210 ohci_rhsc_enable(void *v_sc) 1211 { 1212 ohci_softc_t *sc = v_sc; 1213 int s; 1214 1215 if (sc->sc_bus.dying) 1216 return; 1217 1218 s = splhardusb(); 1219 ohci_rhsc(sc, sc->sc_intrxfer); 1220 DPRINTFN(2, ("%s: rhsc interrupt enabled\n", 1221 sc->sc_bus.bdev.dv_xname)); 1222 1223 ohci_rhsc_able(sc, 1); 1224 splx(s); 1225 } 1226 1227 #ifdef OHCI_DEBUG 1228 char *ohci_cc_strs[] = { 1229 "NO_ERROR", 1230 "CRC", 1231 "BIT_STUFFING", 1232 "DATA_TOGGLE_MISMATCH", 1233 "STALL", 1234 "DEVICE_NOT_RESPONDING", 1235 "PID_CHECK_FAILURE", 1236 "UNEXPECTED_PID", 1237 "DATA_OVERRUN", 1238 "DATA_UNDERRUN", 1239 "BUFFER_OVERRUN", 1240 "BUFFER_UNDERRUN", 1241 "reserved", 1242 "reserved", 1243 "NOT_ACCESSED", 1244 "NOT_ACCESSED", 1245 }; 1246 #endif 1247 1248 void 1249 ohci_add_done(ohci_softc_t *sc, ohci_physaddr_t done) 1250 { 1251 ohci_soft_itd_t *sitd, *sidone, **ip; 1252 ohci_soft_td_t *std, *sdone, **p; 1253 1254 /* Reverse the done list. */ 1255 for (sdone = NULL, sidone = NULL; done != 0; ) { 1256 std = ohci_hash_find_td(sc, done); 1257 if (std != NULL) { 1258 std->dnext = sdone; 1259 done = letoh32(std->td.td_nexttd); 1260 sdone = std; 1261 DPRINTFN(10,("add TD %p\n", std)); 1262 continue; 1263 } 1264 sitd = ohci_hash_find_itd(sc, done); 1265 if (sitd != NULL) { 1266 sitd->dnext = sidone; 1267 done = letoh32(sitd->itd.itd_nextitd); 1268 sidone = sitd; 1269 DPRINTFN(5,("add ITD %p\n", sitd)); 1270 continue; 1271 } 1272 panic("ohci_add_done: addr 0x%08lx not found", (u_long)done); 1273 } 1274 1275 /* sdone & sidone now hold the done lists. */ 1276 /* Put them on the already processed lists. */ 1277 for (p = &sc->sc_sdone; *p != NULL; p = &(*p)->dnext) 1278 ; 1279 *p = sdone; 1280 for (ip = &sc->sc_sidone; *ip != NULL; ip = &(*ip)->dnext) 1281 ; 1282 *ip = sidone; 1283 } 1284 1285 void 1286 ohci_softintr(void *v) 1287 { 1288 ohci_softc_t *sc = v; 1289 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1290 ohci_soft_td_t *std, *sdone, *stdnext; 1291 usbd_xfer_handle xfer; 1292 struct ohci_pipe *opipe; 1293 int len, cc, s; 1294 int i, j, actlen, iframes, uedir; 1295 1296 DPRINTFN(10,("ohci_softintr: enter\n")); 1297 1298 if (sc->sc_bus.dying) 1299 return; 1300 1301 sc->sc_bus.intr_context++; 1302 1303 s = splhardusb(); 1304 sdone = sc->sc_sdone; 1305 sc->sc_sdone = NULL; 1306 sidone = sc->sc_sidone; 1307 sc->sc_sidone = NULL; 1308 splx(s); 1309 1310 DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone)); 1311 1312 #ifdef OHCI_DEBUG 1313 if (ohcidebug > 10) { 1314 DPRINTF(("ohci_process_done: TD done:\n")); 1315 ohci_dump_tds(sdone); 1316 } 1317 #endif 1318 1319 for (std = sdone; std; std = stdnext) { 1320 xfer = std->xfer; 1321 stdnext = std->dnext; 1322 DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n", 1323 std, xfer, xfer ? xfer->hcpriv : 0)); 1324 if (xfer == NULL) { 1325 /* 1326 * xfer == NULL: There seems to be no xfer associated 1327 * with this TD. It is tailp that happened to end up on 1328 * the done queue. 1329 * Shouldn't happen, but some chips are broken(?). 1330 */ 1331 continue; 1332 } 1333 if (xfer->status == USBD_CANCELLED || 1334 xfer->status == USBD_TIMEOUT) { 1335 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1336 xfer)); 1337 /* Handled by abort routine. */ 1338 continue; 1339 } 1340 timeout_del(&xfer->timeout_handle); 1341 1342 len = std->len; 1343 if (std->td.td_cbp != 0) 1344 len -= letoh32(std->td.td_be) - 1345 letoh32(std->td.td_cbp) + 1; 1346 DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len, 1347 std->flags)); 1348 if (std->flags & OHCI_ADD_LEN) 1349 xfer->actlen += len; 1350 1351 cc = OHCI_TD_GET_CC(letoh32(std->td.td_flags)); 1352 if (cc == OHCI_CC_NO_ERROR) { 1353 if (std->flags & OHCI_CALL_DONE) { 1354 xfer->status = USBD_NORMAL_COMPLETION; 1355 s = splusb(); 1356 usb_transfer_complete(xfer); 1357 splx(s); 1358 } 1359 ohci_free_std(sc, std); 1360 } else { 1361 /* 1362 * Endpoint is halted. First unlink all the TDs 1363 * belonging to the failed transfer, and then restart 1364 * the endpoint. 1365 */ 1366 ohci_soft_td_t *p, *n; 1367 opipe = (struct ohci_pipe *)xfer->pipe; 1368 1369 DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n", 1370 OHCI_TD_GET_CC(letoh32(std->td.td_flags)), 1371 ohci_cc_strs[OHCI_TD_GET_CC(letoh32(std->td.td_flags))])); 1372 1373 /* remove TDs */ 1374 for (p = std; p->xfer == xfer; p = n) { 1375 n = p->nexttd; 1376 ohci_free_std(sc, p); 1377 } 1378 1379 /* clear halt */ 1380 opipe->sed->ed.ed_headp = htole32(p->physaddr); 1381 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1382 1383 if (cc == OHCI_CC_STALL) 1384 xfer->status = USBD_STALLED; 1385 else 1386 xfer->status = USBD_IOERROR; 1387 s = splusb(); 1388 usb_transfer_complete(xfer); 1389 splx(s); 1390 } 1391 } 1392 1393 #ifdef OHCI_DEBUG 1394 if (ohcidebug > 10) { 1395 DPRINTF(("ohci_softintr: ITD done:\n")); 1396 ohci_dump_itds(sidone); 1397 } 1398 #endif 1399 1400 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1401 xfer = sitd->xfer; 1402 sitdnext = sitd->dnext; 1403 DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n", 1404 sitd, xfer, xfer ? xfer->hcpriv : 0)); 1405 if (xfer == NULL) 1406 continue; 1407 if (xfer->status == USBD_CANCELLED || 1408 xfer->status == USBD_TIMEOUT) { 1409 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1410 xfer)); 1411 /* Handled by abort routine. */ 1412 continue; 1413 } 1414 #ifdef DIAGNOSTIC 1415 if (sitd->isdone) 1416 printf("ohci_softintr: sitd=%p is done\n", sitd); 1417 sitd->isdone = 1; 1418 #endif 1419 if (sitd->flags & OHCI_CALL_DONE) { 1420 ohci_soft_itd_t *next; 1421 1422 opipe = (struct ohci_pipe *)xfer->pipe; 1423 opipe->u.iso.inuse -= xfer->nframes; 1424 uedir = UE_GET_DIR(xfer->pipe->endpoint->edesc-> 1425 bEndpointAddress); 1426 xfer->status = USBD_NORMAL_COMPLETION; 1427 actlen = 0; 1428 for (i = 0, sitd = xfer->hcpriv; ; 1429 sitd = next) { 1430 next = sitd->nextitd; 1431 if (OHCI_ITD_GET_CC(letoh32(sitd-> 1432 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1433 xfer->status = USBD_IOERROR; 1434 /* For input, update frlengths with actual */ 1435 /* XXX anything necessary for output? */ 1436 if (uedir == UE_DIR_IN && 1437 xfer->status == USBD_NORMAL_COMPLETION) { 1438 iframes = OHCI_ITD_GET_FC(letoh32( 1439 sitd->itd.itd_flags)); 1440 for (j = 0; j < iframes; i++, j++) { 1441 len = letoh16(sitd-> 1442 itd.itd_offset[j]); 1443 if ((OHCI_ITD_PSW_GET_CC(len) & 1444 OHCI_CC_NOT_ACCESSED_MASK) 1445 == OHCI_CC_NOT_ACCESSED) 1446 len = 0; 1447 else 1448 len = OHCI_ITD_PSW_LENGTH(len); 1449 xfer->frlengths[i] = len; 1450 actlen += len; 1451 } 1452 } 1453 if (sitd->flags & OHCI_CALL_DONE) 1454 break; 1455 ohci_free_sitd(sc, sitd); 1456 } 1457 ohci_free_sitd(sc, sitd); 1458 if (uedir == UE_DIR_IN && 1459 xfer->status == USBD_NORMAL_COMPLETION) 1460 xfer->actlen = actlen; 1461 xfer->hcpriv = NULL; 1462 1463 s = splusb(); 1464 usb_transfer_complete(xfer); 1465 splx(s); 1466 } 1467 } 1468 1469 if (sc->sc_softwake) { 1470 sc->sc_softwake = 0; 1471 wakeup(&sc->sc_softwake); 1472 } 1473 1474 sc->sc_bus.intr_context--; 1475 DPRINTFN(10,("ohci_softintr: done:\n")); 1476 } 1477 1478 void 1479 ohci_device_ctrl_done(usbd_xfer_handle xfer) 1480 { 1481 DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer)); 1482 1483 #ifdef DIAGNOSTIC 1484 if (!(xfer->rqflags & URQ_REQUEST)) { 1485 panic("ohci_device_ctrl_done: not a request"); 1486 } 1487 #endif 1488 } 1489 1490 void 1491 ohci_device_intr_done(usbd_xfer_handle xfer) 1492 { 1493 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1494 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 1495 ohci_soft_ed_t *sed = opipe->sed; 1496 ohci_soft_td_t *data, *tail; 1497 1498 1499 DPRINTFN(10, ("ohci_device_intr_done: xfer=%p, actlen=%d\n", xfer, 1500 xfer->actlen)); 1501 1502 if (xfer->pipe->repeat) { 1503 data = opipe->tail.td; 1504 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1505 if (tail == NULL) { 1506 xfer->status = USBD_NOMEM; 1507 return; 1508 } 1509 tail->xfer = NULL; 1510 1511 data->td.td_flags = htole32( 1512 OHCI_TD_IN | OHCI_TD_NOCC | 1513 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1514 if (xfer->flags & USBD_SHORT_XFER_OK) 1515 data->td.td_flags |= htole32(OHCI_TD_R); 1516 data->td.td_cbp = htole32(DMAADDR(&xfer->dmabuf, 0)); 1517 data->nexttd = tail; 1518 data->td.td_nexttd = htole32(tail->physaddr); 1519 data->td.td_be = htole32(letoh32(data->td.td_cbp) + 1520 xfer->length - 1); 1521 data->len = xfer->length; 1522 data->xfer = xfer; 1523 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1524 xfer->hcpriv = data; 1525 xfer->actlen = 0; 1526 1527 sed->ed.ed_tailp = htole32(tail->physaddr); 1528 opipe->tail.td = tail; 1529 } 1530 } 1531 1532 void 1533 ohci_device_bulk_done(usbd_xfer_handle xfer) 1534 { 1535 DPRINTFN(10, ("ohci_device_bulk_done: xfer=%p, actlen=%d\n", xfer, 1536 xfer->actlen)); 1537 } 1538 1539 void 1540 ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer) 1541 { 1542 u_char *p; 1543 int i, m; 1544 int hstatus; 1545 1546 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1547 DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n", 1548 sc, xfer, hstatus)); 1549 1550 if (xfer == NULL) { 1551 /* Just ignore the change. */ 1552 return; 1553 } 1554 1555 p = KERNADDR(&xfer->dmabuf, 0); 1556 m = min(sc->sc_noport, xfer->length * 8 - 1); 1557 memset(p, 0, xfer->length); 1558 for (i = 1; i <= m; i++) { 1559 /* Pick out CHANGE bits from the status reg. */ 1560 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1561 p[i/8] |= 1 << (i%8); 1562 } 1563 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 1564 xfer->actlen = xfer->length; 1565 xfer->status = USBD_NORMAL_COMPLETION; 1566 1567 usb_transfer_complete(xfer); 1568 } 1569 1570 void 1571 ohci_root_intr_done(usbd_xfer_handle xfer) 1572 { 1573 } 1574 1575 void 1576 ohci_root_ctrl_done(usbd_xfer_handle xfer) 1577 { 1578 } 1579 1580 /* 1581 * Wait here until controller claims to have an interrupt. 1582 * Then call ohci_intr and return. Use timeout to avoid waiting 1583 * too long. 1584 */ 1585 void 1586 ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer) 1587 { 1588 int timo; 1589 u_int32_t intrs; 1590 1591 xfer->status = USBD_IN_PROGRESS; 1592 for (timo = xfer->timeout; timo >= 0; timo--) { 1593 usb_delay_ms(&sc->sc_bus, 1); 1594 if (sc->sc_bus.dying) 1595 break; 1596 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1597 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 1598 #ifdef OHCI_DEBUG 1599 if (ohcidebug > 15) 1600 ohci_dumpregs(sc); 1601 #endif 1602 if (intrs) { 1603 ohci_intr1(sc); 1604 if (xfer->status != USBD_IN_PROGRESS) 1605 return; 1606 } 1607 } 1608 1609 /* Timeout */ 1610 DPRINTF(("ohci_waitintr: timeout\n")); 1611 xfer->status = USBD_TIMEOUT; 1612 usb_transfer_complete(xfer); 1613 /* XXX should free TD */ 1614 } 1615 1616 void 1617 ohci_poll(struct usbd_bus *bus) 1618 { 1619 ohci_softc_t *sc = (ohci_softc_t *)bus; 1620 #ifdef OHCI_DEBUG 1621 static int last; 1622 int new; 1623 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1624 if (new != last) { 1625 DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new)); 1626 last = new; 1627 } 1628 #endif 1629 1630 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) 1631 ohci_intr1(sc); 1632 } 1633 1634 usbd_status 1635 ohci_device_request(usbd_xfer_handle xfer) 1636 { 1637 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1638 usb_device_request_t *req = &xfer->request; 1639 usbd_device_handle dev = opipe->pipe.device; 1640 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 1641 int addr = dev->address; 1642 ohci_soft_td_t *setup, *stat, *next, *tail; 1643 ohci_soft_ed_t *sed; 1644 int isread; 1645 u_int len; 1646 usbd_status err; 1647 int s; 1648 1649 isread = req->bmRequestType & UT_READ; 1650 len = UGETW(req->wLength); 1651 1652 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 1653 "wValue=0x%04x, wIndex=0x%04x len=%u, addr=%d, endpt=%d\n", 1654 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1655 UGETW(req->wIndex), len, addr, 1656 opipe->pipe.endpoint->edesc->bEndpointAddress)); 1657 1658 setup = opipe->tail.td; 1659 stat = ohci_alloc_std(sc); 1660 if (stat == NULL) { 1661 err = USBD_NOMEM; 1662 goto bad1; 1663 } 1664 tail = ohci_alloc_std(sc); 1665 if (tail == NULL) { 1666 err = USBD_NOMEM; 1667 goto bad2; 1668 } 1669 tail->xfer = NULL; 1670 1671 sed = opipe->sed; 1672 opipe->u.ctl.length = len; 1673 1674 /* Update device address and length since they may have changed 1675 during the setup of the control pipe in usbd_new_device(). */ 1676 /* XXX This only needs to be done once, but it's too early in open. */ 1677 /* XXXX Should not touch ED here! */ 1678 sed->ed.ed_flags = htole32( 1679 (letoh32(sed->ed.ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) | 1680 OHCI_ED_SET_FA(addr) | 1681 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize))); 1682 1683 next = stat; 1684 1685 /* Set up data transaction */ 1686 if (len != 0) { 1687 ohci_soft_td_t *std = stat; 1688 1689 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 1690 std, &stat); 1691 stat = stat->nexttd; /* point at free TD */ 1692 if (err) 1693 goto bad3; 1694 /* Start toggle at 1 and then use the carried toggle. */ 1695 std->td.td_flags &= htole32(~OHCI_TD_TOGGLE_MASK); 1696 std->td.td_flags |= htole32(OHCI_TD_TOGGLE_1); 1697 } 1698 1699 memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req); 1700 1701 setup->td.td_flags = htole32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1702 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1703 setup->td.td_cbp = htole32(DMAADDR(&opipe->u.ctl.reqdma, 0)); 1704 setup->nexttd = next; 1705 setup->td.td_nexttd = htole32(next->physaddr); 1706 setup->td.td_be = htole32(letoh32(setup->td.td_cbp) + sizeof *req - 1); 1707 setup->len = 0; 1708 setup->xfer = xfer; 1709 setup->flags = 0; 1710 xfer->hcpriv = setup; 1711 1712 stat->td.td_flags = htole32( 1713 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 1714 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1715 stat->td.td_cbp = 0; 1716 stat->nexttd = tail; 1717 stat->td.td_nexttd = htole32(tail->physaddr); 1718 stat->td.td_be = 0; 1719 stat->flags = OHCI_CALL_DONE; 1720 stat->len = 0; 1721 stat->xfer = xfer; 1722 1723 #ifdef OHCI_DEBUG 1724 if (ohcidebug > 5) { 1725 DPRINTF(("ohci_device_request:\n")); 1726 ohci_dump_ed(sed); 1727 ohci_dump_tds(setup); 1728 } 1729 #endif 1730 1731 /* Insert ED in schedule */ 1732 s = splusb(); 1733 sed->ed.ed_tailp = htole32(tail->physaddr); 1734 opipe->tail.td = tail; 1735 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1736 if (xfer->timeout && !sc->sc_bus.use_polling) { 1737 timeout_del(&xfer->timeout_handle); 1738 timeout_set(&xfer->timeout_handle, ohci_timeout, xfer); 1739 timeout_add(&xfer->timeout_handle, mstohz(xfer->timeout)); 1740 } 1741 splx(s); 1742 1743 #ifdef OHCI_DEBUG 1744 if (ohcidebug > 20) { 1745 delay(10000); 1746 DPRINTF(("ohci_device_request: status=%x\n", 1747 OREAD4(sc, OHCI_COMMAND_STATUS))); 1748 ohci_dumpregs(sc); 1749 printf("ctrl head:\n"); 1750 ohci_dump_ed(sc->sc_ctrl_head); 1751 printf("sed:\n"); 1752 ohci_dump_ed(sed); 1753 ohci_dump_tds(setup); 1754 } 1755 #endif 1756 1757 return (USBD_NORMAL_COMPLETION); 1758 1759 bad3: 1760 ohci_free_std(sc, tail); 1761 bad2: 1762 ohci_free_std(sc, stat); 1763 bad1: 1764 return (err); 1765 } 1766 1767 /* 1768 * Add an ED to the schedule. Called at splusb(). 1769 */ 1770 void 1771 ohci_add_ed(ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1772 { 1773 DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head)); 1774 1775 SPLUSBCHECK; 1776 sed->next = head->next; 1777 sed->ed.ed_nexted = head->ed.ed_nexted; 1778 head->next = sed; 1779 head->ed.ed_nexted = htole32(sed->physaddr); 1780 } 1781 1782 /* 1783 * Remove an ED from the schedule. Called at splusb(). 1784 */ 1785 void 1786 ohci_rem_ed(ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1787 { 1788 ohci_soft_ed_t *p; 1789 1790 SPLUSBCHECK; 1791 1792 /* XXX */ 1793 for (p = head; p != NULL && p->next != sed; p = p->next) 1794 ; 1795 if (p == NULL) 1796 panic("ohci_rem_ed: ED not found"); 1797 p->next = sed->next; 1798 p->ed.ed_nexted = sed->ed.ed_nexted; 1799 } 1800 1801 /* 1802 * When a transfer is completed the TD is added to the done queue by 1803 * the host controller. This queue is the processed by software. 1804 * Unfortunately the queue contains the physical address of the TD 1805 * and we have no simple way to translate this back to a kernel address. 1806 * To make the translation possible (and fast) we use a hash table of 1807 * TDs currently in the schedule. The physical address is used as the 1808 * hash value. 1809 */ 1810 1811 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1812 /* Called at splusb() */ 1813 void 1814 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1815 { 1816 int h = HASH(std->physaddr); 1817 1818 SPLUSBCHECK; 1819 1820 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1821 } 1822 1823 /* Called at splusb() */ 1824 void 1825 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1826 { 1827 SPLUSBCHECK; 1828 1829 LIST_REMOVE(std, hnext); 1830 } 1831 1832 ohci_soft_td_t * 1833 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1834 { 1835 int h = HASH(a); 1836 ohci_soft_td_t *std; 1837 1838 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1839 std != NULL; 1840 std = LIST_NEXT(std, hnext)) 1841 if (std->physaddr == a) 1842 return (std); 1843 return (NULL); 1844 } 1845 1846 /* Called at splusb() */ 1847 void 1848 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1849 { 1850 int h = HASH(sitd->physaddr); 1851 1852 SPLUSBCHECK; 1853 1854 DPRINTFN(10,("ohci_hash_add_itd: sitd=%p physaddr=0x%08lx\n", 1855 sitd, (u_long)sitd->physaddr)); 1856 1857 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1858 } 1859 1860 /* Called at splusb() */ 1861 void 1862 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1863 { 1864 SPLUSBCHECK; 1865 1866 DPRINTFN(10,("ohci_hash_rem_itd: sitd=%p physaddr=0x%08lx\n", 1867 sitd, (u_long)sitd->physaddr)); 1868 1869 LIST_REMOVE(sitd, hnext); 1870 } 1871 1872 ohci_soft_itd_t * 1873 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1874 { 1875 int h = HASH(a); 1876 ohci_soft_itd_t *sitd; 1877 1878 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1879 sitd != NULL; 1880 sitd = LIST_NEXT(sitd, hnext)) 1881 if (sitd->physaddr == a) 1882 return (sitd); 1883 return (NULL); 1884 } 1885 1886 void 1887 ohci_timeout(void *addr) 1888 { 1889 struct ohci_xfer *oxfer = addr; 1890 struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.pipe; 1891 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 1892 1893 DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer)); 1894 1895 if (sc->sc_bus.dying) { 1896 ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT); 1897 return; 1898 } 1899 1900 /* Execute the abort in a process context. */ 1901 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr, 1902 USB_TASK_TYPE_ABORT); 1903 usb_add_task(oxfer->xfer.pipe->device, &oxfer->abort_task); 1904 } 1905 1906 void 1907 ohci_timeout_task(void *addr) 1908 { 1909 usbd_xfer_handle xfer = addr; 1910 int s; 1911 1912 DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer)); 1913 1914 s = splusb(); 1915 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1916 splx(s); 1917 } 1918 1919 #ifdef OHCI_DEBUG 1920 void 1921 ohci_dump_tds(ohci_soft_td_t *std) 1922 { 1923 for (; std; std = std->nexttd) 1924 ohci_dump_td(std); 1925 } 1926 1927 void 1928 ohci_dump_td(ohci_soft_td_t *std) 1929 { 1930 char sbuf[128]; 1931 1932 bitmask_snprintf((u_int32_t)letoh32(std->td.td_flags), 1933 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 1934 sbuf, sizeof(sbuf)); 1935 1936 printf("TD(%p) at %08lx: %s delay=%d ec=%d cc=%d\ncbp=0x%08lx " 1937 "nexttd=0x%08lx be=0x%08lx\n", 1938 std, (u_long)std->physaddr, sbuf, 1939 OHCI_TD_GET_DI(letoh32(std->td.td_flags)), 1940 OHCI_TD_GET_EC(letoh32(std->td.td_flags)), 1941 OHCI_TD_GET_CC(letoh32(std->td.td_flags)), 1942 (u_long)letoh32(std->td.td_cbp), 1943 (u_long)letoh32(std->td.td_nexttd), 1944 (u_long)letoh32(std->td.td_be)); 1945 } 1946 1947 void 1948 ohci_dump_itd(ohci_soft_itd_t *sitd) 1949 { 1950 int i; 1951 1952 printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n" 1953 "bp0=0x%08lx next=0x%08lx be=0x%08lx\n", 1954 sitd, (u_long)sitd->physaddr, 1955 OHCI_ITD_GET_SF(letoh32(sitd->itd.itd_flags)), 1956 OHCI_ITD_GET_DI(letoh32(sitd->itd.itd_flags)), 1957 OHCI_ITD_GET_FC(letoh32(sitd->itd.itd_flags)), 1958 OHCI_ITD_GET_CC(letoh32(sitd->itd.itd_flags)), 1959 (u_long)letoh32(sitd->itd.itd_bp0), 1960 (u_long)letoh32(sitd->itd.itd_nextitd), 1961 (u_long)letoh32(sitd->itd.itd_be)); 1962 for (i = 0; i < OHCI_ITD_NOFFSET; i++) 1963 printf("offs[%d]=0x%04x ", i, 1964 (u_int)letoh16(sitd->itd.itd_offset[i])); 1965 printf("\n"); 1966 } 1967 1968 void 1969 ohci_dump_itds(ohci_soft_itd_t *sitd) 1970 { 1971 for (; sitd; sitd = sitd->nextitd) 1972 ohci_dump_itd(sitd); 1973 } 1974 1975 void 1976 ohci_dump_ed(ohci_soft_ed_t *sed) 1977 { 1978 char sbuf[128], sbuf2[128]; 1979 1980 bitmask_snprintf((u_int32_t)letoh32(sed->ed.ed_flags), 1981 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 1982 sbuf, sizeof(sbuf)); 1983 bitmask_snprintf((u_int32_t)letoh32(sed->ed.ed_headp), 1984 "\20\1HALT\2CARRY", sbuf2, sizeof(sbuf2)); 1985 1986 printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\n" 1987 "tailp=0x%08lx headflags=%s headp=0x%08lx nexted=0x%08lx\n", 1988 sed, (u_long)sed->physaddr, 1989 OHCI_ED_GET_FA(letoh32(sed->ed.ed_flags)), 1990 OHCI_ED_GET_EN(letoh32(sed->ed.ed_flags)), 1991 OHCI_ED_GET_MAXP(letoh32(sed->ed.ed_flags)), sbuf, 1992 (u_long)letoh32(sed->ed.ed_tailp), sbuf2, 1993 (u_long)letoh32(sed->ed.ed_headp), 1994 (u_long)letoh32(sed->ed.ed_nexted)); 1995 } 1996 #endif 1997 1998 usbd_status 1999 ohci_open(usbd_pipe_handle pipe) 2000 { 2001 usbd_device_handle dev = pipe->device; 2002 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 2003 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 2004 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2005 u_int8_t addr = dev->address; 2006 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2007 ohci_soft_ed_t *sed; 2008 ohci_soft_td_t *std; 2009 ohci_soft_itd_t *sitd; 2010 ohci_physaddr_t tdphys; 2011 u_int32_t fmt; 2012 usbd_status err; 2013 int s; 2014 int ival; 2015 2016 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 2017 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 2018 2019 if (sc->sc_bus.dying) 2020 return (USBD_IOERROR); 2021 2022 std = NULL; 2023 sed = NULL; 2024 2025 if (addr == sc->sc_addr) { 2026 switch (ed->bEndpointAddress) { 2027 case USB_CONTROL_ENDPOINT: 2028 pipe->methods = &ohci_root_ctrl_methods; 2029 break; 2030 case UE_DIR_IN | OHCI_INTR_ENDPT: 2031 pipe->methods = &ohci_root_intr_methods; 2032 break; 2033 default: 2034 return (USBD_INVAL); 2035 } 2036 } else { 2037 sed = ohci_alloc_sed(sc); 2038 if (sed == NULL) 2039 goto bad0; 2040 opipe->sed = sed; 2041 if (xfertype == UE_ISOCHRONOUS) { 2042 sitd = ohci_alloc_sitd(sc); 2043 if (sitd == NULL) 2044 goto bad1; 2045 opipe->tail.itd = sitd; 2046 tdphys = sitd->physaddr; 2047 fmt = OHCI_ED_FORMAT_ISO; 2048 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2049 fmt |= OHCI_ED_DIR_IN; 2050 else 2051 fmt |= OHCI_ED_DIR_OUT; 2052 } else { 2053 std = ohci_alloc_std(sc); 2054 if (std == NULL) 2055 goto bad1; 2056 opipe->tail.td = std; 2057 tdphys = std->physaddr; 2058 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2059 } 2060 sed->ed.ed_flags = htole32( 2061 OHCI_ED_SET_FA(addr) | 2062 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2063 (dev->speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2064 fmt | OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2065 sed->ed.ed_headp = htole32(tdphys | 2066 (pipe->endpoint->savedtoggle ? OHCI_TOGGLECARRY : 0)); 2067 sed->ed.ed_tailp = htole32(tdphys); 2068 2069 switch (xfertype) { 2070 case UE_CONTROL: 2071 pipe->methods = &ohci_device_ctrl_methods; 2072 err = usb_allocmem(&sc->sc_bus, 2073 sizeof(usb_device_request_t), 2074 0, &opipe->u.ctl.reqdma); 2075 if (err) 2076 goto bad; 2077 s = splusb(); 2078 ohci_add_ed(sed, sc->sc_ctrl_head); 2079 splx(s); 2080 break; 2081 case UE_INTERRUPT: 2082 pipe->methods = &ohci_device_intr_methods; 2083 ival = pipe->interval; 2084 if (ival == USBD_DEFAULT_INTERVAL) 2085 ival = ed->bInterval; 2086 return (ohci_device_setintr(sc, opipe, ival)); 2087 case UE_ISOCHRONOUS: 2088 pipe->methods = &ohci_device_isoc_methods; 2089 return (ohci_setup_isoc(pipe)); 2090 case UE_BULK: 2091 pipe->methods = &ohci_device_bulk_methods; 2092 s = splusb(); 2093 ohci_add_ed(sed, sc->sc_bulk_head); 2094 splx(s); 2095 break; 2096 } 2097 } 2098 return (USBD_NORMAL_COMPLETION); 2099 2100 bad: 2101 if (std != NULL) 2102 ohci_free_std(sc, std); 2103 bad1: 2104 if (sed != NULL) 2105 ohci_free_sed(sc, sed); 2106 bad0: 2107 return (USBD_NOMEM); 2108 2109 } 2110 2111 /* 2112 * Close a reqular pipe. 2113 * Assumes that there are no pending transactions. 2114 */ 2115 void 2116 ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head) 2117 { 2118 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2119 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2120 ohci_soft_ed_t *sed = opipe->sed; 2121 int s; 2122 2123 s = splusb(); 2124 #ifdef DIAGNOSTIC 2125 sed->ed.ed_flags |= htole32(OHCI_ED_SKIP); 2126 if ((letoh32(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2127 (letoh32(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2128 ohci_soft_td_t *std; 2129 std = ohci_hash_find_td(sc, letoh32(sed->ed.ed_headp)); 2130 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2131 "tl=0x%x pipe=%p, std=%p\n", sed, 2132 (int)letoh32(sed->ed.ed_headp), 2133 (int)letoh32(sed->ed.ed_tailp), 2134 pipe, std); 2135 #ifdef USB_DEBUG 2136 usbd_dump_pipe(&opipe->pipe); 2137 #endif 2138 #ifdef OHCI_DEBUG 2139 ohci_dump_ed(sed); 2140 if (std) 2141 ohci_dump_td(std); 2142 #endif 2143 usb_delay_ms(&sc->sc_bus, 2); 2144 if ((letoh32(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2145 (letoh32(sed->ed.ed_headp) & OHCI_HEADMASK)) 2146 printf("ohci_close_pipe: pipe still not empty\n"); 2147 } 2148 #endif 2149 ohci_rem_ed(sed, head); 2150 /* Make sure the host controller is not touching this ED */ 2151 usb_delay_ms(&sc->sc_bus, 1); 2152 splx(s); 2153 pipe->endpoint->savedtoggle = 2154 (letoh32(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2155 ohci_free_sed(sc, opipe->sed); 2156 } 2157 2158 /* 2159 * Abort a device request. 2160 * If this routine is called at splusb() it guarantees that the request 2161 * will be removed from the hardware scheduling and that the callback 2162 * for it will be called with USBD_CANCELLED status. 2163 * It's impossible to guarantee that the requested transfer will not 2164 * have happened since the hardware runs concurrently. 2165 * If the transaction has already happened we rely on the ordinary 2166 * interrupt processing to process it. 2167 */ 2168 void 2169 ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2170 { 2171 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2172 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 2173 ohci_soft_ed_t *sed = opipe->sed; 2174 ohci_soft_td_t *p, *n; 2175 ohci_physaddr_t headp; 2176 int s, hit; 2177 2178 DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe, 2179 sed)); 2180 2181 if (sc->sc_bus.dying) { 2182 /* If we're dying, just do the software part. */ 2183 s = splusb(); 2184 xfer->status = status; /* make software ignore it */ 2185 timeout_del(&xfer->timeout_handle); 2186 usb_transfer_complete(xfer); 2187 splx(s); 2188 return; 2189 } 2190 2191 if (xfer->device->bus->intr_context || !curproc) 2192 panic("ohci_abort_xfer: not in process context"); 2193 2194 /* 2195 * Step 1: Make interrupt routine and hardware ignore xfer. 2196 */ 2197 s = splusb(); 2198 xfer->status = status; /* make software ignore it */ 2199 timeout_del(&xfer->timeout_handle); 2200 splx(s); 2201 DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed)); 2202 sed->ed.ed_flags |= htole32(OHCI_ED_SKIP); /* force hardware skip */ 2203 2204 /* 2205 * Step 2: Wait until we know hardware has finished any possible 2206 * use of the xfer. Also make sure the soft interrupt routine 2207 * has run. 2208 */ 2209 usb_delay_ms(opipe->pipe.device->bus, 20); /* Hardware finishes in 1ms */ 2210 s = splusb(); 2211 sc->sc_softwake = 1; 2212 usb_schedsoftintr(&sc->sc_bus); 2213 tsleep(&sc->sc_softwake, PZERO, "ohciab", 0); 2214 splx(s); 2215 2216 /* 2217 * Step 3: Remove any vestiges of the xfer from the hardware. 2218 * The complication here is that the hardware may have executed 2219 * beyond the xfer we're trying to abort. So as we're scanning 2220 * the TDs of this xfer we check if the hardware points to 2221 * any of them. 2222 */ 2223 s = splusb(); /* XXX why? */ 2224 p = xfer->hcpriv; 2225 #ifdef DIAGNOSTIC 2226 if (p == NULL) { 2227 splx(s); 2228 printf("ohci_abort_xfer: hcpriv is NULL\n"); 2229 return; 2230 } 2231 #endif 2232 #ifdef OHCI_DEBUG 2233 if (ohcidebug > 1) { 2234 DPRINTF(("ohci_abort_xfer: sed=\n")); 2235 ohci_dump_ed(sed); 2236 ohci_dump_tds(p); 2237 } 2238 #endif 2239 headp = letoh32(sed->ed.ed_headp) & OHCI_HEADMASK; 2240 hit = 0; 2241 for (; p->xfer == xfer; p = n) { 2242 hit |= headp == p->physaddr; 2243 n = p->nexttd; 2244 if (OHCI_TD_GET_CC(letoh32(p->td.td_flags)) == 2245 OHCI_CC_NOT_ACCESSED) 2246 ohci_free_std(sc, p); 2247 } 2248 /* Zap headp register if hardware pointed inside the xfer. */ 2249 if (hit) { 2250 DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n", 2251 (int)p->physaddr, (int)letoh32(sed->ed.ed_tailp))); 2252 sed->ed.ed_headp = htole32(p->physaddr); /* unlink TDs */ 2253 } else { 2254 DPRINTFN(1,("ohci_abort_xfer: no hit\n")); 2255 } 2256 2257 /* 2258 * Step 4: Turn on hardware again. 2259 */ 2260 sed->ed.ed_flags &= htole32(~OHCI_ED_SKIP); /* remove hardware skip */ 2261 2262 /* 2263 * Step 5: Execute callback. 2264 */ 2265 usb_transfer_complete(xfer); 2266 2267 splx(s); 2268 } 2269 2270 /* 2271 * Data structures and routines to emulate the root hub. 2272 */ 2273 usb_device_descriptor_t ohci_devd = { 2274 USB_DEVICE_DESCRIPTOR_SIZE, 2275 UDESC_DEVICE, /* type */ 2276 {0x00, 0x01}, /* USB version */ 2277 UDCLASS_HUB, /* class */ 2278 UDSUBCLASS_HUB, /* subclass */ 2279 UDPROTO_FSHUB, 2280 64, /* max packet */ 2281 {0},{0},{0x00,0x01}, /* device id */ 2282 1,2,0, /* string indices */ 2283 1 /* # of configurations */ 2284 }; 2285 2286 usb_config_descriptor_t ohci_confd = { 2287 USB_CONFIG_DESCRIPTOR_SIZE, 2288 UDESC_CONFIG, 2289 {USB_CONFIG_DESCRIPTOR_SIZE + 2290 USB_INTERFACE_DESCRIPTOR_SIZE + 2291 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2292 1, 2293 1, 2294 0, 2295 UC_SELF_POWERED, 2296 0 /* max power */ 2297 }; 2298 2299 usb_interface_descriptor_t ohci_ifcd = { 2300 USB_INTERFACE_DESCRIPTOR_SIZE, 2301 UDESC_INTERFACE, 2302 0, 2303 0, 2304 1, 2305 UICLASS_HUB, 2306 UISUBCLASS_HUB, 2307 UIPROTO_FSHUB, 2308 0 2309 }; 2310 2311 usb_endpoint_descriptor_t ohci_endpd = { 2312 USB_ENDPOINT_DESCRIPTOR_SIZE, 2313 UDESC_ENDPOINT, 2314 UE_DIR_IN | OHCI_INTR_ENDPT, 2315 UE_INTERRUPT, 2316 {8, 0}, /* max packet */ 2317 255 2318 }; 2319 2320 usb_hub_descriptor_t ohci_hubd = { 2321 USB_HUB_DESCRIPTOR_SIZE, 2322 UDESC_HUB, 2323 0, 2324 {0,0}, 2325 0, 2326 0, 2327 {0}, 2328 }; 2329 2330 int 2331 ohci_str(usb_string_descriptor_t *p, int l, const char *s) 2332 { 2333 int i; 2334 2335 if (l == 0) 2336 return (0); 2337 p->bLength = 2 * strlen(s) + 2; 2338 if (l == 1) 2339 return (1); 2340 p->bDescriptorType = UDESC_STRING; 2341 l -= 2; 2342 for (i = 0; s[i] && l > 1; i++, l -= 2) 2343 USETW2(p->bString[i], 0, s[i]); 2344 return (2*i+2); 2345 } 2346 2347 /* 2348 * Simulate a hardware hub by handling all the necessary requests. 2349 */ 2350 usbd_status 2351 ohci_root_ctrl_transfer(usbd_xfer_handle xfer) 2352 { 2353 usbd_status err; 2354 2355 /* Insert last in queue. */ 2356 err = usb_insert_transfer(xfer); 2357 if (err) 2358 return (err); 2359 2360 /* Pipe isn't running, start first */ 2361 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2362 } 2363 2364 usbd_status 2365 ohci_root_ctrl_start(usbd_xfer_handle xfer) 2366 { 2367 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 2368 usb_device_request_t *req; 2369 void *buf = NULL; 2370 int port, i; 2371 int s, len, value, index, l, totlen = 0; 2372 usb_port_status_t ps; 2373 usb_hub_descriptor_t hubd; 2374 usbd_status err; 2375 u_int32_t v; 2376 2377 if (sc->sc_bus.dying) 2378 return (USBD_IOERROR); 2379 2380 #ifdef DIAGNOSTIC 2381 if (!(xfer->rqflags & URQ_REQUEST)) 2382 /* XXX panic */ 2383 return (USBD_INVAL); 2384 #endif 2385 req = &xfer->request; 2386 2387 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 2388 req->bmRequestType, req->bRequest)); 2389 2390 len = UGETW(req->wLength); 2391 value = UGETW(req->wValue); 2392 index = UGETW(req->wIndex); 2393 2394 if (len != 0) 2395 buf = KERNADDR(&xfer->dmabuf, 0); 2396 2397 #define C(x,y) ((x) | ((y) << 8)) 2398 switch(C(req->bRequest, req->bmRequestType)) { 2399 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2400 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2401 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2402 /* 2403 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2404 * for the integrated root hub. 2405 */ 2406 break; 2407 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2408 if (len > 0) { 2409 *(u_int8_t *)buf = sc->sc_conf; 2410 totlen = 1; 2411 } 2412 break; 2413 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2414 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 2415 switch(value >> 8) { 2416 case UDESC_DEVICE: 2417 if ((value & 0xff) != 0) { 2418 err = USBD_IOERROR; 2419 goto ret; 2420 } 2421 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2422 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 2423 memcpy(buf, &ohci_devd, l); 2424 break; 2425 case UDESC_CONFIG: 2426 if ((value & 0xff) != 0) { 2427 err = USBD_IOERROR; 2428 goto ret; 2429 } 2430 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2431 memcpy(buf, &ohci_confd, l); 2432 buf = (char *)buf + l; 2433 len -= l; 2434 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2435 totlen += l; 2436 memcpy(buf, &ohci_ifcd, l); 2437 buf = (char *)buf + l; 2438 len -= l; 2439 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2440 totlen += l; 2441 memcpy(buf, &ohci_endpd, l); 2442 break; 2443 case UDESC_STRING: 2444 if (len == 0) 2445 break; 2446 *(u_int8_t *)buf = 0; 2447 totlen = 1; 2448 switch (value & 0xff) { 2449 case 0: /* Language table */ 2450 totlen = ohci_str(buf, len, "\001"); 2451 break; 2452 case 1: /* Vendor */ 2453 totlen = ohci_str(buf, len, sc->sc_vendor); 2454 break; 2455 case 2: /* Product */ 2456 totlen = ohci_str(buf, len, "OHCI root hub"); 2457 break; 2458 } 2459 break; 2460 default: 2461 err = USBD_IOERROR; 2462 goto ret; 2463 } 2464 break; 2465 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2466 if (len > 0) { 2467 *(u_int8_t *)buf = 0; 2468 totlen = 1; 2469 } 2470 break; 2471 case C(UR_GET_STATUS, UT_READ_DEVICE): 2472 if (len > 1) { 2473 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2474 totlen = 2; 2475 } 2476 break; 2477 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2478 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2479 if (len > 1) { 2480 USETW(((usb_status_t *)buf)->wStatus, 0); 2481 totlen = 2; 2482 } 2483 break; 2484 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2485 if (value >= USB_MAX_DEVICES) { 2486 err = USBD_IOERROR; 2487 goto ret; 2488 } 2489 sc->sc_addr = value; 2490 break; 2491 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2492 if (value != 0 && value != 1) { 2493 err = USBD_IOERROR; 2494 goto ret; 2495 } 2496 sc->sc_conf = value; 2497 break; 2498 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2499 break; 2500 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2501 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2502 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2503 err = USBD_IOERROR; 2504 goto ret; 2505 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2506 break; 2507 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2508 break; 2509 /* Hub requests */ 2510 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2511 break; 2512 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2513 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 2514 "port=%d feature=%d\n", 2515 index, value)); 2516 if (index < 1 || index > sc->sc_noport) { 2517 err = USBD_IOERROR; 2518 goto ret; 2519 } 2520 port = OHCI_RH_PORT_STATUS(index); 2521 switch(value) { 2522 case UHF_PORT_ENABLE: 2523 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2524 break; 2525 case UHF_PORT_SUSPEND: 2526 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2527 break; 2528 case UHF_PORT_POWER: 2529 /* Yes, writing to the LOW_SPEED bit clears power. */ 2530 OWRITE4(sc, port, UPS_LOW_SPEED); 2531 break; 2532 case UHF_C_PORT_CONNECTION: 2533 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2534 break; 2535 case UHF_C_PORT_ENABLE: 2536 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2537 break; 2538 case UHF_C_PORT_SUSPEND: 2539 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2540 break; 2541 case UHF_C_PORT_OVER_CURRENT: 2542 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2543 break; 2544 case UHF_C_PORT_RESET: 2545 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2546 break; 2547 default: 2548 err = USBD_IOERROR; 2549 goto ret; 2550 } 2551 switch(value) { 2552 case UHF_C_PORT_CONNECTION: 2553 case UHF_C_PORT_ENABLE: 2554 case UHF_C_PORT_SUSPEND: 2555 case UHF_C_PORT_OVER_CURRENT: 2556 case UHF_C_PORT_RESET: 2557 /* Enable RHSC interrupt if condition is cleared. */ 2558 if ((OREAD4(sc, port) >> 16) == 0) 2559 ohci_rhsc_able(sc, 1); 2560 break; 2561 default: 2562 break; 2563 } 2564 break; 2565 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2566 if ((value & 0xff) != 0) { 2567 err = USBD_IOERROR; 2568 goto ret; 2569 } 2570 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2571 hubd = ohci_hubd; 2572 hubd.bNbrPorts = sc->sc_noport; 2573 USETW(hubd.wHubCharacteristics, 2574 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2575 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2576 /* XXX overcurrent */ 2577 ); 2578 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2579 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2580 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2581 hubd.DeviceRemovable[i++] = (u_int8_t)v; 2582 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2583 l = min(len, hubd.bDescLength); 2584 totlen = l; 2585 memcpy(buf, &hubd, l); 2586 break; 2587 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2588 if (len != 4) { 2589 err = USBD_IOERROR; 2590 goto ret; 2591 } 2592 memset(buf, 0, len); /* ? XXX */ 2593 totlen = len; 2594 break; 2595 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2596 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 2597 index)); 2598 if (index < 1 || index > sc->sc_noport) { 2599 err = USBD_IOERROR; 2600 goto ret; 2601 } 2602 if (len != 4) { 2603 err = USBD_IOERROR; 2604 goto ret; 2605 } 2606 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2607 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 2608 v)); 2609 USETW(ps.wPortStatus, v); 2610 USETW(ps.wPortChange, v >> 16); 2611 l = min(len, sizeof ps); 2612 memcpy(buf, &ps, l); 2613 totlen = l; 2614 break; 2615 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2616 err = USBD_IOERROR; 2617 goto ret; 2618 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2619 break; 2620 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2621 if (index < 1 || index > sc->sc_noport) { 2622 err = USBD_IOERROR; 2623 goto ret; 2624 } 2625 port = OHCI_RH_PORT_STATUS(index); 2626 switch(value) { 2627 case UHF_PORT_ENABLE: 2628 OWRITE4(sc, port, UPS_PORT_ENABLED); 2629 break; 2630 case UHF_PORT_SUSPEND: 2631 OWRITE4(sc, port, UPS_SUSPEND); 2632 break; 2633 case UHF_PORT_RESET: 2634 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 2635 index)); 2636 OWRITE4(sc, port, UPS_RESET); 2637 for (i = 0; i < 5; i++) { 2638 usb_delay_ms(&sc->sc_bus, 2639 USB_PORT_ROOT_RESET_DELAY); 2640 if (sc->sc_bus.dying) { 2641 err = USBD_IOERROR; 2642 goto ret; 2643 } 2644 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2645 break; 2646 } 2647 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 2648 index, OREAD4(sc, port))); 2649 break; 2650 case UHF_PORT_POWER: 2651 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 2652 "%d\n", index)); 2653 OWRITE4(sc, port, UPS_PORT_POWER); 2654 break; 2655 case UHF_PORT_DISOWN_TO_1_1: 2656 /* accept, but do nothing */ 2657 break; 2658 default: 2659 err = USBD_IOERROR; 2660 goto ret; 2661 } 2662 break; 2663 default: 2664 err = USBD_IOERROR; 2665 goto ret; 2666 } 2667 xfer->actlen = totlen; 2668 err = USBD_NORMAL_COMPLETION; 2669 ret: 2670 xfer->status = err; 2671 s = splusb(); 2672 usb_transfer_complete(xfer); 2673 splx(s); 2674 return (USBD_IN_PROGRESS); 2675 } 2676 2677 /* Abort a root control request. */ 2678 void 2679 ohci_root_ctrl_abort(usbd_xfer_handle xfer) 2680 { 2681 /* Nothing to do, all transfers are synchronous. */ 2682 } 2683 2684 /* Close the root pipe. */ 2685 void 2686 ohci_root_ctrl_close(usbd_pipe_handle pipe) 2687 { 2688 DPRINTF(("ohci_root_ctrl_close\n")); 2689 /* Nothing to do. */ 2690 } 2691 2692 usbd_status 2693 ohci_root_intr_transfer(usbd_xfer_handle xfer) 2694 { 2695 usbd_status err; 2696 2697 /* Insert last in queue. */ 2698 err = usb_insert_transfer(xfer); 2699 if (err) 2700 return (err); 2701 2702 /* Pipe isn't running, start first */ 2703 return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2704 } 2705 2706 usbd_status 2707 ohci_root_intr_start(usbd_xfer_handle xfer) 2708 { 2709 usbd_pipe_handle pipe = xfer->pipe; 2710 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2711 2712 if (sc->sc_bus.dying) 2713 return (USBD_IOERROR); 2714 2715 sc->sc_intrxfer = xfer; 2716 2717 return (USBD_IN_PROGRESS); 2718 } 2719 2720 /* Abort a root interrupt request. */ 2721 void 2722 ohci_root_intr_abort(usbd_xfer_handle xfer) 2723 { 2724 int s; 2725 2726 if (xfer->pipe->intrxfer == xfer) { 2727 DPRINTF(("ohci_root_intr_abort: remove\n")); 2728 xfer->pipe->intrxfer = NULL; 2729 } 2730 xfer->status = USBD_CANCELLED; 2731 s = splusb(); 2732 usb_transfer_complete(xfer); 2733 splx(s); 2734 } 2735 2736 /* Close the root pipe. */ 2737 void 2738 ohci_root_intr_close(usbd_pipe_handle pipe) 2739 { 2740 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2741 2742 DPRINTF(("ohci_root_intr_close\n")); 2743 2744 sc->sc_intrxfer = NULL; 2745 } 2746 2747 /************************/ 2748 2749 usbd_status 2750 ohci_device_ctrl_transfer(usbd_xfer_handle xfer) 2751 { 2752 usbd_status err; 2753 2754 /* Insert last in queue. */ 2755 err = usb_insert_transfer(xfer); 2756 if (err) 2757 return (err); 2758 2759 /* Pipe isn't running, start first */ 2760 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2761 } 2762 2763 usbd_status 2764 ohci_device_ctrl_start(usbd_xfer_handle xfer) 2765 { 2766 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 2767 usbd_status err; 2768 2769 if (sc->sc_bus.dying) 2770 return (USBD_IOERROR); 2771 2772 #ifdef DIAGNOSTIC 2773 if (!(xfer->rqflags & URQ_REQUEST)) { 2774 /* XXX panic */ 2775 printf("ohci_device_ctrl_transfer: not a request\n"); 2776 return (USBD_INVAL); 2777 } 2778 #endif 2779 2780 err = ohci_device_request(xfer); 2781 if (err) 2782 return (err); 2783 2784 if (sc->sc_bus.use_polling) 2785 ohci_waitintr(sc, xfer); 2786 2787 return (USBD_IN_PROGRESS); 2788 } 2789 2790 /* Abort a device control request. */ 2791 void 2792 ohci_device_ctrl_abort(usbd_xfer_handle xfer) 2793 { 2794 DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer)); 2795 ohci_abort_xfer(xfer, USBD_CANCELLED); 2796 } 2797 2798 /* Close a device control pipe. */ 2799 void 2800 ohci_device_ctrl_close(usbd_pipe_handle pipe) 2801 { 2802 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2803 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2804 2805 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 2806 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2807 ohci_free_std(sc, opipe->tail.td); 2808 } 2809 2810 /************************/ 2811 2812 void 2813 ohci_device_clear_toggle(usbd_pipe_handle pipe) 2814 { 2815 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2816 2817 opipe->sed->ed.ed_headp &= htole32(~OHCI_TOGGLECARRY); 2818 } 2819 2820 void 2821 ohci_noop(usbd_pipe_handle pipe) 2822 { 2823 } 2824 2825 usbd_status 2826 ohci_device_bulk_transfer(usbd_xfer_handle xfer) 2827 { 2828 usbd_status err; 2829 2830 /* Insert last in queue. */ 2831 err = usb_insert_transfer(xfer); 2832 if (err) 2833 return (err); 2834 2835 /* Pipe isn't running, start first */ 2836 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2837 } 2838 2839 usbd_status 2840 ohci_device_bulk_start(usbd_xfer_handle xfer) 2841 { 2842 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2843 usbd_device_handle dev = opipe->pipe.device; 2844 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 2845 int addr = dev->address; 2846 ohci_soft_td_t *data, *tail, *tdp; 2847 ohci_soft_ed_t *sed; 2848 u_int len; 2849 int s, isread, endpt; 2850 usbd_status err; 2851 2852 if (sc->sc_bus.dying) 2853 return (USBD_IOERROR); 2854 2855 #ifdef DIAGNOSTIC 2856 if (xfer->rqflags & URQ_REQUEST) { 2857 /* XXX panic */ 2858 printf("ohci_device_bulk_start: a request\n"); 2859 return (USBD_INVAL); 2860 } 2861 #endif 2862 2863 len = xfer->length; 2864 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 2865 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2866 sed = opipe->sed; 2867 2868 DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%u isread=%d " 2869 "flags=%d endpt=%d\n", xfer, len, isread, xfer->flags, 2870 endpt)); 2871 2872 opipe->u.bulk.isread = isread; 2873 opipe->u.bulk.length = len; 2874 2875 /* Update device address */ 2876 sed->ed.ed_flags = htole32( 2877 (letoh32(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 2878 OHCI_ED_SET_FA(addr)); 2879 2880 /* Allocate a chain of new TDs (including a new tail). */ 2881 data = opipe->tail.td; 2882 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 2883 data, &tail); 2884 /* We want interrupt at the end of the transfer. */ 2885 tail->td.td_flags &= htole32(~OHCI_TD_INTR_MASK); 2886 tail->td.td_flags |= htole32(OHCI_TD_SET_DI(1)); 2887 tail->flags |= OHCI_CALL_DONE; 2888 tail = tail->nexttd; /* point at sentinel */ 2889 if (err) 2890 return (err); 2891 2892 tail->xfer = NULL; 2893 xfer->hcpriv = data; 2894 2895 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 2896 "td_cbp=0x%08x td_be=0x%08x\n", 2897 (int)letoh32(sed->ed.ed_flags), 2898 (int)letoh32(data->td.td_flags), 2899 (int)letoh32(data->td.td_cbp), 2900 (int)letoh32(data->td.td_be))); 2901 2902 #ifdef OHCI_DEBUG 2903 if (ohcidebug > 5) { 2904 ohci_dump_ed(sed); 2905 ohci_dump_tds(data); 2906 } 2907 #endif 2908 2909 /* Insert ED in schedule */ 2910 s = splusb(); 2911 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 2912 tdp->xfer = xfer; 2913 } 2914 sed->ed.ed_tailp = htole32(tail->physaddr); 2915 opipe->tail.td = tail; 2916 sed->ed.ed_flags &= htole32(~OHCI_ED_SKIP); 2917 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2918 if (xfer->timeout && !sc->sc_bus.use_polling) { 2919 timeout_del(&xfer->timeout_handle); 2920 timeout_set(&xfer->timeout_handle, ohci_timeout, xfer); 2921 timeout_add(&xfer->timeout_handle, mstohz(xfer->timeout)); 2922 } 2923 2924 #if 0 2925 /* This goes wrong if we are too slow. */ 2926 if (ohcidebug > 10) { 2927 delay(10000); 2928 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 2929 OREAD4(sc, OHCI_COMMAND_STATUS))); 2930 ohci_dump_ed(sed); 2931 ohci_dump_tds(data); 2932 } 2933 #endif 2934 2935 splx(s); 2936 2937 if (sc->sc_bus.use_polling) 2938 ohci_waitintr(sc, xfer); 2939 2940 return (USBD_IN_PROGRESS); 2941 } 2942 2943 void 2944 ohci_device_bulk_abort(usbd_xfer_handle xfer) 2945 { 2946 DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer)); 2947 ohci_abort_xfer(xfer, USBD_CANCELLED); 2948 } 2949 2950 /* 2951 * Close a device bulk pipe. 2952 */ 2953 void 2954 ohci_device_bulk_close(usbd_pipe_handle pipe) 2955 { 2956 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2957 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2958 2959 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 2960 ohci_close_pipe(pipe, sc->sc_bulk_head); 2961 ohci_free_std(sc, opipe->tail.td); 2962 } 2963 2964 /************************/ 2965 2966 usbd_status 2967 ohci_device_intr_transfer(usbd_xfer_handle xfer) 2968 { 2969 usbd_status err; 2970 2971 /* Insert last in queue. */ 2972 err = usb_insert_transfer(xfer); 2973 if (err) 2974 return (err); 2975 2976 /* Pipe isn't running, start first */ 2977 return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2978 } 2979 2980 usbd_status 2981 ohci_device_intr_start(usbd_xfer_handle xfer) 2982 { 2983 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2984 usbd_device_handle dev = opipe->pipe.device; 2985 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 2986 ohci_soft_ed_t *sed = opipe->sed; 2987 ohci_soft_td_t *data, *tail; 2988 int s, len, isread, endpt; 2989 2990 if (sc->sc_bus.dying) 2991 return (USBD_IOERROR); 2992 2993 DPRINTFN(3, ("ohci_device_intr_transfer: xfer=%p len=%u " 2994 "flags=%d priv=%p\n", 2995 xfer, xfer->length, xfer->flags, xfer->priv)); 2996 2997 #ifdef DIAGNOSTIC 2998 if (xfer->rqflags & URQ_REQUEST) 2999 panic("ohci_device_intr_transfer: a request"); 3000 #endif 3001 3002 len = xfer->length; 3003 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3004 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3005 3006 data = opipe->tail.td; 3007 tail = ohci_alloc_std(sc); 3008 if (tail == NULL) 3009 return (USBD_NOMEM); 3010 tail->xfer = NULL; 3011 3012 data->td.td_flags = htole32( 3013 isread ? OHCI_TD_IN : OHCI_TD_OUT | 3014 OHCI_TD_NOCC | 3015 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 3016 if (xfer->flags & USBD_SHORT_XFER_OK) 3017 data->td.td_flags |= htole32(OHCI_TD_R); 3018 data->td.td_cbp = htole32(DMAADDR(&xfer->dmabuf, 0)); 3019 data->nexttd = tail; 3020 data->td.td_nexttd = htole32(tail->physaddr); 3021 data->td.td_be = htole32(letoh32(data->td.td_cbp) + len - 1); 3022 data->len = len; 3023 data->xfer = xfer; 3024 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 3025 xfer->hcpriv = data; 3026 3027 #ifdef OHCI_DEBUG 3028 if (ohcidebug > 5) { 3029 DPRINTF(("ohci_device_intr_transfer:\n")); 3030 ohci_dump_ed(sed); 3031 ohci_dump_tds(data); 3032 } 3033 #endif 3034 3035 /* Insert ED in schedule */ 3036 s = splusb(); 3037 sed->ed.ed_tailp = htole32(tail->physaddr); 3038 opipe->tail.td = tail; 3039 sed->ed.ed_flags &= htole32(~OHCI_ED_SKIP); 3040 3041 #if 0 3042 /* 3043 * This goes horribly wrong, printing thousands of descriptors, 3044 * because false references are followed due to the fact that the 3045 * TD is gone. 3046 */ 3047 if (ohcidebug > 5) { 3048 usb_delay_ms(&sc->sc_bus, 5); 3049 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3050 OREAD4(sc, OHCI_COMMAND_STATUS))); 3051 ohci_dump_ed(sed); 3052 ohci_dump_tds(data); 3053 } 3054 #endif 3055 splx(s); 3056 3057 return (USBD_IN_PROGRESS); 3058 } 3059 3060 /* Abort a device control request. */ 3061 void 3062 ohci_device_intr_abort(usbd_xfer_handle xfer) 3063 { 3064 if (xfer->pipe->intrxfer == xfer) { 3065 DPRINTF(("ohci_device_intr_abort: remove\n")); 3066 xfer->pipe->intrxfer = NULL; 3067 } 3068 ohci_abort_xfer(xfer, USBD_CANCELLED); 3069 } 3070 3071 /* Close a device interrupt pipe. */ 3072 void 3073 ohci_device_intr_close(usbd_pipe_handle pipe) 3074 { 3075 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3076 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 3077 int nslots = opipe->u.intr.nslots; 3078 int pos = opipe->u.intr.pos; 3079 int j; 3080 ohci_soft_ed_t *p, *sed = opipe->sed; 3081 int s; 3082 3083 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 3084 pipe, nslots, pos)); 3085 s = splusb(); 3086 sed->ed.ed_flags |= htole32(OHCI_ED_SKIP); 3087 if ((letoh32(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3088 (letoh32(sed->ed.ed_headp) & OHCI_HEADMASK)) 3089 usb_delay_ms(&sc->sc_bus, 2); 3090 3091 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3092 ; 3093 #ifdef DIAGNOSTIC 3094 if (p == NULL) 3095 panic("ohci_device_intr_close: ED not found"); 3096 #endif 3097 p->next = sed->next; 3098 p->ed.ed_nexted = sed->ed.ed_nexted; 3099 splx(s); 3100 3101 for (j = 0; j < nslots; j++) 3102 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3103 3104 ohci_free_std(sc, opipe->tail.td); 3105 ohci_free_sed(sc, opipe->sed); 3106 } 3107 3108 usbd_status 3109 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3110 { 3111 int i, j, s, best; 3112 u_int npoll, slow, shigh, nslots; 3113 u_int bestbw, bw; 3114 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3115 3116 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 3117 if (ival == 0) { 3118 printf("ohci_setintr: 0 interval\n"); 3119 return (USBD_INVAL); 3120 } 3121 3122 npoll = OHCI_NO_INTRS; 3123 while (npoll > ival) 3124 npoll /= 2; 3125 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 3126 3127 /* 3128 * We now know which level in the tree the ED must go into. 3129 * Figure out which slot has most bandwidth left over. 3130 * Slots to examine: 3131 * npoll 3132 * 1 0 3133 * 2 1 2 3134 * 4 3 4 5 6 3135 * 8 7 8 9 10 11 12 13 14 3136 * N (N-1) .. (N-1+N-1) 3137 */ 3138 slow = npoll-1; 3139 shigh = slow + npoll; 3140 nslots = OHCI_NO_INTRS / npoll; 3141 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3142 bw = 0; 3143 for (j = 0; j < nslots; j++) 3144 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3145 if (bw < bestbw) { 3146 best = i; 3147 bestbw = bw; 3148 } 3149 } 3150 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 3151 best, slow, shigh, bestbw)); 3152 3153 s = splusb(); 3154 hsed = sc->sc_eds[best]; 3155 sed->next = hsed->next; 3156 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3157 hsed->next = sed; 3158 hsed->ed.ed_nexted = htole32(sed->physaddr); 3159 splx(s); 3160 3161 for (j = 0; j < nslots; j++) 3162 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3163 opipe->u.intr.nslots = nslots; 3164 opipe->u.intr.pos = best; 3165 3166 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 3167 return (USBD_NORMAL_COMPLETION); 3168 } 3169 3170 /***********************/ 3171 3172 usbd_status 3173 ohci_device_isoc_transfer(usbd_xfer_handle xfer) 3174 { 3175 usbd_status err; 3176 3177 DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer)); 3178 3179 /* Put it on our queue, */ 3180 err = usb_insert_transfer(xfer); 3181 3182 /* bail out on error, */ 3183 if (err && err != USBD_IN_PROGRESS) 3184 return (err); 3185 3186 /* XXX should check inuse here */ 3187 3188 /* insert into schedule, */ 3189 ohci_device_isoc_enter(xfer); 3190 3191 /* and start if the pipe wasn't running */ 3192 if (!err) 3193 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 3194 3195 return (err); 3196 } 3197 3198 void 3199 ohci_device_isoc_enter(usbd_xfer_handle xfer) 3200 { 3201 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3202 usbd_device_handle dev = opipe->pipe.device; 3203 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 3204 ohci_soft_ed_t *sed = opipe->sed; 3205 struct iso *iso = &opipe->u.iso; 3206 ohci_soft_itd_t *sitd, *nsitd; 3207 ohci_physaddr_t buf, offs, noffs, bp0; 3208 int i, ncur, nframes; 3209 int s; 3210 3211 DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p " 3212 "nframes=%d\n", 3213 iso->inuse, iso->next, xfer, xfer->nframes)); 3214 3215 if (sc->sc_bus.dying) 3216 return; 3217 3218 if (iso->next == -1) { 3219 /* Not in use yet, schedule it a few frames ahead. */ 3220 iso->next = letoh32(sc->sc_hcca->hcca_frame_number) + 5; 3221 DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n", 3222 iso->next)); 3223 } 3224 3225 sitd = opipe->tail.itd; 3226 buf = DMAADDR(&xfer->dmabuf, 0); 3227 bp0 = OHCI_PAGE(buf); 3228 offs = OHCI_PAGE_OFFSET(buf); 3229 nframes = xfer->nframes; 3230 xfer->hcpriv = sitd; 3231 for (i = ncur = 0; i < nframes; i++, ncur++) { 3232 noffs = offs + xfer->frlengths[i]; 3233 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3234 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3235 3236 /* Allocate next ITD */ 3237 nsitd = ohci_alloc_sitd(sc); 3238 if (nsitd == NULL) { 3239 /* XXX what now? */ 3240 printf("%s: isoc TD alloc failed\n", 3241 sc->sc_bus.bdev.dv_xname); 3242 return; 3243 } 3244 3245 /* Fill current ITD */ 3246 sitd->itd.itd_flags = htole32( 3247 OHCI_ITD_NOCC | 3248 OHCI_ITD_SET_SF(iso->next) | 3249 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3250 OHCI_ITD_SET_FC(ncur)); 3251 sitd->itd.itd_bp0 = htole32(bp0); 3252 sitd->nextitd = nsitd; 3253 sitd->itd.itd_nextitd = htole32(nsitd->physaddr); 3254 sitd->itd.itd_be = htole32(bp0 + offs - 1); 3255 sitd->xfer = xfer; 3256 sitd->flags = 0; 3257 3258 sitd = nsitd; 3259 iso->next = iso->next + ncur; 3260 bp0 = OHCI_PAGE(buf + offs); 3261 ncur = 0; 3262 } 3263 sitd->itd.itd_offset[ncur] = htole16(OHCI_ITD_MK_OFFS(offs)); 3264 offs = noffs; 3265 } 3266 nsitd = ohci_alloc_sitd(sc); 3267 if (nsitd == NULL) { 3268 /* XXX what now? */ 3269 printf("%s: isoc TD alloc failed\n", 3270 sc->sc_bus.bdev.dv_xname); 3271 return; 3272 } 3273 /* Fixup last used ITD */ 3274 sitd->itd.itd_flags = htole32( 3275 OHCI_ITD_NOCC | 3276 OHCI_ITD_SET_SF(iso->next) | 3277 OHCI_ITD_SET_DI(0) | 3278 OHCI_ITD_SET_FC(ncur)); 3279 sitd->itd.itd_bp0 = htole32(bp0); 3280 sitd->nextitd = nsitd; 3281 sitd->itd.itd_nextitd = htole32(nsitd->physaddr); 3282 sitd->itd.itd_be = htole32(bp0 + offs - 1); 3283 sitd->xfer = xfer; 3284 sitd->flags = OHCI_CALL_DONE; 3285 3286 iso->next = iso->next + ncur; 3287 iso->inuse += nframes; 3288 3289 xfer->actlen = offs; /* XXX pretend we did it all */ 3290 3291 xfer->status = USBD_IN_PROGRESS; 3292 3293 #ifdef OHCI_DEBUG 3294 if (ohcidebug > 5) { 3295 DPRINTF(("ohci_device_isoc_enter: frame=%d\n", 3296 letoh32(sc->sc_hcca->hcca_frame_number))); 3297 ohci_dump_itds(xfer->hcpriv); 3298 ohci_dump_ed(sed); 3299 } 3300 #endif 3301 3302 s = splusb(); 3303 sed->ed.ed_tailp = htole32(nsitd->physaddr); 3304 opipe->tail.itd = nsitd; 3305 sed->ed.ed_flags &= htole32(~OHCI_ED_SKIP); 3306 splx(s); 3307 3308 #ifdef OHCI_DEBUG 3309 if (ohcidebug > 5) { 3310 delay(150000); 3311 DPRINTF(("ohci_device_isoc_enter: after frame=%d\n", 3312 letoh32(sc->sc_hcca->hcca_frame_number))); 3313 ohci_dump_itds(xfer->hcpriv); 3314 ohci_dump_ed(sed); 3315 } 3316 #endif 3317 } 3318 3319 usbd_status 3320 ohci_device_isoc_start(usbd_xfer_handle xfer) 3321 { 3322 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3323 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 3324 3325 DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer)); 3326 3327 if (sc->sc_bus.dying) 3328 return (USBD_IOERROR); 3329 3330 #ifdef DIAGNOSTIC 3331 if (xfer->status != USBD_IN_PROGRESS) 3332 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3333 #endif 3334 3335 /* XXX anything to do? */ 3336 3337 return (USBD_IN_PROGRESS); 3338 } 3339 3340 void 3341 ohci_device_isoc_abort(usbd_xfer_handle xfer) 3342 { 3343 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3344 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 3345 ohci_soft_ed_t *sed; 3346 ohci_soft_itd_t *sitd; 3347 int s; 3348 3349 s = splusb(); 3350 3351 DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p\n", xfer)); 3352 3353 /* Transfer is already done. */ 3354 if (xfer->status != USBD_NOT_STARTED && 3355 xfer->status != USBD_IN_PROGRESS) { 3356 splx(s); 3357 printf("ohci_device_isoc_abort: early return\n"); 3358 return; 3359 } 3360 3361 /* Give xfer the requested abort code. */ 3362 xfer->status = USBD_CANCELLED; 3363 3364 sed = opipe->sed; 3365 sed->ed.ed_flags |= htole32(OHCI_ED_SKIP); /* force hardware skip */ 3366 3367 sitd = xfer->hcpriv; 3368 #ifdef DIAGNOSTIC 3369 if (sitd == NULL) { 3370 splx(s); 3371 printf("ohci_device_isoc_abort: hcpriv==0\n"); 3372 return; 3373 } 3374 #endif 3375 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3376 #ifdef DIAGNOSTIC 3377 DPRINTFN(1,("abort sets done sitd=%p\n", sitd)); 3378 sitd->isdone = 1; 3379 #endif 3380 } 3381 3382 splx(s); 3383 3384 usb_delay_ms(&sc->sc_bus, OHCI_ITD_NOFFSET); 3385 3386 s = splusb(); 3387 3388 /* Run callback. */ 3389 usb_transfer_complete(xfer); 3390 3391 sed->ed.ed_headp = htole32(sitd->physaddr); /* unlink TDs */ 3392 sed->ed.ed_flags &= htole32(~OHCI_ED_SKIP); /* remove hardware skip */ 3393 3394 splx(s); 3395 } 3396 3397 void 3398 ohci_device_isoc_done(usbd_xfer_handle xfer) 3399 { 3400 DPRINTFN(1,("ohci_device_isoc_done: xfer=%p\n", xfer)); 3401 } 3402 3403 usbd_status 3404 ohci_setup_isoc(usbd_pipe_handle pipe) 3405 { 3406 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3407 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 3408 struct iso *iso = &opipe->u.iso; 3409 int s; 3410 3411 iso->next = -1; 3412 iso->inuse = 0; 3413 3414 s = splusb(); 3415 ohci_add_ed(opipe->sed, sc->sc_isoc_head); 3416 splx(s); 3417 3418 return (USBD_NORMAL_COMPLETION); 3419 } 3420 3421 void 3422 ohci_device_isoc_close(usbd_pipe_handle pipe) 3423 { 3424 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3425 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 3426 3427 DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe)); 3428 ohci_close_pipe(pipe, sc->sc_isoc_head); 3429 #ifdef DIAGNOSTIC 3430 opipe->tail.itd->isdone = 1; 3431 #endif 3432 ohci_free_sitd(sc, opipe->tail.itd); 3433 } 3434