1 /* $OpenBSD: ohci.c,v 1.88 2008/09/10 14:01:23 blambert Exp $ */ 2 /* $NetBSD: ohci.c,v 1.139 2003/02/22 05:24:16 tsutsui Exp $ */ 3 /* $FreeBSD: src/sys/dev/usb/ohci.c,v 1.22 1999/11/17 22:33:40 n_hibma Exp $ */ 4 5 /* 6 * Copyright (c) 1998 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by Lennart Augustsson (lennart@augustsson.net) at 11 * Carlstedt Research & Technology. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * USB Open Host Controller driver. 37 * 38 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 39 * USB spec: http://www.usb.org/developers/docs/usbspec.zip 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/device.h> 47 #include <sys/selinfo.h> 48 #include <sys/proc.h> 49 #include <sys/queue.h> 50 51 #include <machine/bus.h> 52 #include <machine/endian.h> 53 54 #include <dev/usb/usb.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdivar.h> 57 #include <dev/usb/usb_mem.h> 58 #include <dev/usb/usb_quirks.h> 59 60 #include <dev/usb/ohcireg.h> 61 #include <dev/usb/ohcivar.h> 62 63 struct cfdriver ohci_cd = { 64 NULL, "ohci", DV_DULL 65 }; 66 67 #ifdef OHCI_DEBUG 68 #define DPRINTF(x) do { if (ohcidebug) printf x; } while (0) 69 #define DPRINTFN(n,x) do { if (ohcidebug>(n)) printf x; } while (0) 70 int ohcidebug = 0; 71 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 72 #else 73 #define DPRINTF(x) 74 #define DPRINTFN(n,x) 75 #endif 76 77 #define mstohz(ms) ((ms) * hz / 1000) 78 79 /* 80 * The OHCI controller is little endian, so on big endian machines 81 * the data stored in memory needs to be swapped. 82 */ 83 84 struct ohci_pipe; 85 86 ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 87 void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 88 89 ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 90 void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 91 92 ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 93 void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 94 95 #if 0 96 void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 97 ohci_soft_td_t *); 98 #endif 99 usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 100 ohci_softc_t *, int, int, usbd_xfer_handle, 101 ohci_soft_td_t *, ohci_soft_td_t **); 102 103 void ohci_shutdown(void *v); 104 usbd_status ohci_open(usbd_pipe_handle); 105 void ohci_poll(struct usbd_bus *); 106 void ohci_softintr(void *); 107 void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle); 108 void ohci_add_done(ohci_softc_t *, ohci_physaddr_t); 109 void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle); 110 111 usbd_status ohci_device_request(usbd_xfer_handle xfer); 112 void ohci_add_ed(ohci_soft_ed_t *, ohci_soft_ed_t *); 113 void ohci_rem_ed(ohci_soft_ed_t *, ohci_soft_ed_t *); 114 void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 115 void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 116 ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 117 void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 118 void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 119 ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 120 121 usbd_status ohci_setup_isoc(usbd_pipe_handle pipe); 122 void ohci_device_isoc_enter(usbd_xfer_handle); 123 124 usbd_status ohci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 125 void ohci_freem(struct usbd_bus *, usb_dma_t *); 126 127 usbd_xfer_handle ohci_allocx(struct usbd_bus *); 128 void ohci_freex(struct usbd_bus *, usbd_xfer_handle); 129 130 usbd_status ohci_root_ctrl_transfer(usbd_xfer_handle); 131 usbd_status ohci_root_ctrl_start(usbd_xfer_handle); 132 void ohci_root_ctrl_abort(usbd_xfer_handle); 133 void ohci_root_ctrl_close(usbd_pipe_handle); 134 void ohci_root_ctrl_done(usbd_xfer_handle); 135 136 usbd_status ohci_root_intr_transfer(usbd_xfer_handle); 137 usbd_status ohci_root_intr_start(usbd_xfer_handle); 138 void ohci_root_intr_abort(usbd_xfer_handle); 139 void ohci_root_intr_close(usbd_pipe_handle); 140 void ohci_root_intr_done(usbd_xfer_handle); 141 142 usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle); 143 usbd_status ohci_device_ctrl_start(usbd_xfer_handle); 144 void ohci_device_ctrl_abort(usbd_xfer_handle); 145 void ohci_device_ctrl_close(usbd_pipe_handle); 146 void ohci_device_ctrl_done(usbd_xfer_handle); 147 148 usbd_status ohci_device_bulk_transfer(usbd_xfer_handle); 149 usbd_status ohci_device_bulk_start(usbd_xfer_handle); 150 void ohci_device_bulk_abort(usbd_xfer_handle); 151 void ohci_device_bulk_close(usbd_pipe_handle); 152 void ohci_device_bulk_done(usbd_xfer_handle); 153 154 usbd_status ohci_device_intr_transfer(usbd_xfer_handle); 155 usbd_status ohci_device_intr_start(usbd_xfer_handle); 156 void ohci_device_intr_abort(usbd_xfer_handle); 157 void ohci_device_intr_close(usbd_pipe_handle); 158 void ohci_device_intr_done(usbd_xfer_handle); 159 160 usbd_status ohci_device_isoc_transfer(usbd_xfer_handle); 161 usbd_status ohci_device_isoc_start(usbd_xfer_handle); 162 void ohci_device_isoc_abort(usbd_xfer_handle); 163 void ohci_device_isoc_close(usbd_pipe_handle); 164 void ohci_device_isoc_done(usbd_xfer_handle); 165 166 usbd_status ohci_device_setintr(ohci_softc_t *sc, 167 struct ohci_pipe *pipe, int ival); 168 169 int ohci_str(usb_string_descriptor_t *, int, const char *); 170 171 void ohci_timeout(void *); 172 void ohci_timeout_task(void *); 173 void ohci_rhsc_able(ohci_softc_t *, int); 174 void ohci_rhsc_enable(void *); 175 176 void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *); 177 void ohci_abort_xfer(usbd_xfer_handle, usbd_status); 178 179 void ohci_device_clear_toggle(usbd_pipe_handle pipe); 180 void ohci_noop(usbd_pipe_handle pipe); 181 182 #ifdef OHCI_DEBUG 183 void ohci_dumpregs(ohci_softc_t *); 184 void ohci_dump_tds(ohci_soft_td_t *); 185 void ohci_dump_td(ohci_soft_td_t *); 186 void ohci_dump_ed(ohci_soft_ed_t *); 187 void ohci_dump_itd(ohci_soft_itd_t *); 188 void ohci_dump_itds(ohci_soft_itd_t *); 189 #endif 190 191 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 192 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 193 #define OWRITE1(sc, r, x) \ 194 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 195 #define OWRITE2(sc, r, x) \ 196 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 197 #define OWRITE4(sc, r, x) \ 198 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 199 #define OREAD1(sc, r) (OBARR(sc), bus_space_read_1((sc)->iot, (sc)->ioh, (r))) 200 #define OREAD2(sc, r) (OBARR(sc), bus_space_read_2((sc)->iot, (sc)->ioh, (r))) 201 #define OREAD4(sc, r) (OBARR(sc), bus_space_read_4((sc)->iot, (sc)->ioh, (r))) 202 203 /* Reverse the bits in a value 0 .. 31 */ 204 u_int8_t revbits[OHCI_NO_INTRS] = 205 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 206 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 207 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 208 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 209 210 struct ohci_pipe { 211 struct usbd_pipe pipe; 212 ohci_soft_ed_t *sed; 213 union { 214 ohci_soft_td_t *td; 215 ohci_soft_itd_t *itd; 216 } tail; 217 /* Info needed for different pipe kinds. */ 218 union { 219 /* Control pipe */ 220 struct { 221 usb_dma_t reqdma; 222 u_int length; 223 ohci_soft_td_t *setup, *data, *stat; 224 } ctl; 225 /* Interrupt pipe */ 226 struct { 227 int nslots; 228 int pos; 229 } intr; 230 /* Bulk pipe */ 231 struct { 232 u_int length; 233 int isread; 234 } bulk; 235 /* Iso pipe */ 236 struct iso { 237 int next, inuse; 238 } iso; 239 } u; 240 }; 241 242 #define OHCI_INTR_ENDPT 1 243 244 struct usbd_bus_methods ohci_bus_methods = { 245 ohci_open, 246 ohci_softintr, 247 ohci_poll, 248 ohci_allocm, 249 ohci_freem, 250 ohci_allocx, 251 ohci_freex, 252 }; 253 254 struct usbd_pipe_methods ohci_root_ctrl_methods = { 255 ohci_root_ctrl_transfer, 256 ohci_root_ctrl_start, 257 ohci_root_ctrl_abort, 258 ohci_root_ctrl_close, 259 ohci_noop, 260 ohci_root_ctrl_done, 261 }; 262 263 struct usbd_pipe_methods ohci_root_intr_methods = { 264 ohci_root_intr_transfer, 265 ohci_root_intr_start, 266 ohci_root_intr_abort, 267 ohci_root_intr_close, 268 ohci_noop, 269 ohci_root_intr_done, 270 }; 271 272 struct usbd_pipe_methods ohci_device_ctrl_methods = { 273 ohci_device_ctrl_transfer, 274 ohci_device_ctrl_start, 275 ohci_device_ctrl_abort, 276 ohci_device_ctrl_close, 277 ohci_noop, 278 ohci_device_ctrl_done, 279 }; 280 281 struct usbd_pipe_methods ohci_device_intr_methods = { 282 ohci_device_intr_transfer, 283 ohci_device_intr_start, 284 ohci_device_intr_abort, 285 ohci_device_intr_close, 286 ohci_device_clear_toggle, 287 ohci_device_intr_done, 288 }; 289 290 struct usbd_pipe_methods ohci_device_bulk_methods = { 291 ohci_device_bulk_transfer, 292 ohci_device_bulk_start, 293 ohci_device_bulk_abort, 294 ohci_device_bulk_close, 295 ohci_device_clear_toggle, 296 ohci_device_bulk_done, 297 }; 298 299 struct usbd_pipe_methods ohci_device_isoc_methods = { 300 ohci_device_isoc_transfer, 301 ohci_device_isoc_start, 302 ohci_device_isoc_abort, 303 ohci_device_isoc_close, 304 ohci_noop, 305 ohci_device_isoc_done, 306 }; 307 308 int 309 ohci_activate(struct device *self, enum devact act) 310 { 311 struct ohci_softc *sc = (struct ohci_softc *)self; 312 int rv = 0; 313 314 switch (act) { 315 case DVACT_ACTIVATE: 316 break; 317 318 case DVACT_DEACTIVATE: 319 if (sc->sc_child != NULL) 320 rv = config_deactivate(sc->sc_child); 321 sc->sc_dying = 1; 322 break; 323 } 324 return (rv); 325 } 326 327 int 328 ohci_detach(struct ohci_softc *sc, int flags) 329 { 330 int rv = 0; 331 332 if (sc->sc_child != NULL) 333 rv = config_detach(sc->sc_child, flags); 334 335 if (rv != 0) 336 return (rv); 337 338 timeout_del(&sc->sc_tmo_rhsc); 339 340 if (sc->sc_shutdownhook != NULL) 341 shutdownhook_disestablish(sc->sc_shutdownhook); 342 343 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 344 345 /* free data structures XXX */ 346 347 return (rv); 348 } 349 350 ohci_soft_ed_t * 351 ohci_alloc_sed(ohci_softc_t *sc) 352 { 353 ohci_soft_ed_t *sed; 354 usbd_status err; 355 int i, offs; 356 usb_dma_t dma; 357 358 if (sc->sc_freeeds == NULL) { 359 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 360 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 361 OHCI_ED_ALIGN, &dma); 362 if (err) 363 return (0); 364 for(i = 0; i < OHCI_SED_CHUNK; i++) { 365 offs = i * OHCI_SED_SIZE; 366 sed = KERNADDR(&dma, offs); 367 sed->physaddr = DMAADDR(&dma, offs); 368 sed->next = sc->sc_freeeds; 369 sc->sc_freeeds = sed; 370 } 371 } 372 sed = sc->sc_freeeds; 373 sc->sc_freeeds = sed->next; 374 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 375 sed->next = 0; 376 return (sed); 377 } 378 379 void 380 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 381 { 382 sed->next = sc->sc_freeeds; 383 sc->sc_freeeds = sed; 384 } 385 386 ohci_soft_td_t * 387 ohci_alloc_std(ohci_softc_t *sc) 388 { 389 ohci_soft_td_t *std; 390 usbd_status err; 391 int i, offs; 392 usb_dma_t dma; 393 int s; 394 395 if (sc->sc_freetds == NULL) { 396 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 397 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 398 OHCI_TD_ALIGN, &dma); 399 if (err) 400 return (NULL); 401 s = splusb(); 402 for(i = 0; i < OHCI_STD_CHUNK; i++) { 403 offs = i * OHCI_STD_SIZE; 404 std = KERNADDR(&dma, offs); 405 std->physaddr = DMAADDR(&dma, offs); 406 std->nexttd = sc->sc_freetds; 407 sc->sc_freetds = std; 408 } 409 splx(s); 410 } 411 412 s = splusb(); 413 std = sc->sc_freetds; 414 sc->sc_freetds = std->nexttd; 415 memset(&std->td, 0, sizeof(ohci_td_t)); 416 std->nexttd = NULL; 417 std->xfer = NULL; 418 ohci_hash_add_td(sc, std); 419 splx(s); 420 421 return (std); 422 } 423 424 void 425 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 426 { 427 int s; 428 429 s = splusb(); 430 ohci_hash_rem_td(sc, std); 431 std->nexttd = sc->sc_freetds; 432 sc->sc_freetds = std; 433 splx(s); 434 } 435 436 usbd_status 437 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 438 int alen, int rd, usbd_xfer_handle xfer, 439 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 440 { 441 ohci_soft_td_t *next, *cur; 442 ohci_physaddr_t dataphys, dataphysend; 443 u_int32_t tdflags; 444 int len, curlen; 445 usb_dma_t *dma = &xfer->dmabuf; 446 u_int16_t flags = xfer->flags; 447 448 DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%d\n", alen)); 449 450 len = alen; 451 cur = sp; 452 dataphys = DMAADDR(dma, 0); 453 dataphysend = OHCI_PAGE(dataphys + len - 1); 454 tdflags = htole32( 455 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 456 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 457 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 458 459 for (;;) { 460 next = ohci_alloc_std(sc); 461 if (next == NULL) 462 goto nomem; 463 464 /* The OHCI hardware can handle at most one page crossing. */ 465 if (OHCI_PAGE(dataphys) == dataphysend || 466 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 467 /* we can handle it in this TD */ 468 curlen = len; 469 } else { 470 /* must use multiple TDs, fill as much as possible. */ 471 curlen = 2 * OHCI_PAGE_SIZE - 472 (dataphys & (OHCI_PAGE_SIZE-1)); 473 /* the length must be a multiple of the max size */ 474 curlen -= curlen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize); 475 #ifdef DIAGNOSTIC 476 if (curlen == 0) 477 panic("ohci_alloc_std: curlen == 0"); 478 #endif 479 } 480 DPRINTFN(4,("ohci_alloc_std_chain: dataphys=0x%08x " 481 "dataphysend=0x%08x len=%d curlen=%d\n", 482 dataphys, dataphysend, 483 len, curlen)); 484 len -= curlen; 485 486 cur->td.td_flags = tdflags; 487 cur->td.td_cbp = htole32(dataphys); 488 cur->nexttd = next; 489 cur->td.td_nexttd = htole32(next->physaddr); 490 cur->td.td_be = htole32(dataphys + curlen - 1); 491 cur->len = curlen; 492 cur->flags = OHCI_ADD_LEN; 493 cur->xfer = xfer; 494 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n", 495 dataphys, dataphys + curlen - 1)); 496 if (len == 0) 497 break; 498 DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n")); 499 dataphys += curlen; 500 cur = next; 501 } 502 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 503 alen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize) == 0) { 504 /* Force a 0 length transfer at the end. */ 505 506 cur = next; 507 next = ohci_alloc_std(sc); 508 if (next == NULL) 509 goto nomem; 510 511 cur->td.td_flags = tdflags; 512 cur->td.td_cbp = 0; /* indicate 0 length packet */ 513 cur->nexttd = next; 514 cur->td.td_nexttd = htole32(next->physaddr); 515 cur->td.td_be = ~0; 516 cur->len = 0; 517 cur->flags = 0; 518 cur->xfer = xfer; 519 DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n")); 520 } 521 *ep = cur; 522 523 return (USBD_NORMAL_COMPLETION); 524 525 nomem: 526 /* XXX free chain */ 527 return (USBD_NOMEM); 528 } 529 530 #if 0 531 void 532 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 533 ohci_soft_td_t *stdend) 534 { 535 ohci_soft_td_t *p; 536 537 for (; std != stdend; std = p) { 538 p = std->nexttd; 539 ohci_free_std(sc, std); 540 } 541 } 542 #endif 543 544 ohci_soft_itd_t * 545 ohci_alloc_sitd(ohci_softc_t *sc) 546 { 547 ohci_soft_itd_t *sitd; 548 usbd_status err; 549 int i, s, offs; 550 usb_dma_t dma; 551 552 if (sc->sc_freeitds == NULL) { 553 DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n")); 554 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 555 OHCI_ITD_ALIGN, &dma); 556 if (err) 557 return (NULL); 558 s = splusb(); 559 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 560 offs = i * OHCI_SITD_SIZE; 561 sitd = KERNADDR(&dma, offs); 562 sitd->physaddr = DMAADDR(&dma, offs); 563 sitd->nextitd = sc->sc_freeitds; 564 sc->sc_freeitds = sitd; 565 } 566 splx(s); 567 } 568 569 s = splusb(); 570 sitd = sc->sc_freeitds; 571 sc->sc_freeitds = sitd->nextitd; 572 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 573 sitd->nextitd = NULL; 574 sitd->xfer = NULL; 575 ohci_hash_add_itd(sc, sitd); 576 splx(s); 577 578 #ifdef DIAGNOSTIC 579 sitd->isdone = 0; 580 #endif 581 582 return (sitd); 583 } 584 585 void 586 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 587 { 588 int s; 589 590 DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd)); 591 592 #ifdef DIAGNOSTIC 593 if (!sitd->isdone) { 594 panic("ohci_free_sitd: sitd=%p not done", sitd); 595 return; 596 } 597 /* Warn double free */ 598 sitd->isdone = 0; 599 #endif 600 601 s = splusb(); 602 ohci_hash_rem_itd(sc, sitd); 603 sitd->nextitd = sc->sc_freeitds; 604 sc->sc_freeitds = sitd; 605 splx(s); 606 } 607 608 usbd_status 609 ohci_checkrev(ohci_softc_t *sc) 610 { 611 u_int32_t rev; 612 613 printf(","); 614 rev = OREAD4(sc, OHCI_REVISION); 615 printf(" version %d.%d%s\n", OHCI_REV_HI(rev), OHCI_REV_LO(rev), 616 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 617 618 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 619 printf("%s: unsupported OHCI revision\n", 620 sc->sc_bus.bdev.dv_xname); 621 sc->sc_bus.usbrev = USBREV_UNKNOWN; 622 return (USBD_INVAL); 623 } 624 sc->sc_bus.usbrev = USBREV_1_0; 625 626 return (USBD_NORMAL_COMPLETION); 627 } 628 629 usbd_status 630 ohci_handover(ohci_softc_t *sc) 631 { 632 u_int32_t s, ctl; 633 int i; 634 635 ctl = OREAD4(sc, OHCI_CONTROL); 636 if (ctl & OHCI_IR) { 637 /* SMM active, request change */ 638 DPRINTF(("ohci_handover: SMM active, request owner change\n")); 639 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 640 (OHCI_OC | OHCI_MIE)) 641 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 642 s = OREAD4(sc, OHCI_COMMAND_STATUS); 643 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 644 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 645 usb_delay_ms(&sc->sc_bus, 1); 646 ctl = OREAD4(sc, OHCI_CONTROL); 647 } 648 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 649 if (ctl & OHCI_IR) { 650 printf("%s: SMM does not respond, will reset\n", 651 sc->sc_bus.bdev.dv_xname); 652 } 653 } 654 655 return (USBD_NORMAL_COMPLETION); 656 } 657 658 usbd_status 659 ohci_init(ohci_softc_t *sc) 660 { 661 ohci_soft_ed_t *sed, *psed; 662 usbd_status err; 663 int i; 664 u_int32_t ctl, rwc, ival, hcr, fm, per, desca, descb; 665 666 DPRINTF(("ohci_init: start\n")); 667 668 for (i = 0; i < OHCI_HASH_SIZE; i++) 669 LIST_INIT(&sc->sc_hash_tds[i]); 670 for (i = 0; i < OHCI_HASH_SIZE; i++) 671 LIST_INIT(&sc->sc_hash_itds[i]); 672 673 SIMPLEQ_INIT(&sc->sc_free_xfers); 674 675 /* XXX determine alignment by R/W */ 676 /* Allocate the HCCA area. */ 677 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 678 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 679 if (err) 680 return (err); 681 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 682 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 683 684 sc->sc_eintrs = OHCI_NORMAL_INTRS; 685 686 /* Allocate dummy ED that starts the control list. */ 687 sc->sc_ctrl_head = ohci_alloc_sed(sc); 688 if (sc->sc_ctrl_head == NULL) { 689 err = USBD_NOMEM; 690 goto bad1; 691 } 692 sc->sc_ctrl_head->ed.ed_flags |= htole32(OHCI_ED_SKIP); 693 694 /* Allocate dummy ED that starts the bulk list. */ 695 sc->sc_bulk_head = ohci_alloc_sed(sc); 696 if (sc->sc_bulk_head == NULL) { 697 err = USBD_NOMEM; 698 goto bad2; 699 } 700 sc->sc_bulk_head->ed.ed_flags |= htole32(OHCI_ED_SKIP); 701 702 /* Allocate dummy ED that starts the isochronous list. */ 703 sc->sc_isoc_head = ohci_alloc_sed(sc); 704 if (sc->sc_isoc_head == NULL) { 705 err = USBD_NOMEM; 706 goto bad3; 707 } 708 sc->sc_isoc_head->ed.ed_flags |= htole32(OHCI_ED_SKIP); 709 710 /* Allocate all the dummy EDs that make up the interrupt tree. */ 711 for (i = 0; i < OHCI_NO_EDS; i++) { 712 sed = ohci_alloc_sed(sc); 713 if (sed == NULL) { 714 while (--i >= 0) 715 ohci_free_sed(sc, sc->sc_eds[i]); 716 err = USBD_NOMEM; 717 goto bad4; 718 } 719 /* All ED fields are set to 0. */ 720 sc->sc_eds[i] = sed; 721 sed->ed.ed_flags |= htole32(OHCI_ED_SKIP); 722 if (i != 0) 723 psed = sc->sc_eds[(i-1) / 2]; 724 else 725 psed= sc->sc_isoc_head; 726 sed->next = psed; 727 sed->ed.ed_nexted = htole32(psed->physaddr); 728 } 729 /* 730 * Fill HCCA interrupt table. The bit reversal is to get 731 * the tree set up properly to spread the interrupts. 732 */ 733 for (i = 0; i < OHCI_NO_INTRS; i++) 734 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 735 htole32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 736 737 #ifdef OHCI_DEBUG 738 if (ohcidebug > 15) { 739 for (i = 0; i < OHCI_NO_EDS; i++) { 740 printf("ed#%d ", i); 741 ohci_dump_ed(sc->sc_eds[i]); 742 } 743 printf("iso "); 744 ohci_dump_ed(sc->sc_isoc_head); 745 } 746 #endif 747 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 748 ctl = OREAD4(sc, OHCI_CONTROL); 749 rwc = ctl & OHCI_RWC; 750 fm = OREAD4(sc, OHCI_FM_INTERVAL); 751 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 752 descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 753 754 /* Determine in what context we are running. */ 755 if (ctl & OHCI_IR) { 756 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 757 goto reset; 758 #if 0 759 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 760 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 761 /* BIOS started controller. */ 762 DPRINTF(("ohci_init: BIOS active\n")); 763 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 764 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 765 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 766 } 767 #endif 768 } else { 769 DPRINTF(("ohci_init: cold started\n")); 770 reset: 771 /* Controller was cold started. */ 772 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 773 } 774 775 /* 776 * This reset should not be necessary according to the OHCI spec, but 777 * without it some controllers do not start. 778 */ 779 DPRINTF(("%s: resetting\n", sc->sc_bus.bdev.dv_xname)); 780 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 781 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 782 783 /* We now own the host controller and the bus has been reset. */ 784 785 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 786 /* Nominal time for a reset is 10 us. */ 787 for (i = 0; i < 10; i++) { 788 delay(10); 789 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 790 if (!hcr) 791 break; 792 } 793 if (hcr) { 794 printf("%s: reset timeout\n", sc->sc_bus.bdev.dv_xname); 795 err = USBD_IOERROR; 796 goto bad5; 797 } 798 #ifdef OHCI_DEBUG 799 if (ohcidebug > 15) 800 ohci_dumpregs(sc); 801 #endif 802 803 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 804 805 /* Set up HC registers. */ 806 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 807 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 808 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 809 /* disable all interrupts and then switch on all desired interrupts */ 810 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 811 /* switch on desired functional features */ 812 ctl = OREAD4(sc, OHCI_CONTROL); 813 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 814 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 815 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 816 /* And finally start it! */ 817 OWRITE4(sc, OHCI_CONTROL, ctl); 818 819 /* 820 * The controller is now OPERATIONAL. Set a some final 821 * registers that should be set earlier, but that the 822 * controller ignores when in the SUSPEND state. 823 */ 824 ival = OHCI_GET_IVAL(fm); 825 fm = (OREAD4(sc, OHCI_FM_REMAINING) & OHCI_FIT) ^ OHCI_FIT; 826 fm |= OHCI_FSMPS(ival) | ival; 827 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 828 per = OHCI_PERIODIC(ival); /* 90% periodic */ 829 OWRITE4(sc, OHCI_PERIODIC_START, per); 830 831 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 832 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 833 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 834 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 835 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 836 OWRITE4(sc, OHCI_RH_DESCRIPTOR_B, descb); 837 usb_delay_ms(&sc->sc_bus, OHCI_GET_POTPGT(desca) * UHD_PWRON_FACTOR); 838 839 /* 840 * The AMD756 requires a delay before re-reading the register, 841 * otherwise it will occasionally report 0 ports. 842 */ 843 sc->sc_noport = 0; 844 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 845 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 846 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 847 } 848 849 #ifdef OHCI_DEBUG 850 if (ohcidebug > 5) 851 ohci_dumpregs(sc); 852 #endif 853 854 /* Set up the bus struct. */ 855 sc->sc_bus.methods = &ohci_bus_methods; 856 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 857 858 sc->sc_control = sc->sc_intre = 0; 859 sc->sc_shutdownhook = shutdownhook_establish(ohci_shutdown, sc); 860 861 timeout_set(&sc->sc_tmo_rhsc, ohci_rhsc_enable, sc); 862 863 /* Finally, turn on interrupts. */ 864 DPRINTFN(1,("ohci_init: enabling\n")); 865 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 866 867 return (USBD_NORMAL_COMPLETION); 868 869 bad5: 870 for (i = 0; i < OHCI_NO_EDS; i++) 871 ohci_free_sed(sc, sc->sc_eds[i]); 872 bad4: 873 ohci_free_sed(sc, sc->sc_isoc_head); 874 bad3: 875 ohci_free_sed(sc, sc->sc_bulk_head); 876 bad2: 877 ohci_free_sed(sc, sc->sc_ctrl_head); 878 bad1: 879 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 880 return (err); 881 } 882 883 usbd_status 884 ohci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 885 { 886 struct ohci_softc *sc = (struct ohci_softc *)bus; 887 888 return (usb_allocmem(&sc->sc_bus, size, 0, dma)); 889 } 890 891 void 892 ohci_freem(struct usbd_bus *bus, usb_dma_t *dma) 893 { 894 struct ohci_softc *sc = (struct ohci_softc *)bus; 895 896 usb_freemem(&sc->sc_bus, dma); 897 } 898 899 usbd_xfer_handle 900 ohci_allocx(struct usbd_bus *bus) 901 { 902 struct ohci_softc *sc = (struct ohci_softc *)bus; 903 usbd_xfer_handle xfer; 904 905 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 906 if (xfer != NULL) { 907 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 908 #ifdef DIAGNOSTIC 909 if (xfer->busy_free != XFER_FREE) { 910 printf("ohci_allocx: xfer=%p not free, 0x%08x\n", xfer, 911 xfer->busy_free); 912 } 913 #endif 914 } else { 915 xfer = malloc(sizeof(struct ohci_xfer), M_USB, M_NOWAIT); 916 } 917 if (xfer != NULL) { 918 memset(xfer, 0, sizeof (struct ohci_xfer)); 919 #ifdef DIAGNOSTIC 920 xfer->busy_free = XFER_BUSY; 921 #endif 922 } 923 return (xfer); 924 } 925 926 void 927 ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 928 { 929 struct ohci_softc *sc = (struct ohci_softc *)bus; 930 931 #ifdef DIAGNOSTIC 932 if (xfer->busy_free != XFER_BUSY) { 933 printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 934 xfer->busy_free); 935 return; 936 } 937 xfer->busy_free = XFER_FREE; 938 #endif 939 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 940 } 941 942 /* 943 * Shut down the controller when the system is going down. 944 */ 945 void 946 ohci_shutdown(void *v) 947 { 948 ohci_softc_t *sc = v; 949 950 DPRINTF(("ohci_shutdown: stopping the HC\n")); 951 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 952 } 953 954 /* 955 * Handle suspend/resume. 956 * 957 * We need to switch to polling mode here, because this routine is 958 * called from an interrupt context. This is all right since we 959 * are almost suspended anyway. 960 */ 961 void 962 ohci_power(int why, void *v) 963 { 964 ohci_softc_t *sc = v; 965 u_int32_t reg; 966 int s; 967 968 #ifdef OHCI_DEBUG 969 DPRINTF(("ohci_power: sc=%p, why=%d\n", sc, why)); 970 ohci_dumpregs(sc); 971 #endif 972 973 s = splhardusb(); 974 switch (why) { 975 case PWR_SUSPEND: 976 case PWR_STANDBY: 977 sc->sc_bus.use_polling++; 978 reg = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 979 if (sc->sc_control == 0) { 980 /* 981 * Preserve register values, in case that APM BIOS 982 * does not recover them. 983 */ 984 sc->sc_control = reg; 985 sc->sc_intre = OREAD4(sc, OHCI_INTERRUPT_ENABLE); 986 sc->sc_ival = OHCI_GET_IVAL(OREAD4(sc, 987 OHCI_FM_INTERVAL)); 988 } 989 reg |= OHCI_HCFS_SUSPEND; 990 OWRITE4(sc, OHCI_CONTROL, reg); 991 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 992 sc->sc_bus.use_polling--; 993 break; 994 case PWR_RESUME: 995 sc->sc_bus.use_polling++; 996 997 /* Some broken BIOSes do not recover these values */ 998 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 999 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 1000 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 1001 if (sc->sc_intre) 1002 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, 1003 sc->sc_intre & (OHCI_ALL_INTRS | OHCI_MIE)); 1004 if (sc->sc_control) 1005 reg = sc->sc_control; 1006 else 1007 reg = OREAD4(sc, OHCI_CONTROL); 1008 reg |= OHCI_HCFS_RESUME; 1009 OWRITE4(sc, OHCI_CONTROL, reg); 1010 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1011 reg = (reg & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1012 OWRITE4(sc, OHCI_CONTROL, reg); 1013 1014 reg = (OREAD4(sc, OHCI_FM_REMAINING) & OHCI_FIT) ^ OHCI_FIT; 1015 reg |= OHCI_FSMPS(sc->sc_ival) | sc->sc_ival; 1016 OWRITE4(sc, OHCI_FM_INTERVAL, reg); 1017 OWRITE4(sc, OHCI_PERIODIC_START, OHCI_PERIODIC(sc->sc_ival)); 1018 1019 /* Fiddle the No OverCurrent Protection to avoid a chip bug */ 1020 reg = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 1021 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, reg | OHCI_NOCP); 1022 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 1023 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1024 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, reg); 1025 1026 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1027 sc->sc_control = sc->sc_intre = sc->sc_ival = 0; 1028 sc->sc_bus.use_polling--; 1029 break; 1030 } 1031 splx(s); 1032 } 1033 1034 #ifdef OHCI_DEBUG 1035 void 1036 ohci_dumpregs(ohci_softc_t *sc) 1037 { 1038 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 1039 OREAD4(sc, OHCI_REVISION), 1040 OREAD4(sc, OHCI_CONTROL), 1041 OREAD4(sc, OHCI_COMMAND_STATUS))); 1042 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 1043 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1044 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1045 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 1046 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 1047 OREAD4(sc, OHCI_HCCA), 1048 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1049 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 1050 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 1051 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1052 OREAD4(sc, OHCI_BULK_HEAD_ED), 1053 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 1054 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 1055 OREAD4(sc, OHCI_DONE_HEAD), 1056 OREAD4(sc, OHCI_FM_INTERVAL), 1057 OREAD4(sc, OHCI_FM_REMAINING))); 1058 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 1059 OREAD4(sc, OHCI_FM_NUMBER), 1060 OREAD4(sc, OHCI_PERIODIC_START), 1061 OREAD4(sc, OHCI_LS_THRESHOLD))); 1062 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 1063 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1064 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1065 OREAD4(sc, OHCI_RH_STATUS))); 1066 DPRINTF((" port1=0x%08x port2=0x%08x\n", 1067 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1068 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 1069 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 1070 letoh32(sc->sc_hcca->hcca_frame_number), 1071 letoh32(sc->sc_hcca->hcca_done_head))); 1072 } 1073 #endif 1074 1075 int ohci_intr1(ohci_softc_t *); 1076 1077 int 1078 ohci_intr(void *p) 1079 { 1080 ohci_softc_t *sc = p; 1081 1082 if (sc == NULL || sc->sc_dying) 1083 return (0); 1084 1085 /* If we get an interrupt while polling, then just ignore it. */ 1086 if (!cold && sc->sc_bus.use_polling) { 1087 #ifdef DIAGNOSTIC 1088 static struct timeval ohci_intr_tv; 1089 if ((OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) && 1090 usbd_ratecheck(&ohci_intr_tv)) 1091 DPRINTFN(16, 1092 ("ohci_intr: ignored interrupt while polling\n")); 1093 #endif 1094 return (0); 1095 } 1096 1097 return (ohci_intr1(sc)); 1098 } 1099 1100 int 1101 ohci_intr1(ohci_softc_t *sc) 1102 { 1103 u_int32_t intrs, eintrs; 1104 ohci_physaddr_t done; 1105 1106 DPRINTFN(14,("ohci_intr1: enter\n")); 1107 1108 /* In case the interrupt occurs before initialization has completed. */ 1109 if (sc == NULL || sc->sc_hcca == NULL) { 1110 #ifdef DIAGNOSTIC 1111 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1112 #endif 1113 return (0); 1114 } 1115 1116 intrs = 0; 1117 done = letoh32(sc->sc_hcca->hcca_done_head); 1118 if (done != 0) { 1119 if (done & ~OHCI_DONE_INTRS) 1120 intrs = OHCI_WDH; 1121 if (done & OHCI_DONE_INTRS) 1122 intrs |= OREAD4(sc, OHCI_INTERRUPT_STATUS); 1123 sc->sc_hcca->hcca_done_head = 0; 1124 } else { 1125 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1126 /* If we've flushed out a WDH then reread */ 1127 if (intrs & OHCI_WDH) { 1128 done = letoh32(sc->sc_hcca->hcca_done_head); 1129 sc->sc_hcca->hcca_done_head = 0; 1130 } 1131 } 1132 1133 if (!intrs) 1134 return (0); 1135 1136 intrs &= ~OHCI_MIE; 1137 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs); /* Acknowledge */ 1138 eintrs = intrs & sc->sc_eintrs; 1139 if (!eintrs) 1140 return (0); 1141 1142 sc->sc_bus.intr_context++; 1143 sc->sc_bus.no_intrs++; 1144 DPRINTFN(7, ("ohci_intr: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 1145 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 1146 (u_int)eintrs)); 1147 1148 if (eintrs & OHCI_SO) { 1149 sc->sc_overrun_cnt++; 1150 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1151 printf("%s: %u scheduling overruns\n", 1152 sc->sc_bus.bdev.dv_xname, sc->sc_overrun_cnt); 1153 sc->sc_overrun_cnt = 0; 1154 } 1155 /* XXX do what */ 1156 eintrs &= ~OHCI_SO; 1157 } 1158 if (eintrs & OHCI_WDH) { 1159 ohci_add_done(sc, done &~ OHCI_DONE_INTRS); 1160 usb_schedsoftintr(&sc->sc_bus); 1161 eintrs &= ~OHCI_WDH; 1162 } 1163 if (eintrs & OHCI_RD) { 1164 printf("%s: resume detect\n", sc->sc_bus.bdev.dv_xname); 1165 /* XXX process resume detect */ 1166 } 1167 if (eintrs & OHCI_UE) { 1168 printf("%s: unrecoverable error, controller halted\n", 1169 sc->sc_bus.bdev.dv_xname); 1170 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1171 /* XXX what else */ 1172 } 1173 if (eintrs & OHCI_RHSC) { 1174 ohci_rhsc(sc, sc->sc_intrxfer); 1175 /* 1176 * Disable RHSC interrupt for now, because it will be 1177 * on until the port has been reset. 1178 */ 1179 ohci_rhsc_able(sc, 0); 1180 DPRINTFN(2, ("%s: rhsc interrupt disabled\n", 1181 sc->sc_bus.bdev.dv_xname)); 1182 1183 /* Do not allow RHSC interrupts > 1 per second */ 1184 timeout_add_sec(&sc->sc_tmo_rhsc, 1); 1185 eintrs &= ~OHCI_RHSC; 1186 } 1187 1188 sc->sc_bus.intr_context--; 1189 1190 if (eintrs != 0) { 1191 /* Block unprocessed interrupts. XXX */ 1192 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1193 sc->sc_eintrs &= ~eintrs; 1194 printf("%s: blocking intrs 0x%x\n", 1195 sc->sc_bus.bdev.dv_xname, eintrs); 1196 } 1197 1198 return (1); 1199 } 1200 1201 void 1202 ohci_rhsc_able(ohci_softc_t *sc, int on) 1203 { 1204 DPRINTFN(4, ("ohci_rhsc_able: on=%d\n", on)); 1205 if (on) { 1206 sc->sc_eintrs |= OHCI_RHSC; 1207 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1208 } else { 1209 sc->sc_eintrs &= ~OHCI_RHSC; 1210 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC); 1211 } 1212 } 1213 1214 void 1215 ohci_rhsc_enable(void *v_sc) 1216 { 1217 ohci_softc_t *sc = v_sc; 1218 int s; 1219 1220 s = splhardusb(); 1221 ohci_rhsc(sc, sc->sc_intrxfer); 1222 DPRINTFN(2, ("%s: rhsc interrupt enabled\n", 1223 sc->sc_bus.bdev.dv_xname)); 1224 1225 ohci_rhsc_able(sc, 1); 1226 splx(s); 1227 } 1228 1229 #ifdef OHCI_DEBUG 1230 char *ohci_cc_strs[] = { 1231 "NO_ERROR", 1232 "CRC", 1233 "BIT_STUFFING", 1234 "DATA_TOGGLE_MISMATCH", 1235 "STALL", 1236 "DEVICE_NOT_RESPONDING", 1237 "PID_CHECK_FAILURE", 1238 "UNEXPECTED_PID", 1239 "DATA_OVERRUN", 1240 "DATA_UNDERRUN", 1241 "BUFFER_OVERRUN", 1242 "BUFFER_UNDERRUN", 1243 "reserved", 1244 "reserved", 1245 "NOT_ACCESSED", 1246 "NOT_ACCESSED", 1247 }; 1248 #endif 1249 1250 void 1251 ohci_add_done(ohci_softc_t *sc, ohci_physaddr_t done) 1252 { 1253 ohci_soft_itd_t *sitd, *sidone, **ip; 1254 ohci_soft_td_t *std, *sdone, **p; 1255 1256 /* Reverse the done list. */ 1257 for (sdone = NULL, sidone = NULL; done != 0; ) { 1258 std = ohci_hash_find_td(sc, done); 1259 if (std != NULL) { 1260 std->dnext = sdone; 1261 done = letoh32(std->td.td_nexttd); 1262 sdone = std; 1263 DPRINTFN(10,("add TD %p\n", std)); 1264 continue; 1265 } 1266 sitd = ohci_hash_find_itd(sc, done); 1267 if (sitd != NULL) { 1268 sitd->dnext = sidone; 1269 done = letoh32(sitd->itd.itd_nextitd); 1270 sidone = sitd; 1271 DPRINTFN(5,("add ITD %p\n", sitd)); 1272 continue; 1273 } 1274 panic("ohci_add_done: addr 0x%08lx not found", (u_long)done); 1275 } 1276 1277 /* sdone & sidone now hold the done lists. */ 1278 /* Put them on the already processed lists. */ 1279 for (p = &sc->sc_sdone; *p != NULL; p = &(*p)->dnext) 1280 ; 1281 *p = sdone; 1282 for (ip = &sc->sc_sidone; *ip != NULL; ip = &(*ip)->dnext) 1283 ; 1284 *ip = sidone; 1285 } 1286 1287 void 1288 ohci_softintr(void *v) 1289 { 1290 ohci_softc_t *sc = v; 1291 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1292 ohci_soft_td_t *std, *sdone, *stdnext; 1293 usbd_xfer_handle xfer; 1294 struct ohci_pipe *opipe; 1295 int len, cc, s; 1296 int i, j, actlen, iframes, uedir; 1297 1298 DPRINTFN(10,("ohci_softintr: enter\n")); 1299 1300 sc->sc_bus.intr_context++; 1301 1302 s = splhardusb(); 1303 sdone = sc->sc_sdone; 1304 sc->sc_sdone = NULL; 1305 sidone = sc->sc_sidone; 1306 sc->sc_sidone = NULL; 1307 splx(s); 1308 1309 DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone)); 1310 1311 #ifdef OHCI_DEBUG 1312 if (ohcidebug > 10) { 1313 DPRINTF(("ohci_process_done: TD done:\n")); 1314 ohci_dump_tds(sdone); 1315 } 1316 #endif 1317 1318 for (std = sdone; std; std = stdnext) { 1319 xfer = std->xfer; 1320 stdnext = std->dnext; 1321 DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n", 1322 std, xfer, xfer ? xfer->hcpriv : 0)); 1323 if (xfer == NULL) { 1324 /* 1325 * xfer == NULL: There seems to be no xfer associated 1326 * with this TD. It is tailp that happened to end up on 1327 * the done queue. 1328 * Shouldn't happen, but some chips are broken(?). 1329 */ 1330 continue; 1331 } 1332 if (xfer->status == USBD_CANCELLED || 1333 xfer->status == USBD_TIMEOUT) { 1334 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1335 xfer)); 1336 /* Handled by abort routine. */ 1337 continue; 1338 } 1339 timeout_del(&xfer->timeout_handle); 1340 1341 len = std->len; 1342 if (std->td.td_cbp != 0) 1343 len -= letoh32(std->td.td_be) - 1344 letoh32(std->td.td_cbp) + 1; 1345 DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len, 1346 std->flags)); 1347 if (std->flags & OHCI_ADD_LEN) 1348 xfer->actlen += len; 1349 1350 cc = OHCI_TD_GET_CC(letoh32(std->td.td_flags)); 1351 if (cc == OHCI_CC_NO_ERROR) { 1352 if (std->flags & OHCI_CALL_DONE) { 1353 xfer->status = USBD_NORMAL_COMPLETION; 1354 s = splusb(); 1355 usb_transfer_complete(xfer); 1356 splx(s); 1357 } 1358 ohci_free_std(sc, std); 1359 } else { 1360 /* 1361 * Endpoint is halted. First unlink all the TDs 1362 * belonging to the failed transfer, and then restart 1363 * the endpoint. 1364 */ 1365 ohci_soft_td_t *p, *n; 1366 opipe = (struct ohci_pipe *)xfer->pipe; 1367 1368 DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n", 1369 OHCI_TD_GET_CC(letoh32(std->td.td_flags)), 1370 ohci_cc_strs[OHCI_TD_GET_CC(letoh32(std->td.td_flags))])); 1371 1372 /* remove TDs */ 1373 for (p = std; p->xfer == xfer; p = n) { 1374 n = p->nexttd; 1375 ohci_free_std(sc, p); 1376 } 1377 1378 /* clear halt */ 1379 opipe->sed->ed.ed_headp = htole32(p->physaddr); 1380 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1381 1382 if (cc == OHCI_CC_STALL) 1383 xfer->status = USBD_STALLED; 1384 else 1385 xfer->status = USBD_IOERROR; 1386 s = splusb(); 1387 usb_transfer_complete(xfer); 1388 splx(s); 1389 } 1390 } 1391 1392 #ifdef OHCI_DEBUG 1393 if (ohcidebug > 10) { 1394 DPRINTF(("ohci_softintr: ITD done:\n")); 1395 ohci_dump_itds(sidone); 1396 } 1397 #endif 1398 1399 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1400 xfer = sitd->xfer; 1401 sitdnext = sitd->dnext; 1402 DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n", 1403 sitd, xfer, xfer ? xfer->hcpriv : 0)); 1404 if (xfer == NULL) 1405 continue; 1406 if (xfer->status == USBD_CANCELLED || 1407 xfer->status == USBD_TIMEOUT) { 1408 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1409 xfer)); 1410 /* Handled by abort routine. */ 1411 continue; 1412 } 1413 #ifdef DIAGNOSTIC 1414 if (sitd->isdone) 1415 printf("ohci_softintr: sitd=%p is done\n", sitd); 1416 sitd->isdone = 1; 1417 #endif 1418 if (sitd->flags & OHCI_CALL_DONE) { 1419 ohci_soft_itd_t *next; 1420 1421 opipe = (struct ohci_pipe *)xfer->pipe; 1422 opipe->u.iso.inuse -= xfer->nframes; 1423 uedir = UE_GET_DIR(xfer->pipe->endpoint->edesc-> 1424 bEndpointAddress); 1425 xfer->status = USBD_NORMAL_COMPLETION; 1426 actlen = 0; 1427 for (i = 0, sitd = xfer->hcpriv;; 1428 sitd = next) { 1429 next = sitd->nextitd; 1430 if (OHCI_ITD_GET_CC(letoh32(sitd-> 1431 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1432 xfer->status = USBD_IOERROR; 1433 /* For input, update frlengths with actual */ 1434 /* XXX anything necessary for output? */ 1435 if (uedir == UE_DIR_IN && 1436 xfer->status == USBD_NORMAL_COMPLETION) { 1437 iframes = OHCI_ITD_GET_FC(letoh32( 1438 sitd->itd.itd_flags)); 1439 for (j = 0; j < iframes; i++, j++) { 1440 len = letoh16(sitd-> 1441 itd.itd_offset[j]); 1442 if ((OHCI_ITD_PSW_GET_CC(len) & 1443 OHCI_CC_NOT_ACCESSED_MASK) 1444 == OHCI_CC_NOT_ACCESSED) 1445 len = 0; 1446 else 1447 len = OHCI_ITD_PSW_LENGTH(len); 1448 xfer->frlengths[i] = len; 1449 actlen += len; 1450 } 1451 } 1452 if (sitd->flags & OHCI_CALL_DONE) 1453 break; 1454 ohci_free_sitd(sc, sitd); 1455 } 1456 ohci_free_sitd(sc, sitd); 1457 if (uedir == UE_DIR_IN && 1458 xfer->status == USBD_NORMAL_COMPLETION) 1459 xfer->actlen = actlen; 1460 xfer->hcpriv = NULL; 1461 1462 s = splusb(); 1463 usb_transfer_complete(xfer); 1464 splx(s); 1465 } 1466 } 1467 1468 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 1469 if (sc->sc_softwake) { 1470 sc->sc_softwake = 0; 1471 wakeup(&sc->sc_softwake); 1472 } 1473 #endif /* __HAVE_GENERIC_SOFT_INTERRUPTS */ 1474 1475 sc->sc_bus.intr_context--; 1476 DPRINTFN(10,("ohci_softintr: done:\n")); 1477 } 1478 1479 void 1480 ohci_device_ctrl_done(usbd_xfer_handle xfer) 1481 { 1482 DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer)); 1483 1484 #ifdef DIAGNOSTIC 1485 if (!(xfer->rqflags & URQ_REQUEST)) { 1486 panic("ohci_device_ctrl_done: not a request"); 1487 } 1488 #endif 1489 } 1490 1491 void 1492 ohci_device_intr_done(usbd_xfer_handle xfer) 1493 { 1494 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1495 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 1496 ohci_soft_ed_t *sed = opipe->sed; 1497 ohci_soft_td_t *data, *tail; 1498 1499 1500 DPRINTFN(10, ("ohci_device_intr_done: xfer=%p, actlen=%d\n", xfer, 1501 xfer->actlen)); 1502 1503 if (xfer->pipe->repeat) { 1504 data = opipe->tail.td; 1505 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1506 if (tail == NULL) { 1507 xfer->status = USBD_NOMEM; 1508 return; 1509 } 1510 tail->xfer = NULL; 1511 1512 data->td.td_flags = htole32( 1513 OHCI_TD_IN | OHCI_TD_NOCC | 1514 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1515 if (xfer->flags & USBD_SHORT_XFER_OK) 1516 data->td.td_flags |= htole32(OHCI_TD_R); 1517 data->td.td_cbp = htole32(DMAADDR(&xfer->dmabuf, 0)); 1518 data->nexttd = tail; 1519 data->td.td_nexttd = htole32(tail->physaddr); 1520 data->td.td_be = htole32(letoh32(data->td.td_cbp) + 1521 xfer->length - 1); 1522 data->len = xfer->length; 1523 data->xfer = xfer; 1524 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1525 xfer->hcpriv = data; 1526 xfer->actlen = 0; 1527 1528 sed->ed.ed_tailp = htole32(tail->physaddr); 1529 opipe->tail.td = tail; 1530 } 1531 } 1532 1533 void 1534 ohci_device_bulk_done(usbd_xfer_handle xfer) 1535 { 1536 DPRINTFN(10, ("ohci_device_bulk_done: xfer=%p, actlen=%d\n", xfer, 1537 xfer->actlen)); 1538 } 1539 1540 void 1541 ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer) 1542 { 1543 usbd_pipe_handle pipe; 1544 u_char *p; 1545 int i, m; 1546 int hstatus; 1547 1548 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1549 DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n", 1550 sc, xfer, hstatus)); 1551 1552 if (xfer == NULL) { 1553 /* Just ignore the change. */ 1554 return; 1555 } 1556 1557 pipe = xfer->pipe; 1558 1559 p = KERNADDR(&xfer->dmabuf, 0); 1560 m = min(sc->sc_noport, xfer->length * 8 - 1); 1561 memset(p, 0, xfer->length); 1562 for (i = 1; i <= m; i++) { 1563 /* Pick out CHANGE bits from the status reg. */ 1564 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1565 p[i/8] |= 1 << (i%8); 1566 } 1567 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 1568 xfer->actlen = xfer->length; 1569 xfer->status = USBD_NORMAL_COMPLETION; 1570 1571 usb_transfer_complete(xfer); 1572 } 1573 1574 void 1575 ohci_root_intr_done(usbd_xfer_handle xfer) 1576 { 1577 } 1578 1579 void 1580 ohci_root_ctrl_done(usbd_xfer_handle xfer) 1581 { 1582 } 1583 1584 /* 1585 * Wait here until controller claims to have an interrupt. 1586 * Then call ohci_intr and return. Use timeout to avoid waiting 1587 * too long. 1588 */ 1589 void 1590 ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer) 1591 { 1592 int timo; 1593 u_int32_t intrs; 1594 1595 xfer->status = USBD_IN_PROGRESS; 1596 for (timo = xfer->timeout; timo >= 0; timo--) { 1597 usb_delay_ms(&sc->sc_bus, 1); 1598 if (sc->sc_dying) 1599 break; 1600 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1601 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 1602 #ifdef OHCI_DEBUG 1603 if (ohcidebug > 15) 1604 ohci_dumpregs(sc); 1605 #endif 1606 if (intrs) { 1607 ohci_intr1(sc); 1608 if (xfer->status != USBD_IN_PROGRESS) 1609 return; 1610 } 1611 } 1612 1613 /* Timeout */ 1614 DPRINTF(("ohci_waitintr: timeout\n")); 1615 xfer->status = USBD_TIMEOUT; 1616 usb_transfer_complete(xfer); 1617 /* XXX should free TD */ 1618 } 1619 1620 void 1621 ohci_poll(struct usbd_bus *bus) 1622 { 1623 ohci_softc_t *sc = (ohci_softc_t *)bus; 1624 #ifdef OHCI_DEBUG 1625 static int last; 1626 int new; 1627 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1628 if (new != last) { 1629 DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new)); 1630 last = new; 1631 } 1632 #endif 1633 1634 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) 1635 ohci_intr1(sc); 1636 } 1637 1638 usbd_status 1639 ohci_device_request(usbd_xfer_handle xfer) 1640 { 1641 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1642 usb_device_request_t *req = &xfer->request; 1643 usbd_device_handle dev = opipe->pipe.device; 1644 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 1645 int addr = dev->address; 1646 ohci_soft_td_t *setup, *stat, *next, *tail; 1647 ohci_soft_ed_t *sed; 1648 int isread; 1649 int len; 1650 usbd_status err; 1651 int s; 1652 1653 isread = req->bmRequestType & UT_READ; 1654 len = UGETW(req->wLength); 1655 1656 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 1657 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 1658 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1659 UGETW(req->wIndex), len, addr, 1660 opipe->pipe.endpoint->edesc->bEndpointAddress)); 1661 1662 setup = opipe->tail.td; 1663 stat = ohci_alloc_std(sc); 1664 if (stat == NULL) { 1665 err = USBD_NOMEM; 1666 goto bad1; 1667 } 1668 tail = ohci_alloc_std(sc); 1669 if (tail == NULL) { 1670 err = USBD_NOMEM; 1671 goto bad2; 1672 } 1673 tail->xfer = NULL; 1674 1675 sed = opipe->sed; 1676 opipe->u.ctl.length = len; 1677 1678 /* Update device address and length since they may have changed 1679 during the setup of the control pipe in usbd_new_device(). */ 1680 /* XXX This only needs to be done once, but it's too early in open. */ 1681 /* XXXX Should not touch ED here! */ 1682 sed->ed.ed_flags = htole32( 1683 (letoh32(sed->ed.ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) | 1684 OHCI_ED_SET_FA(addr) | 1685 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize))); 1686 1687 next = stat; 1688 1689 /* Set up data transaction */ 1690 if (len != 0) { 1691 ohci_soft_td_t *std = stat; 1692 1693 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 1694 std, &stat); 1695 stat = stat->nexttd; /* point at free TD */ 1696 if (err) 1697 goto bad3; 1698 /* Start toggle at 1 and then use the carried toggle. */ 1699 std->td.td_flags &= htole32(~OHCI_TD_TOGGLE_MASK); 1700 std->td.td_flags |= htole32(OHCI_TD_TOGGLE_1); 1701 } 1702 1703 memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req); 1704 1705 setup->td.td_flags = htole32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1706 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1707 setup->td.td_cbp = htole32(DMAADDR(&opipe->u.ctl.reqdma, 0)); 1708 setup->nexttd = next; 1709 setup->td.td_nexttd = htole32(next->physaddr); 1710 setup->td.td_be = htole32(letoh32(setup->td.td_cbp) + sizeof *req - 1); 1711 setup->len = 0; 1712 setup->xfer = xfer; 1713 setup->flags = 0; 1714 xfer->hcpriv = setup; 1715 1716 stat->td.td_flags = htole32( 1717 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 1718 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1719 stat->td.td_cbp = 0; 1720 stat->nexttd = tail; 1721 stat->td.td_nexttd = htole32(tail->physaddr); 1722 stat->td.td_be = 0; 1723 stat->flags = OHCI_CALL_DONE; 1724 stat->len = 0; 1725 stat->xfer = xfer; 1726 1727 #ifdef OHCI_DEBUG 1728 if (ohcidebug > 5) { 1729 DPRINTF(("ohci_device_request:\n")); 1730 ohci_dump_ed(sed); 1731 ohci_dump_tds(setup); 1732 } 1733 #endif 1734 1735 /* Insert ED in schedule */ 1736 s = splusb(); 1737 sed->ed.ed_tailp = htole32(tail->physaddr); 1738 opipe->tail.td = tail; 1739 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1740 if (xfer->timeout && !sc->sc_bus.use_polling) { 1741 timeout_del(&xfer->timeout_handle); 1742 timeout_set(&xfer->timeout_handle, ohci_timeout, xfer); 1743 timeout_add(&xfer->timeout_handle, mstohz(xfer->timeout)); 1744 } 1745 splx(s); 1746 1747 #ifdef OHCI_DEBUG 1748 if (ohcidebug > 20) { 1749 delay(10000); 1750 DPRINTF(("ohci_device_request: status=%x\n", 1751 OREAD4(sc, OHCI_COMMAND_STATUS))); 1752 ohci_dumpregs(sc); 1753 printf("ctrl head:\n"); 1754 ohci_dump_ed(sc->sc_ctrl_head); 1755 printf("sed:\n"); 1756 ohci_dump_ed(sed); 1757 ohci_dump_tds(setup); 1758 } 1759 #endif 1760 1761 return (USBD_NORMAL_COMPLETION); 1762 1763 bad3: 1764 ohci_free_std(sc, tail); 1765 bad2: 1766 ohci_free_std(sc, stat); 1767 bad1: 1768 return (err); 1769 } 1770 1771 /* 1772 * Add an ED to the schedule. Called at splusb(). 1773 */ 1774 void 1775 ohci_add_ed(ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1776 { 1777 DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head)); 1778 1779 SPLUSBCHECK; 1780 sed->next = head->next; 1781 sed->ed.ed_nexted = head->ed.ed_nexted; 1782 head->next = sed; 1783 head->ed.ed_nexted = htole32(sed->physaddr); 1784 } 1785 1786 /* 1787 * Remove an ED from the schedule. Called at splusb(). 1788 */ 1789 void 1790 ohci_rem_ed(ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1791 { 1792 ohci_soft_ed_t *p; 1793 1794 SPLUSBCHECK; 1795 1796 /* XXX */ 1797 for (p = head; p != NULL && p->next != sed; p = p->next) 1798 ; 1799 if (p == NULL) 1800 panic("ohci_rem_ed: ED not found"); 1801 p->next = sed->next; 1802 p->ed.ed_nexted = sed->ed.ed_nexted; 1803 } 1804 1805 /* 1806 * When a transfer is completed the TD is added to the done queue by 1807 * the host controller. This queue is the processed by software. 1808 * Unfortunately the queue contains the physical address of the TD 1809 * and we have no simple way to translate this back to a kernel address. 1810 * To make the translation possible (and fast) we use a hash table of 1811 * TDs currently in the schedule. The physical address is used as the 1812 * hash value. 1813 */ 1814 1815 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1816 /* Called at splusb() */ 1817 void 1818 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1819 { 1820 int h = HASH(std->physaddr); 1821 1822 SPLUSBCHECK; 1823 1824 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1825 } 1826 1827 /* Called at splusb() */ 1828 void 1829 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1830 { 1831 SPLUSBCHECK; 1832 1833 LIST_REMOVE(std, hnext); 1834 } 1835 1836 ohci_soft_td_t * 1837 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1838 { 1839 int h = HASH(a); 1840 ohci_soft_td_t *std; 1841 1842 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1843 std != NULL; 1844 std = LIST_NEXT(std, hnext)) 1845 if (std->physaddr == a) 1846 return (std); 1847 return (NULL); 1848 } 1849 1850 /* Called at splusb() */ 1851 void 1852 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1853 { 1854 int h = HASH(sitd->physaddr); 1855 1856 SPLUSBCHECK; 1857 1858 DPRINTFN(10,("ohci_hash_add_itd: sitd=%p physaddr=0x%08lx\n", 1859 sitd, (u_long)sitd->physaddr)); 1860 1861 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1862 } 1863 1864 /* Called at splusb() */ 1865 void 1866 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1867 { 1868 SPLUSBCHECK; 1869 1870 DPRINTFN(10,("ohci_hash_rem_itd: sitd=%p physaddr=0x%08lx\n", 1871 sitd, (u_long)sitd->physaddr)); 1872 1873 LIST_REMOVE(sitd, hnext); 1874 } 1875 1876 ohci_soft_itd_t * 1877 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1878 { 1879 int h = HASH(a); 1880 ohci_soft_itd_t *sitd; 1881 1882 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1883 sitd != NULL; 1884 sitd = LIST_NEXT(sitd, hnext)) 1885 if (sitd->physaddr == a) 1886 return (sitd); 1887 return (NULL); 1888 } 1889 1890 void 1891 ohci_timeout(void *addr) 1892 { 1893 struct ohci_xfer *oxfer = addr; 1894 struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.pipe; 1895 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 1896 1897 DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer)); 1898 1899 if (sc->sc_dying) { 1900 ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT); 1901 return; 1902 } 1903 1904 /* Execute the abort in a process context. */ 1905 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr); 1906 usb_add_task(oxfer->xfer.pipe->device, &oxfer->abort_task); 1907 } 1908 1909 void 1910 ohci_timeout_task(void *addr) 1911 { 1912 usbd_xfer_handle xfer = addr; 1913 int s; 1914 1915 DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer)); 1916 1917 s = splusb(); 1918 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1919 splx(s); 1920 } 1921 1922 #ifdef OHCI_DEBUG 1923 void 1924 ohci_dump_tds(ohci_soft_td_t *std) 1925 { 1926 for (; std; std = std->nexttd) 1927 ohci_dump_td(std); 1928 } 1929 1930 void 1931 ohci_dump_td(ohci_soft_td_t *std) 1932 { 1933 char sbuf[128]; 1934 1935 bitmask_snprintf((u_int32_t)letoh32(std->td.td_flags), 1936 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 1937 sbuf, sizeof(sbuf)); 1938 1939 printf("TD(%p) at %08lx: %s delay=%d ec=%d cc=%d\ncbp=0x%08lx " 1940 "nexttd=0x%08lx be=0x%08lx\n", 1941 std, (u_long)std->physaddr, sbuf, 1942 OHCI_TD_GET_DI(letoh32(std->td.td_flags)), 1943 OHCI_TD_GET_EC(letoh32(std->td.td_flags)), 1944 OHCI_TD_GET_CC(letoh32(std->td.td_flags)), 1945 (u_long)letoh32(std->td.td_cbp), 1946 (u_long)letoh32(std->td.td_nexttd), 1947 (u_long)letoh32(std->td.td_be)); 1948 } 1949 1950 void 1951 ohci_dump_itd(ohci_soft_itd_t *sitd) 1952 { 1953 int i; 1954 1955 printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n" 1956 "bp0=0x%08lx next=0x%08lx be=0x%08lx\n", 1957 sitd, (u_long)sitd->physaddr, 1958 OHCI_ITD_GET_SF(letoh32(sitd->itd.itd_flags)), 1959 OHCI_ITD_GET_DI(letoh32(sitd->itd.itd_flags)), 1960 OHCI_ITD_GET_FC(letoh32(sitd->itd.itd_flags)), 1961 OHCI_ITD_GET_CC(letoh32(sitd->itd.itd_flags)), 1962 (u_long)letoh32(sitd->itd.itd_bp0), 1963 (u_long)letoh32(sitd->itd.itd_nextitd), 1964 (u_long)letoh32(sitd->itd.itd_be)); 1965 for (i = 0; i < OHCI_ITD_NOFFSET; i++) 1966 printf("offs[%d]=0x%04x ", i, 1967 (u_int)letoh16(sitd->itd.itd_offset[i])); 1968 printf("\n"); 1969 } 1970 1971 void 1972 ohci_dump_itds(ohci_soft_itd_t *sitd) 1973 { 1974 for (; sitd; sitd = sitd->nextitd) 1975 ohci_dump_itd(sitd); 1976 } 1977 1978 void 1979 ohci_dump_ed(ohci_soft_ed_t *sed) 1980 { 1981 char sbuf[128], sbuf2[128]; 1982 1983 bitmask_snprintf((u_int32_t)letoh32(sed->ed.ed_flags), 1984 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 1985 sbuf, sizeof(sbuf)); 1986 bitmask_snprintf((u_int32_t)letoh32(sed->ed.ed_headp), 1987 "\20\1HALT\2CARRY", sbuf2, sizeof(sbuf2)); 1988 1989 printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\n" 1990 "tailp=0x%08lx headflags=%s headp=0x%08lx nexted=0x%08lx\n", 1991 sed, (u_long)sed->physaddr, 1992 OHCI_ED_GET_FA(letoh32(sed->ed.ed_flags)), 1993 OHCI_ED_GET_EN(letoh32(sed->ed.ed_flags)), 1994 OHCI_ED_GET_MAXP(letoh32(sed->ed.ed_flags)), sbuf, 1995 (u_long)letoh32(sed->ed.ed_tailp), sbuf2, 1996 (u_long)letoh32(sed->ed.ed_headp), 1997 (u_long)letoh32(sed->ed.ed_nexted)); 1998 } 1999 #endif 2000 2001 usbd_status 2002 ohci_open(usbd_pipe_handle pipe) 2003 { 2004 usbd_device_handle dev = pipe->device; 2005 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 2006 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 2007 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2008 u_int8_t addr = dev->address; 2009 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2010 ohci_soft_ed_t *sed; 2011 ohci_soft_td_t *std; 2012 ohci_soft_itd_t *sitd; 2013 ohci_physaddr_t tdphys; 2014 u_int32_t fmt; 2015 usbd_status err; 2016 int s; 2017 int ival; 2018 2019 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 2020 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 2021 2022 if (sc->sc_dying) 2023 return (USBD_IOERROR); 2024 2025 std = NULL; 2026 sed = NULL; 2027 2028 if (addr == sc->sc_addr) { 2029 switch (ed->bEndpointAddress) { 2030 case USB_CONTROL_ENDPOINT: 2031 pipe->methods = &ohci_root_ctrl_methods; 2032 break; 2033 case UE_DIR_IN | OHCI_INTR_ENDPT: 2034 pipe->methods = &ohci_root_intr_methods; 2035 break; 2036 default: 2037 return (USBD_INVAL); 2038 } 2039 } else { 2040 sed = ohci_alloc_sed(sc); 2041 if (sed == NULL) 2042 goto bad0; 2043 opipe->sed = sed; 2044 if (xfertype == UE_ISOCHRONOUS) { 2045 sitd = ohci_alloc_sitd(sc); 2046 if (sitd == NULL) 2047 goto bad1; 2048 opipe->tail.itd = sitd; 2049 tdphys = sitd->physaddr; 2050 fmt = OHCI_ED_FORMAT_ISO; 2051 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2052 fmt |= OHCI_ED_DIR_IN; 2053 else 2054 fmt |= OHCI_ED_DIR_OUT; 2055 } else { 2056 std = ohci_alloc_std(sc); 2057 if (std == NULL) 2058 goto bad1; 2059 opipe->tail.td = std; 2060 tdphys = std->physaddr; 2061 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2062 } 2063 sed->ed.ed_flags = htole32( 2064 OHCI_ED_SET_FA(addr) | 2065 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2066 (dev->speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2067 fmt | OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2068 sed->ed.ed_headp = htole32(tdphys | 2069 (pipe->endpoint->savedtoggle ? OHCI_TOGGLECARRY : 0)); 2070 sed->ed.ed_tailp = htole32(tdphys); 2071 2072 switch (xfertype) { 2073 case UE_CONTROL: 2074 pipe->methods = &ohci_device_ctrl_methods; 2075 err = usb_allocmem(&sc->sc_bus, 2076 sizeof(usb_device_request_t), 2077 0, &opipe->u.ctl.reqdma); 2078 if (err) 2079 goto bad; 2080 s = splusb(); 2081 ohci_add_ed(sed, sc->sc_ctrl_head); 2082 splx(s); 2083 break; 2084 case UE_INTERRUPT: 2085 pipe->methods = &ohci_device_intr_methods; 2086 ival = pipe->interval; 2087 if (ival == USBD_DEFAULT_INTERVAL) 2088 ival = ed->bInterval; 2089 return (ohci_device_setintr(sc, opipe, ival)); 2090 case UE_ISOCHRONOUS: 2091 pipe->methods = &ohci_device_isoc_methods; 2092 return (ohci_setup_isoc(pipe)); 2093 case UE_BULK: 2094 pipe->methods = &ohci_device_bulk_methods; 2095 s = splusb(); 2096 ohci_add_ed(sed, sc->sc_bulk_head); 2097 splx(s); 2098 break; 2099 } 2100 } 2101 return (USBD_NORMAL_COMPLETION); 2102 2103 bad: 2104 if (std != NULL) 2105 ohci_free_std(sc, std); 2106 bad1: 2107 if (sed != NULL) 2108 ohci_free_sed(sc, sed); 2109 bad0: 2110 return (USBD_NOMEM); 2111 2112 } 2113 2114 /* 2115 * Close a reqular pipe. 2116 * Assumes that there are no pending transactions. 2117 */ 2118 void 2119 ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head) 2120 { 2121 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2122 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2123 ohci_soft_ed_t *sed = opipe->sed; 2124 int s; 2125 2126 s = splusb(); 2127 #ifdef DIAGNOSTIC 2128 sed->ed.ed_flags |= htole32(OHCI_ED_SKIP); 2129 if ((letoh32(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2130 (letoh32(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2131 ohci_soft_td_t *std; 2132 std = ohci_hash_find_td(sc, letoh32(sed->ed.ed_headp)); 2133 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2134 "tl=0x%x pipe=%p, std=%p\n", sed, 2135 (int)letoh32(sed->ed.ed_headp), 2136 (int)letoh32(sed->ed.ed_tailp), 2137 pipe, std); 2138 #ifdef USB_DEBUG 2139 usbd_dump_pipe(&opipe->pipe); 2140 #endif 2141 #ifdef OHCI_DEBUG 2142 ohci_dump_ed(sed); 2143 if (std) 2144 ohci_dump_td(std); 2145 #endif 2146 usb_delay_ms(&sc->sc_bus, 2); 2147 if ((letoh32(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2148 (letoh32(sed->ed.ed_headp) & OHCI_HEADMASK)) 2149 printf("ohci_close_pipe: pipe still not empty\n"); 2150 } 2151 #endif 2152 ohci_rem_ed(sed, head); 2153 /* Make sure the host controller is not touching this ED */ 2154 usb_delay_ms(&sc->sc_bus, 1); 2155 splx(s); 2156 pipe->endpoint->savedtoggle = 2157 (letoh32(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2158 ohci_free_sed(sc, opipe->sed); 2159 } 2160 2161 /* 2162 * Abort a device request. 2163 * If this routine is called at splusb() it guarantees that the request 2164 * will be removed from the hardware scheduling and that the callback 2165 * for it will be called with USBD_CANCELLED status. 2166 * It's impossible to guarantee that the requested transfer will not 2167 * have happened since the hardware runs concurrently. 2168 * If the transaction has already happened we rely on the ordinary 2169 * interrupt processing to process it. 2170 */ 2171 void 2172 ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2173 { 2174 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2175 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 2176 ohci_soft_ed_t *sed = opipe->sed; 2177 ohci_soft_td_t *p, *n; 2178 ohci_physaddr_t headp; 2179 int s, hit; 2180 2181 DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe, 2182 sed)); 2183 2184 if (sc->sc_dying) { 2185 /* If we're dying, just do the software part. */ 2186 s = splusb(); 2187 xfer->status = status; /* make software ignore it */ 2188 timeout_del(&xfer->timeout_handle); 2189 usb_transfer_complete(xfer); 2190 splx(s); 2191 return; 2192 } 2193 2194 if (xfer->device->bus->intr_context || !curproc) 2195 panic("ohci_abort_xfer: not in process context"); 2196 2197 /* 2198 * Step 1: Make interrupt routine and hardware ignore xfer. 2199 */ 2200 s = splusb(); 2201 xfer->status = status; /* make software ignore it */ 2202 timeout_del(&xfer->timeout_handle); 2203 splx(s); 2204 DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed)); 2205 sed->ed.ed_flags |= htole32(OHCI_ED_SKIP); /* force hardware skip */ 2206 2207 /* 2208 * Step 2: Wait until we know hardware has finished any possible 2209 * use of the xfer. Also make sure the soft interrupt routine 2210 * has run. 2211 */ 2212 usb_delay_ms(opipe->pipe.device->bus, 20); /* Hardware finishes in 1ms */ 2213 s = splusb(); 2214 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 2215 sc->sc_softwake = 1; 2216 #endif /* __HAVE_GENERIC_SOFT_INTERRUPTS */ 2217 usb_schedsoftintr(&sc->sc_bus); 2218 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 2219 tsleep(&sc->sc_softwake, PZERO, "ohciab", 0); 2220 #endif /* __HAVE_GENERIC_SOFT_INTERRUPTS */ 2221 splx(s); 2222 2223 /* 2224 * Step 3: Remove any vestiges of the xfer from the hardware. 2225 * The complication here is that the hardware may have executed 2226 * beyond the xfer we're trying to abort. So as we're scanning 2227 * the TDs of this xfer we check if the hardware points to 2228 * any of them. 2229 */ 2230 s = splusb(); /* XXX why? */ 2231 p = xfer->hcpriv; 2232 #ifdef DIAGNOSTIC 2233 if (p == NULL) { 2234 splx(s); 2235 printf("ohci_abort_xfer: hcpriv is NULL\n"); 2236 return; 2237 } 2238 #endif 2239 #ifdef OHCI_DEBUG 2240 if (ohcidebug > 1) { 2241 DPRINTF(("ohci_abort_xfer: sed=\n")); 2242 ohci_dump_ed(sed); 2243 ohci_dump_tds(p); 2244 } 2245 #endif 2246 headp = letoh32(sed->ed.ed_headp) & OHCI_HEADMASK; 2247 hit = 0; 2248 for (; p->xfer == xfer; p = n) { 2249 hit |= headp == p->physaddr; 2250 n = p->nexttd; 2251 if (OHCI_TD_GET_CC(letoh32(p->td.td_flags)) == 2252 OHCI_CC_NOT_ACCESSED) 2253 ohci_free_std(sc, p); 2254 } 2255 /* Zap headp register if hardware pointed inside the xfer. */ 2256 if (hit) { 2257 DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n", 2258 (int)p->physaddr, (int)letoh32(sed->ed.ed_tailp))); 2259 sed->ed.ed_headp = htole32(p->physaddr); /* unlink TDs */ 2260 } else { 2261 DPRINTFN(1,("ohci_abort_xfer: no hit\n")); 2262 } 2263 2264 /* 2265 * Step 4: Turn on hardware again. 2266 */ 2267 sed->ed.ed_flags &= htole32(~OHCI_ED_SKIP); /* remove hardware skip */ 2268 2269 /* 2270 * Step 5: Execute callback. 2271 */ 2272 usb_transfer_complete(xfer); 2273 2274 splx(s); 2275 } 2276 2277 /* 2278 * Data structures and routines to emulate the root hub. 2279 */ 2280 usb_device_descriptor_t ohci_devd = { 2281 USB_DEVICE_DESCRIPTOR_SIZE, 2282 UDESC_DEVICE, /* type */ 2283 {0x00, 0x01}, /* USB version */ 2284 UDCLASS_HUB, /* class */ 2285 UDSUBCLASS_HUB, /* subclass */ 2286 UDPROTO_FSHUB, 2287 64, /* max packet */ 2288 {0},{0},{0x00,0x01}, /* device id */ 2289 1,2,0, /* string indices */ 2290 1 /* # of configurations */ 2291 }; 2292 2293 usb_config_descriptor_t ohci_confd = { 2294 USB_CONFIG_DESCRIPTOR_SIZE, 2295 UDESC_CONFIG, 2296 {USB_CONFIG_DESCRIPTOR_SIZE + 2297 USB_INTERFACE_DESCRIPTOR_SIZE + 2298 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2299 1, 2300 1, 2301 0, 2302 UC_SELF_POWERED, 2303 0 /* max power */ 2304 }; 2305 2306 usb_interface_descriptor_t ohci_ifcd = { 2307 USB_INTERFACE_DESCRIPTOR_SIZE, 2308 UDESC_INTERFACE, 2309 0, 2310 0, 2311 1, 2312 UICLASS_HUB, 2313 UISUBCLASS_HUB, 2314 UIPROTO_FSHUB, 2315 0 2316 }; 2317 2318 usb_endpoint_descriptor_t ohci_endpd = { 2319 USB_ENDPOINT_DESCRIPTOR_SIZE, 2320 UDESC_ENDPOINT, 2321 UE_DIR_IN | OHCI_INTR_ENDPT, 2322 UE_INTERRUPT, 2323 {8, 0}, /* max packet */ 2324 255 2325 }; 2326 2327 usb_hub_descriptor_t ohci_hubd = { 2328 USB_HUB_DESCRIPTOR_SIZE, 2329 UDESC_HUB, 2330 0, 2331 {0,0}, 2332 0, 2333 0, 2334 {0}, 2335 }; 2336 2337 int 2338 ohci_str(usb_string_descriptor_t *p, int l, const char *s) 2339 { 2340 int i; 2341 2342 if (l == 0) 2343 return (0); 2344 p->bLength = 2 * strlen(s) + 2; 2345 if (l == 1) 2346 return (1); 2347 p->bDescriptorType = UDESC_STRING; 2348 l -= 2; 2349 for (i = 0; s[i] && l > 1; i++, l -= 2) 2350 USETW2(p->bString[i], 0, s[i]); 2351 return (2*i+2); 2352 } 2353 2354 /* 2355 * Simulate a hardware hub by handling all the necessary requests. 2356 */ 2357 usbd_status 2358 ohci_root_ctrl_transfer(usbd_xfer_handle xfer) 2359 { 2360 usbd_status err; 2361 2362 /* Insert last in queue. */ 2363 err = usb_insert_transfer(xfer); 2364 if (err) 2365 return (err); 2366 2367 /* Pipe isn't running, start first */ 2368 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2369 } 2370 2371 usbd_status 2372 ohci_root_ctrl_start(usbd_xfer_handle xfer) 2373 { 2374 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 2375 usb_device_request_t *req; 2376 void *buf = NULL; 2377 int port, i; 2378 int s, len, value, index, l, totlen = 0; 2379 usb_port_status_t ps; 2380 usb_hub_descriptor_t hubd; 2381 usbd_status err; 2382 u_int32_t v; 2383 2384 if (sc->sc_dying) 2385 return (USBD_IOERROR); 2386 2387 #ifdef DIAGNOSTIC 2388 if (!(xfer->rqflags & URQ_REQUEST)) 2389 /* XXX panic */ 2390 return (USBD_INVAL); 2391 #endif 2392 req = &xfer->request; 2393 2394 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 2395 req->bmRequestType, req->bRequest)); 2396 2397 len = UGETW(req->wLength); 2398 value = UGETW(req->wValue); 2399 index = UGETW(req->wIndex); 2400 2401 if (len != 0) 2402 buf = KERNADDR(&xfer->dmabuf, 0); 2403 2404 #define C(x,y) ((x) | ((y) << 8)) 2405 switch(C(req->bRequest, req->bmRequestType)) { 2406 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2407 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2408 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2409 /* 2410 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2411 * for the integrated root hub. 2412 */ 2413 break; 2414 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2415 if (len > 0) { 2416 *(u_int8_t *)buf = sc->sc_conf; 2417 totlen = 1; 2418 } 2419 break; 2420 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2421 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 2422 switch(value >> 8) { 2423 case UDESC_DEVICE: 2424 if ((value & 0xff) != 0) { 2425 err = USBD_IOERROR; 2426 goto ret; 2427 } 2428 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2429 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 2430 memcpy(buf, &ohci_devd, l); 2431 break; 2432 case UDESC_CONFIG: 2433 if ((value & 0xff) != 0) { 2434 err = USBD_IOERROR; 2435 goto ret; 2436 } 2437 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2438 memcpy(buf, &ohci_confd, l); 2439 buf = (char *)buf + l; 2440 len -= l; 2441 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2442 totlen += l; 2443 memcpy(buf, &ohci_ifcd, l); 2444 buf = (char *)buf + l; 2445 len -= l; 2446 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2447 totlen += l; 2448 memcpy(buf, &ohci_endpd, l); 2449 break; 2450 case UDESC_STRING: 2451 if (len == 0) 2452 break; 2453 *(u_int8_t *)buf = 0; 2454 totlen = 1; 2455 switch (value & 0xff) { 2456 case 0: /* Language table */ 2457 totlen = ohci_str(buf, len, "\001"); 2458 break; 2459 case 1: /* Vendor */ 2460 totlen = ohci_str(buf, len, sc->sc_vendor); 2461 break; 2462 case 2: /* Product */ 2463 totlen = ohci_str(buf, len, "OHCI root hub"); 2464 break; 2465 } 2466 break; 2467 default: 2468 err = USBD_IOERROR; 2469 goto ret; 2470 } 2471 break; 2472 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2473 if (len > 0) { 2474 *(u_int8_t *)buf = 0; 2475 totlen = 1; 2476 } 2477 break; 2478 case C(UR_GET_STATUS, UT_READ_DEVICE): 2479 if (len > 1) { 2480 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2481 totlen = 2; 2482 } 2483 break; 2484 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2485 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2486 if (len > 1) { 2487 USETW(((usb_status_t *)buf)->wStatus, 0); 2488 totlen = 2; 2489 } 2490 break; 2491 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2492 if (value >= USB_MAX_DEVICES) { 2493 err = USBD_IOERROR; 2494 goto ret; 2495 } 2496 sc->sc_addr = value; 2497 break; 2498 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2499 if (value != 0 && value != 1) { 2500 err = USBD_IOERROR; 2501 goto ret; 2502 } 2503 sc->sc_conf = value; 2504 break; 2505 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2506 break; 2507 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2508 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2509 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2510 err = USBD_IOERROR; 2511 goto ret; 2512 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2513 break; 2514 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2515 break; 2516 /* Hub requests */ 2517 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2518 break; 2519 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2520 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 2521 "port=%d feature=%d\n", 2522 index, value)); 2523 if (index < 1 || index > sc->sc_noport) { 2524 err = USBD_IOERROR; 2525 goto ret; 2526 } 2527 port = OHCI_RH_PORT_STATUS(index); 2528 switch(value) { 2529 case UHF_PORT_ENABLE: 2530 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2531 break; 2532 case UHF_PORT_SUSPEND: 2533 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2534 break; 2535 case UHF_PORT_POWER: 2536 /* Yes, writing to the LOW_SPEED bit clears power. */ 2537 OWRITE4(sc, port, UPS_LOW_SPEED); 2538 break; 2539 case UHF_C_PORT_CONNECTION: 2540 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2541 break; 2542 case UHF_C_PORT_ENABLE: 2543 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2544 break; 2545 case UHF_C_PORT_SUSPEND: 2546 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2547 break; 2548 case UHF_C_PORT_OVER_CURRENT: 2549 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2550 break; 2551 case UHF_C_PORT_RESET: 2552 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2553 break; 2554 default: 2555 err = USBD_IOERROR; 2556 goto ret; 2557 } 2558 switch(value) { 2559 case UHF_C_PORT_CONNECTION: 2560 case UHF_C_PORT_ENABLE: 2561 case UHF_C_PORT_SUSPEND: 2562 case UHF_C_PORT_OVER_CURRENT: 2563 case UHF_C_PORT_RESET: 2564 /* Enable RHSC interrupt if condition is cleared. */ 2565 if ((OREAD4(sc, port) >> 16) == 0) 2566 ohci_rhsc_able(sc, 1); 2567 break; 2568 default: 2569 break; 2570 } 2571 break; 2572 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2573 if ((value & 0xff) != 0) { 2574 err = USBD_IOERROR; 2575 goto ret; 2576 } 2577 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2578 hubd = ohci_hubd; 2579 hubd.bNbrPorts = sc->sc_noport; 2580 USETW(hubd.wHubCharacteristics, 2581 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2582 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2583 /* XXX overcurrent */ 2584 ); 2585 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2586 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2587 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2588 hubd.DeviceRemovable[i++] = (u_int8_t)v; 2589 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2590 l = min(len, hubd.bDescLength); 2591 totlen = l; 2592 memcpy(buf, &hubd, l); 2593 break; 2594 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2595 if (len != 4) { 2596 err = USBD_IOERROR; 2597 goto ret; 2598 } 2599 memset(buf, 0, len); /* ? XXX */ 2600 totlen = len; 2601 break; 2602 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2603 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 2604 index)); 2605 if (index < 1 || index > sc->sc_noport) { 2606 err = USBD_IOERROR; 2607 goto ret; 2608 } 2609 if (len != 4) { 2610 err = USBD_IOERROR; 2611 goto ret; 2612 } 2613 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2614 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 2615 v)); 2616 USETW(ps.wPortStatus, v); 2617 USETW(ps.wPortChange, v >> 16); 2618 l = min(len, sizeof ps); 2619 memcpy(buf, &ps, l); 2620 totlen = l; 2621 break; 2622 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2623 err = USBD_IOERROR; 2624 goto ret; 2625 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2626 break; 2627 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2628 if (index < 1 || index > sc->sc_noport) { 2629 err = USBD_IOERROR; 2630 goto ret; 2631 } 2632 port = OHCI_RH_PORT_STATUS(index); 2633 switch(value) { 2634 case UHF_PORT_ENABLE: 2635 OWRITE4(sc, port, UPS_PORT_ENABLED); 2636 break; 2637 case UHF_PORT_SUSPEND: 2638 OWRITE4(sc, port, UPS_SUSPEND); 2639 break; 2640 case UHF_PORT_RESET: 2641 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 2642 index)); 2643 OWRITE4(sc, port, UPS_RESET); 2644 for (i = 0; i < 5; i++) { 2645 usb_delay_ms(&sc->sc_bus, 2646 USB_PORT_ROOT_RESET_DELAY); 2647 if (sc->sc_dying) { 2648 err = USBD_IOERROR; 2649 goto ret; 2650 } 2651 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2652 break; 2653 } 2654 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 2655 index, OREAD4(sc, port))); 2656 break; 2657 case UHF_PORT_POWER: 2658 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 2659 "%d\n", index)); 2660 OWRITE4(sc, port, UPS_PORT_POWER); 2661 break; 2662 case UHF_PORT_DISOWN_TO_1_1: 2663 /* accept, but do nothing */ 2664 break; 2665 default: 2666 err = USBD_IOERROR; 2667 goto ret; 2668 } 2669 break; 2670 default: 2671 err = USBD_IOERROR; 2672 goto ret; 2673 } 2674 xfer->actlen = totlen; 2675 err = USBD_NORMAL_COMPLETION; 2676 ret: 2677 xfer->status = err; 2678 s = splusb(); 2679 usb_transfer_complete(xfer); 2680 splx(s); 2681 return (USBD_IN_PROGRESS); 2682 } 2683 2684 /* Abort a root control request. */ 2685 void 2686 ohci_root_ctrl_abort(usbd_xfer_handle xfer) 2687 { 2688 /* Nothing to do, all transfers are synchronous. */ 2689 } 2690 2691 /* Close the root pipe. */ 2692 void 2693 ohci_root_ctrl_close(usbd_pipe_handle pipe) 2694 { 2695 DPRINTF(("ohci_root_ctrl_close\n")); 2696 /* Nothing to do. */ 2697 } 2698 2699 usbd_status 2700 ohci_root_intr_transfer(usbd_xfer_handle xfer) 2701 { 2702 usbd_status err; 2703 2704 /* Insert last in queue. */ 2705 err = usb_insert_transfer(xfer); 2706 if (err) 2707 return (err); 2708 2709 /* Pipe isn't running, start first */ 2710 return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2711 } 2712 2713 usbd_status 2714 ohci_root_intr_start(usbd_xfer_handle xfer) 2715 { 2716 usbd_pipe_handle pipe = xfer->pipe; 2717 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2718 2719 if (sc->sc_dying) 2720 return (USBD_IOERROR); 2721 2722 sc->sc_intrxfer = xfer; 2723 2724 return (USBD_IN_PROGRESS); 2725 } 2726 2727 /* Abort a root interrupt request. */ 2728 void 2729 ohci_root_intr_abort(usbd_xfer_handle xfer) 2730 { 2731 int s; 2732 2733 if (xfer->pipe->intrxfer == xfer) { 2734 DPRINTF(("ohci_root_intr_abort: remove\n")); 2735 xfer->pipe->intrxfer = NULL; 2736 } 2737 xfer->status = USBD_CANCELLED; 2738 s = splusb(); 2739 usb_transfer_complete(xfer); 2740 splx(s); 2741 } 2742 2743 /* Close the root pipe. */ 2744 void 2745 ohci_root_intr_close(usbd_pipe_handle pipe) 2746 { 2747 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2748 2749 DPRINTF(("ohci_root_intr_close\n")); 2750 2751 sc->sc_intrxfer = NULL; 2752 } 2753 2754 /************************/ 2755 2756 usbd_status 2757 ohci_device_ctrl_transfer(usbd_xfer_handle xfer) 2758 { 2759 usbd_status err; 2760 2761 /* Insert last in queue. */ 2762 err = usb_insert_transfer(xfer); 2763 if (err) 2764 return (err); 2765 2766 /* Pipe isn't running, start first */ 2767 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2768 } 2769 2770 usbd_status 2771 ohci_device_ctrl_start(usbd_xfer_handle xfer) 2772 { 2773 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 2774 usbd_status err; 2775 2776 if (sc->sc_dying) 2777 return (USBD_IOERROR); 2778 2779 #ifdef DIAGNOSTIC 2780 if (!(xfer->rqflags & URQ_REQUEST)) { 2781 /* XXX panic */ 2782 printf("ohci_device_ctrl_transfer: not a request\n"); 2783 return (USBD_INVAL); 2784 } 2785 #endif 2786 2787 err = ohci_device_request(xfer); 2788 if (err) 2789 return (err); 2790 2791 if (sc->sc_bus.use_polling) 2792 ohci_waitintr(sc, xfer); 2793 2794 return (USBD_IN_PROGRESS); 2795 } 2796 2797 /* Abort a device control request. */ 2798 void 2799 ohci_device_ctrl_abort(usbd_xfer_handle xfer) 2800 { 2801 DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer)); 2802 ohci_abort_xfer(xfer, USBD_CANCELLED); 2803 } 2804 2805 /* Close a device control pipe. */ 2806 void 2807 ohci_device_ctrl_close(usbd_pipe_handle pipe) 2808 { 2809 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2810 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2811 2812 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 2813 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2814 ohci_free_std(sc, opipe->tail.td); 2815 } 2816 2817 /************************/ 2818 2819 void 2820 ohci_device_clear_toggle(usbd_pipe_handle pipe) 2821 { 2822 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2823 2824 opipe->sed->ed.ed_headp &= htole32(~OHCI_TOGGLECARRY); 2825 } 2826 2827 void 2828 ohci_noop(usbd_pipe_handle pipe) 2829 { 2830 } 2831 2832 usbd_status 2833 ohci_device_bulk_transfer(usbd_xfer_handle xfer) 2834 { 2835 usbd_status err; 2836 2837 /* Insert last in queue. */ 2838 err = usb_insert_transfer(xfer); 2839 if (err) 2840 return (err); 2841 2842 /* Pipe isn't running, start first */ 2843 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2844 } 2845 2846 usbd_status 2847 ohci_device_bulk_start(usbd_xfer_handle xfer) 2848 { 2849 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2850 usbd_device_handle dev = opipe->pipe.device; 2851 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 2852 int addr = dev->address; 2853 ohci_soft_td_t *data, *tail, *tdp; 2854 ohci_soft_ed_t *sed; 2855 int s, len, isread, endpt; 2856 usbd_status err; 2857 2858 if (sc->sc_dying) 2859 return (USBD_IOERROR); 2860 2861 #ifdef DIAGNOSTIC 2862 if (xfer->rqflags & URQ_REQUEST) { 2863 /* XXX panic */ 2864 printf("ohci_device_bulk_start: a request\n"); 2865 return (USBD_INVAL); 2866 } 2867 #endif 2868 2869 len = xfer->length; 2870 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 2871 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2872 sed = opipe->sed; 2873 2874 DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%d isread=%d " 2875 "flags=%d endpt=%d\n", xfer, len, isread, xfer->flags, 2876 endpt)); 2877 2878 opipe->u.bulk.isread = isread; 2879 opipe->u.bulk.length = len; 2880 2881 /* Update device address */ 2882 sed->ed.ed_flags = htole32( 2883 (letoh32(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 2884 OHCI_ED_SET_FA(addr)); 2885 2886 /* Allocate a chain of new TDs (including a new tail). */ 2887 data = opipe->tail.td; 2888 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 2889 data, &tail); 2890 /* We want interrupt at the end of the transfer. */ 2891 tail->td.td_flags &= htole32(~OHCI_TD_INTR_MASK); 2892 tail->td.td_flags |= htole32(OHCI_TD_SET_DI(1)); 2893 tail->flags |= OHCI_CALL_DONE; 2894 tail = tail->nexttd; /* point at sentinel */ 2895 if (err) 2896 return (err); 2897 2898 tail->xfer = NULL; 2899 xfer->hcpriv = data; 2900 2901 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 2902 "td_cbp=0x%08x td_be=0x%08x\n", 2903 (int)letoh32(sed->ed.ed_flags), 2904 (int)letoh32(data->td.td_flags), 2905 (int)letoh32(data->td.td_cbp), 2906 (int)letoh32(data->td.td_be))); 2907 2908 #ifdef OHCI_DEBUG 2909 if (ohcidebug > 5) { 2910 ohci_dump_ed(sed); 2911 ohci_dump_tds(data); 2912 } 2913 #endif 2914 2915 /* Insert ED in schedule */ 2916 s = splusb(); 2917 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 2918 tdp->xfer = xfer; 2919 } 2920 sed->ed.ed_tailp = htole32(tail->physaddr); 2921 opipe->tail.td = tail; 2922 sed->ed.ed_flags &= htole32(~OHCI_ED_SKIP); 2923 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2924 if (xfer->timeout && !sc->sc_bus.use_polling) { 2925 timeout_del(&xfer->timeout_handle); 2926 timeout_set(&xfer->timeout_handle, ohci_timeout, xfer); 2927 timeout_add(&xfer->timeout_handle, mstohz(xfer->timeout)); 2928 } 2929 2930 #if 0 2931 /* This goes wrong if we are too slow. */ 2932 if (ohcidebug > 10) { 2933 delay(10000); 2934 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 2935 OREAD4(sc, OHCI_COMMAND_STATUS))); 2936 ohci_dump_ed(sed); 2937 ohci_dump_tds(data); 2938 } 2939 #endif 2940 2941 splx(s); 2942 2943 if (sc->sc_bus.use_polling) 2944 ohci_waitintr(sc, xfer); 2945 2946 return (USBD_IN_PROGRESS); 2947 } 2948 2949 void 2950 ohci_device_bulk_abort(usbd_xfer_handle xfer) 2951 { 2952 DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer)); 2953 ohci_abort_xfer(xfer, USBD_CANCELLED); 2954 } 2955 2956 /* 2957 * Close a device bulk pipe. 2958 */ 2959 void 2960 ohci_device_bulk_close(usbd_pipe_handle pipe) 2961 { 2962 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2963 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2964 2965 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 2966 ohci_close_pipe(pipe, sc->sc_bulk_head); 2967 ohci_free_std(sc, opipe->tail.td); 2968 } 2969 2970 /************************/ 2971 2972 usbd_status 2973 ohci_device_intr_transfer(usbd_xfer_handle xfer) 2974 { 2975 usbd_status err; 2976 2977 /* Insert last in queue. */ 2978 err = usb_insert_transfer(xfer); 2979 if (err) 2980 return (err); 2981 2982 /* Pipe isn't running, start first */ 2983 return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2984 } 2985 2986 usbd_status 2987 ohci_device_intr_start(usbd_xfer_handle xfer) 2988 { 2989 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2990 usbd_device_handle dev = opipe->pipe.device; 2991 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 2992 ohci_soft_ed_t *sed = opipe->sed; 2993 ohci_soft_td_t *data, *tail; 2994 int s, len, isread, endpt; 2995 2996 if (sc->sc_dying) 2997 return (USBD_IOERROR); 2998 2999 DPRINTFN(3, ("ohci_device_intr_transfer: xfer=%p len=%d " 3000 "flags=%d priv=%p\n", 3001 xfer, xfer->length, xfer->flags, xfer->priv)); 3002 3003 #ifdef DIAGNOSTIC 3004 if (xfer->rqflags & URQ_REQUEST) 3005 panic("ohci_device_intr_transfer: a request"); 3006 #endif 3007 3008 len = xfer->length; 3009 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3010 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3011 3012 data = opipe->tail.td; 3013 tail = ohci_alloc_std(sc); 3014 if (tail == NULL) 3015 return (USBD_NOMEM); 3016 tail->xfer = NULL; 3017 3018 data->td.td_flags = htole32( 3019 isread ? OHCI_TD_IN : OHCI_TD_OUT | 3020 OHCI_TD_NOCC | 3021 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 3022 if (xfer->flags & USBD_SHORT_XFER_OK) 3023 data->td.td_flags |= htole32(OHCI_TD_R); 3024 data->td.td_cbp = htole32(DMAADDR(&xfer->dmabuf, 0)); 3025 data->nexttd = tail; 3026 data->td.td_nexttd = htole32(tail->physaddr); 3027 data->td.td_be = htole32(letoh32(data->td.td_cbp) + len - 1); 3028 data->len = len; 3029 data->xfer = xfer; 3030 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 3031 xfer->hcpriv = data; 3032 3033 #ifdef OHCI_DEBUG 3034 if (ohcidebug > 5) { 3035 DPRINTF(("ohci_device_intr_transfer:\n")); 3036 ohci_dump_ed(sed); 3037 ohci_dump_tds(data); 3038 } 3039 #endif 3040 3041 /* Insert ED in schedule */ 3042 s = splusb(); 3043 sed->ed.ed_tailp = htole32(tail->physaddr); 3044 opipe->tail.td = tail; 3045 sed->ed.ed_flags &= htole32(~OHCI_ED_SKIP); 3046 3047 #if 0 3048 /* 3049 * This goes horribly wrong, printing thousands of descriptors, 3050 * because false references are followed due to the fact that the 3051 * TD is gone. 3052 */ 3053 if (ohcidebug > 5) { 3054 usb_delay_ms(&sc->sc_bus, 5); 3055 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3056 OREAD4(sc, OHCI_COMMAND_STATUS))); 3057 ohci_dump_ed(sed); 3058 ohci_dump_tds(data); 3059 } 3060 #endif 3061 splx(s); 3062 3063 return (USBD_IN_PROGRESS); 3064 } 3065 3066 /* Abort a device control request. */ 3067 void 3068 ohci_device_intr_abort(usbd_xfer_handle xfer) 3069 { 3070 if (xfer->pipe->intrxfer == xfer) { 3071 DPRINTF(("ohci_device_intr_abort: remove\n")); 3072 xfer->pipe->intrxfer = NULL; 3073 } 3074 ohci_abort_xfer(xfer, USBD_CANCELLED); 3075 } 3076 3077 /* Close a device interrupt pipe. */ 3078 void 3079 ohci_device_intr_close(usbd_pipe_handle pipe) 3080 { 3081 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3082 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 3083 int nslots = opipe->u.intr.nslots; 3084 int pos = opipe->u.intr.pos; 3085 int j; 3086 ohci_soft_ed_t *p, *sed = opipe->sed; 3087 int s; 3088 3089 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 3090 pipe, nslots, pos)); 3091 s = splusb(); 3092 sed->ed.ed_flags |= htole32(OHCI_ED_SKIP); 3093 if ((letoh32(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3094 (letoh32(sed->ed.ed_headp) & OHCI_HEADMASK)) 3095 usb_delay_ms(&sc->sc_bus, 2); 3096 3097 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3098 ; 3099 #ifdef DIAGNOSTIC 3100 if (p == NULL) 3101 panic("ohci_device_intr_close: ED not found"); 3102 #endif 3103 p->next = sed->next; 3104 p->ed.ed_nexted = sed->ed.ed_nexted; 3105 splx(s); 3106 3107 for (j = 0; j < nslots; j++) 3108 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3109 3110 ohci_free_std(sc, opipe->tail.td); 3111 ohci_free_sed(sc, opipe->sed); 3112 } 3113 3114 usbd_status 3115 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3116 { 3117 int i, j, s, best; 3118 u_int npoll, slow, shigh, nslots; 3119 u_int bestbw, bw; 3120 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3121 3122 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 3123 if (ival == 0) { 3124 printf("ohci_setintr: 0 interval\n"); 3125 return (USBD_INVAL); 3126 } 3127 3128 npoll = OHCI_NO_INTRS; 3129 while (npoll > ival) 3130 npoll /= 2; 3131 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 3132 3133 /* 3134 * We now know which level in the tree the ED must go into. 3135 * Figure out which slot has most bandwidth left over. 3136 * Slots to examine: 3137 * npoll 3138 * 1 0 3139 * 2 1 2 3140 * 4 3 4 5 6 3141 * 8 7 8 9 10 11 12 13 14 3142 * N (N-1) .. (N-1+N-1) 3143 */ 3144 slow = npoll-1; 3145 shigh = slow + npoll; 3146 nslots = OHCI_NO_INTRS / npoll; 3147 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3148 bw = 0; 3149 for (j = 0; j < nslots; j++) 3150 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3151 if (bw < bestbw) { 3152 best = i; 3153 bestbw = bw; 3154 } 3155 } 3156 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 3157 best, slow, shigh, bestbw)); 3158 3159 s = splusb(); 3160 hsed = sc->sc_eds[best]; 3161 sed->next = hsed->next; 3162 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3163 hsed->next = sed; 3164 hsed->ed.ed_nexted = htole32(sed->physaddr); 3165 splx(s); 3166 3167 for (j = 0; j < nslots; j++) 3168 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3169 opipe->u.intr.nslots = nslots; 3170 opipe->u.intr.pos = best; 3171 3172 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 3173 return (USBD_NORMAL_COMPLETION); 3174 } 3175 3176 /***********************/ 3177 3178 usbd_status 3179 ohci_device_isoc_transfer(usbd_xfer_handle xfer) 3180 { 3181 usbd_status err; 3182 3183 DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer)); 3184 3185 /* Put it on our queue, */ 3186 err = usb_insert_transfer(xfer); 3187 3188 /* bail out on error, */ 3189 if (err && err != USBD_IN_PROGRESS) 3190 return (err); 3191 3192 /* XXX should check inuse here */ 3193 3194 /* insert into schedule, */ 3195 ohci_device_isoc_enter(xfer); 3196 3197 /* and start if the pipe wasn't running */ 3198 if (!err) 3199 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 3200 3201 return (err); 3202 } 3203 3204 void 3205 ohci_device_isoc_enter(usbd_xfer_handle xfer) 3206 { 3207 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3208 usbd_device_handle dev = opipe->pipe.device; 3209 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 3210 ohci_soft_ed_t *sed = opipe->sed; 3211 struct iso *iso = &opipe->u.iso; 3212 ohci_soft_itd_t *sitd, *nsitd; 3213 ohci_physaddr_t buf, offs, noffs, bp0; 3214 int i, ncur, nframes; 3215 int s; 3216 3217 DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p " 3218 "nframes=%d\n", 3219 iso->inuse, iso->next, xfer, xfer->nframes)); 3220 3221 if (sc->sc_dying) 3222 return; 3223 3224 if (iso->next == -1) { 3225 /* Not in use yet, schedule it a few frames ahead. */ 3226 iso->next = letoh32(sc->sc_hcca->hcca_frame_number) + 5; 3227 DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n", 3228 iso->next)); 3229 } 3230 3231 sitd = opipe->tail.itd; 3232 buf = DMAADDR(&xfer->dmabuf, 0); 3233 bp0 = OHCI_PAGE(buf); 3234 offs = OHCI_PAGE_OFFSET(buf); 3235 nframes = xfer->nframes; 3236 xfer->hcpriv = sitd; 3237 for (i = ncur = 0; i < nframes; i++, ncur++) { 3238 noffs = offs + xfer->frlengths[i]; 3239 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3240 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3241 3242 /* Allocate next ITD */ 3243 nsitd = ohci_alloc_sitd(sc); 3244 if (nsitd == NULL) { 3245 /* XXX what now? */ 3246 printf("%s: isoc TD alloc failed\n", 3247 sc->sc_bus.bdev.dv_xname); 3248 return; 3249 } 3250 3251 /* Fill current ITD */ 3252 sitd->itd.itd_flags = htole32( 3253 OHCI_ITD_NOCC | 3254 OHCI_ITD_SET_SF(iso->next) | 3255 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3256 OHCI_ITD_SET_FC(ncur)); 3257 sitd->itd.itd_bp0 = htole32(bp0); 3258 sitd->nextitd = nsitd; 3259 sitd->itd.itd_nextitd = htole32(nsitd->physaddr); 3260 sitd->itd.itd_be = htole32(bp0 + offs - 1); 3261 sitd->xfer = xfer; 3262 sitd->flags = 0; 3263 3264 sitd = nsitd; 3265 iso->next = iso->next + ncur; 3266 bp0 = OHCI_PAGE(buf + offs); 3267 ncur = 0; 3268 } 3269 sitd->itd.itd_offset[ncur] = htole16(OHCI_ITD_MK_OFFS(offs)); 3270 offs = noffs; 3271 } 3272 nsitd = ohci_alloc_sitd(sc); 3273 if (nsitd == NULL) { 3274 /* XXX what now? */ 3275 printf("%s: isoc TD alloc failed\n", 3276 sc->sc_bus.bdev.dv_xname); 3277 return; 3278 } 3279 /* Fixup last used ITD */ 3280 sitd->itd.itd_flags = htole32( 3281 OHCI_ITD_NOCC | 3282 OHCI_ITD_SET_SF(iso->next) | 3283 OHCI_ITD_SET_DI(0) | 3284 OHCI_ITD_SET_FC(ncur)); 3285 sitd->itd.itd_bp0 = htole32(bp0); 3286 sitd->nextitd = nsitd; 3287 sitd->itd.itd_nextitd = htole32(nsitd->physaddr); 3288 sitd->itd.itd_be = htole32(bp0 + offs - 1); 3289 sitd->xfer = xfer; 3290 sitd->flags = OHCI_CALL_DONE; 3291 3292 iso->next = iso->next + ncur; 3293 iso->inuse += nframes; 3294 3295 xfer->actlen = offs; /* XXX pretend we did it all */ 3296 3297 xfer->status = USBD_IN_PROGRESS; 3298 3299 #ifdef OHCI_DEBUG 3300 if (ohcidebug > 5) { 3301 DPRINTF(("ohci_device_isoc_enter: frame=%d\n", 3302 letoh32(sc->sc_hcca->hcca_frame_number))); 3303 ohci_dump_itds(xfer->hcpriv); 3304 ohci_dump_ed(sed); 3305 } 3306 #endif 3307 3308 s = splusb(); 3309 sed->ed.ed_tailp = htole32(nsitd->physaddr); 3310 opipe->tail.itd = nsitd; 3311 sed->ed.ed_flags &= htole32(~OHCI_ED_SKIP); 3312 splx(s); 3313 3314 #ifdef OHCI_DEBUG 3315 if (ohcidebug > 5) { 3316 delay(150000); 3317 DPRINTF(("ohci_device_isoc_enter: after frame=%d\n", 3318 letoh32(sc->sc_hcca->hcca_frame_number))); 3319 ohci_dump_itds(xfer->hcpriv); 3320 ohci_dump_ed(sed); 3321 } 3322 #endif 3323 } 3324 3325 usbd_status 3326 ohci_device_isoc_start(usbd_xfer_handle xfer) 3327 { 3328 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3329 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 3330 3331 DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer)); 3332 3333 if (sc->sc_dying) 3334 return (USBD_IOERROR); 3335 3336 #ifdef DIAGNOSTIC 3337 if (xfer->status != USBD_IN_PROGRESS) 3338 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3339 #endif 3340 3341 /* XXX anything to do? */ 3342 3343 return (USBD_IN_PROGRESS); 3344 } 3345 3346 void 3347 ohci_device_isoc_abort(usbd_xfer_handle xfer) 3348 { 3349 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3350 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 3351 ohci_soft_ed_t *sed; 3352 ohci_soft_itd_t *sitd; 3353 int s; 3354 3355 s = splusb(); 3356 3357 DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p\n", xfer)); 3358 3359 /* Transfer is already done. */ 3360 if (xfer->status != USBD_NOT_STARTED && 3361 xfer->status != USBD_IN_PROGRESS) { 3362 splx(s); 3363 printf("ohci_device_isoc_abort: early return\n"); 3364 return; 3365 } 3366 3367 /* Give xfer the requested abort code. */ 3368 xfer->status = USBD_CANCELLED; 3369 3370 sed = opipe->sed; 3371 sed->ed.ed_flags |= htole32(OHCI_ED_SKIP); /* force hardware skip */ 3372 3373 sitd = xfer->hcpriv; 3374 #ifdef DIAGNOSTIC 3375 if (sitd == NULL) { 3376 splx(s); 3377 printf("ohci_device_isoc_abort: hcpriv==0\n"); 3378 return; 3379 } 3380 #endif 3381 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3382 #ifdef DIAGNOSTIC 3383 DPRINTFN(1,("abort sets done sitd=%p\n", sitd)); 3384 sitd->isdone = 1; 3385 #endif 3386 } 3387 3388 splx(s); 3389 3390 usb_delay_ms(&sc->sc_bus, OHCI_ITD_NOFFSET); 3391 3392 s = splusb(); 3393 3394 /* Run callback. */ 3395 usb_transfer_complete(xfer); 3396 3397 sed->ed.ed_headp = htole32(sitd->physaddr); /* unlink TDs */ 3398 sed->ed.ed_flags &= htole32(~OHCI_ED_SKIP); /* remove hardware skip */ 3399 3400 splx(s); 3401 } 3402 3403 void 3404 ohci_device_isoc_done(usbd_xfer_handle xfer) 3405 { 3406 DPRINTFN(1,("ohci_device_isoc_done: xfer=%p\n", xfer)); 3407 } 3408 3409 usbd_status 3410 ohci_setup_isoc(usbd_pipe_handle pipe) 3411 { 3412 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3413 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 3414 struct iso *iso = &opipe->u.iso; 3415 int s; 3416 3417 iso->next = -1; 3418 iso->inuse = 0; 3419 3420 s = splusb(); 3421 ohci_add_ed(opipe->sed, sc->sc_isoc_head); 3422 splx(s); 3423 3424 return (USBD_NORMAL_COMPLETION); 3425 } 3426 3427 void 3428 ohci_device_isoc_close(usbd_pipe_handle pipe) 3429 { 3430 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3431 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 3432 3433 DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe)); 3434 ohci_close_pipe(pipe, sc->sc_isoc_head); 3435 #ifdef DIAGNOSTIC 3436 opipe->tail.itd->isdone = 1; 3437 #endif 3438 ohci_free_sitd(sc, opipe->tail.itd); 3439 } 3440