1 /* $OpenBSD: if_urtwreg.h,v 1.2 2008/12/03 10:44:17 jsg Exp $ */ 2 /*- 3 * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #define URTW_CONFIG_NO 1 19 #define URTW_IFACE_INDEX 0 20 21 /* for 8187 */ 22 #define URTW_MAC0 0x0000 /* 1 byte */ 23 #define URTW_MAC1 0x0001 /* 1 byte */ 24 #define URTW_MAC2 0x0002 /* 1 byte */ 25 #define URTW_MAC3 0x0003 /* 1 byte */ 26 #define URTW_MAC4 0x0004 /* 1 byte */ 27 #define URTW_MAC5 0x0005 /* 1 byte */ 28 #define URTW_BRSR 0x002c /* 2 byte */ 29 #define URTW_BRSR_MBR_8185 (0x0fff) 30 #define URTW_BSSID 0x002e /* 6 byte */ 31 #define URTW_RESP_RATE 0x0034 /* 1 byte */ 32 #define URTW_RESP_MAX_RATE_SHIFT (4) 33 #define URTW_RESP_MIN_RATE_SHIFT (0) 34 #define URTW_EIFS 0x0035 /* 1 byte */ 35 #define URTW_INTR_MASK 0x003c /* 2 byte */ 36 #define URTW_CMD 0x0037 /* 1 byte */ 37 #define URTW_CMD_TX_ENABLE (0x4) 38 #define URTW_CMD_RX_ENABLE (0x8) 39 #define URTW_CMD_RST (0x10) 40 #define URTW_TX_CONF 0x0040 /* 4 byte */ 41 #define URTW_TX_LOOPBACK_SHIFT (17) 42 #define URTW_TX_LOOPBACK_NONE (0 << URTW_TX_LOOPBACK_SHIFT) 43 #define URTW_TX_LOOPBACK_MAC (1 << URTW_TX_LOOPBACK_SHIFT) 44 #define URTW_TX_LOOPBACK_BASEBAND (2 << URTW_TX_LOOPBACK_SHIFT) 45 #define URTW_TX_LOOPBACK_CONTINUE (3 << URTW_TX_LOOPBACK_SHIFT) 46 #define URTW_TX_LOOPBACK_MASK (0x60000) 47 #define URTW_TX_DPRETRY_MASK (0xff00) 48 #define URTW_TX_RTSRETRY_MASK (0xff) 49 #define URTW_TX_DPRETRY_SHIFT (0) 50 #define URTW_TX_RTSRETRY_SHIFT (8) 51 #define URTW_TX_NOCRC (0x10000) 52 #define URTW_TX_MXDMA_MASK (0xe00000) 53 #define URTW_TX_MXDMA_1024 (6 << URTW_TX_MXDMA_SHIFT) 54 #define URTW_TX_MXDMA_2048 (7 << URTW_TX_MXDMA_SHIFT) 55 #define URTW_TX_MXDMA_SHIFT (21) 56 #define URTW_TX_CWMIN (1 << 31) 57 #define URTW_TX_DISCW (1 << 20) 58 #define URTW_TX_SWPLCPLEN (1 << 24) 59 #define URTW_TX_NOICV (0x80000) 60 #define URTW_RX 0x0044 /* 4 byte */ 61 #define URTW_RX_9356SEL (1 << 6) 62 #define URTW_RX_FILTER_MASK \ 63 (URTW_RX_FILTER_ALLMAC | URTW_RX_FILTER_NICMAC | URTW_RX_FILTER_MCAST | \ 64 URTW_RX_FILTER_BCAST | URTW_RX_FILTER_CRCERR | URTW_RX_FILTER_ICVERR | \ 65 URTW_RX_FILTER_DATA | URTW_RX_FILTER_CTL | URTW_RX_FILTER_MNG | \ 66 (1 << 21) | \ 67 URTW_RX_FILTER_PWR | URTW_RX_CHECK_BSSID) 68 #define URTW_RX_FILTER_ALLMAC (0x00000001) 69 #define URTW_RX_FILTER_NICMAC (0x00000002) 70 #define URTW_RX_FILTER_MCAST (0x00000004) 71 #define URTW_RX_FILTER_BCAST (0x00000008) 72 #define URTW_RX_FILTER_CRCERR (0x00000020) 73 #define URTW_RX_FILTER_ICVERR (0x00001000) 74 #define URTW_RX_FILTER_DATA (0x00040000) 75 #define URTW_RX_FILTER_CTL (0x00080000) 76 #define URTW_RX_FILTER_MNG (0x00100000) 77 #define URTW_RX_FILTER_PWR (0x00400000) 78 #define URTW_RX_CHECK_BSSID (0x00800000) 79 #define URTW_RX_FIFO_THRESHOLD_MASK ((1 << 13) | (1 << 14) | (1 << 15)) 80 #define URTW_RX_FIFO_THRESHOLD_SHIFT (13) 81 #define URTW_RX_FIFO_THRESHOLD_128 (3) 82 #define URTW_RX_FIFO_THRESHOLD_256 (4) 83 #define URTW_RX_FIFO_THRESHOLD_512 (5) 84 #define URTW_RX_FIFO_THRESHOLD_1024 (6) 85 #define URTW_RX_FIFO_THRESHOLD_NONE (7 << URTW_RX_FIFO_THRESHOLD_SHIFT) 86 #define URTW_RX_AUTORESETPHY (1 << URTW_RX_AUTORESETPHY_SHIFT) 87 #define URTW_RX_AUTORESETPHY_SHIFT (28) 88 #define URTW_MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10)) 89 #define URTW_MAX_RX_DMA_2048 (7 << URTW_MAX_RX_DMA_SHIFT) 90 #define URTW_MAX_RX_DMA_1024 (6) 91 #define URTW_MAX_RX_DMA_SHIFT (10) 92 #define URTW_RCR_ONLYERLPKT (1 << 31) 93 #define URTW_INT_TIMEOUT 0x0048 /* 4 byte */ 94 #define URTW_EPROM_CMD 0x0050 /* 1 byte */ 95 #define URTW_EPROM_CMD_NORMAL (0x0) 96 #define URTW_EPROM_CMD_NORMAL_MODE \ 97 (URTW_EPROM_CMD_NORMAL << URTW_EPROM_CMD_SHIFT) 98 #define URTW_EPROM_CMD_LOAD (0x1) 99 #define URTW_EPROM_CMD_PROGRAM (0x2) 100 #define URTW_EPROM_CMD_PROGRAM_MODE \ 101 (URTW_EPROM_CMD_PROGRAM << URTW_EPROM_CMD_SHIFT) 102 #define URTW_EPROM_CMD_CONFIG (0x3) 103 #define URTW_EPROM_CMD_SHIFT (6) 104 #define URTW_EPROM_CMD_MASK ((1 << 7) | (1 << 6)) 105 #define URTW_EPROM_READBIT (0x1) 106 #define URTW_EPROM_WRITEBIT (0x2) 107 #define URTW_EPROM_CK (0x4) 108 #define URTW_EPROM_CS (0x8) 109 #define URTW_CONFIG2 0x0053 110 #define URTW_ANAPARAM 0x0054 /* 4 byte */ 111 #define URTW_8225_ANAPARAM_ON (0xa0000a59) 112 #define URTW_MSR 0x0058 /* 1 byte */ 113 #define URTW_MSR_LINK_MASK ((1 << 2) | (1 << 3)) 114 #define URTW_MSR_LINK_SHIFT (2) 115 #define URTW_MSR_LINK_NONE (0 << URTW_MSR_LINK_SHIFT) 116 #define URTW_MSR_LINK_ADHOC (1 << URTW_MSR_LINK_SHIFT) 117 #define URTW_MSR_LINK_STA (2 << URTW_MSR_LINK_SHIFT) 118 #define URTW_MSR_LINK_HOSTAP (3 << URTW_MSR_LINK_SHIFT) 119 #define URTW_CONFIG3 0x0059 /* 1 byte */ 120 #define URTW_CONFIG3_ANAPARAM_WRITE (0x40) 121 #define URTW_CONFIG3_ANAPARAM_W_SHIFT (6) 122 #define URTW_PSR 0x005e /* 1 byte */ 123 #define URTW_ANAPARAM2 0x0060 /* 4 byte */ 124 #define URTW_8225_ANAPARAM2_ON (0x860c7312) 125 #define URTW_BEACON_INTERVAL 0x0070 /* 2 byte */ 126 #define URTW_ATIM_WND 0x0072 /* 2 byte */ 127 #define URTW_BEACON_INTERVAL_TIME 0x0074 /* 2 byte */ 128 #define URTW_ATIM_TR_ITV 0x0076 /* 2 byte */ 129 #define URTW_RF_PINS_OUTPUT 0x0080 /* 2 byte */ 130 #define URTW_BB_HOST_BANG_CLK (1 << 1) 131 #define URTW_BB_HOST_BANG_EN (1 << 2) 132 #define URTW_BB_HOST_BANG_RW (1 << 3) 133 #define URTW_RF_PINS_ENABLE 0x0082 /* 2 byte */ 134 #define URTW_RF_PINS_SELECT 0x0084 /* 2 byte */ 135 #define URTW_RF_PINS_INPUT 0x0086 /* 2 byte */ 136 #define URTW_RF_PARA 0x0088 /* 4 byte */ 137 #define URTW_RF_TIMING 0x008c /* 4 byte */ 138 #define URTW_GP_ENABLE 0x0090 /* 1 byte */ 139 #define URTW_GPIO 0x0091 /* 1 byte */ 140 #define URTW_TX_AGC_CTL 0x009c /* 1 byte */ 141 #define URTW_TX_AGC_CTL_PERPACKET_GAIN (0x1) 142 #define URTW_TX_AGC_CTL_PERPACKET_ANTSEL (0x2) 143 #define URTW_TX_AGC_CTL_FEEDBACK_ANT (0x4) 144 #define URTW_TX_GAIN_CCK 0x009d /* 1 byte */ 145 #define URTW_TX_GAIN_OFDM 0x009e /* 1 byte */ 146 #define URTW_TX_ANTENNA 0x009f /* 1 byte */ 147 #define URTW_WPA_CONFIG 0x00b0 /* 1 byte */ 148 #define URTW_SIFS 0x00b4 /* 1 byte */ 149 #define URTW_DIFS 0x00b5 /* 1 byte */ 150 #define URTW_SLOT 0x00b6 /* 1 byte */ 151 #define URTW_CW_CONF 0x00bc /* 1 byte */ 152 #define URTW_CW_CONF_PERPACKET_RETRY (0x2) 153 #define URTW_CW_CONF_PERPACKET_CW (0x1) 154 #define URTW_CW_VAL 0x00bd /* 1 byte */ 155 #define URTW_RATE_FALLBACK 0x00be /* 1 byte */ 156 #define URTW_TALLY_SEL 0x00fc /* 1 byte */ 157 158 /* for EEPROM */ 159 #define URTW_EPROM_TXPW_BASE 0x05 160 #define URTW_EPROM_RFCHIPID 0x06 161 #define URTW_EPROM_RFCHIPID_RTL8225U (5) 162 #define URTW_EPROM_MACADDR 0x07 163 #define URTW_EPROM_TXPW0 0x16 164 #define URTW_EPROM_TXPW2 0x1b 165 #define URTW_EPROM_TXPW1 0x3d 166 #define URTW_EPROM_SWREV 0x3f 167 #define URTW_EPROM_CID_MASK (0xff) 168 #define URTW_EPROM_CID_RSVD0 (0x00) 169 #define URTW_EPROM_CID_RSVD1 (0xff) 170 #define URTW_EPROM_CID_ALPHA0 (0x01) 171 #define URTW_EPROM_CID_SERCOMM_PS (0x02) 172 #define URTW_EPROM_CID_HW_LED (0x03) 173 174 /* LED */ 175 #define URTW_CID_DEFAULT 0 176 #define URTW_CID_8187_ALPHA0 1 177 #define URTW_CID_8187_SERCOMM_PS 2 178 #define URTW_CID_8187_HW_LED 3 179 #define URTW_SW_LED_MODE0 0 180 #define URTW_SW_LED_MODE1 1 181 #define URTW_SW_LED_MODE2 2 182 #define URTW_SW_LED_MODE3 3 183 #define URTW_HW_LED 4 184 #define URTW_LED_CTL_POWER_ON 0 185 #define URTW_LED_CTL_LINK 2 186 #define URTW_LED_CTL_TX 4 187 #define URTW_LED_PIN_GPIO0 0 188 #define URTW_LED_PIN_LED0 1 189 #define URTW_LED_PIN_LED1 2 190 #define URTW_LED_UNKNOWN 0 191 #define URTW_LED_ON 1 192 #define URTW_LED_OFF 2 193 #define URTW_LED_BLINK_NORMAL 3 194 #define URTW_LED_BLINK_SLOWLY 4 195 #define URTW_LED_POWER_ON_BLINK 5 196 #define URTW_LED_SCAN_BLINK 6 197 #define URTW_LED_NO_LINK_BLINK 7 198 #define URTW_LED_BLINK_CM3 8 199 200 /* for extra area */ 201 #define URTW_EPROM_DISABLE 0 202 #define URTW_EPROM_ENABLE 1 203 #define URTW_EPROM_DELAY 10 204 #define URTW_8187_GETREGS_REQ 5 205 #define URTW_8187_SETREGS_REQ 5 206 #define URTW_8225_RF_MAX_SENS 6 207 #define URTW_8225_RF_DEF_SENS 4 208 #define URTW_DEFAULT_RTS_RETRY 7 209 #define URTW_DEFAULT_TX_RETRY 7 210 #define URTW_DEFAULT_RTS_THRESHOLD 2342U 211 212 #define URTW_MAX_CHANNELS 15 213 214 struct urtw_data { 215 struct urtw_softc *sc; 216 usbd_xfer_handle xfer; 217 uint8_t *buf; 218 struct mbuf *m; 219 struct ieee80211_node *ni; /* NB: tx only */ 220 }; 221 222 /* XXX not correct.. */ 223 #define URTW_MIN_RXBUFSZ \ 224 (sizeof(struct ieee80211_frame_min)) 225 226 #define URTW_RX_DATA_LIST_COUNT 1 227 #define URTW_TX_DATA_LIST_COUNT 16 228 #define URTW_RX_MAXSIZE 0x9c4 229 #define URTW_TX_MAXSIZE 0x9c4 230 231 struct urtw_rx_radiotap_header { 232 struct ieee80211_radiotap_header wr_ihdr; 233 uint8_t wr_flags; 234 uint16_t wr_chan_freq; 235 uint16_t wr_chan_flags; 236 int8_t wr_dbm_antsignal; 237 } __packed; 238 239 #define URTW_RX_RADIOTAP_PRESENT \ 240 ((1 << IEEE80211_RADIOTAP_FLAGS) | \ 241 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 242 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL)) 243 244 struct urtw_tx_radiotap_header { 245 struct ieee80211_radiotap_header wt_ihdr; 246 uint8_t wt_flags; 247 uint8_t wt_rate; 248 uint16_t wt_chan_freq; 249 uint16_t wt_chan_flags; 250 } __packed; 251 252 #define URTW_TX_RADIOTAP_PRESENT \ 253 ((1 << IEEE80211_RADIOTAP_FLAGS) | \ 254 (1 << IEEE80211_RADIOTAP_CHANNEL)) 255 256 struct urtw_softc { 257 struct device sc_dev; 258 struct ieee80211com sc_ic; 259 int (*sc_newstate)(struct ieee80211com *, 260 enum ieee80211_state, int); 261 usbd_device_handle sc_udev; 262 usbd_interface_handle sc_iface; 263 264 int sc_debug; 265 int sc_if_flags; 266 int sc_flags; 267 #define URTW_INIT_ONCE (1 << 1) 268 struct usb_task sc_task; 269 #define URTW_SET_CHANNEL 1 270 enum ieee80211_state sc_state; 271 int sc_arg; 272 int sc_epromtype; 273 #define URTW_EEPROM_93C46 0 274 #define URTW_EEPROM_93C56 1 275 uint8_t sc_crcmon; 276 uint8_t sc_bssid[IEEE80211_ADDR_LEN]; 277 278 /* for RF */ 279 usbd_status (*sc_rf_init)(struct urtw_softc *); 280 usbd_status (*sc_rf_set_chan)(struct urtw_softc *, 281 int); 282 usbd_status (*sc_rf_set_sens)(struct urtw_softc *, 283 int); 284 uint8_t sc_rfchip; 285 uint32_t sc_max_sens; 286 uint32_t sc_sens; 287 /* for LED */ 288 struct timeout sc_led_ch; 289 struct usb_task sc_ledtask; 290 uint8_t sc_psr; 291 uint8_t sc_strategy; 292 #define URTW_LED_GPIO 1 293 uint8_t sc_gpio_ledon; 294 uint8_t sc_gpio_ledinprogress; 295 uint8_t sc_gpio_ledstate; 296 uint8_t sc_gpio_ledpin; 297 uint8_t sc_gpio_blinktime; 298 uint8_t sc_gpio_blinkstate; 299 /* RX/TX */ 300 usbd_pipe_handle sc_rxpipe; 301 usbd_pipe_handle sc_txpipe_low; 302 usbd_pipe_handle sc_txpipe_normal; 303 #define URTW_PRIORITY_LOW 0 304 #define URTW_PRIORITY_NORMAL 1 305 #define URTW_DATA_TIMEOUT 10000 /* 10 sec */ 306 struct urtw_data sc_rxdata[URTW_RX_DATA_LIST_COUNT]; 307 struct urtw_data sc_txdata[URTW_TX_DATA_LIST_COUNT]; 308 uint32_t sc_tx_low_queued; 309 uint32_t sc_tx_normal_queued; 310 uint32_t sc_txidx; 311 uint8_t sc_rts_retry; 312 uint8_t sc_tx_retry; 313 uint8_t sc_preamble_mode; 314 struct timeout scan_to; 315 int sc_txtimer; 316 int sc_currate; 317 /* TX power */ 318 uint8_t sc_txpwr_cck[URTW_MAX_CHANNELS]; 319 uint8_t sc_txpwr_cck_base; 320 uint8_t sc_txpwr_ofdm[URTW_MAX_CHANNELS]; 321 uint8_t sc_txpwr_ofdm_base; 322 323 #if NBPFILTER > 0 324 caddr_t sc_drvbpf; 325 326 union { 327 struct urtw_rx_radiotap_header th; 328 uint8_t pad[64]; 329 } sc_rxtapu; 330 #define sc_rxtap sc_rxtapu.th 331 int sc_rxtap_len; 332 333 union { 334 struct urtw_tx_radiotap_header th; 335 uint8_t pad[64]; 336 } sc_txtapu; 337 #define sc_txtap sc_txtapu.th 338 int sc_txtap_len; 339 #endif 340 }; 341