1 /* $OpenBSD: if_urtwn.c,v 1.107 2023/04/28 01:24:14 kevlo Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss@yahoo.com.au> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188FTV/RTL8188RU/ 23 * RTL8192CU/RTL8192EU. 24 */ 25 26 #include "bpfilter.h" 27 28 #include <sys/param.h> 29 #include <sys/sockio.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/timeout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 #include <sys/endian.h> 38 39 #include <machine/bus.h> 40 #include <machine/intr.h> 41 42 #if NBPFILTER > 0 43 #include <net/bpf.h> 44 #endif 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 49 #include <netinet/in.h> 50 #include <netinet/if_ether.h> 51 52 #include <net80211/ieee80211_var.h> 53 #include <net80211/ieee80211_amrr.h> 54 #include <net80211/ieee80211_radiotap.h> 55 56 #include <dev/usb/usb.h> 57 #include <dev/usb/usbdi.h> 58 #include <dev/usb/usbdivar.h> 59 #include <dev/usb/usbdi_util.h> 60 #include <dev/usb/usbdevs.h> 61 62 #include <dev/ic/r92creg.h> 63 #include <dev/ic/rtwnvar.h> 64 65 /* Maximum number of output pipes is 3. */ 66 #define R92C_MAX_EPOUT 3 67 68 #define R92C_HQ_NPAGES 12 69 #define R92C_LQ_NPAGES 2 70 #define R92C_NQ_NPAGES 2 71 #define R92C_TXPKTBUF_COUNT 256 72 #define R92C_TX_PAGE_COUNT 248 73 #define R92C_MAX_RX_DMA_SIZE 0x2800 74 75 #define R88E_HQ_NPAGES 0 76 #define R88E_LQ_NPAGES 9 77 #define R88E_NQ_NPAGES 0 78 #define R88E_TXPKTBUF_COUNT 177 79 #define R88E_TX_PAGE_COUNT 168 80 #define R88E_MAX_RX_DMA_SIZE 0x2400 81 82 #define R88F_HQ_NPAGES 12 83 #define R88F_LQ_NPAGES 2 84 #define R88F_NQ_NPAGES 2 85 #define R88F_TXPKTBUF_COUNT 177 86 #define R88F_TX_PAGE_COUNT 247 87 #define R88F_MAX_RX_DMA_SIZE 0x3f80 88 89 #define R92E_HQ_NPAGES 16 90 #define R92E_LQ_NPAGES 16 91 #define R92E_NQ_NPAGES 16 92 #define R92E_TX_PAGE_COUNT 248 93 #define R92E_MAX_RX_DMA_SIZE 0x3fc0 94 95 #define R92C_TXDESC_SUMSIZE 32 96 #define R92C_TXDESC_SUMOFFSET 14 97 98 /* USB Requests. */ 99 #define R92C_REQ_REGS 0x05 100 101 /* 102 * Driver definitions. 103 */ 104 #define URTWN_RX_LIST_COUNT 1 105 #define URTWN_TX_LIST_COUNT 8 106 #define URTWN_HOST_CMD_RING_COUNT 32 107 108 #define URTWN_RXBUFSZ (16 * 1024) 109 #define URTWN_TXBUFSZ (sizeof(struct r92e_tx_desc_usb) + IEEE80211_MAX_LEN) 110 111 #define URTWN_RIDX_COUNT 28 112 113 #define URTWN_TX_TIMEOUT 5000 /* ms */ 114 115 #define URTWN_LED_LINK 0 116 #define URTWN_LED_DATA 1 117 118 struct urtwn_rx_radiotap_header { 119 struct ieee80211_radiotap_header wr_ihdr; 120 uint8_t wr_flags; 121 uint8_t wr_rate; 122 uint16_t wr_chan_freq; 123 uint16_t wr_chan_flags; 124 uint8_t wr_dbm_antsignal; 125 } __packed; 126 127 #define URTWN_RX_RADIOTAP_PRESENT \ 128 (1 << IEEE80211_RADIOTAP_FLAGS | \ 129 1 << IEEE80211_RADIOTAP_RATE | \ 130 1 << IEEE80211_RADIOTAP_CHANNEL | \ 131 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) 132 133 struct urtwn_tx_radiotap_header { 134 struct ieee80211_radiotap_header wt_ihdr; 135 uint8_t wt_flags; 136 uint16_t wt_chan_freq; 137 uint16_t wt_chan_flags; 138 } __packed; 139 140 #define URTWN_TX_RADIOTAP_PRESENT \ 141 (1 << IEEE80211_RADIOTAP_FLAGS | \ 142 1 << IEEE80211_RADIOTAP_CHANNEL) 143 144 struct urtwn_softc; 145 146 struct urtwn_rx_data { 147 struct urtwn_softc *sc; 148 struct usbd_xfer *xfer; 149 uint8_t *buf; 150 }; 151 152 struct urtwn_tx_data { 153 struct urtwn_softc *sc; 154 struct usbd_pipe *pipe; 155 struct usbd_xfer *xfer; 156 uint8_t *buf; 157 TAILQ_ENTRY(urtwn_tx_data) next; 158 }; 159 160 struct urtwn_host_cmd { 161 void (*cb)(struct urtwn_softc *, void *); 162 uint8_t data[256]; 163 }; 164 165 struct urtwn_cmd_newstate { 166 enum ieee80211_state state; 167 int arg; 168 }; 169 170 struct urtwn_cmd_key { 171 struct ieee80211_key key; 172 struct ieee80211_node *ni; 173 }; 174 175 struct urtwn_host_cmd_ring { 176 struct urtwn_host_cmd cmd[URTWN_HOST_CMD_RING_COUNT]; 177 int cur; 178 int next; 179 int queued; 180 }; 181 182 struct urtwn_softc { 183 struct device sc_dev; 184 struct rtwn_softc sc_sc; 185 186 struct usbd_device *sc_udev; 187 struct usbd_interface *sc_iface; 188 struct usb_task sc_task; 189 190 struct timeout scan_to; 191 struct timeout calib_to; 192 193 int ntx; 194 struct usbd_pipe *rx_pipe; 195 struct usbd_pipe *tx_pipe[R92C_MAX_EPOUT]; 196 int ac2idx[EDCA_NUM_AC]; 197 198 struct urtwn_host_cmd_ring cmdq; 199 struct urtwn_rx_data rx_data[URTWN_RX_LIST_COUNT]; 200 struct urtwn_tx_data tx_data[URTWN_TX_LIST_COUNT]; 201 TAILQ_HEAD(, urtwn_tx_data) tx_free_list; 202 203 struct ieee80211_amrr amrr; 204 struct ieee80211_amrr_node amn; 205 206 #if NBPFILTER > 0 207 caddr_t sc_drvbpf; 208 209 union { 210 struct urtwn_rx_radiotap_header th; 211 uint8_t pad[64]; 212 } sc_rxtapu; 213 #define sc_rxtap sc_rxtapu.th 214 int sc_rxtap_len; 215 216 union { 217 struct urtwn_tx_radiotap_header th; 218 uint8_t pad[64]; 219 } sc_txtapu; 220 #define sc_txtap sc_txtapu.th 221 int sc_txtap_len; 222 #endif 223 int sc_key_tasks; 224 }; 225 226 #ifdef URTWN_DEBUG 227 #define DPRINTF(x) do { if (urtwn_debug) printf x; } while (0) 228 #define DPRINTFN(n, x) do { if (urtwn_debug >= (n)) printf x; } while (0) 229 int urtwn_debug = 4; 230 #else 231 #define DPRINTF(x) 232 #define DPRINTFN(n, x) 233 #endif 234 235 /* 236 * Various supported device vendors/products. 237 */ 238 #define URTWN_DEV(v, p, f) \ 239 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, (f) | RTWN_CHIP_USB } 240 #define URTWN_DEV_8192CU(v, p) URTWN_DEV(v, p, RTWN_CHIP_92C | RTWN_CHIP_88C) 241 #define URTWN_DEV_8192EU(v, p) URTWN_DEV(v, p, RTWN_CHIP_92E) 242 #define URTWN_DEV_8188EU(v, p) URTWN_DEV(v, p, RTWN_CHIP_88E) 243 #define URTWN_DEV_8188F(v, p) URTWN_DEV(v, p, RTWN_CHIP_88F) 244 static const struct urtwn_type { 245 struct usb_devno dev; 246 uint32_t chip; 247 } urtwn_devs[] = { 248 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_1), 249 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_1), 250 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_2), 251 URTWN_DEV_8192CU(ABOCOM, RTL8192CU), 252 URTWN_DEV_8192CU(ASUS, RTL8192CU), 253 URTWN_DEV_8192CU(ASUS, RTL8192CU_2), 254 URTWN_DEV_8192CU(ASUS, RTL8192CU_3), 255 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CE_1), 256 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CE_2), 257 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CU), 258 URTWN_DEV_8192CU(BELKIN, F7D2102), 259 URTWN_DEV_8192CU(BELKIN, F9L1004V1), 260 URTWN_DEV_8192CU(BELKIN, RTL8188CU), 261 URTWN_DEV_8192CU(BELKIN, RTL8188CUS), 262 URTWN_DEV_8192CU(BELKIN, RTL8192CU), 263 URTWN_DEV_8192CU(BELKIN, RTL8192CU_1), 264 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_1), 265 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_2), 266 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_3), 267 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_4), 268 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_5), 269 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_6), 270 URTWN_DEV_8192CU(COMPARE, RTL8192CU), 271 URTWN_DEV_8192CU(COREGA, RTL8192CU), 272 URTWN_DEV_8192CU(DLINK, DWA131B), 273 URTWN_DEV_8192CU(DLINK, RTL8188CU), 274 URTWN_DEV_8192CU(DLINK, RTL8192CU_1), 275 URTWN_DEV_8192CU(DLINK, RTL8192CU_2), 276 URTWN_DEV_8192CU(DLINK, RTL8192CU_3), 277 URTWN_DEV_8192CU(DLINK, RTL8192CU_4), 278 URTWN_DEV_8192CU(EDIMAX, EW7811UN), 279 URTWN_DEV_8192CU(EDIMAX, RTL8192CU), 280 URTWN_DEV_8192CU(FEIXUN, RTL8188CU), 281 URTWN_DEV_8192CU(FEIXUN, RTL8192CU), 282 URTWN_DEV_8192CU(GUILLEMOT, HWNUP150), 283 URTWN_DEV_8192CU(GUILLEMOT, RTL8192CU), 284 URTWN_DEV_8192CU(HAWKING, RTL8192CU), 285 URTWN_DEV_8192CU(HAWKING, RTL8192CU_2), 286 URTWN_DEV_8192CU(HP3, RTL8188CU), 287 URTWN_DEV_8192CU(IODATA, WNG150UM), 288 URTWN_DEV_8192CU(IODATA, RTL8192CU), 289 URTWN_DEV_8192CU(NETGEAR, N300MA), 290 URTWN_DEV_8192CU(NETGEAR, WNA1000M), 291 URTWN_DEV_8192CU(NETGEAR, WNA1000MV2), 292 URTWN_DEV_8192CU(NETGEAR, RTL8192CU), 293 URTWN_DEV_8192CU(NETGEAR4, RTL8188CU), 294 URTWN_DEV_8192CU(NETWEEN, RTL8192CU), 295 URTWN_DEV_8192CU(NOVATECH, RTL8188CU), 296 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_1), 297 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_2), 298 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_3), 299 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_4), 300 URTWN_DEV_8192CU(PLANEX2, RTL8188CUS), 301 URTWN_DEV_8192CU(PLANEX2, RTL8192CU), 302 URTWN_DEV_8192CU(REALTEK, RTL8188CE_0), 303 URTWN_DEV_8192CU(REALTEK, RTL8188CE_1), 304 URTWN_DEV_8192CU(REALTEK, RTL8188CTV), 305 URTWN_DEV_8192CU(REALTEK, RTL8188CU_0), 306 URTWN_DEV_8192CU(REALTEK, RTL8188CU_1), 307 URTWN_DEV_8192CU(REALTEK, RTL8188CU_2), 308 URTWN_DEV_8192CU(REALTEK, RTL8188CU_3), 309 URTWN_DEV_8192CU(REALTEK, RTL8188CU_4), 310 URTWN_DEV_8192CU(REALTEK, RTL8188CU_5), 311 URTWN_DEV_8192CU(REALTEK, RTL8188CU_COMBO), 312 URTWN_DEV_8192CU(REALTEK, RTL8188CUS), 313 URTWN_DEV_8192CU(REALTEK, RTL8188RU), 314 URTWN_DEV_8192CU(REALTEK, RTL8188RU_2), 315 URTWN_DEV_8192CU(REALTEK, RTL8188RU_3), 316 URTWN_DEV_8192CU(REALTEK, RTL8191CU), 317 URTWN_DEV_8192CU(REALTEK, RTL8192CE), 318 URTWN_DEV_8192CU(REALTEK, RTL8192CE_VAU), 319 URTWN_DEV_8192CU(REALTEK, RTL8192CU), 320 URTWN_DEV_8192CU(SITECOMEU, RTL8188CU), 321 URTWN_DEV_8192CU(SITECOMEU, RTL8188CU_2), 322 URTWN_DEV_8192CU(SITECOMEU, RTL8192CU), 323 URTWN_DEV_8192CU(SITECOMEU, RTL8192CU_2), 324 URTWN_DEV_8192CU(SITECOMEU, WLA2100V2), 325 URTWN_DEV_8192CU(TPLINK, RTL8192CU), 326 URTWN_DEV_8192CU(TRENDNET, RTL8188CU), 327 URTWN_DEV_8192CU(TRENDNET, RTL8192CU), 328 URTWN_DEV_8192CU(ZYXEL, RTL8192CU), 329 /* URTWN_RTL8188E */ 330 URTWN_DEV_8188EU(ABOCOM, RTL8188EU), 331 URTWN_DEV_8188EU(DLINK, DWA121B1), 332 URTWN_DEV_8188EU(DLINK, DWA123D1), 333 URTWN_DEV_8188EU(DLINK, DWA125D1), 334 URTWN_DEV_8188EU(EDIMAX, EW7811UNV2), 335 URTWN_DEV_8188EU(ELECOM, WDC150SU2M), 336 URTWN_DEV_8188EU(REALTEK, RTL8188ETV), 337 URTWN_DEV_8188EU(REALTEK, RTL8188EU), 338 URTWN_DEV_8188EU(TPLINK, RTL8188EUS), 339 URTWN_DEV_8188EU(ASUS, RTL8188EUS), 340 /* URTWN_RTL8188FTV */ 341 URTWN_DEV_8188F(REALTEK, RTL8188FTV), 342 343 /* URTWN_RTL8192EU */ 344 URTWN_DEV_8192EU(DLINK, DWA131E1), 345 URTWN_DEV_8192EU(REALTEK, RTL8192EU), 346 URTWN_DEV_8192EU(TPLINK, RTL8192EU), 347 URTWN_DEV_8192EU(TPLINK, RTL8192EU_2), 348 URTWN_DEV_8192EU(TPLINK, RTL8192EU_3) 349 }; 350 351 #define urtwn_lookup(v, p) \ 352 ((const struct urtwn_type *)usb_lookup(urtwn_devs, v, p)) 353 354 int urtwn_match(struct device *, void *, void *); 355 void urtwn_attach(struct device *, struct device *, void *); 356 int urtwn_detach(struct device *, int); 357 int urtwn_open_pipes(struct urtwn_softc *); 358 void urtwn_close_pipes(struct urtwn_softc *); 359 int urtwn_alloc_rx_list(struct urtwn_softc *); 360 void urtwn_free_rx_list(struct urtwn_softc *); 361 int urtwn_alloc_tx_list(struct urtwn_softc *); 362 void urtwn_free_tx_list(struct urtwn_softc *); 363 void urtwn_task(void *); 364 void urtwn_do_async(struct urtwn_softc *, 365 void (*)(struct urtwn_softc *, void *), void *, int); 366 void urtwn_wait_async(void *); 367 int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 368 int); 369 void urtwn_write_1(void *, uint16_t, uint8_t); 370 void urtwn_write_2(void *, uint16_t, uint16_t); 371 void urtwn_write_4(void *, uint16_t, uint32_t); 372 int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 373 int); 374 uint8_t urtwn_read_1(void *, uint16_t); 375 uint16_t urtwn_read_2(void *, uint16_t); 376 uint32_t urtwn_read_4(void *, uint16_t); 377 int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 378 void urtwn_calib_to(void *); 379 void urtwn_calib_cb(struct urtwn_softc *, void *); 380 void urtwn_scan_to(void *); 381 void urtwn_next_scan(void *); 382 void urtwn_cancel_scan(void *); 383 int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 384 int); 385 void urtwn_newstate_cb(struct urtwn_softc *, void *); 386 void urtwn_updateslot(struct ieee80211com *); 387 void urtwn_updateslot_cb(struct urtwn_softc *, void *); 388 void urtwn_updateedca(struct ieee80211com *); 389 void urtwn_updateedca_cb(struct urtwn_softc *, void *); 390 int urtwn_set_key(struct ieee80211com *, struct ieee80211_node *, 391 struct ieee80211_key *); 392 void urtwn_set_key_cb(struct urtwn_softc *, void *); 393 void urtwn_delete_key(struct ieee80211com *, 394 struct ieee80211_node *, struct ieee80211_key *); 395 void urtwn_delete_key_cb(struct urtwn_softc *, void *); 396 void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 397 struct mbuf_list *); 398 void urtwn_rxeof(struct usbd_xfer *, void *, 399 usbd_status); 400 void urtwn_txeof(struct usbd_xfer *, void *, 401 usbd_status); 402 int urtwn_tx(void *, struct mbuf *, struct ieee80211_node *); 403 int urtwn_ioctl(struct ifnet *, u_long, caddr_t); 404 int urtwn_power_on(void *); 405 int urtwn_alloc_buffers(void *); 406 int urtwn_r92c_power_on(struct urtwn_softc *); 407 int urtwn_r92e_power_on(struct urtwn_softc *); 408 int urtwn_r88e_power_on(struct urtwn_softc *); 409 int urtwn_r88f_power_on(struct urtwn_softc *); 410 int urtwn_llt_init(struct urtwn_softc *, int); 411 int urtwn_fw_loadpage(void *, int, uint8_t *, int); 412 int urtwn_load_firmware(void *, u_char **, size_t *); 413 int urtwn_dma_init(void *); 414 void urtwn_aggr_init(void *); 415 void urtwn_mac_init(void *); 416 void urtwn_bb_init(void *); 417 void urtwn_burstlen_init(struct urtwn_softc *); 418 int urtwn_init(void *); 419 void urtwn_stop(void *); 420 int urtwn_is_oactive(void *); 421 void urtwn_next_calib(void *); 422 void urtwn_cancel_calib(void *); 423 424 /* Aliases. */ 425 #define urtwn_bb_write urtwn_write_4 426 #define urtwn_bb_read urtwn_read_4 427 428 struct cfdriver urtwn_cd = { 429 NULL, "urtwn", DV_IFNET 430 }; 431 432 const struct cfattach urtwn_ca = { 433 sizeof(struct urtwn_softc), urtwn_match, urtwn_attach, urtwn_detach 434 }; 435 436 int 437 urtwn_match(struct device *parent, void *match, void *aux) 438 { 439 struct usb_attach_arg *uaa = aux; 440 441 if (uaa->iface == NULL || uaa->configno != 1) 442 return (UMATCH_NONE); 443 444 return ((urtwn_lookup(uaa->vendor, uaa->product) != NULL) ? 445 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 446 } 447 448 void 449 urtwn_attach(struct device *parent, struct device *self, void *aux) 450 { 451 struct urtwn_softc *sc = (struct urtwn_softc *)self; 452 struct usb_attach_arg *uaa = aux; 453 struct ifnet *ifp; 454 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 455 456 sc->sc_udev = uaa->device; 457 sc->sc_iface = uaa->iface; 458 459 sc->sc_sc.chip = urtwn_lookup(uaa->vendor, uaa->product)->chip; 460 461 usb_init_task(&sc->sc_task, urtwn_task, sc, USB_TASK_TYPE_GENERIC); 462 timeout_set(&sc->scan_to, urtwn_scan_to, sc); 463 timeout_set(&sc->calib_to, urtwn_calib_to, sc); 464 if (urtwn_open_pipes(sc) != 0) 465 return; 466 467 sc->amrr.amrr_min_success_threshold = 1; 468 sc->amrr.amrr_max_success_threshold = 10; 469 470 /* Attach the bus-agnostic driver. */ 471 sc->sc_sc.sc_ops.cookie = sc; 472 sc->sc_sc.sc_ops.write_1 = urtwn_write_1; 473 sc->sc_sc.sc_ops.write_2 = urtwn_write_2; 474 sc->sc_sc.sc_ops.write_4 = urtwn_write_4; 475 sc->sc_sc.sc_ops.read_1 = urtwn_read_1; 476 sc->sc_sc.sc_ops.read_2 = urtwn_read_2; 477 sc->sc_sc.sc_ops.read_4 = urtwn_read_4; 478 sc->sc_sc.sc_ops.tx = urtwn_tx; 479 sc->sc_sc.sc_ops.power_on = urtwn_power_on; 480 sc->sc_sc.sc_ops.dma_init = urtwn_dma_init; 481 sc->sc_sc.sc_ops.fw_loadpage = urtwn_fw_loadpage; 482 sc->sc_sc.sc_ops.load_firmware = urtwn_load_firmware; 483 sc->sc_sc.sc_ops.aggr_init = urtwn_aggr_init; 484 sc->sc_sc.sc_ops.mac_init = urtwn_mac_init; 485 sc->sc_sc.sc_ops.bb_init = urtwn_bb_init; 486 sc->sc_sc.sc_ops.alloc_buffers = urtwn_alloc_buffers; 487 sc->sc_sc.sc_ops.init = urtwn_init; 488 sc->sc_sc.sc_ops.stop = urtwn_stop; 489 sc->sc_sc.sc_ops.is_oactive = urtwn_is_oactive; 490 sc->sc_sc.sc_ops.next_calib = urtwn_next_calib; 491 sc->sc_sc.sc_ops.cancel_calib = urtwn_cancel_calib; 492 sc->sc_sc.sc_ops.next_scan = urtwn_next_scan; 493 sc->sc_sc.sc_ops.cancel_scan = urtwn_cancel_scan; 494 sc->sc_sc.sc_ops.wait_async = urtwn_wait_async; 495 if (rtwn_attach(&sc->sc_dev, &sc->sc_sc) != 0) { 496 urtwn_close_pipes(sc); 497 return; 498 } 499 500 /* ifp is now valid */ 501 ifp = &sc->sc_sc.sc_ic.ic_if; 502 ifp->if_ioctl = urtwn_ioctl; 503 504 ic->ic_updateslot = urtwn_updateslot; 505 ic->ic_updateedca = urtwn_updateedca; 506 ic->ic_set_key = urtwn_set_key; 507 ic->ic_delete_key = urtwn_delete_key; 508 /* Override state transition machine. */ 509 ic->ic_newstate = urtwn_newstate; 510 511 #if NBPFILTER > 0 512 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 513 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 514 515 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 516 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 517 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 518 519 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 520 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 521 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 522 #endif 523 } 524 525 int 526 urtwn_detach(struct device *self, int flags) 527 { 528 struct urtwn_softc *sc = (struct urtwn_softc *)self; 529 int s; 530 531 s = splusb(); 532 533 if (timeout_initialized(&sc->scan_to)) 534 timeout_del(&sc->scan_to); 535 if (timeout_initialized(&sc->calib_to)) 536 timeout_del(&sc->calib_to); 537 538 /* Wait for all async commands to complete. */ 539 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 540 541 usbd_ref_wait(sc->sc_udev); 542 543 rtwn_detach(&sc->sc_sc, flags); 544 545 /* Abort and close Tx/Rx pipes. */ 546 urtwn_close_pipes(sc); 547 548 /* Free Tx/Rx buffers. */ 549 urtwn_free_tx_list(sc); 550 urtwn_free_rx_list(sc); 551 splx(s); 552 553 return (0); 554 } 555 556 int 557 urtwn_open_pipes(struct urtwn_softc *sc) 558 { 559 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 560 uint8_t epaddr[R92C_MAX_EPOUT] = { 0, 0, 0 }; 561 uint8_t rx_no; 562 usb_interface_descriptor_t *id; 563 usb_endpoint_descriptor_t *ed; 564 int i, error, nrx = 0; 565 566 /* Find all bulk endpoints. */ 567 id = usbd_get_interface_descriptor(sc->sc_iface); 568 for (i = 0; i < id->bNumEndpoints; i++) { 569 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 570 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) 571 continue; 572 573 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 574 rx_no = ed->bEndpointAddress; 575 nrx++; 576 } else { 577 if (sc->ntx < R92C_MAX_EPOUT) 578 epaddr[sc->ntx] = ed->bEndpointAddress; 579 sc->ntx++; 580 } 581 } 582 if (nrx == 0) { 583 printf("%s: %d: invalid number of Rx bulk pipes\n", 584 sc->sc_dev.dv_xname, nrx); 585 return (EIO); 586 } 587 DPRINTF(("found %d bulk-out pipes\n", sc->ntx)); 588 if (sc->ntx == 0 || sc->ntx > R92C_MAX_EPOUT) { 589 printf("%s: %d: invalid number of Tx bulk pipes\n", 590 sc->sc_dev.dv_xname, sc->ntx); 591 return (EIO); 592 } 593 594 /* Open bulk-in pipe. */ 595 error = usbd_open_pipe(sc->sc_iface, rx_no, 0, &sc->rx_pipe); 596 if (error != 0) { 597 printf("%s: could not open Rx bulk pipe\n", 598 sc->sc_dev.dv_xname); 599 goto fail; 600 } 601 602 /* Open bulk-out pipes (up to 3). */ 603 for (i = 0; i < sc->ntx; i++) { 604 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 0, 605 &sc->tx_pipe[i]); 606 if (error != 0) { 607 printf("%s: could not open Tx bulk pipe 0x%02x\n", 608 sc->sc_dev.dv_xname, epaddr[i]); 609 goto fail; 610 } 611 } 612 613 /* Map 802.11 access categories to USB pipes. */ 614 sc->ac2idx[EDCA_AC_BK] = 615 sc->ac2idx[EDCA_AC_BE] = (sc->ntx == 3) ? 2 : ((sc->ntx == 2) ? 1 : 0); 616 sc->ac2idx[EDCA_AC_VI] = (sc->ntx == 3) ? 1 : 0; 617 sc->ac2idx[EDCA_AC_VO] = 0; /* Always use highest prio. */ 618 619 if (error != 0) 620 fail: urtwn_close_pipes(sc); 621 return (error); 622 } 623 624 void 625 urtwn_close_pipes(struct urtwn_softc *sc) 626 { 627 int i; 628 629 /* Close Rx pipe. */ 630 if (sc->rx_pipe != NULL) { 631 usbd_close_pipe(sc->rx_pipe); 632 sc->rx_pipe = NULL; 633 } 634 /* Close Tx pipes. */ 635 for (i = 0; i < R92C_MAX_EPOUT; i++) { 636 if (sc->tx_pipe[i] == NULL) 637 continue; 638 usbd_close_pipe(sc->tx_pipe[i]); 639 sc->tx_pipe[i] = NULL; 640 } 641 } 642 643 int 644 urtwn_alloc_rx_list(struct urtwn_softc *sc) 645 { 646 struct urtwn_rx_data *data; 647 int i, error = 0; 648 649 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 650 data = &sc->rx_data[i]; 651 652 data->sc = sc; /* Backpointer for callbacks. */ 653 654 data->xfer = usbd_alloc_xfer(sc->sc_udev); 655 if (data->xfer == NULL) { 656 printf("%s: could not allocate xfer\n", 657 sc->sc_dev.dv_xname); 658 error = ENOMEM; 659 break; 660 } 661 data->buf = usbd_alloc_buffer(data->xfer, URTWN_RXBUFSZ); 662 if (data->buf == NULL) { 663 printf("%s: could not allocate xfer buffer\n", 664 sc->sc_dev.dv_xname); 665 error = ENOMEM; 666 break; 667 } 668 } 669 if (error != 0) 670 urtwn_free_rx_list(sc); 671 return (error); 672 } 673 674 void 675 urtwn_free_rx_list(struct urtwn_softc *sc) 676 { 677 int i; 678 679 /* NB: Caller must abort pipe first. */ 680 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 681 if (sc->rx_data[i].xfer != NULL) 682 usbd_free_xfer(sc->rx_data[i].xfer); 683 sc->rx_data[i].xfer = NULL; 684 } 685 } 686 687 int 688 urtwn_alloc_tx_list(struct urtwn_softc *sc) 689 { 690 struct urtwn_tx_data *data; 691 int i, error = 0; 692 693 TAILQ_INIT(&sc->tx_free_list); 694 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 695 data = &sc->tx_data[i]; 696 697 data->sc = sc; /* Backpointer for callbacks. */ 698 699 data->xfer = usbd_alloc_xfer(sc->sc_udev); 700 if (data->xfer == NULL) { 701 printf("%s: could not allocate xfer\n", 702 sc->sc_dev.dv_xname); 703 error = ENOMEM; 704 break; 705 } 706 data->buf = usbd_alloc_buffer(data->xfer, URTWN_TXBUFSZ); 707 if (data->buf == NULL) { 708 printf("%s: could not allocate xfer buffer\n", 709 sc->sc_dev.dv_xname); 710 error = ENOMEM; 711 break; 712 } 713 /* Append this Tx buffer to our free list. */ 714 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 715 } 716 if (error != 0) 717 urtwn_free_tx_list(sc); 718 return (error); 719 } 720 721 void 722 urtwn_free_tx_list(struct urtwn_softc *sc) 723 { 724 int i; 725 726 /* NB: Caller must abort pipe first. */ 727 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 728 if (sc->tx_data[i].xfer != NULL) 729 usbd_free_xfer(sc->tx_data[i].xfer); 730 sc->tx_data[i].xfer = NULL; 731 } 732 } 733 734 void 735 urtwn_task(void *arg) 736 { 737 struct urtwn_softc *sc = arg; 738 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 739 struct urtwn_host_cmd *cmd; 740 int s; 741 742 /* Process host commands. */ 743 s = splusb(); 744 while (ring->next != ring->cur) { 745 cmd = &ring->cmd[ring->next]; 746 splx(s); 747 /* Invoke callback. */ 748 cmd->cb(sc, cmd->data); 749 s = splusb(); 750 ring->queued--; 751 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 752 } 753 splx(s); 754 } 755 756 void 757 urtwn_do_async(struct urtwn_softc *sc, 758 void (*cb)(struct urtwn_softc *, void *), void *arg, int len) 759 { 760 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 761 struct urtwn_host_cmd *cmd; 762 int s; 763 764 s = splusb(); 765 cmd = &ring->cmd[ring->cur]; 766 cmd->cb = cb; 767 KASSERT(len <= sizeof(cmd->data)); 768 memcpy(cmd->data, arg, len); 769 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 770 771 /* If there is no pending command already, schedule a task. */ 772 if (++ring->queued == 1) 773 usb_add_task(sc->sc_udev, &sc->sc_task); 774 splx(s); 775 } 776 777 void 778 urtwn_wait_async(void *cookie) 779 { 780 struct urtwn_softc *sc = cookie; 781 int s; 782 783 s = splusb(); 784 /* Wait for all queued asynchronous commands to complete. */ 785 usb_wait_task(sc->sc_udev, &sc->sc_task); 786 splx(s); 787 } 788 789 int 790 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 791 int len) 792 { 793 usb_device_request_t req; 794 795 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 796 req.bRequest = R92C_REQ_REGS; 797 USETW(req.wValue, addr); 798 USETW(req.wIndex, 0); 799 USETW(req.wLength, len); 800 return (usbd_do_request(sc->sc_udev, &req, buf)); 801 } 802 803 void 804 urtwn_write_1(void *cookie, uint16_t addr, uint8_t val) 805 { 806 struct urtwn_softc *sc = cookie; 807 808 urtwn_write_region_1(sc, addr, &val, 1); 809 } 810 811 void 812 urtwn_write_2(void *cookie, uint16_t addr, uint16_t val) 813 { 814 struct urtwn_softc *sc = cookie; 815 816 val = htole16(val); 817 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 818 } 819 820 void 821 urtwn_write_4(void *cookie, uint16_t addr, uint32_t val) 822 { 823 struct urtwn_softc *sc = cookie; 824 825 val = htole32(val); 826 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 827 } 828 829 int 830 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 831 int len) 832 { 833 usb_device_request_t req; 834 835 req.bmRequestType = UT_READ_VENDOR_DEVICE; 836 req.bRequest = R92C_REQ_REGS; 837 USETW(req.wValue, addr); 838 USETW(req.wIndex, 0); 839 USETW(req.wLength, len); 840 return (usbd_do_request(sc->sc_udev, &req, buf)); 841 } 842 843 uint8_t 844 urtwn_read_1(void *cookie, uint16_t addr) 845 { 846 struct urtwn_softc *sc = cookie; 847 uint8_t val; 848 849 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 850 return (0xff); 851 return (val); 852 } 853 854 uint16_t 855 urtwn_read_2(void *cookie, uint16_t addr) 856 { 857 struct urtwn_softc *sc = cookie; 858 uint16_t val; 859 860 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 861 return (0xffff); 862 return (letoh16(val)); 863 } 864 865 uint32_t 866 urtwn_read_4(void *cookie, uint16_t addr) 867 { 868 struct urtwn_softc *sc = cookie; 869 uint32_t val; 870 871 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 872 return (0xffffffff); 873 return (letoh32(val)); 874 } 875 876 int 877 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 878 { 879 int ntries; 880 881 urtwn_write_4(sc, R92C_LLT_INIT, 882 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 883 SM(R92C_LLT_INIT_ADDR, addr) | 884 SM(R92C_LLT_INIT_DATA, data)); 885 /* Wait for write operation to complete. */ 886 for (ntries = 0; ntries < 20; ntries++) { 887 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 888 R92C_LLT_INIT_OP_NO_ACTIVE) 889 return (0); 890 DELAY(5); 891 } 892 return (ETIMEDOUT); 893 } 894 895 void 896 urtwn_calib_to(void *arg) 897 { 898 struct urtwn_softc *sc = arg; 899 900 if (usbd_is_dying(sc->sc_udev)) 901 return; 902 903 usbd_ref_incr(sc->sc_udev); 904 905 /* Do it in a process context. */ 906 urtwn_do_async(sc, urtwn_calib_cb, NULL, 0); 907 908 usbd_ref_decr(sc->sc_udev); 909 } 910 911 void 912 urtwn_calib_cb(struct urtwn_softc *sc, void *arg) 913 { 914 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 915 int s; 916 917 s = splnet(); 918 if (ic->ic_opmode == IEEE80211_M_STA) { 919 ieee80211_amrr_choose(&sc->amrr, ic->ic_bss, &sc->amn); 920 } 921 splx(s); 922 923 rtwn_calib(&sc->sc_sc); 924 } 925 926 void 927 urtwn_next_calib(void *cookie) 928 { 929 struct urtwn_softc *sc = cookie; 930 931 if (!usbd_is_dying(sc->sc_udev)) 932 timeout_add_sec(&sc->calib_to, 2); 933 } 934 935 void 936 urtwn_cancel_calib(void *cookie) 937 { 938 struct urtwn_softc *sc = cookie; 939 940 if (timeout_initialized(&sc->calib_to)) 941 timeout_del(&sc->calib_to); 942 } 943 944 void 945 urtwn_scan_to(void *arg) 946 { 947 struct urtwn_softc *sc = arg; 948 949 if (usbd_is_dying(sc->sc_udev)) 950 return; 951 952 usbd_ref_incr(sc->sc_udev); 953 rtwn_next_scan(&sc->sc_sc); 954 usbd_ref_decr(sc->sc_udev); 955 } 956 957 void 958 urtwn_next_scan(void *arg) 959 { 960 struct urtwn_softc *sc = arg; 961 962 if (!usbd_is_dying(sc->sc_udev)) 963 timeout_add_msec(&sc->scan_to, 200); 964 } 965 966 void 967 urtwn_cancel_scan(void *cookie) 968 { 969 struct urtwn_softc *sc = cookie; 970 971 if (timeout_initialized(&sc->scan_to)) 972 timeout_del(&sc->scan_to); 973 } 974 975 int 976 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 977 { 978 struct rtwn_softc *sc_sc = ic->ic_softc; 979 struct device *self = sc_sc->sc_pdev; 980 struct urtwn_softc *sc = (struct urtwn_softc *)self; 981 struct urtwn_cmd_newstate cmd; 982 983 /* Do it in a process context. */ 984 cmd.state = nstate; 985 cmd.arg = arg; 986 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 987 return (0); 988 } 989 990 void 991 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 992 { 993 struct urtwn_cmd_newstate *cmd = arg; 994 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 995 996 rtwn_newstate(ic, cmd->state, cmd->arg); 997 } 998 999 void 1000 urtwn_updateslot(struct ieee80211com *ic) 1001 { 1002 struct rtwn_softc *sc_sc = ic->ic_softc; 1003 struct device *self = sc_sc->sc_pdev; 1004 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1005 1006 /* Do it in a process context. */ 1007 urtwn_do_async(sc, urtwn_updateslot_cb, NULL, 0); 1008 } 1009 1010 void 1011 urtwn_updateslot_cb(struct urtwn_softc *sc, void *arg) 1012 { 1013 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1014 1015 rtwn_updateslot(ic); 1016 } 1017 1018 void 1019 urtwn_updateedca(struct ieee80211com *ic) 1020 { 1021 struct rtwn_softc *sc_sc = ic->ic_softc; 1022 struct device *self = sc_sc->sc_pdev; 1023 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1024 1025 /* Do it in a process context. */ 1026 urtwn_do_async(sc, urtwn_updateedca_cb, NULL, 0); 1027 } 1028 1029 void 1030 urtwn_updateedca_cb(struct urtwn_softc *sc, void *arg) 1031 { 1032 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1033 1034 rtwn_updateedca(ic); 1035 } 1036 1037 int 1038 urtwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1039 struct ieee80211_key *k) 1040 { 1041 struct rtwn_softc *sc_sc = ic->ic_softc; 1042 struct device *self = sc_sc->sc_pdev; 1043 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1044 struct urtwn_cmd_key cmd; 1045 1046 /* Only handle keys for CCMP */ 1047 if (k->k_cipher != IEEE80211_CIPHER_CCMP) 1048 return ieee80211_set_key(ic, ni, k); 1049 1050 /* Defer setting of WEP keys until interface is brought up. */ 1051 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 1052 (IFF_UP | IFF_RUNNING)) 1053 return (0); 1054 1055 /* Do it in a process context. */ 1056 cmd.key = *k; 1057 cmd.ni = ni; 1058 urtwn_do_async(sc, urtwn_set_key_cb, &cmd, sizeof(cmd)); 1059 sc->sc_key_tasks++; 1060 1061 return (EBUSY); 1062 } 1063 1064 void 1065 urtwn_set_key_cb(struct urtwn_softc *sc, void *arg) 1066 { 1067 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1068 struct urtwn_cmd_key *cmd = arg; 1069 1070 sc->sc_key_tasks--; 1071 1072 if (rtwn_set_key(ic, cmd->ni, &cmd->key) == 0) { 1073 if (sc->sc_key_tasks == 0) { 1074 DPRINTF(("marking port %s valid\n", 1075 ether_sprintf(cmd->ni->ni_macaddr))); 1076 cmd->ni->ni_port_valid = 1; 1077 ieee80211_set_link_state(ic, LINK_STATE_UP); 1078 } 1079 } else { 1080 IEEE80211_SEND_MGMT(ic, cmd->ni, IEEE80211_FC0_SUBTYPE_DEAUTH, 1081 IEEE80211_REASON_AUTH_LEAVE); 1082 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1083 } 1084 } 1085 1086 void 1087 urtwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1088 struct ieee80211_key *k) 1089 { 1090 struct rtwn_softc *sc_sc = ic->ic_softc; 1091 struct device *self = sc_sc->sc_pdev; 1092 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1093 struct urtwn_cmd_key cmd; 1094 1095 /* Only handle keys for CCMP */ 1096 if (k->k_cipher != IEEE80211_CIPHER_CCMP) { 1097 ieee80211_delete_key(ic, ni, k); 1098 return; 1099 } 1100 1101 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 1102 ic->ic_state != IEEE80211_S_RUN) 1103 return; /* Nothing to do. */ 1104 1105 /* Do it in a process context. */ 1106 cmd.key = *k; 1107 cmd.ni = ni; 1108 urtwn_do_async(sc, urtwn_delete_key_cb, &cmd, sizeof(cmd)); 1109 } 1110 1111 void 1112 urtwn_delete_key_cb(struct urtwn_softc *sc, void *arg) 1113 { 1114 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1115 struct urtwn_cmd_key *cmd = arg; 1116 1117 rtwn_delete_key(ic, cmd->ni, &cmd->key); 1118 } 1119 1120 int 1121 urtwn_ccmp_decap(struct urtwn_softc *sc, struct mbuf *m, 1122 struct ieee80211_node *ni) 1123 { 1124 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1125 struct ieee80211_key *k; 1126 struct ieee80211_frame *wh; 1127 uint64_t pn, *prsc; 1128 uint8_t *ivp; 1129 uint8_t tid; 1130 int hdrlen, hasqos; 1131 1132 k = ieee80211_get_rxkey(ic, m, ni); 1133 if (k == NULL) 1134 return 1; 1135 1136 wh = mtod(m, struct ieee80211_frame *); 1137 hdrlen = ieee80211_get_hdrlen(wh); 1138 ivp = (uint8_t *)wh + hdrlen; 1139 1140 /* Check that ExtIV bit is set. */ 1141 if (!(ivp[3] & IEEE80211_WEP_EXTIV)) 1142 return 1; 1143 1144 hasqos = ieee80211_has_qos(wh); 1145 tid = hasqos ? ieee80211_get_qos(wh) & IEEE80211_QOS_TID : 0; 1146 prsc = &k->k_rsc[tid]; 1147 1148 /* Extract the 48-bit PN from the CCMP header. */ 1149 pn = (uint64_t)ivp[0] | 1150 (uint64_t)ivp[1] << 8 | 1151 (uint64_t)ivp[4] << 16 | 1152 (uint64_t)ivp[5] << 24 | 1153 (uint64_t)ivp[6] << 32 | 1154 (uint64_t)ivp[7] << 40; 1155 if (pn <= *prsc) { 1156 ic->ic_stats.is_ccmp_replays++; 1157 return 1; 1158 } 1159 /* Last seen packet number is updated in ieee80211_inputm(). */ 1160 1161 /* Strip MIC. IV will be stripped by ieee80211_inputm(). */ 1162 m_adj(m, -IEEE80211_CCMP_MICLEN); 1163 return 0; 1164 } 1165 1166 void 1167 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, 1168 struct mbuf_list *ml) 1169 { 1170 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1171 struct ifnet *ifp = &ic->ic_if; 1172 struct ieee80211_rxinfo rxi; 1173 struct ieee80211_frame *wh; 1174 struct ieee80211_node *ni; 1175 struct r92c_rx_desc_usb *rxd; 1176 uint32_t rxdw0, rxdw3; 1177 struct mbuf *m; 1178 uint8_t rate; 1179 int8_t rssi = 0; 1180 int s, infosz; 1181 1182 rxd = (struct r92c_rx_desc_usb *)buf; 1183 rxdw0 = letoh32(rxd->rxdw0); 1184 rxdw3 = letoh32(rxd->rxdw3); 1185 1186 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1187 /* 1188 * This should not happen since we setup our Rx filter 1189 * to not receive these frames. 1190 */ 1191 ifp->if_ierrors++; 1192 return; 1193 } 1194 if (__predict_false(pktlen < sizeof(*wh) || pktlen > MCLBYTES)) { 1195 ifp->if_ierrors++; 1196 return; 1197 } 1198 1199 rate = (sc->sc_sc.chip & (RTWN_CHIP_88F | RTWN_CHIP_92E)) ? 1200 MS(rxdw3, R92E_RXDW3_RATE) : MS(rxdw3, R92C_RXDW3_RATE); 1201 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1202 1203 /* Get RSSI from PHY status descriptor if present. */ 1204 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1205 rssi = rtwn_get_rssi(&sc->sc_sc, rate, &rxd[1]); 1206 /* Update our average RSSI. */ 1207 rtwn_update_avgrssi(&sc->sc_sc, rate, rssi); 1208 } 1209 1210 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 1211 pktlen, rate, infosz, rssi)); 1212 1213 MGETHDR(m, M_DONTWAIT, MT_DATA); 1214 if (__predict_false(m == NULL)) { 1215 ifp->if_ierrors++; 1216 return; 1217 } 1218 if (pktlen > MHLEN) { 1219 MCLGET(m, M_DONTWAIT); 1220 if (__predict_false(!(m->m_flags & M_EXT))) { 1221 ifp->if_ierrors++; 1222 m_freem(m); 1223 return; 1224 } 1225 } 1226 /* Finalize mbuf. */ 1227 wh = (struct ieee80211_frame *)((uint8_t *)&rxd[1] + infosz); 1228 memcpy(mtod(m, uint8_t *), wh, pktlen); 1229 m->m_pkthdr.len = m->m_len = pktlen; 1230 1231 s = splnet(); 1232 #if NBPFILTER > 0 1233 if (__predict_false(sc->sc_drvbpf != NULL)) { 1234 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1235 struct mbuf mb; 1236 1237 tap->wr_flags = 0; 1238 /* Map HW rate index to 802.11 rate. */ 1239 if (!(rxdw3 & R92C_RXDW3_HT)) { 1240 switch (rate) { 1241 /* CCK. */ 1242 case 0: tap->wr_rate = 2; break; 1243 case 1: tap->wr_rate = 4; break; 1244 case 2: tap->wr_rate = 11; break; 1245 case 3: tap->wr_rate = 22; break; 1246 /* OFDM. */ 1247 case 4: tap->wr_rate = 12; break; 1248 case 5: tap->wr_rate = 18; break; 1249 case 6: tap->wr_rate = 24; break; 1250 case 7: tap->wr_rate = 36; break; 1251 case 8: tap->wr_rate = 48; break; 1252 case 9: tap->wr_rate = 72; break; 1253 case 10: tap->wr_rate = 96; break; 1254 case 11: tap->wr_rate = 108; break; 1255 } 1256 if (rate <= 3) 1257 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1258 } else if (rate >= 12) { /* MCS0~15. */ 1259 /* Bit 7 set means HT MCS instead of rate. */ 1260 tap->wr_rate = 0x80 | (rate - 12); 1261 } 1262 tap->wr_dbm_antsignal = rssi; 1263 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1264 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1265 1266 mb.m_data = (caddr_t)tap; 1267 mb.m_len = sc->sc_rxtap_len; 1268 mb.m_next = m; 1269 mb.m_nextpkt = NULL; 1270 mb.m_type = 0; 1271 mb.m_flags = 0; 1272 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1273 } 1274 #endif 1275 1276 ni = ieee80211_find_rxnode(ic, wh); 1277 memset(&rxi, 0, sizeof(rxi)); 1278 rxi.rxi_rssi = rssi; 1279 1280 /* Handle hardware decryption. */ 1281 if (((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) 1282 && (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && 1283 (ni->ni_flags & IEEE80211_NODE_RXPROT) && 1284 ((!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1285 ni->ni_pairwise_key.k_cipher == IEEE80211_CIPHER_CCMP) || 1286 (IEEE80211_IS_MULTICAST(wh->i_addr1) && 1287 ni->ni_rsngroupcipher == IEEE80211_CIPHER_CCMP))) { 1288 if (urtwn_ccmp_decap(sc, m, ni) != 0) { 1289 ifp->if_ierrors++; 1290 m_freem(m); 1291 ieee80211_release_node(ic, ni); 1292 splx(s); 1293 return; 1294 } 1295 rxi.rxi_flags |= IEEE80211_RXI_HWDEC; 1296 } 1297 1298 ieee80211_inputm(ifp, m, ni, &rxi, ml); 1299 /* Node is no longer needed. */ 1300 ieee80211_release_node(ic, ni); 1301 splx(s); 1302 } 1303 1304 void 1305 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, 1306 usbd_status status) 1307 { 1308 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1309 struct urtwn_rx_data *data = priv; 1310 struct urtwn_softc *sc = data->sc; 1311 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1312 struct r92c_rx_desc_usb *rxd; 1313 uint32_t rxdw0; 1314 uint8_t *buf; 1315 int len, totlen, pktlen, infosz, npkts, error, align; 1316 1317 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1318 DPRINTF(("RX status=%d\n", status)); 1319 if (status == USBD_STALLED) 1320 usbd_clear_endpoint_stall_async(sc->rx_pipe); 1321 if (status != USBD_CANCELLED) 1322 goto resubmit; 1323 return; 1324 } 1325 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 1326 1327 if (__predict_false(len < sizeof(*rxd))) { 1328 DPRINTF(("xfer too short %d\n", len)); 1329 goto resubmit; 1330 } 1331 buf = data->buf; 1332 1333 /* Get the number of encapsulated frames. */ 1334 rxd = (struct r92c_rx_desc_usb *)buf; 1335 npkts = MS(letoh32(rxd->rxdw2), R92C_RXDW2_PKTCNT); 1336 DPRINTFN(4, ("Rx %d frames in one chunk\n", npkts)); 1337 1338 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1339 int ntries, type; 1340 struct r88e_tx_rpt_ccx *rxstat; 1341 1342 type = MS(letoh32(rxd->rxdw3), R88E_RXDW3_RPT); 1343 1344 if (type == R88E_RXDW3_RPT_TX1) { 1345 buf += sizeof(struct r92c_rx_desc_usb); 1346 rxstat = (struct r88e_tx_rpt_ccx *)buf; 1347 ntries = MS(letoh32(rxstat->rptb2), 1348 R88E_RPTB2_RETRY_CNT); 1349 1350 if (rxstat->rptb1 & R88E_RPTB1_PKT_OK) 1351 sc->amn.amn_txcnt++; 1352 if (ntries > 0) 1353 sc->amn.amn_retrycnt++; 1354 1355 goto resubmit; 1356 } 1357 } else if (sc->sc_sc.chip & (RTWN_CHIP_88F | RTWN_CHIP_92E)) { 1358 int type; 1359 struct r92e_c2h_tx_rpt *txrpt; 1360 1361 if (letoh32(rxd->rxdw2) & R92E_RXDW2_RPT_C2H) { 1362 if (len < sizeof(struct r92c_rx_desc_usb) + 2) 1363 goto resubmit; 1364 1365 type = buf[sizeof(struct r92c_rx_desc_usb)]; 1366 switch (type) { 1367 case R92C_C2HEVT_TX_REPORT: 1368 buf += sizeof(struct r92c_rx_desc_usb) + 2; 1369 txrpt = (struct r92e_c2h_tx_rpt *)buf; 1370 if (MS(txrpt->rptb2, R92E_RPTB2_RETRY_CNT) > 0) 1371 sc->amn.amn_retrycnt++; 1372 if ((txrpt->rptb0 & (R92E_RPTB0_RETRY_OVER | 1373 R92E_RPTB0_LIFE_EXPIRE)) == 0) 1374 sc->amn.amn_txcnt++; 1375 break; 1376 default: 1377 break; 1378 } 1379 goto resubmit; 1380 } 1381 } 1382 1383 align = ((sc->sc_sc.chip & (RTWN_CHIP_88F | RTWN_CHIP_92E)) ? 7 : 127); 1384 1385 /* Process all of them. */ 1386 while (npkts-- > 0) { 1387 if (__predict_false(len < sizeof(*rxd))) 1388 break; 1389 rxd = (struct r92c_rx_desc_usb *)buf; 1390 rxdw0 = letoh32(rxd->rxdw0); 1391 1392 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1393 if (__predict_false(pktlen == 0)) 1394 break; 1395 1396 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1397 1398 /* Make sure everything fits in xfer. */ 1399 totlen = sizeof(*rxd) + infosz + pktlen; 1400 if (__predict_false(totlen > len)) 1401 break; 1402 1403 /* Process 802.11 frame. */ 1404 urtwn_rx_frame(sc, buf, pktlen, &ml); 1405 1406 /* Handle chunk alignment. */ 1407 totlen = (totlen + align) & ~align; 1408 buf += totlen; 1409 len -= totlen; 1410 } 1411 if_input(&ic->ic_if, &ml); 1412 1413 resubmit: 1414 /* Setup a new transfer. */ 1415 usbd_setup_xfer(xfer, sc->rx_pipe, data, data->buf, URTWN_RXBUFSZ, 1416 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, urtwn_rxeof); 1417 error = usbd_transfer(data->xfer); 1418 if (error != 0 && error != USBD_IN_PROGRESS) 1419 DPRINTF(("could not set up new transfer: %d\n", error)); 1420 } 1421 1422 void 1423 urtwn_txeof(struct usbd_xfer *xfer, void *priv, 1424 usbd_status status) 1425 { 1426 struct urtwn_tx_data *data = priv; 1427 struct urtwn_softc *sc = data->sc; 1428 struct ifnet *ifp = &sc->sc_sc.sc_ic.ic_if; 1429 int s; 1430 1431 s = splnet(); 1432 /* Put this Tx buffer back to our free list. */ 1433 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1434 1435 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1436 DPRINTF(("TX status=%d\n", status)); 1437 if (status == USBD_STALLED) 1438 usbd_clear_endpoint_stall_async(data->pipe); 1439 ifp->if_oerrors++; 1440 splx(s); 1441 return; 1442 } 1443 sc->sc_sc.sc_tx_timer = 0; 1444 1445 /* We just released a Tx buffer, notify Tx. */ 1446 if (ifq_is_oactive(&ifp->if_snd)) { 1447 ifq_clr_oactive(&ifp->if_snd); 1448 rtwn_start(ifp); 1449 } 1450 splx(s); 1451 } 1452 1453 void 1454 urtwn_tx_fill_desc(struct urtwn_softc *sc, uint8_t **txdp, struct mbuf *m, 1455 struct ieee80211_frame *wh, struct ieee80211_key *k, 1456 struct ieee80211_node *ni) 1457 { 1458 struct r92c_tx_desc_usb *txd; 1459 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1460 uint8_t raid, type, rtsrate; 1461 uint32_t pktlen; 1462 1463 txd = (struct r92c_tx_desc_usb *)*txdp; 1464 (*txdp) += sizeof(*txd); 1465 memset(txd, 0, sizeof(*txd)); 1466 1467 pktlen = m->m_pkthdr.len; 1468 if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) { 1469 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, 1470 R92C_TXDW1_CIPHER_AES)); 1471 pktlen += IEEE80211_CCMP_HDRLEN; 1472 } 1473 1474 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1475 1476 txd->txdw0 |= htole32( 1477 SM(R92C_TXDW0_PKTLEN, pktlen) | 1478 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1479 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1480 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1481 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1482 1483 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1484 type == IEEE80211_FC0_TYPE_DATA) { 1485 if (ic->ic_curmode == IEEE80211_MODE_11B || 1486 (sc->sc_sc.sc_flags & RTWN_FLAG_FORCE_RAID_11B)) 1487 raid = R92C_RAID_11B; 1488 else 1489 raid = R92C_RAID_11BG; 1490 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1491 txd->txdw1 |= htole32( 1492 SM(R88E_TXDW1_MACID, R92C_MACID_BSS) | 1493 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1494 SM(R92C_TXDW1_RAID, raid)); 1495 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1496 /* Request TX status report for AMRR */ 1497 txd->txdw2 |= htole32(R92C_TXDW2_CCX_RPT); 1498 } else { 1499 txd->txdw1 |= htole32( 1500 SM(R92C_TXDW1_MACID, R92C_MACID_BSS) | 1501 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1502 SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1503 } 1504 1505 if (pktlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 1506 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1507 R92C_TXDW4_HWRTSEN); 1508 } else if (ic->ic_flags & IEEE80211_F_USEPROT) { 1509 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1510 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1511 R92C_TXDW4_HWRTSEN); 1512 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1513 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1514 R92C_TXDW4_HWRTSEN); 1515 } 1516 } 1517 txd->txdw5 |= htole32(0x0001ff00); 1518 1519 if (ic->ic_curmode == IEEE80211_MODE_11B) 1520 rtsrate = 0; /* CCK1 */ 1521 else 1522 rtsrate = 8; /* OFDM24 */ 1523 1524 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1525 /* Use AMRR */ 1526 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1527 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, rtsrate)); 1528 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1529 ni->ni_txrate)); 1530 } else { 1531 /* Send data at OFDM54. */ 1532 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, rtsrate)); 1533 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1534 } 1535 } else { 1536 txd->txdw1 |= htole32( 1537 SM(R92C_TXDW1_MACID, 0) | 1538 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1539 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1540 1541 /* Force CCK1. */ 1542 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1543 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1544 } 1545 /* Set sequence number (already little endian). */ 1546 txd->txdseq |= (*(uint16_t *)wh->i_seq) >> IEEE80211_SEQ_SEQ_SHIFT; 1547 1548 if (!ieee80211_has_qos(wh)) { 1549 /* Use HW sequence numbering for non-QoS frames. */ 1550 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1551 txd->txdseq |= htole16(R92C_TXDW3_HWSEQEN); 1552 } else 1553 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1554 } 1555 1556 void 1557 urtwn_tx_fill_desc_gen2(struct urtwn_softc *sc, uint8_t **txdp, struct mbuf *m, 1558 struct ieee80211_frame *wh, struct ieee80211_key *k, 1559 struct ieee80211_node *ni) 1560 { 1561 struct r92e_tx_desc_usb *txd; 1562 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1563 uint8_t raid, type; 1564 uint32_t pktlen; 1565 1566 txd = (struct r92e_tx_desc_usb *)*txdp; 1567 (*txdp) += sizeof(*txd); 1568 memset(txd, 0, sizeof(*txd)); 1569 1570 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1571 1572 pktlen = m->m_pkthdr.len; 1573 if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) { 1574 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, 1575 R92C_TXDW1_CIPHER_AES)); 1576 pktlen += IEEE80211_CCMP_HDRLEN; 1577 } 1578 1579 txd->txdw0 |= htole32( 1580 SM(R92C_TXDW0_PKTLEN, pktlen) | 1581 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1582 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1583 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1584 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1585 1586 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1587 type == IEEE80211_FC0_TYPE_DATA) { 1588 if (ic->ic_curmode == IEEE80211_MODE_11B || 1589 (sc->sc_sc.sc_flags & RTWN_FLAG_FORCE_RAID_11B)) 1590 raid = R92E_RAID_11B; 1591 else 1592 raid = R92E_RAID_11BG; 1593 txd->txdw1 |= htole32( 1594 SM(R92E_TXDW1_MACID, R92C_MACID_BSS) | 1595 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1596 SM(R92C_TXDW1_RAID, raid)); 1597 /* Request TX status report for AMRR */ 1598 txd->txdw2 |= htole32(R92C_TXDW2_CCX_RPT | R88E_TXDW2_AGGBK); 1599 1600 if (pktlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 1601 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1602 R92C_TXDW4_HWRTSEN); 1603 } else if (ic->ic_flags & IEEE80211_F_USEPROT) { 1604 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1605 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1606 R92C_TXDW4_HWRTSEN); 1607 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1608 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1609 R92C_TXDW4_HWRTSEN); 1610 } 1611 } 1612 txd->txdw5 |= htole32(0x0001ff00); 1613 1614 /* Use AMRR */ 1615 txd->txdw3 |= htole32(R92E_TXDW3_DRVRATE); 1616 txd->txdw4 |= htole32(SM(R92E_TXDW4_RTSRATE, 8)); 1617 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATE, ni->ni_txrate)); 1618 } else { 1619 txd->txdw1 |= htole32( 1620 SM(R92E_TXDW1_MACID, 0) | 1621 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1622 SM(R92C_TXDW1_RAID, R92E_RAID_11B)); 1623 1624 /* Force CCK1. */ 1625 txd->txdw3 |= htole32(R92E_TXDW3_DRVRATE); 1626 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATE, 0)); 1627 } 1628 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATEFB, 0x1f)); 1629 1630 txd->txdseq2 |= htole16(SM(R92E_TXDSEQ2_HWSEQ, *(uint16_t *)wh->i_seq)); 1631 1632 if (!ieee80211_has_qos(wh)) { 1633 /* Use HW sequence numbering for non-QoS frames. */ 1634 txd->txdw7 |= htole16(R92C_TXDW3_HWSEQEN); 1635 } 1636 } 1637 1638 int 1639 urtwn_tx(void *cookie, struct mbuf *m, struct ieee80211_node *ni) 1640 { 1641 struct urtwn_softc *sc = cookie; 1642 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1643 struct ieee80211_frame *wh; 1644 struct ieee80211_key *k = NULL; 1645 struct urtwn_tx_data *data; 1646 struct usbd_pipe *pipe; 1647 uint16_t qos, sum; 1648 uint8_t tid, qid; 1649 int i, xferlen, error, headerlen; 1650 uint8_t *txdp; 1651 1652 wh = mtod(m, struct ieee80211_frame *); 1653 1654 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1655 k = ieee80211_get_txkey(ic, wh, ni); 1656 if (k->k_cipher != IEEE80211_CIPHER_CCMP) { 1657 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1658 return (ENOBUFS); 1659 wh = mtod(m, struct ieee80211_frame *); 1660 } 1661 } 1662 1663 if (ieee80211_has_qos(wh)) { 1664 qos = ieee80211_get_qos(wh); 1665 tid = qos & IEEE80211_QOS_TID; 1666 qid = ieee80211_up_to_ac(ic, tid); 1667 } else if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) 1668 != IEEE80211_FC0_TYPE_DATA) { 1669 /* Use AC VO for management frames. */ 1670 qid = EDCA_AC_VO; 1671 } else 1672 qid = EDCA_AC_BE; 1673 1674 /* Get the USB pipe to use for this AC. */ 1675 pipe = sc->tx_pipe[sc->ac2idx[qid]]; 1676 1677 /* Grab a Tx buffer from our free list. */ 1678 data = TAILQ_FIRST(&sc->tx_free_list); 1679 TAILQ_REMOVE(&sc->tx_free_list, data, next); 1680 1681 /* Fill Tx descriptor. */ 1682 txdp = data->buf; 1683 if (sc->sc_sc.chip & (RTWN_CHIP_88F | RTWN_CHIP_92E)) 1684 urtwn_tx_fill_desc_gen2(sc, &txdp, m, wh, k, ni); 1685 else 1686 urtwn_tx_fill_desc(sc, &txdp, m, wh, k, ni); 1687 1688 /* Compute Tx descriptor checksum. */ 1689 sum = 0; 1690 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 1691 sum ^= ((uint16_t *)data->buf)[i]; 1692 ((uint16_t *)data->buf)[R92C_TXDESC_SUMOFFSET] = sum; 1693 1694 #if NBPFILTER > 0 1695 if (__predict_false(sc->sc_drvbpf != NULL)) { 1696 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1697 struct mbuf mb; 1698 1699 tap->wt_flags = 0; 1700 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1701 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1702 1703 mb.m_data = (caddr_t)tap; 1704 mb.m_len = sc->sc_txtap_len; 1705 mb.m_next = m; 1706 mb.m_nextpkt = NULL; 1707 mb.m_type = 0; 1708 mb.m_flags = 0; 1709 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1710 } 1711 #endif 1712 1713 if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) { 1714 xferlen = (txdp - data->buf) + m->m_pkthdr.len + 1715 IEEE80211_CCMP_HDRLEN; 1716 headerlen = ieee80211_get_hdrlen(wh); 1717 1718 m_copydata(m, 0, headerlen, txdp); 1719 txdp += headerlen; 1720 1721 k->k_tsc++; 1722 txdp[0] = k->k_tsc; 1723 txdp[1] = k->k_tsc >> 8; 1724 txdp[2] = 0; 1725 txdp[3] = k->k_id | IEEE80211_WEP_EXTIV; 1726 txdp[4] = k->k_tsc >> 16; 1727 txdp[5] = k->k_tsc >> 24; 1728 txdp[6] = k->k_tsc >> 32; 1729 txdp[7] = k->k_tsc >> 40; 1730 txdp += IEEE80211_CCMP_HDRLEN; 1731 1732 m_copydata(m, headerlen, m->m_pkthdr.len - headerlen, txdp); 1733 m_freem(m); 1734 } else { 1735 xferlen = (txdp - data->buf) + m->m_pkthdr.len; 1736 m_copydata(m, 0, m->m_pkthdr.len, txdp); 1737 m_freem(m); 1738 } 1739 1740 data->pipe = pipe; 1741 usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen, 1742 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTWN_TX_TIMEOUT, 1743 urtwn_txeof); 1744 error = usbd_transfer(data->xfer); 1745 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) { 1746 /* Put this Tx buffer back to our free list. */ 1747 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1748 return (error); 1749 } 1750 ieee80211_release_node(ic, ni); 1751 return (0); 1752 } 1753 1754 int 1755 urtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1756 { 1757 struct rtwn_softc *sc_sc = ifp->if_softc; 1758 struct device *self = sc_sc->sc_pdev; 1759 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1760 int error; 1761 1762 if (usbd_is_dying(sc->sc_udev)) 1763 return ENXIO; 1764 1765 usbd_ref_incr(sc->sc_udev); 1766 error = rtwn_ioctl(ifp, cmd, data); 1767 usbd_ref_decr(sc->sc_udev); 1768 1769 return (error); 1770 } 1771 1772 int 1773 urtwn_r92c_power_on(struct urtwn_softc *sc) 1774 { 1775 uint32_t reg; 1776 int ntries; 1777 1778 /* Wait for autoload done bit. */ 1779 for (ntries = 0; ntries < 1000; ntries++) { 1780 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 1781 break; 1782 DELAY(5); 1783 } 1784 if (ntries == 1000) { 1785 printf("%s: timeout waiting for chip autoload\n", 1786 sc->sc_dev.dv_xname); 1787 return (ETIMEDOUT); 1788 } 1789 1790 /* Unlock ISO/CLK/Power control register. */ 1791 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 1792 /* Move SPS into PWM mode. */ 1793 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 1794 DELAY(100); 1795 1796 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 1797 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 1798 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 1799 reg | R92C_LDOV12D_CTRL_LDV12_EN); 1800 DELAY(100); 1801 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 1802 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 1803 ~R92C_SYS_ISO_CTRL_MD2PP); 1804 } 1805 1806 /* Auto enable WLAN. */ 1807 urtwn_write_2(sc, R92C_APS_FSMCO, 1808 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1809 for (ntries = 0; ntries < 1000; ntries++) { 1810 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1811 R92C_APS_FSMCO_APFM_ONMAC)) 1812 break; 1813 DELAY(5); 1814 } 1815 if (ntries == 1000) { 1816 printf("%s: timeout waiting for MAC auto ON\n", 1817 sc->sc_dev.dv_xname); 1818 return (ETIMEDOUT); 1819 } 1820 1821 /* Enable radio, GPIO and LED functions. */ 1822 urtwn_write_2(sc, R92C_APS_FSMCO, 1823 R92C_APS_FSMCO_AFSM_HSUS | 1824 R92C_APS_FSMCO_PDN_EN | 1825 R92C_APS_FSMCO_PFM_ALDN); 1826 /* Release RF digital isolation. */ 1827 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1828 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 1829 1830 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1831 reg = urtwn_read_2(sc, R92C_CR); 1832 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1833 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1834 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 1835 R92C_CR_ENSEC; 1836 urtwn_write_2(sc, R92C_CR, reg); 1837 1838 urtwn_write_1(sc, 0xfe10, 0x19); 1839 return (0); 1840 } 1841 1842 int 1843 urtwn_r92e_power_on(struct urtwn_softc *sc) 1844 { 1845 uint32_t reg; 1846 int ntries; 1847 1848 if (urtwn_read_4(sc, R92C_SYS_CFG) & R92E_SYS_CFG_SPSLDO_SEL) { 1849 /* LDO. */ 1850 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 1851 } else { 1852 reg = urtwn_read_4(sc, R92C_SYS_SWR_CTRL2); 1853 reg &= 0xff0fffff; 1854 reg |= 0x00500000; 1855 urtwn_write_4(sc, R92C_SYS_SWR_CTRL2, reg); 1856 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 1857 } 1858 1859 /* 40MHz crystal source */ 1860 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 1861 urtwn_read_1(sc, R92C_AFE_PLL_CTRL) & 0xfb); 1862 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL_EXT, 1863 urtwn_read_4(sc, R92C_AFE_XTAL_CTRL_EXT) & 0xfffffc7f); 1864 1865 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 1866 urtwn_read_1(sc, R92C_AFE_PLL_CTRL) & 0xbf); 1867 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL_EXT, 1868 urtwn_read_4(sc, R92C_AFE_XTAL_CTRL_EXT) & 0xffdfffff); 1869 1870 /* Disable HWPDN. */ 1871 urtwn_write_2(sc, R92C_APS_FSMCO, 1872 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 1873 for (ntries = 0; ntries < 5000; ntries++) { 1874 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 1875 break; 1876 DELAY(10); 1877 } 1878 if (ntries == 5000) { 1879 printf("%s: timeout waiting for chip power up\n", 1880 sc->sc_dev.dv_xname); 1881 return (ETIMEDOUT); 1882 } 1883 1884 /* Disable WL suspend. */ 1885 urtwn_write_2(sc, R92C_APS_FSMCO, 1886 urtwn_read_2(sc, R92C_APS_FSMCO) & 1887 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 1888 1889 /* Auto enable WLAN. */ 1890 urtwn_write_4(sc, R92C_APS_FSMCO, 1891 urtwn_read_4(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 1892 urtwn_write_2(sc, R92C_APS_FSMCO, 1893 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1894 for (ntries = 0; ntries < 5000; ntries++) { 1895 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1896 R92C_APS_FSMCO_APFM_ONMAC)) 1897 break; 1898 DELAY(10); 1899 } 1900 if (ntries == 5000) { 1901 printf("%s: timeout waiting for MAC auto ON\n", 1902 sc->sc_dev.dv_xname); 1903 return (ETIMEDOUT); 1904 } 1905 1906 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1907 urtwn_write_2(sc, R92C_CR, 0); 1908 reg = urtwn_read_2(sc, R92C_CR); 1909 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1910 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1911 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 1912 urtwn_write_2(sc, R92C_CR, reg); 1913 return (0); 1914 } 1915 1916 int 1917 urtwn_r88e_power_on(struct urtwn_softc *sc) 1918 { 1919 uint32_t reg; 1920 int ntries; 1921 1922 /* Wait for power ready bit. */ 1923 for (ntries = 0; ntries < 5000; ntries++) { 1924 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 1925 break; 1926 DELAY(10); 1927 } 1928 if (ntries == 5000) { 1929 printf("%s: timeout waiting for chip power up\n", 1930 sc->sc_dev.dv_xname); 1931 return (ETIMEDOUT); 1932 } 1933 1934 /* Reset BB. */ 1935 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 1936 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 1937 R92C_SYS_FUNC_EN_BB_GLB_RST)); 1938 1939 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 1940 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 1941 1942 /* Disable HWPDN. */ 1943 urtwn_write_2(sc, R92C_APS_FSMCO, 1944 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 1945 /* Disable WL suspend. */ 1946 urtwn_write_2(sc, R92C_APS_FSMCO, 1947 urtwn_read_2(sc, R92C_APS_FSMCO) & 1948 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 1949 1950 /* Auto enable WLAN. */ 1951 urtwn_write_2(sc, R92C_APS_FSMCO, 1952 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1953 for (ntries = 0; ntries < 5000; ntries++) { 1954 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1955 R92C_APS_FSMCO_APFM_ONMAC)) 1956 break; 1957 DELAY(10); 1958 } 1959 if (ntries == 5000) { 1960 printf("%s: timeout waiting for MAC auto ON\n", 1961 sc->sc_dev.dv_xname); 1962 return (ETIMEDOUT); 1963 } 1964 1965 /* Enable LDO normal mode. */ 1966 urtwn_write_1(sc, R92C_LPLDO_CTRL, 1967 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 1968 1969 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1970 urtwn_write_2(sc, R92C_CR, 0); 1971 reg = urtwn_read_2(sc, R92C_CR); 1972 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1973 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1974 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 1975 urtwn_write_2(sc, R92C_CR, reg); 1976 return (0); 1977 } 1978 1979 int 1980 urtwn_r88f_power_on(struct urtwn_softc *sc) 1981 { 1982 uint32_t reg; 1983 int ntries; 1984 1985 /* Enable WL suspend. */ 1986 urtwn_write_2(sc, R92C_APS_FSMCO, 1987 urtwn_read_2(sc, R92C_APS_FSMCO) & 1988 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 1989 /* Turn off USB APHY LDO under suspend mode. */ 1990 urtwn_write_1(sc, 0xc4, urtwn_read_1(sc, 0xc4) & ~0x10); 1991 1992 /* Disable SW LPS. */ 1993 urtwn_write_2(sc, R92C_APS_FSMCO, 1994 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APFM_RSM); 1995 /* Wait for power ready bit. */ 1996 for (ntries = 0; ntries < 5000; ntries++) { 1997 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 1998 break; 1999 DELAY(10); 2000 } 2001 if (ntries == 5000) { 2002 printf("%s: timeout waiting for chip power up\n", 2003 sc->sc_dev.dv_xname); 2004 return (ETIMEDOUT); 2005 } 2006 /* Disable HWPDN. */ 2007 urtwn_write_2(sc, R92C_APS_FSMCO, 2008 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 2009 /* Disable WL suspend. */ 2010 urtwn_write_2(sc, R92C_APS_FSMCO, 2011 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_AFSM_HSUS); 2012 /* Auto enable WLAN. */ 2013 urtwn_write_2(sc, R92C_APS_FSMCO, 2014 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2015 for (ntries = 0; ntries < 5000; ntries++) { 2016 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2017 R92C_APS_FSMCO_APFM_ONMAC)) 2018 break; 2019 DELAY(10); 2020 } 2021 if (ntries == 5000) { 2022 printf("%s: timeout waiting for MAC auto ON\n", 2023 sc->sc_dev.dv_xname); 2024 return (ETIMEDOUT); 2025 } 2026 /* Reduce RF noise. */ 2027 urtwn_write_1(sc, R92C_AFE_LDO_CTRL, 0x35); 2028 2029 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2030 urtwn_write_2(sc, R92C_CR, 0); 2031 reg = urtwn_read_2(sc, R92C_CR); 2032 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2033 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2034 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2035 urtwn_write_2(sc, R92C_CR, reg); 2036 return (0); 2037 } 2038 2039 int 2040 urtwn_llt_init(struct urtwn_softc *sc, int page_count) 2041 { 2042 int i, error, pktbuf_count; 2043 2044 pktbuf_count = (sc->sc_sc.chip & RTWN_CHIP_88E) ? 2045 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2046 2047 /* Reserve pages [0; page_count]. */ 2048 for (i = 0; i < page_count; i++) { 2049 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2050 return (error); 2051 } 2052 /* NB: 0xff indicates end-of-list. */ 2053 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2054 return (error); 2055 /* 2056 * Use pages [page_count + 1; pktbuf_count - 1] 2057 * as ring buffer. 2058 */ 2059 for (++i; i < pktbuf_count - 1; i++) { 2060 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2061 return (error); 2062 } 2063 /* Make the last page point to the beginning of the ring buffer. */ 2064 error = urtwn_llt_write(sc, i, page_count + 1); 2065 return (error); 2066 } 2067 2068 int 2069 urtwn_auto_llt_init(struct urtwn_softc *sc) 2070 { 2071 int ntries; 2072 2073 urtwn_write_4(sc, R92E_AUTO_LLT, 2074 urtwn_read_4(sc, R92E_AUTO_LLT) | R92E_AUTO_LLT_EN); 2075 for (ntries = 0; ntries < 1000; ntries++) { 2076 if (!(urtwn_read_4(sc, R92E_AUTO_LLT) & R92E_AUTO_LLT_EN)) 2077 return (0); 2078 DELAY(2); 2079 } 2080 2081 return (ETIMEDOUT); 2082 } 2083 2084 int 2085 urtwn_fw_loadpage(void *cookie, int page, uint8_t *buf, int len) 2086 { 2087 struct urtwn_softc *sc = cookie; 2088 uint32_t reg; 2089 int maxblksz, off, mlen, error = 0; 2090 2091 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2092 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2093 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2094 2095 maxblksz = (sc->sc_sc.chip & RTWN_CHIP_92E) ? 254 : 196; 2096 2097 off = R92C_FW_START_ADDR; 2098 while (len > 0) { 2099 if (len > maxblksz) 2100 mlen = maxblksz; 2101 else if (len > 4) 2102 mlen = 4; 2103 else 2104 mlen = 1; 2105 error = urtwn_write_region_1(sc, off, buf, mlen); 2106 if (error != 0) 2107 break; 2108 off += mlen; 2109 buf += mlen; 2110 len -= mlen; 2111 } 2112 return (error); 2113 } 2114 2115 int 2116 urtwn_load_firmware(void *cookie, u_char **fw, size_t *len) 2117 { 2118 struct urtwn_softc *sc = cookie; 2119 const char *name; 2120 int error; 2121 2122 if (sc->sc_sc.chip & RTWN_CHIP_92E) 2123 name = "urtwn-rtl8192eu"; 2124 else if (sc->sc_sc.chip & RTWN_CHIP_88E) 2125 name = "urtwn-rtl8188eu"; 2126 else if (sc->sc_sc.chip & RTWN_CHIP_88F) 2127 name = "urtwn-rtl8188ftv"; 2128 else if ((sc->sc_sc.chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2129 RTWN_CHIP_UMC_A_CUT) 2130 name = "urtwn-rtl8192cU"; 2131 else 2132 name = "urtwn-rtl8192cT"; 2133 2134 error = loadfirmware(name, fw, len); 2135 if (error) 2136 printf("%s: could not read firmware %s (error %d)\n", 2137 sc->sc_dev.dv_xname, name, error); 2138 return (error); 2139 } 2140 2141 int 2142 urtwn_dma_init(void *cookie) 2143 { 2144 struct urtwn_softc *sc = cookie; 2145 uint32_t reg; 2146 uint16_t dmasize; 2147 int hqpages, lqpages, nqpages, pagecnt, boundary; 2148 int error, hashq, haslq, hasnq; 2149 2150 /* Default initialization of chipset values. */ 2151 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2152 hqpages = R88E_HQ_NPAGES; 2153 lqpages = R88E_LQ_NPAGES; 2154 nqpages = R88E_NQ_NPAGES; 2155 pagecnt = R88E_TX_PAGE_COUNT; 2156 dmasize = R88E_MAX_RX_DMA_SIZE; 2157 } else if (sc->sc_sc.chip & RTWN_CHIP_88F) { 2158 hqpages = R88F_HQ_NPAGES; 2159 lqpages = R88F_LQ_NPAGES; 2160 nqpages = R88F_NQ_NPAGES; 2161 pagecnt = R88F_TX_PAGE_COUNT; 2162 dmasize = R88F_MAX_RX_DMA_SIZE; 2163 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2164 hqpages = R92E_HQ_NPAGES; 2165 lqpages = R92E_LQ_NPAGES; 2166 nqpages = R92E_NQ_NPAGES; 2167 pagecnt = R92E_TX_PAGE_COUNT; 2168 dmasize = R92E_MAX_RX_DMA_SIZE; 2169 } else { 2170 hqpages = R92C_HQ_NPAGES; 2171 lqpages = R92C_LQ_NPAGES; 2172 nqpages = R92C_NQ_NPAGES; 2173 pagecnt = R92C_TX_PAGE_COUNT; 2174 dmasize = R92C_MAX_RX_DMA_SIZE; 2175 } 2176 boundary = pagecnt + 1; 2177 2178 /* Initialize LLT table. */ 2179 if (sc->sc_sc.chip & (RTWN_CHIP_88F | RTWN_CHIP_92E)) 2180 error = urtwn_auto_llt_init(sc); 2181 else 2182 error = urtwn_llt_init(sc, pagecnt); 2183 if (error != 0) 2184 return (error); 2185 2186 /* Get Tx queues to USB endpoints mapping. */ 2187 hashq = hasnq = haslq = 0; 2188 switch (sc->ntx) { 2189 case 3: 2190 haslq = 1; 2191 pagecnt -= lqpages; 2192 /* FALLTHROUGH */ 2193 case 2: 2194 hasnq = 1; 2195 pagecnt -= nqpages; 2196 /* FALLTHROUGH */ 2197 case 1: 2198 hashq = 1; 2199 pagecnt -= hqpages; 2200 break; 2201 } 2202 2203 /* Set number of pages for normal priority queue. */ 2204 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2205 urtwn_write_4(sc, R92C_RQPN, 2206 /* Set number of pages for public queue. */ 2207 SM(R92C_RQPN_PUBQ, pagecnt) | 2208 /* Set number of pages for high priority queue. */ 2209 SM(R92C_RQPN_HPQ, hashq ? hqpages : 0) | 2210 /* Set number of pages for low priority queue. */ 2211 SM(R92C_RQPN_LPQ, haslq ? lqpages : 0) | 2212 /* Load values. */ 2213 R92C_RQPN_LD); 2214 2215 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, boundary); 2216 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, boundary); 2217 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, boundary); 2218 urtwn_write_1(sc, R92C_TRXFF_BNDY, boundary); 2219 urtwn_write_1(sc, R92C_TDECTRL + 1, boundary); 2220 2221 /* Set queue to USB pipe mapping. */ 2222 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2223 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2224 if (haslq) 2225 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2226 else if (hashq) { 2227 if (!hasnq) 2228 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2229 else 2230 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2231 } 2232 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2233 2234 /* Set Tx/Rx transfer page boundary. */ 2235 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, dmasize - 1); 2236 2237 if (!(sc->sc_sc.chip & RTWN_CHIP_92E)) { 2238 /* Set Tx/Rx transfer page size. */ 2239 if (sc->sc_sc.chip & RTWN_CHIP_88F) { 2240 urtwn_write_1(sc, R92C_PBP, 2241 SM(R92C_PBP_PSRX, R92C_PBP_256) | 2242 SM(R92C_PBP_PSTX, R92C_PBP_256)); 2243 } else { 2244 urtwn_write_1(sc, R92C_PBP, 2245 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2246 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2247 } 2248 } 2249 return (error); 2250 } 2251 2252 void 2253 urtwn_aggr_init(void *cookie) 2254 { 2255 struct urtwn_softc *sc = cookie; 2256 uint32_t reg = 0; 2257 int dmasize, dmatiming, ndesc; 2258 2259 /* Set burst packet length. */ 2260 if (sc->sc_sc.chip & (RTWN_CHIP_88F | RTWN_CHIP_92E)) 2261 urtwn_burstlen_init(sc); 2262 2263 if (sc->sc_sc.chip & RTWN_CHIP_88F) { 2264 dmasize = 5; 2265 dmatiming = 32; 2266 ndesc = 6; 2267 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2268 dmasize = 6; 2269 dmatiming = 32; 2270 ndesc = 3; 2271 } else { 2272 dmasize = 48; 2273 dmatiming = 4; 2274 ndesc = (sc->sc_sc.chip & RTWN_CHIP_88E) ? 1 : 6; 2275 } 2276 2277 /* Tx aggregation setting. */ 2278 reg = urtwn_read_4(sc, R92C_TDECTRL); 2279 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, ndesc); 2280 urtwn_write_4(sc, R92C_TDECTRL, reg); 2281 if (sc->sc_sc.chip & (RTWN_CHIP_88F | RTWN_CHIP_92E)) 2282 urtwn_write_1(sc, R92E_DWBCN1_CTRL, ndesc << 1); 2283 2284 /* Rx aggregation setting. */ 2285 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 2286 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 2287 2288 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, dmasize); 2289 if (sc->sc_sc.chip & (RTWN_CHIP_92C | RTWN_CHIP_88C)) 2290 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, dmatiming); 2291 else 2292 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, dmatiming); 2293 2294 if (sc->sc_sc.chip & RTWN_CHIP_88F) { 2295 urtwn_write_1(sc, R92E_RXDMA_PRO, 2296 urtwn_read_1(sc, R92E_RXDMA_PRO) | R92E_RXDMA_PRO_DMA_MODE); 2297 } 2298 2299 /* Drop incorrect bulk out. */ 2300 urtwn_write_4(sc, R92C_TXDMA_OFFSET_CHK, 2301 urtwn_read_4(sc, R92C_TXDMA_OFFSET_CHK) | 2302 R92C_TXDMA_OFFSET_CHK_DROP_DATA_EN); 2303 } 2304 2305 void 2306 urtwn_mac_init(void *cookie) 2307 { 2308 struct urtwn_softc *sc = cookie; 2309 int i; 2310 2311 /* Write MAC initialization values. */ 2312 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2313 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2314 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2315 rtl8188eu_mac[i].val); 2316 } 2317 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2318 } else if (sc->sc_sc.chip & RTWN_CHIP_88F) { 2319 for (i = 0; i < nitems(rtl8188ftv_mac); i++) { 2320 urtwn_write_1(sc, rtl8188ftv_mac[i].reg, 2321 rtl8188ftv_mac[i].val); 2322 } 2323 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2324 for (i = 0; i < nitems(rtl8192eu_mac); i++) { 2325 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 2326 rtl8192eu_mac[i].val); 2327 } 2328 } else { 2329 for (i = 0; i < nitems(rtl8192cu_mac); i++) 2330 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2331 rtl8192cu_mac[i].val); 2332 } 2333 } 2334 2335 void 2336 urtwn_bb_init(void *cookie) 2337 { 2338 struct urtwn_softc *sc = cookie; 2339 const struct r92c_bb_prog *prog; 2340 uint32_t reg; 2341 uint8_t xtal; 2342 int i; 2343 2344 /* Enable BB and RF. */ 2345 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2346 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2347 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2348 R92C_SYS_FUNC_EN_DIO_RF); 2349 2350 if (!(sc->sc_sc.chip & (RTWN_CHIP_88E | RTWN_CHIP_88F | RTWN_CHIP_92E))) 2351 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2352 2353 urtwn_write_1(sc, R92C_RF_CTRL, 2354 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2355 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2356 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2357 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2358 2359 if (!(sc->sc_sc.chip & 2360 (RTWN_CHIP_88E | RTWN_CHIP_88F | RTWN_CHIP_92E))) { 2361 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2362 urtwn_write_1(sc, 0x15, 0xe9); 2363 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2364 } 2365 2366 /* Select BB programming based on board type. */ 2367 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2368 prog = &rtl8188eu_bb_prog; 2369 else if (sc->sc_sc.chip & RTWN_CHIP_88F) 2370 prog = &rtl8188ftv_bb_prog; 2371 else if (sc->sc_sc.chip & RTWN_CHIP_92E) 2372 prog = &rtl8192eu_bb_prog; 2373 else if (!(sc->sc_sc.chip & RTWN_CHIP_92C)) { 2374 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD) 2375 prog = &rtl8188ce_bb_prog; 2376 else if (sc->sc_sc.board_type == R92C_BOARD_TYPE_HIGHPA) 2377 prog = &rtl8188ru_bb_prog; 2378 else 2379 prog = &rtl8188cu_bb_prog; 2380 } else { 2381 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD) 2382 prog = &rtl8192ce_bb_prog; 2383 else 2384 prog = &rtl8192cu_bb_prog; 2385 } 2386 /* Write BB initialization values. */ 2387 for (i = 0; i < prog->count; i++) { 2388 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2389 DELAY(1); 2390 } 2391 2392 if (sc->sc_sc.chip & RTWN_CHIP_92C_1T2R) { 2393 /* 8192C 1T only configuration. */ 2394 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2395 reg = (reg & ~0x00000003) | 0x2; 2396 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2397 2398 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2399 reg = (reg & ~0x00300033) | 0x00200022; 2400 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2401 2402 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2403 reg = (reg & ~0xff000000) | 0x45 << 24; 2404 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2405 2406 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2407 reg = (reg & ~0x000000ff) | 0x23; 2408 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2409 2410 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2411 reg = (reg & ~0x00000030) | 1 << 4; 2412 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2413 2414 reg = urtwn_bb_read(sc, 0xe74); 2415 reg = (reg & ~0x0c000000) | 2 << 26; 2416 urtwn_bb_write(sc, 0xe74, reg); 2417 reg = urtwn_bb_read(sc, 0xe78); 2418 reg = (reg & ~0x0c000000) | 2 << 26; 2419 urtwn_bb_write(sc, 0xe78, reg); 2420 reg = urtwn_bb_read(sc, 0xe7c); 2421 reg = (reg & ~0x0c000000) | 2 << 26; 2422 urtwn_bb_write(sc, 0xe7c, reg); 2423 reg = urtwn_bb_read(sc, 0xe80); 2424 reg = (reg & ~0x0c000000) | 2 << 26; 2425 urtwn_bb_write(sc, 0xe80, reg); 2426 reg = urtwn_bb_read(sc, 0xe88); 2427 reg = (reg & ~0x0c000000) | 2 << 26; 2428 urtwn_bb_write(sc, 0xe88, reg); 2429 } 2430 2431 /* Write AGC values. */ 2432 for (i = 0; i < prog->agccount; i++) { 2433 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2434 prog->agcvals[i]); 2435 DELAY(1); 2436 } 2437 2438 if (sc->sc_sc.chip & (RTWN_CHIP_88E | RTWN_CHIP_88F)) { 2439 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2440 DELAY(1); 2441 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2442 DELAY(1); 2443 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2444 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040022); 2445 DELAY(1); 2446 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040020); 2447 DELAY(1); 2448 } 2449 2450 if (sc->sc_sc.chip & (RTWN_CHIP_88E | RTWN_CHIP_88F)) { 2451 xtal = sc->sc_sc.crystal_cap & 0x3f; 2452 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2453 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2454 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, xtal | xtal << 6)); 2455 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2456 xtal = sc->sc_sc.crystal_cap & 0x3f; 2457 reg = urtwn_bb_read(sc, R92C_AFE_CTRL3); 2458 urtwn_bb_write(sc, R92C_AFE_CTRL3, 2459 RW(reg, R92C_AFE_CTRL3_ADDR, xtal | xtal << 6)); 2460 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0x000f81fb); 2461 } 2462 2463 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & R92C_HSSI_PARAM2_CCK_HIPWR) 2464 sc->sc_sc.sc_flags |= RTWN_FLAG_CCK_HIPWR; 2465 } 2466 2467 void 2468 urtwn_burstlen_init(struct urtwn_softc *sc) 2469 { 2470 uint8_t reg; 2471 2472 reg = urtwn_read_1(sc, R92E_RXDMA_PRO); 2473 reg &= ~0x30; 2474 switch (sc->sc_udev->speed) { 2475 case USB_SPEED_HIGH: 2476 urtwn_write_1(sc, R92E_RXDMA_PRO, reg | 0x1e); 2477 break; 2478 default: 2479 urtwn_write_1(sc, R92E_RXDMA_PRO, reg | 0x2e); 2480 break; 2481 } 2482 2483 if (sc->sc_sc.chip & RTWN_CHIP_88F) { 2484 /* Setup AMPDU aggregation. */ 2485 urtwn_write_1(sc, R88F_HT_SINGLE_AMPDU, 2486 urtwn_read_1(sc, R88F_HT_SINGLE_AMPDU) | 2487 R88F_HT_SINGLE_AMPDU_EN); 2488 urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0c14); 2489 urtwn_write_1(sc, R88F_AMPDU_MAX_TIME, 0x70); 2490 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0xffffffff); 2491 2492 /* For VHT packet length 11K */ 2493 urtwn_write_1(sc, R88F_RX_PKT_LIMIT, 0x18); 2494 2495 urtwn_write_1(sc, R92C_PIFS, 0); 2496 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 0x80); 2497 urtwn_write_4(sc, R92C_FAST_EDCA_CTRL, 0x03086666); 2498 urtwn_write_1(sc, R92C_USTIME_TSF, 0x28); 2499 urtwn_write_1(sc, R88F_USTIME_EDCA, 0x28); 2500 2501 /* To prevent mac is reseted by bus. */ 2502 urtwn_write_1(sc, R92C_RSV_CTRL, 2503 urtwn_read_1(sc, R92C_RSV_CTRL) | 2504 R92C_RSV_CTRL_R_DIS_PRST_0 | R92C_RSV_CTRL_R_DIS_PRST_1); 2505 } 2506 } 2507 2508 int 2509 urtwn_power_on(void *cookie) 2510 { 2511 struct urtwn_softc *sc = cookie; 2512 2513 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2514 return (urtwn_r88e_power_on(sc)); 2515 else if (sc->sc_sc.chip & RTWN_CHIP_88F) 2516 return (urtwn_r88f_power_on(sc)); 2517 else if (sc->sc_sc.chip & RTWN_CHIP_92E) 2518 return (urtwn_r92e_power_on(sc)); 2519 2520 return (urtwn_r92c_power_on(sc)); 2521 } 2522 2523 int 2524 urtwn_alloc_buffers(void *cookie) 2525 { 2526 struct urtwn_softc *sc = cookie; 2527 int error; 2528 2529 /* Init host async commands ring. */ 2530 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 2531 2532 /* Allocate Tx/Rx buffers. */ 2533 error = urtwn_alloc_rx_list(sc); 2534 if (error != 0) { 2535 printf("%s: could not allocate Rx buffers\n", 2536 sc->sc_dev.dv_xname); 2537 return (error); 2538 } 2539 error = urtwn_alloc_tx_list(sc); 2540 if (error != 0) { 2541 printf("%s: could not allocate Tx buffers\n", 2542 sc->sc_dev.dv_xname); 2543 return (error); 2544 } 2545 2546 return (0); 2547 } 2548 2549 int 2550 urtwn_init(void *cookie) 2551 { 2552 struct urtwn_softc *sc = cookie; 2553 int i, error; 2554 2555 /* Reset USB mode switch setting. */ 2556 if (sc->sc_sc.chip & RTWN_CHIP_92E) 2557 urtwn_write_1(sc, R92C_ACLK_MON, 0); 2558 2559 /* Queue Rx xfers. */ 2560 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 2561 struct urtwn_rx_data *data = &sc->rx_data[i]; 2562 2563 usbd_setup_xfer(data->xfer, sc->rx_pipe, data, data->buf, 2564 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 2565 USBD_NO_TIMEOUT, urtwn_rxeof); 2566 error = usbd_transfer(data->xfer); 2567 if (error != 0 && error != USBD_IN_PROGRESS) 2568 return (error); 2569 } 2570 2571 ieee80211_amrr_node_init(&sc->amrr, &sc->amn); 2572 2573 /* 2574 * Enable TX reports for AMRR. 2575 * In order to get reports we need to explicitly reset the register. 2576 */ 2577 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2578 urtwn_write_1(sc, R88E_TX_RPT_CTRL, (urtwn_read_1(sc, 2579 R88E_TX_RPT_CTRL) & ~0) | R88E_TX_RPT_CTRL_EN); 2580 2581 return (0); 2582 } 2583 2584 void 2585 urtwn_stop(void *cookie) 2586 { 2587 struct urtwn_softc *sc = cookie; 2588 int i; 2589 2590 /* Abort Tx. */ 2591 for (i = 0; i < R92C_MAX_EPOUT; i++) { 2592 if (sc->tx_pipe[i] != NULL) 2593 usbd_abort_pipe(sc->tx_pipe[i]); 2594 } 2595 /* Stop Rx pipe. */ 2596 usbd_abort_pipe(sc->rx_pipe); 2597 /* Free Tx/Rx buffers. */ 2598 urtwn_free_tx_list(sc); 2599 urtwn_free_rx_list(sc); 2600 } 2601 2602 int 2603 urtwn_is_oactive(void *cookie) 2604 { 2605 struct urtwn_softc *sc = cookie; 2606 2607 return (TAILQ_EMPTY(&sc->tx_free_list)); 2608 } 2609