1 /* $OpenBSD: if_urtwn.c,v 1.69 2017/01/30 21:54:30 stsp Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 22 */ 23 24 #include "bpfilter.h" 25 26 #include <sys/param.h> 27 #include <sys/sockio.h> 28 #include <sys/mbuf.h> 29 #include <sys/kernel.h> 30 #include <sys/socket.h> 31 #include <sys/systm.h> 32 #include <sys/timeout.h> 33 #include <sys/conf.h> 34 #include <sys/device.h> 35 #include <sys/endian.h> 36 37 #include <machine/intr.h> 38 39 #if NBPFILTER > 0 40 #include <net/bpf.h> 41 #endif 42 #include <net/if.h> 43 #include <net/if_dl.h> 44 #include <net/if_media.h> 45 46 #include <netinet/in.h> 47 #include <netinet/if_ether.h> 48 49 #include <net80211/ieee80211_var.h> 50 #include <net80211/ieee80211_amrr.h> 51 #include <net80211/ieee80211_radiotap.h> 52 53 #include <dev/usb/usb.h> 54 #include <dev/usb/usbdi.h> 55 #include <dev/usb/usbdi_util.h> 56 #include <dev/usb/usbdevs.h> 57 58 #include <dev/ic/r92creg.h> 59 #include <dev/ic/rtwnvar.h> 60 61 /* Maximum number of output pipes is 3. */ 62 #define R92C_MAX_EPOUT 3 63 64 #define R92C_PUBQ_NPAGES 231 65 #define R92C_TXPKTBUF_COUNT 256 66 #define R92C_TX_PAGE_COUNT 248 67 #define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) 68 #define R88E_TXPKTBUF_COUNT 177 69 #define R88E_TX_PAGE_COUNT 169 70 #define R88E_TX_PAGE_BOUNDARY (R88E_TX_PAGE_COUNT + 1) 71 72 /* USB Requests. */ 73 #define R92C_REQ_REGS 0x05 74 75 /* 76 * Driver definitions. 77 */ 78 #define URTWN_RX_LIST_COUNT 1 79 #define URTWN_TX_LIST_COUNT 8 80 #define URTWN_HOST_CMD_RING_COUNT 32 81 82 #define URTWN_RXBUFSZ (16 * 1024) 83 #define URTWN_TXBUFSZ (sizeof(struct r92c_tx_desc_usb) + IEEE80211_MAX_LEN) 84 85 #define URTWN_RIDX_COUNT 28 86 87 #define URTWN_TX_TIMEOUT 5000 /* ms */ 88 89 #define URTWN_LED_LINK 0 90 #define URTWN_LED_DATA 1 91 92 struct urtwn_rx_radiotap_header { 93 struct ieee80211_radiotap_header wr_ihdr; 94 uint8_t wr_flags; 95 uint8_t wr_rate; 96 uint16_t wr_chan_freq; 97 uint16_t wr_chan_flags; 98 uint8_t wr_dbm_antsignal; 99 } __packed; 100 101 #define URTWN_RX_RADIOTAP_PRESENT \ 102 (1 << IEEE80211_RADIOTAP_FLAGS | \ 103 1 << IEEE80211_RADIOTAP_RATE | \ 104 1 << IEEE80211_RADIOTAP_CHANNEL | \ 105 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) 106 107 struct urtwn_tx_radiotap_header { 108 struct ieee80211_radiotap_header wt_ihdr; 109 uint8_t wt_flags; 110 uint16_t wt_chan_freq; 111 uint16_t wt_chan_flags; 112 } __packed; 113 114 #define URTWN_TX_RADIOTAP_PRESENT \ 115 (1 << IEEE80211_RADIOTAP_FLAGS | \ 116 1 << IEEE80211_RADIOTAP_CHANNEL) 117 118 struct urtwn_softc; 119 120 struct urtwn_rx_data { 121 struct urtwn_softc *sc; 122 struct usbd_xfer *xfer; 123 uint8_t *buf; 124 }; 125 126 struct urtwn_tx_data { 127 struct urtwn_softc *sc; 128 struct usbd_pipe *pipe; 129 struct usbd_xfer *xfer; 130 uint8_t *buf; 131 TAILQ_ENTRY(urtwn_tx_data) next; 132 }; 133 134 struct urtwn_host_cmd { 135 void (*cb)(struct urtwn_softc *, void *); 136 uint8_t data[256]; 137 }; 138 139 struct urtwn_cmd_newstate { 140 enum ieee80211_state state; 141 int arg; 142 }; 143 144 struct urtwn_cmd_key { 145 struct ieee80211_key key; 146 struct ieee80211_node *ni; 147 }; 148 149 struct urtwn_host_cmd_ring { 150 struct urtwn_host_cmd cmd[URTWN_HOST_CMD_RING_COUNT]; 151 int cur; 152 int next; 153 int queued; 154 }; 155 156 struct urtwn_softc { 157 struct device sc_dev; 158 struct rtwn_softc sc_sc; 159 160 struct usbd_device *sc_udev; 161 struct usbd_interface *sc_iface; 162 struct usb_task sc_task; 163 164 struct timeout scan_to; 165 struct timeout calib_to; 166 167 struct usbd_pipe *rx_pipe; 168 struct usbd_pipe *tx_pipe[R92C_MAX_EPOUT]; 169 int ac2idx[EDCA_NUM_AC]; 170 171 struct urtwn_host_cmd_ring cmdq; 172 struct urtwn_rx_data rx_data[URTWN_RX_LIST_COUNT]; 173 struct urtwn_tx_data tx_data[URTWN_TX_LIST_COUNT]; 174 TAILQ_HEAD(, urtwn_tx_data) tx_free_list; 175 176 struct ieee80211_amrr amrr; 177 struct ieee80211_amrr_node amn; 178 179 #if NBPFILTER > 0 180 caddr_t sc_drvbpf; 181 182 union { 183 struct urtwn_rx_radiotap_header th; 184 uint8_t pad[64]; 185 } sc_rxtapu; 186 #define sc_rxtap sc_rxtapu.th 187 int sc_rxtap_len; 188 189 union { 190 struct urtwn_tx_radiotap_header th; 191 uint8_t pad[64]; 192 } sc_txtapu; 193 #define sc_txtap sc_txtapu.th 194 int sc_txtap_len; 195 #endif 196 }; 197 198 #ifdef URTWN_DEBUG 199 #define DPRINTF(x) do { if (urtwn_debug) printf x; } while (0) 200 #define DPRINTFN(n, x) do { if (urtwn_debug >= (n)) printf x; } while (0) 201 int urtwn_debug = 4; 202 #else 203 #define DPRINTF(x) 204 #define DPRINTFN(n, x) 205 #endif 206 207 static const struct usb_devno urtwn_devs[] = { 208 { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8188CU_1 }, 209 { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8188CU_2 }, 210 { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8192CU }, 211 { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_RTL8192CU }, 212 { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_RTL8192CU_2 }, 213 { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_RTL8192CU_3 }, 214 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8188CE_1 }, 215 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8188CE_2 }, 216 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8188CU }, 217 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F7D2102 }, 218 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F9L1004V1 }, 219 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8188CU }, 220 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8188CUS }, 221 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8192CU }, 222 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8192CU_1 }, 223 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8192CU_2 }, 224 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_1 }, 225 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_2 }, 226 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_3 }, 227 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_4 }, 228 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_5 }, 229 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_6 }, 230 { USB_VENDOR_COMPARE, USB_PRODUCT_COMPARE_RTL8192CU }, 231 { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_RTL8192CU }, 232 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DWA131B }, 233 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8188CU }, 234 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_1 }, 235 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_2 }, 236 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_3 }, 237 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_4 }, 238 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_EW7811UN }, 239 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8192CU }, 240 { USB_VENDOR_FEIXUN, USB_PRODUCT_FEIXUN_RTL8188CU }, 241 { USB_VENDOR_FEIXUN, USB_PRODUCT_FEIXUN_RTL8192CU }, 242 { USB_VENDOR_GUILLEMOT, USB_PRODUCT_GUILLEMOT_HWNUP150 }, 243 { USB_VENDOR_GUILLEMOT, USB_PRODUCT_GUILLEMOT_RTL8192CU }, 244 { USB_VENDOR_HAWKING, USB_PRODUCT_HAWKING_RTL8192CU }, 245 { USB_VENDOR_HAWKING, USB_PRODUCT_HAWKING_RTL8192CU_2 }, 246 { USB_VENDOR_HP3, USB_PRODUCT_HP3_RTL8188CU }, 247 { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_WNG150UM }, 248 { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_RTL8192CU }, 249 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_N300MA }, 250 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNA1000M }, 251 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNA1000Mv2 }, 252 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_RTL8192CU }, 253 { USB_VENDOR_NETGEAR4, USB_PRODUCT_NETGEAR4_RTL8188CU }, 254 { USB_VENDOR_NETWEEN, USB_PRODUCT_NETWEEN_RTL8192CU }, 255 { USB_VENDOR_NOVATECH, USB_PRODUCT_NOVATECH_RTL8188CU }, 256 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_1 }, 257 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_2 }, 258 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_3 }, 259 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_4 }, 260 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CUS }, 261 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8192CU }, 262 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CE_0 }, 263 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CE_1 }, 264 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CTV }, 265 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_0 }, 266 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_1 }, 267 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_2 }, 268 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_3 }, 269 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_4 }, 270 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_5 }, 271 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_COMBO }, 272 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CUS }, 273 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188RU }, 274 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188RU_2 }, 275 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188RU_3 }, 276 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8191CU }, 277 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8192CE }, 278 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8192CE_VAU }, 279 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8192CU }, 280 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_RTL8188CU }, 281 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_RTL8188CU_2 }, 282 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_RTL8192CU }, 283 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_RTL8192CU_2 }, 284 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_WLA2100V2 }, 285 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_RTL8192CU }, 286 { USB_VENDOR_TRENDNET, USB_PRODUCT_TRENDNET_RTL8188CU }, 287 { USB_VENDOR_TRENDNET, USB_PRODUCT_TRENDNET_RTL8192CU }, 288 { USB_VENDOR_ZYXEL, USB_PRODUCT_ZYXEL_RTL8192CU }, 289 /* URTWN_RTL8188E */ 290 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DWA123D1 }, 291 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DWA125D1 }, 292 { USB_VENDOR_ELECOM, USB_PRODUCT_ELECOM_WDC150SU2M }, 293 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188ETV }, 294 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188EU } 295 }; 296 297 int urtwn_match(struct device *, void *, void *); 298 void urtwn_attach(struct device *, struct device *, void *); 299 int urtwn_detach(struct device *, int); 300 int urtwn_open_pipes(struct urtwn_softc *); 301 void urtwn_close_pipes(struct urtwn_softc *); 302 int urtwn_alloc_rx_list(struct urtwn_softc *); 303 void urtwn_free_rx_list(struct urtwn_softc *); 304 int urtwn_alloc_tx_list(struct urtwn_softc *); 305 void urtwn_free_tx_list(struct urtwn_softc *); 306 void urtwn_task(void *); 307 void urtwn_do_async(struct urtwn_softc *, 308 void (*)(struct urtwn_softc *, void *), void *, int); 309 void urtwn_wait_async(void *); 310 int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 311 int); 312 void urtwn_write_1(void *, uint16_t, uint8_t); 313 void urtwn_write_2(void *, uint16_t, uint16_t); 314 void urtwn_write_4(void *, uint16_t, uint32_t); 315 int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 316 int); 317 uint8_t urtwn_read_1(void *, uint16_t); 318 uint16_t urtwn_read_2(void *, uint16_t); 319 uint32_t urtwn_read_4(void *, uint16_t); 320 int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 321 void urtwn_calib_to(void *); 322 void urtwn_calib_cb(struct urtwn_softc *, void *); 323 void urtwn_scan_to(void *); 324 void urtwn_next_scan(void *); 325 void urtwn_cancel_scan(void *); 326 int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 327 int); 328 void urtwn_newstate_cb(struct urtwn_softc *, void *); 329 void urtwn_updateslot(struct ieee80211com *); 330 void urtwn_updateslot_cb(struct urtwn_softc *, void *); 331 void urtwn_updateedca(struct ieee80211com *); 332 void urtwn_updateedca_cb(struct urtwn_softc *, void *); 333 int urtwn_set_key(struct ieee80211com *, struct ieee80211_node *, 334 struct ieee80211_key *); 335 void urtwn_set_key_cb(struct urtwn_softc *, void *); 336 void urtwn_delete_key(struct ieee80211com *, 337 struct ieee80211_node *, struct ieee80211_key *); 338 void urtwn_delete_key_cb(struct urtwn_softc *, void *); 339 void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 340 void urtwn_rxeof(struct usbd_xfer *, void *, 341 usbd_status); 342 void urtwn_txeof(struct usbd_xfer *, void *, 343 usbd_status); 344 int urtwn_tx(void *, struct mbuf *, struct ieee80211_node *); 345 int urtwn_ioctl(struct ifnet *, u_long, caddr_t); 346 int urtwn_power_on(void *); 347 int urtwn_alloc_buffers(void *); 348 int urtwn_r92c_power_on(struct urtwn_softc *); 349 int urtwn_r88e_power_on(struct urtwn_softc *); 350 int urtwn_llt_init(struct urtwn_softc *); 351 int urtwn_fw_loadpage(void *, int, uint8_t *, int); 352 int urtwn_load_firmware(void *, u_char **, size_t *); 353 int urtwn_dma_init(void *); 354 int urtwn_r92c_dma_init(struct urtwn_softc *); 355 int urtwn_r88e_dma_init(struct urtwn_softc *); 356 void urtwn_mac_init(void *); 357 void urtwn_bb_init(void *); 358 int urtwn_init(void *); 359 void urtwn_stop(void *); 360 int urtwn_is_oactive(void *); 361 void urtwn_next_calib(void *); 362 void urtwn_cancel_calib(void *); 363 364 /* Aliases. */ 365 #define urtwn_bb_write urtwn_write_4 366 #define urtwn_bb_read urtwn_read_4 367 368 struct cfdriver urtwn_cd = { 369 NULL, "urtwn", DV_IFNET 370 }; 371 372 const struct cfattach urtwn_ca = { 373 sizeof(struct urtwn_softc), urtwn_match, urtwn_attach, urtwn_detach 374 }; 375 376 int 377 urtwn_match(struct device *parent, void *match, void *aux) 378 { 379 struct usb_attach_arg *uaa = aux; 380 381 if (uaa->iface == NULL || uaa->configno != 1) 382 return (UMATCH_NONE); 383 384 return ((usb_lookup(urtwn_devs, uaa->vendor, uaa->product) != NULL) ? 385 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 386 } 387 388 void 389 urtwn_attach(struct device *parent, struct device *self, void *aux) 390 { 391 struct urtwn_softc *sc = (struct urtwn_softc *)self; 392 struct usb_attach_arg *uaa = aux; 393 struct ifnet *ifp; 394 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 395 uint32_t chip_type; 396 397 sc->sc_udev = uaa->device; 398 sc->sc_iface = uaa->iface; 399 400 usb_init_task(&sc->sc_task, urtwn_task, sc, USB_TASK_TYPE_GENERIC); 401 timeout_set(&sc->scan_to, urtwn_scan_to, sc); 402 timeout_set(&sc->calib_to, urtwn_calib_to, sc); 403 if (urtwn_open_pipes(sc) != 0) 404 return; 405 406 chip_type = RTWN_CHIP_USB; 407 if (uaa->product == USB_PRODUCT_DLINK_DWA123D1 || 408 uaa->product == USB_PRODUCT_DLINK_DWA125D1 || 409 uaa->product == USB_PRODUCT_ELECOM_WDC150SU2M || 410 uaa->product == USB_PRODUCT_REALTEK_RTL8188EU || 411 uaa->product == USB_PRODUCT_REALTEK_RTL8188ETV) 412 chip_type |= RTWN_CHIP_88E; 413 else 414 chip_type |= (RTWN_CHIP_92C | RTWN_CHIP_88C); 415 416 sc->amrr.amrr_min_success_threshold = 1; 417 sc->amrr.amrr_max_success_threshold = 10; 418 419 /* Attach the bus-agnostic driver. */ 420 sc->sc_sc.sc_ops.cookie = sc; 421 sc->sc_sc.sc_ops.write_1 = urtwn_write_1; 422 sc->sc_sc.sc_ops.write_2 = urtwn_write_2; 423 sc->sc_sc.sc_ops.write_4 = urtwn_write_4; 424 sc->sc_sc.sc_ops.read_1 = urtwn_read_1; 425 sc->sc_sc.sc_ops.read_2 = urtwn_read_2; 426 sc->sc_sc.sc_ops.read_4 = urtwn_read_4; 427 sc->sc_sc.sc_ops.tx = urtwn_tx; 428 sc->sc_sc.sc_ops.power_on = urtwn_power_on; 429 sc->sc_sc.sc_ops.dma_init = urtwn_dma_init; 430 sc->sc_sc.sc_ops.fw_loadpage = urtwn_fw_loadpage; 431 sc->sc_sc.sc_ops.load_firmware = urtwn_load_firmware; 432 sc->sc_sc.sc_ops.mac_init = urtwn_mac_init; 433 sc->sc_sc.sc_ops.bb_init = urtwn_bb_init; 434 sc->sc_sc.sc_ops.alloc_buffers = urtwn_alloc_buffers; 435 sc->sc_sc.sc_ops.init = urtwn_init; 436 sc->sc_sc.sc_ops.stop = urtwn_stop; 437 sc->sc_sc.sc_ops.is_oactive = urtwn_is_oactive; 438 sc->sc_sc.sc_ops.next_calib = urtwn_next_calib; 439 sc->sc_sc.sc_ops.cancel_calib = urtwn_cancel_calib; 440 sc->sc_sc.sc_ops.next_scan = urtwn_next_scan; 441 sc->sc_sc.sc_ops.cancel_scan = urtwn_cancel_scan; 442 sc->sc_sc.sc_ops.wait_async = urtwn_wait_async; 443 if (rtwn_attach(&sc->sc_dev, &sc->sc_sc, chip_type) != 0) { 444 urtwn_close_pipes(sc); 445 return; 446 } 447 448 /* ifp is now valid */ 449 ifp = &sc->sc_sc.sc_ic.ic_if; 450 ifp->if_ioctl = urtwn_ioctl; 451 452 ic->ic_updateslot = urtwn_updateslot; 453 ic->ic_updateedca = urtwn_updateedca; 454 #ifdef notyet 455 ic->ic_set_key = urtwn_set_key; 456 ic->ic_delete_key = urtwn_delete_key; 457 #endif 458 /* Override state transition machine. */ 459 ic->ic_newstate = urtwn_newstate; 460 461 #if NBPFILTER > 0 462 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 463 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 464 465 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 466 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 467 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 468 469 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 470 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 471 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 472 #endif 473 } 474 475 int 476 urtwn_detach(struct device *self, int flags) 477 { 478 struct urtwn_softc *sc = (struct urtwn_softc *)self; 479 int s; 480 481 s = splusb(); 482 483 if (timeout_initialized(&sc->scan_to)) 484 timeout_del(&sc->scan_to); 485 if (timeout_initialized(&sc->calib_to)) 486 timeout_del(&sc->calib_to); 487 488 /* Wait for all async commands to complete. */ 489 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 490 491 usbd_ref_wait(sc->sc_udev); 492 493 rtwn_detach(&sc->sc_sc, flags); 494 495 /* Abort and close Tx/Rx pipes. */ 496 urtwn_close_pipes(sc); 497 498 /* Free Tx/Rx buffers. */ 499 urtwn_free_tx_list(sc); 500 urtwn_free_rx_list(sc); 501 splx(s); 502 503 return (0); 504 } 505 506 int 507 urtwn_open_pipes(struct urtwn_softc *sc) 508 { 509 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 510 const uint8_t epaddr[] = { 0x02, 0x03, 0x05 }; 511 usb_interface_descriptor_t *id; 512 usb_endpoint_descriptor_t *ed; 513 int i, ntx = 0, error; 514 515 /* Determine the number of bulk-out pipes. */ 516 id = usbd_get_interface_descriptor(sc->sc_iface); 517 for (i = 0; i < id->bNumEndpoints; i++) { 518 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 519 if (ed != NULL && 520 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK && 521 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) 522 ntx++; 523 } 524 DPRINTF(("found %d bulk-out pipes\n", ntx)); 525 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 526 printf("%s: %d: invalid number of Tx bulk pipes\n", 527 sc->sc_dev.dv_xname, ntx); 528 return (EIO); 529 } 530 531 /* Open bulk-in pipe at address 0x81. */ 532 error = usbd_open_pipe(sc->sc_iface, 0x81, 0, &sc->rx_pipe); 533 if (error != 0) { 534 printf("%s: could not open Rx bulk pipe\n", 535 sc->sc_dev.dv_xname); 536 goto fail; 537 } 538 539 /* Open bulk-out pipes (up to 3). */ 540 for (i = 0; i < ntx; i++) { 541 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 0, 542 &sc->tx_pipe[i]); 543 if (error != 0) { 544 printf("%s: could not open Tx bulk pipe 0x%02x\n", 545 sc->sc_dev.dv_xname, epaddr[i]); 546 goto fail; 547 } 548 } 549 550 /* Map 802.11 access categories to USB pipes. */ 551 sc->ac2idx[EDCA_AC_BK] = 552 sc->ac2idx[EDCA_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 553 sc->ac2idx[EDCA_AC_VI] = (ntx == 3) ? 1 : 0; 554 sc->ac2idx[EDCA_AC_VO] = 0; /* Always use highest prio. */ 555 556 if (error != 0) 557 fail: urtwn_close_pipes(sc); 558 return (error); 559 } 560 561 void 562 urtwn_close_pipes(struct urtwn_softc *sc) 563 { 564 int i; 565 566 /* Close Rx pipe. */ 567 if (sc->rx_pipe != NULL) { 568 usbd_abort_pipe(sc->rx_pipe); 569 usbd_close_pipe(sc->rx_pipe); 570 } 571 /* Close Tx pipes. */ 572 for (i = 0; i < R92C_MAX_EPOUT; i++) { 573 if (sc->tx_pipe[i] == NULL) 574 continue; 575 usbd_abort_pipe(sc->tx_pipe[i]); 576 usbd_close_pipe(sc->tx_pipe[i]); 577 } 578 } 579 580 int 581 urtwn_alloc_rx_list(struct urtwn_softc *sc) 582 { 583 struct urtwn_rx_data *data; 584 int i, error = 0; 585 586 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 587 data = &sc->rx_data[i]; 588 589 data->sc = sc; /* Backpointer for callbacks. */ 590 591 data->xfer = usbd_alloc_xfer(sc->sc_udev); 592 if (data->xfer == NULL) { 593 printf("%s: could not allocate xfer\n", 594 sc->sc_dev.dv_xname); 595 error = ENOMEM; 596 break; 597 } 598 data->buf = usbd_alloc_buffer(data->xfer, URTWN_RXBUFSZ); 599 if (data->buf == NULL) { 600 printf("%s: could not allocate xfer buffer\n", 601 sc->sc_dev.dv_xname); 602 error = ENOMEM; 603 break; 604 } 605 } 606 if (error != 0) 607 urtwn_free_rx_list(sc); 608 return (error); 609 } 610 611 void 612 urtwn_free_rx_list(struct urtwn_softc *sc) 613 { 614 int i; 615 616 /* NB: Caller must abort pipe first. */ 617 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 618 if (sc->rx_data[i].xfer != NULL) 619 usbd_free_xfer(sc->rx_data[i].xfer); 620 sc->rx_data[i].xfer = NULL; 621 } 622 } 623 624 int 625 urtwn_alloc_tx_list(struct urtwn_softc *sc) 626 { 627 struct urtwn_tx_data *data; 628 int i, error = 0; 629 630 TAILQ_INIT(&sc->tx_free_list); 631 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 632 data = &sc->tx_data[i]; 633 634 data->sc = sc; /* Backpointer for callbacks. */ 635 636 data->xfer = usbd_alloc_xfer(sc->sc_udev); 637 if (data->xfer == NULL) { 638 printf("%s: could not allocate xfer\n", 639 sc->sc_dev.dv_xname); 640 error = ENOMEM; 641 break; 642 } 643 data->buf = usbd_alloc_buffer(data->xfer, URTWN_TXBUFSZ); 644 if (data->buf == NULL) { 645 printf("%s: could not allocate xfer buffer\n", 646 sc->sc_dev.dv_xname); 647 error = ENOMEM; 648 break; 649 } 650 /* Append this Tx buffer to our free list. */ 651 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 652 } 653 if (error != 0) 654 urtwn_free_tx_list(sc); 655 return (error); 656 } 657 658 void 659 urtwn_free_tx_list(struct urtwn_softc *sc) 660 { 661 int i; 662 663 /* NB: Caller must abort pipe first. */ 664 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 665 if (sc->tx_data[i].xfer != NULL) 666 usbd_free_xfer(sc->tx_data[i].xfer); 667 sc->tx_data[i].xfer = NULL; 668 } 669 } 670 671 void 672 urtwn_task(void *arg) 673 { 674 struct urtwn_softc *sc = arg; 675 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 676 struct urtwn_host_cmd *cmd; 677 int s; 678 679 /* Process host commands. */ 680 s = splusb(); 681 while (ring->next != ring->cur) { 682 cmd = &ring->cmd[ring->next]; 683 splx(s); 684 /* Invoke callback. */ 685 cmd->cb(sc, cmd->data); 686 s = splusb(); 687 ring->queued--; 688 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 689 } 690 splx(s); 691 } 692 693 void 694 urtwn_do_async(struct urtwn_softc *sc, 695 void (*cb)(struct urtwn_softc *, void *), void *arg, int len) 696 { 697 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 698 struct urtwn_host_cmd *cmd; 699 int s; 700 701 s = splusb(); 702 cmd = &ring->cmd[ring->cur]; 703 cmd->cb = cb; 704 KASSERT(len <= sizeof(cmd->data)); 705 memcpy(cmd->data, arg, len); 706 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 707 708 /* If there is no pending command already, schedule a task. */ 709 if (++ring->queued == 1) 710 usb_add_task(sc->sc_udev, &sc->sc_task); 711 splx(s); 712 } 713 714 void 715 urtwn_wait_async(void *cookie) 716 { 717 struct urtwn_softc *sc = cookie; 718 int s; 719 720 s = splusb(); 721 /* Wait for all queued asynchronous commands to complete. */ 722 usb_wait_task(sc->sc_udev, &sc->sc_task); 723 splx(s); 724 } 725 726 int 727 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 728 int len) 729 { 730 usb_device_request_t req; 731 732 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 733 req.bRequest = R92C_REQ_REGS; 734 USETW(req.wValue, addr); 735 USETW(req.wIndex, 0); 736 USETW(req.wLength, len); 737 return (usbd_do_request(sc->sc_udev, &req, buf)); 738 } 739 740 void 741 urtwn_write_1(void *cookie, uint16_t addr, uint8_t val) 742 { 743 struct urtwn_softc *sc = cookie; 744 745 urtwn_write_region_1(sc, addr, &val, 1); 746 } 747 748 void 749 urtwn_write_2(void *cookie, uint16_t addr, uint16_t val) 750 { 751 struct urtwn_softc *sc = cookie; 752 753 val = htole16(val); 754 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 755 } 756 757 void 758 urtwn_write_4(void *cookie, uint16_t addr, uint32_t val) 759 { 760 struct urtwn_softc *sc = cookie; 761 762 val = htole32(val); 763 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 764 } 765 766 int 767 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 768 int len) 769 { 770 usb_device_request_t req; 771 772 req.bmRequestType = UT_READ_VENDOR_DEVICE; 773 req.bRequest = R92C_REQ_REGS; 774 USETW(req.wValue, addr); 775 USETW(req.wIndex, 0); 776 USETW(req.wLength, len); 777 return (usbd_do_request(sc->sc_udev, &req, buf)); 778 } 779 780 uint8_t 781 urtwn_read_1(void *cookie, uint16_t addr) 782 { 783 struct urtwn_softc *sc = cookie; 784 uint8_t val; 785 786 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 787 return (0xff); 788 return (val); 789 } 790 791 uint16_t 792 urtwn_read_2(void *cookie, uint16_t addr) 793 { 794 struct urtwn_softc *sc = cookie; 795 uint16_t val; 796 797 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 798 return (0xffff); 799 return (letoh16(val)); 800 } 801 802 uint32_t 803 urtwn_read_4(void *cookie, uint16_t addr) 804 { 805 struct urtwn_softc *sc = cookie; 806 uint32_t val; 807 808 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 809 return (0xffffffff); 810 return (letoh32(val)); 811 } 812 813 int 814 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 815 { 816 int ntries; 817 818 urtwn_write_4(sc, R92C_LLT_INIT, 819 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 820 SM(R92C_LLT_INIT_ADDR, addr) | 821 SM(R92C_LLT_INIT_DATA, data)); 822 /* Wait for write operation to complete. */ 823 for (ntries = 0; ntries < 20; ntries++) { 824 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 825 R92C_LLT_INIT_OP_NO_ACTIVE) 826 return (0); 827 DELAY(5); 828 } 829 return (ETIMEDOUT); 830 } 831 832 void 833 urtwn_calib_to(void *arg) 834 { 835 struct urtwn_softc *sc = arg; 836 837 if (usbd_is_dying(sc->sc_udev)) 838 return; 839 840 usbd_ref_incr(sc->sc_udev); 841 842 /* Do it in a process context. */ 843 urtwn_do_async(sc, urtwn_calib_cb, NULL, 0); 844 845 usbd_ref_decr(sc->sc_udev); 846 } 847 848 /* ARGSUSED */ 849 void 850 urtwn_calib_cb(struct urtwn_softc *sc, void *arg) 851 { 852 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 853 int s; 854 855 s = splnet(); 856 if (ic->ic_opmode == IEEE80211_M_STA) { 857 ieee80211_amrr_choose(&sc->amrr, ic->ic_bss, &sc->amn); 858 } 859 splx(s); 860 861 rtwn_calib(&sc->sc_sc); 862 } 863 864 void 865 urtwn_next_calib(void *cookie) 866 { 867 struct urtwn_softc *sc = cookie; 868 869 if (!usbd_is_dying(sc->sc_udev)) 870 timeout_add_sec(&sc->calib_to, 2); 871 } 872 873 void 874 urtwn_cancel_calib(void *cookie) 875 { 876 struct urtwn_softc *sc = cookie; 877 878 if (timeout_initialized(&sc->calib_to)) 879 timeout_del(&sc->calib_to); 880 } 881 882 void 883 urtwn_scan_to(void *arg) 884 { 885 struct urtwn_softc *sc = arg; 886 887 if (usbd_is_dying(sc->sc_udev)) 888 return; 889 890 usbd_ref_incr(sc->sc_udev); 891 rtwn_next_scan(&sc->sc_sc); 892 usbd_ref_decr(sc->sc_udev); 893 } 894 895 void 896 urtwn_next_scan(void *arg) 897 { 898 struct urtwn_softc *sc = arg; 899 900 if (!usbd_is_dying(sc->sc_udev)) 901 timeout_add_msec(&sc->scan_to, 200); 902 } 903 904 void 905 urtwn_cancel_scan(void *cookie) 906 { 907 struct urtwn_softc *sc = cookie; 908 909 if (timeout_initialized(&sc->scan_to)) 910 timeout_del(&sc->scan_to); 911 } 912 913 int 914 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 915 { 916 struct rtwn_softc *sc_sc = ic->ic_softc; 917 struct device *self = sc_sc->sc_pdev; 918 struct urtwn_softc *sc = (struct urtwn_softc *)self; 919 struct urtwn_cmd_newstate cmd; 920 921 /* Do it in a process context. */ 922 cmd.state = nstate; 923 cmd.arg = arg; 924 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 925 return (0); 926 } 927 928 void 929 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 930 { 931 struct urtwn_cmd_newstate *cmd = arg; 932 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 933 934 rtwn_newstate(ic, cmd->state, cmd->arg); 935 } 936 937 void 938 urtwn_updateslot(struct ieee80211com *ic) 939 { 940 struct rtwn_softc *sc_sc = ic->ic_softc; 941 struct device *self = sc_sc->sc_pdev; 942 struct urtwn_softc *sc = (struct urtwn_softc *)self; 943 944 /* Do it in a process context. */ 945 urtwn_do_async(sc, urtwn_updateslot_cb, NULL, 0); 946 } 947 948 /* ARGSUSED */ 949 void 950 urtwn_updateslot_cb(struct urtwn_softc *sc, void *arg) 951 { 952 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 953 954 rtwn_updateslot(ic); 955 } 956 957 void 958 urtwn_updateedca(struct ieee80211com *ic) 959 { 960 struct rtwn_softc *sc_sc = ic->ic_softc; 961 struct device *self = sc_sc->sc_pdev; 962 struct urtwn_softc *sc = (struct urtwn_softc *)self; 963 964 /* Do it in a process context. */ 965 urtwn_do_async(sc, urtwn_updateedca_cb, NULL, 0); 966 } 967 968 /* ARGSUSED */ 969 void 970 urtwn_updateedca_cb(struct urtwn_softc *sc, void *arg) 971 { 972 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 973 974 rtwn_updateedca(ic); 975 } 976 977 int 978 urtwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 979 struct ieee80211_key *k) 980 { 981 struct rtwn_softc *sc_sc = ic->ic_softc; 982 struct device *self = sc_sc->sc_pdev; 983 struct urtwn_softc *sc = (struct urtwn_softc *)self; 984 struct urtwn_cmd_key cmd; 985 986 /* Defer setting of WEP keys until interface is brought up. */ 987 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 988 (IFF_UP | IFF_RUNNING)) 989 return (0); 990 991 /* Do it in a process context. */ 992 cmd.key = *k; 993 cmd.ni = ni; 994 urtwn_do_async(sc, urtwn_set_key_cb, &cmd, sizeof(cmd)); 995 return (0); 996 } 997 998 void 999 urtwn_set_key_cb(struct urtwn_softc *sc, void *arg) 1000 { 1001 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1002 struct urtwn_cmd_key *cmd = arg; 1003 1004 rtwn_set_key(ic, cmd->ni, &cmd->key); 1005 } 1006 1007 void 1008 urtwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1009 struct ieee80211_key *k) 1010 { 1011 struct rtwn_softc *sc_sc = ic->ic_softc; 1012 struct device *self = sc_sc->sc_pdev; 1013 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1014 struct urtwn_cmd_key cmd; 1015 1016 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 1017 ic->ic_state != IEEE80211_S_RUN) 1018 return; /* Nothing to do. */ 1019 1020 /* Do it in a process context. */ 1021 cmd.key = *k; 1022 cmd.ni = ni; 1023 urtwn_do_async(sc, urtwn_delete_key_cb, &cmd, sizeof(cmd)); 1024 } 1025 1026 void 1027 urtwn_delete_key_cb(struct urtwn_softc *sc, void *arg) 1028 { 1029 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1030 struct urtwn_cmd_key *cmd = arg; 1031 1032 rtwn_delete_key(ic, cmd->ni, &cmd->key); 1033 } 1034 1035 void 1036 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 1037 { 1038 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1039 struct ifnet *ifp = &ic->ic_if; 1040 struct ieee80211_rxinfo rxi; 1041 struct ieee80211_frame *wh; 1042 struct ieee80211_node *ni; 1043 struct r92c_rx_desc_usb *rxd; 1044 uint32_t rxdw0, rxdw3; 1045 struct mbuf *m; 1046 uint8_t rate; 1047 int8_t rssi = 0; 1048 int s, infosz; 1049 1050 rxd = (struct r92c_rx_desc_usb *)buf; 1051 rxdw0 = letoh32(rxd->rxdw0); 1052 rxdw3 = letoh32(rxd->rxdw3); 1053 1054 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1055 /* 1056 * This should not happen since we setup our Rx filter 1057 * to not receive these frames. 1058 */ 1059 ifp->if_ierrors++; 1060 return; 1061 } 1062 if (__predict_false(pktlen < sizeof(*wh) || pktlen > MCLBYTES)) { 1063 ifp->if_ierrors++; 1064 return; 1065 } 1066 1067 rate = MS(rxdw3, R92C_RXDW3_RATE); 1068 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1069 1070 /* Get RSSI from PHY status descriptor if present. */ 1071 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1072 rssi = rtwn_get_rssi(&sc->sc_sc, rate, &rxd[1]); 1073 /* Update our average RSSI. */ 1074 rtwn_update_avgrssi(&sc->sc_sc, rate, rssi); 1075 } 1076 1077 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 1078 pktlen, rate, infosz, rssi)); 1079 1080 MGETHDR(m, M_DONTWAIT, MT_DATA); 1081 if (__predict_false(m == NULL)) { 1082 ifp->if_ierrors++; 1083 return; 1084 } 1085 if (pktlen > MHLEN) { 1086 MCLGET(m, M_DONTWAIT); 1087 if (__predict_false(!(m->m_flags & M_EXT))) { 1088 ifp->if_ierrors++; 1089 m_freem(m); 1090 return; 1091 } 1092 } 1093 /* Finalize mbuf. */ 1094 wh = (struct ieee80211_frame *)((uint8_t *)&rxd[1] + infosz); 1095 memcpy(mtod(m, uint8_t *), wh, pktlen); 1096 m->m_pkthdr.len = m->m_len = pktlen; 1097 1098 s = splnet(); 1099 #if NBPFILTER > 0 1100 if (__predict_false(sc->sc_drvbpf != NULL)) { 1101 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1102 struct mbuf mb; 1103 1104 tap->wr_flags = 0; 1105 /* Map HW rate index to 802.11 rate. */ 1106 tap->wr_flags = 2; 1107 if (!(rxdw3 & R92C_RXDW3_HT)) { 1108 switch (rate) { 1109 /* CCK. */ 1110 case 0: tap->wr_rate = 2; break; 1111 case 1: tap->wr_rate = 4; break; 1112 case 2: tap->wr_rate = 11; break; 1113 case 3: tap->wr_rate = 22; break; 1114 /* OFDM. */ 1115 case 4: tap->wr_rate = 12; break; 1116 case 5: tap->wr_rate = 18; break; 1117 case 6: tap->wr_rate = 24; break; 1118 case 7: tap->wr_rate = 36; break; 1119 case 8: tap->wr_rate = 48; break; 1120 case 9: tap->wr_rate = 72; break; 1121 case 10: tap->wr_rate = 96; break; 1122 case 11: tap->wr_rate = 108; break; 1123 } 1124 } else if (rate >= 12) { /* MCS0~15. */ 1125 /* Bit 7 set means HT MCS instead of rate. */ 1126 tap->wr_rate = 0x80 | (rate - 12); 1127 } 1128 tap->wr_dbm_antsignal = rssi; 1129 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1130 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1131 1132 mb.m_data = (caddr_t)tap; 1133 mb.m_len = sc->sc_rxtap_len; 1134 mb.m_next = m; 1135 mb.m_nextpkt = NULL; 1136 mb.m_type = 0; 1137 mb.m_flags = 0; 1138 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1139 } 1140 #endif 1141 1142 ni = ieee80211_find_rxnode(ic, wh); 1143 rxi.rxi_flags = 0; 1144 rxi.rxi_rssi = rssi; 1145 rxi.rxi_tstamp = 0; /* Unused. */ 1146 ieee80211_input(ifp, m, ni, &rxi); 1147 /* Node is no longer needed. */ 1148 ieee80211_release_node(ic, ni); 1149 splx(s); 1150 } 1151 1152 void 1153 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, 1154 usbd_status status) 1155 { 1156 struct urtwn_rx_data *data = priv; 1157 struct urtwn_softc *sc = data->sc; 1158 struct r92c_rx_desc_usb *rxd; 1159 uint32_t rxdw0; 1160 uint8_t *buf; 1161 int len, totlen, pktlen, infosz, npkts, error; 1162 1163 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1164 DPRINTF(("RX status=%d\n", status)); 1165 if (status == USBD_STALLED) 1166 usbd_clear_endpoint_stall_async(sc->rx_pipe); 1167 if (status != USBD_CANCELLED) 1168 goto resubmit; 1169 return; 1170 } 1171 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 1172 1173 if (__predict_false(len < sizeof(*rxd))) { 1174 DPRINTF(("xfer too short %d\n", len)); 1175 goto resubmit; 1176 } 1177 buf = data->buf; 1178 1179 /* Get the number of encapsulated frames. */ 1180 rxd = (struct r92c_rx_desc_usb *)buf; 1181 npkts = MS(letoh32(rxd->rxdw2), R92C_RXDW2_PKTCNT); 1182 DPRINTFN(4, ("Rx %d frames in one chunk\n", npkts)); 1183 1184 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1185 int ntries, type; 1186 struct r88e_tx_rpt_ccx *rxstat; 1187 1188 type = MS(letoh32(rxd->rxdw3), R88E_RXDW3_RPT); 1189 1190 if (type == R88E_RXDW3_RPT_TX1) { 1191 buf += sizeof(struct r92c_rx_desc_usb); 1192 rxstat = (struct r88e_tx_rpt_ccx *)buf; 1193 ntries = MS(letoh32(rxstat->rptb2), 1194 R88E_RPTB2_RETRY_CNT); 1195 1196 if (rxstat->rptb1 & R88E_RPTB1_PKT_OK) 1197 sc->amn.amn_txcnt++; 1198 if (ntries > 0) 1199 sc->amn.amn_retrycnt++; 1200 1201 goto resubmit; 1202 } 1203 } 1204 1205 /* Process all of them. */ 1206 while (npkts-- > 0) { 1207 if (__predict_false(len < sizeof(*rxd))) 1208 break; 1209 rxd = (struct r92c_rx_desc_usb *)buf; 1210 rxdw0 = letoh32(rxd->rxdw0); 1211 1212 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1213 if (__predict_false(pktlen == 0)) 1214 break; 1215 1216 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1217 1218 /* Make sure everything fits in xfer. */ 1219 totlen = sizeof(*rxd) + infosz + pktlen; 1220 if (__predict_false(totlen > len)) 1221 break; 1222 1223 /* Process 802.11 frame. */ 1224 urtwn_rx_frame(sc, buf, pktlen); 1225 1226 /* Next chunk is 128-byte aligned. */ 1227 totlen = (totlen + 127) & ~127; 1228 buf += totlen; 1229 len -= totlen; 1230 } 1231 1232 resubmit: 1233 /* Setup a new transfer. */ 1234 usbd_setup_xfer(xfer, sc->rx_pipe, data, data->buf, URTWN_RXBUFSZ, 1235 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, urtwn_rxeof); 1236 error = usbd_transfer(data->xfer); 1237 if (error != 0 && error != USBD_IN_PROGRESS) 1238 DPRINTF(("could not set up new transfer: %d\n", error)); 1239 } 1240 1241 void 1242 urtwn_txeof(struct usbd_xfer *xfer, void *priv, 1243 usbd_status status) 1244 { 1245 struct urtwn_tx_data *data = priv; 1246 struct urtwn_softc *sc = data->sc; 1247 struct ifnet *ifp = &sc->sc_sc.sc_ic.ic_if; 1248 int s; 1249 1250 s = splnet(); 1251 /* Put this Tx buffer back to our free list. */ 1252 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1253 1254 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1255 DPRINTF(("TX status=%d\n", status)); 1256 if (status == USBD_STALLED) 1257 usbd_clear_endpoint_stall_async(data->pipe); 1258 ifp->if_oerrors++; 1259 splx(s); 1260 return; 1261 } 1262 sc->sc_sc.sc_tx_timer = 0; 1263 1264 /* We just released a Tx buffer, notify Tx. */ 1265 if (ifq_is_oactive(&ifp->if_snd)) { 1266 ifq_clr_oactive(&ifp->if_snd); 1267 rtwn_start(ifp); 1268 } 1269 splx(s); 1270 } 1271 1272 int 1273 urtwn_tx(void *cookie, struct mbuf *m, struct ieee80211_node *ni) 1274 { 1275 struct urtwn_softc *sc = cookie; 1276 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1277 struct ieee80211_frame *wh; 1278 struct ieee80211_key *k = NULL; 1279 struct urtwn_tx_data *data; 1280 struct r92c_tx_desc_usb *txd; 1281 struct usbd_pipe *pipe; 1282 uint16_t qos, sum; 1283 uint8_t raid, type, tid, qid; 1284 int i, hasqos, xferlen, error; 1285 1286 wh = mtod(m, struct ieee80211_frame *); 1287 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1288 1289 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1290 k = ieee80211_get_txkey(ic, wh, ni); 1291 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1292 return (ENOBUFS); 1293 wh = mtod(m, struct ieee80211_frame *); 1294 } 1295 1296 if ((hasqos = ieee80211_has_qos(wh))) { 1297 qos = ieee80211_get_qos(wh); 1298 tid = qos & IEEE80211_QOS_TID; 1299 qid = ieee80211_up_to_ac(ic, tid); 1300 } else if (type != IEEE80211_FC0_TYPE_DATA) { 1301 /* Use AC VO for management frames. */ 1302 qid = EDCA_AC_VO; 1303 } else 1304 qid = EDCA_AC_BE; 1305 1306 /* Get the USB pipe to use for this AC. */ 1307 pipe = sc->tx_pipe[sc->ac2idx[qid]]; 1308 1309 /* Grab a Tx buffer from our free list. */ 1310 data = TAILQ_FIRST(&sc->tx_free_list); 1311 TAILQ_REMOVE(&sc->tx_free_list, data, next); 1312 1313 /* Fill Tx descriptor. */ 1314 txd = (struct r92c_tx_desc_usb *)data->buf; 1315 memset(txd, 0, sizeof(*txd)); 1316 1317 txd->txdw0 |= htole32( 1318 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 1319 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1320 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1321 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1322 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1323 1324 #ifdef notyet 1325 if (k != NULL) { 1326 switch (k->k_cipher) { 1327 case IEEE80211_CIPHER_WEP40: 1328 case IEEE80211_CIPHER_WEP104: 1329 case IEEE80211_CIPHER_TKIP: 1330 cipher = R92C_TXDW1_CIPHER_RC4; 1331 break; 1332 case IEEE80211_CIPHER_CCMP: 1333 cipher = R92C_TXDW1_CIPHER_AES; 1334 break; 1335 default: 1336 cipher = R92C_TXDW1_CIPHER_NONE; 1337 } 1338 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 1339 } 1340 #endif 1341 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1342 type == IEEE80211_FC0_TYPE_DATA) { 1343 if (ic->ic_curmode == IEEE80211_MODE_11B || 1344 (sc->sc_sc.sc_flags & RTWN_FLAG_FORCE_RAID_11B)) 1345 raid = R92C_RAID_11B; 1346 else 1347 raid = R92C_RAID_11BG; 1348 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1349 txd->txdw1 |= htole32( 1350 SM(R88E_TXDW1_MACID, R92C_MACID_BSS) | 1351 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1352 SM(R92C_TXDW1_RAID, raid)); 1353 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1354 /* Request TX status report for AMRR */ 1355 txd->txdw2 |= htole32(R92C_TXDW2_CCX_RPT); 1356 } else { 1357 txd->txdw1 |= htole32( 1358 SM(R92C_TXDW1_MACID, R92C_MACID_BSS) | 1359 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1360 SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1361 } 1362 1363 if (m->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 1364 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1365 R92C_TXDW4_HWRTSEN); 1366 } else if (ic->ic_flags & IEEE80211_F_USEPROT) { 1367 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1368 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1369 R92C_TXDW4_HWRTSEN); 1370 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1371 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1372 R92C_TXDW4_HWRTSEN); 1373 } 1374 } 1375 txd->txdw5 |= htole32(0x0001ff00); 1376 1377 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1378 /* Use AMRR */ 1379 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1380 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 1381 ni->ni_txrate)); 1382 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1383 ni->ni_txrate)); 1384 } else { 1385 /* Send RTS at OFDM24 and data at OFDM54. */ 1386 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1387 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1388 } 1389 } else { 1390 txd->txdw1 |= htole32( 1391 SM(R92C_TXDW1_MACID, 0) | 1392 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1393 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1394 1395 /* Force CCK1. */ 1396 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1397 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1398 } 1399 /* Set sequence number (already little endian). */ 1400 txd->txdseq |= *(uint16_t *)wh->i_seq; 1401 1402 if (!hasqos) { 1403 /* Use HW sequence numbering for non-QoS frames. */ 1404 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1405 txd->txdseq |= htole16(0x8000); /* WTF? */ 1406 } else 1407 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1408 1409 /* Compute Tx descriptor checksum. */ 1410 sum = 0; 1411 for (i = 0; i < sizeof(*txd) / 2; i++) 1412 sum ^= ((uint16_t *)txd)[i]; 1413 txd->txdsum = sum; /* NB: already little endian. */ 1414 1415 #if NBPFILTER > 0 1416 if (__predict_false(sc->sc_drvbpf != NULL)) { 1417 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1418 struct mbuf mb; 1419 1420 tap->wt_flags = 0; 1421 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1422 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1423 1424 mb.m_data = (caddr_t)tap; 1425 mb.m_len = sc->sc_txtap_len; 1426 mb.m_next = m; 1427 mb.m_nextpkt = NULL; 1428 mb.m_type = 0; 1429 mb.m_flags = 0; 1430 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1431 } 1432 #endif 1433 1434 xferlen = sizeof(*txd) + m->m_pkthdr.len; 1435 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]); 1436 m_freem(m); 1437 1438 data->pipe = pipe; 1439 usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen, 1440 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTWN_TX_TIMEOUT, 1441 urtwn_txeof); 1442 error = usbd_transfer(data->xfer); 1443 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) { 1444 /* Put this Tx buffer back to our free list. */ 1445 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1446 return (error); 1447 } 1448 ieee80211_release_node(ic, ni); 1449 return (0); 1450 } 1451 1452 int 1453 urtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1454 { 1455 struct rtwn_softc *sc_sc = ifp->if_softc; 1456 struct device *self = sc_sc->sc_pdev; 1457 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1458 int error; 1459 1460 if (usbd_is_dying(sc->sc_udev)) 1461 return ENXIO; 1462 1463 usbd_ref_incr(sc->sc_udev); 1464 error = rtwn_ioctl(ifp, cmd, data); 1465 usbd_ref_decr(sc->sc_udev); 1466 1467 return (error); 1468 } 1469 1470 int 1471 urtwn_r92c_power_on(struct urtwn_softc *sc) 1472 { 1473 uint32_t reg; 1474 int ntries; 1475 1476 /* Wait for autoload done bit. */ 1477 for (ntries = 0; ntries < 1000; ntries++) { 1478 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 1479 break; 1480 DELAY(5); 1481 } 1482 if (ntries == 1000) { 1483 printf("%s: timeout waiting for chip autoload\n", 1484 sc->sc_dev.dv_xname); 1485 return (ETIMEDOUT); 1486 } 1487 1488 /* Unlock ISO/CLK/Power control register. */ 1489 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 1490 /* Move SPS into PWM mode. */ 1491 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 1492 DELAY(100); 1493 1494 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 1495 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 1496 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 1497 reg | R92C_LDOV12D_CTRL_LDV12_EN); 1498 DELAY(100); 1499 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 1500 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 1501 ~R92C_SYS_ISO_CTRL_MD2PP); 1502 } 1503 1504 /* Auto enable WLAN. */ 1505 urtwn_write_2(sc, R92C_APS_FSMCO, 1506 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1507 for (ntries = 0; ntries < 1000; ntries++) { 1508 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1509 R92C_APS_FSMCO_APFM_ONMAC)) 1510 break; 1511 DELAY(5); 1512 } 1513 if (ntries == 1000) { 1514 printf("%s: timeout waiting for MAC auto ON\n", 1515 sc->sc_dev.dv_xname); 1516 return (ETIMEDOUT); 1517 } 1518 1519 /* Enable radio, GPIO and LED functions. */ 1520 urtwn_write_2(sc, R92C_APS_FSMCO, 1521 R92C_APS_FSMCO_AFSM_HSUS | 1522 R92C_APS_FSMCO_PDN_EN | 1523 R92C_APS_FSMCO_PFM_ALDN); 1524 /* Release RF digital isolation. */ 1525 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1526 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 1527 1528 /* Initialize MAC. */ 1529 urtwn_write_1(sc, R92C_APSD_CTRL, 1530 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 1531 for (ntries = 0; ntries < 200; ntries++) { 1532 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 1533 R92C_APSD_CTRL_OFF_STATUS)) 1534 break; 1535 DELAY(5); 1536 } 1537 if (ntries == 200) { 1538 printf("%s: timeout waiting for MAC initialization\n", 1539 sc->sc_dev.dv_xname); 1540 return (ETIMEDOUT); 1541 } 1542 1543 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1544 reg = urtwn_read_2(sc, R92C_CR); 1545 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1546 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1547 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 1548 R92C_CR_ENSEC; 1549 urtwn_write_2(sc, R92C_CR, reg); 1550 1551 urtwn_write_1(sc, 0xfe10, 0x19); 1552 return (0); 1553 } 1554 1555 int 1556 urtwn_r88e_power_on(struct urtwn_softc *sc) 1557 { 1558 uint32_t reg; 1559 int ntries; 1560 1561 /* Wait for power ready bit. */ 1562 for (ntries = 0; ntries < 5000; ntries++) { 1563 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 1564 break; 1565 DELAY(10); 1566 } 1567 if (ntries == 5000) { 1568 printf("%s: timeout waiting for chip power up\n", 1569 sc->sc_dev.dv_xname); 1570 return (ETIMEDOUT); 1571 } 1572 1573 /* Reset BB. */ 1574 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 1575 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 1576 R92C_SYS_FUNC_EN_BB_GLB_RST)); 1577 1578 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 1579 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 1580 1581 /* Disable HWPDN. */ 1582 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 1583 urtwn_write_2(sc, R92C_APS_FSMCO, 1584 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 1585 1586 /* Disable WL suspend. */ 1587 urtwn_write_2(sc, R92C_APS_FSMCO, 1588 urtwn_read_2(sc, R92C_APS_FSMCO) & 1589 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 1590 1591 urtwn_write_2(sc, R92C_APS_FSMCO, 1592 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1593 for (ntries = 0; ntries < 5000; ntries++) { 1594 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1595 R92C_APS_FSMCO_APFM_ONMAC)) 1596 break; 1597 DELAY(10); 1598 } 1599 if (ntries == 5000) 1600 return (ETIMEDOUT); 1601 1602 /* Enable LDO normal mode. */ 1603 urtwn_write_1(sc, R92C_LPLDO_CTRL, 1604 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 1605 1606 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1607 urtwn_write_2(sc, R92C_CR, 0); 1608 reg = urtwn_read_2(sc, R92C_CR); 1609 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1610 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1611 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 1612 urtwn_write_2(sc, R92C_CR, reg); 1613 1614 return (0); 1615 } 1616 1617 int 1618 urtwn_llt_init(struct urtwn_softc *sc) 1619 { 1620 int i, error, page_count, pktbuf_count; 1621 1622 page_count = (sc->sc_sc.chip & RTWN_CHIP_88E) ? 1623 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 1624 pktbuf_count = (sc->sc_sc.chip & RTWN_CHIP_88E) ? 1625 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 1626 1627 /* Reserve pages [0; page_count]. */ 1628 for (i = 0; i < page_count; i++) { 1629 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1630 return (error); 1631 } 1632 /* NB: 0xff indicates end-of-list. */ 1633 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 1634 return (error); 1635 /* 1636 * Use pages [page_count + 1; pktbuf_count - 1] 1637 * as ring buffer. 1638 */ 1639 for (++i; i < pktbuf_count - 1; i++) { 1640 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1641 return (error); 1642 } 1643 /* Make the last page point to the beginning of the ring buffer. */ 1644 error = urtwn_llt_write(sc, i, page_count + 1); 1645 return (error); 1646 } 1647 1648 int 1649 urtwn_fw_loadpage(void *cookie, int page, uint8_t *buf, int len) 1650 { 1651 struct urtwn_softc *sc = cookie; 1652 uint32_t reg; 1653 int off, mlen, error = 0; 1654 1655 reg = urtwn_read_4(sc, R92C_MCUFWDL); 1656 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 1657 urtwn_write_4(sc, R92C_MCUFWDL, reg); 1658 1659 off = R92C_FW_START_ADDR; 1660 while (len > 0) { 1661 if (len > 196) 1662 mlen = 196; 1663 else if (len > 4) 1664 mlen = 4; 1665 else 1666 mlen = 1; 1667 error = urtwn_write_region_1(sc, off, buf, mlen); 1668 if (error != 0) 1669 break; 1670 off += mlen; 1671 buf += mlen; 1672 len -= mlen; 1673 } 1674 return (error); 1675 } 1676 1677 int 1678 urtwn_load_firmware(void *cookie, u_char **fw, size_t *len) 1679 { 1680 struct urtwn_softc *sc = cookie; 1681 const char *name; 1682 int error; 1683 1684 if (sc->sc_sc.chip & RTWN_CHIP_88E) 1685 name = "urtwn-rtl8188eufw"; 1686 else if ((sc->sc_sc.chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 1687 RTWN_CHIP_UMC_A_CUT) 1688 name = "urtwn-rtl8192cfwU"; 1689 else 1690 name = "urtwn-rtl8192cfwT"; 1691 1692 error = loadfirmware(name, fw, len); 1693 if (error) 1694 printf("%s: could not read firmware %s (error %d)\n", 1695 sc->sc_dev.dv_xname, name, error); 1696 return (error); 1697 } 1698 1699 int 1700 urtwn_dma_init(void *cookie) 1701 { 1702 struct urtwn_softc *sc = cookie; 1703 1704 if (sc->sc_sc.chip & RTWN_CHIP_88E) 1705 return urtwn_r88e_dma_init(sc); 1706 1707 return urtwn_r92c_dma_init(sc); 1708 } 1709 1710 int 1711 urtwn_r92c_dma_init(struct urtwn_softc *sc) 1712 { 1713 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 1714 uint32_t reg; 1715 int error; 1716 1717 /* Initialize LLT table. */ 1718 error = urtwn_llt_init(sc); 1719 if (error != 0) 1720 return (error); 1721 1722 /* Get Tx queues to USB endpoints mapping. */ 1723 hashq = hasnq = haslq = 0; 1724 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 1725 DPRINTFN(2, ("USB endpoints mapping 0x%x\n", reg)); 1726 if (MS(reg, R92C_USB_EP_HQ) != 0) 1727 hashq = 1; 1728 if (MS(reg, R92C_USB_EP_NQ) != 0) 1729 hasnq = 1; 1730 if (MS(reg, R92C_USB_EP_LQ) != 0) 1731 haslq = 1; 1732 nqueues = hashq + hasnq + haslq; 1733 if (nqueues == 0) 1734 return (EIO); 1735 /* Get the number of pages for each queue. */ 1736 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 1737 /* The remaining pages are assigned to the high priority queue. */ 1738 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 1739 1740 /* Set number of pages for normal priority queue. */ 1741 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 1742 urtwn_write_4(sc, R92C_RQPN, 1743 /* Set number of pages for public queue. */ 1744 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 1745 /* Set number of pages for high priority queue. */ 1746 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 1747 /* Set number of pages for low priority queue. */ 1748 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 1749 /* Load values. */ 1750 R92C_RQPN_LD); 1751 1752 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 1753 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 1754 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 1755 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 1756 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 1757 1758 /* Set queue to USB pipe mapping. */ 1759 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 1760 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 1761 if (nqueues == 1) { 1762 if (hashq) 1763 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 1764 else if (hasnq) 1765 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 1766 else 1767 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 1768 } else if (nqueues == 2) { 1769 /* All 2-endpoints configs have a high priority queue. */ 1770 if (!hashq) 1771 return (EIO); 1772 if (hasnq) 1773 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 1774 else 1775 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 1776 } else 1777 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 1778 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 1779 1780 /* Set Tx/Rx transfer page boundary. */ 1781 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 1782 1783 /* Set Tx/Rx transfer page size. */ 1784 urtwn_write_1(sc, R92C_PBP, 1785 SM(R92C_PBP_PSRX, R92C_PBP_128) | 1786 SM(R92C_PBP_PSTX, R92C_PBP_128)); 1787 return (0); 1788 } 1789 1790 int 1791 urtwn_r88e_dma_init(struct urtwn_softc *sc) 1792 { 1793 usb_interface_descriptor_t *id; 1794 uint32_t reg; 1795 int nqueues = 1; 1796 int error; 1797 1798 /* Initialize LLT table. */ 1799 error = urtwn_llt_init(sc); 1800 if (error != 0) 1801 return (error); 1802 1803 /* Get Tx queues to USB endpoints mapping. */ 1804 id = usbd_get_interface_descriptor(sc->sc_iface); 1805 nqueues = id->bNumEndpoints - 1; 1806 1807 /* Set number of pages for normal priority queue. */ 1808 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 1809 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 1810 1811 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 1812 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 1813 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 1814 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 1815 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 1816 1817 /* Set queue to USB pipe mapping. */ 1818 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 1819 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 1820 if (nqueues == 1) 1821 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 1822 else if (nqueues == 2) 1823 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 1824 else 1825 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 1826 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 1827 1828 /* Set Tx/Rx transfer page boundary. */ 1829 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 1830 1831 /* Set Tx/Rx transfer page size. */ 1832 urtwn_write_1(sc, R92C_PBP, 1833 SM(R92C_PBP_PSRX, R92C_PBP_128) | 1834 SM(R92C_PBP_PSTX, R92C_PBP_128)); 1835 1836 return (0); 1837 } 1838 1839 void 1840 urtwn_mac_init(void *cookie) 1841 { 1842 struct urtwn_softc *sc = cookie; 1843 int i; 1844 1845 /* Write MAC initialization values. */ 1846 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1847 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 1848 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 1849 rtl8188eu_mac[i].val); 1850 } 1851 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 1852 } else { 1853 for (i = 0; i < nitems(rtl8192cu_mac); i++) 1854 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 1855 rtl8192cu_mac[i].val); 1856 } 1857 } 1858 1859 void 1860 urtwn_bb_init(void *cookie) 1861 { 1862 struct urtwn_softc *sc = cookie; 1863 const struct r92c_bb_prog *prog; 1864 uint32_t reg; 1865 uint8_t crystalcap; 1866 int i; 1867 1868 /* Enable BB and RF. */ 1869 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1870 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 1871 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 1872 R92C_SYS_FUNC_EN_DIO_RF); 1873 1874 if (!(sc->sc_sc.chip & RTWN_CHIP_88E)) 1875 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 1876 1877 urtwn_write_1(sc, R92C_RF_CTRL, 1878 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 1879 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 1880 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 1881 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 1882 1883 if (!(sc->sc_sc.chip & RTWN_CHIP_88E)) { 1884 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 1885 urtwn_write_1(sc, 0x15, 0xe9); 1886 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 1887 } 1888 1889 /* Select BB programming based on board type. */ 1890 if (sc->sc_sc.chip & RTWN_CHIP_88E) 1891 prog = &rtl8188eu_bb_prog; 1892 else if (!(sc->sc_sc.chip & RTWN_CHIP_92C)) { 1893 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD) 1894 prog = &rtl8188ce_bb_prog; 1895 else if (sc->sc_sc.board_type == R92C_BOARD_TYPE_HIGHPA) 1896 prog = &rtl8188ru_bb_prog; 1897 else 1898 prog = &rtl8188cu_bb_prog; 1899 } else { 1900 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD) 1901 prog = &rtl8192ce_bb_prog; 1902 else 1903 prog = &rtl8192cu_bb_prog; 1904 } 1905 /* Write BB initialization values. */ 1906 for (i = 0; i < prog->count; i++) { 1907 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 1908 DELAY(1); 1909 } 1910 1911 if (sc->sc_sc.chip & RTWN_CHIP_92C_1T2R) { 1912 /* 8192C 1T only configuration. */ 1913 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 1914 reg = (reg & ~0x00000003) | 0x2; 1915 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 1916 1917 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 1918 reg = (reg & ~0x00300033) | 0x00200022; 1919 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 1920 1921 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 1922 reg = (reg & ~0xff000000) | 0x45 << 24; 1923 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 1924 1925 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 1926 reg = (reg & ~0x000000ff) | 0x23; 1927 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 1928 1929 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 1930 reg = (reg & ~0x00000030) | 1 << 4; 1931 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 1932 1933 reg = urtwn_bb_read(sc, 0xe74); 1934 reg = (reg & ~0x0c000000) | 2 << 26; 1935 urtwn_bb_write(sc, 0xe74, reg); 1936 reg = urtwn_bb_read(sc, 0xe78); 1937 reg = (reg & ~0x0c000000) | 2 << 26; 1938 urtwn_bb_write(sc, 0xe78, reg); 1939 reg = urtwn_bb_read(sc, 0xe7c); 1940 reg = (reg & ~0x0c000000) | 2 << 26; 1941 urtwn_bb_write(sc, 0xe7c, reg); 1942 reg = urtwn_bb_read(sc, 0xe80); 1943 reg = (reg & ~0x0c000000) | 2 << 26; 1944 urtwn_bb_write(sc, 0xe80, reg); 1945 reg = urtwn_bb_read(sc, 0xe88); 1946 reg = (reg & ~0x0c000000) | 2 << 26; 1947 urtwn_bb_write(sc, 0xe88, reg); 1948 } 1949 1950 /* Write AGC values. */ 1951 for (i = 0; i < prog->agccount; i++) { 1952 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 1953 prog->agcvals[i]); 1954 DELAY(1); 1955 } 1956 1957 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1958 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 1959 DELAY(1); 1960 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 1961 DELAY(1); 1962 1963 crystalcap = sc->sc_sc.r88e_rom[0xb9]; 1964 if (crystalcap == 0xff) 1965 crystalcap = 0x20; 1966 crystalcap &= 0x3f; 1967 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 1968 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 1969 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 1970 crystalcap | crystalcap << 6)); 1971 } else { 1972 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 1973 R92C_HSSI_PARAM2_CCK_HIPWR) 1974 sc->sc_sc.sc_flags |= RTWN_FLAG_CCK_HIPWR; 1975 } 1976 } 1977 1978 int 1979 urtwn_power_on(void *cookie) 1980 { 1981 struct urtwn_softc *sc = cookie; 1982 1983 if (sc->sc_sc.chip & RTWN_CHIP_88E) 1984 return urtwn_r88e_power_on(sc); 1985 1986 return urtwn_r92c_power_on(sc); 1987 } 1988 1989 int 1990 urtwn_alloc_buffers(void *cookie) 1991 { 1992 struct urtwn_softc *sc = cookie; 1993 int error; 1994 1995 /* Init host async commands ring. */ 1996 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 1997 1998 /* Allocate Tx/Rx buffers. */ 1999 error = urtwn_alloc_rx_list(sc); 2000 if (error != 0) { 2001 printf("%s: could not allocate Rx buffers\n", 2002 sc->sc_dev.dv_xname); 2003 return (error); 2004 } 2005 error = urtwn_alloc_tx_list(sc); 2006 if (error != 0) { 2007 printf("%s: could not allocate Tx buffers\n", 2008 sc->sc_dev.dv_xname); 2009 return (error); 2010 } 2011 2012 return (0); 2013 } 2014 2015 int 2016 urtwn_init(void *cookie) 2017 { 2018 struct urtwn_softc *sc = cookie; 2019 int i, error; 2020 2021 /* Queue Rx xfers. */ 2022 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 2023 struct urtwn_rx_data *data = &sc->rx_data[i]; 2024 2025 usbd_setup_xfer(data->xfer, sc->rx_pipe, data, data->buf, 2026 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 2027 USBD_NO_TIMEOUT, urtwn_rxeof); 2028 error = usbd_transfer(data->xfer); 2029 if (error != 0 && error != USBD_IN_PROGRESS) 2030 return (error); 2031 } 2032 2033 ieee80211_amrr_node_init(&sc->amrr, &sc->amn); 2034 2035 /* 2036 * Enable TX reports for AMRR. 2037 * In order to get reports we need to explicitly reset the register. 2038 */ 2039 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2040 urtwn_write_1(sc, R88E_TX_RPT_CTRL, (urtwn_read_1(sc, 2041 R88E_TX_RPT_CTRL) & ~0) | R88E_TX_RPT1_ENA); 2042 2043 return (0); 2044 } 2045 2046 void 2047 urtwn_stop(void *cookie) 2048 { 2049 struct urtwn_softc *sc = cookie; 2050 int i; 2051 2052 /* Abort Tx. */ 2053 for (i = 0; i < R92C_MAX_EPOUT; i++) { 2054 if (sc->tx_pipe[i] != NULL) 2055 usbd_abort_pipe(sc->tx_pipe[i]); 2056 } 2057 /* Stop Rx pipe. */ 2058 usbd_abort_pipe(sc->rx_pipe); 2059 /* Free Tx/Rx buffers. */ 2060 urtwn_free_tx_list(sc); 2061 urtwn_free_rx_list(sc); 2062 } 2063 2064 int 2065 urtwn_is_oactive(void *cookie) 2066 { 2067 struct urtwn_softc *sc = cookie; 2068 2069 return (TAILQ_EMPTY(&sc->tx_free_list)); 2070 } 2071