1 /* $OpenBSD: if_urtwn.c,v 1.79 2018/10/01 11:03:46 jmatthew Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 22 */ 23 24 #include "bpfilter.h" 25 26 #include <sys/param.h> 27 #include <sys/sockio.h> 28 #include <sys/mbuf.h> 29 #include <sys/kernel.h> 30 #include <sys/socket.h> 31 #include <sys/systm.h> 32 #include <sys/timeout.h> 33 #include <sys/conf.h> 34 #include <sys/device.h> 35 #include <sys/endian.h> 36 37 #include <machine/intr.h> 38 39 #if NBPFILTER > 0 40 #include <net/bpf.h> 41 #endif 42 #include <net/if.h> 43 #include <net/if_dl.h> 44 #include <net/if_media.h> 45 46 #include <netinet/in.h> 47 #include <netinet/if_ether.h> 48 49 #include <net80211/ieee80211_var.h> 50 #include <net80211/ieee80211_amrr.h> 51 #include <net80211/ieee80211_radiotap.h> 52 53 #include <dev/usb/usb.h> 54 #include <dev/usb/usbdi.h> 55 #include <dev/usb/usbdi_util.h> 56 #include <dev/usb/usbdevs.h> 57 58 #include <dev/ic/r92creg.h> 59 #include <dev/ic/rtwnvar.h> 60 61 /* Maximum number of output pipes is 3. */ 62 #define R92C_MAX_EPOUT 3 63 64 #define R92C_HQ_NPAGES 12 65 #define R92C_LQ_NPAGES 2 66 #define R92C_NQ_NPAGES 2 67 #define R92C_TXPKTBUF_COUNT 256 68 #define R92C_TX_PAGE_COUNT 248 69 #define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) 70 #define R92C_MAX_RX_DMA_SIZE 0x2800 71 #define R88E_HQ_NPAGES 0 72 #define R88E_LQ_NPAGES 9 73 #define R88E_NQ_NPAGES 0 74 #define R88E_TXPKTBUF_COUNT 177 75 #define R88E_TX_PAGE_COUNT 168 76 #define R88E_TX_PAGE_BOUNDARY (R88E_TX_PAGE_COUNT + 1) 77 #define R88E_MAX_RX_DMA_SIZE 0x2400 78 79 /* USB Requests. */ 80 #define R92C_REQ_REGS 0x05 81 82 /* 83 * Driver definitions. 84 */ 85 #define URTWN_RX_LIST_COUNT 1 86 #define URTWN_TX_LIST_COUNT 8 87 #define URTWN_HOST_CMD_RING_COUNT 32 88 89 #define URTWN_RXBUFSZ (16 * 1024) 90 #define URTWN_TXBUFSZ (sizeof(struct r92c_tx_desc_usb) + IEEE80211_MAX_LEN) 91 92 #define URTWN_RIDX_COUNT 28 93 94 #define URTWN_TX_TIMEOUT 5000 /* ms */ 95 96 #define URTWN_LED_LINK 0 97 #define URTWN_LED_DATA 1 98 99 struct urtwn_rx_radiotap_header { 100 struct ieee80211_radiotap_header wr_ihdr; 101 uint8_t wr_flags; 102 uint8_t wr_rate; 103 uint16_t wr_chan_freq; 104 uint16_t wr_chan_flags; 105 uint8_t wr_dbm_antsignal; 106 } __packed; 107 108 #define URTWN_RX_RADIOTAP_PRESENT \ 109 (1 << IEEE80211_RADIOTAP_FLAGS | \ 110 1 << IEEE80211_RADIOTAP_RATE | \ 111 1 << IEEE80211_RADIOTAP_CHANNEL | \ 112 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) 113 114 struct urtwn_tx_radiotap_header { 115 struct ieee80211_radiotap_header wt_ihdr; 116 uint8_t wt_flags; 117 uint16_t wt_chan_freq; 118 uint16_t wt_chan_flags; 119 } __packed; 120 121 #define URTWN_TX_RADIOTAP_PRESENT \ 122 (1 << IEEE80211_RADIOTAP_FLAGS | \ 123 1 << IEEE80211_RADIOTAP_CHANNEL) 124 125 struct urtwn_softc; 126 127 struct urtwn_rx_data { 128 struct urtwn_softc *sc; 129 struct usbd_xfer *xfer; 130 uint8_t *buf; 131 }; 132 133 struct urtwn_tx_data { 134 struct urtwn_softc *sc; 135 struct usbd_pipe *pipe; 136 struct usbd_xfer *xfer; 137 uint8_t *buf; 138 TAILQ_ENTRY(urtwn_tx_data) next; 139 }; 140 141 struct urtwn_host_cmd { 142 void (*cb)(struct urtwn_softc *, void *); 143 uint8_t data[256]; 144 }; 145 146 struct urtwn_cmd_newstate { 147 enum ieee80211_state state; 148 int arg; 149 }; 150 151 struct urtwn_cmd_key { 152 struct ieee80211_key key; 153 struct ieee80211_node *ni; 154 }; 155 156 struct urtwn_host_cmd_ring { 157 struct urtwn_host_cmd cmd[URTWN_HOST_CMD_RING_COUNT]; 158 int cur; 159 int next; 160 int queued; 161 }; 162 163 struct urtwn_softc { 164 struct device sc_dev; 165 struct rtwn_softc sc_sc; 166 167 struct usbd_device *sc_udev; 168 struct usbd_interface *sc_iface; 169 struct usb_task sc_task; 170 171 struct timeout scan_to; 172 struct timeout calib_to; 173 174 int ntx; 175 struct usbd_pipe *rx_pipe; 176 struct usbd_pipe *tx_pipe[R92C_MAX_EPOUT]; 177 int ac2idx[EDCA_NUM_AC]; 178 179 struct urtwn_host_cmd_ring cmdq; 180 struct urtwn_rx_data rx_data[URTWN_RX_LIST_COUNT]; 181 struct urtwn_tx_data tx_data[URTWN_TX_LIST_COUNT]; 182 TAILQ_HEAD(, urtwn_tx_data) tx_free_list; 183 184 struct ieee80211_amrr amrr; 185 struct ieee80211_amrr_node amn; 186 187 #if NBPFILTER > 0 188 caddr_t sc_drvbpf; 189 190 union { 191 struct urtwn_rx_radiotap_header th; 192 uint8_t pad[64]; 193 } sc_rxtapu; 194 #define sc_rxtap sc_rxtapu.th 195 int sc_rxtap_len; 196 197 union { 198 struct urtwn_tx_radiotap_header th; 199 uint8_t pad[64]; 200 } sc_txtapu; 201 #define sc_txtap sc_txtapu.th 202 int sc_txtap_len; 203 #endif 204 }; 205 206 #ifdef URTWN_DEBUG 207 #define DPRINTF(x) do { if (urtwn_debug) printf x; } while (0) 208 #define DPRINTFN(n, x) do { if (urtwn_debug >= (n)) printf x; } while (0) 209 int urtwn_debug = 4; 210 #else 211 #define DPRINTF(x) 212 #define DPRINTFN(n, x) 213 #endif 214 215 /* 216 * Various supported device vendors/products. 217 */ 218 #define URTWN_DEV(v, p, f) \ 219 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, (f) | RTWN_CHIP_USB } 220 #define URTWN_DEV_8192CU(v, p) URTWN_DEV(v, p, RTWN_CHIP_92C | RTWN_CHIP_88C) 221 #define URTWN_DEV_8188EU(v, p) URTWN_DEV(v, p, RTWN_CHIP_88E) 222 static const struct urtwn_type { 223 struct usb_devno dev; 224 uint32_t chip; 225 } urtwn_devs[] = { 226 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_1), 227 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_1), 228 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_2), 229 URTWN_DEV_8192CU(ABOCOM, RTL8192CU), 230 URTWN_DEV_8192CU(ASUS, RTL8192CU), 231 URTWN_DEV_8192CU(ASUS, RTL8192CU_2), 232 URTWN_DEV_8192CU(ASUS, RTL8192CU_3), 233 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CE_1), 234 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CE_2), 235 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CU), 236 URTWN_DEV_8192CU(BELKIN, F7D2102), 237 URTWN_DEV_8192CU(BELKIN, F9L1004V1), 238 URTWN_DEV_8192CU(BELKIN, RTL8188CU), 239 URTWN_DEV_8192CU(BELKIN, RTL8188CUS), 240 URTWN_DEV_8192CU(BELKIN, RTL8192CU), 241 URTWN_DEV_8192CU(BELKIN, RTL8192CU_1), 242 URTWN_DEV_8192CU(BELKIN, RTL8192CU_2), 243 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_1), 244 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_2), 245 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_3), 246 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_4), 247 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_5), 248 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_6), 249 URTWN_DEV_8192CU(COMPARE, RTL8192CU), 250 URTWN_DEV_8192CU(COREGA, RTL8192CU), 251 URTWN_DEV_8192CU(DLINK, DWA131B), 252 URTWN_DEV_8192CU(DLINK, RTL8188CU), 253 URTWN_DEV_8192CU(DLINK, RTL8192CU_1), 254 URTWN_DEV_8192CU(DLINK, RTL8192CU_2), 255 URTWN_DEV_8192CU(DLINK, RTL8192CU_3), 256 URTWN_DEV_8192CU(DLINK, RTL8192CU_4), 257 URTWN_DEV_8192CU(EDIMAX, EW7811UN), 258 URTWN_DEV_8192CU(EDIMAX, RTL8192CU), 259 URTWN_DEV_8192CU(FEIXUN, RTL8188CU), 260 URTWN_DEV_8192CU(FEIXUN, RTL8192CU), 261 URTWN_DEV_8192CU(GUILLEMOT, HWNUP150), 262 URTWN_DEV_8192CU(GUILLEMOT, RTL8192CU), 263 URTWN_DEV_8192CU(HAWKING, RTL8192CU), 264 URTWN_DEV_8192CU(HAWKING, RTL8192CU_2), 265 URTWN_DEV_8192CU(HP3, RTL8188CU), 266 URTWN_DEV_8192CU(IODATA, WNG150UM), 267 URTWN_DEV_8192CU(IODATA, RTL8192CU), 268 URTWN_DEV_8192CU(NETGEAR, N300MA), 269 URTWN_DEV_8192CU(NETGEAR, WNA1000M), 270 URTWN_DEV_8192CU(NETGEAR, WNA1000Mv2), 271 URTWN_DEV_8192CU(NETGEAR, RTL8192CU), 272 URTWN_DEV_8192CU(NETGEAR4, RTL8188CU), 273 URTWN_DEV_8192CU(NETWEEN, RTL8192CU), 274 URTWN_DEV_8192CU(NOVATECH, RTL8188CU), 275 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_1), 276 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_2), 277 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_3), 278 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_4), 279 URTWN_DEV_8192CU(PLANEX2, RTL8188CUS), 280 URTWN_DEV_8192CU(PLANEX2, RTL8192CU), 281 URTWN_DEV_8192CU(REALTEK, RTL8188CE_0), 282 URTWN_DEV_8192CU(REALTEK, RTL8188CE_1), 283 URTWN_DEV_8192CU(REALTEK, RTL8188CTV), 284 URTWN_DEV_8192CU(REALTEK, RTL8188CU_0), 285 URTWN_DEV_8192CU(REALTEK, RTL8188CU_1), 286 URTWN_DEV_8192CU(REALTEK, RTL8188CU_2), 287 URTWN_DEV_8192CU(REALTEK, RTL8188CU_3), 288 URTWN_DEV_8192CU(REALTEK, RTL8188CU_4), 289 URTWN_DEV_8192CU(REALTEK, RTL8188CU_5), 290 URTWN_DEV_8192CU(REALTEK, RTL8188CU_COMBO), 291 URTWN_DEV_8192CU(REALTEK, RTL8188CUS), 292 URTWN_DEV_8192CU(REALTEK, RTL8188RU), 293 URTWN_DEV_8192CU(REALTEK, RTL8188RU_2), 294 URTWN_DEV_8192CU(REALTEK, RTL8188RU_3), 295 URTWN_DEV_8192CU(REALTEK, RTL8191CU), 296 URTWN_DEV_8192CU(REALTEK, RTL8192CE), 297 URTWN_DEV_8192CU(REALTEK, RTL8192CE_VAU), 298 URTWN_DEV_8192CU(REALTEK, RTL8192CU), 299 URTWN_DEV_8192CU(SITECOMEU, RTL8188CU), 300 URTWN_DEV_8192CU(SITECOMEU, RTL8188CU_2), 301 URTWN_DEV_8192CU(SITECOMEU, RTL8192CU), 302 URTWN_DEV_8192CU(SITECOMEU, RTL8192CU_2), 303 URTWN_DEV_8192CU(SITECOMEU, WLA2100V2), 304 URTWN_DEV_8192CU(TPLINK, RTL8192CU), 305 URTWN_DEV_8192CU(TRENDNET, RTL8188CU), 306 URTWN_DEV_8192CU(TRENDNET, RTL8192CU), 307 URTWN_DEV_8192CU(ZYXEL, RTL8192CU), 308 /* URTWN_RTL8188E */ 309 URTWN_DEV_8188EU(ABOCOM, RTL8188EU), 310 URTWN_DEV_8188EU(DLINK, DWA123D1), 311 URTWN_DEV_8188EU(DLINK, DWA125D1), 312 URTWN_DEV_8188EU(ELECOM, WDC150SU2M), 313 URTWN_DEV_8188EU(REALTEK, RTL8188ETV), 314 URTWN_DEV_8188EU(REALTEK, RTL8188EU), 315 URTWN_DEV_8188EU(TPLINK, RTL8188EUS) 316 }; 317 318 #define urtwn_lookup(v, p) \ 319 ((const struct urtwn_type *)usb_lookup(urtwn_devs, v, p)) 320 321 int urtwn_match(struct device *, void *, void *); 322 void urtwn_attach(struct device *, struct device *, void *); 323 int urtwn_detach(struct device *, int); 324 int urtwn_open_pipes(struct urtwn_softc *); 325 void urtwn_close_pipes(struct urtwn_softc *); 326 int urtwn_alloc_rx_list(struct urtwn_softc *); 327 void urtwn_free_rx_list(struct urtwn_softc *); 328 int urtwn_alloc_tx_list(struct urtwn_softc *); 329 void urtwn_free_tx_list(struct urtwn_softc *); 330 void urtwn_task(void *); 331 void urtwn_do_async(struct urtwn_softc *, 332 void (*)(struct urtwn_softc *, void *), void *, int); 333 void urtwn_wait_async(void *); 334 int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 335 int); 336 void urtwn_write_1(void *, uint16_t, uint8_t); 337 void urtwn_write_2(void *, uint16_t, uint16_t); 338 void urtwn_write_4(void *, uint16_t, uint32_t); 339 int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 340 int); 341 uint8_t urtwn_read_1(void *, uint16_t); 342 uint16_t urtwn_read_2(void *, uint16_t); 343 uint32_t urtwn_read_4(void *, uint16_t); 344 int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 345 void urtwn_calib_to(void *); 346 void urtwn_calib_cb(struct urtwn_softc *, void *); 347 void urtwn_scan_to(void *); 348 void urtwn_next_scan(void *); 349 void urtwn_cancel_scan(void *); 350 int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 351 int); 352 void urtwn_newstate_cb(struct urtwn_softc *, void *); 353 void urtwn_updateslot(struct ieee80211com *); 354 void urtwn_updateslot_cb(struct urtwn_softc *, void *); 355 void urtwn_updateedca(struct ieee80211com *); 356 void urtwn_updateedca_cb(struct urtwn_softc *, void *); 357 int urtwn_set_key(struct ieee80211com *, struct ieee80211_node *, 358 struct ieee80211_key *); 359 void urtwn_set_key_cb(struct urtwn_softc *, void *); 360 void urtwn_delete_key(struct ieee80211com *, 361 struct ieee80211_node *, struct ieee80211_key *); 362 void urtwn_delete_key_cb(struct urtwn_softc *, void *); 363 void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 364 void urtwn_rxeof(struct usbd_xfer *, void *, 365 usbd_status); 366 void urtwn_txeof(struct usbd_xfer *, void *, 367 usbd_status); 368 int urtwn_tx(void *, struct mbuf *, struct ieee80211_node *); 369 int urtwn_ioctl(struct ifnet *, u_long, caddr_t); 370 int urtwn_power_on(void *); 371 int urtwn_alloc_buffers(void *); 372 int urtwn_r92c_power_on(struct urtwn_softc *); 373 int urtwn_r88e_power_on(struct urtwn_softc *); 374 int urtwn_llt_init(struct urtwn_softc *, int); 375 int urtwn_fw_loadpage(void *, int, uint8_t *, int); 376 int urtwn_load_firmware(void *, u_char **, size_t *); 377 int urtwn_dma_init(void *); 378 void urtwn_mac_init(void *); 379 void urtwn_bb_init(void *); 380 int urtwn_init(void *); 381 void urtwn_stop(void *); 382 int urtwn_is_oactive(void *); 383 void urtwn_next_calib(void *); 384 void urtwn_cancel_calib(void *); 385 386 /* Aliases. */ 387 #define urtwn_bb_write urtwn_write_4 388 #define urtwn_bb_read urtwn_read_4 389 390 struct cfdriver urtwn_cd = { 391 NULL, "urtwn", DV_IFNET 392 }; 393 394 const struct cfattach urtwn_ca = { 395 sizeof(struct urtwn_softc), urtwn_match, urtwn_attach, urtwn_detach 396 }; 397 398 int 399 urtwn_match(struct device *parent, void *match, void *aux) 400 { 401 struct usb_attach_arg *uaa = aux; 402 403 if (uaa->iface == NULL || uaa->configno != 1) 404 return (UMATCH_NONE); 405 406 return ((urtwn_lookup(uaa->vendor, uaa->product) != NULL) ? 407 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 408 } 409 410 void 411 urtwn_attach(struct device *parent, struct device *self, void *aux) 412 { 413 struct urtwn_softc *sc = (struct urtwn_softc *)self; 414 struct usb_attach_arg *uaa = aux; 415 struct ifnet *ifp; 416 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 417 418 sc->sc_udev = uaa->device; 419 sc->sc_iface = uaa->iface; 420 421 sc->sc_sc.chip = urtwn_lookup(uaa->vendor, uaa->product)->chip; 422 423 usb_init_task(&sc->sc_task, urtwn_task, sc, USB_TASK_TYPE_GENERIC); 424 timeout_set(&sc->scan_to, urtwn_scan_to, sc); 425 timeout_set(&sc->calib_to, urtwn_calib_to, sc); 426 if (urtwn_open_pipes(sc) != 0) 427 return; 428 429 sc->amrr.amrr_min_success_threshold = 1; 430 sc->amrr.amrr_max_success_threshold = 10; 431 432 /* Attach the bus-agnostic driver. */ 433 sc->sc_sc.sc_ops.cookie = sc; 434 sc->sc_sc.sc_ops.write_1 = urtwn_write_1; 435 sc->sc_sc.sc_ops.write_2 = urtwn_write_2; 436 sc->sc_sc.sc_ops.write_4 = urtwn_write_4; 437 sc->sc_sc.sc_ops.read_1 = urtwn_read_1; 438 sc->sc_sc.sc_ops.read_2 = urtwn_read_2; 439 sc->sc_sc.sc_ops.read_4 = urtwn_read_4; 440 sc->sc_sc.sc_ops.tx = urtwn_tx; 441 sc->sc_sc.sc_ops.power_on = urtwn_power_on; 442 sc->sc_sc.sc_ops.dma_init = urtwn_dma_init; 443 sc->sc_sc.sc_ops.fw_loadpage = urtwn_fw_loadpage; 444 sc->sc_sc.sc_ops.load_firmware = urtwn_load_firmware; 445 sc->sc_sc.sc_ops.mac_init = urtwn_mac_init; 446 sc->sc_sc.sc_ops.bb_init = urtwn_bb_init; 447 sc->sc_sc.sc_ops.alloc_buffers = urtwn_alloc_buffers; 448 sc->sc_sc.sc_ops.init = urtwn_init; 449 sc->sc_sc.sc_ops.stop = urtwn_stop; 450 sc->sc_sc.sc_ops.is_oactive = urtwn_is_oactive; 451 sc->sc_sc.sc_ops.next_calib = urtwn_next_calib; 452 sc->sc_sc.sc_ops.cancel_calib = urtwn_cancel_calib; 453 sc->sc_sc.sc_ops.next_scan = urtwn_next_scan; 454 sc->sc_sc.sc_ops.cancel_scan = urtwn_cancel_scan; 455 sc->sc_sc.sc_ops.wait_async = urtwn_wait_async; 456 if (rtwn_attach(&sc->sc_dev, &sc->sc_sc) != 0) { 457 urtwn_close_pipes(sc); 458 return; 459 } 460 461 /* ifp is now valid */ 462 ifp = &sc->sc_sc.sc_ic.ic_if; 463 ifp->if_ioctl = urtwn_ioctl; 464 465 ic->ic_updateslot = urtwn_updateslot; 466 ic->ic_updateedca = urtwn_updateedca; 467 #ifdef notyet 468 ic->ic_set_key = urtwn_set_key; 469 ic->ic_delete_key = urtwn_delete_key; 470 #endif 471 /* Override state transition machine. */ 472 ic->ic_newstate = urtwn_newstate; 473 474 #if NBPFILTER > 0 475 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 476 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 477 478 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 479 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 480 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 481 482 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 483 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 484 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 485 #endif 486 } 487 488 int 489 urtwn_detach(struct device *self, int flags) 490 { 491 struct urtwn_softc *sc = (struct urtwn_softc *)self; 492 int s; 493 494 s = splusb(); 495 496 if (timeout_initialized(&sc->scan_to)) 497 timeout_del(&sc->scan_to); 498 if (timeout_initialized(&sc->calib_to)) 499 timeout_del(&sc->calib_to); 500 501 /* Wait for all async commands to complete. */ 502 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 503 504 usbd_ref_wait(sc->sc_udev); 505 506 rtwn_detach(&sc->sc_sc, flags); 507 508 /* Abort and close Tx/Rx pipes. */ 509 urtwn_close_pipes(sc); 510 511 /* Free Tx/Rx buffers. */ 512 urtwn_free_tx_list(sc); 513 urtwn_free_rx_list(sc); 514 splx(s); 515 516 return (0); 517 } 518 519 int 520 urtwn_open_pipes(struct urtwn_softc *sc) 521 { 522 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 523 uint8_t epaddr[R92C_MAX_EPOUT] = { 0, 0, 0 }; 524 uint8_t rx_no; 525 usb_interface_descriptor_t *id; 526 usb_endpoint_descriptor_t *ed; 527 int i, error, nrx = 0; 528 529 /* Find all bulk endpoints. */ 530 id = usbd_get_interface_descriptor(sc->sc_iface); 531 for (i = 0; i < id->bNumEndpoints; i++) { 532 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 533 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) 534 continue; 535 536 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 537 rx_no = ed->bEndpointAddress; 538 nrx++; 539 } else { 540 if (sc->ntx < R92C_MAX_EPOUT) 541 epaddr[sc->ntx] = ed->bEndpointAddress; 542 sc->ntx++; 543 } 544 } 545 if (nrx == 0) { 546 printf("%s: %d: invalid number of Rx bulk pipes\n", 547 sc->sc_dev.dv_xname, nrx); 548 return (EIO); 549 } 550 DPRINTF(("found %d bulk-out pipes\n", sc->ntx)); 551 if (sc->ntx == 0 || sc->ntx > R92C_MAX_EPOUT) { 552 printf("%s: %d: invalid number of Tx bulk pipes\n", 553 sc->sc_dev.dv_xname, sc->ntx); 554 return (EIO); 555 } 556 557 /* Open bulk-in pipe. */ 558 error = usbd_open_pipe(sc->sc_iface, rx_no, 0, &sc->rx_pipe); 559 if (error != 0) { 560 printf("%s: could not open Rx bulk pipe\n", 561 sc->sc_dev.dv_xname); 562 goto fail; 563 } 564 565 /* Open bulk-out pipes (up to 3). */ 566 for (i = 0; i < sc->ntx; i++) { 567 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 0, 568 &sc->tx_pipe[i]); 569 if (error != 0) { 570 printf("%s: could not open Tx bulk pipe 0x%02x\n", 571 sc->sc_dev.dv_xname, epaddr[i]); 572 goto fail; 573 } 574 } 575 576 /* Map 802.11 access categories to USB pipes. */ 577 sc->ac2idx[EDCA_AC_BK] = 578 sc->ac2idx[EDCA_AC_BE] = (sc->ntx == 3) ? 2 : ((sc->ntx == 2) ? 1 : 0); 579 sc->ac2idx[EDCA_AC_VI] = (sc->ntx == 3) ? 1 : 0; 580 sc->ac2idx[EDCA_AC_VO] = 0; /* Always use highest prio. */ 581 582 if (error != 0) 583 fail: urtwn_close_pipes(sc); 584 return (error); 585 } 586 587 void 588 urtwn_close_pipes(struct urtwn_softc *sc) 589 { 590 int i; 591 592 /* Close Rx pipe. */ 593 if (sc->rx_pipe != NULL) { 594 usbd_abort_pipe(sc->rx_pipe); 595 usbd_close_pipe(sc->rx_pipe); 596 } 597 /* Close Tx pipes. */ 598 for (i = 0; i < R92C_MAX_EPOUT; i++) { 599 if (sc->tx_pipe[i] == NULL) 600 continue; 601 usbd_abort_pipe(sc->tx_pipe[i]); 602 usbd_close_pipe(sc->tx_pipe[i]); 603 } 604 } 605 606 int 607 urtwn_alloc_rx_list(struct urtwn_softc *sc) 608 { 609 struct urtwn_rx_data *data; 610 int i, error = 0; 611 612 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 613 data = &sc->rx_data[i]; 614 615 data->sc = sc; /* Backpointer for callbacks. */ 616 617 data->xfer = usbd_alloc_xfer(sc->sc_udev); 618 if (data->xfer == NULL) { 619 printf("%s: could not allocate xfer\n", 620 sc->sc_dev.dv_xname); 621 error = ENOMEM; 622 break; 623 } 624 data->buf = usbd_alloc_buffer(data->xfer, URTWN_RXBUFSZ); 625 if (data->buf == NULL) { 626 printf("%s: could not allocate xfer buffer\n", 627 sc->sc_dev.dv_xname); 628 error = ENOMEM; 629 break; 630 } 631 } 632 if (error != 0) 633 urtwn_free_rx_list(sc); 634 return (error); 635 } 636 637 void 638 urtwn_free_rx_list(struct urtwn_softc *sc) 639 { 640 int i; 641 642 /* NB: Caller must abort pipe first. */ 643 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 644 if (sc->rx_data[i].xfer != NULL) 645 usbd_free_xfer(sc->rx_data[i].xfer); 646 sc->rx_data[i].xfer = NULL; 647 } 648 } 649 650 int 651 urtwn_alloc_tx_list(struct urtwn_softc *sc) 652 { 653 struct urtwn_tx_data *data; 654 int i, error = 0; 655 656 TAILQ_INIT(&sc->tx_free_list); 657 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 658 data = &sc->tx_data[i]; 659 660 data->sc = sc; /* Backpointer for callbacks. */ 661 662 data->xfer = usbd_alloc_xfer(sc->sc_udev); 663 if (data->xfer == NULL) { 664 printf("%s: could not allocate xfer\n", 665 sc->sc_dev.dv_xname); 666 error = ENOMEM; 667 break; 668 } 669 data->buf = usbd_alloc_buffer(data->xfer, URTWN_TXBUFSZ); 670 if (data->buf == NULL) { 671 printf("%s: could not allocate xfer buffer\n", 672 sc->sc_dev.dv_xname); 673 error = ENOMEM; 674 break; 675 } 676 /* Append this Tx buffer to our free list. */ 677 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 678 } 679 if (error != 0) 680 urtwn_free_tx_list(sc); 681 return (error); 682 } 683 684 void 685 urtwn_free_tx_list(struct urtwn_softc *sc) 686 { 687 int i; 688 689 /* NB: Caller must abort pipe first. */ 690 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 691 if (sc->tx_data[i].xfer != NULL) 692 usbd_free_xfer(sc->tx_data[i].xfer); 693 sc->tx_data[i].xfer = NULL; 694 } 695 } 696 697 void 698 urtwn_task(void *arg) 699 { 700 struct urtwn_softc *sc = arg; 701 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 702 struct urtwn_host_cmd *cmd; 703 int s; 704 705 /* Process host commands. */ 706 s = splusb(); 707 while (ring->next != ring->cur) { 708 cmd = &ring->cmd[ring->next]; 709 splx(s); 710 /* Invoke callback. */ 711 cmd->cb(sc, cmd->data); 712 s = splusb(); 713 ring->queued--; 714 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 715 } 716 splx(s); 717 } 718 719 void 720 urtwn_do_async(struct urtwn_softc *sc, 721 void (*cb)(struct urtwn_softc *, void *), void *arg, int len) 722 { 723 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 724 struct urtwn_host_cmd *cmd; 725 int s; 726 727 s = splusb(); 728 cmd = &ring->cmd[ring->cur]; 729 cmd->cb = cb; 730 KASSERT(len <= sizeof(cmd->data)); 731 memcpy(cmd->data, arg, len); 732 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 733 734 /* If there is no pending command already, schedule a task. */ 735 if (++ring->queued == 1) 736 usb_add_task(sc->sc_udev, &sc->sc_task); 737 splx(s); 738 } 739 740 void 741 urtwn_wait_async(void *cookie) 742 { 743 struct urtwn_softc *sc = cookie; 744 int s; 745 746 s = splusb(); 747 /* Wait for all queued asynchronous commands to complete. */ 748 usb_wait_task(sc->sc_udev, &sc->sc_task); 749 splx(s); 750 } 751 752 int 753 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 754 int len) 755 { 756 usb_device_request_t req; 757 758 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 759 req.bRequest = R92C_REQ_REGS; 760 USETW(req.wValue, addr); 761 USETW(req.wIndex, 0); 762 USETW(req.wLength, len); 763 return (usbd_do_request(sc->sc_udev, &req, buf)); 764 } 765 766 void 767 urtwn_write_1(void *cookie, uint16_t addr, uint8_t val) 768 { 769 struct urtwn_softc *sc = cookie; 770 771 urtwn_write_region_1(sc, addr, &val, 1); 772 } 773 774 void 775 urtwn_write_2(void *cookie, uint16_t addr, uint16_t val) 776 { 777 struct urtwn_softc *sc = cookie; 778 779 val = htole16(val); 780 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 781 } 782 783 void 784 urtwn_write_4(void *cookie, uint16_t addr, uint32_t val) 785 { 786 struct urtwn_softc *sc = cookie; 787 788 val = htole32(val); 789 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 790 } 791 792 int 793 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 794 int len) 795 { 796 usb_device_request_t req; 797 798 req.bmRequestType = UT_READ_VENDOR_DEVICE; 799 req.bRequest = R92C_REQ_REGS; 800 USETW(req.wValue, addr); 801 USETW(req.wIndex, 0); 802 USETW(req.wLength, len); 803 return (usbd_do_request(sc->sc_udev, &req, buf)); 804 } 805 806 uint8_t 807 urtwn_read_1(void *cookie, uint16_t addr) 808 { 809 struct urtwn_softc *sc = cookie; 810 uint8_t val; 811 812 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 813 return (0xff); 814 return (val); 815 } 816 817 uint16_t 818 urtwn_read_2(void *cookie, uint16_t addr) 819 { 820 struct urtwn_softc *sc = cookie; 821 uint16_t val; 822 823 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 824 return (0xffff); 825 return (letoh16(val)); 826 } 827 828 uint32_t 829 urtwn_read_4(void *cookie, uint16_t addr) 830 { 831 struct urtwn_softc *sc = cookie; 832 uint32_t val; 833 834 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 835 return (0xffffffff); 836 return (letoh32(val)); 837 } 838 839 int 840 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 841 { 842 int ntries; 843 844 urtwn_write_4(sc, R92C_LLT_INIT, 845 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 846 SM(R92C_LLT_INIT_ADDR, addr) | 847 SM(R92C_LLT_INIT_DATA, data)); 848 /* Wait for write operation to complete. */ 849 for (ntries = 0; ntries < 20; ntries++) { 850 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 851 R92C_LLT_INIT_OP_NO_ACTIVE) 852 return (0); 853 DELAY(5); 854 } 855 return (ETIMEDOUT); 856 } 857 858 void 859 urtwn_calib_to(void *arg) 860 { 861 struct urtwn_softc *sc = arg; 862 863 if (usbd_is_dying(sc->sc_udev)) 864 return; 865 866 usbd_ref_incr(sc->sc_udev); 867 868 /* Do it in a process context. */ 869 urtwn_do_async(sc, urtwn_calib_cb, NULL, 0); 870 871 usbd_ref_decr(sc->sc_udev); 872 } 873 874 /* ARGSUSED */ 875 void 876 urtwn_calib_cb(struct urtwn_softc *sc, void *arg) 877 { 878 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 879 int s; 880 881 s = splnet(); 882 if (ic->ic_opmode == IEEE80211_M_STA) { 883 ieee80211_amrr_choose(&sc->amrr, ic->ic_bss, &sc->amn); 884 } 885 splx(s); 886 887 rtwn_calib(&sc->sc_sc); 888 } 889 890 void 891 urtwn_next_calib(void *cookie) 892 { 893 struct urtwn_softc *sc = cookie; 894 895 if (!usbd_is_dying(sc->sc_udev)) 896 timeout_add_sec(&sc->calib_to, 2); 897 } 898 899 void 900 urtwn_cancel_calib(void *cookie) 901 { 902 struct urtwn_softc *sc = cookie; 903 904 if (timeout_initialized(&sc->calib_to)) 905 timeout_del(&sc->calib_to); 906 } 907 908 void 909 urtwn_scan_to(void *arg) 910 { 911 struct urtwn_softc *sc = arg; 912 913 if (usbd_is_dying(sc->sc_udev)) 914 return; 915 916 usbd_ref_incr(sc->sc_udev); 917 rtwn_next_scan(&sc->sc_sc); 918 usbd_ref_decr(sc->sc_udev); 919 } 920 921 void 922 urtwn_next_scan(void *arg) 923 { 924 struct urtwn_softc *sc = arg; 925 926 if (!usbd_is_dying(sc->sc_udev)) 927 timeout_add_msec(&sc->scan_to, 200); 928 } 929 930 void 931 urtwn_cancel_scan(void *cookie) 932 { 933 struct urtwn_softc *sc = cookie; 934 935 if (timeout_initialized(&sc->scan_to)) 936 timeout_del(&sc->scan_to); 937 } 938 939 int 940 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 941 { 942 struct rtwn_softc *sc_sc = ic->ic_softc; 943 struct device *self = sc_sc->sc_pdev; 944 struct urtwn_softc *sc = (struct urtwn_softc *)self; 945 struct urtwn_cmd_newstate cmd; 946 947 /* Do it in a process context. */ 948 cmd.state = nstate; 949 cmd.arg = arg; 950 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 951 return (0); 952 } 953 954 void 955 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 956 { 957 struct urtwn_cmd_newstate *cmd = arg; 958 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 959 960 rtwn_newstate(ic, cmd->state, cmd->arg); 961 } 962 963 void 964 urtwn_updateslot(struct ieee80211com *ic) 965 { 966 struct rtwn_softc *sc_sc = ic->ic_softc; 967 struct device *self = sc_sc->sc_pdev; 968 struct urtwn_softc *sc = (struct urtwn_softc *)self; 969 970 /* Do it in a process context. */ 971 urtwn_do_async(sc, urtwn_updateslot_cb, NULL, 0); 972 } 973 974 /* ARGSUSED */ 975 void 976 urtwn_updateslot_cb(struct urtwn_softc *sc, void *arg) 977 { 978 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 979 980 rtwn_updateslot(ic); 981 } 982 983 void 984 urtwn_updateedca(struct ieee80211com *ic) 985 { 986 struct rtwn_softc *sc_sc = ic->ic_softc; 987 struct device *self = sc_sc->sc_pdev; 988 struct urtwn_softc *sc = (struct urtwn_softc *)self; 989 990 /* Do it in a process context. */ 991 urtwn_do_async(sc, urtwn_updateedca_cb, NULL, 0); 992 } 993 994 /* ARGSUSED */ 995 void 996 urtwn_updateedca_cb(struct urtwn_softc *sc, void *arg) 997 { 998 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 999 1000 rtwn_updateedca(ic); 1001 } 1002 1003 int 1004 urtwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1005 struct ieee80211_key *k) 1006 { 1007 struct rtwn_softc *sc_sc = ic->ic_softc; 1008 struct device *self = sc_sc->sc_pdev; 1009 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1010 struct urtwn_cmd_key cmd; 1011 1012 /* Defer setting of WEP keys until interface is brought up. */ 1013 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 1014 (IFF_UP | IFF_RUNNING)) 1015 return (0); 1016 1017 /* Do it in a process context. */ 1018 cmd.key = *k; 1019 cmd.ni = ni; 1020 urtwn_do_async(sc, urtwn_set_key_cb, &cmd, sizeof(cmd)); 1021 return (0); 1022 } 1023 1024 void 1025 urtwn_set_key_cb(struct urtwn_softc *sc, void *arg) 1026 { 1027 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1028 struct urtwn_cmd_key *cmd = arg; 1029 1030 rtwn_set_key(ic, cmd->ni, &cmd->key); 1031 } 1032 1033 void 1034 urtwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1035 struct ieee80211_key *k) 1036 { 1037 struct rtwn_softc *sc_sc = ic->ic_softc; 1038 struct device *self = sc_sc->sc_pdev; 1039 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1040 struct urtwn_cmd_key cmd; 1041 1042 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 1043 ic->ic_state != IEEE80211_S_RUN) 1044 return; /* Nothing to do. */ 1045 1046 /* Do it in a process context. */ 1047 cmd.key = *k; 1048 cmd.ni = ni; 1049 urtwn_do_async(sc, urtwn_delete_key_cb, &cmd, sizeof(cmd)); 1050 } 1051 1052 void 1053 urtwn_delete_key_cb(struct urtwn_softc *sc, void *arg) 1054 { 1055 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1056 struct urtwn_cmd_key *cmd = arg; 1057 1058 rtwn_delete_key(ic, cmd->ni, &cmd->key); 1059 } 1060 1061 void 1062 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 1063 { 1064 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1065 struct ifnet *ifp = &ic->ic_if; 1066 struct ieee80211_rxinfo rxi; 1067 struct ieee80211_frame *wh; 1068 struct ieee80211_node *ni; 1069 struct r92c_rx_desc_usb *rxd; 1070 uint32_t rxdw0, rxdw3; 1071 struct mbuf *m; 1072 uint8_t rate; 1073 int8_t rssi = 0; 1074 int s, infosz; 1075 1076 rxd = (struct r92c_rx_desc_usb *)buf; 1077 rxdw0 = letoh32(rxd->rxdw0); 1078 rxdw3 = letoh32(rxd->rxdw3); 1079 1080 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1081 /* 1082 * This should not happen since we setup our Rx filter 1083 * to not receive these frames. 1084 */ 1085 ifp->if_ierrors++; 1086 return; 1087 } 1088 if (__predict_false(pktlen < sizeof(*wh) || pktlen > MCLBYTES)) { 1089 ifp->if_ierrors++; 1090 return; 1091 } 1092 1093 rate = MS(rxdw3, R92C_RXDW3_RATE); 1094 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1095 1096 /* Get RSSI from PHY status descriptor if present. */ 1097 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1098 rssi = rtwn_get_rssi(&sc->sc_sc, rate, &rxd[1]); 1099 /* Update our average RSSI. */ 1100 rtwn_update_avgrssi(&sc->sc_sc, rate, rssi); 1101 } 1102 1103 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 1104 pktlen, rate, infosz, rssi)); 1105 1106 MGETHDR(m, M_DONTWAIT, MT_DATA); 1107 if (__predict_false(m == NULL)) { 1108 ifp->if_ierrors++; 1109 return; 1110 } 1111 if (pktlen > MHLEN) { 1112 MCLGET(m, M_DONTWAIT); 1113 if (__predict_false(!(m->m_flags & M_EXT))) { 1114 ifp->if_ierrors++; 1115 m_freem(m); 1116 return; 1117 } 1118 } 1119 /* Finalize mbuf. */ 1120 wh = (struct ieee80211_frame *)((uint8_t *)&rxd[1] + infosz); 1121 memcpy(mtod(m, uint8_t *), wh, pktlen); 1122 m->m_pkthdr.len = m->m_len = pktlen; 1123 1124 s = splnet(); 1125 #if NBPFILTER > 0 1126 if (__predict_false(sc->sc_drvbpf != NULL)) { 1127 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1128 struct mbuf mb; 1129 1130 tap->wr_flags = 0; 1131 /* Map HW rate index to 802.11 rate. */ 1132 if (!(rxdw3 & R92C_RXDW3_HT)) { 1133 switch (rate) { 1134 /* CCK. */ 1135 case 0: tap->wr_rate = 2; break; 1136 case 1: tap->wr_rate = 4; break; 1137 case 2: tap->wr_rate = 11; break; 1138 case 3: tap->wr_rate = 22; break; 1139 /* OFDM. */ 1140 case 4: tap->wr_rate = 12; break; 1141 case 5: tap->wr_rate = 18; break; 1142 case 6: tap->wr_rate = 24; break; 1143 case 7: tap->wr_rate = 36; break; 1144 case 8: tap->wr_rate = 48; break; 1145 case 9: tap->wr_rate = 72; break; 1146 case 10: tap->wr_rate = 96; break; 1147 case 11: tap->wr_rate = 108; break; 1148 } 1149 if (rate <= 3) 1150 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1151 } else if (rate >= 12) { /* MCS0~15. */ 1152 /* Bit 7 set means HT MCS instead of rate. */ 1153 tap->wr_rate = 0x80 | (rate - 12); 1154 } 1155 tap->wr_dbm_antsignal = rssi; 1156 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1157 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1158 1159 mb.m_data = (caddr_t)tap; 1160 mb.m_len = sc->sc_rxtap_len; 1161 mb.m_next = m; 1162 mb.m_nextpkt = NULL; 1163 mb.m_type = 0; 1164 mb.m_flags = 0; 1165 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1166 } 1167 #endif 1168 1169 ni = ieee80211_find_rxnode(ic, wh); 1170 rxi.rxi_flags = 0; 1171 rxi.rxi_rssi = rssi; 1172 rxi.rxi_tstamp = 0; /* Unused. */ 1173 ieee80211_input(ifp, m, ni, &rxi); 1174 /* Node is no longer needed. */ 1175 ieee80211_release_node(ic, ni); 1176 splx(s); 1177 } 1178 1179 void 1180 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, 1181 usbd_status status) 1182 { 1183 struct urtwn_rx_data *data = priv; 1184 struct urtwn_softc *sc = data->sc; 1185 struct r92c_rx_desc_usb *rxd; 1186 uint32_t rxdw0; 1187 uint8_t *buf; 1188 int len, totlen, pktlen, infosz, npkts, error; 1189 1190 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1191 DPRINTF(("RX status=%d\n", status)); 1192 if (status == USBD_STALLED) 1193 usbd_clear_endpoint_stall_async(sc->rx_pipe); 1194 if (status != USBD_CANCELLED) 1195 goto resubmit; 1196 return; 1197 } 1198 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 1199 1200 if (__predict_false(len < sizeof(*rxd))) { 1201 DPRINTF(("xfer too short %d\n", len)); 1202 goto resubmit; 1203 } 1204 buf = data->buf; 1205 1206 /* Get the number of encapsulated frames. */ 1207 rxd = (struct r92c_rx_desc_usb *)buf; 1208 npkts = MS(letoh32(rxd->rxdw2), R92C_RXDW2_PKTCNT); 1209 DPRINTFN(4, ("Rx %d frames in one chunk\n", npkts)); 1210 1211 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1212 int ntries, type; 1213 struct r88e_tx_rpt_ccx *rxstat; 1214 1215 type = MS(letoh32(rxd->rxdw3), R88E_RXDW3_RPT); 1216 1217 if (type == R88E_RXDW3_RPT_TX1) { 1218 buf += sizeof(struct r92c_rx_desc_usb); 1219 rxstat = (struct r88e_tx_rpt_ccx *)buf; 1220 ntries = MS(letoh32(rxstat->rptb2), 1221 R88E_RPTB2_RETRY_CNT); 1222 1223 if (rxstat->rptb1 & R88E_RPTB1_PKT_OK) 1224 sc->amn.amn_txcnt++; 1225 if (ntries > 0) 1226 sc->amn.amn_retrycnt++; 1227 1228 goto resubmit; 1229 } 1230 } 1231 1232 /* Process all of them. */ 1233 while (npkts-- > 0) { 1234 if (__predict_false(len < sizeof(*rxd))) 1235 break; 1236 rxd = (struct r92c_rx_desc_usb *)buf; 1237 rxdw0 = letoh32(rxd->rxdw0); 1238 1239 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1240 if (__predict_false(pktlen == 0)) 1241 break; 1242 1243 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1244 1245 /* Make sure everything fits in xfer. */ 1246 totlen = sizeof(*rxd) + infosz + pktlen; 1247 if (__predict_false(totlen > len)) 1248 break; 1249 1250 /* Process 802.11 frame. */ 1251 urtwn_rx_frame(sc, buf, pktlen); 1252 1253 /* Next chunk is 128-byte aligned. */ 1254 totlen = (totlen + 127) & ~127; 1255 buf += totlen; 1256 len -= totlen; 1257 } 1258 1259 resubmit: 1260 /* Setup a new transfer. */ 1261 usbd_setup_xfer(xfer, sc->rx_pipe, data, data->buf, URTWN_RXBUFSZ, 1262 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, urtwn_rxeof); 1263 error = usbd_transfer(data->xfer); 1264 if (error != 0 && error != USBD_IN_PROGRESS) 1265 DPRINTF(("could not set up new transfer: %d\n", error)); 1266 } 1267 1268 void 1269 urtwn_txeof(struct usbd_xfer *xfer, void *priv, 1270 usbd_status status) 1271 { 1272 struct urtwn_tx_data *data = priv; 1273 struct urtwn_softc *sc = data->sc; 1274 struct ifnet *ifp = &sc->sc_sc.sc_ic.ic_if; 1275 int s; 1276 1277 s = splnet(); 1278 /* Put this Tx buffer back to our free list. */ 1279 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1280 1281 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1282 DPRINTF(("TX status=%d\n", status)); 1283 if (status == USBD_STALLED) 1284 usbd_clear_endpoint_stall_async(data->pipe); 1285 ifp->if_oerrors++; 1286 splx(s); 1287 return; 1288 } 1289 sc->sc_sc.sc_tx_timer = 0; 1290 1291 /* We just released a Tx buffer, notify Tx. */ 1292 if (ifq_is_oactive(&ifp->if_snd)) { 1293 ifq_clr_oactive(&ifp->if_snd); 1294 rtwn_start(ifp); 1295 } 1296 splx(s); 1297 } 1298 1299 int 1300 urtwn_tx(void *cookie, struct mbuf *m, struct ieee80211_node *ni) 1301 { 1302 struct urtwn_softc *sc = cookie; 1303 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1304 struct ieee80211_frame *wh; 1305 struct ieee80211_key *k = NULL; 1306 struct urtwn_tx_data *data; 1307 struct r92c_tx_desc_usb *txd; 1308 struct usbd_pipe *pipe; 1309 uint16_t qos, sum; 1310 uint8_t raid, type, tid, qid; 1311 int i, hasqos, xferlen, error; 1312 1313 wh = mtod(m, struct ieee80211_frame *); 1314 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1315 1316 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1317 k = ieee80211_get_txkey(ic, wh, ni); 1318 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1319 return (ENOBUFS); 1320 wh = mtod(m, struct ieee80211_frame *); 1321 } 1322 1323 if ((hasqos = ieee80211_has_qos(wh))) { 1324 qos = ieee80211_get_qos(wh); 1325 tid = qos & IEEE80211_QOS_TID; 1326 qid = ieee80211_up_to_ac(ic, tid); 1327 } else if (type != IEEE80211_FC0_TYPE_DATA) { 1328 /* Use AC VO for management frames. */ 1329 qid = EDCA_AC_VO; 1330 } else 1331 qid = EDCA_AC_BE; 1332 1333 /* Get the USB pipe to use for this AC. */ 1334 pipe = sc->tx_pipe[sc->ac2idx[qid]]; 1335 1336 /* Grab a Tx buffer from our free list. */ 1337 data = TAILQ_FIRST(&sc->tx_free_list); 1338 TAILQ_REMOVE(&sc->tx_free_list, data, next); 1339 1340 /* Fill Tx descriptor. */ 1341 txd = (struct r92c_tx_desc_usb *)data->buf; 1342 memset(txd, 0, sizeof(*txd)); 1343 1344 txd->txdw0 |= htole32( 1345 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 1346 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1347 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1348 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1349 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1350 1351 #ifdef notyet 1352 if (k != NULL) { 1353 switch (k->k_cipher) { 1354 case IEEE80211_CIPHER_WEP40: 1355 case IEEE80211_CIPHER_WEP104: 1356 case IEEE80211_CIPHER_TKIP: 1357 cipher = R92C_TXDW1_CIPHER_RC4; 1358 break; 1359 case IEEE80211_CIPHER_CCMP: 1360 cipher = R92C_TXDW1_CIPHER_AES; 1361 break; 1362 default: 1363 cipher = R92C_TXDW1_CIPHER_NONE; 1364 } 1365 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 1366 } 1367 #endif 1368 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1369 type == IEEE80211_FC0_TYPE_DATA) { 1370 if (ic->ic_curmode == IEEE80211_MODE_11B || 1371 (sc->sc_sc.sc_flags & RTWN_FLAG_FORCE_RAID_11B)) 1372 raid = R92C_RAID_11B; 1373 else 1374 raid = R92C_RAID_11BG; 1375 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1376 txd->txdw1 |= htole32( 1377 SM(R88E_TXDW1_MACID, R92C_MACID_BSS) | 1378 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1379 SM(R92C_TXDW1_RAID, raid)); 1380 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1381 /* Request TX status report for AMRR */ 1382 txd->txdw2 |= htole32(R92C_TXDW2_CCX_RPT); 1383 } else { 1384 txd->txdw1 |= htole32( 1385 SM(R92C_TXDW1_MACID, R92C_MACID_BSS) | 1386 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1387 SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1388 } 1389 1390 if (m->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 1391 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1392 R92C_TXDW4_HWRTSEN); 1393 } else if (ic->ic_flags & IEEE80211_F_USEPROT) { 1394 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1395 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1396 R92C_TXDW4_HWRTSEN); 1397 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1398 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1399 R92C_TXDW4_HWRTSEN); 1400 } 1401 } 1402 txd->txdw5 |= htole32(0x0001ff00); 1403 1404 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1405 /* Use AMRR */ 1406 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1407 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 1408 ni->ni_txrate)); 1409 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1410 ni->ni_txrate)); 1411 } else { 1412 /* Send RTS at OFDM24 and data at OFDM54. */ 1413 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1414 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1415 } 1416 } else { 1417 txd->txdw1 |= htole32( 1418 SM(R92C_TXDW1_MACID, 0) | 1419 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1420 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1421 1422 /* Force CCK1. */ 1423 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1424 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1425 } 1426 /* Set sequence number (already little endian). */ 1427 txd->txdseq |= (*(uint16_t *)wh->i_seq) >> IEEE80211_SEQ_SEQ_SHIFT; 1428 1429 if (!hasqos) { 1430 /* Use HW sequence numbering for non-QoS frames. */ 1431 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1432 txd->txdseq |= htole16(R92C_TXDW3_HWSEQEN); 1433 } else 1434 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1435 1436 /* Compute Tx descriptor checksum. */ 1437 sum = 0; 1438 for (i = 0; i < sizeof(*txd) / 2; i++) 1439 sum ^= ((uint16_t *)txd)[i]; 1440 txd->txdsum = sum; /* NB: already little endian. */ 1441 1442 #if NBPFILTER > 0 1443 if (__predict_false(sc->sc_drvbpf != NULL)) { 1444 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1445 struct mbuf mb; 1446 1447 tap->wt_flags = 0; 1448 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1449 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1450 1451 mb.m_data = (caddr_t)tap; 1452 mb.m_len = sc->sc_txtap_len; 1453 mb.m_next = m; 1454 mb.m_nextpkt = NULL; 1455 mb.m_type = 0; 1456 mb.m_flags = 0; 1457 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1458 } 1459 #endif 1460 1461 xferlen = sizeof(*txd) + m->m_pkthdr.len; 1462 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]); 1463 m_freem(m); 1464 1465 data->pipe = pipe; 1466 usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen, 1467 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTWN_TX_TIMEOUT, 1468 urtwn_txeof); 1469 error = usbd_transfer(data->xfer); 1470 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) { 1471 /* Put this Tx buffer back to our free list. */ 1472 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1473 return (error); 1474 } 1475 ieee80211_release_node(ic, ni); 1476 return (0); 1477 } 1478 1479 int 1480 urtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1481 { 1482 struct rtwn_softc *sc_sc = ifp->if_softc; 1483 struct device *self = sc_sc->sc_pdev; 1484 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1485 int error; 1486 1487 if (usbd_is_dying(sc->sc_udev)) 1488 return ENXIO; 1489 1490 usbd_ref_incr(sc->sc_udev); 1491 error = rtwn_ioctl(ifp, cmd, data); 1492 usbd_ref_decr(sc->sc_udev); 1493 1494 return (error); 1495 } 1496 1497 int 1498 urtwn_r92c_power_on(struct urtwn_softc *sc) 1499 { 1500 uint32_t reg; 1501 int ntries; 1502 1503 /* Wait for autoload done bit. */ 1504 for (ntries = 0; ntries < 1000; ntries++) { 1505 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 1506 break; 1507 DELAY(5); 1508 } 1509 if (ntries == 1000) { 1510 printf("%s: timeout waiting for chip autoload\n", 1511 sc->sc_dev.dv_xname); 1512 return (ETIMEDOUT); 1513 } 1514 1515 /* Unlock ISO/CLK/Power control register. */ 1516 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 1517 /* Move SPS into PWM mode. */ 1518 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 1519 DELAY(100); 1520 1521 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 1522 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 1523 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 1524 reg | R92C_LDOV12D_CTRL_LDV12_EN); 1525 DELAY(100); 1526 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 1527 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 1528 ~R92C_SYS_ISO_CTRL_MD2PP); 1529 } 1530 1531 /* Auto enable WLAN. */ 1532 urtwn_write_2(sc, R92C_APS_FSMCO, 1533 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1534 for (ntries = 0; ntries < 1000; ntries++) { 1535 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1536 R92C_APS_FSMCO_APFM_ONMAC)) 1537 break; 1538 DELAY(5); 1539 } 1540 if (ntries == 1000) { 1541 printf("%s: timeout waiting for MAC auto ON\n", 1542 sc->sc_dev.dv_xname); 1543 return (ETIMEDOUT); 1544 } 1545 1546 /* Enable radio, GPIO and LED functions. */ 1547 urtwn_write_2(sc, R92C_APS_FSMCO, 1548 R92C_APS_FSMCO_AFSM_HSUS | 1549 R92C_APS_FSMCO_PDN_EN | 1550 R92C_APS_FSMCO_PFM_ALDN); 1551 /* Release RF digital isolation. */ 1552 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1553 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 1554 1555 /* Initialize MAC. */ 1556 urtwn_write_1(sc, R92C_APSD_CTRL, 1557 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 1558 for (ntries = 0; ntries < 200; ntries++) { 1559 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 1560 R92C_APSD_CTRL_OFF_STATUS)) 1561 break; 1562 DELAY(5); 1563 } 1564 if (ntries == 200) { 1565 printf("%s: timeout waiting for MAC initialization\n", 1566 sc->sc_dev.dv_xname); 1567 return (ETIMEDOUT); 1568 } 1569 1570 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1571 reg = urtwn_read_2(sc, R92C_CR); 1572 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1573 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1574 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 1575 R92C_CR_ENSEC; 1576 urtwn_write_2(sc, R92C_CR, reg); 1577 1578 urtwn_write_1(sc, 0xfe10, 0x19); 1579 return (0); 1580 } 1581 1582 int 1583 urtwn_r88e_power_on(struct urtwn_softc *sc) 1584 { 1585 uint32_t reg; 1586 int ntries; 1587 1588 /* Wait for power ready bit. */ 1589 for (ntries = 0; ntries < 5000; ntries++) { 1590 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 1591 break; 1592 DELAY(10); 1593 } 1594 if (ntries == 5000) { 1595 printf("%s: timeout waiting for chip power up\n", 1596 sc->sc_dev.dv_xname); 1597 return (ETIMEDOUT); 1598 } 1599 1600 /* Reset BB. */ 1601 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 1602 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 1603 R92C_SYS_FUNC_EN_BB_GLB_RST)); 1604 1605 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 1606 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 1607 1608 /* Disable HWPDN. */ 1609 urtwn_write_2(sc, R92C_APS_FSMCO, 1610 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 1611 /* Disable WL suspend. */ 1612 urtwn_write_2(sc, R92C_APS_FSMCO, 1613 urtwn_read_2(sc, R92C_APS_FSMCO) & 1614 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 1615 1616 /* Auto enable WLAN. */ 1617 urtwn_write_2(sc, R92C_APS_FSMCO, 1618 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1619 for (ntries = 0; ntries < 5000; ntries++) { 1620 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1621 R92C_APS_FSMCO_APFM_ONMAC)) 1622 break; 1623 DELAY(10); 1624 } 1625 if (ntries == 5000) { 1626 printf("%s: timeout waiting for MAC auto ON\n", 1627 sc->sc_dev.dv_xname); 1628 return (ETIMEDOUT); 1629 } 1630 1631 /* Enable LDO normal mode. */ 1632 urtwn_write_1(sc, R92C_LPLDO_CTRL, 1633 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 1634 1635 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1636 urtwn_write_2(sc, R92C_CR, 0); 1637 reg = urtwn_read_2(sc, R92C_CR); 1638 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1639 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1640 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 1641 urtwn_write_2(sc, R92C_CR, reg); 1642 return (0); 1643 } 1644 1645 int 1646 urtwn_llt_init(struct urtwn_softc *sc, int page_count) 1647 { 1648 int i, error, pktbuf_count; 1649 1650 pktbuf_count = (sc->sc_sc.chip & RTWN_CHIP_88E) ? 1651 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 1652 1653 /* Reserve pages [0; page_count]. */ 1654 for (i = 0; i < page_count; i++) { 1655 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1656 return (error); 1657 } 1658 /* NB: 0xff indicates end-of-list. */ 1659 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 1660 return (error); 1661 /* 1662 * Use pages [page_count + 1; pktbuf_count - 1] 1663 * as ring buffer. 1664 */ 1665 for (++i; i < pktbuf_count - 1; i++) { 1666 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1667 return (error); 1668 } 1669 /* Make the last page point to the beginning of the ring buffer. */ 1670 error = urtwn_llt_write(sc, i, page_count + 1); 1671 return (error); 1672 } 1673 1674 int 1675 urtwn_fw_loadpage(void *cookie, int page, uint8_t *buf, int len) 1676 { 1677 struct urtwn_softc *sc = cookie; 1678 uint32_t reg; 1679 int off, mlen, error = 0; 1680 1681 reg = urtwn_read_4(sc, R92C_MCUFWDL); 1682 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 1683 urtwn_write_4(sc, R92C_MCUFWDL, reg); 1684 1685 off = R92C_FW_START_ADDR; 1686 while (len > 0) { 1687 if (len > 196) 1688 mlen = 196; 1689 else if (len > 4) 1690 mlen = 4; 1691 else 1692 mlen = 1; 1693 error = urtwn_write_region_1(sc, off, buf, mlen); 1694 if (error != 0) 1695 break; 1696 off += mlen; 1697 buf += mlen; 1698 len -= mlen; 1699 } 1700 return (error); 1701 } 1702 1703 int 1704 urtwn_load_firmware(void *cookie, u_char **fw, size_t *len) 1705 { 1706 struct urtwn_softc *sc = cookie; 1707 const char *name; 1708 int error; 1709 1710 if (sc->sc_sc.chip & RTWN_CHIP_88E) 1711 name = "urtwn-rtl8188eufw"; 1712 else if ((sc->sc_sc.chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 1713 RTWN_CHIP_UMC_A_CUT) 1714 name = "urtwn-rtl8192cfwU"; 1715 else 1716 name = "urtwn-rtl8192cfwT"; 1717 1718 error = loadfirmware(name, fw, len); 1719 if (error) 1720 printf("%s: could not read firmware %s (error %d)\n", 1721 sc->sc_dev.dv_xname, name, error); 1722 return (error); 1723 } 1724 1725 int 1726 urtwn_dma_init(void *cookie) 1727 { 1728 struct urtwn_softc *sc = cookie; 1729 uint32_t reg; 1730 uint16_t dmasize; 1731 int hqpages, lqpages, nqpages, pagecnt, boundary; 1732 int error, hashq, haslq, hasnq; 1733 1734 /* Default initialization of chipset values. */ 1735 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1736 hqpages = R88E_HQ_NPAGES; 1737 lqpages = R88E_LQ_NPAGES; 1738 nqpages = R88E_NQ_NPAGES; 1739 pagecnt = R88E_TX_PAGE_COUNT; 1740 boundary = R88E_TX_PAGE_BOUNDARY; 1741 dmasize = R88E_MAX_RX_DMA_SIZE; 1742 } else { 1743 hqpages = R92C_HQ_NPAGES; 1744 lqpages = R92C_LQ_NPAGES; 1745 nqpages = R92C_NQ_NPAGES; 1746 pagecnt = R92C_TX_PAGE_COUNT; 1747 boundary = R92C_TX_PAGE_BOUNDARY; 1748 dmasize = R92C_MAX_RX_DMA_SIZE; 1749 } 1750 1751 /* Initialize LLT table. */ 1752 error = urtwn_llt_init(sc, pagecnt); 1753 if (error != 0) 1754 return (error); 1755 1756 /* Get Tx queues to USB endpoints mapping. */ 1757 hashq = hasnq = haslq = 0; 1758 switch (sc->ntx) { 1759 case 3: 1760 haslq = 1; 1761 pagecnt -= lqpages; 1762 /* FALLTHROUGH */ 1763 case 2: 1764 hasnq = 1; 1765 pagecnt -= nqpages; 1766 /* FALLTHROUGH */ 1767 case 1: 1768 hashq = 1; 1769 pagecnt -= hqpages; 1770 break; 1771 } 1772 1773 /* Set number of pages for normal priority queue. */ 1774 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 1775 urtwn_write_4(sc, R92C_RQPN, 1776 /* Set number of pages for public queue. */ 1777 SM(R92C_RQPN_PUBQ, pagecnt) | 1778 /* Set number of pages for high priority queue. */ 1779 SM(R92C_RQPN_HPQ, hashq ? hqpages : 0) | 1780 /* Set number of pages for low priority queue. */ 1781 SM(R92C_RQPN_LPQ, haslq ? lqpages : 0) | 1782 /* Load values. */ 1783 R92C_RQPN_LD); 1784 1785 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, boundary); 1786 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, boundary); 1787 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, boundary); 1788 urtwn_write_1(sc, R92C_TRXFF_BNDY, boundary); 1789 urtwn_write_1(sc, R92C_TDECTRL + 1, boundary); 1790 1791 /* Set queue to USB pipe mapping. */ 1792 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 1793 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 1794 if (haslq) 1795 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 1796 else if (hashq) { 1797 if (!hasnq) 1798 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 1799 else 1800 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 1801 } 1802 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 1803 1804 /* Set Tx/Rx transfer page boundary. */ 1805 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, dmasize - 1); 1806 1807 /* Set Tx/Rx transfer page size. */ 1808 urtwn_write_1(sc, R92C_PBP, 1809 SM(R92C_PBP_PSRX, R92C_PBP_128) | 1810 SM(R92C_PBP_PSTX, R92C_PBP_128)); 1811 return (error); 1812 } 1813 1814 void 1815 urtwn_mac_init(void *cookie) 1816 { 1817 struct urtwn_softc *sc = cookie; 1818 int i; 1819 1820 /* Write MAC initialization values. */ 1821 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1822 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 1823 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 1824 rtl8188eu_mac[i].val); 1825 } 1826 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 1827 } else { 1828 for (i = 0; i < nitems(rtl8192cu_mac); i++) 1829 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 1830 rtl8192cu_mac[i].val); 1831 } 1832 } 1833 1834 void 1835 urtwn_bb_init(void *cookie) 1836 { 1837 struct urtwn_softc *sc = cookie; 1838 const struct r92c_bb_prog *prog; 1839 uint32_t reg; 1840 uint8_t xtal; 1841 int i; 1842 1843 /* Enable BB and RF. */ 1844 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1845 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 1846 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 1847 R92C_SYS_FUNC_EN_DIO_RF); 1848 1849 if (!(sc->sc_sc.chip & RTWN_CHIP_88E)) 1850 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 1851 1852 urtwn_write_1(sc, R92C_RF_CTRL, 1853 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 1854 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 1855 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 1856 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 1857 1858 if (!(sc->sc_sc.chip & RTWN_CHIP_88E)) { 1859 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 1860 urtwn_write_1(sc, 0x15, 0xe9); 1861 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 1862 } 1863 1864 /* Select BB programming based on board type. */ 1865 if (sc->sc_sc.chip & RTWN_CHIP_88E) 1866 prog = &rtl8188eu_bb_prog; 1867 else if (!(sc->sc_sc.chip & RTWN_CHIP_92C)) { 1868 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD) 1869 prog = &rtl8188ce_bb_prog; 1870 else if (sc->sc_sc.board_type == R92C_BOARD_TYPE_HIGHPA) 1871 prog = &rtl8188ru_bb_prog; 1872 else 1873 prog = &rtl8188cu_bb_prog; 1874 } else { 1875 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD) 1876 prog = &rtl8192ce_bb_prog; 1877 else 1878 prog = &rtl8192cu_bb_prog; 1879 } 1880 /* Write BB initialization values. */ 1881 for (i = 0; i < prog->count; i++) { 1882 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 1883 DELAY(1); 1884 } 1885 1886 if (sc->sc_sc.chip & RTWN_CHIP_92C_1T2R) { 1887 /* 8192C 1T only configuration. */ 1888 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 1889 reg = (reg & ~0x00000003) | 0x2; 1890 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 1891 1892 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 1893 reg = (reg & ~0x00300033) | 0x00200022; 1894 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 1895 1896 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 1897 reg = (reg & ~0xff000000) | 0x45 << 24; 1898 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 1899 1900 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 1901 reg = (reg & ~0x000000ff) | 0x23; 1902 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 1903 1904 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 1905 reg = (reg & ~0x00000030) | 1 << 4; 1906 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 1907 1908 reg = urtwn_bb_read(sc, 0xe74); 1909 reg = (reg & ~0x0c000000) | 2 << 26; 1910 urtwn_bb_write(sc, 0xe74, reg); 1911 reg = urtwn_bb_read(sc, 0xe78); 1912 reg = (reg & ~0x0c000000) | 2 << 26; 1913 urtwn_bb_write(sc, 0xe78, reg); 1914 reg = urtwn_bb_read(sc, 0xe7c); 1915 reg = (reg & ~0x0c000000) | 2 << 26; 1916 urtwn_bb_write(sc, 0xe7c, reg); 1917 reg = urtwn_bb_read(sc, 0xe80); 1918 reg = (reg & ~0x0c000000) | 2 << 26; 1919 urtwn_bb_write(sc, 0xe80, reg); 1920 reg = urtwn_bb_read(sc, 0xe88); 1921 reg = (reg & ~0x0c000000) | 2 << 26; 1922 urtwn_bb_write(sc, 0xe88, reg); 1923 } 1924 1925 /* Write AGC values. */ 1926 for (i = 0; i < prog->agccount; i++) { 1927 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 1928 prog->agcvals[i]); 1929 DELAY(1); 1930 } 1931 1932 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1933 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 1934 DELAY(1); 1935 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 1936 DELAY(1); 1937 1938 xtal = sc->sc_sc.crystal_cap & 0x3f; 1939 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 1940 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 1941 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, xtal | xtal << 6)); 1942 } 1943 1944 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & R92C_HSSI_PARAM2_CCK_HIPWR) 1945 sc->sc_sc.sc_flags |= RTWN_FLAG_CCK_HIPWR; 1946 } 1947 1948 int 1949 urtwn_power_on(void *cookie) 1950 { 1951 struct urtwn_softc *sc = cookie; 1952 1953 if (sc->sc_sc.chip & RTWN_CHIP_88E) 1954 return (urtwn_r88e_power_on(sc)); 1955 1956 return (urtwn_r92c_power_on(sc)); 1957 } 1958 1959 int 1960 urtwn_alloc_buffers(void *cookie) 1961 { 1962 struct urtwn_softc *sc = cookie; 1963 int error; 1964 1965 /* Init host async commands ring. */ 1966 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 1967 1968 /* Allocate Tx/Rx buffers. */ 1969 error = urtwn_alloc_rx_list(sc); 1970 if (error != 0) { 1971 printf("%s: could not allocate Rx buffers\n", 1972 sc->sc_dev.dv_xname); 1973 return (error); 1974 } 1975 error = urtwn_alloc_tx_list(sc); 1976 if (error != 0) { 1977 printf("%s: could not allocate Tx buffers\n", 1978 sc->sc_dev.dv_xname); 1979 return (error); 1980 } 1981 1982 return (0); 1983 } 1984 1985 int 1986 urtwn_init(void *cookie) 1987 { 1988 struct urtwn_softc *sc = cookie; 1989 int i, error; 1990 1991 /* Queue Rx xfers. */ 1992 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 1993 struct urtwn_rx_data *data = &sc->rx_data[i]; 1994 1995 usbd_setup_xfer(data->xfer, sc->rx_pipe, data, data->buf, 1996 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 1997 USBD_NO_TIMEOUT, urtwn_rxeof); 1998 error = usbd_transfer(data->xfer); 1999 if (error != 0 && error != USBD_IN_PROGRESS) 2000 return (error); 2001 } 2002 2003 ieee80211_amrr_node_init(&sc->amrr, &sc->amn); 2004 2005 /* 2006 * Enable TX reports for AMRR. 2007 * In order to get reports we need to explicitly reset the register. 2008 */ 2009 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2010 urtwn_write_1(sc, R88E_TX_RPT_CTRL, (urtwn_read_1(sc, 2011 R88E_TX_RPT_CTRL) & ~0) | R88E_TX_RPT_CTRL_EN); 2012 2013 return (0); 2014 } 2015 2016 void 2017 urtwn_stop(void *cookie) 2018 { 2019 struct urtwn_softc *sc = cookie; 2020 int i; 2021 2022 /* Abort Tx. */ 2023 for (i = 0; i < R92C_MAX_EPOUT; i++) { 2024 if (sc->tx_pipe[i] != NULL) 2025 usbd_abort_pipe(sc->tx_pipe[i]); 2026 } 2027 /* Stop Rx pipe. */ 2028 usbd_abort_pipe(sc->rx_pipe); 2029 /* Free Tx/Rx buffers. */ 2030 urtwn_free_tx_list(sc); 2031 urtwn_free_rx_list(sc); 2032 } 2033 2034 int 2035 urtwn_is_oactive(void *cookie) 2036 { 2037 struct urtwn_softc *sc = cookie; 2038 2039 return (TAILQ_EMPTY(&sc->tx_free_list)); 2040 } 2041