1 /* $OpenBSD: if_urtwn.c,v 1.82 2019/01/14 06:25:26 jmatthew Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss@yahoo.com.au> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU/ 23 * RTL8192EU. 24 */ 25 26 #include "bpfilter.h" 27 28 #include <sys/param.h> 29 #include <sys/sockio.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/timeout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 #include <sys/endian.h> 38 39 #include <machine/bus.h> 40 #include <machine/intr.h> 41 42 #if NBPFILTER > 0 43 #include <net/bpf.h> 44 #endif 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 49 #include <netinet/in.h> 50 #include <netinet/if_ether.h> 51 52 #include <net80211/ieee80211_var.h> 53 #include <net80211/ieee80211_amrr.h> 54 #include <net80211/ieee80211_radiotap.h> 55 56 #include <dev/usb/usb.h> 57 #include <dev/usb/usbdi.h> 58 #include <dev/usb/usbdivar.h> 59 #include <dev/usb/usbdi_util.h> 60 #include <dev/usb/usbdevs.h> 61 62 #include <dev/ic/r92creg.h> 63 #include <dev/ic/rtwnvar.h> 64 65 /* Maximum number of output pipes is 3. */ 66 #define R92C_MAX_EPOUT 3 67 68 #define R92C_HQ_NPAGES 12 69 #define R92C_LQ_NPAGES 2 70 #define R92C_NQ_NPAGES 2 71 #define R92C_TXPKTBUF_COUNT 256 72 #define R92C_TX_PAGE_COUNT 248 73 #define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) 74 #define R92C_MAX_RX_DMA_SIZE 0x2800 75 76 #define R88E_HQ_NPAGES 0 77 #define R88E_LQ_NPAGES 9 78 #define R88E_NQ_NPAGES 0 79 #define R88E_TXPKTBUF_COUNT 177 80 #define R88E_TX_PAGE_COUNT 168 81 #define R88E_TX_PAGE_BOUNDARY (R88E_TX_PAGE_COUNT + 1) 82 #define R88E_MAX_RX_DMA_SIZE 0x2400 83 84 #define R92E_HQ_NPAGES 16 85 #define R92E_LQ_NPAGES 16 86 #define R92E_NQ_NPAGES 16 87 #define R92E_TX_PAGE_COUNT 248 88 #define R92E_TX_PAGE_BOUNDARY (R92E_TX_PAGE_COUNT + 1) 89 #define R92E_MAX_RX_DMA_SIZE 0x3fc0 90 91 #define R92C_TXDESC_SUMSIZE 32 92 #define R92C_TXDESC_SUMOFFSET 14 93 94 /* USB Requests. */ 95 #define R92C_REQ_REGS 0x05 96 97 /* 98 * Driver definitions. 99 */ 100 #define URTWN_RX_LIST_COUNT 1 101 #define URTWN_TX_LIST_COUNT 8 102 #define URTWN_HOST_CMD_RING_COUNT 32 103 104 #define URTWN_RXBUFSZ (16 * 1024) 105 #define URTWN_TXBUFSZ (sizeof(struct r92e_tx_desc_usb) + IEEE80211_MAX_LEN) 106 107 #define URTWN_RIDX_COUNT 28 108 109 #define URTWN_TX_TIMEOUT 5000 /* ms */ 110 111 #define URTWN_LED_LINK 0 112 #define URTWN_LED_DATA 1 113 114 struct urtwn_rx_radiotap_header { 115 struct ieee80211_radiotap_header wr_ihdr; 116 uint8_t wr_flags; 117 uint8_t wr_rate; 118 uint16_t wr_chan_freq; 119 uint16_t wr_chan_flags; 120 uint8_t wr_dbm_antsignal; 121 } __packed; 122 123 #define URTWN_RX_RADIOTAP_PRESENT \ 124 (1 << IEEE80211_RADIOTAP_FLAGS | \ 125 1 << IEEE80211_RADIOTAP_RATE | \ 126 1 << IEEE80211_RADIOTAP_CHANNEL | \ 127 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) 128 129 struct urtwn_tx_radiotap_header { 130 struct ieee80211_radiotap_header wt_ihdr; 131 uint8_t wt_flags; 132 uint16_t wt_chan_freq; 133 uint16_t wt_chan_flags; 134 } __packed; 135 136 #define URTWN_TX_RADIOTAP_PRESENT \ 137 (1 << IEEE80211_RADIOTAP_FLAGS | \ 138 1 << IEEE80211_RADIOTAP_CHANNEL) 139 140 struct urtwn_softc; 141 142 struct urtwn_rx_data { 143 struct urtwn_softc *sc; 144 struct usbd_xfer *xfer; 145 uint8_t *buf; 146 }; 147 148 struct urtwn_tx_data { 149 struct urtwn_softc *sc; 150 struct usbd_pipe *pipe; 151 struct usbd_xfer *xfer; 152 uint8_t *buf; 153 TAILQ_ENTRY(urtwn_tx_data) next; 154 }; 155 156 struct urtwn_host_cmd { 157 void (*cb)(struct urtwn_softc *, void *); 158 uint8_t data[256]; 159 }; 160 161 struct urtwn_cmd_newstate { 162 enum ieee80211_state state; 163 int arg; 164 }; 165 166 struct urtwn_cmd_key { 167 struct ieee80211_key key; 168 struct ieee80211_node *ni; 169 }; 170 171 struct urtwn_host_cmd_ring { 172 struct urtwn_host_cmd cmd[URTWN_HOST_CMD_RING_COUNT]; 173 int cur; 174 int next; 175 int queued; 176 }; 177 178 struct urtwn_softc { 179 struct device sc_dev; 180 struct rtwn_softc sc_sc; 181 182 struct usbd_device *sc_udev; 183 struct usbd_interface *sc_iface; 184 struct usb_task sc_task; 185 186 struct timeout scan_to; 187 struct timeout calib_to; 188 189 int ntx; 190 struct usbd_pipe *rx_pipe; 191 struct usbd_pipe *tx_pipe[R92C_MAX_EPOUT]; 192 int ac2idx[EDCA_NUM_AC]; 193 194 struct urtwn_host_cmd_ring cmdq; 195 struct urtwn_rx_data rx_data[URTWN_RX_LIST_COUNT]; 196 struct urtwn_tx_data tx_data[URTWN_TX_LIST_COUNT]; 197 TAILQ_HEAD(, urtwn_tx_data) tx_free_list; 198 199 struct ieee80211_amrr amrr; 200 struct ieee80211_amrr_node amn; 201 202 #if NBPFILTER > 0 203 caddr_t sc_drvbpf; 204 205 union { 206 struct urtwn_rx_radiotap_header th; 207 uint8_t pad[64]; 208 } sc_rxtapu; 209 #define sc_rxtap sc_rxtapu.th 210 int sc_rxtap_len; 211 212 union { 213 struct urtwn_tx_radiotap_header th; 214 uint8_t pad[64]; 215 } sc_txtapu; 216 #define sc_txtap sc_txtapu.th 217 int sc_txtap_len; 218 #endif 219 }; 220 221 #ifdef URTWN_DEBUG 222 #define DPRINTF(x) do { if (urtwn_debug) printf x; } while (0) 223 #define DPRINTFN(n, x) do { if (urtwn_debug >= (n)) printf x; } while (0) 224 int urtwn_debug = 4; 225 #else 226 #define DPRINTF(x) 227 #define DPRINTFN(n, x) 228 #endif 229 230 /* 231 * Various supported device vendors/products. 232 */ 233 #define URTWN_DEV(v, p, f) \ 234 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, (f) | RTWN_CHIP_USB } 235 #define URTWN_DEV_8192CU(v, p) URTWN_DEV(v, p, RTWN_CHIP_92C | RTWN_CHIP_88C) 236 #define URTWN_DEV_8188EU(v, p) URTWN_DEV(v, p, RTWN_CHIP_88E) 237 #define URTWN_DEV_8192EU(v, p) URTWN_DEV(v, p, RTWN_CHIP_92E) 238 static const struct urtwn_type { 239 struct usb_devno dev; 240 uint32_t chip; 241 } urtwn_devs[] = { 242 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_1), 243 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_1), 244 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_2), 245 URTWN_DEV_8192CU(ABOCOM, RTL8192CU), 246 URTWN_DEV_8192CU(ASUS, RTL8192CU), 247 URTWN_DEV_8192CU(ASUS, RTL8192CU_2), 248 URTWN_DEV_8192CU(ASUS, RTL8192CU_3), 249 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CE_1), 250 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CE_2), 251 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CU), 252 URTWN_DEV_8192CU(BELKIN, F7D2102), 253 URTWN_DEV_8192CU(BELKIN, F9L1004V1), 254 URTWN_DEV_8192CU(BELKIN, RTL8188CU), 255 URTWN_DEV_8192CU(BELKIN, RTL8188CUS), 256 URTWN_DEV_8192CU(BELKIN, RTL8192CU), 257 URTWN_DEV_8192CU(BELKIN, RTL8192CU_1), 258 URTWN_DEV_8192CU(BELKIN, RTL8192CU_2), 259 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_1), 260 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_2), 261 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_3), 262 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_4), 263 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_5), 264 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_6), 265 URTWN_DEV_8192CU(COMPARE, RTL8192CU), 266 URTWN_DEV_8192CU(COREGA, RTL8192CU), 267 URTWN_DEV_8192CU(DLINK, DWA131B), 268 URTWN_DEV_8192CU(DLINK, RTL8188CU), 269 URTWN_DEV_8192CU(DLINK, RTL8192CU_1), 270 URTWN_DEV_8192CU(DLINK, RTL8192CU_2), 271 URTWN_DEV_8192CU(DLINK, RTL8192CU_3), 272 URTWN_DEV_8192CU(DLINK, RTL8192CU_4), 273 URTWN_DEV_8192CU(EDIMAX, EW7811UN), 274 URTWN_DEV_8192CU(EDIMAX, RTL8192CU), 275 URTWN_DEV_8192CU(FEIXUN, RTL8188CU), 276 URTWN_DEV_8192CU(FEIXUN, RTL8192CU), 277 URTWN_DEV_8192CU(GUILLEMOT, HWNUP150), 278 URTWN_DEV_8192CU(GUILLEMOT, RTL8192CU), 279 URTWN_DEV_8192CU(HAWKING, RTL8192CU), 280 URTWN_DEV_8192CU(HAWKING, RTL8192CU_2), 281 URTWN_DEV_8192CU(HP3, RTL8188CU), 282 URTWN_DEV_8192CU(IODATA, WNG150UM), 283 URTWN_DEV_8192CU(IODATA, RTL8192CU), 284 URTWN_DEV_8192CU(NETGEAR, N300MA), 285 URTWN_DEV_8192CU(NETGEAR, WNA1000M), 286 URTWN_DEV_8192CU(NETGEAR, WNA1000Mv2), 287 URTWN_DEV_8192CU(NETGEAR, RTL8192CU), 288 URTWN_DEV_8192CU(NETGEAR4, RTL8188CU), 289 URTWN_DEV_8192CU(NETWEEN, RTL8192CU), 290 URTWN_DEV_8192CU(NOVATECH, RTL8188CU), 291 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_1), 292 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_2), 293 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_3), 294 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_4), 295 URTWN_DEV_8192CU(PLANEX2, RTL8188CUS), 296 URTWN_DEV_8192CU(PLANEX2, RTL8192CU), 297 URTWN_DEV_8192CU(REALTEK, RTL8188CE_0), 298 URTWN_DEV_8192CU(REALTEK, RTL8188CE_1), 299 URTWN_DEV_8192CU(REALTEK, RTL8188CTV), 300 URTWN_DEV_8192CU(REALTEK, RTL8188CU_0), 301 URTWN_DEV_8192CU(REALTEK, RTL8188CU_1), 302 URTWN_DEV_8192CU(REALTEK, RTL8188CU_2), 303 URTWN_DEV_8192CU(REALTEK, RTL8188CU_3), 304 URTWN_DEV_8192CU(REALTEK, RTL8188CU_4), 305 URTWN_DEV_8192CU(REALTEK, RTL8188CU_5), 306 URTWN_DEV_8192CU(REALTEK, RTL8188CU_COMBO), 307 URTWN_DEV_8192CU(REALTEK, RTL8188CUS), 308 URTWN_DEV_8192CU(REALTEK, RTL8188RU), 309 URTWN_DEV_8192CU(REALTEK, RTL8188RU_2), 310 URTWN_DEV_8192CU(REALTEK, RTL8188RU_3), 311 URTWN_DEV_8192CU(REALTEK, RTL8191CU), 312 URTWN_DEV_8192CU(REALTEK, RTL8192CE), 313 URTWN_DEV_8192CU(REALTEK, RTL8192CE_VAU), 314 URTWN_DEV_8192CU(REALTEK, RTL8192CU), 315 URTWN_DEV_8192CU(SITECOMEU, RTL8188CU), 316 URTWN_DEV_8192CU(SITECOMEU, RTL8188CU_2), 317 URTWN_DEV_8192CU(SITECOMEU, RTL8192CU), 318 URTWN_DEV_8192CU(SITECOMEU, RTL8192CU_2), 319 URTWN_DEV_8192CU(SITECOMEU, WLA2100V2), 320 URTWN_DEV_8192CU(TPLINK, RTL8192CU), 321 URTWN_DEV_8192CU(TRENDNET, RTL8188CU), 322 URTWN_DEV_8192CU(TRENDNET, RTL8192CU), 323 URTWN_DEV_8192CU(ZYXEL, RTL8192CU), 324 /* URTWN_RTL8188E */ 325 URTWN_DEV_8188EU(ABOCOM, RTL8188EU), 326 URTWN_DEV_8188EU(DLINK, DWA123D1), 327 URTWN_DEV_8188EU(DLINK, DWA125D1), 328 URTWN_DEV_8188EU(ELECOM, WDC150SU2M), 329 URTWN_DEV_8188EU(REALTEK, RTL8188ETV), 330 URTWN_DEV_8188EU(REALTEK, RTL8188EU), 331 URTWN_DEV_8188EU(TPLINK, RTL8188EUS), 332 /* URTWN_RTL8192EU */ 333 URTWN_DEV_8192EU(DLINK, DWA131E1), 334 URTWN_DEV_8192EU(REALTEK, RTL8192EU), 335 URTWN_DEV_8192EU(TPLINK, RTL8192EU) 336 }; 337 338 #define urtwn_lookup(v, p) \ 339 ((const struct urtwn_type *)usb_lookup(urtwn_devs, v, p)) 340 341 int urtwn_match(struct device *, void *, void *); 342 void urtwn_attach(struct device *, struct device *, void *); 343 int urtwn_detach(struct device *, int); 344 int urtwn_open_pipes(struct urtwn_softc *); 345 void urtwn_close_pipes(struct urtwn_softc *); 346 int urtwn_alloc_rx_list(struct urtwn_softc *); 347 void urtwn_free_rx_list(struct urtwn_softc *); 348 int urtwn_alloc_tx_list(struct urtwn_softc *); 349 void urtwn_free_tx_list(struct urtwn_softc *); 350 void urtwn_task(void *); 351 void urtwn_do_async(struct urtwn_softc *, 352 void (*)(struct urtwn_softc *, void *), void *, int); 353 void urtwn_wait_async(void *); 354 int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 355 int); 356 void urtwn_write_1(void *, uint16_t, uint8_t); 357 void urtwn_write_2(void *, uint16_t, uint16_t); 358 void urtwn_write_4(void *, uint16_t, uint32_t); 359 int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 360 int); 361 uint8_t urtwn_read_1(void *, uint16_t); 362 uint16_t urtwn_read_2(void *, uint16_t); 363 uint32_t urtwn_read_4(void *, uint16_t); 364 int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 365 void urtwn_calib_to(void *); 366 void urtwn_calib_cb(struct urtwn_softc *, void *); 367 void urtwn_scan_to(void *); 368 void urtwn_next_scan(void *); 369 void urtwn_cancel_scan(void *); 370 int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 371 int); 372 void urtwn_newstate_cb(struct urtwn_softc *, void *); 373 void urtwn_updateslot(struct ieee80211com *); 374 void urtwn_updateslot_cb(struct urtwn_softc *, void *); 375 void urtwn_updateedca(struct ieee80211com *); 376 void urtwn_updateedca_cb(struct urtwn_softc *, void *); 377 int urtwn_set_key(struct ieee80211com *, struct ieee80211_node *, 378 struct ieee80211_key *); 379 void urtwn_set_key_cb(struct urtwn_softc *, void *); 380 void urtwn_delete_key(struct ieee80211com *, 381 struct ieee80211_node *, struct ieee80211_key *); 382 void urtwn_delete_key_cb(struct urtwn_softc *, void *); 383 void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 384 void urtwn_rxeof(struct usbd_xfer *, void *, 385 usbd_status); 386 void urtwn_txeof(struct usbd_xfer *, void *, 387 usbd_status); 388 int urtwn_tx(void *, struct mbuf *, struct ieee80211_node *); 389 int urtwn_ioctl(struct ifnet *, u_long, caddr_t); 390 int urtwn_power_on(void *); 391 int urtwn_alloc_buffers(void *); 392 int urtwn_r92c_power_on(struct urtwn_softc *); 393 int urtwn_r92e_power_on(struct urtwn_softc *); 394 int urtwn_r88e_power_on(struct urtwn_softc *); 395 int urtwn_llt_init(struct urtwn_softc *, int); 396 int urtwn_fw_loadpage(void *, int, uint8_t *, int); 397 int urtwn_load_firmware(void *, u_char **, size_t *); 398 int urtwn_dma_init(void *); 399 void urtwn_mac_init(void *); 400 void urtwn_bb_init(void *); 401 int urtwn_init(void *); 402 void urtwn_stop(void *); 403 int urtwn_is_oactive(void *); 404 void urtwn_next_calib(void *); 405 void urtwn_cancel_calib(void *); 406 407 /* Aliases. */ 408 #define urtwn_bb_write urtwn_write_4 409 #define urtwn_bb_read urtwn_read_4 410 411 struct cfdriver urtwn_cd = { 412 NULL, "urtwn", DV_IFNET 413 }; 414 415 const struct cfattach urtwn_ca = { 416 sizeof(struct urtwn_softc), urtwn_match, urtwn_attach, urtwn_detach 417 }; 418 419 int 420 urtwn_match(struct device *parent, void *match, void *aux) 421 { 422 struct usb_attach_arg *uaa = aux; 423 424 if (uaa->iface == NULL || uaa->configno != 1) 425 return (UMATCH_NONE); 426 427 return ((urtwn_lookup(uaa->vendor, uaa->product) != NULL) ? 428 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 429 } 430 431 void 432 urtwn_attach(struct device *parent, struct device *self, void *aux) 433 { 434 struct urtwn_softc *sc = (struct urtwn_softc *)self; 435 struct usb_attach_arg *uaa = aux; 436 struct ifnet *ifp; 437 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 438 439 sc->sc_udev = uaa->device; 440 sc->sc_iface = uaa->iface; 441 442 sc->sc_sc.chip = urtwn_lookup(uaa->vendor, uaa->product)->chip; 443 444 usb_init_task(&sc->sc_task, urtwn_task, sc, USB_TASK_TYPE_GENERIC); 445 timeout_set(&sc->scan_to, urtwn_scan_to, sc); 446 timeout_set(&sc->calib_to, urtwn_calib_to, sc); 447 if (urtwn_open_pipes(sc) != 0) 448 return; 449 450 sc->amrr.amrr_min_success_threshold = 1; 451 sc->amrr.amrr_max_success_threshold = 10; 452 453 /* Attach the bus-agnostic driver. */ 454 sc->sc_sc.sc_ops.cookie = sc; 455 sc->sc_sc.sc_ops.write_1 = urtwn_write_1; 456 sc->sc_sc.sc_ops.write_2 = urtwn_write_2; 457 sc->sc_sc.sc_ops.write_4 = urtwn_write_4; 458 sc->sc_sc.sc_ops.read_1 = urtwn_read_1; 459 sc->sc_sc.sc_ops.read_2 = urtwn_read_2; 460 sc->sc_sc.sc_ops.read_4 = urtwn_read_4; 461 sc->sc_sc.sc_ops.tx = urtwn_tx; 462 sc->sc_sc.sc_ops.power_on = urtwn_power_on; 463 sc->sc_sc.sc_ops.dma_init = urtwn_dma_init; 464 sc->sc_sc.sc_ops.fw_loadpage = urtwn_fw_loadpage; 465 sc->sc_sc.sc_ops.load_firmware = urtwn_load_firmware; 466 sc->sc_sc.sc_ops.mac_init = urtwn_mac_init; 467 sc->sc_sc.sc_ops.bb_init = urtwn_bb_init; 468 sc->sc_sc.sc_ops.alloc_buffers = urtwn_alloc_buffers; 469 sc->sc_sc.sc_ops.init = urtwn_init; 470 sc->sc_sc.sc_ops.stop = urtwn_stop; 471 sc->sc_sc.sc_ops.is_oactive = urtwn_is_oactive; 472 sc->sc_sc.sc_ops.next_calib = urtwn_next_calib; 473 sc->sc_sc.sc_ops.cancel_calib = urtwn_cancel_calib; 474 sc->sc_sc.sc_ops.next_scan = urtwn_next_scan; 475 sc->sc_sc.sc_ops.cancel_scan = urtwn_cancel_scan; 476 sc->sc_sc.sc_ops.wait_async = urtwn_wait_async; 477 if (rtwn_attach(&sc->sc_dev, &sc->sc_sc) != 0) { 478 urtwn_close_pipes(sc); 479 return; 480 } 481 482 /* ifp is now valid */ 483 ifp = &sc->sc_sc.sc_ic.ic_if; 484 ifp->if_ioctl = urtwn_ioctl; 485 486 ic->ic_updateslot = urtwn_updateslot; 487 ic->ic_updateedca = urtwn_updateedca; 488 #ifdef notyet 489 ic->ic_set_key = urtwn_set_key; 490 ic->ic_delete_key = urtwn_delete_key; 491 #endif 492 /* Override state transition machine. */ 493 ic->ic_newstate = urtwn_newstate; 494 495 #if NBPFILTER > 0 496 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 497 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 498 499 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 500 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 501 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 502 503 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 504 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 505 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 506 #endif 507 } 508 509 int 510 urtwn_detach(struct device *self, int flags) 511 { 512 struct urtwn_softc *sc = (struct urtwn_softc *)self; 513 int s; 514 515 s = splusb(); 516 517 if (timeout_initialized(&sc->scan_to)) 518 timeout_del(&sc->scan_to); 519 if (timeout_initialized(&sc->calib_to)) 520 timeout_del(&sc->calib_to); 521 522 /* Wait for all async commands to complete. */ 523 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 524 525 usbd_ref_wait(sc->sc_udev); 526 527 rtwn_detach(&sc->sc_sc, flags); 528 529 /* Abort and close Tx/Rx pipes. */ 530 urtwn_close_pipes(sc); 531 532 /* Free Tx/Rx buffers. */ 533 urtwn_free_tx_list(sc); 534 urtwn_free_rx_list(sc); 535 splx(s); 536 537 return (0); 538 } 539 540 int 541 urtwn_open_pipes(struct urtwn_softc *sc) 542 { 543 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 544 uint8_t epaddr[R92C_MAX_EPOUT] = { 0, 0, 0 }; 545 uint8_t rx_no; 546 usb_interface_descriptor_t *id; 547 usb_endpoint_descriptor_t *ed; 548 int i, error, nrx = 0; 549 550 /* Find all bulk endpoints. */ 551 id = usbd_get_interface_descriptor(sc->sc_iface); 552 for (i = 0; i < id->bNumEndpoints; i++) { 553 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 554 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) 555 continue; 556 557 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 558 rx_no = ed->bEndpointAddress; 559 nrx++; 560 } else { 561 if (sc->ntx < R92C_MAX_EPOUT) 562 epaddr[sc->ntx] = ed->bEndpointAddress; 563 sc->ntx++; 564 } 565 } 566 if (nrx == 0) { 567 printf("%s: %d: invalid number of Rx bulk pipes\n", 568 sc->sc_dev.dv_xname, nrx); 569 return (EIO); 570 } 571 DPRINTF(("found %d bulk-out pipes\n", sc->ntx)); 572 if (sc->ntx == 0 || sc->ntx > R92C_MAX_EPOUT) { 573 printf("%s: %d: invalid number of Tx bulk pipes\n", 574 sc->sc_dev.dv_xname, sc->ntx); 575 return (EIO); 576 } 577 578 /* Open bulk-in pipe. */ 579 error = usbd_open_pipe(sc->sc_iface, rx_no, 0, &sc->rx_pipe); 580 if (error != 0) { 581 printf("%s: could not open Rx bulk pipe\n", 582 sc->sc_dev.dv_xname); 583 goto fail; 584 } 585 586 /* Open bulk-out pipes (up to 3). */ 587 for (i = 0; i < sc->ntx; i++) { 588 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 0, 589 &sc->tx_pipe[i]); 590 if (error != 0) { 591 printf("%s: could not open Tx bulk pipe 0x%02x\n", 592 sc->sc_dev.dv_xname, epaddr[i]); 593 goto fail; 594 } 595 } 596 597 /* Map 802.11 access categories to USB pipes. */ 598 sc->ac2idx[EDCA_AC_BK] = 599 sc->ac2idx[EDCA_AC_BE] = (sc->ntx == 3) ? 2 : ((sc->ntx == 2) ? 1 : 0); 600 sc->ac2idx[EDCA_AC_VI] = (sc->ntx == 3) ? 1 : 0; 601 sc->ac2idx[EDCA_AC_VO] = 0; /* Always use highest prio. */ 602 603 if (error != 0) 604 fail: urtwn_close_pipes(sc); 605 return (error); 606 } 607 608 void 609 urtwn_close_pipes(struct urtwn_softc *sc) 610 { 611 int i; 612 613 /* Close Rx pipe. */ 614 if (sc->rx_pipe != NULL) { 615 usbd_abort_pipe(sc->rx_pipe); 616 usbd_close_pipe(sc->rx_pipe); 617 } 618 /* Close Tx pipes. */ 619 for (i = 0; i < R92C_MAX_EPOUT; i++) { 620 if (sc->tx_pipe[i] == NULL) 621 continue; 622 usbd_abort_pipe(sc->tx_pipe[i]); 623 usbd_close_pipe(sc->tx_pipe[i]); 624 } 625 } 626 627 int 628 urtwn_alloc_rx_list(struct urtwn_softc *sc) 629 { 630 struct urtwn_rx_data *data; 631 int i, error = 0; 632 633 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 634 data = &sc->rx_data[i]; 635 636 data->sc = sc; /* Backpointer for callbacks. */ 637 638 data->xfer = usbd_alloc_xfer(sc->sc_udev); 639 if (data->xfer == NULL) { 640 printf("%s: could not allocate xfer\n", 641 sc->sc_dev.dv_xname); 642 error = ENOMEM; 643 break; 644 } 645 data->buf = usbd_alloc_buffer(data->xfer, URTWN_RXBUFSZ); 646 if (data->buf == NULL) { 647 printf("%s: could not allocate xfer buffer\n", 648 sc->sc_dev.dv_xname); 649 error = ENOMEM; 650 break; 651 } 652 } 653 if (error != 0) 654 urtwn_free_rx_list(sc); 655 return (error); 656 } 657 658 void 659 urtwn_free_rx_list(struct urtwn_softc *sc) 660 { 661 int i; 662 663 /* NB: Caller must abort pipe first. */ 664 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 665 if (sc->rx_data[i].xfer != NULL) 666 usbd_free_xfer(sc->rx_data[i].xfer); 667 sc->rx_data[i].xfer = NULL; 668 } 669 } 670 671 int 672 urtwn_alloc_tx_list(struct urtwn_softc *sc) 673 { 674 struct urtwn_tx_data *data; 675 int i, error = 0; 676 677 TAILQ_INIT(&sc->tx_free_list); 678 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 679 data = &sc->tx_data[i]; 680 681 data->sc = sc; /* Backpointer for callbacks. */ 682 683 data->xfer = usbd_alloc_xfer(sc->sc_udev); 684 if (data->xfer == NULL) { 685 printf("%s: could not allocate xfer\n", 686 sc->sc_dev.dv_xname); 687 error = ENOMEM; 688 break; 689 } 690 data->buf = usbd_alloc_buffer(data->xfer, URTWN_TXBUFSZ); 691 if (data->buf == NULL) { 692 printf("%s: could not allocate xfer buffer\n", 693 sc->sc_dev.dv_xname); 694 error = ENOMEM; 695 break; 696 } 697 /* Append this Tx buffer to our free list. */ 698 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 699 } 700 if (error != 0) 701 urtwn_free_tx_list(sc); 702 return (error); 703 } 704 705 void 706 urtwn_free_tx_list(struct urtwn_softc *sc) 707 { 708 int i; 709 710 /* NB: Caller must abort pipe first. */ 711 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 712 if (sc->tx_data[i].xfer != NULL) 713 usbd_free_xfer(sc->tx_data[i].xfer); 714 sc->tx_data[i].xfer = NULL; 715 } 716 } 717 718 void 719 urtwn_task(void *arg) 720 { 721 struct urtwn_softc *sc = arg; 722 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 723 struct urtwn_host_cmd *cmd; 724 int s; 725 726 /* Process host commands. */ 727 s = splusb(); 728 while (ring->next != ring->cur) { 729 cmd = &ring->cmd[ring->next]; 730 splx(s); 731 /* Invoke callback. */ 732 cmd->cb(sc, cmd->data); 733 s = splusb(); 734 ring->queued--; 735 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 736 } 737 splx(s); 738 } 739 740 void 741 urtwn_do_async(struct urtwn_softc *sc, 742 void (*cb)(struct urtwn_softc *, void *), void *arg, int len) 743 { 744 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 745 struct urtwn_host_cmd *cmd; 746 int s; 747 748 s = splusb(); 749 cmd = &ring->cmd[ring->cur]; 750 cmd->cb = cb; 751 KASSERT(len <= sizeof(cmd->data)); 752 memcpy(cmd->data, arg, len); 753 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 754 755 /* If there is no pending command already, schedule a task. */ 756 if (++ring->queued == 1) 757 usb_add_task(sc->sc_udev, &sc->sc_task); 758 splx(s); 759 } 760 761 void 762 urtwn_wait_async(void *cookie) 763 { 764 struct urtwn_softc *sc = cookie; 765 int s; 766 767 s = splusb(); 768 /* Wait for all queued asynchronous commands to complete. */ 769 usb_wait_task(sc->sc_udev, &sc->sc_task); 770 splx(s); 771 } 772 773 int 774 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 775 int len) 776 { 777 usb_device_request_t req; 778 779 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 780 req.bRequest = R92C_REQ_REGS; 781 USETW(req.wValue, addr); 782 USETW(req.wIndex, 0); 783 USETW(req.wLength, len); 784 return (usbd_do_request(sc->sc_udev, &req, buf)); 785 } 786 787 void 788 urtwn_write_1(void *cookie, uint16_t addr, uint8_t val) 789 { 790 struct urtwn_softc *sc = cookie; 791 792 urtwn_write_region_1(sc, addr, &val, 1); 793 } 794 795 void 796 urtwn_write_2(void *cookie, uint16_t addr, uint16_t val) 797 { 798 struct urtwn_softc *sc = cookie; 799 800 val = htole16(val); 801 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 802 } 803 804 void 805 urtwn_write_4(void *cookie, uint16_t addr, uint32_t val) 806 { 807 struct urtwn_softc *sc = cookie; 808 809 val = htole32(val); 810 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 811 } 812 813 int 814 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 815 int len) 816 { 817 usb_device_request_t req; 818 819 req.bmRequestType = UT_READ_VENDOR_DEVICE; 820 req.bRequest = R92C_REQ_REGS; 821 USETW(req.wValue, addr); 822 USETW(req.wIndex, 0); 823 USETW(req.wLength, len); 824 return (usbd_do_request(sc->sc_udev, &req, buf)); 825 } 826 827 uint8_t 828 urtwn_read_1(void *cookie, uint16_t addr) 829 { 830 struct urtwn_softc *sc = cookie; 831 uint8_t val; 832 833 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 834 return (0xff); 835 return (val); 836 } 837 838 uint16_t 839 urtwn_read_2(void *cookie, uint16_t addr) 840 { 841 struct urtwn_softc *sc = cookie; 842 uint16_t val; 843 844 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 845 return (0xffff); 846 return (letoh16(val)); 847 } 848 849 uint32_t 850 urtwn_read_4(void *cookie, uint16_t addr) 851 { 852 struct urtwn_softc *sc = cookie; 853 uint32_t val; 854 855 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 856 return (0xffffffff); 857 return (letoh32(val)); 858 } 859 860 int 861 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 862 { 863 int ntries; 864 865 urtwn_write_4(sc, R92C_LLT_INIT, 866 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 867 SM(R92C_LLT_INIT_ADDR, addr) | 868 SM(R92C_LLT_INIT_DATA, data)); 869 /* Wait for write operation to complete. */ 870 for (ntries = 0; ntries < 20; ntries++) { 871 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 872 R92C_LLT_INIT_OP_NO_ACTIVE) 873 return (0); 874 DELAY(5); 875 } 876 return (ETIMEDOUT); 877 } 878 879 void 880 urtwn_calib_to(void *arg) 881 { 882 struct urtwn_softc *sc = arg; 883 884 if (usbd_is_dying(sc->sc_udev)) 885 return; 886 887 usbd_ref_incr(sc->sc_udev); 888 889 /* Do it in a process context. */ 890 urtwn_do_async(sc, urtwn_calib_cb, NULL, 0); 891 892 usbd_ref_decr(sc->sc_udev); 893 } 894 895 /* ARGSUSED */ 896 void 897 urtwn_calib_cb(struct urtwn_softc *sc, void *arg) 898 { 899 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 900 int s; 901 902 s = splnet(); 903 if (ic->ic_opmode == IEEE80211_M_STA) { 904 ieee80211_amrr_choose(&sc->amrr, ic->ic_bss, &sc->amn); 905 } 906 splx(s); 907 908 rtwn_calib(&sc->sc_sc); 909 } 910 911 void 912 urtwn_next_calib(void *cookie) 913 { 914 struct urtwn_softc *sc = cookie; 915 916 if (!usbd_is_dying(sc->sc_udev)) 917 timeout_add_sec(&sc->calib_to, 2); 918 } 919 920 void 921 urtwn_cancel_calib(void *cookie) 922 { 923 struct urtwn_softc *sc = cookie; 924 925 if (timeout_initialized(&sc->calib_to)) 926 timeout_del(&sc->calib_to); 927 } 928 929 void 930 urtwn_scan_to(void *arg) 931 { 932 struct urtwn_softc *sc = arg; 933 934 if (usbd_is_dying(sc->sc_udev)) 935 return; 936 937 usbd_ref_incr(sc->sc_udev); 938 rtwn_next_scan(&sc->sc_sc); 939 usbd_ref_decr(sc->sc_udev); 940 } 941 942 void 943 urtwn_next_scan(void *arg) 944 { 945 struct urtwn_softc *sc = arg; 946 947 if (!usbd_is_dying(sc->sc_udev)) 948 timeout_add_msec(&sc->scan_to, 200); 949 } 950 951 void 952 urtwn_cancel_scan(void *cookie) 953 { 954 struct urtwn_softc *sc = cookie; 955 956 if (timeout_initialized(&sc->scan_to)) 957 timeout_del(&sc->scan_to); 958 } 959 960 int 961 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 962 { 963 struct rtwn_softc *sc_sc = ic->ic_softc; 964 struct device *self = sc_sc->sc_pdev; 965 struct urtwn_softc *sc = (struct urtwn_softc *)self; 966 struct urtwn_cmd_newstate cmd; 967 968 /* Do it in a process context. */ 969 cmd.state = nstate; 970 cmd.arg = arg; 971 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 972 return (0); 973 } 974 975 void 976 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 977 { 978 struct urtwn_cmd_newstate *cmd = arg; 979 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 980 981 rtwn_newstate(ic, cmd->state, cmd->arg); 982 } 983 984 void 985 urtwn_updateslot(struct ieee80211com *ic) 986 { 987 struct rtwn_softc *sc_sc = ic->ic_softc; 988 struct device *self = sc_sc->sc_pdev; 989 struct urtwn_softc *sc = (struct urtwn_softc *)self; 990 991 /* Do it in a process context. */ 992 urtwn_do_async(sc, urtwn_updateslot_cb, NULL, 0); 993 } 994 995 /* ARGSUSED */ 996 void 997 urtwn_updateslot_cb(struct urtwn_softc *sc, void *arg) 998 { 999 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1000 1001 rtwn_updateslot(ic); 1002 } 1003 1004 void 1005 urtwn_updateedca(struct ieee80211com *ic) 1006 { 1007 struct rtwn_softc *sc_sc = ic->ic_softc; 1008 struct device *self = sc_sc->sc_pdev; 1009 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1010 1011 /* Do it in a process context. */ 1012 urtwn_do_async(sc, urtwn_updateedca_cb, NULL, 0); 1013 } 1014 1015 /* ARGSUSED */ 1016 void 1017 urtwn_updateedca_cb(struct urtwn_softc *sc, void *arg) 1018 { 1019 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1020 1021 rtwn_updateedca(ic); 1022 } 1023 1024 int 1025 urtwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1026 struct ieee80211_key *k) 1027 { 1028 struct rtwn_softc *sc_sc = ic->ic_softc; 1029 struct device *self = sc_sc->sc_pdev; 1030 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1031 struct urtwn_cmd_key cmd; 1032 1033 /* Defer setting of WEP keys until interface is brought up. */ 1034 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 1035 (IFF_UP | IFF_RUNNING)) 1036 return (0); 1037 1038 /* Do it in a process context. */ 1039 cmd.key = *k; 1040 cmd.ni = ni; 1041 urtwn_do_async(sc, urtwn_set_key_cb, &cmd, sizeof(cmd)); 1042 return (0); 1043 } 1044 1045 void 1046 urtwn_set_key_cb(struct urtwn_softc *sc, void *arg) 1047 { 1048 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1049 struct urtwn_cmd_key *cmd = arg; 1050 1051 rtwn_set_key(ic, cmd->ni, &cmd->key); 1052 } 1053 1054 void 1055 urtwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1056 struct ieee80211_key *k) 1057 { 1058 struct rtwn_softc *sc_sc = ic->ic_softc; 1059 struct device *self = sc_sc->sc_pdev; 1060 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1061 struct urtwn_cmd_key cmd; 1062 1063 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 1064 ic->ic_state != IEEE80211_S_RUN) 1065 return; /* Nothing to do. */ 1066 1067 /* Do it in a process context. */ 1068 cmd.key = *k; 1069 cmd.ni = ni; 1070 urtwn_do_async(sc, urtwn_delete_key_cb, &cmd, sizeof(cmd)); 1071 } 1072 1073 void 1074 urtwn_delete_key_cb(struct urtwn_softc *sc, void *arg) 1075 { 1076 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1077 struct urtwn_cmd_key *cmd = arg; 1078 1079 rtwn_delete_key(ic, cmd->ni, &cmd->key); 1080 } 1081 1082 void 1083 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 1084 { 1085 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1086 struct ifnet *ifp = &ic->ic_if; 1087 struct ieee80211_rxinfo rxi; 1088 struct ieee80211_frame *wh; 1089 struct ieee80211_node *ni; 1090 struct r92c_rx_desc_usb *rxd; 1091 uint32_t rxdw0, rxdw3; 1092 struct mbuf *m; 1093 uint8_t rate; 1094 int8_t rssi = 0; 1095 int s, infosz; 1096 1097 rxd = (struct r92c_rx_desc_usb *)buf; 1098 rxdw0 = letoh32(rxd->rxdw0); 1099 rxdw3 = letoh32(rxd->rxdw3); 1100 1101 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1102 /* 1103 * This should not happen since we setup our Rx filter 1104 * to not receive these frames. 1105 */ 1106 ifp->if_ierrors++; 1107 return; 1108 } 1109 if (__predict_false(pktlen < sizeof(*wh) || pktlen > MCLBYTES)) { 1110 ifp->if_ierrors++; 1111 return; 1112 } 1113 1114 rate = MS(rxdw3, R92C_RXDW3_RATE); 1115 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1116 1117 /* Get RSSI from PHY status descriptor if present. */ 1118 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1119 rssi = rtwn_get_rssi(&sc->sc_sc, rate, &rxd[1]); 1120 /* Update our average RSSI. */ 1121 rtwn_update_avgrssi(&sc->sc_sc, rate, rssi); 1122 } 1123 1124 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 1125 pktlen, rate, infosz, rssi)); 1126 1127 MGETHDR(m, M_DONTWAIT, MT_DATA); 1128 if (__predict_false(m == NULL)) { 1129 ifp->if_ierrors++; 1130 return; 1131 } 1132 if (pktlen > MHLEN) { 1133 MCLGET(m, M_DONTWAIT); 1134 if (__predict_false(!(m->m_flags & M_EXT))) { 1135 ifp->if_ierrors++; 1136 m_freem(m); 1137 return; 1138 } 1139 } 1140 /* Finalize mbuf. */ 1141 wh = (struct ieee80211_frame *)((uint8_t *)&rxd[1] + infosz); 1142 memcpy(mtod(m, uint8_t *), wh, pktlen); 1143 m->m_pkthdr.len = m->m_len = pktlen; 1144 1145 s = splnet(); 1146 #if NBPFILTER > 0 1147 if (__predict_false(sc->sc_drvbpf != NULL)) { 1148 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1149 struct mbuf mb; 1150 1151 tap->wr_flags = 0; 1152 /* Map HW rate index to 802.11 rate. */ 1153 if (!(rxdw3 & R92C_RXDW3_HT)) { 1154 switch (rate) { 1155 /* CCK. */ 1156 case 0: tap->wr_rate = 2; break; 1157 case 1: tap->wr_rate = 4; break; 1158 case 2: tap->wr_rate = 11; break; 1159 case 3: tap->wr_rate = 22; break; 1160 /* OFDM. */ 1161 case 4: tap->wr_rate = 12; break; 1162 case 5: tap->wr_rate = 18; break; 1163 case 6: tap->wr_rate = 24; break; 1164 case 7: tap->wr_rate = 36; break; 1165 case 8: tap->wr_rate = 48; break; 1166 case 9: tap->wr_rate = 72; break; 1167 case 10: tap->wr_rate = 96; break; 1168 case 11: tap->wr_rate = 108; break; 1169 } 1170 if (rate <= 3) 1171 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1172 } else if (rate >= 12) { /* MCS0~15. */ 1173 /* Bit 7 set means HT MCS instead of rate. */ 1174 tap->wr_rate = 0x80 | (rate - 12); 1175 } 1176 tap->wr_dbm_antsignal = rssi; 1177 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1178 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1179 1180 mb.m_data = (caddr_t)tap; 1181 mb.m_len = sc->sc_rxtap_len; 1182 mb.m_next = m; 1183 mb.m_nextpkt = NULL; 1184 mb.m_type = 0; 1185 mb.m_flags = 0; 1186 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1187 } 1188 #endif 1189 1190 ni = ieee80211_find_rxnode(ic, wh); 1191 rxi.rxi_flags = 0; 1192 rxi.rxi_rssi = rssi; 1193 rxi.rxi_tstamp = 0; /* Unused. */ 1194 ieee80211_input(ifp, m, ni, &rxi); 1195 /* Node is no longer needed. */ 1196 ieee80211_release_node(ic, ni); 1197 splx(s); 1198 } 1199 1200 void 1201 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, 1202 usbd_status status) 1203 { 1204 struct urtwn_rx_data *data = priv; 1205 struct urtwn_softc *sc = data->sc; 1206 struct r92c_rx_desc_usb *rxd; 1207 uint32_t rxdw0; 1208 uint8_t *buf; 1209 int len, totlen, pktlen, infosz, npkts, error, align; 1210 1211 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1212 DPRINTF(("RX status=%d\n", status)); 1213 if (status == USBD_STALLED) 1214 usbd_clear_endpoint_stall_async(sc->rx_pipe); 1215 if (status != USBD_CANCELLED) 1216 goto resubmit; 1217 return; 1218 } 1219 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 1220 1221 if (__predict_false(len < sizeof(*rxd))) { 1222 DPRINTF(("xfer too short %d\n", len)); 1223 goto resubmit; 1224 } 1225 buf = data->buf; 1226 1227 /* Get the number of encapsulated frames. */ 1228 rxd = (struct r92c_rx_desc_usb *)buf; 1229 npkts = MS(letoh32(rxd->rxdw2), R92C_RXDW2_PKTCNT); 1230 DPRINTFN(4, ("Rx %d frames in one chunk\n", npkts)); 1231 1232 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1233 int ntries, type; 1234 struct r88e_tx_rpt_ccx *rxstat; 1235 1236 type = MS(letoh32(rxd->rxdw3), R88E_RXDW3_RPT); 1237 1238 if (type == R88E_RXDW3_RPT_TX1) { 1239 buf += sizeof(struct r92c_rx_desc_usb); 1240 rxstat = (struct r88e_tx_rpt_ccx *)buf; 1241 ntries = MS(letoh32(rxstat->rptb2), 1242 R88E_RPTB2_RETRY_CNT); 1243 1244 if (rxstat->rptb1 & R88E_RPTB1_PKT_OK) 1245 sc->amn.amn_txcnt++; 1246 if (ntries > 0) 1247 sc->amn.amn_retrycnt++; 1248 1249 goto resubmit; 1250 } 1251 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 1252 int type; 1253 struct r92e_c2h_tx_rpt *txrpt; 1254 1255 if (letoh32(rxd->rxdw2) & R92E_RXDW2_RPT_C2H) { 1256 if (len < sizeof(struct r92c_rx_desc_usb) + 2) 1257 goto resubmit; 1258 1259 type = buf[sizeof(struct r92c_rx_desc_usb)]; 1260 switch (type) { 1261 case R92C_C2HEVT_TX_REPORT: 1262 buf += sizeof(struct r92c_rx_desc_usb) + 2; 1263 txrpt = (struct r92e_c2h_tx_rpt *)buf; 1264 if (MS(txrpt->rptb2, R92E_RPTB2_RETRY_CNT) > 0) 1265 sc->amn.amn_retrycnt++; 1266 if ((txrpt->rptb0 & (R92E_RPTB0_RETRY_OVER | 1267 R92E_RPTB0_LIFE_EXPIRE)) == 0) 1268 sc->amn.amn_txcnt++; 1269 break; 1270 default: 1271 break; 1272 } 1273 goto resubmit; 1274 } 1275 } 1276 1277 align = (sc->sc_sc.chip & RTWN_CHIP_92E ? 7 : 127); 1278 1279 /* Process all of them. */ 1280 while (npkts-- > 0) { 1281 if (__predict_false(len < sizeof(*rxd))) 1282 break; 1283 rxd = (struct r92c_rx_desc_usb *)buf; 1284 rxdw0 = letoh32(rxd->rxdw0); 1285 1286 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1287 if (__predict_false(pktlen == 0)) 1288 break; 1289 1290 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1291 1292 /* Make sure everything fits in xfer. */ 1293 totlen = sizeof(*rxd) + infosz + pktlen; 1294 if (__predict_false(totlen > len)) 1295 break; 1296 1297 /* Process 802.11 frame. */ 1298 urtwn_rx_frame(sc, buf, pktlen); 1299 1300 /* Handle chunk alignment. */ 1301 totlen = (totlen + align) & ~align; 1302 buf += totlen; 1303 len -= totlen; 1304 } 1305 1306 resubmit: 1307 /* Setup a new transfer. */ 1308 usbd_setup_xfer(xfer, sc->rx_pipe, data, data->buf, URTWN_RXBUFSZ, 1309 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, urtwn_rxeof); 1310 error = usbd_transfer(data->xfer); 1311 if (error != 0 && error != USBD_IN_PROGRESS) 1312 DPRINTF(("could not set up new transfer: %d\n", error)); 1313 } 1314 1315 void 1316 urtwn_txeof(struct usbd_xfer *xfer, void *priv, 1317 usbd_status status) 1318 { 1319 struct urtwn_tx_data *data = priv; 1320 struct urtwn_softc *sc = data->sc; 1321 struct ifnet *ifp = &sc->sc_sc.sc_ic.ic_if; 1322 int s; 1323 1324 s = splnet(); 1325 /* Put this Tx buffer back to our free list. */ 1326 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1327 1328 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1329 DPRINTF(("TX status=%d\n", status)); 1330 if (status == USBD_STALLED) 1331 usbd_clear_endpoint_stall_async(data->pipe); 1332 ifp->if_oerrors++; 1333 splx(s); 1334 return; 1335 } 1336 sc->sc_sc.sc_tx_timer = 0; 1337 1338 /* We just released a Tx buffer, notify Tx. */ 1339 if (ifq_is_oactive(&ifp->if_snd)) { 1340 ifq_clr_oactive(&ifp->if_snd); 1341 rtwn_start(ifp); 1342 } 1343 splx(s); 1344 } 1345 1346 void 1347 urtwn_tx_fill_desc(struct urtwn_softc *sc, uint8_t **txdp, struct mbuf *m, 1348 struct ieee80211_frame *wh, struct ieee80211_key *k, 1349 struct ieee80211_node *ni) 1350 { 1351 struct r92c_tx_desc_usb *txd; 1352 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1353 uint8_t raid, type; 1354 1355 txd = (struct r92c_tx_desc_usb *)*txdp; 1356 (*txdp) += sizeof(*txd); 1357 memset(txd, 0, sizeof(*txd)); 1358 1359 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1360 1361 txd->txdw0 |= htole32( 1362 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 1363 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1364 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1365 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1366 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1367 1368 #ifdef notyet 1369 if (k != NULL) { 1370 switch (k->k_cipher) { 1371 case IEEE80211_CIPHER_WEP40: 1372 case IEEE80211_CIPHER_WEP104: 1373 case IEEE80211_CIPHER_TKIP: 1374 cipher = R92C_TXDW1_CIPHER_RC4; 1375 break; 1376 case IEEE80211_CIPHER_CCMP: 1377 cipher = R92C_TXDW1_CIPHER_AES; 1378 break; 1379 default: 1380 cipher = R92C_TXDW1_CIPHER_NONE; 1381 } 1382 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 1383 } 1384 #endif 1385 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1386 type == IEEE80211_FC0_TYPE_DATA) { 1387 if (ic->ic_curmode == IEEE80211_MODE_11B || 1388 (sc->sc_sc.sc_flags & RTWN_FLAG_FORCE_RAID_11B)) 1389 raid = R92C_RAID_11B; 1390 else 1391 raid = R92C_RAID_11BG; 1392 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1393 txd->txdw1 |= htole32( 1394 SM(R88E_TXDW1_MACID, R92C_MACID_BSS) | 1395 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1396 SM(R92C_TXDW1_RAID, raid)); 1397 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1398 /* Request TX status report for AMRR */ 1399 txd->txdw2 |= htole32(R92C_TXDW2_CCX_RPT); 1400 } else { 1401 txd->txdw1 |= htole32( 1402 SM(R92C_TXDW1_MACID, R92C_MACID_BSS) | 1403 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1404 SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1405 } 1406 1407 if (m->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 1408 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1409 R92C_TXDW4_HWRTSEN); 1410 } else if (ic->ic_flags & IEEE80211_F_USEPROT) { 1411 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1412 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1413 R92C_TXDW4_HWRTSEN); 1414 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1415 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1416 R92C_TXDW4_HWRTSEN); 1417 } 1418 } 1419 txd->txdw5 |= htole32(0x0001ff00); 1420 1421 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1422 /* Use AMRR */ 1423 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1424 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 1425 ni->ni_txrate)); 1426 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1427 ni->ni_txrate)); 1428 } else { 1429 /* Send RTS at OFDM24 and data at OFDM54. */ 1430 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1431 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1432 } 1433 } else { 1434 txd->txdw1 |= htole32( 1435 SM(R92C_TXDW1_MACID, 0) | 1436 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1437 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1438 1439 /* Force CCK1. */ 1440 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1441 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1442 } 1443 /* Set sequence number (already little endian). */ 1444 txd->txdseq |= (*(uint16_t *)wh->i_seq) >> IEEE80211_SEQ_SEQ_SHIFT; 1445 1446 if (!ieee80211_has_qos(wh)) { 1447 /* Use HW sequence numbering for non-QoS frames. */ 1448 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1449 txd->txdseq |= htole16(R92C_TXDW3_HWSEQEN); 1450 } else 1451 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1452 } 1453 1454 void 1455 urtwn_tx_fill_desc_gen2(struct urtwn_softc *sc, uint8_t **txdp, struct mbuf *m, 1456 struct ieee80211_frame *wh, struct ieee80211_key *k, 1457 struct ieee80211_node *ni) 1458 { 1459 struct r92e_tx_desc_usb *txd; 1460 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1461 uint8_t raid, type; 1462 1463 txd = (struct r92e_tx_desc_usb *)*txdp; 1464 (*txdp) += sizeof(*txd); 1465 memset(txd, 0, sizeof(*txd)); 1466 1467 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1468 1469 txd->txdw0 |= htole32( 1470 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 1471 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1472 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1473 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1474 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1475 1476 #ifdef notyet 1477 /* cipher */ 1478 #endif 1479 1480 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1481 type == IEEE80211_FC0_TYPE_DATA) { 1482 if (ic->ic_curmode == IEEE80211_MODE_11B || 1483 (sc->sc_sc.sc_flags & RTWN_FLAG_FORCE_RAID_11B)) 1484 raid = R92E_RAID_11B; 1485 else 1486 raid = R92E_RAID_11BG; 1487 txd->txdw1 |= htole32( 1488 SM(R92E_TXDW1_MACID, R92C_MACID_BSS) | 1489 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1490 SM(R92C_TXDW1_RAID, raid)); 1491 /* Request TX status report for AMRR */ 1492 txd->txdw2 |= htole32(R92C_TXDW2_CCX_RPT | R88E_TXDW2_AGGBK); 1493 1494 if (m->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 1495 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1496 R92C_TXDW4_HWRTSEN); 1497 } else if (ic->ic_flags & IEEE80211_F_USEPROT) { 1498 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1499 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1500 R92C_TXDW4_HWRTSEN); 1501 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1502 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1503 R92C_TXDW4_HWRTSEN); 1504 } 1505 } 1506 txd->txdw5 |= htole32(0x0001ff00); 1507 1508 /* Use AMRR */ 1509 txd->txdw3 |= htole32(R92E_TXDW3_DRVRATE); 1510 txd->txdw4 |= htole32(SM(R92E_TXDW4_RTSRATE, ni->ni_txrate)); 1511 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATE, ni->ni_txrate)); 1512 } else { 1513 txd->txdw1 |= htole32( 1514 SM(R92E_TXDW1_MACID, 0) | 1515 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1516 SM(R92C_TXDW1_RAID, R92E_RAID_11B)); 1517 1518 /* Force CCK1. */ 1519 txd->txdw3 |= htole32(R92E_TXDW3_DRVRATE); 1520 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATE, 0)); 1521 } 1522 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATEFB, 0x1f)); 1523 1524 txd->txdseq2 |= htole16(SM(R92E_TXDSEQ2_HWSEQ, *(uint16_t *)wh->i_seq)); 1525 1526 if (!ieee80211_has_qos(wh)) { 1527 /* Use HW sequence numbering for non-QoS frames. */ 1528 txd->txdw7 |= htole16(R92C_TXDW3_HWSEQEN); 1529 } 1530 } 1531 1532 int 1533 urtwn_tx(void *cookie, struct mbuf *m, struct ieee80211_node *ni) 1534 { 1535 struct urtwn_softc *sc = cookie; 1536 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1537 struct ieee80211_frame *wh; 1538 struct ieee80211_key *k = NULL; 1539 struct urtwn_tx_data *data; 1540 struct usbd_pipe *pipe; 1541 uint16_t qos, sum; 1542 uint8_t tid, qid; 1543 int i, xferlen, error; 1544 uint8_t *txdp; 1545 1546 wh = mtod(m, struct ieee80211_frame *); 1547 1548 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1549 k = ieee80211_get_txkey(ic, wh, ni); 1550 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1551 return (ENOBUFS); 1552 wh = mtod(m, struct ieee80211_frame *); 1553 } 1554 1555 if (ieee80211_has_qos(wh)) { 1556 qos = ieee80211_get_qos(wh); 1557 tid = qos & IEEE80211_QOS_TID; 1558 qid = ieee80211_up_to_ac(ic, tid); 1559 } else if ((wh->i_fc[1] & IEEE80211_FC0_TYPE_MASK) 1560 != IEEE80211_FC0_TYPE_DATA) { 1561 /* Use AC VO for management frames. */ 1562 qid = EDCA_AC_VO; 1563 } else 1564 qid = EDCA_AC_BE; 1565 1566 /* Get the USB pipe to use for this AC. */ 1567 pipe = sc->tx_pipe[sc->ac2idx[qid]]; 1568 1569 /* Grab a Tx buffer from our free list. */ 1570 data = TAILQ_FIRST(&sc->tx_free_list); 1571 TAILQ_REMOVE(&sc->tx_free_list, data, next); 1572 1573 /* Fill Tx descriptor. */ 1574 txdp = data->buf; 1575 if (sc->sc_sc.chip & RTWN_CHIP_92E) 1576 urtwn_tx_fill_desc_gen2(sc, &txdp, m, wh, k, ni); 1577 else 1578 urtwn_tx_fill_desc(sc, &txdp, m, wh, k, ni); 1579 1580 /* Compute Tx descriptor checksum. */ 1581 sum = 0; 1582 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 1583 sum ^= ((uint16_t *)data->buf)[i]; 1584 ((uint16_t *)data->buf)[R92C_TXDESC_SUMOFFSET] = sum; 1585 1586 #if NBPFILTER > 0 1587 if (__predict_false(sc->sc_drvbpf != NULL)) { 1588 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1589 struct mbuf mb; 1590 1591 tap->wt_flags = 0; 1592 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1593 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1594 1595 mb.m_data = (caddr_t)tap; 1596 mb.m_len = sc->sc_txtap_len; 1597 mb.m_next = m; 1598 mb.m_nextpkt = NULL; 1599 mb.m_type = 0; 1600 mb.m_flags = 0; 1601 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1602 } 1603 #endif 1604 1605 xferlen = (txdp - data->buf) + m->m_pkthdr.len; 1606 m_copydata(m, 0, m->m_pkthdr.len, txdp); 1607 m_freem(m); 1608 1609 data->pipe = pipe; 1610 usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen, 1611 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTWN_TX_TIMEOUT, 1612 urtwn_txeof); 1613 error = usbd_transfer(data->xfer); 1614 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) { 1615 /* Put this Tx buffer back to our free list. */ 1616 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1617 return (error); 1618 } 1619 ieee80211_release_node(ic, ni); 1620 return (0); 1621 } 1622 1623 int 1624 urtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1625 { 1626 struct rtwn_softc *sc_sc = ifp->if_softc; 1627 struct device *self = sc_sc->sc_pdev; 1628 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1629 int error; 1630 1631 if (usbd_is_dying(sc->sc_udev)) 1632 return ENXIO; 1633 1634 usbd_ref_incr(sc->sc_udev); 1635 error = rtwn_ioctl(ifp, cmd, data); 1636 usbd_ref_decr(sc->sc_udev); 1637 1638 return (error); 1639 } 1640 1641 int 1642 urtwn_r92c_power_on(struct urtwn_softc *sc) 1643 { 1644 uint32_t reg; 1645 int ntries; 1646 1647 /* Wait for autoload done bit. */ 1648 for (ntries = 0; ntries < 1000; ntries++) { 1649 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 1650 break; 1651 DELAY(5); 1652 } 1653 if (ntries == 1000) { 1654 printf("%s: timeout waiting for chip autoload\n", 1655 sc->sc_dev.dv_xname); 1656 return (ETIMEDOUT); 1657 } 1658 1659 /* Unlock ISO/CLK/Power control register. */ 1660 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 1661 /* Move SPS into PWM mode. */ 1662 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 1663 DELAY(100); 1664 1665 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 1666 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 1667 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 1668 reg | R92C_LDOV12D_CTRL_LDV12_EN); 1669 DELAY(100); 1670 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 1671 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 1672 ~R92C_SYS_ISO_CTRL_MD2PP); 1673 } 1674 1675 /* Auto enable WLAN. */ 1676 urtwn_write_2(sc, R92C_APS_FSMCO, 1677 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1678 for (ntries = 0; ntries < 1000; ntries++) { 1679 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1680 R92C_APS_FSMCO_APFM_ONMAC)) 1681 break; 1682 DELAY(5); 1683 } 1684 if (ntries == 1000) { 1685 printf("%s: timeout waiting for MAC auto ON\n", 1686 sc->sc_dev.dv_xname); 1687 return (ETIMEDOUT); 1688 } 1689 1690 /* Enable radio, GPIO and LED functions. */ 1691 urtwn_write_2(sc, R92C_APS_FSMCO, 1692 R92C_APS_FSMCO_AFSM_HSUS | 1693 R92C_APS_FSMCO_PDN_EN | 1694 R92C_APS_FSMCO_PFM_ALDN); 1695 /* Release RF digital isolation. */ 1696 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1697 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 1698 1699 /* Initialize MAC. */ 1700 urtwn_write_1(sc, R92C_APSD_CTRL, 1701 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 1702 for (ntries = 0; ntries < 200; ntries++) { 1703 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 1704 R92C_APSD_CTRL_OFF_STATUS)) 1705 break; 1706 DELAY(5); 1707 } 1708 if (ntries == 200) { 1709 printf("%s: timeout waiting for MAC initialization\n", 1710 sc->sc_dev.dv_xname); 1711 return (ETIMEDOUT); 1712 } 1713 1714 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1715 reg = urtwn_read_2(sc, R92C_CR); 1716 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1717 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1718 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 1719 R92C_CR_ENSEC; 1720 urtwn_write_2(sc, R92C_CR, reg); 1721 1722 urtwn_write_1(sc, 0xfe10, 0x19); 1723 return (0); 1724 } 1725 1726 int 1727 urtwn_r92e_power_on(struct urtwn_softc *sc) 1728 { 1729 uint32_t reg; 1730 int ntries; 1731 1732 if (urtwn_read_4(sc, R92C_SYS_CFG) & R92E_SYS_CFG_SPSLDO_SEL) { 1733 /* LDO. */ 1734 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 1735 } else { 1736 reg = urtwn_read_4(sc, R92C_SYS_SWR_CTRL2); 1737 reg &= 0xff0fffff; 1738 reg |= 0x00500000; 1739 urtwn_write_4(sc, R92C_SYS_SWR_CTRL2, reg); 1740 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 1741 } 1742 1743 /* 40MHz crystal source */ 1744 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 1745 urtwn_read_1(sc, R92C_AFE_PLL_CTRL) & 0xfb); 1746 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL_EXT, 1747 urtwn_read_4(sc, R92C_AFE_XTAL_CTRL_EXT) & 0xfffffc7f); 1748 1749 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 1750 urtwn_read_1(sc, R92C_AFE_PLL_CTRL) & 0xbf); 1751 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL_EXT, 1752 urtwn_read_4(sc, R92C_AFE_XTAL_CTRL_EXT) & 0xffdfffff); 1753 1754 /* Disable HWPDN. */ 1755 urtwn_write_2(sc, R92C_APS_FSMCO, 1756 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 1757 for (ntries = 0; ntries < 5000; ntries++) { 1758 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 1759 break; 1760 DELAY(10); 1761 } 1762 if (ntries == 5000) { 1763 printf("%s: timeout waiting for chip power up\n", 1764 sc->sc_dev.dv_xname); 1765 return (ETIMEDOUT); 1766 } 1767 1768 /* Disable WL suspend. */ 1769 urtwn_write_2(sc, R92C_APS_FSMCO, 1770 urtwn_read_2(sc, R92C_APS_FSMCO) & 1771 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 1772 1773 /* Auto enable WLAN. */ 1774 urtwn_write_4(sc, R92C_APS_FSMCO, 1775 urtwn_read_4(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 1776 urtwn_write_2(sc, R92C_APS_FSMCO, 1777 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1778 for (ntries = 0; ntries < 5000; ntries++) { 1779 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1780 R92C_APS_FSMCO_APFM_ONMAC)) 1781 break; 1782 DELAY(10); 1783 } 1784 if (ntries == 5000) { 1785 printf("%s: timeout waiting for MAC auto ON\n", 1786 sc->sc_dev.dv_xname); 1787 return (ETIMEDOUT); 1788 } 1789 1790 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1791 urtwn_write_2(sc, R92C_CR, 0); 1792 reg = urtwn_read_2(sc, R92C_CR); 1793 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1794 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1795 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 1796 urtwn_write_2(sc, R92C_CR, reg); 1797 return (0); 1798 } 1799 1800 int 1801 urtwn_r88e_power_on(struct urtwn_softc *sc) 1802 { 1803 uint32_t reg; 1804 int ntries; 1805 1806 /* Wait for power ready bit. */ 1807 for (ntries = 0; ntries < 5000; ntries++) { 1808 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 1809 break; 1810 DELAY(10); 1811 } 1812 if (ntries == 5000) { 1813 printf("%s: timeout waiting for chip power up\n", 1814 sc->sc_dev.dv_xname); 1815 return (ETIMEDOUT); 1816 } 1817 1818 /* Reset BB. */ 1819 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 1820 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 1821 R92C_SYS_FUNC_EN_BB_GLB_RST)); 1822 1823 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 1824 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 1825 1826 /* Disable HWPDN. */ 1827 urtwn_write_2(sc, R92C_APS_FSMCO, 1828 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 1829 /* Disable WL suspend. */ 1830 urtwn_write_2(sc, R92C_APS_FSMCO, 1831 urtwn_read_2(sc, R92C_APS_FSMCO) & 1832 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 1833 1834 /* Auto enable WLAN. */ 1835 urtwn_write_2(sc, R92C_APS_FSMCO, 1836 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1837 for (ntries = 0; ntries < 5000; ntries++) { 1838 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1839 R92C_APS_FSMCO_APFM_ONMAC)) 1840 break; 1841 DELAY(10); 1842 } 1843 if (ntries == 5000) { 1844 printf("%s: timeout waiting for MAC auto ON\n", 1845 sc->sc_dev.dv_xname); 1846 return (ETIMEDOUT); 1847 } 1848 1849 /* Enable LDO normal mode. */ 1850 urtwn_write_1(sc, R92C_LPLDO_CTRL, 1851 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 1852 1853 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1854 urtwn_write_2(sc, R92C_CR, 0); 1855 reg = urtwn_read_2(sc, R92C_CR); 1856 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1857 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1858 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 1859 urtwn_write_2(sc, R92C_CR, reg); 1860 return (0); 1861 } 1862 1863 int 1864 urtwn_llt_init(struct urtwn_softc *sc, int page_count) 1865 { 1866 int i, error, pktbuf_count; 1867 1868 pktbuf_count = (sc->sc_sc.chip & RTWN_CHIP_88E) ? 1869 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 1870 1871 /* Reserve pages [0; page_count]. */ 1872 for (i = 0; i < page_count; i++) { 1873 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1874 return (error); 1875 } 1876 /* NB: 0xff indicates end-of-list. */ 1877 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 1878 return (error); 1879 /* 1880 * Use pages [page_count + 1; pktbuf_count - 1] 1881 * as ring buffer. 1882 */ 1883 for (++i; i < pktbuf_count - 1; i++) { 1884 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1885 return (error); 1886 } 1887 /* Make the last page point to the beginning of the ring buffer. */ 1888 error = urtwn_llt_write(sc, i, page_count + 1); 1889 return (error); 1890 } 1891 1892 int 1893 urtwn_auto_llt_init(struct urtwn_softc *sc) 1894 { 1895 int ntries; 1896 1897 urtwn_write_4(sc, R92E_AUTO_LLT, urtwn_read_4(sc, 1898 R92E_AUTO_LLT) | R92E_AUTO_LLT_EN); 1899 for (ntries = 0; ntries < 1000; ntries++) { 1900 if (!(urtwn_read_4(sc, R92E_AUTO_LLT) & R92E_AUTO_LLT_EN)) 1901 return (0); 1902 DELAY(2); 1903 } 1904 1905 return (ETIMEDOUT); 1906 } 1907 1908 int 1909 urtwn_fw_loadpage(void *cookie, int page, uint8_t *buf, int len) 1910 { 1911 struct urtwn_softc *sc = cookie; 1912 uint32_t reg; 1913 int off, mlen, error = 0; 1914 1915 reg = urtwn_read_4(sc, R92C_MCUFWDL); 1916 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 1917 urtwn_write_4(sc, R92C_MCUFWDL, reg); 1918 1919 off = R92C_FW_START_ADDR; 1920 while (len > 0) { 1921 if (len > 196) 1922 mlen = 196; 1923 else if (len > 4) 1924 mlen = 4; 1925 else 1926 mlen = 1; 1927 error = urtwn_write_region_1(sc, off, buf, mlen); 1928 if (error != 0) 1929 break; 1930 off += mlen; 1931 buf += mlen; 1932 len -= mlen; 1933 } 1934 return (error); 1935 } 1936 1937 int 1938 urtwn_load_firmware(void *cookie, u_char **fw, size_t *len) 1939 { 1940 struct urtwn_softc *sc = cookie; 1941 const char *name; 1942 int error; 1943 1944 if (sc->sc_sc.chip & RTWN_CHIP_92E) 1945 name = "urtwn-rtl8192eu_nic"; 1946 else if (sc->sc_sc.chip & RTWN_CHIP_88E) 1947 name = "urtwn-rtl8188eufw"; 1948 else if ((sc->sc_sc.chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 1949 RTWN_CHIP_UMC_A_CUT) 1950 name = "urtwn-rtl8192cfwU"; 1951 else 1952 name = "urtwn-rtl8192cfwT"; 1953 1954 error = loadfirmware(name, fw, len); 1955 if (error) 1956 printf("%s: could not read firmware %s (error %d)\n", 1957 sc->sc_dev.dv_xname, name, error); 1958 return (error); 1959 } 1960 1961 int 1962 urtwn_dma_init(void *cookie) 1963 { 1964 struct urtwn_softc *sc = cookie; 1965 uint32_t reg; 1966 uint16_t dmasize; 1967 int hqpages, lqpages, nqpages, pagecnt, boundary; 1968 int error, hashq, haslq, hasnq; 1969 1970 /* Default initialization of chipset values. */ 1971 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1972 hqpages = R88E_HQ_NPAGES; 1973 lqpages = R88E_LQ_NPAGES; 1974 nqpages = R88E_NQ_NPAGES; 1975 pagecnt = R88E_TX_PAGE_COUNT; 1976 boundary = R88E_TX_PAGE_BOUNDARY; 1977 dmasize = R88E_MAX_RX_DMA_SIZE; 1978 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 1979 hqpages = R92E_HQ_NPAGES; 1980 lqpages = R92E_LQ_NPAGES; 1981 nqpages = R92E_NQ_NPAGES; 1982 pagecnt = R92E_TX_PAGE_COUNT; 1983 boundary = R92E_TX_PAGE_BOUNDARY; 1984 dmasize = R92E_MAX_RX_DMA_SIZE; 1985 } else { 1986 hqpages = R92C_HQ_NPAGES; 1987 lqpages = R92C_LQ_NPAGES; 1988 nqpages = R92C_NQ_NPAGES; 1989 pagecnt = R92C_TX_PAGE_COUNT; 1990 boundary = R92C_TX_PAGE_BOUNDARY; 1991 dmasize = R92C_MAX_RX_DMA_SIZE; 1992 } 1993 1994 /* Initialize LLT table. */ 1995 if (sc->sc_sc.chip & RTWN_CHIP_92E) { 1996 error = urtwn_auto_llt_init(sc); 1997 } else { 1998 error = urtwn_llt_init(sc, pagecnt); 1999 } 2000 if (error != 0) 2001 return (error); 2002 2003 /* Get Tx queues to USB endpoints mapping. */ 2004 hashq = hasnq = haslq = 0; 2005 switch (sc->ntx) { 2006 case 3: 2007 haslq = 1; 2008 pagecnt -= lqpages; 2009 /* FALLTHROUGH */ 2010 case 2: 2011 hasnq = 1; 2012 pagecnt -= nqpages; 2013 /* FALLTHROUGH */ 2014 case 1: 2015 hashq = 1; 2016 pagecnt -= hqpages; 2017 break; 2018 } 2019 2020 /* Set number of pages for normal priority queue. */ 2021 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2022 urtwn_write_4(sc, R92C_RQPN, 2023 /* Set number of pages for public queue. */ 2024 SM(R92C_RQPN_PUBQ, pagecnt) | 2025 /* Set number of pages for high priority queue. */ 2026 SM(R92C_RQPN_HPQ, hashq ? hqpages : 0) | 2027 /* Set number of pages for low priority queue. */ 2028 SM(R92C_RQPN_LPQ, haslq ? lqpages : 0) | 2029 /* Load values. */ 2030 R92C_RQPN_LD); 2031 2032 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, boundary); 2033 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, boundary); 2034 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, boundary); 2035 urtwn_write_1(sc, R92C_TRXFF_BNDY, boundary); 2036 urtwn_write_1(sc, R92C_TDECTRL + 1, boundary); 2037 2038 /* Set queue to USB pipe mapping. */ 2039 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2040 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2041 if (haslq) 2042 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2043 else if (hashq) { 2044 if (!hasnq) 2045 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2046 else 2047 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2048 } 2049 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2050 2051 /* Set Tx/Rx transfer page boundary. */ 2052 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, dmasize - 1); 2053 2054 if (!(sc->sc_sc.chip & RTWN_CHIP_92E)) { 2055 /* Set Tx/Rx transfer page size. */ 2056 urtwn_write_1(sc, R92C_PBP, 2057 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2058 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2059 } 2060 return (error); 2061 } 2062 2063 void 2064 urtwn_mac_init(void *cookie) 2065 { 2066 struct urtwn_softc *sc = cookie; 2067 int i; 2068 2069 /* Write MAC initialization values. */ 2070 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2071 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2072 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2073 rtl8188eu_mac[i].val); 2074 } 2075 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2076 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2077 for (i = 0; i < nitems(rtl8192eu_mac); i++) { 2078 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 2079 rtl8192eu_mac[i].val); 2080 } 2081 } else { 2082 for (i = 0; i < nitems(rtl8192cu_mac); i++) 2083 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2084 rtl8192cu_mac[i].val); 2085 } 2086 } 2087 2088 void 2089 urtwn_bb_init(void *cookie) 2090 { 2091 struct urtwn_softc *sc = cookie; 2092 const struct r92c_bb_prog *prog; 2093 uint32_t reg; 2094 uint8_t xtal; 2095 int i; 2096 2097 /* Enable BB and RF. */ 2098 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2099 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2100 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2101 R92C_SYS_FUNC_EN_DIO_RF); 2102 2103 if (!(sc->sc_sc.chip & (RTWN_CHIP_88E | RTWN_CHIP_92E))) 2104 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2105 2106 urtwn_write_1(sc, R92C_RF_CTRL, 2107 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2108 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2109 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2110 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2111 2112 if (!(sc->sc_sc.chip & (RTWN_CHIP_88E | RTWN_CHIP_92E))) { 2113 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2114 urtwn_write_1(sc, 0x15, 0xe9); 2115 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2116 } 2117 2118 /* Select BB programming based on board type. */ 2119 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2120 prog = &rtl8188eu_bb_prog; 2121 else if (sc->sc_sc.chip & RTWN_CHIP_92E) 2122 prog = &rtl8192eu_bb_prog; 2123 else if (!(sc->sc_sc.chip & RTWN_CHIP_92C)) { 2124 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD) 2125 prog = &rtl8188ce_bb_prog; 2126 else if (sc->sc_sc.board_type == R92C_BOARD_TYPE_HIGHPA) 2127 prog = &rtl8188ru_bb_prog; 2128 else 2129 prog = &rtl8188cu_bb_prog; 2130 } else { 2131 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD) 2132 prog = &rtl8192ce_bb_prog; 2133 else 2134 prog = &rtl8192cu_bb_prog; 2135 } 2136 /* Write BB initialization values. */ 2137 for (i = 0; i < prog->count; i++) { 2138 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2139 DELAY(1); 2140 } 2141 2142 if (sc->sc_sc.chip & RTWN_CHIP_92C_1T2R) { 2143 /* 8192C 1T only configuration. */ 2144 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2145 reg = (reg & ~0x00000003) | 0x2; 2146 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2147 2148 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2149 reg = (reg & ~0x00300033) | 0x00200022; 2150 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2151 2152 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2153 reg = (reg & ~0xff000000) | 0x45 << 24; 2154 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2155 2156 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2157 reg = (reg & ~0x000000ff) | 0x23; 2158 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2159 2160 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2161 reg = (reg & ~0x00000030) | 1 << 4; 2162 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2163 2164 reg = urtwn_bb_read(sc, 0xe74); 2165 reg = (reg & ~0x0c000000) | 2 << 26; 2166 urtwn_bb_write(sc, 0xe74, reg); 2167 reg = urtwn_bb_read(sc, 0xe78); 2168 reg = (reg & ~0x0c000000) | 2 << 26; 2169 urtwn_bb_write(sc, 0xe78, reg); 2170 reg = urtwn_bb_read(sc, 0xe7c); 2171 reg = (reg & ~0x0c000000) | 2 << 26; 2172 urtwn_bb_write(sc, 0xe7c, reg); 2173 reg = urtwn_bb_read(sc, 0xe80); 2174 reg = (reg & ~0x0c000000) | 2 << 26; 2175 urtwn_bb_write(sc, 0xe80, reg); 2176 reg = urtwn_bb_read(sc, 0xe88); 2177 reg = (reg & ~0x0c000000) | 2 << 26; 2178 urtwn_bb_write(sc, 0xe88, reg); 2179 } 2180 2181 /* Write AGC values. */ 2182 for (i = 0; i < prog->agccount; i++) { 2183 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2184 prog->agcvals[i]); 2185 DELAY(1); 2186 } 2187 2188 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2189 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2190 DELAY(1); 2191 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2192 DELAY(1); 2193 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2194 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040022); 2195 DELAY(1); 2196 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040020); 2197 DELAY(1); 2198 } 2199 2200 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2201 xtal = sc->sc_sc.crystal_cap & 0x3f; 2202 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2203 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2204 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, xtal | xtal << 6)); 2205 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2206 xtal = sc->sc_sc.crystal_cap & 0x3f; 2207 reg = urtwn_read_4(sc, R92C_AFE_CTRL3); 2208 reg &= 0xff000fff; 2209 reg |= (xtal | (xtal << 6)) << 12; 2210 urtwn_write_4(sc, R92C_AFE_CTRL3, reg); 2211 2212 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0x000f81fb); 2213 } 2214 2215 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & R92C_HSSI_PARAM2_CCK_HIPWR) 2216 sc->sc_sc.sc_flags |= RTWN_FLAG_CCK_HIPWR; 2217 } 2218 2219 int 2220 urtwn_power_on(void *cookie) 2221 { 2222 struct urtwn_softc *sc = cookie; 2223 2224 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2225 return (urtwn_r88e_power_on(sc)); 2226 else if (sc->sc_sc.chip & RTWN_CHIP_92E) 2227 return (urtwn_r92e_power_on(sc)); 2228 2229 return (urtwn_r92c_power_on(sc)); 2230 } 2231 2232 int 2233 urtwn_alloc_buffers(void *cookie) 2234 { 2235 struct urtwn_softc *sc = cookie; 2236 int error; 2237 2238 /* Init host async commands ring. */ 2239 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 2240 2241 /* Allocate Tx/Rx buffers. */ 2242 error = urtwn_alloc_rx_list(sc); 2243 if (error != 0) { 2244 printf("%s: could not allocate Rx buffers\n", 2245 sc->sc_dev.dv_xname); 2246 return (error); 2247 } 2248 error = urtwn_alloc_tx_list(sc); 2249 if (error != 0) { 2250 printf("%s: could not allocate Tx buffers\n", 2251 sc->sc_dev.dv_xname); 2252 return (error); 2253 } 2254 2255 return (0); 2256 } 2257 2258 int 2259 urtwn_init(void *cookie) 2260 { 2261 struct urtwn_softc *sc = cookie; 2262 int i, error; 2263 2264 if (sc->sc_sc.chip & RTWN_CHIP_92E) 2265 urtwn_write_1(sc, R92C_ACLK_MON, 0); 2266 2267 /* Queue Rx xfers. */ 2268 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 2269 struct urtwn_rx_data *data = &sc->rx_data[i]; 2270 2271 usbd_setup_xfer(data->xfer, sc->rx_pipe, data, data->buf, 2272 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 2273 USBD_NO_TIMEOUT, urtwn_rxeof); 2274 error = usbd_transfer(data->xfer); 2275 if (error != 0 && error != USBD_IN_PROGRESS) 2276 return (error); 2277 } 2278 2279 ieee80211_amrr_node_init(&sc->amrr, &sc->amn); 2280 2281 /* 2282 * Enable TX reports for AMRR. 2283 * In order to get reports we need to explicitly reset the register. 2284 */ 2285 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2286 urtwn_write_1(sc, R88E_TX_RPT_CTRL, (urtwn_read_1(sc, 2287 R88E_TX_RPT_CTRL) & ~0) | R88E_TX_RPT_CTRL_EN); 2288 2289 return (0); 2290 } 2291 2292 void 2293 urtwn_stop(void *cookie) 2294 { 2295 struct urtwn_softc *sc = cookie; 2296 int i; 2297 2298 /* Abort Tx. */ 2299 for (i = 0; i < R92C_MAX_EPOUT; i++) { 2300 if (sc->tx_pipe[i] != NULL) 2301 usbd_abort_pipe(sc->tx_pipe[i]); 2302 } 2303 /* Stop Rx pipe. */ 2304 usbd_abort_pipe(sc->rx_pipe); 2305 /* Free Tx/Rx buffers. */ 2306 urtwn_free_tx_list(sc); 2307 urtwn_free_rx_list(sc); 2308 } 2309 2310 int 2311 urtwn_is_oactive(void *cookie) 2312 { 2313 struct urtwn_softc *sc = cookie; 2314 2315 return (TAILQ_EMPTY(&sc->tx_free_list)); 2316 } 2317