1 /* $OpenBSD: if_urtwn.c,v 1.96 2020/11/15 00:04:05 jmatthew Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss@yahoo.com.au> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU/ 23 * RTL8192EU. 24 */ 25 26 #include "bpfilter.h" 27 28 #include <sys/param.h> 29 #include <sys/sockio.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/timeout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 #include <sys/endian.h> 38 39 #include <machine/bus.h> 40 #include <machine/intr.h> 41 42 #if NBPFILTER > 0 43 #include <net/bpf.h> 44 #endif 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 49 #include <netinet/in.h> 50 #include <netinet/if_ether.h> 51 52 #include <net80211/ieee80211_var.h> 53 #include <net80211/ieee80211_amrr.h> 54 #include <net80211/ieee80211_radiotap.h> 55 56 #include <dev/usb/usb.h> 57 #include <dev/usb/usbdi.h> 58 #include <dev/usb/usbdivar.h> 59 #include <dev/usb/usbdi_util.h> 60 #include <dev/usb/usbdevs.h> 61 62 #include <dev/ic/r92creg.h> 63 #include <dev/ic/rtwnvar.h> 64 65 /* Maximum number of output pipes is 3. */ 66 #define R92C_MAX_EPOUT 3 67 68 #define R92C_HQ_NPAGES 12 69 #define R92C_LQ_NPAGES 2 70 #define R92C_NQ_NPAGES 2 71 #define R92C_TXPKTBUF_COUNT 256 72 #define R92C_TX_PAGE_COUNT 248 73 #define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) 74 #define R92C_MAX_RX_DMA_SIZE 0x2800 75 76 #define R88E_HQ_NPAGES 0 77 #define R88E_LQ_NPAGES 9 78 #define R88E_NQ_NPAGES 0 79 #define R88E_TXPKTBUF_COUNT 177 80 #define R88E_TX_PAGE_COUNT 168 81 #define R88E_TX_PAGE_BOUNDARY (R88E_TX_PAGE_COUNT + 1) 82 #define R88E_MAX_RX_DMA_SIZE 0x2400 83 84 #define R92E_HQ_NPAGES 16 85 #define R92E_LQ_NPAGES 16 86 #define R92E_NQ_NPAGES 16 87 #define R92E_TX_PAGE_COUNT 248 88 #define R92E_TX_PAGE_BOUNDARY (R92E_TX_PAGE_COUNT + 1) 89 #define R92E_MAX_RX_DMA_SIZE 0x3fc0 90 91 #define R92C_TXDESC_SUMSIZE 32 92 #define R92C_TXDESC_SUMOFFSET 14 93 94 /* USB Requests. */ 95 #define R92C_REQ_REGS 0x05 96 97 /* 98 * Driver definitions. 99 */ 100 #define URTWN_RX_LIST_COUNT 1 101 #define URTWN_TX_LIST_COUNT 8 102 #define URTWN_HOST_CMD_RING_COUNT 32 103 104 #define URTWN_RXBUFSZ (16 * 1024) 105 #define URTWN_TXBUFSZ (sizeof(struct r92e_tx_desc_usb) + IEEE80211_MAX_LEN) 106 107 #define URTWN_RIDX_COUNT 28 108 109 #define URTWN_TX_TIMEOUT 5000 /* ms */ 110 111 #define URTWN_LED_LINK 0 112 #define URTWN_LED_DATA 1 113 114 struct urtwn_rx_radiotap_header { 115 struct ieee80211_radiotap_header wr_ihdr; 116 uint8_t wr_flags; 117 uint8_t wr_rate; 118 uint16_t wr_chan_freq; 119 uint16_t wr_chan_flags; 120 uint8_t wr_dbm_antsignal; 121 } __packed; 122 123 #define URTWN_RX_RADIOTAP_PRESENT \ 124 (1 << IEEE80211_RADIOTAP_FLAGS | \ 125 1 << IEEE80211_RADIOTAP_RATE | \ 126 1 << IEEE80211_RADIOTAP_CHANNEL | \ 127 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) 128 129 struct urtwn_tx_radiotap_header { 130 struct ieee80211_radiotap_header wt_ihdr; 131 uint8_t wt_flags; 132 uint16_t wt_chan_freq; 133 uint16_t wt_chan_flags; 134 } __packed; 135 136 #define URTWN_TX_RADIOTAP_PRESENT \ 137 (1 << IEEE80211_RADIOTAP_FLAGS | \ 138 1 << IEEE80211_RADIOTAP_CHANNEL) 139 140 struct urtwn_softc; 141 142 struct urtwn_rx_data { 143 struct urtwn_softc *sc; 144 struct usbd_xfer *xfer; 145 uint8_t *buf; 146 }; 147 148 struct urtwn_tx_data { 149 struct urtwn_softc *sc; 150 struct usbd_pipe *pipe; 151 struct usbd_xfer *xfer; 152 uint8_t *buf; 153 TAILQ_ENTRY(urtwn_tx_data) next; 154 }; 155 156 struct urtwn_host_cmd { 157 void (*cb)(struct urtwn_softc *, void *); 158 uint8_t data[256]; 159 }; 160 161 struct urtwn_cmd_newstate { 162 enum ieee80211_state state; 163 int arg; 164 }; 165 166 struct urtwn_cmd_key { 167 struct ieee80211_key key; 168 struct ieee80211_node *ni; 169 }; 170 171 struct urtwn_host_cmd_ring { 172 struct urtwn_host_cmd cmd[URTWN_HOST_CMD_RING_COUNT]; 173 int cur; 174 int next; 175 int queued; 176 }; 177 178 struct urtwn_softc { 179 struct device sc_dev; 180 struct rtwn_softc sc_sc; 181 182 struct usbd_device *sc_udev; 183 struct usbd_interface *sc_iface; 184 struct usb_task sc_task; 185 186 struct timeout scan_to; 187 struct timeout calib_to; 188 189 int ntx; 190 struct usbd_pipe *rx_pipe; 191 struct usbd_pipe *tx_pipe[R92C_MAX_EPOUT]; 192 int ac2idx[EDCA_NUM_AC]; 193 194 struct urtwn_host_cmd_ring cmdq; 195 struct urtwn_rx_data rx_data[URTWN_RX_LIST_COUNT]; 196 struct urtwn_tx_data tx_data[URTWN_TX_LIST_COUNT]; 197 TAILQ_HEAD(, urtwn_tx_data) tx_free_list; 198 199 struct ieee80211_amrr amrr; 200 struct ieee80211_amrr_node amn; 201 202 #if NBPFILTER > 0 203 caddr_t sc_drvbpf; 204 205 union { 206 struct urtwn_rx_radiotap_header th; 207 uint8_t pad[64]; 208 } sc_rxtapu; 209 #define sc_rxtap sc_rxtapu.th 210 int sc_rxtap_len; 211 212 union { 213 struct urtwn_tx_radiotap_header th; 214 uint8_t pad[64]; 215 } sc_txtapu; 216 #define sc_txtap sc_txtapu.th 217 int sc_txtap_len; 218 #endif 219 int sc_key_tasks; 220 }; 221 222 #ifdef URTWN_DEBUG 223 #define DPRINTF(x) do { if (urtwn_debug) printf x; } while (0) 224 #define DPRINTFN(n, x) do { if (urtwn_debug >= (n)) printf x; } while (0) 225 int urtwn_debug = 4; 226 #else 227 #define DPRINTF(x) 228 #define DPRINTFN(n, x) 229 #endif 230 231 /* 232 * Various supported device vendors/products. 233 */ 234 #define URTWN_DEV(v, p, f) \ 235 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, (f) | RTWN_CHIP_USB } 236 #define URTWN_DEV_8192CU(v, p) URTWN_DEV(v, p, RTWN_CHIP_92C | RTWN_CHIP_88C) 237 #define URTWN_DEV_8188EU(v, p) URTWN_DEV(v, p, RTWN_CHIP_88E) 238 #define URTWN_DEV_8192EU(v, p) URTWN_DEV(v, p, RTWN_CHIP_92E) 239 static const struct urtwn_type { 240 struct usb_devno dev; 241 uint32_t chip; 242 } urtwn_devs[] = { 243 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_1), 244 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_1), 245 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_2), 246 URTWN_DEV_8192CU(ABOCOM, RTL8192CU), 247 URTWN_DEV_8192CU(ASUS, RTL8192CU), 248 URTWN_DEV_8192CU(ASUS, RTL8192CU_2), 249 URTWN_DEV_8192CU(ASUS, RTL8192CU_3), 250 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CE_1), 251 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CE_2), 252 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CU), 253 URTWN_DEV_8192CU(BELKIN, F7D2102), 254 URTWN_DEV_8192CU(BELKIN, F9L1004V1), 255 URTWN_DEV_8192CU(BELKIN, RTL8188CU), 256 URTWN_DEV_8192CU(BELKIN, RTL8188CUS), 257 URTWN_DEV_8192CU(BELKIN, RTL8192CU), 258 URTWN_DEV_8192CU(BELKIN, RTL8192CU_1), 259 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_1), 260 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_2), 261 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_3), 262 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_4), 263 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_5), 264 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_6), 265 URTWN_DEV_8192CU(COMPARE, RTL8192CU), 266 URTWN_DEV_8192CU(COREGA, RTL8192CU), 267 URTWN_DEV_8192CU(DLINK, DWA131B), 268 URTWN_DEV_8192CU(DLINK, RTL8188CU), 269 URTWN_DEV_8192CU(DLINK, RTL8192CU_1), 270 URTWN_DEV_8192CU(DLINK, RTL8192CU_2), 271 URTWN_DEV_8192CU(DLINK, RTL8192CU_3), 272 URTWN_DEV_8192CU(DLINK, RTL8192CU_4), 273 URTWN_DEV_8192CU(EDIMAX, EW7811UN), 274 URTWN_DEV_8192CU(EDIMAX, RTL8192CU), 275 URTWN_DEV_8192CU(FEIXUN, RTL8188CU), 276 URTWN_DEV_8192CU(FEIXUN, RTL8192CU), 277 URTWN_DEV_8192CU(GUILLEMOT, HWNUP150), 278 URTWN_DEV_8192CU(GUILLEMOT, RTL8192CU), 279 URTWN_DEV_8192CU(HAWKING, RTL8192CU), 280 URTWN_DEV_8192CU(HAWKING, RTL8192CU_2), 281 URTWN_DEV_8192CU(HP3, RTL8188CU), 282 URTWN_DEV_8192CU(IODATA, WNG150UM), 283 URTWN_DEV_8192CU(IODATA, RTL8192CU), 284 URTWN_DEV_8192CU(NETGEAR, N300MA), 285 URTWN_DEV_8192CU(NETGEAR, WNA1000M), 286 URTWN_DEV_8192CU(NETGEAR, WNA1000MV2), 287 URTWN_DEV_8192CU(NETGEAR, RTL8192CU), 288 URTWN_DEV_8192CU(NETGEAR4, RTL8188CU), 289 URTWN_DEV_8192CU(NETWEEN, RTL8192CU), 290 URTWN_DEV_8192CU(NOVATECH, RTL8188CU), 291 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_1), 292 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_2), 293 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_3), 294 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_4), 295 URTWN_DEV_8192CU(PLANEX2, RTL8188CUS), 296 URTWN_DEV_8192CU(PLANEX2, RTL8192CU), 297 URTWN_DEV_8192CU(REALTEK, RTL8188CE_0), 298 URTWN_DEV_8192CU(REALTEK, RTL8188CE_1), 299 URTWN_DEV_8192CU(REALTEK, RTL8188CTV), 300 URTWN_DEV_8192CU(REALTEK, RTL8188CU_0), 301 URTWN_DEV_8192CU(REALTEK, RTL8188CU_1), 302 URTWN_DEV_8192CU(REALTEK, RTL8188CU_2), 303 URTWN_DEV_8192CU(REALTEK, RTL8188CU_3), 304 URTWN_DEV_8192CU(REALTEK, RTL8188CU_4), 305 URTWN_DEV_8192CU(REALTEK, RTL8188CU_5), 306 URTWN_DEV_8192CU(REALTEK, RTL8188CU_COMBO), 307 URTWN_DEV_8192CU(REALTEK, RTL8188CUS), 308 URTWN_DEV_8192CU(REALTEK, RTL8188RU), 309 URTWN_DEV_8192CU(REALTEK, RTL8188RU_2), 310 URTWN_DEV_8192CU(REALTEK, RTL8188RU_3), 311 URTWN_DEV_8192CU(REALTEK, RTL8191CU), 312 URTWN_DEV_8192CU(REALTEK, RTL8192CE), 313 URTWN_DEV_8192CU(REALTEK, RTL8192CE_VAU), 314 URTWN_DEV_8192CU(REALTEK, RTL8192CU), 315 URTWN_DEV_8192CU(SITECOMEU, RTL8188CU), 316 URTWN_DEV_8192CU(SITECOMEU, RTL8188CU_2), 317 URTWN_DEV_8192CU(SITECOMEU, RTL8192CU), 318 URTWN_DEV_8192CU(SITECOMEU, RTL8192CU_2), 319 URTWN_DEV_8192CU(SITECOMEU, WLA2100V2), 320 URTWN_DEV_8192CU(TPLINK, RTL8192CU), 321 URTWN_DEV_8192CU(TRENDNET, RTL8188CU), 322 URTWN_DEV_8192CU(TRENDNET, RTL8192CU), 323 URTWN_DEV_8192CU(ZYXEL, RTL8192CU), 324 /* URTWN_RTL8188E */ 325 URTWN_DEV_8188EU(ABOCOM, RTL8188EU), 326 URTWN_DEV_8188EU(DLINK, DWA121B1), 327 URTWN_DEV_8188EU(DLINK, DWA123D1), 328 URTWN_DEV_8188EU(DLINK, DWA125D1), 329 URTWN_DEV_8188EU(EDIMAX, EW7811UNV2), 330 URTWN_DEV_8188EU(ELECOM, WDC150SU2M), 331 URTWN_DEV_8188EU(REALTEK, RTL8188ETV), 332 URTWN_DEV_8188EU(REALTEK, RTL8188EU), 333 URTWN_DEV_8188EU(TPLINK, RTL8188EUS), 334 /* URTWN_RTL8192EU */ 335 URTWN_DEV_8192EU(DLINK, DWA131E1), 336 URTWN_DEV_8192EU(REALTEK, RTL8192EU), 337 URTWN_DEV_8192EU(TPLINK, RTL8192EU), 338 URTWN_DEV_8192EU(TPLINK, RTL8192EU_2), 339 URTWN_DEV_8192EU(TPLINK, RTL8192EU_3) 340 }; 341 342 #define urtwn_lookup(v, p) \ 343 ((const struct urtwn_type *)usb_lookup(urtwn_devs, v, p)) 344 345 int urtwn_match(struct device *, void *, void *); 346 void urtwn_attach(struct device *, struct device *, void *); 347 int urtwn_detach(struct device *, int); 348 int urtwn_open_pipes(struct urtwn_softc *); 349 void urtwn_close_pipes(struct urtwn_softc *); 350 int urtwn_alloc_rx_list(struct urtwn_softc *); 351 void urtwn_free_rx_list(struct urtwn_softc *); 352 int urtwn_alloc_tx_list(struct urtwn_softc *); 353 void urtwn_free_tx_list(struct urtwn_softc *); 354 void urtwn_task(void *); 355 void urtwn_do_async(struct urtwn_softc *, 356 void (*)(struct urtwn_softc *, void *), void *, int); 357 void urtwn_wait_async(void *); 358 int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 359 int); 360 void urtwn_write_1(void *, uint16_t, uint8_t); 361 void urtwn_write_2(void *, uint16_t, uint16_t); 362 void urtwn_write_4(void *, uint16_t, uint32_t); 363 int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 364 int); 365 uint8_t urtwn_read_1(void *, uint16_t); 366 uint16_t urtwn_read_2(void *, uint16_t); 367 uint32_t urtwn_read_4(void *, uint16_t); 368 int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 369 void urtwn_calib_to(void *); 370 void urtwn_calib_cb(struct urtwn_softc *, void *); 371 void urtwn_scan_to(void *); 372 void urtwn_next_scan(void *); 373 void urtwn_cancel_scan(void *); 374 int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 375 int); 376 void urtwn_newstate_cb(struct urtwn_softc *, void *); 377 void urtwn_updateslot(struct ieee80211com *); 378 void urtwn_updateslot_cb(struct urtwn_softc *, void *); 379 void urtwn_updateedca(struct ieee80211com *); 380 void urtwn_updateedca_cb(struct urtwn_softc *, void *); 381 int urtwn_set_key(struct ieee80211com *, struct ieee80211_node *, 382 struct ieee80211_key *); 383 void urtwn_set_key_cb(struct urtwn_softc *, void *); 384 void urtwn_delete_key(struct ieee80211com *, 385 struct ieee80211_node *, struct ieee80211_key *); 386 void urtwn_delete_key_cb(struct urtwn_softc *, void *); 387 void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 388 struct mbuf_list *); 389 void urtwn_rxeof(struct usbd_xfer *, void *, 390 usbd_status); 391 void urtwn_txeof(struct usbd_xfer *, void *, 392 usbd_status); 393 int urtwn_tx(void *, struct mbuf *, struct ieee80211_node *); 394 int urtwn_ioctl(struct ifnet *, u_long, caddr_t); 395 int urtwn_power_on(void *); 396 int urtwn_alloc_buffers(void *); 397 int urtwn_r92c_power_on(struct urtwn_softc *); 398 int urtwn_r92e_power_on(struct urtwn_softc *); 399 int urtwn_r88e_power_on(struct urtwn_softc *); 400 int urtwn_llt_init(struct urtwn_softc *, int); 401 int urtwn_fw_loadpage(void *, int, uint8_t *, int); 402 int urtwn_load_firmware(void *, u_char **, size_t *); 403 int urtwn_dma_init(void *); 404 void urtwn_aggr_init(void *); 405 void urtwn_mac_init(void *); 406 void urtwn_bb_init(void *); 407 void urtwn_burstlen_init(struct urtwn_softc *); 408 int urtwn_init(void *); 409 void urtwn_stop(void *); 410 int urtwn_is_oactive(void *); 411 void urtwn_next_calib(void *); 412 void urtwn_cancel_calib(void *); 413 414 /* Aliases. */ 415 #define urtwn_bb_write urtwn_write_4 416 #define urtwn_bb_read urtwn_read_4 417 418 struct cfdriver urtwn_cd = { 419 NULL, "urtwn", DV_IFNET 420 }; 421 422 const struct cfattach urtwn_ca = { 423 sizeof(struct urtwn_softc), urtwn_match, urtwn_attach, urtwn_detach 424 }; 425 426 int 427 urtwn_match(struct device *parent, void *match, void *aux) 428 { 429 struct usb_attach_arg *uaa = aux; 430 431 if (uaa->iface == NULL || uaa->configno != 1) 432 return (UMATCH_NONE); 433 434 return ((urtwn_lookup(uaa->vendor, uaa->product) != NULL) ? 435 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 436 } 437 438 void 439 urtwn_attach(struct device *parent, struct device *self, void *aux) 440 { 441 struct urtwn_softc *sc = (struct urtwn_softc *)self; 442 struct usb_attach_arg *uaa = aux; 443 struct ifnet *ifp; 444 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 445 446 sc->sc_udev = uaa->device; 447 sc->sc_iface = uaa->iface; 448 449 sc->sc_sc.chip = urtwn_lookup(uaa->vendor, uaa->product)->chip; 450 451 usb_init_task(&sc->sc_task, urtwn_task, sc, USB_TASK_TYPE_GENERIC); 452 timeout_set(&sc->scan_to, urtwn_scan_to, sc); 453 timeout_set(&sc->calib_to, urtwn_calib_to, sc); 454 if (urtwn_open_pipes(sc) != 0) 455 return; 456 457 sc->amrr.amrr_min_success_threshold = 1; 458 sc->amrr.amrr_max_success_threshold = 10; 459 460 /* Attach the bus-agnostic driver. */ 461 sc->sc_sc.sc_ops.cookie = sc; 462 sc->sc_sc.sc_ops.write_1 = urtwn_write_1; 463 sc->sc_sc.sc_ops.write_2 = urtwn_write_2; 464 sc->sc_sc.sc_ops.write_4 = urtwn_write_4; 465 sc->sc_sc.sc_ops.read_1 = urtwn_read_1; 466 sc->sc_sc.sc_ops.read_2 = urtwn_read_2; 467 sc->sc_sc.sc_ops.read_4 = urtwn_read_4; 468 sc->sc_sc.sc_ops.tx = urtwn_tx; 469 sc->sc_sc.sc_ops.power_on = urtwn_power_on; 470 sc->sc_sc.sc_ops.dma_init = urtwn_dma_init; 471 sc->sc_sc.sc_ops.fw_loadpage = urtwn_fw_loadpage; 472 sc->sc_sc.sc_ops.load_firmware = urtwn_load_firmware; 473 sc->sc_sc.sc_ops.aggr_init = urtwn_aggr_init; 474 sc->sc_sc.sc_ops.mac_init = urtwn_mac_init; 475 sc->sc_sc.sc_ops.bb_init = urtwn_bb_init; 476 sc->sc_sc.sc_ops.alloc_buffers = urtwn_alloc_buffers; 477 sc->sc_sc.sc_ops.init = urtwn_init; 478 sc->sc_sc.sc_ops.stop = urtwn_stop; 479 sc->sc_sc.sc_ops.is_oactive = urtwn_is_oactive; 480 sc->sc_sc.sc_ops.next_calib = urtwn_next_calib; 481 sc->sc_sc.sc_ops.cancel_calib = urtwn_cancel_calib; 482 sc->sc_sc.sc_ops.next_scan = urtwn_next_scan; 483 sc->sc_sc.sc_ops.cancel_scan = urtwn_cancel_scan; 484 sc->sc_sc.sc_ops.wait_async = urtwn_wait_async; 485 if (rtwn_attach(&sc->sc_dev, &sc->sc_sc) != 0) { 486 urtwn_close_pipes(sc); 487 return; 488 } 489 490 /* ifp is now valid */ 491 ifp = &sc->sc_sc.sc_ic.ic_if; 492 ifp->if_ioctl = urtwn_ioctl; 493 494 ic->ic_updateslot = urtwn_updateslot; 495 ic->ic_updateedca = urtwn_updateedca; 496 ic->ic_set_key = urtwn_set_key; 497 ic->ic_delete_key = urtwn_delete_key; 498 /* Override state transition machine. */ 499 ic->ic_newstate = urtwn_newstate; 500 501 #if NBPFILTER > 0 502 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 503 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 504 505 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 506 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 507 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 508 509 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 510 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 511 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 512 #endif 513 } 514 515 int 516 urtwn_detach(struct device *self, int flags) 517 { 518 struct urtwn_softc *sc = (struct urtwn_softc *)self; 519 int s; 520 521 s = splusb(); 522 523 if (timeout_initialized(&sc->scan_to)) 524 timeout_del(&sc->scan_to); 525 if (timeout_initialized(&sc->calib_to)) 526 timeout_del(&sc->calib_to); 527 528 /* Wait for all async commands to complete. */ 529 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 530 531 usbd_ref_wait(sc->sc_udev); 532 533 rtwn_detach(&sc->sc_sc, flags); 534 535 /* Abort and close Tx/Rx pipes. */ 536 urtwn_close_pipes(sc); 537 538 /* Free Tx/Rx buffers. */ 539 urtwn_free_tx_list(sc); 540 urtwn_free_rx_list(sc); 541 splx(s); 542 543 return (0); 544 } 545 546 int 547 urtwn_open_pipes(struct urtwn_softc *sc) 548 { 549 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 550 uint8_t epaddr[R92C_MAX_EPOUT] = { 0, 0, 0 }; 551 uint8_t rx_no; 552 usb_interface_descriptor_t *id; 553 usb_endpoint_descriptor_t *ed; 554 int i, error, nrx = 0; 555 556 /* Find all bulk endpoints. */ 557 id = usbd_get_interface_descriptor(sc->sc_iface); 558 for (i = 0; i < id->bNumEndpoints; i++) { 559 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 560 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) 561 continue; 562 563 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 564 rx_no = ed->bEndpointAddress; 565 nrx++; 566 } else { 567 if (sc->ntx < R92C_MAX_EPOUT) 568 epaddr[sc->ntx] = ed->bEndpointAddress; 569 sc->ntx++; 570 } 571 } 572 if (nrx == 0) { 573 printf("%s: %d: invalid number of Rx bulk pipes\n", 574 sc->sc_dev.dv_xname, nrx); 575 return (EIO); 576 } 577 DPRINTF(("found %d bulk-out pipes\n", sc->ntx)); 578 if (sc->ntx == 0 || sc->ntx > R92C_MAX_EPOUT) { 579 printf("%s: %d: invalid number of Tx bulk pipes\n", 580 sc->sc_dev.dv_xname, sc->ntx); 581 return (EIO); 582 } 583 584 /* Open bulk-in pipe. */ 585 error = usbd_open_pipe(sc->sc_iface, rx_no, 0, &sc->rx_pipe); 586 if (error != 0) { 587 printf("%s: could not open Rx bulk pipe\n", 588 sc->sc_dev.dv_xname); 589 goto fail; 590 } 591 592 /* Open bulk-out pipes (up to 3). */ 593 for (i = 0; i < sc->ntx; i++) { 594 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 0, 595 &sc->tx_pipe[i]); 596 if (error != 0) { 597 printf("%s: could not open Tx bulk pipe 0x%02x\n", 598 sc->sc_dev.dv_xname, epaddr[i]); 599 goto fail; 600 } 601 } 602 603 /* Map 802.11 access categories to USB pipes. */ 604 sc->ac2idx[EDCA_AC_BK] = 605 sc->ac2idx[EDCA_AC_BE] = (sc->ntx == 3) ? 2 : ((sc->ntx == 2) ? 1 : 0); 606 sc->ac2idx[EDCA_AC_VI] = (sc->ntx == 3) ? 1 : 0; 607 sc->ac2idx[EDCA_AC_VO] = 0; /* Always use highest prio. */ 608 609 if (error != 0) 610 fail: urtwn_close_pipes(sc); 611 return (error); 612 } 613 614 void 615 urtwn_close_pipes(struct urtwn_softc *sc) 616 { 617 int i; 618 619 /* Close Rx pipe. */ 620 if (sc->rx_pipe != NULL) 621 usbd_close_pipe(sc->rx_pipe); 622 /* Close Tx pipes. */ 623 for (i = 0; i < R92C_MAX_EPOUT; i++) { 624 if (sc->tx_pipe[i] == NULL) 625 continue; 626 usbd_close_pipe(sc->tx_pipe[i]); 627 } 628 } 629 630 int 631 urtwn_alloc_rx_list(struct urtwn_softc *sc) 632 { 633 struct urtwn_rx_data *data; 634 int i, error = 0; 635 636 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 637 data = &sc->rx_data[i]; 638 639 data->sc = sc; /* Backpointer for callbacks. */ 640 641 data->xfer = usbd_alloc_xfer(sc->sc_udev); 642 if (data->xfer == NULL) { 643 printf("%s: could not allocate xfer\n", 644 sc->sc_dev.dv_xname); 645 error = ENOMEM; 646 break; 647 } 648 data->buf = usbd_alloc_buffer(data->xfer, URTWN_RXBUFSZ); 649 if (data->buf == NULL) { 650 printf("%s: could not allocate xfer buffer\n", 651 sc->sc_dev.dv_xname); 652 error = ENOMEM; 653 break; 654 } 655 } 656 if (error != 0) 657 urtwn_free_rx_list(sc); 658 return (error); 659 } 660 661 void 662 urtwn_free_rx_list(struct urtwn_softc *sc) 663 { 664 int i; 665 666 /* NB: Caller must abort pipe first. */ 667 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 668 if (sc->rx_data[i].xfer != NULL) 669 usbd_free_xfer(sc->rx_data[i].xfer); 670 sc->rx_data[i].xfer = NULL; 671 } 672 } 673 674 int 675 urtwn_alloc_tx_list(struct urtwn_softc *sc) 676 { 677 struct urtwn_tx_data *data; 678 int i, error = 0; 679 680 TAILQ_INIT(&sc->tx_free_list); 681 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 682 data = &sc->tx_data[i]; 683 684 data->sc = sc; /* Backpointer for callbacks. */ 685 686 data->xfer = usbd_alloc_xfer(sc->sc_udev); 687 if (data->xfer == NULL) { 688 printf("%s: could not allocate xfer\n", 689 sc->sc_dev.dv_xname); 690 error = ENOMEM; 691 break; 692 } 693 data->buf = usbd_alloc_buffer(data->xfer, URTWN_TXBUFSZ); 694 if (data->buf == NULL) { 695 printf("%s: could not allocate xfer buffer\n", 696 sc->sc_dev.dv_xname); 697 error = ENOMEM; 698 break; 699 } 700 /* Append this Tx buffer to our free list. */ 701 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 702 } 703 if (error != 0) 704 urtwn_free_tx_list(sc); 705 return (error); 706 } 707 708 void 709 urtwn_free_tx_list(struct urtwn_softc *sc) 710 { 711 int i; 712 713 /* NB: Caller must abort pipe first. */ 714 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 715 if (sc->tx_data[i].xfer != NULL) 716 usbd_free_xfer(sc->tx_data[i].xfer); 717 sc->tx_data[i].xfer = NULL; 718 } 719 } 720 721 void 722 urtwn_task(void *arg) 723 { 724 struct urtwn_softc *sc = arg; 725 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 726 struct urtwn_host_cmd *cmd; 727 int s; 728 729 /* Process host commands. */ 730 s = splusb(); 731 while (ring->next != ring->cur) { 732 cmd = &ring->cmd[ring->next]; 733 splx(s); 734 /* Invoke callback. */ 735 cmd->cb(sc, cmd->data); 736 s = splusb(); 737 ring->queued--; 738 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 739 } 740 splx(s); 741 } 742 743 void 744 urtwn_do_async(struct urtwn_softc *sc, 745 void (*cb)(struct urtwn_softc *, void *), void *arg, int len) 746 { 747 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 748 struct urtwn_host_cmd *cmd; 749 int s; 750 751 s = splusb(); 752 cmd = &ring->cmd[ring->cur]; 753 cmd->cb = cb; 754 KASSERT(len <= sizeof(cmd->data)); 755 memcpy(cmd->data, arg, len); 756 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 757 758 /* If there is no pending command already, schedule a task. */ 759 if (++ring->queued == 1) 760 usb_add_task(sc->sc_udev, &sc->sc_task); 761 splx(s); 762 } 763 764 void 765 urtwn_wait_async(void *cookie) 766 { 767 struct urtwn_softc *sc = cookie; 768 int s; 769 770 s = splusb(); 771 /* Wait for all queued asynchronous commands to complete. */ 772 usb_wait_task(sc->sc_udev, &sc->sc_task); 773 splx(s); 774 } 775 776 int 777 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 778 int len) 779 { 780 usb_device_request_t req; 781 782 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 783 req.bRequest = R92C_REQ_REGS; 784 USETW(req.wValue, addr); 785 USETW(req.wIndex, 0); 786 USETW(req.wLength, len); 787 return (usbd_do_request(sc->sc_udev, &req, buf)); 788 } 789 790 void 791 urtwn_write_1(void *cookie, uint16_t addr, uint8_t val) 792 { 793 struct urtwn_softc *sc = cookie; 794 795 urtwn_write_region_1(sc, addr, &val, 1); 796 } 797 798 void 799 urtwn_write_2(void *cookie, uint16_t addr, uint16_t val) 800 { 801 struct urtwn_softc *sc = cookie; 802 803 val = htole16(val); 804 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 805 } 806 807 void 808 urtwn_write_4(void *cookie, uint16_t addr, uint32_t val) 809 { 810 struct urtwn_softc *sc = cookie; 811 812 val = htole32(val); 813 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 814 } 815 816 int 817 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 818 int len) 819 { 820 usb_device_request_t req; 821 822 req.bmRequestType = UT_READ_VENDOR_DEVICE; 823 req.bRequest = R92C_REQ_REGS; 824 USETW(req.wValue, addr); 825 USETW(req.wIndex, 0); 826 USETW(req.wLength, len); 827 return (usbd_do_request(sc->sc_udev, &req, buf)); 828 } 829 830 uint8_t 831 urtwn_read_1(void *cookie, uint16_t addr) 832 { 833 struct urtwn_softc *sc = cookie; 834 uint8_t val; 835 836 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 837 return (0xff); 838 return (val); 839 } 840 841 uint16_t 842 urtwn_read_2(void *cookie, uint16_t addr) 843 { 844 struct urtwn_softc *sc = cookie; 845 uint16_t val; 846 847 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 848 return (0xffff); 849 return (letoh16(val)); 850 } 851 852 uint32_t 853 urtwn_read_4(void *cookie, uint16_t addr) 854 { 855 struct urtwn_softc *sc = cookie; 856 uint32_t val; 857 858 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 859 return (0xffffffff); 860 return (letoh32(val)); 861 } 862 863 int 864 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 865 { 866 int ntries; 867 868 urtwn_write_4(sc, R92C_LLT_INIT, 869 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 870 SM(R92C_LLT_INIT_ADDR, addr) | 871 SM(R92C_LLT_INIT_DATA, data)); 872 /* Wait for write operation to complete. */ 873 for (ntries = 0; ntries < 20; ntries++) { 874 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 875 R92C_LLT_INIT_OP_NO_ACTIVE) 876 return (0); 877 DELAY(5); 878 } 879 return (ETIMEDOUT); 880 } 881 882 void 883 urtwn_calib_to(void *arg) 884 { 885 struct urtwn_softc *sc = arg; 886 887 if (usbd_is_dying(sc->sc_udev)) 888 return; 889 890 usbd_ref_incr(sc->sc_udev); 891 892 /* Do it in a process context. */ 893 urtwn_do_async(sc, urtwn_calib_cb, NULL, 0); 894 895 usbd_ref_decr(sc->sc_udev); 896 } 897 898 /* ARGSUSED */ 899 void 900 urtwn_calib_cb(struct urtwn_softc *sc, void *arg) 901 { 902 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 903 int s; 904 905 s = splnet(); 906 if (ic->ic_opmode == IEEE80211_M_STA) { 907 ieee80211_amrr_choose(&sc->amrr, ic->ic_bss, &sc->amn); 908 } 909 splx(s); 910 911 rtwn_calib(&sc->sc_sc); 912 } 913 914 void 915 urtwn_next_calib(void *cookie) 916 { 917 struct urtwn_softc *sc = cookie; 918 919 if (!usbd_is_dying(sc->sc_udev)) 920 timeout_add_sec(&sc->calib_to, 2); 921 } 922 923 void 924 urtwn_cancel_calib(void *cookie) 925 { 926 struct urtwn_softc *sc = cookie; 927 928 if (timeout_initialized(&sc->calib_to)) 929 timeout_del(&sc->calib_to); 930 } 931 932 void 933 urtwn_scan_to(void *arg) 934 { 935 struct urtwn_softc *sc = arg; 936 937 if (usbd_is_dying(sc->sc_udev)) 938 return; 939 940 usbd_ref_incr(sc->sc_udev); 941 rtwn_next_scan(&sc->sc_sc); 942 usbd_ref_decr(sc->sc_udev); 943 } 944 945 void 946 urtwn_next_scan(void *arg) 947 { 948 struct urtwn_softc *sc = arg; 949 950 if (!usbd_is_dying(sc->sc_udev)) 951 timeout_add_msec(&sc->scan_to, 200); 952 } 953 954 void 955 urtwn_cancel_scan(void *cookie) 956 { 957 struct urtwn_softc *sc = cookie; 958 959 if (timeout_initialized(&sc->scan_to)) 960 timeout_del(&sc->scan_to); 961 } 962 963 int 964 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 965 { 966 struct rtwn_softc *sc_sc = ic->ic_softc; 967 struct device *self = sc_sc->sc_pdev; 968 struct urtwn_softc *sc = (struct urtwn_softc *)self; 969 struct urtwn_cmd_newstate cmd; 970 971 /* Do it in a process context. */ 972 cmd.state = nstate; 973 cmd.arg = arg; 974 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 975 return (0); 976 } 977 978 void 979 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 980 { 981 struct urtwn_cmd_newstate *cmd = arg; 982 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 983 984 rtwn_newstate(ic, cmd->state, cmd->arg); 985 } 986 987 void 988 urtwn_updateslot(struct ieee80211com *ic) 989 { 990 struct rtwn_softc *sc_sc = ic->ic_softc; 991 struct device *self = sc_sc->sc_pdev; 992 struct urtwn_softc *sc = (struct urtwn_softc *)self; 993 994 /* Do it in a process context. */ 995 urtwn_do_async(sc, urtwn_updateslot_cb, NULL, 0); 996 } 997 998 /* ARGSUSED */ 999 void 1000 urtwn_updateslot_cb(struct urtwn_softc *sc, void *arg) 1001 { 1002 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1003 1004 rtwn_updateslot(ic); 1005 } 1006 1007 void 1008 urtwn_updateedca(struct ieee80211com *ic) 1009 { 1010 struct rtwn_softc *sc_sc = ic->ic_softc; 1011 struct device *self = sc_sc->sc_pdev; 1012 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1013 1014 /* Do it in a process context. */ 1015 urtwn_do_async(sc, urtwn_updateedca_cb, NULL, 0); 1016 } 1017 1018 /* ARGSUSED */ 1019 void 1020 urtwn_updateedca_cb(struct urtwn_softc *sc, void *arg) 1021 { 1022 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1023 1024 rtwn_updateedca(ic); 1025 } 1026 1027 int 1028 urtwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1029 struct ieee80211_key *k) 1030 { 1031 struct rtwn_softc *sc_sc = ic->ic_softc; 1032 struct device *self = sc_sc->sc_pdev; 1033 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1034 struct urtwn_cmd_key cmd; 1035 1036 /* Only handle keys for CCMP */ 1037 if (k->k_cipher != IEEE80211_CIPHER_CCMP) 1038 return ieee80211_set_key(ic, ni, k); 1039 1040 /* Defer setting of WEP keys until interface is brought up. */ 1041 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 1042 (IFF_UP | IFF_RUNNING)) 1043 return (0); 1044 1045 /* Do it in a process context. */ 1046 cmd.key = *k; 1047 cmd.ni = ni; 1048 urtwn_do_async(sc, urtwn_set_key_cb, &cmd, sizeof(cmd)); 1049 sc->sc_key_tasks++; 1050 1051 return (EBUSY); 1052 } 1053 1054 void 1055 urtwn_set_key_cb(struct urtwn_softc *sc, void *arg) 1056 { 1057 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1058 struct urtwn_cmd_key *cmd = arg; 1059 1060 sc->sc_key_tasks--; 1061 1062 if (rtwn_set_key(ic, cmd->ni, &cmd->key) == 0) { 1063 if (sc->sc_key_tasks == 0) { 1064 DPRINTF(("marking port %s valid\n", 1065 ether_sprintf(cmd->ni->ni_macaddr))); 1066 cmd->ni->ni_port_valid = 1; 1067 ieee80211_set_link_state(ic, LINK_STATE_UP); 1068 } 1069 } else { 1070 IEEE80211_SEND_MGMT(ic, cmd->ni, IEEE80211_FC0_SUBTYPE_DEAUTH, 1071 IEEE80211_REASON_AUTH_LEAVE); 1072 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1073 } 1074 } 1075 1076 void 1077 urtwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1078 struct ieee80211_key *k) 1079 { 1080 struct rtwn_softc *sc_sc = ic->ic_softc; 1081 struct device *self = sc_sc->sc_pdev; 1082 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1083 struct urtwn_cmd_key cmd; 1084 1085 /* Only handle keys for CCMP */ 1086 if (k->k_cipher != IEEE80211_CIPHER_CCMP) { 1087 ieee80211_delete_key(ic, ni, k); 1088 return; 1089 } 1090 1091 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 1092 ic->ic_state != IEEE80211_S_RUN) 1093 return; /* Nothing to do. */ 1094 1095 /* Do it in a process context. */ 1096 cmd.key = *k; 1097 cmd.ni = ni; 1098 urtwn_do_async(sc, urtwn_delete_key_cb, &cmd, sizeof(cmd)); 1099 } 1100 1101 void 1102 urtwn_delete_key_cb(struct urtwn_softc *sc, void *arg) 1103 { 1104 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1105 struct urtwn_cmd_key *cmd = arg; 1106 1107 rtwn_delete_key(ic, cmd->ni, &cmd->key); 1108 } 1109 1110 int 1111 urtwn_ccmp_decap(struct urtwn_softc *sc, struct mbuf *m, 1112 struct ieee80211_node *ni) 1113 { 1114 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1115 struct ieee80211_key *k; 1116 struct ieee80211_frame *wh; 1117 uint64_t pn, *prsc; 1118 uint8_t *ivp; 1119 uint8_t tid; 1120 int hdrlen, hasqos; 1121 1122 k = ieee80211_get_rxkey(ic, m, ni); 1123 if (k == NULL) 1124 return 1; 1125 1126 wh = mtod(m, struct ieee80211_frame *); 1127 hdrlen = ieee80211_get_hdrlen(wh); 1128 ivp = (uint8_t *)wh + hdrlen; 1129 1130 /* Check that ExtIV bit is set. */ 1131 if (!(ivp[3] & IEEE80211_WEP_EXTIV)) 1132 return 1; 1133 1134 hasqos = ieee80211_has_qos(wh); 1135 tid = hasqos ? ieee80211_get_qos(wh) & IEEE80211_QOS_TID : 0; 1136 prsc = &k->k_rsc[tid]; 1137 1138 /* Extract the 48-bit PN from the CCMP header. */ 1139 pn = (uint64_t)ivp[0] | 1140 (uint64_t)ivp[1] << 8 | 1141 (uint64_t)ivp[4] << 16 | 1142 (uint64_t)ivp[5] << 24 | 1143 (uint64_t)ivp[6] << 32 | 1144 (uint64_t)ivp[7] << 40; 1145 if (pn <= *prsc) { 1146 ic->ic_stats.is_ccmp_replays++; 1147 return 1; 1148 } 1149 /* Last seen packet number is updated in ieee80211_inputm(). */ 1150 1151 /* Strip MIC. IV will be stripped by ieee80211_inputm(). */ 1152 m_adj(m, -IEEE80211_CCMP_MICLEN); 1153 return 0; 1154 } 1155 1156 void 1157 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, 1158 struct mbuf_list *ml) 1159 { 1160 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1161 struct ifnet *ifp = &ic->ic_if; 1162 struct ieee80211_rxinfo rxi; 1163 struct ieee80211_frame *wh; 1164 struct ieee80211_node *ni; 1165 struct r92c_rx_desc_usb *rxd; 1166 uint32_t rxdw0, rxdw3; 1167 struct mbuf *m; 1168 uint8_t rate; 1169 int8_t rssi = 0; 1170 int s, infosz; 1171 1172 rxd = (struct r92c_rx_desc_usb *)buf; 1173 rxdw0 = letoh32(rxd->rxdw0); 1174 rxdw3 = letoh32(rxd->rxdw3); 1175 1176 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1177 /* 1178 * This should not happen since we setup our Rx filter 1179 * to not receive these frames. 1180 */ 1181 ifp->if_ierrors++; 1182 return; 1183 } 1184 if (__predict_false(pktlen < sizeof(*wh) || pktlen > MCLBYTES)) { 1185 ifp->if_ierrors++; 1186 return; 1187 } 1188 1189 rate = MS(rxdw3, R92C_RXDW3_RATE); 1190 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1191 1192 /* Get RSSI from PHY status descriptor if present. */ 1193 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1194 rssi = rtwn_get_rssi(&sc->sc_sc, rate, &rxd[1]); 1195 /* Update our average RSSI. */ 1196 rtwn_update_avgrssi(&sc->sc_sc, rate, rssi); 1197 } 1198 1199 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 1200 pktlen, rate, infosz, rssi)); 1201 1202 MGETHDR(m, M_DONTWAIT, MT_DATA); 1203 if (__predict_false(m == NULL)) { 1204 ifp->if_ierrors++; 1205 return; 1206 } 1207 if (pktlen > MHLEN) { 1208 MCLGET(m, M_DONTWAIT); 1209 if (__predict_false(!(m->m_flags & M_EXT))) { 1210 ifp->if_ierrors++; 1211 m_freem(m); 1212 return; 1213 } 1214 } 1215 /* Finalize mbuf. */ 1216 wh = (struct ieee80211_frame *)((uint8_t *)&rxd[1] + infosz); 1217 memcpy(mtod(m, uint8_t *), wh, pktlen); 1218 m->m_pkthdr.len = m->m_len = pktlen; 1219 1220 s = splnet(); 1221 #if NBPFILTER > 0 1222 if (__predict_false(sc->sc_drvbpf != NULL)) { 1223 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1224 struct mbuf mb; 1225 1226 tap->wr_flags = 0; 1227 /* Map HW rate index to 802.11 rate. */ 1228 if (!(rxdw3 & R92C_RXDW3_HT)) { 1229 switch (rate) { 1230 /* CCK. */ 1231 case 0: tap->wr_rate = 2; break; 1232 case 1: tap->wr_rate = 4; break; 1233 case 2: tap->wr_rate = 11; break; 1234 case 3: tap->wr_rate = 22; break; 1235 /* OFDM. */ 1236 case 4: tap->wr_rate = 12; break; 1237 case 5: tap->wr_rate = 18; break; 1238 case 6: tap->wr_rate = 24; break; 1239 case 7: tap->wr_rate = 36; break; 1240 case 8: tap->wr_rate = 48; break; 1241 case 9: tap->wr_rate = 72; break; 1242 case 10: tap->wr_rate = 96; break; 1243 case 11: tap->wr_rate = 108; break; 1244 } 1245 if (rate <= 3) 1246 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1247 } else if (rate >= 12) { /* MCS0~15. */ 1248 /* Bit 7 set means HT MCS instead of rate. */ 1249 tap->wr_rate = 0x80 | (rate - 12); 1250 } 1251 tap->wr_dbm_antsignal = rssi; 1252 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1253 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1254 1255 mb.m_data = (caddr_t)tap; 1256 mb.m_len = sc->sc_rxtap_len; 1257 mb.m_next = m; 1258 mb.m_nextpkt = NULL; 1259 mb.m_type = 0; 1260 mb.m_flags = 0; 1261 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1262 } 1263 #endif 1264 1265 ni = ieee80211_find_rxnode(ic, wh); 1266 rxi.rxi_flags = 0; 1267 rxi.rxi_rssi = rssi; 1268 rxi.rxi_tstamp = 0; /* Unused. */ 1269 1270 /* Handle hardware decryption. */ 1271 if (((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) 1272 && (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && 1273 (ni->ni_flags & IEEE80211_NODE_RXPROT) && 1274 ((!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1275 ni->ni_pairwise_key.k_cipher == IEEE80211_CIPHER_CCMP) || 1276 (IEEE80211_IS_MULTICAST(wh->i_addr1) && 1277 ni->ni_rsngroupcipher == IEEE80211_CIPHER_CCMP))) { 1278 if (urtwn_ccmp_decap(sc, m, ni) != 0) { 1279 ifp->if_ierrors++; 1280 m_freem(m); 1281 ieee80211_release_node(ic, ni); 1282 return; 1283 } 1284 rxi.rxi_flags |= IEEE80211_RXI_HWDEC; 1285 } 1286 1287 ieee80211_inputm(ifp, m, ni, &rxi, ml); 1288 /* Node is no longer needed. */ 1289 ieee80211_release_node(ic, ni); 1290 splx(s); 1291 } 1292 1293 void 1294 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, 1295 usbd_status status) 1296 { 1297 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1298 struct urtwn_rx_data *data = priv; 1299 struct urtwn_softc *sc = data->sc; 1300 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1301 struct r92c_rx_desc_usb *rxd; 1302 uint32_t rxdw0; 1303 uint8_t *buf; 1304 int len, totlen, pktlen, infosz, npkts, error, align; 1305 1306 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1307 DPRINTF(("RX status=%d\n", status)); 1308 if (status == USBD_STALLED) 1309 usbd_clear_endpoint_stall_async(sc->rx_pipe); 1310 if (status != USBD_CANCELLED) 1311 goto resubmit; 1312 return; 1313 } 1314 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 1315 1316 if (__predict_false(len < sizeof(*rxd))) { 1317 DPRINTF(("xfer too short %d\n", len)); 1318 goto resubmit; 1319 } 1320 buf = data->buf; 1321 1322 /* Get the number of encapsulated frames. */ 1323 rxd = (struct r92c_rx_desc_usb *)buf; 1324 npkts = MS(letoh32(rxd->rxdw2), R92C_RXDW2_PKTCNT); 1325 DPRINTFN(4, ("Rx %d frames in one chunk\n", npkts)); 1326 1327 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1328 int ntries, type; 1329 struct r88e_tx_rpt_ccx *rxstat; 1330 1331 type = MS(letoh32(rxd->rxdw3), R88E_RXDW3_RPT); 1332 1333 if (type == R88E_RXDW3_RPT_TX1) { 1334 buf += sizeof(struct r92c_rx_desc_usb); 1335 rxstat = (struct r88e_tx_rpt_ccx *)buf; 1336 ntries = MS(letoh32(rxstat->rptb2), 1337 R88E_RPTB2_RETRY_CNT); 1338 1339 if (rxstat->rptb1 & R88E_RPTB1_PKT_OK) 1340 sc->amn.amn_txcnt++; 1341 if (ntries > 0) 1342 sc->amn.amn_retrycnt++; 1343 1344 goto resubmit; 1345 } 1346 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 1347 int type; 1348 struct r92e_c2h_tx_rpt *txrpt; 1349 1350 if (letoh32(rxd->rxdw2) & R92E_RXDW2_RPT_C2H) { 1351 if (len < sizeof(struct r92c_rx_desc_usb) + 2) 1352 goto resubmit; 1353 1354 type = buf[sizeof(struct r92c_rx_desc_usb)]; 1355 switch (type) { 1356 case R92C_C2HEVT_TX_REPORT: 1357 buf += sizeof(struct r92c_rx_desc_usb) + 2; 1358 txrpt = (struct r92e_c2h_tx_rpt *)buf; 1359 if (MS(txrpt->rptb2, R92E_RPTB2_RETRY_CNT) > 0) 1360 sc->amn.amn_retrycnt++; 1361 if ((txrpt->rptb0 & (R92E_RPTB0_RETRY_OVER | 1362 R92E_RPTB0_LIFE_EXPIRE)) == 0) 1363 sc->amn.amn_txcnt++; 1364 break; 1365 default: 1366 break; 1367 } 1368 goto resubmit; 1369 } 1370 } 1371 1372 align = (sc->sc_sc.chip & RTWN_CHIP_92E ? 7 : 127); 1373 1374 /* Process all of them. */ 1375 while (npkts-- > 0) { 1376 if (__predict_false(len < sizeof(*rxd))) 1377 break; 1378 rxd = (struct r92c_rx_desc_usb *)buf; 1379 rxdw0 = letoh32(rxd->rxdw0); 1380 1381 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1382 if (__predict_false(pktlen == 0)) 1383 break; 1384 1385 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1386 1387 /* Make sure everything fits in xfer. */ 1388 totlen = sizeof(*rxd) + infosz + pktlen; 1389 if (__predict_false(totlen > len)) 1390 break; 1391 1392 /* Process 802.11 frame. */ 1393 urtwn_rx_frame(sc, buf, pktlen, &ml); 1394 1395 /* Handle chunk alignment. */ 1396 totlen = (totlen + align) & ~align; 1397 buf += totlen; 1398 len -= totlen; 1399 } 1400 if_input(&ic->ic_if, &ml); 1401 1402 resubmit: 1403 /* Setup a new transfer. */ 1404 usbd_setup_xfer(xfer, sc->rx_pipe, data, data->buf, URTWN_RXBUFSZ, 1405 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, urtwn_rxeof); 1406 error = usbd_transfer(data->xfer); 1407 if (error != 0 && error != USBD_IN_PROGRESS) 1408 DPRINTF(("could not set up new transfer: %d\n", error)); 1409 } 1410 1411 void 1412 urtwn_txeof(struct usbd_xfer *xfer, void *priv, 1413 usbd_status status) 1414 { 1415 struct urtwn_tx_data *data = priv; 1416 struct urtwn_softc *sc = data->sc; 1417 struct ifnet *ifp = &sc->sc_sc.sc_ic.ic_if; 1418 int s; 1419 1420 s = splnet(); 1421 /* Put this Tx buffer back to our free list. */ 1422 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1423 1424 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1425 DPRINTF(("TX status=%d\n", status)); 1426 if (status == USBD_STALLED) 1427 usbd_clear_endpoint_stall_async(data->pipe); 1428 ifp->if_oerrors++; 1429 splx(s); 1430 return; 1431 } 1432 sc->sc_sc.sc_tx_timer = 0; 1433 1434 /* We just released a Tx buffer, notify Tx. */ 1435 if (ifq_is_oactive(&ifp->if_snd)) { 1436 ifq_clr_oactive(&ifp->if_snd); 1437 rtwn_start(ifp); 1438 } 1439 splx(s); 1440 } 1441 1442 void 1443 urtwn_tx_fill_desc(struct urtwn_softc *sc, uint8_t **txdp, struct mbuf *m, 1444 struct ieee80211_frame *wh, struct ieee80211_key *k, 1445 struct ieee80211_node *ni) 1446 { 1447 struct r92c_tx_desc_usb *txd; 1448 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1449 uint8_t raid, type; 1450 uint32_t pktlen; 1451 1452 txd = (struct r92c_tx_desc_usb *)*txdp; 1453 (*txdp) += sizeof(*txd); 1454 memset(txd, 0, sizeof(*txd)); 1455 1456 pktlen = m->m_pkthdr.len; 1457 if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) { 1458 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, 1459 R92C_TXDW1_CIPHER_AES)); 1460 pktlen += IEEE80211_CCMP_HDRLEN; 1461 } 1462 1463 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1464 1465 txd->txdw0 |= htole32( 1466 SM(R92C_TXDW0_PKTLEN, pktlen) | 1467 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1468 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1469 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1470 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1471 1472 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1473 type == IEEE80211_FC0_TYPE_DATA) { 1474 if (ic->ic_curmode == IEEE80211_MODE_11B || 1475 (sc->sc_sc.sc_flags & RTWN_FLAG_FORCE_RAID_11B)) 1476 raid = R92C_RAID_11B; 1477 else 1478 raid = R92C_RAID_11BG; 1479 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1480 txd->txdw1 |= htole32( 1481 SM(R88E_TXDW1_MACID, R92C_MACID_BSS) | 1482 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1483 SM(R92C_TXDW1_RAID, raid)); 1484 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1485 /* Request TX status report for AMRR */ 1486 txd->txdw2 |= htole32(R92C_TXDW2_CCX_RPT); 1487 } else { 1488 txd->txdw1 |= htole32( 1489 SM(R92C_TXDW1_MACID, R92C_MACID_BSS) | 1490 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1491 SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1492 } 1493 1494 if (pktlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 1495 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1496 R92C_TXDW4_HWRTSEN); 1497 } else if (ic->ic_flags & IEEE80211_F_USEPROT) { 1498 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1499 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1500 R92C_TXDW4_HWRTSEN); 1501 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1502 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1503 R92C_TXDW4_HWRTSEN); 1504 } 1505 } 1506 txd->txdw5 |= htole32(0x0001ff00); 1507 1508 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1509 /* Use AMRR */ 1510 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1511 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 1512 ni->ni_txrate)); 1513 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1514 ni->ni_txrate)); 1515 } else { 1516 /* Send RTS at OFDM24 and data at OFDM54. */ 1517 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1518 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1519 } 1520 } else { 1521 txd->txdw1 |= htole32( 1522 SM(R92C_TXDW1_MACID, 0) | 1523 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1524 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1525 1526 /* Force CCK1. */ 1527 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1528 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1529 } 1530 /* Set sequence number (already little endian). */ 1531 txd->txdseq |= (*(uint16_t *)wh->i_seq) >> IEEE80211_SEQ_SEQ_SHIFT; 1532 1533 if (!ieee80211_has_qos(wh)) { 1534 /* Use HW sequence numbering for non-QoS frames. */ 1535 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1536 txd->txdseq |= htole16(R92C_TXDW3_HWSEQEN); 1537 } else 1538 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1539 } 1540 1541 void 1542 urtwn_tx_fill_desc_gen2(struct urtwn_softc *sc, uint8_t **txdp, struct mbuf *m, 1543 struct ieee80211_frame *wh, struct ieee80211_key *k, 1544 struct ieee80211_node *ni) 1545 { 1546 struct r92e_tx_desc_usb *txd; 1547 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1548 uint8_t raid, type; 1549 uint32_t pktlen; 1550 1551 txd = (struct r92e_tx_desc_usb *)*txdp; 1552 (*txdp) += sizeof(*txd); 1553 memset(txd, 0, sizeof(*txd)); 1554 1555 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1556 1557 pktlen = m->m_pkthdr.len; 1558 if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) { 1559 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, 1560 R92C_TXDW1_CIPHER_AES)); 1561 pktlen += IEEE80211_CCMP_HDRLEN; 1562 } 1563 1564 txd->txdw0 |= htole32( 1565 SM(R92C_TXDW0_PKTLEN, pktlen) | 1566 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1567 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1568 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1569 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1570 1571 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1572 type == IEEE80211_FC0_TYPE_DATA) { 1573 if (ic->ic_curmode == IEEE80211_MODE_11B || 1574 (sc->sc_sc.sc_flags & RTWN_FLAG_FORCE_RAID_11B)) 1575 raid = R92E_RAID_11B; 1576 else 1577 raid = R92E_RAID_11BG; 1578 txd->txdw1 |= htole32( 1579 SM(R92E_TXDW1_MACID, R92C_MACID_BSS) | 1580 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1581 SM(R92C_TXDW1_RAID, raid)); 1582 /* Request TX status report for AMRR */ 1583 txd->txdw2 |= htole32(R92C_TXDW2_CCX_RPT | R88E_TXDW2_AGGBK); 1584 1585 if (pktlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 1586 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1587 R92C_TXDW4_HWRTSEN); 1588 } else if (ic->ic_flags & IEEE80211_F_USEPROT) { 1589 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1590 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1591 R92C_TXDW4_HWRTSEN); 1592 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1593 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1594 R92C_TXDW4_HWRTSEN); 1595 } 1596 } 1597 txd->txdw5 |= htole32(0x0001ff00); 1598 1599 /* Use AMRR */ 1600 txd->txdw3 |= htole32(R92E_TXDW3_DRVRATE); 1601 txd->txdw4 |= htole32(SM(R92E_TXDW4_RTSRATE, ni->ni_txrate)); 1602 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATE, ni->ni_txrate)); 1603 } else { 1604 txd->txdw1 |= htole32( 1605 SM(R92E_TXDW1_MACID, 0) | 1606 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1607 SM(R92C_TXDW1_RAID, R92E_RAID_11B)); 1608 1609 /* Force CCK1. */ 1610 txd->txdw3 |= htole32(R92E_TXDW3_DRVRATE); 1611 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATE, 0)); 1612 } 1613 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATEFB, 0x1f)); 1614 1615 txd->txdseq2 |= htole16(SM(R92E_TXDSEQ2_HWSEQ, *(uint16_t *)wh->i_seq)); 1616 1617 if (!ieee80211_has_qos(wh)) { 1618 /* Use HW sequence numbering for non-QoS frames. */ 1619 txd->txdw7 |= htole16(R92C_TXDW3_HWSEQEN); 1620 } 1621 } 1622 1623 int 1624 urtwn_tx(void *cookie, struct mbuf *m, struct ieee80211_node *ni) 1625 { 1626 struct urtwn_softc *sc = cookie; 1627 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1628 struct ieee80211_frame *wh; 1629 struct ieee80211_key *k = NULL; 1630 struct urtwn_tx_data *data; 1631 struct usbd_pipe *pipe; 1632 uint16_t qos, sum; 1633 uint8_t tid, qid; 1634 int i, xferlen, error, headerlen; 1635 uint8_t *txdp; 1636 1637 wh = mtod(m, struct ieee80211_frame *); 1638 1639 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1640 k = ieee80211_get_txkey(ic, wh, ni); 1641 if (k->k_cipher != IEEE80211_CIPHER_CCMP) { 1642 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1643 return (ENOBUFS); 1644 wh = mtod(m, struct ieee80211_frame *); 1645 } 1646 } 1647 1648 if (ieee80211_has_qos(wh)) { 1649 qos = ieee80211_get_qos(wh); 1650 tid = qos & IEEE80211_QOS_TID; 1651 qid = ieee80211_up_to_ac(ic, tid); 1652 } else if ((wh->i_fc[1] & IEEE80211_FC0_TYPE_MASK) 1653 != IEEE80211_FC0_TYPE_DATA) { 1654 /* Use AC VO for management frames. */ 1655 qid = EDCA_AC_VO; 1656 } else 1657 qid = EDCA_AC_BE; 1658 1659 /* Get the USB pipe to use for this AC. */ 1660 pipe = sc->tx_pipe[sc->ac2idx[qid]]; 1661 1662 /* Grab a Tx buffer from our free list. */ 1663 data = TAILQ_FIRST(&sc->tx_free_list); 1664 TAILQ_REMOVE(&sc->tx_free_list, data, next); 1665 1666 /* Fill Tx descriptor. */ 1667 txdp = data->buf; 1668 if (sc->sc_sc.chip & RTWN_CHIP_92E) 1669 urtwn_tx_fill_desc_gen2(sc, &txdp, m, wh, k, ni); 1670 else 1671 urtwn_tx_fill_desc(sc, &txdp, m, wh, k, ni); 1672 1673 /* Compute Tx descriptor checksum. */ 1674 sum = 0; 1675 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 1676 sum ^= ((uint16_t *)data->buf)[i]; 1677 ((uint16_t *)data->buf)[R92C_TXDESC_SUMOFFSET] = sum; 1678 1679 #if NBPFILTER > 0 1680 if (__predict_false(sc->sc_drvbpf != NULL)) { 1681 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1682 struct mbuf mb; 1683 1684 tap->wt_flags = 0; 1685 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1686 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1687 1688 mb.m_data = (caddr_t)tap; 1689 mb.m_len = sc->sc_txtap_len; 1690 mb.m_next = m; 1691 mb.m_nextpkt = NULL; 1692 mb.m_type = 0; 1693 mb.m_flags = 0; 1694 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1695 } 1696 #endif 1697 1698 if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) { 1699 xferlen = (txdp - data->buf) + m->m_pkthdr.len + 1700 IEEE80211_CCMP_HDRLEN; 1701 headerlen = ieee80211_get_hdrlen(wh); 1702 1703 m_copydata(m, 0, headerlen, txdp); 1704 txdp += headerlen; 1705 1706 k->k_tsc++; 1707 txdp[0] = k->k_tsc; 1708 txdp[1] = k->k_tsc >> 8; 1709 txdp[2] = 0; 1710 txdp[3] = k->k_id | IEEE80211_WEP_EXTIV; 1711 txdp[4] = k->k_tsc >> 16; 1712 txdp[5] = k->k_tsc >> 24; 1713 txdp[6] = k->k_tsc >> 32; 1714 txdp[7] = k->k_tsc >> 40; 1715 txdp += IEEE80211_CCMP_HDRLEN; 1716 1717 m_copydata(m, headerlen, m->m_pkthdr.len - headerlen, txdp); 1718 m_freem(m); 1719 } else { 1720 xferlen = (txdp - data->buf) + m->m_pkthdr.len; 1721 m_copydata(m, 0, m->m_pkthdr.len, txdp); 1722 m_freem(m); 1723 } 1724 1725 data->pipe = pipe; 1726 usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen, 1727 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTWN_TX_TIMEOUT, 1728 urtwn_txeof); 1729 error = usbd_transfer(data->xfer); 1730 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) { 1731 /* Put this Tx buffer back to our free list. */ 1732 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1733 return (error); 1734 } 1735 ieee80211_release_node(ic, ni); 1736 return (0); 1737 } 1738 1739 int 1740 urtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1741 { 1742 struct rtwn_softc *sc_sc = ifp->if_softc; 1743 struct device *self = sc_sc->sc_pdev; 1744 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1745 int error; 1746 1747 if (usbd_is_dying(sc->sc_udev)) 1748 return ENXIO; 1749 1750 usbd_ref_incr(sc->sc_udev); 1751 error = rtwn_ioctl(ifp, cmd, data); 1752 usbd_ref_decr(sc->sc_udev); 1753 1754 return (error); 1755 } 1756 1757 int 1758 urtwn_r92c_power_on(struct urtwn_softc *sc) 1759 { 1760 uint32_t reg; 1761 int ntries; 1762 1763 /* Wait for autoload done bit. */ 1764 for (ntries = 0; ntries < 1000; ntries++) { 1765 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 1766 break; 1767 DELAY(5); 1768 } 1769 if (ntries == 1000) { 1770 printf("%s: timeout waiting for chip autoload\n", 1771 sc->sc_dev.dv_xname); 1772 return (ETIMEDOUT); 1773 } 1774 1775 /* Unlock ISO/CLK/Power control register. */ 1776 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 1777 /* Move SPS into PWM mode. */ 1778 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 1779 DELAY(100); 1780 1781 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 1782 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 1783 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 1784 reg | R92C_LDOV12D_CTRL_LDV12_EN); 1785 DELAY(100); 1786 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 1787 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 1788 ~R92C_SYS_ISO_CTRL_MD2PP); 1789 } 1790 1791 /* Auto enable WLAN. */ 1792 urtwn_write_2(sc, R92C_APS_FSMCO, 1793 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1794 for (ntries = 0; ntries < 1000; ntries++) { 1795 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1796 R92C_APS_FSMCO_APFM_ONMAC)) 1797 break; 1798 DELAY(5); 1799 } 1800 if (ntries == 1000) { 1801 printf("%s: timeout waiting for MAC auto ON\n", 1802 sc->sc_dev.dv_xname); 1803 return (ETIMEDOUT); 1804 } 1805 1806 /* Enable radio, GPIO and LED functions. */ 1807 urtwn_write_2(sc, R92C_APS_FSMCO, 1808 R92C_APS_FSMCO_AFSM_HSUS | 1809 R92C_APS_FSMCO_PDN_EN | 1810 R92C_APS_FSMCO_PFM_ALDN); 1811 /* Release RF digital isolation. */ 1812 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1813 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 1814 1815 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1816 reg = urtwn_read_2(sc, R92C_CR); 1817 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1818 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1819 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 1820 R92C_CR_ENSEC; 1821 urtwn_write_2(sc, R92C_CR, reg); 1822 1823 urtwn_write_1(sc, 0xfe10, 0x19); 1824 return (0); 1825 } 1826 1827 int 1828 urtwn_r92e_power_on(struct urtwn_softc *sc) 1829 { 1830 uint32_t reg; 1831 int ntries; 1832 1833 if (urtwn_read_4(sc, R92C_SYS_CFG) & R92E_SYS_CFG_SPSLDO_SEL) { 1834 /* LDO. */ 1835 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 1836 } else { 1837 reg = urtwn_read_4(sc, R92C_SYS_SWR_CTRL2); 1838 reg &= 0xff0fffff; 1839 reg |= 0x00500000; 1840 urtwn_write_4(sc, R92C_SYS_SWR_CTRL2, reg); 1841 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 1842 } 1843 1844 /* 40MHz crystal source */ 1845 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 1846 urtwn_read_1(sc, R92C_AFE_PLL_CTRL) & 0xfb); 1847 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL_EXT, 1848 urtwn_read_4(sc, R92C_AFE_XTAL_CTRL_EXT) & 0xfffffc7f); 1849 1850 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 1851 urtwn_read_1(sc, R92C_AFE_PLL_CTRL) & 0xbf); 1852 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL_EXT, 1853 urtwn_read_4(sc, R92C_AFE_XTAL_CTRL_EXT) & 0xffdfffff); 1854 1855 /* Disable HWPDN. */ 1856 urtwn_write_2(sc, R92C_APS_FSMCO, 1857 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 1858 for (ntries = 0; ntries < 5000; ntries++) { 1859 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 1860 break; 1861 DELAY(10); 1862 } 1863 if (ntries == 5000) { 1864 printf("%s: timeout waiting for chip power up\n", 1865 sc->sc_dev.dv_xname); 1866 return (ETIMEDOUT); 1867 } 1868 1869 /* Disable WL suspend. */ 1870 urtwn_write_2(sc, R92C_APS_FSMCO, 1871 urtwn_read_2(sc, R92C_APS_FSMCO) & 1872 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 1873 1874 /* Auto enable WLAN. */ 1875 urtwn_write_4(sc, R92C_APS_FSMCO, 1876 urtwn_read_4(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 1877 urtwn_write_2(sc, R92C_APS_FSMCO, 1878 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1879 for (ntries = 0; ntries < 5000; ntries++) { 1880 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1881 R92C_APS_FSMCO_APFM_ONMAC)) 1882 break; 1883 DELAY(10); 1884 } 1885 if (ntries == 5000) { 1886 printf("%s: timeout waiting for MAC auto ON\n", 1887 sc->sc_dev.dv_xname); 1888 return (ETIMEDOUT); 1889 } 1890 1891 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1892 urtwn_write_2(sc, R92C_CR, 0); 1893 reg = urtwn_read_2(sc, R92C_CR); 1894 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1895 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1896 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 1897 urtwn_write_2(sc, R92C_CR, reg); 1898 return (0); 1899 } 1900 1901 int 1902 urtwn_r88e_power_on(struct urtwn_softc *sc) 1903 { 1904 uint32_t reg; 1905 int ntries; 1906 1907 /* Wait for power ready bit. */ 1908 for (ntries = 0; ntries < 5000; ntries++) { 1909 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 1910 break; 1911 DELAY(10); 1912 } 1913 if (ntries == 5000) { 1914 printf("%s: timeout waiting for chip power up\n", 1915 sc->sc_dev.dv_xname); 1916 return (ETIMEDOUT); 1917 } 1918 1919 /* Reset BB. */ 1920 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 1921 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 1922 R92C_SYS_FUNC_EN_BB_GLB_RST)); 1923 1924 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 1925 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 1926 1927 /* Disable HWPDN. */ 1928 urtwn_write_2(sc, R92C_APS_FSMCO, 1929 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 1930 /* Disable WL suspend. */ 1931 urtwn_write_2(sc, R92C_APS_FSMCO, 1932 urtwn_read_2(sc, R92C_APS_FSMCO) & 1933 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 1934 1935 /* Auto enable WLAN. */ 1936 urtwn_write_2(sc, R92C_APS_FSMCO, 1937 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1938 for (ntries = 0; ntries < 5000; ntries++) { 1939 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1940 R92C_APS_FSMCO_APFM_ONMAC)) 1941 break; 1942 DELAY(10); 1943 } 1944 if (ntries == 5000) { 1945 printf("%s: timeout waiting for MAC auto ON\n", 1946 sc->sc_dev.dv_xname); 1947 return (ETIMEDOUT); 1948 } 1949 1950 /* Enable LDO normal mode. */ 1951 urtwn_write_1(sc, R92C_LPLDO_CTRL, 1952 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 1953 1954 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1955 urtwn_write_2(sc, R92C_CR, 0); 1956 reg = urtwn_read_2(sc, R92C_CR); 1957 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1958 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1959 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 1960 urtwn_write_2(sc, R92C_CR, reg); 1961 return (0); 1962 } 1963 1964 int 1965 urtwn_llt_init(struct urtwn_softc *sc, int page_count) 1966 { 1967 int i, error, pktbuf_count; 1968 1969 pktbuf_count = (sc->sc_sc.chip & RTWN_CHIP_88E) ? 1970 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 1971 1972 /* Reserve pages [0; page_count]. */ 1973 for (i = 0; i < page_count; i++) { 1974 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1975 return (error); 1976 } 1977 /* NB: 0xff indicates end-of-list. */ 1978 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 1979 return (error); 1980 /* 1981 * Use pages [page_count + 1; pktbuf_count - 1] 1982 * as ring buffer. 1983 */ 1984 for (++i; i < pktbuf_count - 1; i++) { 1985 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1986 return (error); 1987 } 1988 /* Make the last page point to the beginning of the ring buffer. */ 1989 error = urtwn_llt_write(sc, i, page_count + 1); 1990 return (error); 1991 } 1992 1993 int 1994 urtwn_auto_llt_init(struct urtwn_softc *sc) 1995 { 1996 int ntries; 1997 1998 urtwn_write_4(sc, R92E_AUTO_LLT, urtwn_read_4(sc, 1999 R92E_AUTO_LLT) | R92E_AUTO_LLT_EN); 2000 for (ntries = 0; ntries < 1000; ntries++) { 2001 if (!(urtwn_read_4(sc, R92E_AUTO_LLT) & R92E_AUTO_LLT_EN)) 2002 return (0); 2003 DELAY(2); 2004 } 2005 2006 return (ETIMEDOUT); 2007 } 2008 2009 int 2010 urtwn_fw_loadpage(void *cookie, int page, uint8_t *buf, int len) 2011 { 2012 struct urtwn_softc *sc = cookie; 2013 uint32_t reg; 2014 int off, mlen, error = 0; 2015 2016 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2017 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2018 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2019 2020 off = R92C_FW_START_ADDR; 2021 while (len > 0) { 2022 if (len > 196) 2023 mlen = 196; 2024 else if (len > 4) 2025 mlen = 4; 2026 else 2027 mlen = 1; 2028 error = urtwn_write_region_1(sc, off, buf, mlen); 2029 if (error != 0) 2030 break; 2031 off += mlen; 2032 buf += mlen; 2033 len -= mlen; 2034 } 2035 return (error); 2036 } 2037 2038 int 2039 urtwn_load_firmware(void *cookie, u_char **fw, size_t *len) 2040 { 2041 struct urtwn_softc *sc = cookie; 2042 const char *name; 2043 int error; 2044 2045 if (sc->sc_sc.chip & RTWN_CHIP_92E) 2046 name = "urtwn-rtl8192eu_nic"; 2047 else if (sc->sc_sc.chip & RTWN_CHIP_88E) 2048 name = "urtwn-rtl8188eufw"; 2049 else if ((sc->sc_sc.chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2050 RTWN_CHIP_UMC_A_CUT) 2051 name = "urtwn-rtl8192cfwU"; 2052 else 2053 name = "urtwn-rtl8192cfwT"; 2054 2055 error = loadfirmware(name, fw, len); 2056 if (error) 2057 printf("%s: could not read firmware %s (error %d)\n", 2058 sc->sc_dev.dv_xname, name, error); 2059 return (error); 2060 } 2061 2062 int 2063 urtwn_dma_init(void *cookie) 2064 { 2065 struct urtwn_softc *sc = cookie; 2066 uint32_t reg; 2067 uint16_t dmasize; 2068 int hqpages, lqpages, nqpages, pagecnt, boundary; 2069 int error, hashq, haslq, hasnq; 2070 2071 /* Default initialization of chipset values. */ 2072 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2073 hqpages = R88E_HQ_NPAGES; 2074 lqpages = R88E_LQ_NPAGES; 2075 nqpages = R88E_NQ_NPAGES; 2076 pagecnt = R88E_TX_PAGE_COUNT; 2077 boundary = R88E_TX_PAGE_BOUNDARY; 2078 dmasize = R88E_MAX_RX_DMA_SIZE; 2079 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2080 hqpages = R92E_HQ_NPAGES; 2081 lqpages = R92E_LQ_NPAGES; 2082 nqpages = R92E_NQ_NPAGES; 2083 pagecnt = R92E_TX_PAGE_COUNT; 2084 boundary = R92E_TX_PAGE_BOUNDARY; 2085 dmasize = R92E_MAX_RX_DMA_SIZE; 2086 } else { 2087 hqpages = R92C_HQ_NPAGES; 2088 lqpages = R92C_LQ_NPAGES; 2089 nqpages = R92C_NQ_NPAGES; 2090 pagecnt = R92C_TX_PAGE_COUNT; 2091 boundary = R92C_TX_PAGE_BOUNDARY; 2092 dmasize = R92C_MAX_RX_DMA_SIZE; 2093 } 2094 2095 /* Initialize LLT table. */ 2096 if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2097 error = urtwn_auto_llt_init(sc); 2098 } else { 2099 error = urtwn_llt_init(sc, pagecnt); 2100 } 2101 if (error != 0) 2102 return (error); 2103 2104 /* Get Tx queues to USB endpoints mapping. */ 2105 hashq = hasnq = haslq = 0; 2106 switch (sc->ntx) { 2107 case 3: 2108 haslq = 1; 2109 pagecnt -= lqpages; 2110 /* FALLTHROUGH */ 2111 case 2: 2112 hasnq = 1; 2113 pagecnt -= nqpages; 2114 /* FALLTHROUGH */ 2115 case 1: 2116 hashq = 1; 2117 pagecnt -= hqpages; 2118 break; 2119 } 2120 2121 /* Set number of pages for normal priority queue. */ 2122 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2123 urtwn_write_4(sc, R92C_RQPN, 2124 /* Set number of pages for public queue. */ 2125 SM(R92C_RQPN_PUBQ, pagecnt) | 2126 /* Set number of pages for high priority queue. */ 2127 SM(R92C_RQPN_HPQ, hashq ? hqpages : 0) | 2128 /* Set number of pages for low priority queue. */ 2129 SM(R92C_RQPN_LPQ, haslq ? lqpages : 0) | 2130 /* Load values. */ 2131 R92C_RQPN_LD); 2132 2133 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, boundary); 2134 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, boundary); 2135 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, boundary); 2136 urtwn_write_1(sc, R92C_TRXFF_BNDY, boundary); 2137 urtwn_write_1(sc, R92C_TDECTRL + 1, boundary); 2138 2139 /* Set queue to USB pipe mapping. */ 2140 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2141 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2142 if (haslq) 2143 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2144 else if (hashq) { 2145 if (!hasnq) 2146 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2147 else 2148 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2149 } 2150 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2151 2152 /* Set Tx/Rx transfer page boundary. */ 2153 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, dmasize - 1); 2154 2155 if (!(sc->sc_sc.chip & RTWN_CHIP_92E)) { 2156 /* Set Tx/Rx transfer page size. */ 2157 urtwn_write_1(sc, R92C_PBP, 2158 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2159 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2160 } 2161 return (error); 2162 } 2163 2164 void 2165 urtwn_aggr_init(void *cookie) 2166 { 2167 struct urtwn_softc *sc = cookie; 2168 uint32_t reg = 0; 2169 int dmasize, dmatiming, ndesc; 2170 2171 /* Set burst packet length. */ 2172 if (sc->sc_sc.chip & RTWN_CHIP_92E) 2173 urtwn_burstlen_init(sc); 2174 2175 if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2176 dmasize = 6; 2177 dmatiming = 32; 2178 ndesc = 3; 2179 } else { 2180 dmasize = 48; 2181 dmatiming = 4; 2182 ndesc = (sc->sc_sc.chip & RTWN_CHIP_88E) ? 1 : 6; 2183 } 2184 2185 /* Tx aggregation setting. */ 2186 if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2187 urtwn_write_1(sc, R92E_DWBCN1_CTRL, ndesc << 1); 2188 } else { 2189 reg = urtwn_read_4(sc, R92C_TDECTRL); 2190 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, ndesc); 2191 urtwn_write_4(sc, R92C_TDECTRL, reg); 2192 } 2193 2194 /* Rx aggregation setting. */ 2195 if (!(sc->sc_sc.chip & RTWN_CHIP_92E)) { 2196 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 2197 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 2198 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 2199 } 2200 2201 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, dmasize); 2202 if (sc->sc_sc.chip & (RTWN_CHIP_92C | RTWN_CHIP_88C)) 2203 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, dmatiming); 2204 else 2205 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, dmatiming); 2206 2207 /* Drop incorrect bulk out. */ 2208 urtwn_write_4(sc, R92C_TXDMA_OFFSET_CHK, 2209 urtwn_read_4(sc, R92C_TXDMA_OFFSET_CHK) | 2210 R92C_TXDMA_OFFSET_CHK_DROP_DATA_EN); 2211 } 2212 2213 void 2214 urtwn_mac_init(void *cookie) 2215 { 2216 struct urtwn_softc *sc = cookie; 2217 int i; 2218 2219 /* Write MAC initialization values. */ 2220 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2221 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2222 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2223 rtl8188eu_mac[i].val); 2224 } 2225 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2226 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2227 for (i = 0; i < nitems(rtl8192eu_mac); i++) { 2228 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 2229 rtl8192eu_mac[i].val); 2230 } 2231 } else { 2232 for (i = 0; i < nitems(rtl8192cu_mac); i++) 2233 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2234 rtl8192cu_mac[i].val); 2235 } 2236 } 2237 2238 void 2239 urtwn_bb_init(void *cookie) 2240 { 2241 struct urtwn_softc *sc = cookie; 2242 const struct r92c_bb_prog *prog; 2243 uint32_t reg; 2244 uint8_t xtal; 2245 int i; 2246 2247 /* Enable BB and RF. */ 2248 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2249 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2250 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2251 R92C_SYS_FUNC_EN_DIO_RF); 2252 2253 if (!(sc->sc_sc.chip & (RTWN_CHIP_88E | RTWN_CHIP_92E))) 2254 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2255 2256 urtwn_write_1(sc, R92C_RF_CTRL, 2257 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2258 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2259 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2260 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2261 2262 if (!(sc->sc_sc.chip & (RTWN_CHIP_88E | RTWN_CHIP_92E))) { 2263 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2264 urtwn_write_1(sc, 0x15, 0xe9); 2265 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2266 } 2267 2268 /* Select BB programming based on board type. */ 2269 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2270 prog = &rtl8188eu_bb_prog; 2271 else if (sc->sc_sc.chip & RTWN_CHIP_92E) 2272 prog = &rtl8192eu_bb_prog; 2273 else if (!(sc->sc_sc.chip & RTWN_CHIP_92C)) { 2274 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD) 2275 prog = &rtl8188ce_bb_prog; 2276 else if (sc->sc_sc.board_type == R92C_BOARD_TYPE_HIGHPA) 2277 prog = &rtl8188ru_bb_prog; 2278 else 2279 prog = &rtl8188cu_bb_prog; 2280 } else { 2281 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD) 2282 prog = &rtl8192ce_bb_prog; 2283 else 2284 prog = &rtl8192cu_bb_prog; 2285 } 2286 /* Write BB initialization values. */ 2287 for (i = 0; i < prog->count; i++) { 2288 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2289 DELAY(1); 2290 } 2291 2292 if (sc->sc_sc.chip & RTWN_CHIP_92C_1T2R) { 2293 /* 8192C 1T only configuration. */ 2294 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2295 reg = (reg & ~0x00000003) | 0x2; 2296 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2297 2298 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2299 reg = (reg & ~0x00300033) | 0x00200022; 2300 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2301 2302 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2303 reg = (reg & ~0xff000000) | 0x45 << 24; 2304 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2305 2306 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2307 reg = (reg & ~0x000000ff) | 0x23; 2308 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2309 2310 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2311 reg = (reg & ~0x00000030) | 1 << 4; 2312 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2313 2314 reg = urtwn_bb_read(sc, 0xe74); 2315 reg = (reg & ~0x0c000000) | 2 << 26; 2316 urtwn_bb_write(sc, 0xe74, reg); 2317 reg = urtwn_bb_read(sc, 0xe78); 2318 reg = (reg & ~0x0c000000) | 2 << 26; 2319 urtwn_bb_write(sc, 0xe78, reg); 2320 reg = urtwn_bb_read(sc, 0xe7c); 2321 reg = (reg & ~0x0c000000) | 2 << 26; 2322 urtwn_bb_write(sc, 0xe7c, reg); 2323 reg = urtwn_bb_read(sc, 0xe80); 2324 reg = (reg & ~0x0c000000) | 2 << 26; 2325 urtwn_bb_write(sc, 0xe80, reg); 2326 reg = urtwn_bb_read(sc, 0xe88); 2327 reg = (reg & ~0x0c000000) | 2 << 26; 2328 urtwn_bb_write(sc, 0xe88, reg); 2329 } 2330 2331 /* Write AGC values. */ 2332 for (i = 0; i < prog->agccount; i++) { 2333 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2334 prog->agcvals[i]); 2335 DELAY(1); 2336 } 2337 2338 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2339 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2340 DELAY(1); 2341 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2342 DELAY(1); 2343 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2344 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040022); 2345 DELAY(1); 2346 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040020); 2347 DELAY(1); 2348 } 2349 2350 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2351 xtal = sc->sc_sc.crystal_cap & 0x3f; 2352 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2353 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2354 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, xtal | xtal << 6)); 2355 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2356 xtal = sc->sc_sc.crystal_cap & 0x3f; 2357 reg = urtwn_read_4(sc, R92C_AFE_CTRL3); 2358 reg &= 0xff000fff; 2359 reg |= (xtal | (xtal << 6)) << 12; 2360 urtwn_write_4(sc, R92C_AFE_CTRL3, reg); 2361 2362 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0x000f81fb); 2363 } 2364 2365 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & R92C_HSSI_PARAM2_CCK_HIPWR) 2366 sc->sc_sc.sc_flags |= RTWN_FLAG_CCK_HIPWR; 2367 } 2368 2369 void 2370 urtwn_burstlen_init(struct urtwn_softc *sc) 2371 { 2372 uint8_t reg; 2373 2374 reg = urtwn_read_1(sc, R92E_RXDMA_PRO); 2375 reg &= ~0x30; 2376 switch (sc->sc_udev->speed) { 2377 case USB_SPEED_HIGH: 2378 urtwn_write_1(sc, R92E_RXDMA_PRO, reg | 0x1e); 2379 break; 2380 default: 2381 urtwn_write_1(sc, R92E_RXDMA_PRO, reg | 0x2e); 2382 break; 2383 } 2384 } 2385 2386 int 2387 urtwn_power_on(void *cookie) 2388 { 2389 struct urtwn_softc *sc = cookie; 2390 2391 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2392 return (urtwn_r88e_power_on(sc)); 2393 else if (sc->sc_sc.chip & RTWN_CHIP_92E) 2394 return (urtwn_r92e_power_on(sc)); 2395 2396 return (urtwn_r92c_power_on(sc)); 2397 } 2398 2399 int 2400 urtwn_alloc_buffers(void *cookie) 2401 { 2402 struct urtwn_softc *sc = cookie; 2403 int error; 2404 2405 /* Init host async commands ring. */ 2406 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 2407 2408 /* Allocate Tx/Rx buffers. */ 2409 error = urtwn_alloc_rx_list(sc); 2410 if (error != 0) { 2411 printf("%s: could not allocate Rx buffers\n", 2412 sc->sc_dev.dv_xname); 2413 return (error); 2414 } 2415 error = urtwn_alloc_tx_list(sc); 2416 if (error != 0) { 2417 printf("%s: could not allocate Tx buffers\n", 2418 sc->sc_dev.dv_xname); 2419 return (error); 2420 } 2421 2422 return (0); 2423 } 2424 2425 int 2426 urtwn_init(void *cookie) 2427 { 2428 struct urtwn_softc *sc = cookie; 2429 int i, error; 2430 2431 if (sc->sc_sc.chip & RTWN_CHIP_92E) 2432 urtwn_write_1(sc, R92C_ACLK_MON, 0); 2433 2434 /* Queue Rx xfers. */ 2435 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 2436 struct urtwn_rx_data *data = &sc->rx_data[i]; 2437 2438 usbd_setup_xfer(data->xfer, sc->rx_pipe, data, data->buf, 2439 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 2440 USBD_NO_TIMEOUT, urtwn_rxeof); 2441 error = usbd_transfer(data->xfer); 2442 if (error != 0 && error != USBD_IN_PROGRESS) 2443 return (error); 2444 } 2445 2446 ieee80211_amrr_node_init(&sc->amrr, &sc->amn); 2447 2448 /* 2449 * Enable TX reports for AMRR. 2450 * In order to get reports we need to explicitly reset the register. 2451 */ 2452 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2453 urtwn_write_1(sc, R88E_TX_RPT_CTRL, (urtwn_read_1(sc, 2454 R88E_TX_RPT_CTRL) & ~0) | R88E_TX_RPT_CTRL_EN); 2455 2456 return (0); 2457 } 2458 2459 void 2460 urtwn_stop(void *cookie) 2461 { 2462 struct urtwn_softc *sc = cookie; 2463 int i; 2464 2465 /* Abort Tx. */ 2466 for (i = 0; i < R92C_MAX_EPOUT; i++) { 2467 if (sc->tx_pipe[i] != NULL) 2468 usbd_abort_pipe(sc->tx_pipe[i]); 2469 } 2470 /* Stop Rx pipe. */ 2471 usbd_abort_pipe(sc->rx_pipe); 2472 /* Free Tx/Rx buffers. */ 2473 urtwn_free_tx_list(sc); 2474 urtwn_free_rx_list(sc); 2475 } 2476 2477 int 2478 urtwn_is_oactive(void *cookie) 2479 { 2480 struct urtwn_softc *sc = cookie; 2481 2482 return (TAILQ_EMPTY(&sc->tx_free_list)); 2483 } 2484