1 /* $OpenBSD: if_urtwn.c,v 1.92 2020/07/06 10:38:54 jsg Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss@yahoo.com.au> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU/ 23 * RTL8192EU. 24 */ 25 26 #include "bpfilter.h" 27 28 #include <sys/param.h> 29 #include <sys/sockio.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/timeout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 #include <sys/endian.h> 38 39 #include <machine/bus.h> 40 #include <machine/intr.h> 41 42 #if NBPFILTER > 0 43 #include <net/bpf.h> 44 #endif 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 49 #include <netinet/in.h> 50 #include <netinet/if_ether.h> 51 52 #include <net80211/ieee80211_var.h> 53 #include <net80211/ieee80211_amrr.h> 54 #include <net80211/ieee80211_radiotap.h> 55 56 #include <dev/usb/usb.h> 57 #include <dev/usb/usbdi.h> 58 #include <dev/usb/usbdivar.h> 59 #include <dev/usb/usbdi_util.h> 60 #include <dev/usb/usbdevs.h> 61 62 #include <dev/ic/r92creg.h> 63 #include <dev/ic/rtwnvar.h> 64 65 /* Maximum number of output pipes is 3. */ 66 #define R92C_MAX_EPOUT 3 67 68 #define R92C_HQ_NPAGES 12 69 #define R92C_LQ_NPAGES 2 70 #define R92C_NQ_NPAGES 2 71 #define R92C_TXPKTBUF_COUNT 256 72 #define R92C_TX_PAGE_COUNT 248 73 #define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) 74 #define R92C_MAX_RX_DMA_SIZE 0x2800 75 76 #define R88E_HQ_NPAGES 0 77 #define R88E_LQ_NPAGES 9 78 #define R88E_NQ_NPAGES 0 79 #define R88E_TXPKTBUF_COUNT 177 80 #define R88E_TX_PAGE_COUNT 168 81 #define R88E_TX_PAGE_BOUNDARY (R88E_TX_PAGE_COUNT + 1) 82 #define R88E_MAX_RX_DMA_SIZE 0x2400 83 84 #define R92E_HQ_NPAGES 16 85 #define R92E_LQ_NPAGES 16 86 #define R92E_NQ_NPAGES 16 87 #define R92E_TX_PAGE_COUNT 248 88 #define R92E_TX_PAGE_BOUNDARY (R92E_TX_PAGE_COUNT + 1) 89 #define R92E_MAX_RX_DMA_SIZE 0x3fc0 90 91 #define R92C_TXDESC_SUMSIZE 32 92 #define R92C_TXDESC_SUMOFFSET 14 93 94 /* USB Requests. */ 95 #define R92C_REQ_REGS 0x05 96 97 /* 98 * Driver definitions. 99 */ 100 #define URTWN_RX_LIST_COUNT 1 101 #define URTWN_TX_LIST_COUNT 8 102 #define URTWN_HOST_CMD_RING_COUNT 32 103 104 #define URTWN_RXBUFSZ (16 * 1024) 105 #define URTWN_TXBUFSZ (sizeof(struct r92e_tx_desc_usb) + IEEE80211_MAX_LEN) 106 107 #define URTWN_RIDX_COUNT 28 108 109 #define URTWN_TX_TIMEOUT 5000 /* ms */ 110 111 #define URTWN_LED_LINK 0 112 #define URTWN_LED_DATA 1 113 114 struct urtwn_rx_radiotap_header { 115 struct ieee80211_radiotap_header wr_ihdr; 116 uint8_t wr_flags; 117 uint8_t wr_rate; 118 uint16_t wr_chan_freq; 119 uint16_t wr_chan_flags; 120 uint8_t wr_dbm_antsignal; 121 } __packed; 122 123 #define URTWN_RX_RADIOTAP_PRESENT \ 124 (1 << IEEE80211_RADIOTAP_FLAGS | \ 125 1 << IEEE80211_RADIOTAP_RATE | \ 126 1 << IEEE80211_RADIOTAP_CHANNEL | \ 127 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) 128 129 struct urtwn_tx_radiotap_header { 130 struct ieee80211_radiotap_header wt_ihdr; 131 uint8_t wt_flags; 132 uint16_t wt_chan_freq; 133 uint16_t wt_chan_flags; 134 } __packed; 135 136 #define URTWN_TX_RADIOTAP_PRESENT \ 137 (1 << IEEE80211_RADIOTAP_FLAGS | \ 138 1 << IEEE80211_RADIOTAP_CHANNEL) 139 140 struct urtwn_softc; 141 142 struct urtwn_rx_data { 143 struct urtwn_softc *sc; 144 struct usbd_xfer *xfer; 145 uint8_t *buf; 146 }; 147 148 struct urtwn_tx_data { 149 struct urtwn_softc *sc; 150 struct usbd_pipe *pipe; 151 struct usbd_xfer *xfer; 152 uint8_t *buf; 153 TAILQ_ENTRY(urtwn_tx_data) next; 154 }; 155 156 struct urtwn_host_cmd { 157 void (*cb)(struct urtwn_softc *, void *); 158 uint8_t data[256]; 159 }; 160 161 struct urtwn_cmd_newstate { 162 enum ieee80211_state state; 163 int arg; 164 }; 165 166 struct urtwn_cmd_key { 167 struct ieee80211_key key; 168 struct ieee80211_node *ni; 169 }; 170 171 struct urtwn_host_cmd_ring { 172 struct urtwn_host_cmd cmd[URTWN_HOST_CMD_RING_COUNT]; 173 int cur; 174 int next; 175 int queued; 176 }; 177 178 struct urtwn_softc { 179 struct device sc_dev; 180 struct rtwn_softc sc_sc; 181 182 struct usbd_device *sc_udev; 183 struct usbd_interface *sc_iface; 184 struct usb_task sc_task; 185 186 struct timeout scan_to; 187 struct timeout calib_to; 188 189 int ntx; 190 struct usbd_pipe *rx_pipe; 191 struct usbd_pipe *tx_pipe[R92C_MAX_EPOUT]; 192 int ac2idx[EDCA_NUM_AC]; 193 194 struct urtwn_host_cmd_ring cmdq; 195 struct urtwn_rx_data rx_data[URTWN_RX_LIST_COUNT]; 196 struct urtwn_tx_data tx_data[URTWN_TX_LIST_COUNT]; 197 TAILQ_HEAD(, urtwn_tx_data) tx_free_list; 198 199 struct ieee80211_amrr amrr; 200 struct ieee80211_amrr_node amn; 201 202 #if NBPFILTER > 0 203 caddr_t sc_drvbpf; 204 205 union { 206 struct urtwn_rx_radiotap_header th; 207 uint8_t pad[64]; 208 } sc_rxtapu; 209 #define sc_rxtap sc_rxtapu.th 210 int sc_rxtap_len; 211 212 union { 213 struct urtwn_tx_radiotap_header th; 214 uint8_t pad[64]; 215 } sc_txtapu; 216 #define sc_txtap sc_txtapu.th 217 int sc_txtap_len; 218 #endif 219 }; 220 221 #ifdef URTWN_DEBUG 222 #define DPRINTF(x) do { if (urtwn_debug) printf x; } while (0) 223 #define DPRINTFN(n, x) do { if (urtwn_debug >= (n)) printf x; } while (0) 224 int urtwn_debug = 4; 225 #else 226 #define DPRINTF(x) 227 #define DPRINTFN(n, x) 228 #endif 229 230 /* 231 * Various supported device vendors/products. 232 */ 233 #define URTWN_DEV(v, p, f) \ 234 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, (f) | RTWN_CHIP_USB } 235 #define URTWN_DEV_8192CU(v, p) URTWN_DEV(v, p, RTWN_CHIP_92C | RTWN_CHIP_88C) 236 #define URTWN_DEV_8188EU(v, p) URTWN_DEV(v, p, RTWN_CHIP_88E) 237 #define URTWN_DEV_8192EU(v, p) URTWN_DEV(v, p, RTWN_CHIP_92E) 238 static const struct urtwn_type { 239 struct usb_devno dev; 240 uint32_t chip; 241 } urtwn_devs[] = { 242 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_1), 243 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_1), 244 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_2), 245 URTWN_DEV_8192CU(ABOCOM, RTL8192CU), 246 URTWN_DEV_8192CU(ASUS, RTL8192CU), 247 URTWN_DEV_8192CU(ASUS, RTL8192CU_2), 248 URTWN_DEV_8192CU(ASUS, RTL8192CU_3), 249 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CE_1), 250 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CE_2), 251 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CU), 252 URTWN_DEV_8192CU(BELKIN, F7D2102), 253 URTWN_DEV_8192CU(BELKIN, F9L1004V1), 254 URTWN_DEV_8192CU(BELKIN, RTL8188CU), 255 URTWN_DEV_8192CU(BELKIN, RTL8188CUS), 256 URTWN_DEV_8192CU(BELKIN, RTL8192CU), 257 URTWN_DEV_8192CU(BELKIN, RTL8192CU_1), 258 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_1), 259 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_2), 260 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_3), 261 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_4), 262 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_5), 263 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_6), 264 URTWN_DEV_8192CU(COMPARE, RTL8192CU), 265 URTWN_DEV_8192CU(COREGA, RTL8192CU), 266 URTWN_DEV_8192CU(DLINK, DWA131B), 267 URTWN_DEV_8192CU(DLINK, RTL8188CU), 268 URTWN_DEV_8192CU(DLINK, RTL8192CU_1), 269 URTWN_DEV_8192CU(DLINK, RTL8192CU_2), 270 URTWN_DEV_8192CU(DLINK, RTL8192CU_3), 271 URTWN_DEV_8192CU(DLINK, RTL8192CU_4), 272 URTWN_DEV_8192CU(EDIMAX, EW7811UN), 273 URTWN_DEV_8192CU(EDIMAX, RTL8192CU), 274 URTWN_DEV_8192CU(FEIXUN, RTL8188CU), 275 URTWN_DEV_8192CU(FEIXUN, RTL8192CU), 276 URTWN_DEV_8192CU(GUILLEMOT, HWNUP150), 277 URTWN_DEV_8192CU(GUILLEMOT, RTL8192CU), 278 URTWN_DEV_8192CU(HAWKING, RTL8192CU), 279 URTWN_DEV_8192CU(HAWKING, RTL8192CU_2), 280 URTWN_DEV_8192CU(HP3, RTL8188CU), 281 URTWN_DEV_8192CU(IODATA, WNG150UM), 282 URTWN_DEV_8192CU(IODATA, RTL8192CU), 283 URTWN_DEV_8192CU(NETGEAR, N300MA), 284 URTWN_DEV_8192CU(NETGEAR, WNA1000M), 285 URTWN_DEV_8192CU(NETGEAR, WNA1000MV2), 286 URTWN_DEV_8192CU(NETGEAR, RTL8192CU), 287 URTWN_DEV_8192CU(NETGEAR4, RTL8188CU), 288 URTWN_DEV_8192CU(NETWEEN, RTL8192CU), 289 URTWN_DEV_8192CU(NOVATECH, RTL8188CU), 290 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_1), 291 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_2), 292 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_3), 293 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_4), 294 URTWN_DEV_8192CU(PLANEX2, RTL8188CUS), 295 URTWN_DEV_8192CU(PLANEX2, RTL8192CU), 296 URTWN_DEV_8192CU(REALTEK, RTL8188CE_0), 297 URTWN_DEV_8192CU(REALTEK, RTL8188CE_1), 298 URTWN_DEV_8192CU(REALTEK, RTL8188CTV), 299 URTWN_DEV_8192CU(REALTEK, RTL8188CU_0), 300 URTWN_DEV_8192CU(REALTEK, RTL8188CU_1), 301 URTWN_DEV_8192CU(REALTEK, RTL8188CU_2), 302 URTWN_DEV_8192CU(REALTEK, RTL8188CU_3), 303 URTWN_DEV_8192CU(REALTEK, RTL8188CU_4), 304 URTWN_DEV_8192CU(REALTEK, RTL8188CU_5), 305 URTWN_DEV_8192CU(REALTEK, RTL8188CU_COMBO), 306 URTWN_DEV_8192CU(REALTEK, RTL8188CUS), 307 URTWN_DEV_8192CU(REALTEK, RTL8188RU), 308 URTWN_DEV_8192CU(REALTEK, RTL8188RU_2), 309 URTWN_DEV_8192CU(REALTEK, RTL8188RU_3), 310 URTWN_DEV_8192CU(REALTEK, RTL8191CU), 311 URTWN_DEV_8192CU(REALTEK, RTL8192CE), 312 URTWN_DEV_8192CU(REALTEK, RTL8192CE_VAU), 313 URTWN_DEV_8192CU(REALTEK, RTL8192CU), 314 URTWN_DEV_8192CU(SITECOMEU, RTL8188CU), 315 URTWN_DEV_8192CU(SITECOMEU, RTL8188CU_2), 316 URTWN_DEV_8192CU(SITECOMEU, RTL8192CU), 317 URTWN_DEV_8192CU(SITECOMEU, RTL8192CU_2), 318 URTWN_DEV_8192CU(SITECOMEU, WLA2100V2), 319 URTWN_DEV_8192CU(TPLINK, RTL8192CU), 320 URTWN_DEV_8192CU(TRENDNET, RTL8188CU), 321 URTWN_DEV_8192CU(TRENDNET, RTL8192CU), 322 URTWN_DEV_8192CU(ZYXEL, RTL8192CU), 323 /* URTWN_RTL8188E */ 324 URTWN_DEV_8188EU(ABOCOM, RTL8188EU), 325 URTWN_DEV_8188EU(DLINK, DWA121B1), 326 URTWN_DEV_8188EU(DLINK, DWA123D1), 327 URTWN_DEV_8188EU(DLINK, DWA125D1), 328 URTWN_DEV_8188EU(ELECOM, WDC150SU2M), 329 URTWN_DEV_8188EU(REALTEK, RTL8188ETV), 330 URTWN_DEV_8188EU(REALTEK, RTL8188EU), 331 URTWN_DEV_8188EU(TPLINK, RTL8188EUS), 332 /* URTWN_RTL8192EU */ 333 URTWN_DEV_8192EU(DLINK, DWA131E1), 334 URTWN_DEV_8192EU(REALTEK, RTL8192EU), 335 URTWN_DEV_8192EU(TPLINK, RTL8192EU), 336 URTWN_DEV_8192EU(TPLINK, RTL8192EU_2), 337 URTWN_DEV_8192EU(TPLINK, RTL8192EU_3) 338 }; 339 340 #define urtwn_lookup(v, p) \ 341 ((const struct urtwn_type *)usb_lookup(urtwn_devs, v, p)) 342 343 int urtwn_match(struct device *, void *, void *); 344 void urtwn_attach(struct device *, struct device *, void *); 345 int urtwn_detach(struct device *, int); 346 int urtwn_open_pipes(struct urtwn_softc *); 347 void urtwn_close_pipes(struct urtwn_softc *); 348 int urtwn_alloc_rx_list(struct urtwn_softc *); 349 void urtwn_free_rx_list(struct urtwn_softc *); 350 int urtwn_alloc_tx_list(struct urtwn_softc *); 351 void urtwn_free_tx_list(struct urtwn_softc *); 352 void urtwn_task(void *); 353 void urtwn_do_async(struct urtwn_softc *, 354 void (*)(struct urtwn_softc *, void *), void *, int); 355 void urtwn_wait_async(void *); 356 int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 357 int); 358 void urtwn_write_1(void *, uint16_t, uint8_t); 359 void urtwn_write_2(void *, uint16_t, uint16_t); 360 void urtwn_write_4(void *, uint16_t, uint32_t); 361 int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 362 int); 363 uint8_t urtwn_read_1(void *, uint16_t); 364 uint16_t urtwn_read_2(void *, uint16_t); 365 uint32_t urtwn_read_4(void *, uint16_t); 366 int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 367 void urtwn_calib_to(void *); 368 void urtwn_calib_cb(struct urtwn_softc *, void *); 369 void urtwn_scan_to(void *); 370 void urtwn_next_scan(void *); 371 void urtwn_cancel_scan(void *); 372 int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 373 int); 374 void urtwn_newstate_cb(struct urtwn_softc *, void *); 375 void urtwn_updateslot(struct ieee80211com *); 376 void urtwn_updateslot_cb(struct urtwn_softc *, void *); 377 void urtwn_updateedca(struct ieee80211com *); 378 void urtwn_updateedca_cb(struct urtwn_softc *, void *); 379 int urtwn_set_key(struct ieee80211com *, struct ieee80211_node *, 380 struct ieee80211_key *); 381 void urtwn_set_key_cb(struct urtwn_softc *, void *); 382 void urtwn_delete_key(struct ieee80211com *, 383 struct ieee80211_node *, struct ieee80211_key *); 384 void urtwn_delete_key_cb(struct urtwn_softc *, void *); 385 void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 386 struct mbuf_list *); 387 void urtwn_rxeof(struct usbd_xfer *, void *, 388 usbd_status); 389 void urtwn_txeof(struct usbd_xfer *, void *, 390 usbd_status); 391 int urtwn_tx(void *, struct mbuf *, struct ieee80211_node *); 392 int urtwn_ioctl(struct ifnet *, u_long, caddr_t); 393 int urtwn_power_on(void *); 394 int urtwn_alloc_buffers(void *); 395 int urtwn_r92c_power_on(struct urtwn_softc *); 396 int urtwn_r92e_power_on(struct urtwn_softc *); 397 int urtwn_r88e_power_on(struct urtwn_softc *); 398 int urtwn_llt_init(struct urtwn_softc *, int); 399 int urtwn_fw_loadpage(void *, int, uint8_t *, int); 400 int urtwn_load_firmware(void *, u_char **, size_t *); 401 int urtwn_dma_init(void *); 402 void urtwn_aggr_init(void *); 403 void urtwn_mac_init(void *); 404 void urtwn_bb_init(void *); 405 void urtwn_burstlen_init(struct urtwn_softc *); 406 int urtwn_init(void *); 407 void urtwn_stop(void *); 408 int urtwn_is_oactive(void *); 409 void urtwn_next_calib(void *); 410 void urtwn_cancel_calib(void *); 411 412 /* Aliases. */ 413 #define urtwn_bb_write urtwn_write_4 414 #define urtwn_bb_read urtwn_read_4 415 416 struct cfdriver urtwn_cd = { 417 NULL, "urtwn", DV_IFNET 418 }; 419 420 const struct cfattach urtwn_ca = { 421 sizeof(struct urtwn_softc), urtwn_match, urtwn_attach, urtwn_detach 422 }; 423 424 int 425 urtwn_match(struct device *parent, void *match, void *aux) 426 { 427 struct usb_attach_arg *uaa = aux; 428 429 if (uaa->iface == NULL || uaa->configno != 1) 430 return (UMATCH_NONE); 431 432 return ((urtwn_lookup(uaa->vendor, uaa->product) != NULL) ? 433 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 434 } 435 436 void 437 urtwn_attach(struct device *parent, struct device *self, void *aux) 438 { 439 struct urtwn_softc *sc = (struct urtwn_softc *)self; 440 struct usb_attach_arg *uaa = aux; 441 struct ifnet *ifp; 442 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 443 444 sc->sc_udev = uaa->device; 445 sc->sc_iface = uaa->iface; 446 447 sc->sc_sc.chip = urtwn_lookup(uaa->vendor, uaa->product)->chip; 448 449 usb_init_task(&sc->sc_task, urtwn_task, sc, USB_TASK_TYPE_GENERIC); 450 timeout_set(&sc->scan_to, urtwn_scan_to, sc); 451 timeout_set(&sc->calib_to, urtwn_calib_to, sc); 452 if (urtwn_open_pipes(sc) != 0) 453 return; 454 455 sc->amrr.amrr_min_success_threshold = 1; 456 sc->amrr.amrr_max_success_threshold = 10; 457 458 /* Attach the bus-agnostic driver. */ 459 sc->sc_sc.sc_ops.cookie = sc; 460 sc->sc_sc.sc_ops.write_1 = urtwn_write_1; 461 sc->sc_sc.sc_ops.write_2 = urtwn_write_2; 462 sc->sc_sc.sc_ops.write_4 = urtwn_write_4; 463 sc->sc_sc.sc_ops.read_1 = urtwn_read_1; 464 sc->sc_sc.sc_ops.read_2 = urtwn_read_2; 465 sc->sc_sc.sc_ops.read_4 = urtwn_read_4; 466 sc->sc_sc.sc_ops.tx = urtwn_tx; 467 sc->sc_sc.sc_ops.power_on = urtwn_power_on; 468 sc->sc_sc.sc_ops.dma_init = urtwn_dma_init; 469 sc->sc_sc.sc_ops.fw_loadpage = urtwn_fw_loadpage; 470 sc->sc_sc.sc_ops.load_firmware = urtwn_load_firmware; 471 sc->sc_sc.sc_ops.aggr_init = urtwn_aggr_init; 472 sc->sc_sc.sc_ops.mac_init = urtwn_mac_init; 473 sc->sc_sc.sc_ops.bb_init = urtwn_bb_init; 474 sc->sc_sc.sc_ops.alloc_buffers = urtwn_alloc_buffers; 475 sc->sc_sc.sc_ops.init = urtwn_init; 476 sc->sc_sc.sc_ops.stop = urtwn_stop; 477 sc->sc_sc.sc_ops.is_oactive = urtwn_is_oactive; 478 sc->sc_sc.sc_ops.next_calib = urtwn_next_calib; 479 sc->sc_sc.sc_ops.cancel_calib = urtwn_cancel_calib; 480 sc->sc_sc.sc_ops.next_scan = urtwn_next_scan; 481 sc->sc_sc.sc_ops.cancel_scan = urtwn_cancel_scan; 482 sc->sc_sc.sc_ops.wait_async = urtwn_wait_async; 483 if (rtwn_attach(&sc->sc_dev, &sc->sc_sc) != 0) { 484 urtwn_close_pipes(sc); 485 return; 486 } 487 488 /* ifp is now valid */ 489 ifp = &sc->sc_sc.sc_ic.ic_if; 490 ifp->if_ioctl = urtwn_ioctl; 491 492 ic->ic_updateslot = urtwn_updateslot; 493 ic->ic_updateedca = urtwn_updateedca; 494 ic->ic_set_key = urtwn_set_key; 495 ic->ic_delete_key = urtwn_delete_key; 496 /* Override state transition machine. */ 497 ic->ic_newstate = urtwn_newstate; 498 499 #if NBPFILTER > 0 500 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 501 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 502 503 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 504 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 505 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 506 507 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 508 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 509 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 510 #endif 511 } 512 513 int 514 urtwn_detach(struct device *self, int flags) 515 { 516 struct urtwn_softc *sc = (struct urtwn_softc *)self; 517 int s; 518 519 s = splusb(); 520 521 if (timeout_initialized(&sc->scan_to)) 522 timeout_del(&sc->scan_to); 523 if (timeout_initialized(&sc->calib_to)) 524 timeout_del(&sc->calib_to); 525 526 /* Wait for all async commands to complete. */ 527 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 528 529 usbd_ref_wait(sc->sc_udev); 530 531 rtwn_detach(&sc->sc_sc, flags); 532 533 /* Abort and close Tx/Rx pipes. */ 534 urtwn_close_pipes(sc); 535 536 /* Free Tx/Rx buffers. */ 537 urtwn_free_tx_list(sc); 538 urtwn_free_rx_list(sc); 539 splx(s); 540 541 return (0); 542 } 543 544 int 545 urtwn_open_pipes(struct urtwn_softc *sc) 546 { 547 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 548 uint8_t epaddr[R92C_MAX_EPOUT] = { 0, 0, 0 }; 549 uint8_t rx_no; 550 usb_interface_descriptor_t *id; 551 usb_endpoint_descriptor_t *ed; 552 int i, error, nrx = 0; 553 554 /* Find all bulk endpoints. */ 555 id = usbd_get_interface_descriptor(sc->sc_iface); 556 for (i = 0; i < id->bNumEndpoints; i++) { 557 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 558 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) 559 continue; 560 561 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 562 rx_no = ed->bEndpointAddress; 563 nrx++; 564 } else { 565 if (sc->ntx < R92C_MAX_EPOUT) 566 epaddr[sc->ntx] = ed->bEndpointAddress; 567 sc->ntx++; 568 } 569 } 570 if (nrx == 0) { 571 printf("%s: %d: invalid number of Rx bulk pipes\n", 572 sc->sc_dev.dv_xname, nrx); 573 return (EIO); 574 } 575 DPRINTF(("found %d bulk-out pipes\n", sc->ntx)); 576 if (sc->ntx == 0 || sc->ntx > R92C_MAX_EPOUT) { 577 printf("%s: %d: invalid number of Tx bulk pipes\n", 578 sc->sc_dev.dv_xname, sc->ntx); 579 return (EIO); 580 } 581 582 /* Open bulk-in pipe. */ 583 error = usbd_open_pipe(sc->sc_iface, rx_no, 0, &sc->rx_pipe); 584 if (error != 0) { 585 printf("%s: could not open Rx bulk pipe\n", 586 sc->sc_dev.dv_xname); 587 goto fail; 588 } 589 590 /* Open bulk-out pipes (up to 3). */ 591 for (i = 0; i < sc->ntx; i++) { 592 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 0, 593 &sc->tx_pipe[i]); 594 if (error != 0) { 595 printf("%s: could not open Tx bulk pipe 0x%02x\n", 596 sc->sc_dev.dv_xname, epaddr[i]); 597 goto fail; 598 } 599 } 600 601 /* Map 802.11 access categories to USB pipes. */ 602 sc->ac2idx[EDCA_AC_BK] = 603 sc->ac2idx[EDCA_AC_BE] = (sc->ntx == 3) ? 2 : ((sc->ntx == 2) ? 1 : 0); 604 sc->ac2idx[EDCA_AC_VI] = (sc->ntx == 3) ? 1 : 0; 605 sc->ac2idx[EDCA_AC_VO] = 0; /* Always use highest prio. */ 606 607 if (error != 0) 608 fail: urtwn_close_pipes(sc); 609 return (error); 610 } 611 612 void 613 urtwn_close_pipes(struct urtwn_softc *sc) 614 { 615 int i; 616 617 /* Close Rx pipe. */ 618 if (sc->rx_pipe != NULL) { 619 usbd_abort_pipe(sc->rx_pipe); 620 usbd_close_pipe(sc->rx_pipe); 621 } 622 /* Close Tx pipes. */ 623 for (i = 0; i < R92C_MAX_EPOUT; i++) { 624 if (sc->tx_pipe[i] == NULL) 625 continue; 626 usbd_abort_pipe(sc->tx_pipe[i]); 627 usbd_close_pipe(sc->tx_pipe[i]); 628 } 629 } 630 631 int 632 urtwn_alloc_rx_list(struct urtwn_softc *sc) 633 { 634 struct urtwn_rx_data *data; 635 int i, error = 0; 636 637 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 638 data = &sc->rx_data[i]; 639 640 data->sc = sc; /* Backpointer for callbacks. */ 641 642 data->xfer = usbd_alloc_xfer(sc->sc_udev); 643 if (data->xfer == NULL) { 644 printf("%s: could not allocate xfer\n", 645 sc->sc_dev.dv_xname); 646 error = ENOMEM; 647 break; 648 } 649 data->buf = usbd_alloc_buffer(data->xfer, URTWN_RXBUFSZ); 650 if (data->buf == NULL) { 651 printf("%s: could not allocate xfer buffer\n", 652 sc->sc_dev.dv_xname); 653 error = ENOMEM; 654 break; 655 } 656 } 657 if (error != 0) 658 urtwn_free_rx_list(sc); 659 return (error); 660 } 661 662 void 663 urtwn_free_rx_list(struct urtwn_softc *sc) 664 { 665 int i; 666 667 /* NB: Caller must abort pipe first. */ 668 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 669 if (sc->rx_data[i].xfer != NULL) 670 usbd_free_xfer(sc->rx_data[i].xfer); 671 sc->rx_data[i].xfer = NULL; 672 } 673 } 674 675 int 676 urtwn_alloc_tx_list(struct urtwn_softc *sc) 677 { 678 struct urtwn_tx_data *data; 679 int i, error = 0; 680 681 TAILQ_INIT(&sc->tx_free_list); 682 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 683 data = &sc->tx_data[i]; 684 685 data->sc = sc; /* Backpointer for callbacks. */ 686 687 data->xfer = usbd_alloc_xfer(sc->sc_udev); 688 if (data->xfer == NULL) { 689 printf("%s: could not allocate xfer\n", 690 sc->sc_dev.dv_xname); 691 error = ENOMEM; 692 break; 693 } 694 data->buf = usbd_alloc_buffer(data->xfer, URTWN_TXBUFSZ); 695 if (data->buf == NULL) { 696 printf("%s: could not allocate xfer buffer\n", 697 sc->sc_dev.dv_xname); 698 error = ENOMEM; 699 break; 700 } 701 /* Append this Tx buffer to our free list. */ 702 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 703 } 704 if (error != 0) 705 urtwn_free_tx_list(sc); 706 return (error); 707 } 708 709 void 710 urtwn_free_tx_list(struct urtwn_softc *sc) 711 { 712 int i; 713 714 /* NB: Caller must abort pipe first. */ 715 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 716 if (sc->tx_data[i].xfer != NULL) 717 usbd_free_xfer(sc->tx_data[i].xfer); 718 sc->tx_data[i].xfer = NULL; 719 } 720 } 721 722 void 723 urtwn_task(void *arg) 724 { 725 struct urtwn_softc *sc = arg; 726 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 727 struct urtwn_host_cmd *cmd; 728 int s; 729 730 /* Process host commands. */ 731 s = splusb(); 732 while (ring->next != ring->cur) { 733 cmd = &ring->cmd[ring->next]; 734 splx(s); 735 /* Invoke callback. */ 736 cmd->cb(sc, cmd->data); 737 s = splusb(); 738 ring->queued--; 739 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 740 } 741 splx(s); 742 } 743 744 void 745 urtwn_do_async(struct urtwn_softc *sc, 746 void (*cb)(struct urtwn_softc *, void *), void *arg, int len) 747 { 748 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 749 struct urtwn_host_cmd *cmd; 750 int s; 751 752 s = splusb(); 753 cmd = &ring->cmd[ring->cur]; 754 cmd->cb = cb; 755 KASSERT(len <= sizeof(cmd->data)); 756 memcpy(cmd->data, arg, len); 757 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 758 759 /* If there is no pending command already, schedule a task. */ 760 if (++ring->queued == 1) 761 usb_add_task(sc->sc_udev, &sc->sc_task); 762 splx(s); 763 } 764 765 void 766 urtwn_wait_async(void *cookie) 767 { 768 struct urtwn_softc *sc = cookie; 769 int s; 770 771 s = splusb(); 772 /* Wait for all queued asynchronous commands to complete. */ 773 usb_wait_task(sc->sc_udev, &sc->sc_task); 774 splx(s); 775 } 776 777 int 778 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 779 int len) 780 { 781 usb_device_request_t req; 782 783 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 784 req.bRequest = R92C_REQ_REGS; 785 USETW(req.wValue, addr); 786 USETW(req.wIndex, 0); 787 USETW(req.wLength, len); 788 return (usbd_do_request(sc->sc_udev, &req, buf)); 789 } 790 791 void 792 urtwn_write_1(void *cookie, uint16_t addr, uint8_t val) 793 { 794 struct urtwn_softc *sc = cookie; 795 796 urtwn_write_region_1(sc, addr, &val, 1); 797 } 798 799 void 800 urtwn_write_2(void *cookie, uint16_t addr, uint16_t val) 801 { 802 struct urtwn_softc *sc = cookie; 803 804 val = htole16(val); 805 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 806 } 807 808 void 809 urtwn_write_4(void *cookie, uint16_t addr, uint32_t val) 810 { 811 struct urtwn_softc *sc = cookie; 812 813 val = htole32(val); 814 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 815 } 816 817 int 818 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 819 int len) 820 { 821 usb_device_request_t req; 822 823 req.bmRequestType = UT_READ_VENDOR_DEVICE; 824 req.bRequest = R92C_REQ_REGS; 825 USETW(req.wValue, addr); 826 USETW(req.wIndex, 0); 827 USETW(req.wLength, len); 828 return (usbd_do_request(sc->sc_udev, &req, buf)); 829 } 830 831 uint8_t 832 urtwn_read_1(void *cookie, uint16_t addr) 833 { 834 struct urtwn_softc *sc = cookie; 835 uint8_t val; 836 837 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 838 return (0xff); 839 return (val); 840 } 841 842 uint16_t 843 urtwn_read_2(void *cookie, uint16_t addr) 844 { 845 struct urtwn_softc *sc = cookie; 846 uint16_t val; 847 848 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 849 return (0xffff); 850 return (letoh16(val)); 851 } 852 853 uint32_t 854 urtwn_read_4(void *cookie, uint16_t addr) 855 { 856 struct urtwn_softc *sc = cookie; 857 uint32_t val; 858 859 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 860 return (0xffffffff); 861 return (letoh32(val)); 862 } 863 864 int 865 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 866 { 867 int ntries; 868 869 urtwn_write_4(sc, R92C_LLT_INIT, 870 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 871 SM(R92C_LLT_INIT_ADDR, addr) | 872 SM(R92C_LLT_INIT_DATA, data)); 873 /* Wait for write operation to complete. */ 874 for (ntries = 0; ntries < 20; ntries++) { 875 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 876 R92C_LLT_INIT_OP_NO_ACTIVE) 877 return (0); 878 DELAY(5); 879 } 880 return (ETIMEDOUT); 881 } 882 883 void 884 urtwn_calib_to(void *arg) 885 { 886 struct urtwn_softc *sc = arg; 887 888 if (usbd_is_dying(sc->sc_udev)) 889 return; 890 891 usbd_ref_incr(sc->sc_udev); 892 893 /* Do it in a process context. */ 894 urtwn_do_async(sc, urtwn_calib_cb, NULL, 0); 895 896 usbd_ref_decr(sc->sc_udev); 897 } 898 899 /* ARGSUSED */ 900 void 901 urtwn_calib_cb(struct urtwn_softc *sc, void *arg) 902 { 903 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 904 int s; 905 906 s = splnet(); 907 if (ic->ic_opmode == IEEE80211_M_STA) { 908 ieee80211_amrr_choose(&sc->amrr, ic->ic_bss, &sc->amn); 909 } 910 splx(s); 911 912 rtwn_calib(&sc->sc_sc); 913 } 914 915 void 916 urtwn_next_calib(void *cookie) 917 { 918 struct urtwn_softc *sc = cookie; 919 920 if (!usbd_is_dying(sc->sc_udev)) 921 timeout_add_sec(&sc->calib_to, 2); 922 } 923 924 void 925 urtwn_cancel_calib(void *cookie) 926 { 927 struct urtwn_softc *sc = cookie; 928 929 if (timeout_initialized(&sc->calib_to)) 930 timeout_del(&sc->calib_to); 931 } 932 933 void 934 urtwn_scan_to(void *arg) 935 { 936 struct urtwn_softc *sc = arg; 937 938 if (usbd_is_dying(sc->sc_udev)) 939 return; 940 941 usbd_ref_incr(sc->sc_udev); 942 rtwn_next_scan(&sc->sc_sc); 943 usbd_ref_decr(sc->sc_udev); 944 } 945 946 void 947 urtwn_next_scan(void *arg) 948 { 949 struct urtwn_softc *sc = arg; 950 951 if (!usbd_is_dying(sc->sc_udev)) 952 timeout_add_msec(&sc->scan_to, 200); 953 } 954 955 void 956 urtwn_cancel_scan(void *cookie) 957 { 958 struct urtwn_softc *sc = cookie; 959 960 if (timeout_initialized(&sc->scan_to)) 961 timeout_del(&sc->scan_to); 962 } 963 964 int 965 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 966 { 967 struct rtwn_softc *sc_sc = ic->ic_softc; 968 struct device *self = sc_sc->sc_pdev; 969 struct urtwn_softc *sc = (struct urtwn_softc *)self; 970 struct urtwn_cmd_newstate cmd; 971 972 /* Do it in a process context. */ 973 cmd.state = nstate; 974 cmd.arg = arg; 975 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 976 return (0); 977 } 978 979 void 980 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 981 { 982 struct urtwn_cmd_newstate *cmd = arg; 983 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 984 985 rtwn_newstate(ic, cmd->state, cmd->arg); 986 } 987 988 void 989 urtwn_updateslot(struct ieee80211com *ic) 990 { 991 struct rtwn_softc *sc_sc = ic->ic_softc; 992 struct device *self = sc_sc->sc_pdev; 993 struct urtwn_softc *sc = (struct urtwn_softc *)self; 994 995 /* Do it in a process context. */ 996 urtwn_do_async(sc, urtwn_updateslot_cb, NULL, 0); 997 } 998 999 /* ARGSUSED */ 1000 void 1001 urtwn_updateslot_cb(struct urtwn_softc *sc, void *arg) 1002 { 1003 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1004 1005 rtwn_updateslot(ic); 1006 } 1007 1008 void 1009 urtwn_updateedca(struct ieee80211com *ic) 1010 { 1011 struct rtwn_softc *sc_sc = ic->ic_softc; 1012 struct device *self = sc_sc->sc_pdev; 1013 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1014 1015 /* Do it in a process context. */ 1016 urtwn_do_async(sc, urtwn_updateedca_cb, NULL, 0); 1017 } 1018 1019 /* ARGSUSED */ 1020 void 1021 urtwn_updateedca_cb(struct urtwn_softc *sc, void *arg) 1022 { 1023 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1024 1025 rtwn_updateedca(ic); 1026 } 1027 1028 int 1029 urtwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1030 struct ieee80211_key *k) 1031 { 1032 struct rtwn_softc *sc_sc = ic->ic_softc; 1033 struct device *self = sc_sc->sc_pdev; 1034 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1035 struct urtwn_cmd_key cmd; 1036 1037 /* Only handle keys for CCMP */ 1038 if (k->k_cipher != IEEE80211_CIPHER_CCMP) 1039 return ieee80211_set_key(ic, ni, k); 1040 1041 /* Defer setting of WEP keys until interface is brought up. */ 1042 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 1043 (IFF_UP | IFF_RUNNING)) 1044 return (0); 1045 1046 /* Do it in a process context. */ 1047 cmd.key = *k; 1048 cmd.ni = ni; 1049 urtwn_do_async(sc, urtwn_set_key_cb, &cmd, sizeof(cmd)); 1050 return (0); 1051 } 1052 1053 void 1054 urtwn_set_key_cb(struct urtwn_softc *sc, void *arg) 1055 { 1056 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1057 struct urtwn_cmd_key *cmd = arg; 1058 1059 rtwn_set_key(ic, cmd->ni, &cmd->key); 1060 } 1061 1062 void 1063 urtwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1064 struct ieee80211_key *k) 1065 { 1066 struct rtwn_softc *sc_sc = ic->ic_softc; 1067 struct device *self = sc_sc->sc_pdev; 1068 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1069 struct urtwn_cmd_key cmd; 1070 1071 /* Only handle keys for CCMP */ 1072 if (k->k_cipher != IEEE80211_CIPHER_CCMP) { 1073 ieee80211_delete_key(ic, ni, k); 1074 return; 1075 } 1076 1077 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 1078 ic->ic_state != IEEE80211_S_RUN) 1079 return; /* Nothing to do. */ 1080 1081 /* Do it in a process context. */ 1082 cmd.key = *k; 1083 cmd.ni = ni; 1084 urtwn_do_async(sc, urtwn_delete_key_cb, &cmd, sizeof(cmd)); 1085 } 1086 1087 void 1088 urtwn_delete_key_cb(struct urtwn_softc *sc, void *arg) 1089 { 1090 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1091 struct urtwn_cmd_key *cmd = arg; 1092 1093 rtwn_delete_key(ic, cmd->ni, &cmd->key); 1094 } 1095 1096 int 1097 urtwn_ccmp_decap(struct urtwn_softc *sc, struct mbuf *m, 1098 struct ieee80211_node *ni) 1099 { 1100 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1101 struct ieee80211_key *k; 1102 struct ieee80211_frame *wh; 1103 uint64_t pn, *prsc; 1104 uint8_t *ivp; 1105 uint8_t tid; 1106 int hdrlen, hasqos; 1107 1108 k = ieee80211_get_rxkey(ic, m, ni); 1109 if (k == NULL) 1110 return 1; 1111 1112 wh = mtod(m, struct ieee80211_frame *); 1113 hdrlen = ieee80211_get_hdrlen(wh); 1114 ivp = (uint8_t *)wh + hdrlen; 1115 1116 /* Check that ExtIV bit is set. */ 1117 if (!(ivp[3] & IEEE80211_WEP_EXTIV)) 1118 return 1; 1119 1120 hasqos = ieee80211_has_qos(wh); 1121 tid = hasqos ? ieee80211_get_qos(wh) & IEEE80211_QOS_TID : 0; 1122 prsc = &k->k_rsc[tid]; 1123 1124 /* Extract the 48-bit PN from the CCMP header. */ 1125 pn = (uint64_t)ivp[0] | 1126 (uint64_t)ivp[1] << 8 | 1127 (uint64_t)ivp[4] << 16 | 1128 (uint64_t)ivp[5] << 24 | 1129 (uint64_t)ivp[6] << 32 | 1130 (uint64_t)ivp[7] << 40; 1131 if (pn <= *prsc) { 1132 ic->ic_stats.is_ccmp_replays++; 1133 return 1; 1134 } 1135 /* Last seen packet number is updated in ieee80211_inputm(). */ 1136 1137 /* Strip MIC. IV will be stripped by ieee80211_inputm(). */ 1138 m_adj(m, -IEEE80211_CCMP_MICLEN); 1139 return 0; 1140 } 1141 1142 void 1143 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, 1144 struct mbuf_list *ml) 1145 { 1146 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1147 struct ifnet *ifp = &ic->ic_if; 1148 struct ieee80211_rxinfo rxi; 1149 struct ieee80211_frame *wh; 1150 struct ieee80211_node *ni; 1151 struct r92c_rx_desc_usb *rxd; 1152 uint32_t rxdw0, rxdw3; 1153 struct mbuf *m; 1154 uint8_t rate; 1155 int8_t rssi = 0; 1156 int s, infosz; 1157 1158 rxd = (struct r92c_rx_desc_usb *)buf; 1159 rxdw0 = letoh32(rxd->rxdw0); 1160 rxdw3 = letoh32(rxd->rxdw3); 1161 1162 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1163 /* 1164 * This should not happen since we setup our Rx filter 1165 * to not receive these frames. 1166 */ 1167 ifp->if_ierrors++; 1168 return; 1169 } 1170 if (__predict_false(pktlen < sizeof(*wh) || pktlen > MCLBYTES)) { 1171 ifp->if_ierrors++; 1172 return; 1173 } 1174 1175 rate = MS(rxdw3, R92C_RXDW3_RATE); 1176 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1177 1178 /* Get RSSI from PHY status descriptor if present. */ 1179 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1180 rssi = rtwn_get_rssi(&sc->sc_sc, rate, &rxd[1]); 1181 /* Update our average RSSI. */ 1182 rtwn_update_avgrssi(&sc->sc_sc, rate, rssi); 1183 } 1184 1185 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 1186 pktlen, rate, infosz, rssi)); 1187 1188 MGETHDR(m, M_DONTWAIT, MT_DATA); 1189 if (__predict_false(m == NULL)) { 1190 ifp->if_ierrors++; 1191 return; 1192 } 1193 if (pktlen > MHLEN) { 1194 MCLGET(m, M_DONTWAIT); 1195 if (__predict_false(!(m->m_flags & M_EXT))) { 1196 ifp->if_ierrors++; 1197 m_freem(m); 1198 return; 1199 } 1200 } 1201 /* Finalize mbuf. */ 1202 wh = (struct ieee80211_frame *)((uint8_t *)&rxd[1] + infosz); 1203 memcpy(mtod(m, uint8_t *), wh, pktlen); 1204 m->m_pkthdr.len = m->m_len = pktlen; 1205 1206 s = splnet(); 1207 #if NBPFILTER > 0 1208 if (__predict_false(sc->sc_drvbpf != NULL)) { 1209 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1210 struct mbuf mb; 1211 1212 tap->wr_flags = 0; 1213 /* Map HW rate index to 802.11 rate. */ 1214 if (!(rxdw3 & R92C_RXDW3_HT)) { 1215 switch (rate) { 1216 /* CCK. */ 1217 case 0: tap->wr_rate = 2; break; 1218 case 1: tap->wr_rate = 4; break; 1219 case 2: tap->wr_rate = 11; break; 1220 case 3: tap->wr_rate = 22; break; 1221 /* OFDM. */ 1222 case 4: tap->wr_rate = 12; break; 1223 case 5: tap->wr_rate = 18; break; 1224 case 6: tap->wr_rate = 24; break; 1225 case 7: tap->wr_rate = 36; break; 1226 case 8: tap->wr_rate = 48; break; 1227 case 9: tap->wr_rate = 72; break; 1228 case 10: tap->wr_rate = 96; break; 1229 case 11: tap->wr_rate = 108; break; 1230 } 1231 if (rate <= 3) 1232 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1233 } else if (rate >= 12) { /* MCS0~15. */ 1234 /* Bit 7 set means HT MCS instead of rate. */ 1235 tap->wr_rate = 0x80 | (rate - 12); 1236 } 1237 tap->wr_dbm_antsignal = rssi; 1238 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1239 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1240 1241 mb.m_data = (caddr_t)tap; 1242 mb.m_len = sc->sc_rxtap_len; 1243 mb.m_next = m; 1244 mb.m_nextpkt = NULL; 1245 mb.m_type = 0; 1246 mb.m_flags = 0; 1247 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1248 } 1249 #endif 1250 1251 ni = ieee80211_find_rxnode(ic, wh); 1252 rxi.rxi_flags = 0; 1253 rxi.rxi_rssi = rssi; 1254 rxi.rxi_tstamp = 0; /* Unused. */ 1255 1256 /* Handle hardware decryption. */ 1257 if (((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) 1258 && (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && 1259 (ni->ni_flags & IEEE80211_NODE_RXPROT) && 1260 ni->ni_pairwise_key.k_cipher == IEEE80211_CIPHER_CCMP) { 1261 if (urtwn_ccmp_decap(sc, m, ni) != 0) { 1262 ifp->if_ierrors++; 1263 m_freem(m); 1264 ieee80211_release_node(ic, ni); 1265 return; 1266 } 1267 rxi.rxi_flags |= IEEE80211_RXI_HWDEC; 1268 } 1269 1270 ieee80211_inputm(ifp, m, ni, &rxi, ml); 1271 /* Node is no longer needed. */ 1272 ieee80211_release_node(ic, ni); 1273 splx(s); 1274 } 1275 1276 void 1277 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, 1278 usbd_status status) 1279 { 1280 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1281 struct urtwn_rx_data *data = priv; 1282 struct urtwn_softc *sc = data->sc; 1283 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1284 struct r92c_rx_desc_usb *rxd; 1285 uint32_t rxdw0; 1286 uint8_t *buf; 1287 int len, totlen, pktlen, infosz, npkts, error, align; 1288 1289 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1290 DPRINTF(("RX status=%d\n", status)); 1291 if (status == USBD_STALLED) 1292 usbd_clear_endpoint_stall_async(sc->rx_pipe); 1293 if (status != USBD_CANCELLED) 1294 goto resubmit; 1295 return; 1296 } 1297 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 1298 1299 if (__predict_false(len < sizeof(*rxd))) { 1300 DPRINTF(("xfer too short %d\n", len)); 1301 goto resubmit; 1302 } 1303 buf = data->buf; 1304 1305 /* Get the number of encapsulated frames. */ 1306 rxd = (struct r92c_rx_desc_usb *)buf; 1307 npkts = MS(letoh32(rxd->rxdw2), R92C_RXDW2_PKTCNT); 1308 DPRINTFN(4, ("Rx %d frames in one chunk\n", npkts)); 1309 1310 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1311 int ntries, type; 1312 struct r88e_tx_rpt_ccx *rxstat; 1313 1314 type = MS(letoh32(rxd->rxdw3), R88E_RXDW3_RPT); 1315 1316 if (type == R88E_RXDW3_RPT_TX1) { 1317 buf += sizeof(struct r92c_rx_desc_usb); 1318 rxstat = (struct r88e_tx_rpt_ccx *)buf; 1319 ntries = MS(letoh32(rxstat->rptb2), 1320 R88E_RPTB2_RETRY_CNT); 1321 1322 if (rxstat->rptb1 & R88E_RPTB1_PKT_OK) 1323 sc->amn.amn_txcnt++; 1324 if (ntries > 0) 1325 sc->amn.amn_retrycnt++; 1326 1327 goto resubmit; 1328 } 1329 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 1330 int type; 1331 struct r92e_c2h_tx_rpt *txrpt; 1332 1333 if (letoh32(rxd->rxdw2) & R92E_RXDW2_RPT_C2H) { 1334 if (len < sizeof(struct r92c_rx_desc_usb) + 2) 1335 goto resubmit; 1336 1337 type = buf[sizeof(struct r92c_rx_desc_usb)]; 1338 switch (type) { 1339 case R92C_C2HEVT_TX_REPORT: 1340 buf += sizeof(struct r92c_rx_desc_usb) + 2; 1341 txrpt = (struct r92e_c2h_tx_rpt *)buf; 1342 if (MS(txrpt->rptb2, R92E_RPTB2_RETRY_CNT) > 0) 1343 sc->amn.amn_retrycnt++; 1344 if ((txrpt->rptb0 & (R92E_RPTB0_RETRY_OVER | 1345 R92E_RPTB0_LIFE_EXPIRE)) == 0) 1346 sc->amn.amn_txcnt++; 1347 break; 1348 default: 1349 break; 1350 } 1351 goto resubmit; 1352 } 1353 } 1354 1355 align = (sc->sc_sc.chip & RTWN_CHIP_92E ? 7 : 127); 1356 1357 /* Process all of them. */ 1358 while (npkts-- > 0) { 1359 if (__predict_false(len < sizeof(*rxd))) 1360 break; 1361 rxd = (struct r92c_rx_desc_usb *)buf; 1362 rxdw0 = letoh32(rxd->rxdw0); 1363 1364 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1365 if (__predict_false(pktlen == 0)) 1366 break; 1367 1368 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1369 1370 /* Make sure everything fits in xfer. */ 1371 totlen = sizeof(*rxd) + infosz + pktlen; 1372 if (__predict_false(totlen > len)) 1373 break; 1374 1375 /* Process 802.11 frame. */ 1376 urtwn_rx_frame(sc, buf, pktlen, &ml); 1377 1378 /* Handle chunk alignment. */ 1379 totlen = (totlen + align) & ~align; 1380 buf += totlen; 1381 len -= totlen; 1382 } 1383 if_input(&ic->ic_if, &ml); 1384 1385 resubmit: 1386 /* Setup a new transfer. */ 1387 usbd_setup_xfer(xfer, sc->rx_pipe, data, data->buf, URTWN_RXBUFSZ, 1388 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, urtwn_rxeof); 1389 error = usbd_transfer(data->xfer); 1390 if (error != 0 && error != USBD_IN_PROGRESS) 1391 DPRINTF(("could not set up new transfer: %d\n", error)); 1392 } 1393 1394 void 1395 urtwn_txeof(struct usbd_xfer *xfer, void *priv, 1396 usbd_status status) 1397 { 1398 struct urtwn_tx_data *data = priv; 1399 struct urtwn_softc *sc = data->sc; 1400 struct ifnet *ifp = &sc->sc_sc.sc_ic.ic_if; 1401 int s; 1402 1403 s = splnet(); 1404 /* Put this Tx buffer back to our free list. */ 1405 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1406 1407 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1408 DPRINTF(("TX status=%d\n", status)); 1409 if (status == USBD_STALLED) 1410 usbd_clear_endpoint_stall_async(data->pipe); 1411 ifp->if_oerrors++; 1412 splx(s); 1413 return; 1414 } 1415 sc->sc_sc.sc_tx_timer = 0; 1416 1417 /* We just released a Tx buffer, notify Tx. */ 1418 if (ifq_is_oactive(&ifp->if_snd)) { 1419 ifq_clr_oactive(&ifp->if_snd); 1420 rtwn_start(ifp); 1421 } 1422 splx(s); 1423 } 1424 1425 void 1426 urtwn_tx_fill_desc(struct urtwn_softc *sc, uint8_t **txdp, struct mbuf *m, 1427 struct ieee80211_frame *wh, struct ieee80211_key *k, 1428 struct ieee80211_node *ni) 1429 { 1430 struct r92c_tx_desc_usb *txd; 1431 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1432 uint8_t raid, type; 1433 uint32_t pktlen; 1434 1435 txd = (struct r92c_tx_desc_usb *)*txdp; 1436 (*txdp) += sizeof(*txd); 1437 memset(txd, 0, sizeof(*txd)); 1438 1439 pktlen = m->m_pkthdr.len; 1440 if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) { 1441 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, 1442 R92C_TXDW1_CIPHER_AES)); 1443 pktlen += IEEE80211_CCMP_HDRLEN; 1444 } 1445 1446 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1447 1448 txd->txdw0 |= htole32( 1449 SM(R92C_TXDW0_PKTLEN, pktlen) | 1450 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1451 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1452 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1453 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1454 1455 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1456 type == IEEE80211_FC0_TYPE_DATA) { 1457 if (ic->ic_curmode == IEEE80211_MODE_11B || 1458 (sc->sc_sc.sc_flags & RTWN_FLAG_FORCE_RAID_11B)) 1459 raid = R92C_RAID_11B; 1460 else 1461 raid = R92C_RAID_11BG; 1462 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1463 txd->txdw1 |= htole32( 1464 SM(R88E_TXDW1_MACID, R92C_MACID_BSS) | 1465 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1466 SM(R92C_TXDW1_RAID, raid)); 1467 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1468 /* Request TX status report for AMRR */ 1469 txd->txdw2 |= htole32(R92C_TXDW2_CCX_RPT); 1470 } else { 1471 txd->txdw1 |= htole32( 1472 SM(R92C_TXDW1_MACID, R92C_MACID_BSS) | 1473 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1474 SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1475 } 1476 1477 if (pktlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 1478 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1479 R92C_TXDW4_HWRTSEN); 1480 } else if (ic->ic_flags & IEEE80211_F_USEPROT) { 1481 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1482 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1483 R92C_TXDW4_HWRTSEN); 1484 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1485 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1486 R92C_TXDW4_HWRTSEN); 1487 } 1488 } 1489 txd->txdw5 |= htole32(0x0001ff00); 1490 1491 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1492 /* Use AMRR */ 1493 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1494 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 1495 ni->ni_txrate)); 1496 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1497 ni->ni_txrate)); 1498 } else { 1499 /* Send RTS at OFDM24 and data at OFDM54. */ 1500 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1501 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1502 } 1503 } else { 1504 txd->txdw1 |= htole32( 1505 SM(R92C_TXDW1_MACID, 0) | 1506 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1507 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1508 1509 /* Force CCK1. */ 1510 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1511 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1512 } 1513 /* Set sequence number (already little endian). */ 1514 txd->txdseq |= (*(uint16_t *)wh->i_seq) >> IEEE80211_SEQ_SEQ_SHIFT; 1515 1516 if (!ieee80211_has_qos(wh)) { 1517 /* Use HW sequence numbering for non-QoS frames. */ 1518 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1519 txd->txdseq |= htole16(R92C_TXDW3_HWSEQEN); 1520 } else 1521 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1522 } 1523 1524 void 1525 urtwn_tx_fill_desc_gen2(struct urtwn_softc *sc, uint8_t **txdp, struct mbuf *m, 1526 struct ieee80211_frame *wh, struct ieee80211_key *k, 1527 struct ieee80211_node *ni) 1528 { 1529 struct r92e_tx_desc_usb *txd; 1530 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1531 uint8_t raid, type; 1532 uint32_t pktlen; 1533 1534 txd = (struct r92e_tx_desc_usb *)*txdp; 1535 (*txdp) += sizeof(*txd); 1536 memset(txd, 0, sizeof(*txd)); 1537 1538 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1539 1540 pktlen = m->m_pkthdr.len; 1541 if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) { 1542 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, 1543 R92C_TXDW1_CIPHER_AES)); 1544 pktlen += IEEE80211_CCMP_HDRLEN; 1545 } 1546 1547 txd->txdw0 |= htole32( 1548 SM(R92C_TXDW0_PKTLEN, pktlen) | 1549 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1550 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1551 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1552 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1553 1554 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1555 type == IEEE80211_FC0_TYPE_DATA) { 1556 if (ic->ic_curmode == IEEE80211_MODE_11B || 1557 (sc->sc_sc.sc_flags & RTWN_FLAG_FORCE_RAID_11B)) 1558 raid = R92E_RAID_11B; 1559 else 1560 raid = R92E_RAID_11BG; 1561 txd->txdw1 |= htole32( 1562 SM(R92E_TXDW1_MACID, R92C_MACID_BSS) | 1563 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1564 SM(R92C_TXDW1_RAID, raid)); 1565 /* Request TX status report for AMRR */ 1566 txd->txdw2 |= htole32(R92C_TXDW2_CCX_RPT | R88E_TXDW2_AGGBK); 1567 1568 if (pktlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 1569 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1570 R92C_TXDW4_HWRTSEN); 1571 } else if (ic->ic_flags & IEEE80211_F_USEPROT) { 1572 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1573 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1574 R92C_TXDW4_HWRTSEN); 1575 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1576 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1577 R92C_TXDW4_HWRTSEN); 1578 } 1579 } 1580 txd->txdw5 |= htole32(0x0001ff00); 1581 1582 /* Use AMRR */ 1583 txd->txdw3 |= htole32(R92E_TXDW3_DRVRATE); 1584 txd->txdw4 |= htole32(SM(R92E_TXDW4_RTSRATE, ni->ni_txrate)); 1585 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATE, ni->ni_txrate)); 1586 } else { 1587 txd->txdw1 |= htole32( 1588 SM(R92E_TXDW1_MACID, 0) | 1589 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1590 SM(R92C_TXDW1_RAID, R92E_RAID_11B)); 1591 1592 /* Force CCK1. */ 1593 txd->txdw3 |= htole32(R92E_TXDW3_DRVRATE); 1594 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATE, 0)); 1595 } 1596 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATEFB, 0x1f)); 1597 1598 txd->txdseq2 |= htole16(SM(R92E_TXDSEQ2_HWSEQ, *(uint16_t *)wh->i_seq)); 1599 1600 if (!ieee80211_has_qos(wh)) { 1601 /* Use HW sequence numbering for non-QoS frames. */ 1602 txd->txdw7 |= htole16(R92C_TXDW3_HWSEQEN); 1603 } 1604 } 1605 1606 int 1607 urtwn_tx(void *cookie, struct mbuf *m, struct ieee80211_node *ni) 1608 { 1609 struct urtwn_softc *sc = cookie; 1610 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1611 struct ieee80211_frame *wh; 1612 struct ieee80211_key *k = NULL; 1613 struct urtwn_tx_data *data; 1614 struct usbd_pipe *pipe; 1615 uint16_t qos, sum; 1616 uint8_t tid, qid; 1617 int i, xferlen, error, headerlen; 1618 uint8_t *txdp; 1619 1620 wh = mtod(m, struct ieee80211_frame *); 1621 1622 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1623 k = ieee80211_get_txkey(ic, wh, ni); 1624 if (k->k_cipher != IEEE80211_CIPHER_CCMP) { 1625 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1626 return (ENOBUFS); 1627 wh = mtod(m, struct ieee80211_frame *); 1628 } 1629 } 1630 1631 if (ieee80211_has_qos(wh)) { 1632 qos = ieee80211_get_qos(wh); 1633 tid = qos & IEEE80211_QOS_TID; 1634 qid = ieee80211_up_to_ac(ic, tid); 1635 } else if ((wh->i_fc[1] & IEEE80211_FC0_TYPE_MASK) 1636 != IEEE80211_FC0_TYPE_DATA) { 1637 /* Use AC VO for management frames. */ 1638 qid = EDCA_AC_VO; 1639 } else 1640 qid = EDCA_AC_BE; 1641 1642 /* Get the USB pipe to use for this AC. */ 1643 pipe = sc->tx_pipe[sc->ac2idx[qid]]; 1644 1645 /* Grab a Tx buffer from our free list. */ 1646 data = TAILQ_FIRST(&sc->tx_free_list); 1647 TAILQ_REMOVE(&sc->tx_free_list, data, next); 1648 1649 /* Fill Tx descriptor. */ 1650 txdp = data->buf; 1651 if (sc->sc_sc.chip & RTWN_CHIP_92E) 1652 urtwn_tx_fill_desc_gen2(sc, &txdp, m, wh, k, ni); 1653 else 1654 urtwn_tx_fill_desc(sc, &txdp, m, wh, k, ni); 1655 1656 /* Compute Tx descriptor checksum. */ 1657 sum = 0; 1658 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 1659 sum ^= ((uint16_t *)data->buf)[i]; 1660 ((uint16_t *)data->buf)[R92C_TXDESC_SUMOFFSET] = sum; 1661 1662 #if NBPFILTER > 0 1663 if (__predict_false(sc->sc_drvbpf != NULL)) { 1664 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1665 struct mbuf mb; 1666 1667 tap->wt_flags = 0; 1668 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1669 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1670 1671 mb.m_data = (caddr_t)tap; 1672 mb.m_len = sc->sc_txtap_len; 1673 mb.m_next = m; 1674 mb.m_nextpkt = NULL; 1675 mb.m_type = 0; 1676 mb.m_flags = 0; 1677 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1678 } 1679 #endif 1680 1681 if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) { 1682 xferlen = (txdp - data->buf) + m->m_pkthdr.len + 1683 IEEE80211_CCMP_HDRLEN; 1684 headerlen = ieee80211_get_hdrlen(wh); 1685 1686 m_copydata(m, 0, headerlen, txdp); 1687 txdp += headerlen; 1688 1689 k->k_tsc++; 1690 txdp[0] = k->k_tsc; 1691 txdp[1] = k->k_tsc >> 8; 1692 txdp[2] = 0; 1693 txdp[3] = k->k_id | IEEE80211_WEP_EXTIV; 1694 txdp[4] = k->k_tsc >> 16; 1695 txdp[5] = k->k_tsc >> 24; 1696 txdp[6] = k->k_tsc >> 32; 1697 txdp[7] = k->k_tsc >> 40; 1698 txdp += IEEE80211_CCMP_HDRLEN; 1699 1700 m_copydata(m, headerlen, m->m_pkthdr.len - headerlen, txdp); 1701 m_freem(m); 1702 } else { 1703 xferlen = (txdp - data->buf) + m->m_pkthdr.len; 1704 m_copydata(m, 0, m->m_pkthdr.len, txdp); 1705 m_freem(m); 1706 } 1707 1708 data->pipe = pipe; 1709 usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen, 1710 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTWN_TX_TIMEOUT, 1711 urtwn_txeof); 1712 error = usbd_transfer(data->xfer); 1713 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) { 1714 /* Put this Tx buffer back to our free list. */ 1715 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1716 return (error); 1717 } 1718 ieee80211_release_node(ic, ni); 1719 return (0); 1720 } 1721 1722 int 1723 urtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1724 { 1725 struct rtwn_softc *sc_sc = ifp->if_softc; 1726 struct device *self = sc_sc->sc_pdev; 1727 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1728 int error; 1729 1730 if (usbd_is_dying(sc->sc_udev)) 1731 return ENXIO; 1732 1733 usbd_ref_incr(sc->sc_udev); 1734 error = rtwn_ioctl(ifp, cmd, data); 1735 usbd_ref_decr(sc->sc_udev); 1736 1737 return (error); 1738 } 1739 1740 int 1741 urtwn_r92c_power_on(struct urtwn_softc *sc) 1742 { 1743 uint32_t reg; 1744 int ntries; 1745 1746 /* Wait for autoload done bit. */ 1747 for (ntries = 0; ntries < 1000; ntries++) { 1748 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 1749 break; 1750 DELAY(5); 1751 } 1752 if (ntries == 1000) { 1753 printf("%s: timeout waiting for chip autoload\n", 1754 sc->sc_dev.dv_xname); 1755 return (ETIMEDOUT); 1756 } 1757 1758 /* Unlock ISO/CLK/Power control register. */ 1759 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 1760 /* Move SPS into PWM mode. */ 1761 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 1762 DELAY(100); 1763 1764 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 1765 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 1766 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 1767 reg | R92C_LDOV12D_CTRL_LDV12_EN); 1768 DELAY(100); 1769 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 1770 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 1771 ~R92C_SYS_ISO_CTRL_MD2PP); 1772 } 1773 1774 /* Auto enable WLAN. */ 1775 urtwn_write_2(sc, R92C_APS_FSMCO, 1776 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1777 for (ntries = 0; ntries < 1000; ntries++) { 1778 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1779 R92C_APS_FSMCO_APFM_ONMAC)) 1780 break; 1781 DELAY(5); 1782 } 1783 if (ntries == 1000) { 1784 printf("%s: timeout waiting for MAC auto ON\n", 1785 sc->sc_dev.dv_xname); 1786 return (ETIMEDOUT); 1787 } 1788 1789 /* Enable radio, GPIO and LED functions. */ 1790 urtwn_write_2(sc, R92C_APS_FSMCO, 1791 R92C_APS_FSMCO_AFSM_HSUS | 1792 R92C_APS_FSMCO_PDN_EN | 1793 R92C_APS_FSMCO_PFM_ALDN); 1794 /* Release RF digital isolation. */ 1795 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1796 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 1797 1798 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1799 reg = urtwn_read_2(sc, R92C_CR); 1800 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1801 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1802 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 1803 R92C_CR_ENSEC; 1804 urtwn_write_2(sc, R92C_CR, reg); 1805 1806 urtwn_write_1(sc, 0xfe10, 0x19); 1807 return (0); 1808 } 1809 1810 int 1811 urtwn_r92e_power_on(struct urtwn_softc *sc) 1812 { 1813 uint32_t reg; 1814 int ntries; 1815 1816 if (urtwn_read_4(sc, R92C_SYS_CFG) & R92E_SYS_CFG_SPSLDO_SEL) { 1817 /* LDO. */ 1818 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 1819 } else { 1820 reg = urtwn_read_4(sc, R92C_SYS_SWR_CTRL2); 1821 reg &= 0xff0fffff; 1822 reg |= 0x00500000; 1823 urtwn_write_4(sc, R92C_SYS_SWR_CTRL2, reg); 1824 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 1825 } 1826 1827 /* 40MHz crystal source */ 1828 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 1829 urtwn_read_1(sc, R92C_AFE_PLL_CTRL) & 0xfb); 1830 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL_EXT, 1831 urtwn_read_4(sc, R92C_AFE_XTAL_CTRL_EXT) & 0xfffffc7f); 1832 1833 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 1834 urtwn_read_1(sc, R92C_AFE_PLL_CTRL) & 0xbf); 1835 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL_EXT, 1836 urtwn_read_4(sc, R92C_AFE_XTAL_CTRL_EXT) & 0xffdfffff); 1837 1838 /* Disable HWPDN. */ 1839 urtwn_write_2(sc, R92C_APS_FSMCO, 1840 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 1841 for (ntries = 0; ntries < 5000; ntries++) { 1842 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 1843 break; 1844 DELAY(10); 1845 } 1846 if (ntries == 5000) { 1847 printf("%s: timeout waiting for chip power up\n", 1848 sc->sc_dev.dv_xname); 1849 return (ETIMEDOUT); 1850 } 1851 1852 /* Disable WL suspend. */ 1853 urtwn_write_2(sc, R92C_APS_FSMCO, 1854 urtwn_read_2(sc, R92C_APS_FSMCO) & 1855 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 1856 1857 /* Auto enable WLAN. */ 1858 urtwn_write_4(sc, R92C_APS_FSMCO, 1859 urtwn_read_4(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 1860 urtwn_write_2(sc, R92C_APS_FSMCO, 1861 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1862 for (ntries = 0; ntries < 5000; ntries++) { 1863 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1864 R92C_APS_FSMCO_APFM_ONMAC)) 1865 break; 1866 DELAY(10); 1867 } 1868 if (ntries == 5000) { 1869 printf("%s: timeout waiting for MAC auto ON\n", 1870 sc->sc_dev.dv_xname); 1871 return (ETIMEDOUT); 1872 } 1873 1874 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1875 urtwn_write_2(sc, R92C_CR, 0); 1876 reg = urtwn_read_2(sc, R92C_CR); 1877 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1878 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1879 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 1880 urtwn_write_2(sc, R92C_CR, reg); 1881 return (0); 1882 } 1883 1884 int 1885 urtwn_r88e_power_on(struct urtwn_softc *sc) 1886 { 1887 uint32_t reg; 1888 int ntries; 1889 1890 /* Wait for power ready bit. */ 1891 for (ntries = 0; ntries < 5000; ntries++) { 1892 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 1893 break; 1894 DELAY(10); 1895 } 1896 if (ntries == 5000) { 1897 printf("%s: timeout waiting for chip power up\n", 1898 sc->sc_dev.dv_xname); 1899 return (ETIMEDOUT); 1900 } 1901 1902 /* Reset BB. */ 1903 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 1904 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 1905 R92C_SYS_FUNC_EN_BB_GLB_RST)); 1906 1907 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 1908 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 1909 1910 /* Disable HWPDN. */ 1911 urtwn_write_2(sc, R92C_APS_FSMCO, 1912 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 1913 /* Disable WL suspend. */ 1914 urtwn_write_2(sc, R92C_APS_FSMCO, 1915 urtwn_read_2(sc, R92C_APS_FSMCO) & 1916 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 1917 1918 /* Auto enable WLAN. */ 1919 urtwn_write_2(sc, R92C_APS_FSMCO, 1920 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1921 for (ntries = 0; ntries < 5000; ntries++) { 1922 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1923 R92C_APS_FSMCO_APFM_ONMAC)) 1924 break; 1925 DELAY(10); 1926 } 1927 if (ntries == 5000) { 1928 printf("%s: timeout waiting for MAC auto ON\n", 1929 sc->sc_dev.dv_xname); 1930 return (ETIMEDOUT); 1931 } 1932 1933 /* Enable LDO normal mode. */ 1934 urtwn_write_1(sc, R92C_LPLDO_CTRL, 1935 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 1936 1937 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1938 urtwn_write_2(sc, R92C_CR, 0); 1939 reg = urtwn_read_2(sc, R92C_CR); 1940 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1941 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1942 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 1943 urtwn_write_2(sc, R92C_CR, reg); 1944 return (0); 1945 } 1946 1947 int 1948 urtwn_llt_init(struct urtwn_softc *sc, int page_count) 1949 { 1950 int i, error, pktbuf_count; 1951 1952 pktbuf_count = (sc->sc_sc.chip & RTWN_CHIP_88E) ? 1953 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 1954 1955 /* Reserve pages [0; page_count]. */ 1956 for (i = 0; i < page_count; i++) { 1957 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1958 return (error); 1959 } 1960 /* NB: 0xff indicates end-of-list. */ 1961 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 1962 return (error); 1963 /* 1964 * Use pages [page_count + 1; pktbuf_count - 1] 1965 * as ring buffer. 1966 */ 1967 for (++i; i < pktbuf_count - 1; i++) { 1968 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1969 return (error); 1970 } 1971 /* Make the last page point to the beginning of the ring buffer. */ 1972 error = urtwn_llt_write(sc, i, page_count + 1); 1973 return (error); 1974 } 1975 1976 int 1977 urtwn_auto_llt_init(struct urtwn_softc *sc) 1978 { 1979 int ntries; 1980 1981 urtwn_write_4(sc, R92E_AUTO_LLT, urtwn_read_4(sc, 1982 R92E_AUTO_LLT) | R92E_AUTO_LLT_EN); 1983 for (ntries = 0; ntries < 1000; ntries++) { 1984 if (!(urtwn_read_4(sc, R92E_AUTO_LLT) & R92E_AUTO_LLT_EN)) 1985 return (0); 1986 DELAY(2); 1987 } 1988 1989 return (ETIMEDOUT); 1990 } 1991 1992 int 1993 urtwn_fw_loadpage(void *cookie, int page, uint8_t *buf, int len) 1994 { 1995 struct urtwn_softc *sc = cookie; 1996 uint32_t reg; 1997 int off, mlen, error = 0; 1998 1999 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2000 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2001 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2002 2003 off = R92C_FW_START_ADDR; 2004 while (len > 0) { 2005 if (len > 196) 2006 mlen = 196; 2007 else if (len > 4) 2008 mlen = 4; 2009 else 2010 mlen = 1; 2011 error = urtwn_write_region_1(sc, off, buf, mlen); 2012 if (error != 0) 2013 break; 2014 off += mlen; 2015 buf += mlen; 2016 len -= mlen; 2017 } 2018 return (error); 2019 } 2020 2021 int 2022 urtwn_load_firmware(void *cookie, u_char **fw, size_t *len) 2023 { 2024 struct urtwn_softc *sc = cookie; 2025 const char *name; 2026 int error; 2027 2028 if (sc->sc_sc.chip & RTWN_CHIP_92E) 2029 name = "urtwn-rtl8192eu_nic"; 2030 else if (sc->sc_sc.chip & RTWN_CHIP_88E) 2031 name = "urtwn-rtl8188eufw"; 2032 else if ((sc->sc_sc.chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2033 RTWN_CHIP_UMC_A_CUT) 2034 name = "urtwn-rtl8192cfwU"; 2035 else 2036 name = "urtwn-rtl8192cfwT"; 2037 2038 error = loadfirmware(name, fw, len); 2039 if (error) 2040 printf("%s: could not read firmware %s (error %d)\n", 2041 sc->sc_dev.dv_xname, name, error); 2042 return (error); 2043 } 2044 2045 int 2046 urtwn_dma_init(void *cookie) 2047 { 2048 struct urtwn_softc *sc = cookie; 2049 uint32_t reg; 2050 uint16_t dmasize; 2051 int hqpages, lqpages, nqpages, pagecnt, boundary; 2052 int error, hashq, haslq, hasnq; 2053 2054 /* Default initialization of chipset values. */ 2055 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2056 hqpages = R88E_HQ_NPAGES; 2057 lqpages = R88E_LQ_NPAGES; 2058 nqpages = R88E_NQ_NPAGES; 2059 pagecnt = R88E_TX_PAGE_COUNT; 2060 boundary = R88E_TX_PAGE_BOUNDARY; 2061 dmasize = R88E_MAX_RX_DMA_SIZE; 2062 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2063 hqpages = R92E_HQ_NPAGES; 2064 lqpages = R92E_LQ_NPAGES; 2065 nqpages = R92E_NQ_NPAGES; 2066 pagecnt = R92E_TX_PAGE_COUNT; 2067 boundary = R92E_TX_PAGE_BOUNDARY; 2068 dmasize = R92E_MAX_RX_DMA_SIZE; 2069 } else { 2070 hqpages = R92C_HQ_NPAGES; 2071 lqpages = R92C_LQ_NPAGES; 2072 nqpages = R92C_NQ_NPAGES; 2073 pagecnt = R92C_TX_PAGE_COUNT; 2074 boundary = R92C_TX_PAGE_BOUNDARY; 2075 dmasize = R92C_MAX_RX_DMA_SIZE; 2076 } 2077 2078 /* Initialize LLT table. */ 2079 if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2080 error = urtwn_auto_llt_init(sc); 2081 } else { 2082 error = urtwn_llt_init(sc, pagecnt); 2083 } 2084 if (error != 0) 2085 return (error); 2086 2087 /* Get Tx queues to USB endpoints mapping. */ 2088 hashq = hasnq = haslq = 0; 2089 switch (sc->ntx) { 2090 case 3: 2091 haslq = 1; 2092 pagecnt -= lqpages; 2093 /* FALLTHROUGH */ 2094 case 2: 2095 hasnq = 1; 2096 pagecnt -= nqpages; 2097 /* FALLTHROUGH */ 2098 case 1: 2099 hashq = 1; 2100 pagecnt -= hqpages; 2101 break; 2102 } 2103 2104 /* Set number of pages for normal priority queue. */ 2105 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2106 urtwn_write_4(sc, R92C_RQPN, 2107 /* Set number of pages for public queue. */ 2108 SM(R92C_RQPN_PUBQ, pagecnt) | 2109 /* Set number of pages for high priority queue. */ 2110 SM(R92C_RQPN_HPQ, hashq ? hqpages : 0) | 2111 /* Set number of pages for low priority queue. */ 2112 SM(R92C_RQPN_LPQ, haslq ? lqpages : 0) | 2113 /* Load values. */ 2114 R92C_RQPN_LD); 2115 2116 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, boundary); 2117 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, boundary); 2118 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, boundary); 2119 urtwn_write_1(sc, R92C_TRXFF_BNDY, boundary); 2120 urtwn_write_1(sc, R92C_TDECTRL + 1, boundary); 2121 2122 /* Set queue to USB pipe mapping. */ 2123 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2124 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2125 if (haslq) 2126 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2127 else if (hashq) { 2128 if (!hasnq) 2129 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2130 else 2131 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2132 } 2133 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2134 2135 /* Set Tx/Rx transfer page boundary. */ 2136 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, dmasize - 1); 2137 2138 if (!(sc->sc_sc.chip & RTWN_CHIP_92E)) { 2139 /* Set Tx/Rx transfer page size. */ 2140 urtwn_write_1(sc, R92C_PBP, 2141 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2142 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2143 } 2144 return (error); 2145 } 2146 2147 void 2148 urtwn_aggr_init(void *cookie) 2149 { 2150 struct urtwn_softc *sc = cookie; 2151 uint32_t reg = 0; 2152 int dmasize, dmatiming, ndesc; 2153 2154 /* Set burst packet length. */ 2155 if (sc->sc_sc.chip & RTWN_CHIP_92E) 2156 urtwn_burstlen_init(sc); 2157 2158 if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2159 dmasize = 6; 2160 dmatiming = 32; 2161 ndesc = 3; 2162 } else { 2163 dmasize = 48; 2164 dmatiming = 4; 2165 ndesc = (sc->sc_sc.chip & RTWN_CHIP_88E) ? 1 : 6; 2166 } 2167 2168 /* Tx aggregation setting. */ 2169 if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2170 urtwn_write_1(sc, R92E_DWBCN1_CTRL, ndesc << 1); 2171 } else { 2172 reg = urtwn_read_4(sc, R92C_TDECTRL); 2173 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, ndesc); 2174 urtwn_write_4(sc, R92C_TDECTRL, reg); 2175 } 2176 2177 /* Rx aggregation setting. */ 2178 if (!(sc->sc_sc.chip & RTWN_CHIP_92E)) { 2179 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 2180 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 2181 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 2182 } 2183 2184 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, dmasize); 2185 if (sc->sc_sc.chip & (RTWN_CHIP_92C | RTWN_CHIP_88C)) 2186 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, dmatiming); 2187 else 2188 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, dmatiming); 2189 2190 /* Drop incorrect bulk out. */ 2191 urtwn_write_4(sc, R92C_TXDMA_OFFSET_CHK, 2192 urtwn_read_4(sc, R92C_TXDMA_OFFSET_CHK) | 2193 R92C_TXDMA_OFFSET_CHK_DROP_DATA_EN); 2194 } 2195 2196 void 2197 urtwn_mac_init(void *cookie) 2198 { 2199 struct urtwn_softc *sc = cookie; 2200 int i; 2201 2202 /* Write MAC initialization values. */ 2203 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2204 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2205 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2206 rtl8188eu_mac[i].val); 2207 } 2208 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2209 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2210 for (i = 0; i < nitems(rtl8192eu_mac); i++) { 2211 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 2212 rtl8192eu_mac[i].val); 2213 } 2214 } else { 2215 for (i = 0; i < nitems(rtl8192cu_mac); i++) 2216 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2217 rtl8192cu_mac[i].val); 2218 } 2219 } 2220 2221 void 2222 urtwn_bb_init(void *cookie) 2223 { 2224 struct urtwn_softc *sc = cookie; 2225 const struct r92c_bb_prog *prog; 2226 uint32_t reg; 2227 uint8_t xtal; 2228 int i; 2229 2230 /* Enable BB and RF. */ 2231 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2232 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2233 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2234 R92C_SYS_FUNC_EN_DIO_RF); 2235 2236 if (!(sc->sc_sc.chip & (RTWN_CHIP_88E | RTWN_CHIP_92E))) 2237 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2238 2239 urtwn_write_1(sc, R92C_RF_CTRL, 2240 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2241 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2242 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2243 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2244 2245 if (!(sc->sc_sc.chip & (RTWN_CHIP_88E | RTWN_CHIP_92E))) { 2246 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2247 urtwn_write_1(sc, 0x15, 0xe9); 2248 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2249 } 2250 2251 /* Select BB programming based on board type. */ 2252 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2253 prog = &rtl8188eu_bb_prog; 2254 else if (sc->sc_sc.chip & RTWN_CHIP_92E) 2255 prog = &rtl8192eu_bb_prog; 2256 else if (!(sc->sc_sc.chip & RTWN_CHIP_92C)) { 2257 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD) 2258 prog = &rtl8188ce_bb_prog; 2259 else if (sc->sc_sc.board_type == R92C_BOARD_TYPE_HIGHPA) 2260 prog = &rtl8188ru_bb_prog; 2261 else 2262 prog = &rtl8188cu_bb_prog; 2263 } else { 2264 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD) 2265 prog = &rtl8192ce_bb_prog; 2266 else 2267 prog = &rtl8192cu_bb_prog; 2268 } 2269 /* Write BB initialization values. */ 2270 for (i = 0; i < prog->count; i++) { 2271 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2272 DELAY(1); 2273 } 2274 2275 if (sc->sc_sc.chip & RTWN_CHIP_92C_1T2R) { 2276 /* 8192C 1T only configuration. */ 2277 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2278 reg = (reg & ~0x00000003) | 0x2; 2279 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2280 2281 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2282 reg = (reg & ~0x00300033) | 0x00200022; 2283 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2284 2285 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2286 reg = (reg & ~0xff000000) | 0x45 << 24; 2287 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2288 2289 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2290 reg = (reg & ~0x000000ff) | 0x23; 2291 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2292 2293 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2294 reg = (reg & ~0x00000030) | 1 << 4; 2295 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2296 2297 reg = urtwn_bb_read(sc, 0xe74); 2298 reg = (reg & ~0x0c000000) | 2 << 26; 2299 urtwn_bb_write(sc, 0xe74, reg); 2300 reg = urtwn_bb_read(sc, 0xe78); 2301 reg = (reg & ~0x0c000000) | 2 << 26; 2302 urtwn_bb_write(sc, 0xe78, reg); 2303 reg = urtwn_bb_read(sc, 0xe7c); 2304 reg = (reg & ~0x0c000000) | 2 << 26; 2305 urtwn_bb_write(sc, 0xe7c, reg); 2306 reg = urtwn_bb_read(sc, 0xe80); 2307 reg = (reg & ~0x0c000000) | 2 << 26; 2308 urtwn_bb_write(sc, 0xe80, reg); 2309 reg = urtwn_bb_read(sc, 0xe88); 2310 reg = (reg & ~0x0c000000) | 2 << 26; 2311 urtwn_bb_write(sc, 0xe88, reg); 2312 } 2313 2314 /* Write AGC values. */ 2315 for (i = 0; i < prog->agccount; i++) { 2316 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2317 prog->agcvals[i]); 2318 DELAY(1); 2319 } 2320 2321 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2322 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2323 DELAY(1); 2324 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2325 DELAY(1); 2326 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2327 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040022); 2328 DELAY(1); 2329 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040020); 2330 DELAY(1); 2331 } 2332 2333 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2334 xtal = sc->sc_sc.crystal_cap & 0x3f; 2335 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2336 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2337 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, xtal | xtal << 6)); 2338 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2339 xtal = sc->sc_sc.crystal_cap & 0x3f; 2340 reg = urtwn_read_4(sc, R92C_AFE_CTRL3); 2341 reg &= 0xff000fff; 2342 reg |= (xtal | (xtal << 6)) << 12; 2343 urtwn_write_4(sc, R92C_AFE_CTRL3, reg); 2344 2345 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0x000f81fb); 2346 } 2347 2348 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & R92C_HSSI_PARAM2_CCK_HIPWR) 2349 sc->sc_sc.sc_flags |= RTWN_FLAG_CCK_HIPWR; 2350 } 2351 2352 void 2353 urtwn_burstlen_init(struct urtwn_softc *sc) 2354 { 2355 uint8_t reg; 2356 2357 reg = urtwn_read_1(sc, R92E_RXDMA_PRO); 2358 reg &= ~0x30; 2359 switch (sc->sc_udev->speed) { 2360 case USB_SPEED_HIGH: 2361 urtwn_write_1(sc, R92E_RXDMA_PRO, reg | 0x1e); 2362 break; 2363 default: 2364 urtwn_write_1(sc, R92E_RXDMA_PRO, reg | 0x2e); 2365 break; 2366 } 2367 } 2368 2369 int 2370 urtwn_power_on(void *cookie) 2371 { 2372 struct urtwn_softc *sc = cookie; 2373 2374 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2375 return (urtwn_r88e_power_on(sc)); 2376 else if (sc->sc_sc.chip & RTWN_CHIP_92E) 2377 return (urtwn_r92e_power_on(sc)); 2378 2379 return (urtwn_r92c_power_on(sc)); 2380 } 2381 2382 int 2383 urtwn_alloc_buffers(void *cookie) 2384 { 2385 struct urtwn_softc *sc = cookie; 2386 int error; 2387 2388 /* Init host async commands ring. */ 2389 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 2390 2391 /* Allocate Tx/Rx buffers. */ 2392 error = urtwn_alloc_rx_list(sc); 2393 if (error != 0) { 2394 printf("%s: could not allocate Rx buffers\n", 2395 sc->sc_dev.dv_xname); 2396 return (error); 2397 } 2398 error = urtwn_alloc_tx_list(sc); 2399 if (error != 0) { 2400 printf("%s: could not allocate Tx buffers\n", 2401 sc->sc_dev.dv_xname); 2402 return (error); 2403 } 2404 2405 return (0); 2406 } 2407 2408 int 2409 urtwn_init(void *cookie) 2410 { 2411 struct urtwn_softc *sc = cookie; 2412 int i, error; 2413 2414 if (sc->sc_sc.chip & RTWN_CHIP_92E) 2415 urtwn_write_1(sc, R92C_ACLK_MON, 0); 2416 2417 /* Queue Rx xfers. */ 2418 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 2419 struct urtwn_rx_data *data = &sc->rx_data[i]; 2420 2421 usbd_setup_xfer(data->xfer, sc->rx_pipe, data, data->buf, 2422 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 2423 USBD_NO_TIMEOUT, urtwn_rxeof); 2424 error = usbd_transfer(data->xfer); 2425 if (error != 0 && error != USBD_IN_PROGRESS) 2426 return (error); 2427 } 2428 2429 ieee80211_amrr_node_init(&sc->amrr, &sc->amn); 2430 2431 /* 2432 * Enable TX reports for AMRR. 2433 * In order to get reports we need to explicitly reset the register. 2434 */ 2435 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2436 urtwn_write_1(sc, R88E_TX_RPT_CTRL, (urtwn_read_1(sc, 2437 R88E_TX_RPT_CTRL) & ~0) | R88E_TX_RPT_CTRL_EN); 2438 2439 return (0); 2440 } 2441 2442 void 2443 urtwn_stop(void *cookie) 2444 { 2445 struct urtwn_softc *sc = cookie; 2446 int i; 2447 2448 /* Abort Tx. */ 2449 for (i = 0; i < R92C_MAX_EPOUT; i++) { 2450 if (sc->tx_pipe[i] != NULL) 2451 usbd_abort_pipe(sc->tx_pipe[i]); 2452 } 2453 /* Stop Rx pipe. */ 2454 usbd_abort_pipe(sc->rx_pipe); 2455 /* Free Tx/Rx buffers. */ 2456 urtwn_free_tx_list(sc); 2457 urtwn_free_rx_list(sc); 2458 } 2459 2460 int 2461 urtwn_is_oactive(void *cookie) 2462 { 2463 struct urtwn_softc *sc = cookie; 2464 2465 return (TAILQ_EMPTY(&sc->tx_free_list)); 2466 } 2467