1 /* $OpenBSD: if_urtwn.c,v 1.83 2019/03/11 06:19:33 kevlo Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss@yahoo.com.au> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU/ 23 * RTL8192EU. 24 */ 25 26 #include "bpfilter.h" 27 28 #include <sys/param.h> 29 #include <sys/sockio.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/timeout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 #include <sys/endian.h> 38 39 #include <machine/bus.h> 40 #include <machine/intr.h> 41 42 #if NBPFILTER > 0 43 #include <net/bpf.h> 44 #endif 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 49 #include <netinet/in.h> 50 #include <netinet/if_ether.h> 51 52 #include <net80211/ieee80211_var.h> 53 #include <net80211/ieee80211_amrr.h> 54 #include <net80211/ieee80211_radiotap.h> 55 56 #include <dev/usb/usb.h> 57 #include <dev/usb/usbdi.h> 58 #include <dev/usb/usbdivar.h> 59 #include <dev/usb/usbdi_util.h> 60 #include <dev/usb/usbdevs.h> 61 62 #include <dev/ic/r92creg.h> 63 #include <dev/ic/rtwnvar.h> 64 65 /* Maximum number of output pipes is 3. */ 66 #define R92C_MAX_EPOUT 3 67 68 #define R92C_HQ_NPAGES 12 69 #define R92C_LQ_NPAGES 2 70 #define R92C_NQ_NPAGES 2 71 #define R92C_TXPKTBUF_COUNT 256 72 #define R92C_TX_PAGE_COUNT 248 73 #define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) 74 #define R92C_MAX_RX_DMA_SIZE 0x2800 75 76 #define R88E_HQ_NPAGES 0 77 #define R88E_LQ_NPAGES 9 78 #define R88E_NQ_NPAGES 0 79 #define R88E_TXPKTBUF_COUNT 177 80 #define R88E_TX_PAGE_COUNT 168 81 #define R88E_TX_PAGE_BOUNDARY (R88E_TX_PAGE_COUNT + 1) 82 #define R88E_MAX_RX_DMA_SIZE 0x2400 83 84 #define R92E_HQ_NPAGES 16 85 #define R92E_LQ_NPAGES 16 86 #define R92E_NQ_NPAGES 16 87 #define R92E_TX_PAGE_COUNT 248 88 #define R92E_TX_PAGE_BOUNDARY (R92E_TX_PAGE_COUNT + 1) 89 #define R92E_MAX_RX_DMA_SIZE 0x3fc0 90 91 #define R92C_TXDESC_SUMSIZE 32 92 #define R92C_TXDESC_SUMOFFSET 14 93 94 /* USB Requests. */ 95 #define R92C_REQ_REGS 0x05 96 97 /* 98 * Driver definitions. 99 */ 100 #define URTWN_RX_LIST_COUNT 1 101 #define URTWN_TX_LIST_COUNT 8 102 #define URTWN_HOST_CMD_RING_COUNT 32 103 104 #define URTWN_RXBUFSZ (16 * 1024) 105 #define URTWN_TXBUFSZ (sizeof(struct r92e_tx_desc_usb) + IEEE80211_MAX_LEN) 106 107 #define URTWN_RIDX_COUNT 28 108 109 #define URTWN_TX_TIMEOUT 5000 /* ms */ 110 111 #define URTWN_LED_LINK 0 112 #define URTWN_LED_DATA 1 113 114 struct urtwn_rx_radiotap_header { 115 struct ieee80211_radiotap_header wr_ihdr; 116 uint8_t wr_flags; 117 uint8_t wr_rate; 118 uint16_t wr_chan_freq; 119 uint16_t wr_chan_flags; 120 uint8_t wr_dbm_antsignal; 121 } __packed; 122 123 #define URTWN_RX_RADIOTAP_PRESENT \ 124 (1 << IEEE80211_RADIOTAP_FLAGS | \ 125 1 << IEEE80211_RADIOTAP_RATE | \ 126 1 << IEEE80211_RADIOTAP_CHANNEL | \ 127 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) 128 129 struct urtwn_tx_radiotap_header { 130 struct ieee80211_radiotap_header wt_ihdr; 131 uint8_t wt_flags; 132 uint16_t wt_chan_freq; 133 uint16_t wt_chan_flags; 134 } __packed; 135 136 #define URTWN_TX_RADIOTAP_PRESENT \ 137 (1 << IEEE80211_RADIOTAP_FLAGS | \ 138 1 << IEEE80211_RADIOTAP_CHANNEL) 139 140 struct urtwn_softc; 141 142 struct urtwn_rx_data { 143 struct urtwn_softc *sc; 144 struct usbd_xfer *xfer; 145 uint8_t *buf; 146 }; 147 148 struct urtwn_tx_data { 149 struct urtwn_softc *sc; 150 struct usbd_pipe *pipe; 151 struct usbd_xfer *xfer; 152 uint8_t *buf; 153 TAILQ_ENTRY(urtwn_tx_data) next; 154 }; 155 156 struct urtwn_host_cmd { 157 void (*cb)(struct urtwn_softc *, void *); 158 uint8_t data[256]; 159 }; 160 161 struct urtwn_cmd_newstate { 162 enum ieee80211_state state; 163 int arg; 164 }; 165 166 struct urtwn_cmd_key { 167 struct ieee80211_key key; 168 struct ieee80211_node *ni; 169 }; 170 171 struct urtwn_host_cmd_ring { 172 struct urtwn_host_cmd cmd[URTWN_HOST_CMD_RING_COUNT]; 173 int cur; 174 int next; 175 int queued; 176 }; 177 178 struct urtwn_softc { 179 struct device sc_dev; 180 struct rtwn_softc sc_sc; 181 182 struct usbd_device *sc_udev; 183 struct usbd_interface *sc_iface; 184 struct usb_task sc_task; 185 186 struct timeout scan_to; 187 struct timeout calib_to; 188 189 int ntx; 190 struct usbd_pipe *rx_pipe; 191 struct usbd_pipe *tx_pipe[R92C_MAX_EPOUT]; 192 int ac2idx[EDCA_NUM_AC]; 193 194 struct urtwn_host_cmd_ring cmdq; 195 struct urtwn_rx_data rx_data[URTWN_RX_LIST_COUNT]; 196 struct urtwn_tx_data tx_data[URTWN_TX_LIST_COUNT]; 197 TAILQ_HEAD(, urtwn_tx_data) tx_free_list; 198 199 struct ieee80211_amrr amrr; 200 struct ieee80211_amrr_node amn; 201 202 #if NBPFILTER > 0 203 caddr_t sc_drvbpf; 204 205 union { 206 struct urtwn_rx_radiotap_header th; 207 uint8_t pad[64]; 208 } sc_rxtapu; 209 #define sc_rxtap sc_rxtapu.th 210 int sc_rxtap_len; 211 212 union { 213 struct urtwn_tx_radiotap_header th; 214 uint8_t pad[64]; 215 } sc_txtapu; 216 #define sc_txtap sc_txtapu.th 217 int sc_txtap_len; 218 #endif 219 }; 220 221 #ifdef URTWN_DEBUG 222 #define DPRINTF(x) do { if (urtwn_debug) printf x; } while (0) 223 #define DPRINTFN(n, x) do { if (urtwn_debug >= (n)) printf x; } while (0) 224 int urtwn_debug = 4; 225 #else 226 #define DPRINTF(x) 227 #define DPRINTFN(n, x) 228 #endif 229 230 /* 231 * Various supported device vendors/products. 232 */ 233 #define URTWN_DEV(v, p, f) \ 234 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, (f) | RTWN_CHIP_USB } 235 #define URTWN_DEV_8192CU(v, p) URTWN_DEV(v, p, RTWN_CHIP_92C | RTWN_CHIP_88C) 236 #define URTWN_DEV_8188EU(v, p) URTWN_DEV(v, p, RTWN_CHIP_88E) 237 #define URTWN_DEV_8192EU(v, p) URTWN_DEV(v, p, RTWN_CHIP_92E) 238 static const struct urtwn_type { 239 struct usb_devno dev; 240 uint32_t chip; 241 } urtwn_devs[] = { 242 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_1), 243 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_1), 244 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_2), 245 URTWN_DEV_8192CU(ABOCOM, RTL8192CU), 246 URTWN_DEV_8192CU(ASUS, RTL8192CU), 247 URTWN_DEV_8192CU(ASUS, RTL8192CU_2), 248 URTWN_DEV_8192CU(ASUS, RTL8192CU_3), 249 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CE_1), 250 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CE_2), 251 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CU), 252 URTWN_DEV_8192CU(BELKIN, F7D2102), 253 URTWN_DEV_8192CU(BELKIN, F9L1004V1), 254 URTWN_DEV_8192CU(BELKIN, RTL8188CU), 255 URTWN_DEV_8192CU(BELKIN, RTL8188CUS), 256 URTWN_DEV_8192CU(BELKIN, RTL8192CU), 257 URTWN_DEV_8192CU(BELKIN, RTL8192CU_1), 258 URTWN_DEV_8192CU(BELKIN, RTL8192CU_2), 259 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_1), 260 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_2), 261 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_3), 262 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_4), 263 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_5), 264 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_6), 265 URTWN_DEV_8192CU(COMPARE, RTL8192CU), 266 URTWN_DEV_8192CU(COREGA, RTL8192CU), 267 URTWN_DEV_8192CU(DLINK, DWA131B), 268 URTWN_DEV_8192CU(DLINK, RTL8188CU), 269 URTWN_DEV_8192CU(DLINK, RTL8192CU_1), 270 URTWN_DEV_8192CU(DLINK, RTL8192CU_2), 271 URTWN_DEV_8192CU(DLINK, RTL8192CU_3), 272 URTWN_DEV_8192CU(DLINK, RTL8192CU_4), 273 URTWN_DEV_8192CU(EDIMAX, EW7811UN), 274 URTWN_DEV_8192CU(EDIMAX, RTL8192CU), 275 URTWN_DEV_8192CU(FEIXUN, RTL8188CU), 276 URTWN_DEV_8192CU(FEIXUN, RTL8192CU), 277 URTWN_DEV_8192CU(GUILLEMOT, HWNUP150), 278 URTWN_DEV_8192CU(GUILLEMOT, RTL8192CU), 279 URTWN_DEV_8192CU(HAWKING, RTL8192CU), 280 URTWN_DEV_8192CU(HAWKING, RTL8192CU_2), 281 URTWN_DEV_8192CU(HP3, RTL8188CU), 282 URTWN_DEV_8192CU(IODATA, WNG150UM), 283 URTWN_DEV_8192CU(IODATA, RTL8192CU), 284 URTWN_DEV_8192CU(NETGEAR, N300MA), 285 URTWN_DEV_8192CU(NETGEAR, WNA1000M), 286 URTWN_DEV_8192CU(NETGEAR, WNA1000Mv2), 287 URTWN_DEV_8192CU(NETGEAR, RTL8192CU), 288 URTWN_DEV_8192CU(NETGEAR4, RTL8188CU), 289 URTWN_DEV_8192CU(NETWEEN, RTL8192CU), 290 URTWN_DEV_8192CU(NOVATECH, RTL8188CU), 291 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_1), 292 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_2), 293 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_3), 294 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_4), 295 URTWN_DEV_8192CU(PLANEX2, RTL8188CUS), 296 URTWN_DEV_8192CU(PLANEX2, RTL8192CU), 297 URTWN_DEV_8192CU(REALTEK, RTL8188CE_0), 298 URTWN_DEV_8192CU(REALTEK, RTL8188CE_1), 299 URTWN_DEV_8192CU(REALTEK, RTL8188CTV), 300 URTWN_DEV_8192CU(REALTEK, RTL8188CU_0), 301 URTWN_DEV_8192CU(REALTEK, RTL8188CU_1), 302 URTWN_DEV_8192CU(REALTEK, RTL8188CU_2), 303 URTWN_DEV_8192CU(REALTEK, RTL8188CU_3), 304 URTWN_DEV_8192CU(REALTEK, RTL8188CU_4), 305 URTWN_DEV_8192CU(REALTEK, RTL8188CU_5), 306 URTWN_DEV_8192CU(REALTEK, RTL8188CU_COMBO), 307 URTWN_DEV_8192CU(REALTEK, RTL8188CUS), 308 URTWN_DEV_8192CU(REALTEK, RTL8188RU), 309 URTWN_DEV_8192CU(REALTEK, RTL8188RU_2), 310 URTWN_DEV_8192CU(REALTEK, RTL8188RU_3), 311 URTWN_DEV_8192CU(REALTEK, RTL8191CU), 312 URTWN_DEV_8192CU(REALTEK, RTL8192CE), 313 URTWN_DEV_8192CU(REALTEK, RTL8192CE_VAU), 314 URTWN_DEV_8192CU(REALTEK, RTL8192CU), 315 URTWN_DEV_8192CU(SITECOMEU, RTL8188CU), 316 URTWN_DEV_8192CU(SITECOMEU, RTL8188CU_2), 317 URTWN_DEV_8192CU(SITECOMEU, RTL8192CU), 318 URTWN_DEV_8192CU(SITECOMEU, RTL8192CU_2), 319 URTWN_DEV_8192CU(SITECOMEU, WLA2100V2), 320 URTWN_DEV_8192CU(TPLINK, RTL8192CU), 321 URTWN_DEV_8192CU(TRENDNET, RTL8188CU), 322 URTWN_DEV_8192CU(TRENDNET, RTL8192CU), 323 URTWN_DEV_8192CU(ZYXEL, RTL8192CU), 324 /* URTWN_RTL8188E */ 325 URTWN_DEV_8188EU(ABOCOM, RTL8188EU), 326 URTWN_DEV_8188EU(DLINK, DWA123D1), 327 URTWN_DEV_8188EU(DLINK, DWA125D1), 328 URTWN_DEV_8188EU(ELECOM, WDC150SU2M), 329 URTWN_DEV_8188EU(REALTEK, RTL8188ETV), 330 URTWN_DEV_8188EU(REALTEK, RTL8188EU), 331 URTWN_DEV_8188EU(TPLINK, RTL8188EUS), 332 /* URTWN_RTL8192EU */ 333 URTWN_DEV_8192EU(DLINK, DWA131E1), 334 URTWN_DEV_8192EU(REALTEK, RTL8192EU), 335 URTWN_DEV_8192EU(TPLINK, RTL8192EU) 336 }; 337 338 #define urtwn_lookup(v, p) \ 339 ((const struct urtwn_type *)usb_lookup(urtwn_devs, v, p)) 340 341 int urtwn_match(struct device *, void *, void *); 342 void urtwn_attach(struct device *, struct device *, void *); 343 int urtwn_detach(struct device *, int); 344 int urtwn_open_pipes(struct urtwn_softc *); 345 void urtwn_close_pipes(struct urtwn_softc *); 346 int urtwn_alloc_rx_list(struct urtwn_softc *); 347 void urtwn_free_rx_list(struct urtwn_softc *); 348 int urtwn_alloc_tx_list(struct urtwn_softc *); 349 void urtwn_free_tx_list(struct urtwn_softc *); 350 void urtwn_task(void *); 351 void urtwn_do_async(struct urtwn_softc *, 352 void (*)(struct urtwn_softc *, void *), void *, int); 353 void urtwn_wait_async(void *); 354 int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 355 int); 356 void urtwn_write_1(void *, uint16_t, uint8_t); 357 void urtwn_write_2(void *, uint16_t, uint16_t); 358 void urtwn_write_4(void *, uint16_t, uint32_t); 359 int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 360 int); 361 uint8_t urtwn_read_1(void *, uint16_t); 362 uint16_t urtwn_read_2(void *, uint16_t); 363 uint32_t urtwn_read_4(void *, uint16_t); 364 int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 365 void urtwn_calib_to(void *); 366 void urtwn_calib_cb(struct urtwn_softc *, void *); 367 void urtwn_scan_to(void *); 368 void urtwn_next_scan(void *); 369 void urtwn_cancel_scan(void *); 370 int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 371 int); 372 void urtwn_newstate_cb(struct urtwn_softc *, void *); 373 void urtwn_updateslot(struct ieee80211com *); 374 void urtwn_updateslot_cb(struct urtwn_softc *, void *); 375 void urtwn_updateedca(struct ieee80211com *); 376 void urtwn_updateedca_cb(struct urtwn_softc *, void *); 377 int urtwn_set_key(struct ieee80211com *, struct ieee80211_node *, 378 struct ieee80211_key *); 379 void urtwn_set_key_cb(struct urtwn_softc *, void *); 380 void urtwn_delete_key(struct ieee80211com *, 381 struct ieee80211_node *, struct ieee80211_key *); 382 void urtwn_delete_key_cb(struct urtwn_softc *, void *); 383 void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 384 void urtwn_rxeof(struct usbd_xfer *, void *, 385 usbd_status); 386 void urtwn_txeof(struct usbd_xfer *, void *, 387 usbd_status); 388 int urtwn_tx(void *, struct mbuf *, struct ieee80211_node *); 389 int urtwn_ioctl(struct ifnet *, u_long, caddr_t); 390 int urtwn_power_on(void *); 391 int urtwn_alloc_buffers(void *); 392 int urtwn_r92c_power_on(struct urtwn_softc *); 393 int urtwn_r92e_power_on(struct urtwn_softc *); 394 int urtwn_r88e_power_on(struct urtwn_softc *); 395 int urtwn_llt_init(struct urtwn_softc *, int); 396 int urtwn_fw_loadpage(void *, int, uint8_t *, int); 397 int urtwn_load_firmware(void *, u_char **, size_t *); 398 int urtwn_dma_init(void *); 399 void urtwn_aggr_init(void *); 400 void urtwn_mac_init(void *); 401 void urtwn_bb_init(void *); 402 void urtwn_burstlen_init(struct urtwn_softc *); 403 int urtwn_init(void *); 404 void urtwn_stop(void *); 405 int urtwn_is_oactive(void *); 406 void urtwn_next_calib(void *); 407 void urtwn_cancel_calib(void *); 408 409 /* Aliases. */ 410 #define urtwn_bb_write urtwn_write_4 411 #define urtwn_bb_read urtwn_read_4 412 413 struct cfdriver urtwn_cd = { 414 NULL, "urtwn", DV_IFNET 415 }; 416 417 const struct cfattach urtwn_ca = { 418 sizeof(struct urtwn_softc), urtwn_match, urtwn_attach, urtwn_detach 419 }; 420 421 int 422 urtwn_match(struct device *parent, void *match, void *aux) 423 { 424 struct usb_attach_arg *uaa = aux; 425 426 if (uaa->iface == NULL || uaa->configno != 1) 427 return (UMATCH_NONE); 428 429 return ((urtwn_lookup(uaa->vendor, uaa->product) != NULL) ? 430 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 431 } 432 433 void 434 urtwn_attach(struct device *parent, struct device *self, void *aux) 435 { 436 struct urtwn_softc *sc = (struct urtwn_softc *)self; 437 struct usb_attach_arg *uaa = aux; 438 struct ifnet *ifp; 439 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 440 441 sc->sc_udev = uaa->device; 442 sc->sc_iface = uaa->iface; 443 444 sc->sc_sc.chip = urtwn_lookup(uaa->vendor, uaa->product)->chip; 445 446 usb_init_task(&sc->sc_task, urtwn_task, sc, USB_TASK_TYPE_GENERIC); 447 timeout_set(&sc->scan_to, urtwn_scan_to, sc); 448 timeout_set(&sc->calib_to, urtwn_calib_to, sc); 449 if (urtwn_open_pipes(sc) != 0) 450 return; 451 452 sc->amrr.amrr_min_success_threshold = 1; 453 sc->amrr.amrr_max_success_threshold = 10; 454 455 /* Attach the bus-agnostic driver. */ 456 sc->sc_sc.sc_ops.cookie = sc; 457 sc->sc_sc.sc_ops.write_1 = urtwn_write_1; 458 sc->sc_sc.sc_ops.write_2 = urtwn_write_2; 459 sc->sc_sc.sc_ops.write_4 = urtwn_write_4; 460 sc->sc_sc.sc_ops.read_1 = urtwn_read_1; 461 sc->sc_sc.sc_ops.read_2 = urtwn_read_2; 462 sc->sc_sc.sc_ops.read_4 = urtwn_read_4; 463 sc->sc_sc.sc_ops.tx = urtwn_tx; 464 sc->sc_sc.sc_ops.power_on = urtwn_power_on; 465 sc->sc_sc.sc_ops.dma_init = urtwn_dma_init; 466 sc->sc_sc.sc_ops.fw_loadpage = urtwn_fw_loadpage; 467 sc->sc_sc.sc_ops.load_firmware = urtwn_load_firmware; 468 sc->sc_sc.sc_ops.aggr_init = urtwn_aggr_init; 469 sc->sc_sc.sc_ops.mac_init = urtwn_mac_init; 470 sc->sc_sc.sc_ops.bb_init = urtwn_bb_init; 471 sc->sc_sc.sc_ops.alloc_buffers = urtwn_alloc_buffers; 472 sc->sc_sc.sc_ops.init = urtwn_init; 473 sc->sc_sc.sc_ops.stop = urtwn_stop; 474 sc->sc_sc.sc_ops.is_oactive = urtwn_is_oactive; 475 sc->sc_sc.sc_ops.next_calib = urtwn_next_calib; 476 sc->sc_sc.sc_ops.cancel_calib = urtwn_cancel_calib; 477 sc->sc_sc.sc_ops.next_scan = urtwn_next_scan; 478 sc->sc_sc.sc_ops.cancel_scan = urtwn_cancel_scan; 479 sc->sc_sc.sc_ops.wait_async = urtwn_wait_async; 480 if (rtwn_attach(&sc->sc_dev, &sc->sc_sc) != 0) { 481 urtwn_close_pipes(sc); 482 return; 483 } 484 485 /* ifp is now valid */ 486 ifp = &sc->sc_sc.sc_ic.ic_if; 487 ifp->if_ioctl = urtwn_ioctl; 488 489 ic->ic_updateslot = urtwn_updateslot; 490 ic->ic_updateedca = urtwn_updateedca; 491 #ifdef notyet 492 ic->ic_set_key = urtwn_set_key; 493 ic->ic_delete_key = urtwn_delete_key; 494 #endif 495 /* Override state transition machine. */ 496 ic->ic_newstate = urtwn_newstate; 497 498 #if NBPFILTER > 0 499 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 500 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 501 502 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 503 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 504 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 505 506 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 507 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 508 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 509 #endif 510 } 511 512 int 513 urtwn_detach(struct device *self, int flags) 514 { 515 struct urtwn_softc *sc = (struct urtwn_softc *)self; 516 int s; 517 518 s = splusb(); 519 520 if (timeout_initialized(&sc->scan_to)) 521 timeout_del(&sc->scan_to); 522 if (timeout_initialized(&sc->calib_to)) 523 timeout_del(&sc->calib_to); 524 525 /* Wait for all async commands to complete. */ 526 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 527 528 usbd_ref_wait(sc->sc_udev); 529 530 rtwn_detach(&sc->sc_sc, flags); 531 532 /* Abort and close Tx/Rx pipes. */ 533 urtwn_close_pipes(sc); 534 535 /* Free Tx/Rx buffers. */ 536 urtwn_free_tx_list(sc); 537 urtwn_free_rx_list(sc); 538 splx(s); 539 540 return (0); 541 } 542 543 int 544 urtwn_open_pipes(struct urtwn_softc *sc) 545 { 546 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 547 uint8_t epaddr[R92C_MAX_EPOUT] = { 0, 0, 0 }; 548 uint8_t rx_no; 549 usb_interface_descriptor_t *id; 550 usb_endpoint_descriptor_t *ed; 551 int i, error, nrx = 0; 552 553 /* Find all bulk endpoints. */ 554 id = usbd_get_interface_descriptor(sc->sc_iface); 555 for (i = 0; i < id->bNumEndpoints; i++) { 556 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 557 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) 558 continue; 559 560 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 561 rx_no = ed->bEndpointAddress; 562 nrx++; 563 } else { 564 if (sc->ntx < R92C_MAX_EPOUT) 565 epaddr[sc->ntx] = ed->bEndpointAddress; 566 sc->ntx++; 567 } 568 } 569 if (nrx == 0) { 570 printf("%s: %d: invalid number of Rx bulk pipes\n", 571 sc->sc_dev.dv_xname, nrx); 572 return (EIO); 573 } 574 DPRINTF(("found %d bulk-out pipes\n", sc->ntx)); 575 if (sc->ntx == 0 || sc->ntx > R92C_MAX_EPOUT) { 576 printf("%s: %d: invalid number of Tx bulk pipes\n", 577 sc->sc_dev.dv_xname, sc->ntx); 578 return (EIO); 579 } 580 581 /* Open bulk-in pipe. */ 582 error = usbd_open_pipe(sc->sc_iface, rx_no, 0, &sc->rx_pipe); 583 if (error != 0) { 584 printf("%s: could not open Rx bulk pipe\n", 585 sc->sc_dev.dv_xname); 586 goto fail; 587 } 588 589 /* Open bulk-out pipes (up to 3). */ 590 for (i = 0; i < sc->ntx; i++) { 591 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 0, 592 &sc->tx_pipe[i]); 593 if (error != 0) { 594 printf("%s: could not open Tx bulk pipe 0x%02x\n", 595 sc->sc_dev.dv_xname, epaddr[i]); 596 goto fail; 597 } 598 } 599 600 /* Map 802.11 access categories to USB pipes. */ 601 sc->ac2idx[EDCA_AC_BK] = 602 sc->ac2idx[EDCA_AC_BE] = (sc->ntx == 3) ? 2 : ((sc->ntx == 2) ? 1 : 0); 603 sc->ac2idx[EDCA_AC_VI] = (sc->ntx == 3) ? 1 : 0; 604 sc->ac2idx[EDCA_AC_VO] = 0; /* Always use highest prio. */ 605 606 if (error != 0) 607 fail: urtwn_close_pipes(sc); 608 return (error); 609 } 610 611 void 612 urtwn_close_pipes(struct urtwn_softc *sc) 613 { 614 int i; 615 616 /* Close Rx pipe. */ 617 if (sc->rx_pipe != NULL) { 618 usbd_abort_pipe(sc->rx_pipe); 619 usbd_close_pipe(sc->rx_pipe); 620 } 621 /* Close Tx pipes. */ 622 for (i = 0; i < R92C_MAX_EPOUT; i++) { 623 if (sc->tx_pipe[i] == NULL) 624 continue; 625 usbd_abort_pipe(sc->tx_pipe[i]); 626 usbd_close_pipe(sc->tx_pipe[i]); 627 } 628 } 629 630 int 631 urtwn_alloc_rx_list(struct urtwn_softc *sc) 632 { 633 struct urtwn_rx_data *data; 634 int i, error = 0; 635 636 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 637 data = &sc->rx_data[i]; 638 639 data->sc = sc; /* Backpointer for callbacks. */ 640 641 data->xfer = usbd_alloc_xfer(sc->sc_udev); 642 if (data->xfer == NULL) { 643 printf("%s: could not allocate xfer\n", 644 sc->sc_dev.dv_xname); 645 error = ENOMEM; 646 break; 647 } 648 data->buf = usbd_alloc_buffer(data->xfer, URTWN_RXBUFSZ); 649 if (data->buf == NULL) { 650 printf("%s: could not allocate xfer buffer\n", 651 sc->sc_dev.dv_xname); 652 error = ENOMEM; 653 break; 654 } 655 } 656 if (error != 0) 657 urtwn_free_rx_list(sc); 658 return (error); 659 } 660 661 void 662 urtwn_free_rx_list(struct urtwn_softc *sc) 663 { 664 int i; 665 666 /* NB: Caller must abort pipe first. */ 667 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 668 if (sc->rx_data[i].xfer != NULL) 669 usbd_free_xfer(sc->rx_data[i].xfer); 670 sc->rx_data[i].xfer = NULL; 671 } 672 } 673 674 int 675 urtwn_alloc_tx_list(struct urtwn_softc *sc) 676 { 677 struct urtwn_tx_data *data; 678 int i, error = 0; 679 680 TAILQ_INIT(&sc->tx_free_list); 681 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 682 data = &sc->tx_data[i]; 683 684 data->sc = sc; /* Backpointer for callbacks. */ 685 686 data->xfer = usbd_alloc_xfer(sc->sc_udev); 687 if (data->xfer == NULL) { 688 printf("%s: could not allocate xfer\n", 689 sc->sc_dev.dv_xname); 690 error = ENOMEM; 691 break; 692 } 693 data->buf = usbd_alloc_buffer(data->xfer, URTWN_TXBUFSZ); 694 if (data->buf == NULL) { 695 printf("%s: could not allocate xfer buffer\n", 696 sc->sc_dev.dv_xname); 697 error = ENOMEM; 698 break; 699 } 700 /* Append this Tx buffer to our free list. */ 701 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 702 } 703 if (error != 0) 704 urtwn_free_tx_list(sc); 705 return (error); 706 } 707 708 void 709 urtwn_free_tx_list(struct urtwn_softc *sc) 710 { 711 int i; 712 713 /* NB: Caller must abort pipe first. */ 714 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 715 if (sc->tx_data[i].xfer != NULL) 716 usbd_free_xfer(sc->tx_data[i].xfer); 717 sc->tx_data[i].xfer = NULL; 718 } 719 } 720 721 void 722 urtwn_task(void *arg) 723 { 724 struct urtwn_softc *sc = arg; 725 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 726 struct urtwn_host_cmd *cmd; 727 int s; 728 729 /* Process host commands. */ 730 s = splusb(); 731 while (ring->next != ring->cur) { 732 cmd = &ring->cmd[ring->next]; 733 splx(s); 734 /* Invoke callback. */ 735 cmd->cb(sc, cmd->data); 736 s = splusb(); 737 ring->queued--; 738 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 739 } 740 splx(s); 741 } 742 743 void 744 urtwn_do_async(struct urtwn_softc *sc, 745 void (*cb)(struct urtwn_softc *, void *), void *arg, int len) 746 { 747 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 748 struct urtwn_host_cmd *cmd; 749 int s; 750 751 s = splusb(); 752 cmd = &ring->cmd[ring->cur]; 753 cmd->cb = cb; 754 KASSERT(len <= sizeof(cmd->data)); 755 memcpy(cmd->data, arg, len); 756 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 757 758 /* If there is no pending command already, schedule a task. */ 759 if (++ring->queued == 1) 760 usb_add_task(sc->sc_udev, &sc->sc_task); 761 splx(s); 762 } 763 764 void 765 urtwn_wait_async(void *cookie) 766 { 767 struct urtwn_softc *sc = cookie; 768 int s; 769 770 s = splusb(); 771 /* Wait for all queued asynchronous commands to complete. */ 772 usb_wait_task(sc->sc_udev, &sc->sc_task); 773 splx(s); 774 } 775 776 int 777 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 778 int len) 779 { 780 usb_device_request_t req; 781 782 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 783 req.bRequest = R92C_REQ_REGS; 784 USETW(req.wValue, addr); 785 USETW(req.wIndex, 0); 786 USETW(req.wLength, len); 787 return (usbd_do_request(sc->sc_udev, &req, buf)); 788 } 789 790 void 791 urtwn_write_1(void *cookie, uint16_t addr, uint8_t val) 792 { 793 struct urtwn_softc *sc = cookie; 794 795 urtwn_write_region_1(sc, addr, &val, 1); 796 } 797 798 void 799 urtwn_write_2(void *cookie, uint16_t addr, uint16_t val) 800 { 801 struct urtwn_softc *sc = cookie; 802 803 val = htole16(val); 804 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 805 } 806 807 void 808 urtwn_write_4(void *cookie, uint16_t addr, uint32_t val) 809 { 810 struct urtwn_softc *sc = cookie; 811 812 val = htole32(val); 813 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 814 } 815 816 int 817 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 818 int len) 819 { 820 usb_device_request_t req; 821 822 req.bmRequestType = UT_READ_VENDOR_DEVICE; 823 req.bRequest = R92C_REQ_REGS; 824 USETW(req.wValue, addr); 825 USETW(req.wIndex, 0); 826 USETW(req.wLength, len); 827 return (usbd_do_request(sc->sc_udev, &req, buf)); 828 } 829 830 uint8_t 831 urtwn_read_1(void *cookie, uint16_t addr) 832 { 833 struct urtwn_softc *sc = cookie; 834 uint8_t val; 835 836 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 837 return (0xff); 838 return (val); 839 } 840 841 uint16_t 842 urtwn_read_2(void *cookie, uint16_t addr) 843 { 844 struct urtwn_softc *sc = cookie; 845 uint16_t val; 846 847 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 848 return (0xffff); 849 return (letoh16(val)); 850 } 851 852 uint32_t 853 urtwn_read_4(void *cookie, uint16_t addr) 854 { 855 struct urtwn_softc *sc = cookie; 856 uint32_t val; 857 858 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 859 return (0xffffffff); 860 return (letoh32(val)); 861 } 862 863 int 864 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 865 { 866 int ntries; 867 868 urtwn_write_4(sc, R92C_LLT_INIT, 869 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 870 SM(R92C_LLT_INIT_ADDR, addr) | 871 SM(R92C_LLT_INIT_DATA, data)); 872 /* Wait for write operation to complete. */ 873 for (ntries = 0; ntries < 20; ntries++) { 874 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 875 R92C_LLT_INIT_OP_NO_ACTIVE) 876 return (0); 877 DELAY(5); 878 } 879 return (ETIMEDOUT); 880 } 881 882 void 883 urtwn_calib_to(void *arg) 884 { 885 struct urtwn_softc *sc = arg; 886 887 if (usbd_is_dying(sc->sc_udev)) 888 return; 889 890 usbd_ref_incr(sc->sc_udev); 891 892 /* Do it in a process context. */ 893 urtwn_do_async(sc, urtwn_calib_cb, NULL, 0); 894 895 usbd_ref_decr(sc->sc_udev); 896 } 897 898 /* ARGSUSED */ 899 void 900 urtwn_calib_cb(struct urtwn_softc *sc, void *arg) 901 { 902 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 903 int s; 904 905 s = splnet(); 906 if (ic->ic_opmode == IEEE80211_M_STA) { 907 ieee80211_amrr_choose(&sc->amrr, ic->ic_bss, &sc->amn); 908 } 909 splx(s); 910 911 rtwn_calib(&sc->sc_sc); 912 } 913 914 void 915 urtwn_next_calib(void *cookie) 916 { 917 struct urtwn_softc *sc = cookie; 918 919 if (!usbd_is_dying(sc->sc_udev)) 920 timeout_add_sec(&sc->calib_to, 2); 921 } 922 923 void 924 urtwn_cancel_calib(void *cookie) 925 { 926 struct urtwn_softc *sc = cookie; 927 928 if (timeout_initialized(&sc->calib_to)) 929 timeout_del(&sc->calib_to); 930 } 931 932 void 933 urtwn_scan_to(void *arg) 934 { 935 struct urtwn_softc *sc = arg; 936 937 if (usbd_is_dying(sc->sc_udev)) 938 return; 939 940 usbd_ref_incr(sc->sc_udev); 941 rtwn_next_scan(&sc->sc_sc); 942 usbd_ref_decr(sc->sc_udev); 943 } 944 945 void 946 urtwn_next_scan(void *arg) 947 { 948 struct urtwn_softc *sc = arg; 949 950 if (!usbd_is_dying(sc->sc_udev)) 951 timeout_add_msec(&sc->scan_to, 200); 952 } 953 954 void 955 urtwn_cancel_scan(void *cookie) 956 { 957 struct urtwn_softc *sc = cookie; 958 959 if (timeout_initialized(&sc->scan_to)) 960 timeout_del(&sc->scan_to); 961 } 962 963 int 964 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 965 { 966 struct rtwn_softc *sc_sc = ic->ic_softc; 967 struct device *self = sc_sc->sc_pdev; 968 struct urtwn_softc *sc = (struct urtwn_softc *)self; 969 struct urtwn_cmd_newstate cmd; 970 971 /* Do it in a process context. */ 972 cmd.state = nstate; 973 cmd.arg = arg; 974 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 975 return (0); 976 } 977 978 void 979 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 980 { 981 struct urtwn_cmd_newstate *cmd = arg; 982 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 983 984 rtwn_newstate(ic, cmd->state, cmd->arg); 985 } 986 987 void 988 urtwn_updateslot(struct ieee80211com *ic) 989 { 990 struct rtwn_softc *sc_sc = ic->ic_softc; 991 struct device *self = sc_sc->sc_pdev; 992 struct urtwn_softc *sc = (struct urtwn_softc *)self; 993 994 /* Do it in a process context. */ 995 urtwn_do_async(sc, urtwn_updateslot_cb, NULL, 0); 996 } 997 998 /* ARGSUSED */ 999 void 1000 urtwn_updateslot_cb(struct urtwn_softc *sc, void *arg) 1001 { 1002 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1003 1004 rtwn_updateslot(ic); 1005 } 1006 1007 void 1008 urtwn_updateedca(struct ieee80211com *ic) 1009 { 1010 struct rtwn_softc *sc_sc = ic->ic_softc; 1011 struct device *self = sc_sc->sc_pdev; 1012 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1013 1014 /* Do it in a process context. */ 1015 urtwn_do_async(sc, urtwn_updateedca_cb, NULL, 0); 1016 } 1017 1018 /* ARGSUSED */ 1019 void 1020 urtwn_updateedca_cb(struct urtwn_softc *sc, void *arg) 1021 { 1022 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1023 1024 rtwn_updateedca(ic); 1025 } 1026 1027 int 1028 urtwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1029 struct ieee80211_key *k) 1030 { 1031 struct rtwn_softc *sc_sc = ic->ic_softc; 1032 struct device *self = sc_sc->sc_pdev; 1033 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1034 struct urtwn_cmd_key cmd; 1035 1036 /* Defer setting of WEP keys until interface is brought up. */ 1037 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 1038 (IFF_UP | IFF_RUNNING)) 1039 return (0); 1040 1041 /* Do it in a process context. */ 1042 cmd.key = *k; 1043 cmd.ni = ni; 1044 urtwn_do_async(sc, urtwn_set_key_cb, &cmd, sizeof(cmd)); 1045 return (0); 1046 } 1047 1048 void 1049 urtwn_set_key_cb(struct urtwn_softc *sc, void *arg) 1050 { 1051 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1052 struct urtwn_cmd_key *cmd = arg; 1053 1054 rtwn_set_key(ic, cmd->ni, &cmd->key); 1055 } 1056 1057 void 1058 urtwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1059 struct ieee80211_key *k) 1060 { 1061 struct rtwn_softc *sc_sc = ic->ic_softc; 1062 struct device *self = sc_sc->sc_pdev; 1063 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1064 struct urtwn_cmd_key cmd; 1065 1066 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 1067 ic->ic_state != IEEE80211_S_RUN) 1068 return; /* Nothing to do. */ 1069 1070 /* Do it in a process context. */ 1071 cmd.key = *k; 1072 cmd.ni = ni; 1073 urtwn_do_async(sc, urtwn_delete_key_cb, &cmd, sizeof(cmd)); 1074 } 1075 1076 void 1077 urtwn_delete_key_cb(struct urtwn_softc *sc, void *arg) 1078 { 1079 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1080 struct urtwn_cmd_key *cmd = arg; 1081 1082 rtwn_delete_key(ic, cmd->ni, &cmd->key); 1083 } 1084 1085 void 1086 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 1087 { 1088 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1089 struct ifnet *ifp = &ic->ic_if; 1090 struct ieee80211_rxinfo rxi; 1091 struct ieee80211_frame *wh; 1092 struct ieee80211_node *ni; 1093 struct r92c_rx_desc_usb *rxd; 1094 uint32_t rxdw0, rxdw3; 1095 struct mbuf *m; 1096 uint8_t rate; 1097 int8_t rssi = 0; 1098 int s, infosz; 1099 1100 rxd = (struct r92c_rx_desc_usb *)buf; 1101 rxdw0 = letoh32(rxd->rxdw0); 1102 rxdw3 = letoh32(rxd->rxdw3); 1103 1104 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1105 /* 1106 * This should not happen since we setup our Rx filter 1107 * to not receive these frames. 1108 */ 1109 ifp->if_ierrors++; 1110 return; 1111 } 1112 if (__predict_false(pktlen < sizeof(*wh) || pktlen > MCLBYTES)) { 1113 ifp->if_ierrors++; 1114 return; 1115 } 1116 1117 rate = MS(rxdw3, R92C_RXDW3_RATE); 1118 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1119 1120 /* Get RSSI from PHY status descriptor if present. */ 1121 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1122 rssi = rtwn_get_rssi(&sc->sc_sc, rate, &rxd[1]); 1123 /* Update our average RSSI. */ 1124 rtwn_update_avgrssi(&sc->sc_sc, rate, rssi); 1125 } 1126 1127 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 1128 pktlen, rate, infosz, rssi)); 1129 1130 MGETHDR(m, M_DONTWAIT, MT_DATA); 1131 if (__predict_false(m == NULL)) { 1132 ifp->if_ierrors++; 1133 return; 1134 } 1135 if (pktlen > MHLEN) { 1136 MCLGET(m, M_DONTWAIT); 1137 if (__predict_false(!(m->m_flags & M_EXT))) { 1138 ifp->if_ierrors++; 1139 m_freem(m); 1140 return; 1141 } 1142 } 1143 /* Finalize mbuf. */ 1144 wh = (struct ieee80211_frame *)((uint8_t *)&rxd[1] + infosz); 1145 memcpy(mtod(m, uint8_t *), wh, pktlen); 1146 m->m_pkthdr.len = m->m_len = pktlen; 1147 1148 s = splnet(); 1149 #if NBPFILTER > 0 1150 if (__predict_false(sc->sc_drvbpf != NULL)) { 1151 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1152 struct mbuf mb; 1153 1154 tap->wr_flags = 0; 1155 /* Map HW rate index to 802.11 rate. */ 1156 if (!(rxdw3 & R92C_RXDW3_HT)) { 1157 switch (rate) { 1158 /* CCK. */ 1159 case 0: tap->wr_rate = 2; break; 1160 case 1: tap->wr_rate = 4; break; 1161 case 2: tap->wr_rate = 11; break; 1162 case 3: tap->wr_rate = 22; break; 1163 /* OFDM. */ 1164 case 4: tap->wr_rate = 12; break; 1165 case 5: tap->wr_rate = 18; break; 1166 case 6: tap->wr_rate = 24; break; 1167 case 7: tap->wr_rate = 36; break; 1168 case 8: tap->wr_rate = 48; break; 1169 case 9: tap->wr_rate = 72; break; 1170 case 10: tap->wr_rate = 96; break; 1171 case 11: tap->wr_rate = 108; break; 1172 } 1173 if (rate <= 3) 1174 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1175 } else if (rate >= 12) { /* MCS0~15. */ 1176 /* Bit 7 set means HT MCS instead of rate. */ 1177 tap->wr_rate = 0x80 | (rate - 12); 1178 } 1179 tap->wr_dbm_antsignal = rssi; 1180 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1181 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1182 1183 mb.m_data = (caddr_t)tap; 1184 mb.m_len = sc->sc_rxtap_len; 1185 mb.m_next = m; 1186 mb.m_nextpkt = NULL; 1187 mb.m_type = 0; 1188 mb.m_flags = 0; 1189 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1190 } 1191 #endif 1192 1193 ni = ieee80211_find_rxnode(ic, wh); 1194 rxi.rxi_flags = 0; 1195 rxi.rxi_rssi = rssi; 1196 rxi.rxi_tstamp = 0; /* Unused. */ 1197 ieee80211_input(ifp, m, ni, &rxi); 1198 /* Node is no longer needed. */ 1199 ieee80211_release_node(ic, ni); 1200 splx(s); 1201 } 1202 1203 void 1204 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, 1205 usbd_status status) 1206 { 1207 struct urtwn_rx_data *data = priv; 1208 struct urtwn_softc *sc = data->sc; 1209 struct r92c_rx_desc_usb *rxd; 1210 uint32_t rxdw0; 1211 uint8_t *buf; 1212 int len, totlen, pktlen, infosz, npkts, error, align; 1213 1214 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1215 DPRINTF(("RX status=%d\n", status)); 1216 if (status == USBD_STALLED) 1217 usbd_clear_endpoint_stall_async(sc->rx_pipe); 1218 if (status != USBD_CANCELLED) 1219 goto resubmit; 1220 return; 1221 } 1222 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 1223 1224 if (__predict_false(len < sizeof(*rxd))) { 1225 DPRINTF(("xfer too short %d\n", len)); 1226 goto resubmit; 1227 } 1228 buf = data->buf; 1229 1230 /* Get the number of encapsulated frames. */ 1231 rxd = (struct r92c_rx_desc_usb *)buf; 1232 npkts = MS(letoh32(rxd->rxdw2), R92C_RXDW2_PKTCNT); 1233 DPRINTFN(4, ("Rx %d frames in one chunk\n", npkts)); 1234 1235 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1236 int ntries, type; 1237 struct r88e_tx_rpt_ccx *rxstat; 1238 1239 type = MS(letoh32(rxd->rxdw3), R88E_RXDW3_RPT); 1240 1241 if (type == R88E_RXDW3_RPT_TX1) { 1242 buf += sizeof(struct r92c_rx_desc_usb); 1243 rxstat = (struct r88e_tx_rpt_ccx *)buf; 1244 ntries = MS(letoh32(rxstat->rptb2), 1245 R88E_RPTB2_RETRY_CNT); 1246 1247 if (rxstat->rptb1 & R88E_RPTB1_PKT_OK) 1248 sc->amn.amn_txcnt++; 1249 if (ntries > 0) 1250 sc->amn.amn_retrycnt++; 1251 1252 goto resubmit; 1253 } 1254 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 1255 int type; 1256 struct r92e_c2h_tx_rpt *txrpt; 1257 1258 if (letoh32(rxd->rxdw2) & R92E_RXDW2_RPT_C2H) { 1259 if (len < sizeof(struct r92c_rx_desc_usb) + 2) 1260 goto resubmit; 1261 1262 type = buf[sizeof(struct r92c_rx_desc_usb)]; 1263 switch (type) { 1264 case R92C_C2HEVT_TX_REPORT: 1265 buf += sizeof(struct r92c_rx_desc_usb) + 2; 1266 txrpt = (struct r92e_c2h_tx_rpt *)buf; 1267 if (MS(txrpt->rptb2, R92E_RPTB2_RETRY_CNT) > 0) 1268 sc->amn.amn_retrycnt++; 1269 if ((txrpt->rptb0 & (R92E_RPTB0_RETRY_OVER | 1270 R92E_RPTB0_LIFE_EXPIRE)) == 0) 1271 sc->amn.amn_txcnt++; 1272 break; 1273 default: 1274 break; 1275 } 1276 goto resubmit; 1277 } 1278 } 1279 1280 align = (sc->sc_sc.chip & RTWN_CHIP_92E ? 7 : 127); 1281 1282 /* Process all of them. */ 1283 while (npkts-- > 0) { 1284 if (__predict_false(len < sizeof(*rxd))) 1285 break; 1286 rxd = (struct r92c_rx_desc_usb *)buf; 1287 rxdw0 = letoh32(rxd->rxdw0); 1288 1289 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1290 if (__predict_false(pktlen == 0)) 1291 break; 1292 1293 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1294 1295 /* Make sure everything fits in xfer. */ 1296 totlen = sizeof(*rxd) + infosz + pktlen; 1297 if (__predict_false(totlen > len)) 1298 break; 1299 1300 /* Process 802.11 frame. */ 1301 urtwn_rx_frame(sc, buf, pktlen); 1302 1303 /* Handle chunk alignment. */ 1304 totlen = (totlen + align) & ~align; 1305 buf += totlen; 1306 len -= totlen; 1307 } 1308 1309 resubmit: 1310 /* Setup a new transfer. */ 1311 usbd_setup_xfer(xfer, sc->rx_pipe, data, data->buf, URTWN_RXBUFSZ, 1312 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, urtwn_rxeof); 1313 error = usbd_transfer(data->xfer); 1314 if (error != 0 && error != USBD_IN_PROGRESS) 1315 DPRINTF(("could not set up new transfer: %d\n", error)); 1316 } 1317 1318 void 1319 urtwn_txeof(struct usbd_xfer *xfer, void *priv, 1320 usbd_status status) 1321 { 1322 struct urtwn_tx_data *data = priv; 1323 struct urtwn_softc *sc = data->sc; 1324 struct ifnet *ifp = &sc->sc_sc.sc_ic.ic_if; 1325 int s; 1326 1327 s = splnet(); 1328 /* Put this Tx buffer back to our free list. */ 1329 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1330 1331 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1332 DPRINTF(("TX status=%d\n", status)); 1333 if (status == USBD_STALLED) 1334 usbd_clear_endpoint_stall_async(data->pipe); 1335 ifp->if_oerrors++; 1336 splx(s); 1337 return; 1338 } 1339 sc->sc_sc.sc_tx_timer = 0; 1340 1341 /* We just released a Tx buffer, notify Tx. */ 1342 if (ifq_is_oactive(&ifp->if_snd)) { 1343 ifq_clr_oactive(&ifp->if_snd); 1344 rtwn_start(ifp); 1345 } 1346 splx(s); 1347 } 1348 1349 void 1350 urtwn_tx_fill_desc(struct urtwn_softc *sc, uint8_t **txdp, struct mbuf *m, 1351 struct ieee80211_frame *wh, struct ieee80211_key *k, 1352 struct ieee80211_node *ni) 1353 { 1354 struct r92c_tx_desc_usb *txd; 1355 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1356 uint8_t raid, type; 1357 1358 txd = (struct r92c_tx_desc_usb *)*txdp; 1359 (*txdp) += sizeof(*txd); 1360 memset(txd, 0, sizeof(*txd)); 1361 1362 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1363 1364 txd->txdw0 |= htole32( 1365 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 1366 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1367 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1368 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1369 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1370 1371 #ifdef notyet 1372 if (k != NULL) { 1373 switch (k->k_cipher) { 1374 case IEEE80211_CIPHER_WEP40: 1375 case IEEE80211_CIPHER_WEP104: 1376 case IEEE80211_CIPHER_TKIP: 1377 cipher = R92C_TXDW1_CIPHER_RC4; 1378 break; 1379 case IEEE80211_CIPHER_CCMP: 1380 cipher = R92C_TXDW1_CIPHER_AES; 1381 break; 1382 default: 1383 cipher = R92C_TXDW1_CIPHER_NONE; 1384 } 1385 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 1386 } 1387 #endif 1388 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1389 type == IEEE80211_FC0_TYPE_DATA) { 1390 if (ic->ic_curmode == IEEE80211_MODE_11B || 1391 (sc->sc_sc.sc_flags & RTWN_FLAG_FORCE_RAID_11B)) 1392 raid = R92C_RAID_11B; 1393 else 1394 raid = R92C_RAID_11BG; 1395 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1396 txd->txdw1 |= htole32( 1397 SM(R88E_TXDW1_MACID, R92C_MACID_BSS) | 1398 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1399 SM(R92C_TXDW1_RAID, raid)); 1400 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1401 /* Request TX status report for AMRR */ 1402 txd->txdw2 |= htole32(R92C_TXDW2_CCX_RPT); 1403 } else { 1404 txd->txdw1 |= htole32( 1405 SM(R92C_TXDW1_MACID, R92C_MACID_BSS) | 1406 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1407 SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1408 } 1409 1410 if (m->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 1411 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1412 R92C_TXDW4_HWRTSEN); 1413 } else if (ic->ic_flags & IEEE80211_F_USEPROT) { 1414 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1415 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1416 R92C_TXDW4_HWRTSEN); 1417 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1418 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1419 R92C_TXDW4_HWRTSEN); 1420 } 1421 } 1422 txd->txdw5 |= htole32(0x0001ff00); 1423 1424 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1425 /* Use AMRR */ 1426 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1427 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 1428 ni->ni_txrate)); 1429 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1430 ni->ni_txrate)); 1431 } else { 1432 /* Send RTS at OFDM24 and data at OFDM54. */ 1433 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1434 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1435 } 1436 } else { 1437 txd->txdw1 |= htole32( 1438 SM(R92C_TXDW1_MACID, 0) | 1439 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1440 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1441 1442 /* Force CCK1. */ 1443 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1444 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1445 } 1446 /* Set sequence number (already little endian). */ 1447 txd->txdseq |= (*(uint16_t *)wh->i_seq) >> IEEE80211_SEQ_SEQ_SHIFT; 1448 1449 if (!ieee80211_has_qos(wh)) { 1450 /* Use HW sequence numbering for non-QoS frames. */ 1451 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1452 txd->txdseq |= htole16(R92C_TXDW3_HWSEQEN); 1453 } else 1454 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1455 } 1456 1457 void 1458 urtwn_tx_fill_desc_gen2(struct urtwn_softc *sc, uint8_t **txdp, struct mbuf *m, 1459 struct ieee80211_frame *wh, struct ieee80211_key *k, 1460 struct ieee80211_node *ni) 1461 { 1462 struct r92e_tx_desc_usb *txd; 1463 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1464 uint8_t raid, type; 1465 1466 txd = (struct r92e_tx_desc_usb *)*txdp; 1467 (*txdp) += sizeof(*txd); 1468 memset(txd, 0, sizeof(*txd)); 1469 1470 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1471 1472 txd->txdw0 |= htole32( 1473 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 1474 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1475 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1476 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1477 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1478 1479 #ifdef notyet 1480 /* cipher */ 1481 #endif 1482 1483 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1484 type == IEEE80211_FC0_TYPE_DATA) { 1485 if (ic->ic_curmode == IEEE80211_MODE_11B || 1486 (sc->sc_sc.sc_flags & RTWN_FLAG_FORCE_RAID_11B)) 1487 raid = R92E_RAID_11B; 1488 else 1489 raid = R92E_RAID_11BG; 1490 txd->txdw1 |= htole32( 1491 SM(R92E_TXDW1_MACID, R92C_MACID_BSS) | 1492 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1493 SM(R92C_TXDW1_RAID, raid)); 1494 /* Request TX status report for AMRR */ 1495 txd->txdw2 |= htole32(R92C_TXDW2_CCX_RPT | R88E_TXDW2_AGGBK); 1496 1497 if (m->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 1498 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1499 R92C_TXDW4_HWRTSEN); 1500 } else if (ic->ic_flags & IEEE80211_F_USEPROT) { 1501 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1502 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1503 R92C_TXDW4_HWRTSEN); 1504 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1505 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1506 R92C_TXDW4_HWRTSEN); 1507 } 1508 } 1509 txd->txdw5 |= htole32(0x0001ff00); 1510 1511 /* Use AMRR */ 1512 txd->txdw3 |= htole32(R92E_TXDW3_DRVRATE); 1513 txd->txdw4 |= htole32(SM(R92E_TXDW4_RTSRATE, ni->ni_txrate)); 1514 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATE, ni->ni_txrate)); 1515 } else { 1516 txd->txdw1 |= htole32( 1517 SM(R92E_TXDW1_MACID, 0) | 1518 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1519 SM(R92C_TXDW1_RAID, R92E_RAID_11B)); 1520 1521 /* Force CCK1. */ 1522 txd->txdw3 |= htole32(R92E_TXDW3_DRVRATE); 1523 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATE, 0)); 1524 } 1525 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATEFB, 0x1f)); 1526 1527 txd->txdseq2 |= htole16(SM(R92E_TXDSEQ2_HWSEQ, *(uint16_t *)wh->i_seq)); 1528 1529 if (!ieee80211_has_qos(wh)) { 1530 /* Use HW sequence numbering for non-QoS frames. */ 1531 txd->txdw7 |= htole16(R92C_TXDW3_HWSEQEN); 1532 } 1533 } 1534 1535 int 1536 urtwn_tx(void *cookie, struct mbuf *m, struct ieee80211_node *ni) 1537 { 1538 struct urtwn_softc *sc = cookie; 1539 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1540 struct ieee80211_frame *wh; 1541 struct ieee80211_key *k = NULL; 1542 struct urtwn_tx_data *data; 1543 struct usbd_pipe *pipe; 1544 uint16_t qos, sum; 1545 uint8_t tid, qid; 1546 int i, xferlen, error; 1547 uint8_t *txdp; 1548 1549 wh = mtod(m, struct ieee80211_frame *); 1550 1551 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1552 k = ieee80211_get_txkey(ic, wh, ni); 1553 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1554 return (ENOBUFS); 1555 wh = mtod(m, struct ieee80211_frame *); 1556 } 1557 1558 if (ieee80211_has_qos(wh)) { 1559 qos = ieee80211_get_qos(wh); 1560 tid = qos & IEEE80211_QOS_TID; 1561 qid = ieee80211_up_to_ac(ic, tid); 1562 } else if ((wh->i_fc[1] & IEEE80211_FC0_TYPE_MASK) 1563 != IEEE80211_FC0_TYPE_DATA) { 1564 /* Use AC VO for management frames. */ 1565 qid = EDCA_AC_VO; 1566 } else 1567 qid = EDCA_AC_BE; 1568 1569 /* Get the USB pipe to use for this AC. */ 1570 pipe = sc->tx_pipe[sc->ac2idx[qid]]; 1571 1572 /* Grab a Tx buffer from our free list. */ 1573 data = TAILQ_FIRST(&sc->tx_free_list); 1574 TAILQ_REMOVE(&sc->tx_free_list, data, next); 1575 1576 /* Fill Tx descriptor. */ 1577 txdp = data->buf; 1578 if (sc->sc_sc.chip & RTWN_CHIP_92E) 1579 urtwn_tx_fill_desc_gen2(sc, &txdp, m, wh, k, ni); 1580 else 1581 urtwn_tx_fill_desc(sc, &txdp, m, wh, k, ni); 1582 1583 /* Compute Tx descriptor checksum. */ 1584 sum = 0; 1585 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 1586 sum ^= ((uint16_t *)data->buf)[i]; 1587 ((uint16_t *)data->buf)[R92C_TXDESC_SUMOFFSET] = sum; 1588 1589 #if NBPFILTER > 0 1590 if (__predict_false(sc->sc_drvbpf != NULL)) { 1591 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1592 struct mbuf mb; 1593 1594 tap->wt_flags = 0; 1595 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1596 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1597 1598 mb.m_data = (caddr_t)tap; 1599 mb.m_len = sc->sc_txtap_len; 1600 mb.m_next = m; 1601 mb.m_nextpkt = NULL; 1602 mb.m_type = 0; 1603 mb.m_flags = 0; 1604 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1605 } 1606 #endif 1607 1608 xferlen = (txdp - data->buf) + m->m_pkthdr.len; 1609 m_copydata(m, 0, m->m_pkthdr.len, txdp); 1610 m_freem(m); 1611 1612 data->pipe = pipe; 1613 usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen, 1614 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTWN_TX_TIMEOUT, 1615 urtwn_txeof); 1616 error = usbd_transfer(data->xfer); 1617 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) { 1618 /* Put this Tx buffer back to our free list. */ 1619 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1620 return (error); 1621 } 1622 ieee80211_release_node(ic, ni); 1623 return (0); 1624 } 1625 1626 int 1627 urtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1628 { 1629 struct rtwn_softc *sc_sc = ifp->if_softc; 1630 struct device *self = sc_sc->sc_pdev; 1631 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1632 int error; 1633 1634 if (usbd_is_dying(sc->sc_udev)) 1635 return ENXIO; 1636 1637 usbd_ref_incr(sc->sc_udev); 1638 error = rtwn_ioctl(ifp, cmd, data); 1639 usbd_ref_decr(sc->sc_udev); 1640 1641 return (error); 1642 } 1643 1644 int 1645 urtwn_r92c_power_on(struct urtwn_softc *sc) 1646 { 1647 uint32_t reg; 1648 int ntries; 1649 1650 /* Wait for autoload done bit. */ 1651 for (ntries = 0; ntries < 1000; ntries++) { 1652 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 1653 break; 1654 DELAY(5); 1655 } 1656 if (ntries == 1000) { 1657 printf("%s: timeout waiting for chip autoload\n", 1658 sc->sc_dev.dv_xname); 1659 return (ETIMEDOUT); 1660 } 1661 1662 /* Unlock ISO/CLK/Power control register. */ 1663 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 1664 /* Move SPS into PWM mode. */ 1665 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 1666 DELAY(100); 1667 1668 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 1669 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 1670 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 1671 reg | R92C_LDOV12D_CTRL_LDV12_EN); 1672 DELAY(100); 1673 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 1674 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 1675 ~R92C_SYS_ISO_CTRL_MD2PP); 1676 } 1677 1678 /* Auto enable WLAN. */ 1679 urtwn_write_2(sc, R92C_APS_FSMCO, 1680 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1681 for (ntries = 0; ntries < 1000; ntries++) { 1682 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1683 R92C_APS_FSMCO_APFM_ONMAC)) 1684 break; 1685 DELAY(5); 1686 } 1687 if (ntries == 1000) { 1688 printf("%s: timeout waiting for MAC auto ON\n", 1689 sc->sc_dev.dv_xname); 1690 return (ETIMEDOUT); 1691 } 1692 1693 /* Enable radio, GPIO and LED functions. */ 1694 urtwn_write_2(sc, R92C_APS_FSMCO, 1695 R92C_APS_FSMCO_AFSM_HSUS | 1696 R92C_APS_FSMCO_PDN_EN | 1697 R92C_APS_FSMCO_PFM_ALDN); 1698 /* Release RF digital isolation. */ 1699 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1700 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 1701 1702 /* Initialize MAC. */ 1703 urtwn_write_1(sc, R92C_APSD_CTRL, 1704 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 1705 for (ntries = 0; ntries < 200; ntries++) { 1706 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 1707 R92C_APSD_CTRL_OFF_STATUS)) 1708 break; 1709 DELAY(5); 1710 } 1711 if (ntries == 200) { 1712 printf("%s: timeout waiting for MAC initialization\n", 1713 sc->sc_dev.dv_xname); 1714 return (ETIMEDOUT); 1715 } 1716 1717 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1718 reg = urtwn_read_2(sc, R92C_CR); 1719 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1720 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1721 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 1722 R92C_CR_ENSEC; 1723 urtwn_write_2(sc, R92C_CR, reg); 1724 1725 urtwn_write_1(sc, 0xfe10, 0x19); 1726 return (0); 1727 } 1728 1729 int 1730 urtwn_r92e_power_on(struct urtwn_softc *sc) 1731 { 1732 uint32_t reg; 1733 int ntries; 1734 1735 if (urtwn_read_4(sc, R92C_SYS_CFG) & R92E_SYS_CFG_SPSLDO_SEL) { 1736 /* LDO. */ 1737 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 1738 } else { 1739 reg = urtwn_read_4(sc, R92C_SYS_SWR_CTRL2); 1740 reg &= 0xff0fffff; 1741 reg |= 0x00500000; 1742 urtwn_write_4(sc, R92C_SYS_SWR_CTRL2, reg); 1743 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 1744 } 1745 1746 /* 40MHz crystal source */ 1747 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 1748 urtwn_read_1(sc, R92C_AFE_PLL_CTRL) & 0xfb); 1749 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL_EXT, 1750 urtwn_read_4(sc, R92C_AFE_XTAL_CTRL_EXT) & 0xfffffc7f); 1751 1752 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 1753 urtwn_read_1(sc, R92C_AFE_PLL_CTRL) & 0xbf); 1754 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL_EXT, 1755 urtwn_read_4(sc, R92C_AFE_XTAL_CTRL_EXT) & 0xffdfffff); 1756 1757 /* Disable HWPDN. */ 1758 urtwn_write_2(sc, R92C_APS_FSMCO, 1759 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 1760 for (ntries = 0; ntries < 5000; ntries++) { 1761 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 1762 break; 1763 DELAY(10); 1764 } 1765 if (ntries == 5000) { 1766 printf("%s: timeout waiting for chip power up\n", 1767 sc->sc_dev.dv_xname); 1768 return (ETIMEDOUT); 1769 } 1770 1771 /* Disable WL suspend. */ 1772 urtwn_write_2(sc, R92C_APS_FSMCO, 1773 urtwn_read_2(sc, R92C_APS_FSMCO) & 1774 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 1775 1776 /* Auto enable WLAN. */ 1777 urtwn_write_4(sc, R92C_APS_FSMCO, 1778 urtwn_read_4(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 1779 urtwn_write_2(sc, R92C_APS_FSMCO, 1780 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1781 for (ntries = 0; ntries < 5000; ntries++) { 1782 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1783 R92C_APS_FSMCO_APFM_ONMAC)) 1784 break; 1785 DELAY(10); 1786 } 1787 if (ntries == 5000) { 1788 printf("%s: timeout waiting for MAC auto ON\n", 1789 sc->sc_dev.dv_xname); 1790 return (ETIMEDOUT); 1791 } 1792 1793 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1794 urtwn_write_2(sc, R92C_CR, 0); 1795 reg = urtwn_read_2(sc, R92C_CR); 1796 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1797 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1798 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 1799 urtwn_write_2(sc, R92C_CR, reg); 1800 return (0); 1801 } 1802 1803 int 1804 urtwn_r88e_power_on(struct urtwn_softc *sc) 1805 { 1806 uint32_t reg; 1807 int ntries; 1808 1809 /* Wait for power ready bit. */ 1810 for (ntries = 0; ntries < 5000; ntries++) { 1811 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 1812 break; 1813 DELAY(10); 1814 } 1815 if (ntries == 5000) { 1816 printf("%s: timeout waiting for chip power up\n", 1817 sc->sc_dev.dv_xname); 1818 return (ETIMEDOUT); 1819 } 1820 1821 /* Reset BB. */ 1822 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 1823 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 1824 R92C_SYS_FUNC_EN_BB_GLB_RST)); 1825 1826 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 1827 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 1828 1829 /* Disable HWPDN. */ 1830 urtwn_write_2(sc, R92C_APS_FSMCO, 1831 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 1832 /* Disable WL suspend. */ 1833 urtwn_write_2(sc, R92C_APS_FSMCO, 1834 urtwn_read_2(sc, R92C_APS_FSMCO) & 1835 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 1836 1837 /* Auto enable WLAN. */ 1838 urtwn_write_2(sc, R92C_APS_FSMCO, 1839 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1840 for (ntries = 0; ntries < 5000; ntries++) { 1841 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1842 R92C_APS_FSMCO_APFM_ONMAC)) 1843 break; 1844 DELAY(10); 1845 } 1846 if (ntries == 5000) { 1847 printf("%s: timeout waiting for MAC auto ON\n", 1848 sc->sc_dev.dv_xname); 1849 return (ETIMEDOUT); 1850 } 1851 1852 /* Enable LDO normal mode. */ 1853 urtwn_write_1(sc, R92C_LPLDO_CTRL, 1854 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 1855 1856 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1857 urtwn_write_2(sc, R92C_CR, 0); 1858 reg = urtwn_read_2(sc, R92C_CR); 1859 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1860 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1861 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 1862 urtwn_write_2(sc, R92C_CR, reg); 1863 return (0); 1864 } 1865 1866 int 1867 urtwn_llt_init(struct urtwn_softc *sc, int page_count) 1868 { 1869 int i, error, pktbuf_count; 1870 1871 pktbuf_count = (sc->sc_sc.chip & RTWN_CHIP_88E) ? 1872 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 1873 1874 /* Reserve pages [0; page_count]. */ 1875 for (i = 0; i < page_count; i++) { 1876 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1877 return (error); 1878 } 1879 /* NB: 0xff indicates end-of-list. */ 1880 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 1881 return (error); 1882 /* 1883 * Use pages [page_count + 1; pktbuf_count - 1] 1884 * as ring buffer. 1885 */ 1886 for (++i; i < pktbuf_count - 1; i++) { 1887 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1888 return (error); 1889 } 1890 /* Make the last page point to the beginning of the ring buffer. */ 1891 error = urtwn_llt_write(sc, i, page_count + 1); 1892 return (error); 1893 } 1894 1895 int 1896 urtwn_auto_llt_init(struct urtwn_softc *sc) 1897 { 1898 int ntries; 1899 1900 urtwn_write_4(sc, R92E_AUTO_LLT, urtwn_read_4(sc, 1901 R92E_AUTO_LLT) | R92E_AUTO_LLT_EN); 1902 for (ntries = 0; ntries < 1000; ntries++) { 1903 if (!(urtwn_read_4(sc, R92E_AUTO_LLT) & R92E_AUTO_LLT_EN)) 1904 return (0); 1905 DELAY(2); 1906 } 1907 1908 return (ETIMEDOUT); 1909 } 1910 1911 int 1912 urtwn_fw_loadpage(void *cookie, int page, uint8_t *buf, int len) 1913 { 1914 struct urtwn_softc *sc = cookie; 1915 uint32_t reg; 1916 int off, mlen, error = 0; 1917 1918 reg = urtwn_read_4(sc, R92C_MCUFWDL); 1919 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 1920 urtwn_write_4(sc, R92C_MCUFWDL, reg); 1921 1922 off = R92C_FW_START_ADDR; 1923 while (len > 0) { 1924 if (len > 196) 1925 mlen = 196; 1926 else if (len > 4) 1927 mlen = 4; 1928 else 1929 mlen = 1; 1930 error = urtwn_write_region_1(sc, off, buf, mlen); 1931 if (error != 0) 1932 break; 1933 off += mlen; 1934 buf += mlen; 1935 len -= mlen; 1936 } 1937 return (error); 1938 } 1939 1940 int 1941 urtwn_load_firmware(void *cookie, u_char **fw, size_t *len) 1942 { 1943 struct urtwn_softc *sc = cookie; 1944 const char *name; 1945 int error; 1946 1947 if (sc->sc_sc.chip & RTWN_CHIP_92E) 1948 name = "urtwn-rtl8192eu_nic"; 1949 else if (sc->sc_sc.chip & RTWN_CHIP_88E) 1950 name = "urtwn-rtl8188eufw"; 1951 else if ((sc->sc_sc.chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 1952 RTWN_CHIP_UMC_A_CUT) 1953 name = "urtwn-rtl8192cfwU"; 1954 else 1955 name = "urtwn-rtl8192cfwT"; 1956 1957 error = loadfirmware(name, fw, len); 1958 if (error) 1959 printf("%s: could not read firmware %s (error %d)\n", 1960 sc->sc_dev.dv_xname, name, error); 1961 return (error); 1962 } 1963 1964 int 1965 urtwn_dma_init(void *cookie) 1966 { 1967 struct urtwn_softc *sc = cookie; 1968 uint32_t reg; 1969 uint16_t dmasize; 1970 int hqpages, lqpages, nqpages, pagecnt, boundary; 1971 int error, hashq, haslq, hasnq; 1972 1973 /* Default initialization of chipset values. */ 1974 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1975 hqpages = R88E_HQ_NPAGES; 1976 lqpages = R88E_LQ_NPAGES; 1977 nqpages = R88E_NQ_NPAGES; 1978 pagecnt = R88E_TX_PAGE_COUNT; 1979 boundary = R88E_TX_PAGE_BOUNDARY; 1980 dmasize = R88E_MAX_RX_DMA_SIZE; 1981 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 1982 hqpages = R92E_HQ_NPAGES; 1983 lqpages = R92E_LQ_NPAGES; 1984 nqpages = R92E_NQ_NPAGES; 1985 pagecnt = R92E_TX_PAGE_COUNT; 1986 boundary = R92E_TX_PAGE_BOUNDARY; 1987 dmasize = R92E_MAX_RX_DMA_SIZE; 1988 } else { 1989 hqpages = R92C_HQ_NPAGES; 1990 lqpages = R92C_LQ_NPAGES; 1991 nqpages = R92C_NQ_NPAGES; 1992 pagecnt = R92C_TX_PAGE_COUNT; 1993 boundary = R92C_TX_PAGE_BOUNDARY; 1994 dmasize = R92C_MAX_RX_DMA_SIZE; 1995 } 1996 1997 /* Initialize LLT table. */ 1998 if (sc->sc_sc.chip & RTWN_CHIP_92E) { 1999 error = urtwn_auto_llt_init(sc); 2000 } else { 2001 error = urtwn_llt_init(sc, pagecnt); 2002 } 2003 if (error != 0) 2004 return (error); 2005 2006 /* Get Tx queues to USB endpoints mapping. */ 2007 hashq = hasnq = haslq = 0; 2008 switch (sc->ntx) { 2009 case 3: 2010 haslq = 1; 2011 pagecnt -= lqpages; 2012 /* FALLTHROUGH */ 2013 case 2: 2014 hasnq = 1; 2015 pagecnt -= nqpages; 2016 /* FALLTHROUGH */ 2017 case 1: 2018 hashq = 1; 2019 pagecnt -= hqpages; 2020 break; 2021 } 2022 2023 /* Set number of pages for normal priority queue. */ 2024 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2025 urtwn_write_4(sc, R92C_RQPN, 2026 /* Set number of pages for public queue. */ 2027 SM(R92C_RQPN_PUBQ, pagecnt) | 2028 /* Set number of pages for high priority queue. */ 2029 SM(R92C_RQPN_HPQ, hashq ? hqpages : 0) | 2030 /* Set number of pages for low priority queue. */ 2031 SM(R92C_RQPN_LPQ, haslq ? lqpages : 0) | 2032 /* Load values. */ 2033 R92C_RQPN_LD); 2034 2035 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, boundary); 2036 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, boundary); 2037 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, boundary); 2038 urtwn_write_1(sc, R92C_TRXFF_BNDY, boundary); 2039 urtwn_write_1(sc, R92C_TDECTRL + 1, boundary); 2040 2041 /* Set queue to USB pipe mapping. */ 2042 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2043 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2044 if (haslq) 2045 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2046 else if (hashq) { 2047 if (!hasnq) 2048 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2049 else 2050 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2051 } 2052 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2053 2054 /* Set Tx/Rx transfer page boundary. */ 2055 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, dmasize - 1); 2056 2057 if (!(sc->sc_sc.chip & RTWN_CHIP_92E)) { 2058 /* Set Tx/Rx transfer page size. */ 2059 urtwn_write_1(sc, R92C_PBP, 2060 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2061 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2062 } 2063 return (error); 2064 } 2065 2066 void 2067 urtwn_aggr_init(void *cookie) 2068 { 2069 struct urtwn_softc *sc = cookie; 2070 uint32_t reg = 0; 2071 int dmasize, dmatiming, ndesc; 2072 2073 /* Set burst packet length. */ 2074 if (sc->sc_sc.chip & RTWN_CHIP_92E) 2075 urtwn_burstlen_init(sc); 2076 2077 if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2078 dmasize = 6; 2079 dmatiming = 32; 2080 ndesc = 3; 2081 } else { 2082 dmasize = 48; 2083 dmatiming = 4; 2084 ndesc = (sc->sc_sc.chip & RTWN_CHIP_88E) ? 1 : 6; 2085 } 2086 2087 /* Tx aggregation setting. */ 2088 if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2089 urtwn_write_1(sc, R92E_DWBCN1_CTRL, ndesc << 1); 2090 } else { 2091 reg = urtwn_read_4(sc, R92C_TDECTRL); 2092 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, ndesc); 2093 urtwn_write_4(sc, R92C_TDECTRL, reg); 2094 } 2095 2096 /* Rx aggregation setting. */ 2097 if (!(sc->sc_sc.chip & RTWN_CHIP_92E)) { 2098 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 2099 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 2100 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 2101 } 2102 2103 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, dmasize); 2104 if (sc->sc_sc.chip & (RTWN_CHIP_92C | RTWN_CHIP_88C)) 2105 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, dmatiming); 2106 else 2107 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, dmatiming); 2108 2109 /* Drop incorrect bulk out. */ 2110 urtwn_write_4(sc, R92C_TXDMA_OFFSET_CHK, 2111 urtwn_read_4(sc, R92C_TXDMA_OFFSET_CHK) | 2112 R92C_TXDMA_OFFSET_CHK_DROP_DATA_EN); 2113 } 2114 2115 void 2116 urtwn_mac_init(void *cookie) 2117 { 2118 struct urtwn_softc *sc = cookie; 2119 int i; 2120 2121 /* Write MAC initialization values. */ 2122 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2123 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2124 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2125 rtl8188eu_mac[i].val); 2126 } 2127 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2128 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2129 for (i = 0; i < nitems(rtl8192eu_mac); i++) { 2130 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 2131 rtl8192eu_mac[i].val); 2132 } 2133 } else { 2134 for (i = 0; i < nitems(rtl8192cu_mac); i++) 2135 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2136 rtl8192cu_mac[i].val); 2137 } 2138 } 2139 2140 void 2141 urtwn_bb_init(void *cookie) 2142 { 2143 struct urtwn_softc *sc = cookie; 2144 const struct r92c_bb_prog *prog; 2145 uint32_t reg; 2146 uint8_t xtal; 2147 int i; 2148 2149 /* Enable BB and RF. */ 2150 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2151 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2152 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2153 R92C_SYS_FUNC_EN_DIO_RF); 2154 2155 if (!(sc->sc_sc.chip & (RTWN_CHIP_88E | RTWN_CHIP_92E))) 2156 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2157 2158 urtwn_write_1(sc, R92C_RF_CTRL, 2159 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2160 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2161 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2162 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2163 2164 if (!(sc->sc_sc.chip & (RTWN_CHIP_88E | RTWN_CHIP_92E))) { 2165 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2166 urtwn_write_1(sc, 0x15, 0xe9); 2167 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2168 } 2169 2170 /* Select BB programming based on board type. */ 2171 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2172 prog = &rtl8188eu_bb_prog; 2173 else if (sc->sc_sc.chip & RTWN_CHIP_92E) 2174 prog = &rtl8192eu_bb_prog; 2175 else if (!(sc->sc_sc.chip & RTWN_CHIP_92C)) { 2176 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD) 2177 prog = &rtl8188ce_bb_prog; 2178 else if (sc->sc_sc.board_type == R92C_BOARD_TYPE_HIGHPA) 2179 prog = &rtl8188ru_bb_prog; 2180 else 2181 prog = &rtl8188cu_bb_prog; 2182 } else { 2183 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD) 2184 prog = &rtl8192ce_bb_prog; 2185 else 2186 prog = &rtl8192cu_bb_prog; 2187 } 2188 /* Write BB initialization values. */ 2189 for (i = 0; i < prog->count; i++) { 2190 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2191 DELAY(1); 2192 } 2193 2194 if (sc->sc_sc.chip & RTWN_CHIP_92C_1T2R) { 2195 /* 8192C 1T only configuration. */ 2196 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2197 reg = (reg & ~0x00000003) | 0x2; 2198 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2199 2200 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2201 reg = (reg & ~0x00300033) | 0x00200022; 2202 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2203 2204 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2205 reg = (reg & ~0xff000000) | 0x45 << 24; 2206 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2207 2208 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2209 reg = (reg & ~0x000000ff) | 0x23; 2210 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2211 2212 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2213 reg = (reg & ~0x00000030) | 1 << 4; 2214 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2215 2216 reg = urtwn_bb_read(sc, 0xe74); 2217 reg = (reg & ~0x0c000000) | 2 << 26; 2218 urtwn_bb_write(sc, 0xe74, reg); 2219 reg = urtwn_bb_read(sc, 0xe78); 2220 reg = (reg & ~0x0c000000) | 2 << 26; 2221 urtwn_bb_write(sc, 0xe78, reg); 2222 reg = urtwn_bb_read(sc, 0xe7c); 2223 reg = (reg & ~0x0c000000) | 2 << 26; 2224 urtwn_bb_write(sc, 0xe7c, reg); 2225 reg = urtwn_bb_read(sc, 0xe80); 2226 reg = (reg & ~0x0c000000) | 2 << 26; 2227 urtwn_bb_write(sc, 0xe80, reg); 2228 reg = urtwn_bb_read(sc, 0xe88); 2229 reg = (reg & ~0x0c000000) | 2 << 26; 2230 urtwn_bb_write(sc, 0xe88, reg); 2231 } 2232 2233 /* Write AGC values. */ 2234 for (i = 0; i < prog->agccount; i++) { 2235 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2236 prog->agcvals[i]); 2237 DELAY(1); 2238 } 2239 2240 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2241 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2242 DELAY(1); 2243 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2244 DELAY(1); 2245 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2246 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040022); 2247 DELAY(1); 2248 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040020); 2249 DELAY(1); 2250 } 2251 2252 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2253 xtal = sc->sc_sc.crystal_cap & 0x3f; 2254 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2255 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2256 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, xtal | xtal << 6)); 2257 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2258 xtal = sc->sc_sc.crystal_cap & 0x3f; 2259 reg = urtwn_read_4(sc, R92C_AFE_CTRL3); 2260 reg &= 0xff000fff; 2261 reg |= (xtal | (xtal << 6)) << 12; 2262 urtwn_write_4(sc, R92C_AFE_CTRL3, reg); 2263 2264 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0x000f81fb); 2265 } 2266 2267 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & R92C_HSSI_PARAM2_CCK_HIPWR) 2268 sc->sc_sc.sc_flags |= RTWN_FLAG_CCK_HIPWR; 2269 } 2270 2271 void 2272 urtwn_burstlen_init(struct urtwn_softc *sc) 2273 { 2274 uint8_t reg; 2275 2276 reg = urtwn_read_1(sc, R92E_RXDMA_PRO); 2277 reg &= ~0x30; 2278 switch (sc->sc_udev->speed) { 2279 case USB_SPEED_HIGH: 2280 urtwn_write_1(sc, R92E_RXDMA_PRO, reg | 0x1e); 2281 break; 2282 default: 2283 urtwn_write_1(sc, R92E_RXDMA_PRO, reg | 0x2e); 2284 break; 2285 } 2286 } 2287 2288 int 2289 urtwn_power_on(void *cookie) 2290 { 2291 struct urtwn_softc *sc = cookie; 2292 2293 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2294 return (urtwn_r88e_power_on(sc)); 2295 else if (sc->sc_sc.chip & RTWN_CHIP_92E) 2296 return (urtwn_r92e_power_on(sc)); 2297 2298 return (urtwn_r92c_power_on(sc)); 2299 } 2300 2301 int 2302 urtwn_alloc_buffers(void *cookie) 2303 { 2304 struct urtwn_softc *sc = cookie; 2305 int error; 2306 2307 /* Init host async commands ring. */ 2308 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 2309 2310 /* Allocate Tx/Rx buffers. */ 2311 error = urtwn_alloc_rx_list(sc); 2312 if (error != 0) { 2313 printf("%s: could not allocate Rx buffers\n", 2314 sc->sc_dev.dv_xname); 2315 return (error); 2316 } 2317 error = urtwn_alloc_tx_list(sc); 2318 if (error != 0) { 2319 printf("%s: could not allocate Tx buffers\n", 2320 sc->sc_dev.dv_xname); 2321 return (error); 2322 } 2323 2324 return (0); 2325 } 2326 2327 int 2328 urtwn_init(void *cookie) 2329 { 2330 struct urtwn_softc *sc = cookie; 2331 int i, error; 2332 2333 if (sc->sc_sc.chip & RTWN_CHIP_92E) 2334 urtwn_write_1(sc, R92C_ACLK_MON, 0); 2335 2336 /* Queue Rx xfers. */ 2337 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 2338 struct urtwn_rx_data *data = &sc->rx_data[i]; 2339 2340 usbd_setup_xfer(data->xfer, sc->rx_pipe, data, data->buf, 2341 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 2342 USBD_NO_TIMEOUT, urtwn_rxeof); 2343 error = usbd_transfer(data->xfer); 2344 if (error != 0 && error != USBD_IN_PROGRESS) 2345 return (error); 2346 } 2347 2348 ieee80211_amrr_node_init(&sc->amrr, &sc->amn); 2349 2350 /* 2351 * Enable TX reports for AMRR. 2352 * In order to get reports we need to explicitly reset the register. 2353 */ 2354 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2355 urtwn_write_1(sc, R88E_TX_RPT_CTRL, (urtwn_read_1(sc, 2356 R88E_TX_RPT_CTRL) & ~0) | R88E_TX_RPT_CTRL_EN); 2357 2358 return (0); 2359 } 2360 2361 void 2362 urtwn_stop(void *cookie) 2363 { 2364 struct urtwn_softc *sc = cookie; 2365 int i; 2366 2367 /* Abort Tx. */ 2368 for (i = 0; i < R92C_MAX_EPOUT; i++) { 2369 if (sc->tx_pipe[i] != NULL) 2370 usbd_abort_pipe(sc->tx_pipe[i]); 2371 } 2372 /* Stop Rx pipe. */ 2373 usbd_abort_pipe(sc->rx_pipe); 2374 /* Free Tx/Rx buffers. */ 2375 urtwn_free_tx_list(sc); 2376 urtwn_free_rx_list(sc); 2377 } 2378 2379 int 2380 urtwn_is_oactive(void *cookie) 2381 { 2382 struct urtwn_softc *sc = cookie; 2383 2384 return (TAILQ_EMPTY(&sc->tx_free_list)); 2385 } 2386