1 /* $OpenBSD: if_urtwn.c,v 1.101 2022/06/26 15:38:11 jmatthew Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss@yahoo.com.au> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU/ 23 * RTL8192EU. 24 */ 25 26 #include "bpfilter.h" 27 28 #include <sys/param.h> 29 #include <sys/sockio.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/timeout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 #include <sys/endian.h> 38 39 #include <machine/bus.h> 40 #include <machine/intr.h> 41 42 #if NBPFILTER > 0 43 #include <net/bpf.h> 44 #endif 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 49 #include <netinet/in.h> 50 #include <netinet/if_ether.h> 51 52 #include <net80211/ieee80211_var.h> 53 #include <net80211/ieee80211_amrr.h> 54 #include <net80211/ieee80211_radiotap.h> 55 56 #include <dev/usb/usb.h> 57 #include <dev/usb/usbdi.h> 58 #include <dev/usb/usbdivar.h> 59 #include <dev/usb/usbdi_util.h> 60 #include <dev/usb/usbdevs.h> 61 62 #include <dev/ic/r92creg.h> 63 #include <dev/ic/rtwnvar.h> 64 65 /* Maximum number of output pipes is 3. */ 66 #define R92C_MAX_EPOUT 3 67 68 #define R92C_HQ_NPAGES 12 69 #define R92C_LQ_NPAGES 2 70 #define R92C_NQ_NPAGES 2 71 #define R92C_TXPKTBUF_COUNT 256 72 #define R92C_TX_PAGE_COUNT 248 73 #define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) 74 #define R92C_MAX_RX_DMA_SIZE 0x2800 75 76 #define R88E_HQ_NPAGES 0 77 #define R88E_LQ_NPAGES 9 78 #define R88E_NQ_NPAGES 0 79 #define R88E_TXPKTBUF_COUNT 177 80 #define R88E_TX_PAGE_COUNT 168 81 #define R88E_TX_PAGE_BOUNDARY (R88E_TX_PAGE_COUNT + 1) 82 #define R88E_MAX_RX_DMA_SIZE 0x2400 83 84 #define R92E_HQ_NPAGES 16 85 #define R92E_LQ_NPAGES 16 86 #define R92E_NQ_NPAGES 16 87 #define R92E_TX_PAGE_COUNT 248 88 #define R92E_TX_PAGE_BOUNDARY (R92E_TX_PAGE_COUNT + 1) 89 #define R92E_MAX_RX_DMA_SIZE 0x3fc0 90 91 #define R92C_TXDESC_SUMSIZE 32 92 #define R92C_TXDESC_SUMOFFSET 14 93 94 /* USB Requests. */ 95 #define R92C_REQ_REGS 0x05 96 97 /* 98 * Driver definitions. 99 */ 100 #define URTWN_RX_LIST_COUNT 1 101 #define URTWN_TX_LIST_COUNT 8 102 #define URTWN_HOST_CMD_RING_COUNT 32 103 104 #define URTWN_RXBUFSZ (16 * 1024) 105 #define URTWN_TXBUFSZ (sizeof(struct r92e_tx_desc_usb) + IEEE80211_MAX_LEN) 106 107 #define URTWN_RIDX_COUNT 28 108 109 #define URTWN_TX_TIMEOUT 5000 /* ms */ 110 111 #define URTWN_LED_LINK 0 112 #define URTWN_LED_DATA 1 113 114 struct urtwn_rx_radiotap_header { 115 struct ieee80211_radiotap_header wr_ihdr; 116 uint8_t wr_flags; 117 uint8_t wr_rate; 118 uint16_t wr_chan_freq; 119 uint16_t wr_chan_flags; 120 uint8_t wr_dbm_antsignal; 121 } __packed; 122 123 #define URTWN_RX_RADIOTAP_PRESENT \ 124 (1 << IEEE80211_RADIOTAP_FLAGS | \ 125 1 << IEEE80211_RADIOTAP_RATE | \ 126 1 << IEEE80211_RADIOTAP_CHANNEL | \ 127 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) 128 129 struct urtwn_tx_radiotap_header { 130 struct ieee80211_radiotap_header wt_ihdr; 131 uint8_t wt_flags; 132 uint16_t wt_chan_freq; 133 uint16_t wt_chan_flags; 134 } __packed; 135 136 #define URTWN_TX_RADIOTAP_PRESENT \ 137 (1 << IEEE80211_RADIOTAP_FLAGS | \ 138 1 << IEEE80211_RADIOTAP_CHANNEL) 139 140 struct urtwn_softc; 141 142 struct urtwn_rx_data { 143 struct urtwn_softc *sc; 144 struct usbd_xfer *xfer; 145 uint8_t *buf; 146 }; 147 148 struct urtwn_tx_data { 149 struct urtwn_softc *sc; 150 struct usbd_pipe *pipe; 151 struct usbd_xfer *xfer; 152 uint8_t *buf; 153 TAILQ_ENTRY(urtwn_tx_data) next; 154 }; 155 156 struct urtwn_host_cmd { 157 void (*cb)(struct urtwn_softc *, void *); 158 uint8_t data[256]; 159 }; 160 161 struct urtwn_cmd_newstate { 162 enum ieee80211_state state; 163 int arg; 164 }; 165 166 struct urtwn_cmd_key { 167 struct ieee80211_key key; 168 struct ieee80211_node *ni; 169 }; 170 171 struct urtwn_host_cmd_ring { 172 struct urtwn_host_cmd cmd[URTWN_HOST_CMD_RING_COUNT]; 173 int cur; 174 int next; 175 int queued; 176 }; 177 178 struct urtwn_softc { 179 struct device sc_dev; 180 struct rtwn_softc sc_sc; 181 182 struct usbd_device *sc_udev; 183 struct usbd_interface *sc_iface; 184 struct usb_task sc_task; 185 186 struct timeout scan_to; 187 struct timeout calib_to; 188 189 int ntx; 190 struct usbd_pipe *rx_pipe; 191 struct usbd_pipe *tx_pipe[R92C_MAX_EPOUT]; 192 int ac2idx[EDCA_NUM_AC]; 193 194 struct urtwn_host_cmd_ring cmdq; 195 struct urtwn_rx_data rx_data[URTWN_RX_LIST_COUNT]; 196 struct urtwn_tx_data tx_data[URTWN_TX_LIST_COUNT]; 197 TAILQ_HEAD(, urtwn_tx_data) tx_free_list; 198 199 struct ieee80211_amrr amrr; 200 struct ieee80211_amrr_node amn; 201 202 #if NBPFILTER > 0 203 caddr_t sc_drvbpf; 204 205 union { 206 struct urtwn_rx_radiotap_header th; 207 uint8_t pad[64]; 208 } sc_rxtapu; 209 #define sc_rxtap sc_rxtapu.th 210 int sc_rxtap_len; 211 212 union { 213 struct urtwn_tx_radiotap_header th; 214 uint8_t pad[64]; 215 } sc_txtapu; 216 #define sc_txtap sc_txtapu.th 217 int sc_txtap_len; 218 #endif 219 int sc_key_tasks; 220 }; 221 222 #ifdef URTWN_DEBUG 223 #define DPRINTF(x) do { if (urtwn_debug) printf x; } while (0) 224 #define DPRINTFN(n, x) do { if (urtwn_debug >= (n)) printf x; } while (0) 225 int urtwn_debug = 4; 226 #else 227 #define DPRINTF(x) 228 #define DPRINTFN(n, x) 229 #endif 230 231 /* 232 * Various supported device vendors/products. 233 */ 234 #define URTWN_DEV(v, p, f) \ 235 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, (f) | RTWN_CHIP_USB } 236 #define URTWN_DEV_8192CU(v, p) URTWN_DEV(v, p, RTWN_CHIP_92C | RTWN_CHIP_88C) 237 #define URTWN_DEV_8188EU(v, p) URTWN_DEV(v, p, RTWN_CHIP_88E) 238 #define URTWN_DEV_8192EU(v, p) URTWN_DEV(v, p, RTWN_CHIP_92E) 239 static const struct urtwn_type { 240 struct usb_devno dev; 241 uint32_t chip; 242 } urtwn_devs[] = { 243 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_1), 244 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_1), 245 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_2), 246 URTWN_DEV_8192CU(ABOCOM, RTL8192CU), 247 URTWN_DEV_8192CU(ASUS, RTL8192CU), 248 URTWN_DEV_8192CU(ASUS, RTL8192CU_2), 249 URTWN_DEV_8192CU(ASUS, RTL8192CU_3), 250 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CE_1), 251 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CE_2), 252 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CU), 253 URTWN_DEV_8192CU(BELKIN, F7D2102), 254 URTWN_DEV_8192CU(BELKIN, F9L1004V1), 255 URTWN_DEV_8192CU(BELKIN, RTL8188CU), 256 URTWN_DEV_8192CU(BELKIN, RTL8188CUS), 257 URTWN_DEV_8192CU(BELKIN, RTL8192CU), 258 URTWN_DEV_8192CU(BELKIN, RTL8192CU_1), 259 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_1), 260 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_2), 261 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_3), 262 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_4), 263 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_5), 264 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_6), 265 URTWN_DEV_8192CU(COMPARE, RTL8192CU), 266 URTWN_DEV_8192CU(COREGA, RTL8192CU), 267 URTWN_DEV_8192CU(DLINK, DWA131B), 268 URTWN_DEV_8192CU(DLINK, RTL8188CU), 269 URTWN_DEV_8192CU(DLINK, RTL8192CU_1), 270 URTWN_DEV_8192CU(DLINK, RTL8192CU_2), 271 URTWN_DEV_8192CU(DLINK, RTL8192CU_3), 272 URTWN_DEV_8192CU(DLINK, RTL8192CU_4), 273 URTWN_DEV_8192CU(EDIMAX, EW7811UN), 274 URTWN_DEV_8192CU(EDIMAX, RTL8192CU), 275 URTWN_DEV_8192CU(FEIXUN, RTL8188CU), 276 URTWN_DEV_8192CU(FEIXUN, RTL8192CU), 277 URTWN_DEV_8192CU(GUILLEMOT, HWNUP150), 278 URTWN_DEV_8192CU(GUILLEMOT, RTL8192CU), 279 URTWN_DEV_8192CU(HAWKING, RTL8192CU), 280 URTWN_DEV_8192CU(HAWKING, RTL8192CU_2), 281 URTWN_DEV_8192CU(HP3, RTL8188CU), 282 URTWN_DEV_8192CU(IODATA, WNG150UM), 283 URTWN_DEV_8192CU(IODATA, RTL8192CU), 284 URTWN_DEV_8192CU(NETGEAR, N300MA), 285 URTWN_DEV_8192CU(NETGEAR, WNA1000M), 286 URTWN_DEV_8192CU(NETGEAR, WNA1000MV2), 287 URTWN_DEV_8192CU(NETGEAR, RTL8192CU), 288 URTWN_DEV_8192CU(NETGEAR4, RTL8188CU), 289 URTWN_DEV_8192CU(NETWEEN, RTL8192CU), 290 URTWN_DEV_8192CU(NOVATECH, RTL8188CU), 291 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_1), 292 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_2), 293 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_3), 294 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_4), 295 URTWN_DEV_8192CU(PLANEX2, RTL8188CUS), 296 URTWN_DEV_8192CU(PLANEX2, RTL8192CU), 297 URTWN_DEV_8192CU(REALTEK, RTL8188CE_0), 298 URTWN_DEV_8192CU(REALTEK, RTL8188CE_1), 299 URTWN_DEV_8192CU(REALTEK, RTL8188CTV), 300 URTWN_DEV_8192CU(REALTEK, RTL8188CU_0), 301 URTWN_DEV_8192CU(REALTEK, RTL8188CU_1), 302 URTWN_DEV_8192CU(REALTEK, RTL8188CU_2), 303 URTWN_DEV_8192CU(REALTEK, RTL8188CU_3), 304 URTWN_DEV_8192CU(REALTEK, RTL8188CU_4), 305 URTWN_DEV_8192CU(REALTEK, RTL8188CU_5), 306 URTWN_DEV_8192CU(REALTEK, RTL8188CU_COMBO), 307 URTWN_DEV_8192CU(REALTEK, RTL8188CUS), 308 URTWN_DEV_8192CU(REALTEK, RTL8188RU), 309 URTWN_DEV_8192CU(REALTEK, RTL8188RU_2), 310 URTWN_DEV_8192CU(REALTEK, RTL8188RU_3), 311 URTWN_DEV_8192CU(REALTEK, RTL8191CU), 312 URTWN_DEV_8192CU(REALTEK, RTL8192CE), 313 URTWN_DEV_8192CU(REALTEK, RTL8192CE_VAU), 314 URTWN_DEV_8192CU(REALTEK, RTL8192CU), 315 URTWN_DEV_8192CU(SITECOMEU, RTL8188CU), 316 URTWN_DEV_8192CU(SITECOMEU, RTL8188CU_2), 317 URTWN_DEV_8192CU(SITECOMEU, RTL8192CU), 318 URTWN_DEV_8192CU(SITECOMEU, RTL8192CU_2), 319 URTWN_DEV_8192CU(SITECOMEU, WLA2100V2), 320 URTWN_DEV_8192CU(TPLINK, RTL8192CU), 321 URTWN_DEV_8192CU(TRENDNET, RTL8188CU), 322 URTWN_DEV_8192CU(TRENDNET, RTL8192CU), 323 URTWN_DEV_8192CU(ZYXEL, RTL8192CU), 324 /* URTWN_RTL8188E */ 325 URTWN_DEV_8188EU(ABOCOM, RTL8188EU), 326 URTWN_DEV_8188EU(DLINK, DWA121B1), 327 URTWN_DEV_8188EU(DLINK, DWA123D1), 328 URTWN_DEV_8188EU(DLINK, DWA125D1), 329 URTWN_DEV_8188EU(EDIMAX, EW7811UNV2), 330 URTWN_DEV_8188EU(ELECOM, WDC150SU2M), 331 URTWN_DEV_8188EU(REALTEK, RTL8188ETV), 332 URTWN_DEV_8188EU(REALTEK, RTL8188EU), 333 URTWN_DEV_8188EU(TPLINK, RTL8188EUS), 334 URTWN_DEV_8188EU(ASUS, RTL8188EUS), 335 336 /* URTWN_RTL8192EU */ 337 URTWN_DEV_8192EU(DLINK, DWA131E1), 338 URTWN_DEV_8192EU(REALTEK, RTL8192EU), 339 URTWN_DEV_8192EU(TPLINK, RTL8192EU), 340 URTWN_DEV_8192EU(TPLINK, RTL8192EU_2), 341 URTWN_DEV_8192EU(TPLINK, RTL8192EU_3) 342 }; 343 344 #define urtwn_lookup(v, p) \ 345 ((const struct urtwn_type *)usb_lookup(urtwn_devs, v, p)) 346 347 int urtwn_match(struct device *, void *, void *); 348 void urtwn_attach(struct device *, struct device *, void *); 349 int urtwn_detach(struct device *, int); 350 int urtwn_open_pipes(struct urtwn_softc *); 351 void urtwn_close_pipes(struct urtwn_softc *); 352 int urtwn_alloc_rx_list(struct urtwn_softc *); 353 void urtwn_free_rx_list(struct urtwn_softc *); 354 int urtwn_alloc_tx_list(struct urtwn_softc *); 355 void urtwn_free_tx_list(struct urtwn_softc *); 356 void urtwn_task(void *); 357 void urtwn_do_async(struct urtwn_softc *, 358 void (*)(struct urtwn_softc *, void *), void *, int); 359 void urtwn_wait_async(void *); 360 int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 361 int); 362 void urtwn_write_1(void *, uint16_t, uint8_t); 363 void urtwn_write_2(void *, uint16_t, uint16_t); 364 void urtwn_write_4(void *, uint16_t, uint32_t); 365 int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 366 int); 367 uint8_t urtwn_read_1(void *, uint16_t); 368 uint16_t urtwn_read_2(void *, uint16_t); 369 uint32_t urtwn_read_4(void *, uint16_t); 370 int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 371 void urtwn_calib_to(void *); 372 void urtwn_calib_cb(struct urtwn_softc *, void *); 373 void urtwn_scan_to(void *); 374 void urtwn_next_scan(void *); 375 void urtwn_cancel_scan(void *); 376 int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 377 int); 378 void urtwn_newstate_cb(struct urtwn_softc *, void *); 379 void urtwn_updateslot(struct ieee80211com *); 380 void urtwn_updateslot_cb(struct urtwn_softc *, void *); 381 void urtwn_updateedca(struct ieee80211com *); 382 void urtwn_updateedca_cb(struct urtwn_softc *, void *); 383 int urtwn_set_key(struct ieee80211com *, struct ieee80211_node *, 384 struct ieee80211_key *); 385 void urtwn_set_key_cb(struct urtwn_softc *, void *); 386 void urtwn_delete_key(struct ieee80211com *, 387 struct ieee80211_node *, struct ieee80211_key *); 388 void urtwn_delete_key_cb(struct urtwn_softc *, void *); 389 void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 390 struct mbuf_list *); 391 void urtwn_rxeof(struct usbd_xfer *, void *, 392 usbd_status); 393 void urtwn_txeof(struct usbd_xfer *, void *, 394 usbd_status); 395 int urtwn_tx(void *, struct mbuf *, struct ieee80211_node *); 396 int urtwn_ioctl(struct ifnet *, u_long, caddr_t); 397 int urtwn_power_on(void *); 398 int urtwn_alloc_buffers(void *); 399 int urtwn_r92c_power_on(struct urtwn_softc *); 400 int urtwn_r92e_power_on(struct urtwn_softc *); 401 int urtwn_r88e_power_on(struct urtwn_softc *); 402 int urtwn_llt_init(struct urtwn_softc *, int); 403 int urtwn_fw_loadpage(void *, int, uint8_t *, int); 404 int urtwn_load_firmware(void *, u_char **, size_t *); 405 int urtwn_dma_init(void *); 406 void urtwn_aggr_init(void *); 407 void urtwn_mac_init(void *); 408 void urtwn_bb_init(void *); 409 void urtwn_burstlen_init(struct urtwn_softc *); 410 int urtwn_init(void *); 411 void urtwn_stop(void *); 412 int urtwn_is_oactive(void *); 413 void urtwn_next_calib(void *); 414 void urtwn_cancel_calib(void *); 415 416 /* Aliases. */ 417 #define urtwn_bb_write urtwn_write_4 418 #define urtwn_bb_read urtwn_read_4 419 420 struct cfdriver urtwn_cd = { 421 NULL, "urtwn", DV_IFNET 422 }; 423 424 const struct cfattach urtwn_ca = { 425 sizeof(struct urtwn_softc), urtwn_match, urtwn_attach, urtwn_detach 426 }; 427 428 int 429 urtwn_match(struct device *parent, void *match, void *aux) 430 { 431 struct usb_attach_arg *uaa = aux; 432 433 if (uaa->iface == NULL || uaa->configno != 1) 434 return (UMATCH_NONE); 435 436 return ((urtwn_lookup(uaa->vendor, uaa->product) != NULL) ? 437 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 438 } 439 440 void 441 urtwn_attach(struct device *parent, struct device *self, void *aux) 442 { 443 struct urtwn_softc *sc = (struct urtwn_softc *)self; 444 struct usb_attach_arg *uaa = aux; 445 struct ifnet *ifp; 446 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 447 448 sc->sc_udev = uaa->device; 449 sc->sc_iface = uaa->iface; 450 451 sc->sc_sc.chip = urtwn_lookup(uaa->vendor, uaa->product)->chip; 452 453 usb_init_task(&sc->sc_task, urtwn_task, sc, USB_TASK_TYPE_GENERIC); 454 timeout_set(&sc->scan_to, urtwn_scan_to, sc); 455 timeout_set(&sc->calib_to, urtwn_calib_to, sc); 456 if (urtwn_open_pipes(sc) != 0) 457 return; 458 459 sc->amrr.amrr_min_success_threshold = 1; 460 sc->amrr.amrr_max_success_threshold = 10; 461 462 /* Attach the bus-agnostic driver. */ 463 sc->sc_sc.sc_ops.cookie = sc; 464 sc->sc_sc.sc_ops.write_1 = urtwn_write_1; 465 sc->sc_sc.sc_ops.write_2 = urtwn_write_2; 466 sc->sc_sc.sc_ops.write_4 = urtwn_write_4; 467 sc->sc_sc.sc_ops.read_1 = urtwn_read_1; 468 sc->sc_sc.sc_ops.read_2 = urtwn_read_2; 469 sc->sc_sc.sc_ops.read_4 = urtwn_read_4; 470 sc->sc_sc.sc_ops.tx = urtwn_tx; 471 sc->sc_sc.sc_ops.power_on = urtwn_power_on; 472 sc->sc_sc.sc_ops.dma_init = urtwn_dma_init; 473 sc->sc_sc.sc_ops.fw_loadpage = urtwn_fw_loadpage; 474 sc->sc_sc.sc_ops.load_firmware = urtwn_load_firmware; 475 sc->sc_sc.sc_ops.aggr_init = urtwn_aggr_init; 476 sc->sc_sc.sc_ops.mac_init = urtwn_mac_init; 477 sc->sc_sc.sc_ops.bb_init = urtwn_bb_init; 478 sc->sc_sc.sc_ops.alloc_buffers = urtwn_alloc_buffers; 479 sc->sc_sc.sc_ops.init = urtwn_init; 480 sc->sc_sc.sc_ops.stop = urtwn_stop; 481 sc->sc_sc.sc_ops.is_oactive = urtwn_is_oactive; 482 sc->sc_sc.sc_ops.next_calib = urtwn_next_calib; 483 sc->sc_sc.sc_ops.cancel_calib = urtwn_cancel_calib; 484 sc->sc_sc.sc_ops.next_scan = urtwn_next_scan; 485 sc->sc_sc.sc_ops.cancel_scan = urtwn_cancel_scan; 486 sc->sc_sc.sc_ops.wait_async = urtwn_wait_async; 487 if (rtwn_attach(&sc->sc_dev, &sc->sc_sc) != 0) { 488 urtwn_close_pipes(sc); 489 return; 490 } 491 492 /* ifp is now valid */ 493 ifp = &sc->sc_sc.sc_ic.ic_if; 494 ifp->if_ioctl = urtwn_ioctl; 495 496 ic->ic_updateslot = urtwn_updateslot; 497 ic->ic_updateedca = urtwn_updateedca; 498 ic->ic_set_key = urtwn_set_key; 499 ic->ic_delete_key = urtwn_delete_key; 500 /* Override state transition machine. */ 501 ic->ic_newstate = urtwn_newstate; 502 503 #if NBPFILTER > 0 504 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 505 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 506 507 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 508 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 509 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 510 511 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 512 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 513 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 514 #endif 515 } 516 517 int 518 urtwn_detach(struct device *self, int flags) 519 { 520 struct urtwn_softc *sc = (struct urtwn_softc *)self; 521 int s; 522 523 s = splusb(); 524 525 if (timeout_initialized(&sc->scan_to)) 526 timeout_del(&sc->scan_to); 527 if (timeout_initialized(&sc->calib_to)) 528 timeout_del(&sc->calib_to); 529 530 /* Wait for all async commands to complete. */ 531 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 532 533 usbd_ref_wait(sc->sc_udev); 534 535 rtwn_detach(&sc->sc_sc, flags); 536 537 /* Abort and close Tx/Rx pipes. */ 538 urtwn_close_pipes(sc); 539 540 /* Free Tx/Rx buffers. */ 541 urtwn_free_tx_list(sc); 542 urtwn_free_rx_list(sc); 543 splx(s); 544 545 return (0); 546 } 547 548 int 549 urtwn_open_pipes(struct urtwn_softc *sc) 550 { 551 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 552 uint8_t epaddr[R92C_MAX_EPOUT] = { 0, 0, 0 }; 553 uint8_t rx_no; 554 usb_interface_descriptor_t *id; 555 usb_endpoint_descriptor_t *ed; 556 int i, error, nrx = 0; 557 558 /* Find all bulk endpoints. */ 559 id = usbd_get_interface_descriptor(sc->sc_iface); 560 for (i = 0; i < id->bNumEndpoints; i++) { 561 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 562 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) 563 continue; 564 565 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 566 rx_no = ed->bEndpointAddress; 567 nrx++; 568 } else { 569 if (sc->ntx < R92C_MAX_EPOUT) 570 epaddr[sc->ntx] = ed->bEndpointAddress; 571 sc->ntx++; 572 } 573 } 574 if (nrx == 0) { 575 printf("%s: %d: invalid number of Rx bulk pipes\n", 576 sc->sc_dev.dv_xname, nrx); 577 return (EIO); 578 } 579 DPRINTF(("found %d bulk-out pipes\n", sc->ntx)); 580 if (sc->ntx == 0 || sc->ntx > R92C_MAX_EPOUT) { 581 printf("%s: %d: invalid number of Tx bulk pipes\n", 582 sc->sc_dev.dv_xname, sc->ntx); 583 return (EIO); 584 } 585 586 /* Open bulk-in pipe. */ 587 error = usbd_open_pipe(sc->sc_iface, rx_no, 0, &sc->rx_pipe); 588 if (error != 0) { 589 printf("%s: could not open Rx bulk pipe\n", 590 sc->sc_dev.dv_xname); 591 goto fail; 592 } 593 594 /* Open bulk-out pipes (up to 3). */ 595 for (i = 0; i < sc->ntx; i++) { 596 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 0, 597 &sc->tx_pipe[i]); 598 if (error != 0) { 599 printf("%s: could not open Tx bulk pipe 0x%02x\n", 600 sc->sc_dev.dv_xname, epaddr[i]); 601 goto fail; 602 } 603 } 604 605 /* Map 802.11 access categories to USB pipes. */ 606 sc->ac2idx[EDCA_AC_BK] = 607 sc->ac2idx[EDCA_AC_BE] = (sc->ntx == 3) ? 2 : ((sc->ntx == 2) ? 1 : 0); 608 sc->ac2idx[EDCA_AC_VI] = (sc->ntx == 3) ? 1 : 0; 609 sc->ac2idx[EDCA_AC_VO] = 0; /* Always use highest prio. */ 610 611 if (error != 0) 612 fail: urtwn_close_pipes(sc); 613 return (error); 614 } 615 616 void 617 urtwn_close_pipes(struct urtwn_softc *sc) 618 { 619 int i; 620 621 /* Close Rx pipe. */ 622 if (sc->rx_pipe != NULL) 623 usbd_close_pipe(sc->rx_pipe); 624 /* Close Tx pipes. */ 625 for (i = 0; i < R92C_MAX_EPOUT; i++) { 626 if (sc->tx_pipe[i] == NULL) 627 continue; 628 usbd_close_pipe(sc->tx_pipe[i]); 629 } 630 } 631 632 int 633 urtwn_alloc_rx_list(struct urtwn_softc *sc) 634 { 635 struct urtwn_rx_data *data; 636 int i, error = 0; 637 638 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 639 data = &sc->rx_data[i]; 640 641 data->sc = sc; /* Backpointer for callbacks. */ 642 643 data->xfer = usbd_alloc_xfer(sc->sc_udev); 644 if (data->xfer == NULL) { 645 printf("%s: could not allocate xfer\n", 646 sc->sc_dev.dv_xname); 647 error = ENOMEM; 648 break; 649 } 650 data->buf = usbd_alloc_buffer(data->xfer, URTWN_RXBUFSZ); 651 if (data->buf == NULL) { 652 printf("%s: could not allocate xfer buffer\n", 653 sc->sc_dev.dv_xname); 654 error = ENOMEM; 655 break; 656 } 657 } 658 if (error != 0) 659 urtwn_free_rx_list(sc); 660 return (error); 661 } 662 663 void 664 urtwn_free_rx_list(struct urtwn_softc *sc) 665 { 666 int i; 667 668 /* NB: Caller must abort pipe first. */ 669 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 670 if (sc->rx_data[i].xfer != NULL) 671 usbd_free_xfer(sc->rx_data[i].xfer); 672 sc->rx_data[i].xfer = NULL; 673 } 674 } 675 676 int 677 urtwn_alloc_tx_list(struct urtwn_softc *sc) 678 { 679 struct urtwn_tx_data *data; 680 int i, error = 0; 681 682 TAILQ_INIT(&sc->tx_free_list); 683 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 684 data = &sc->tx_data[i]; 685 686 data->sc = sc; /* Backpointer for callbacks. */ 687 688 data->xfer = usbd_alloc_xfer(sc->sc_udev); 689 if (data->xfer == NULL) { 690 printf("%s: could not allocate xfer\n", 691 sc->sc_dev.dv_xname); 692 error = ENOMEM; 693 break; 694 } 695 data->buf = usbd_alloc_buffer(data->xfer, URTWN_TXBUFSZ); 696 if (data->buf == NULL) { 697 printf("%s: could not allocate xfer buffer\n", 698 sc->sc_dev.dv_xname); 699 error = ENOMEM; 700 break; 701 } 702 /* Append this Tx buffer to our free list. */ 703 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 704 } 705 if (error != 0) 706 urtwn_free_tx_list(sc); 707 return (error); 708 } 709 710 void 711 urtwn_free_tx_list(struct urtwn_softc *sc) 712 { 713 int i; 714 715 /* NB: Caller must abort pipe first. */ 716 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 717 if (sc->tx_data[i].xfer != NULL) 718 usbd_free_xfer(sc->tx_data[i].xfer); 719 sc->tx_data[i].xfer = NULL; 720 } 721 } 722 723 void 724 urtwn_task(void *arg) 725 { 726 struct urtwn_softc *sc = arg; 727 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 728 struct urtwn_host_cmd *cmd; 729 int s; 730 731 /* Process host commands. */ 732 s = splusb(); 733 while (ring->next != ring->cur) { 734 cmd = &ring->cmd[ring->next]; 735 splx(s); 736 /* Invoke callback. */ 737 cmd->cb(sc, cmd->data); 738 s = splusb(); 739 ring->queued--; 740 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 741 } 742 splx(s); 743 } 744 745 void 746 urtwn_do_async(struct urtwn_softc *sc, 747 void (*cb)(struct urtwn_softc *, void *), void *arg, int len) 748 { 749 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 750 struct urtwn_host_cmd *cmd; 751 int s; 752 753 s = splusb(); 754 cmd = &ring->cmd[ring->cur]; 755 cmd->cb = cb; 756 KASSERT(len <= sizeof(cmd->data)); 757 memcpy(cmd->data, arg, len); 758 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 759 760 /* If there is no pending command already, schedule a task. */ 761 if (++ring->queued == 1) 762 usb_add_task(sc->sc_udev, &sc->sc_task); 763 splx(s); 764 } 765 766 void 767 urtwn_wait_async(void *cookie) 768 { 769 struct urtwn_softc *sc = cookie; 770 int s; 771 772 s = splusb(); 773 /* Wait for all queued asynchronous commands to complete. */ 774 usb_wait_task(sc->sc_udev, &sc->sc_task); 775 splx(s); 776 } 777 778 int 779 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 780 int len) 781 { 782 usb_device_request_t req; 783 784 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 785 req.bRequest = R92C_REQ_REGS; 786 USETW(req.wValue, addr); 787 USETW(req.wIndex, 0); 788 USETW(req.wLength, len); 789 return (usbd_do_request(sc->sc_udev, &req, buf)); 790 } 791 792 void 793 urtwn_write_1(void *cookie, uint16_t addr, uint8_t val) 794 { 795 struct urtwn_softc *sc = cookie; 796 797 urtwn_write_region_1(sc, addr, &val, 1); 798 } 799 800 void 801 urtwn_write_2(void *cookie, uint16_t addr, uint16_t val) 802 { 803 struct urtwn_softc *sc = cookie; 804 805 val = htole16(val); 806 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 807 } 808 809 void 810 urtwn_write_4(void *cookie, uint16_t addr, uint32_t val) 811 { 812 struct urtwn_softc *sc = cookie; 813 814 val = htole32(val); 815 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 816 } 817 818 int 819 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 820 int len) 821 { 822 usb_device_request_t req; 823 824 req.bmRequestType = UT_READ_VENDOR_DEVICE; 825 req.bRequest = R92C_REQ_REGS; 826 USETW(req.wValue, addr); 827 USETW(req.wIndex, 0); 828 USETW(req.wLength, len); 829 return (usbd_do_request(sc->sc_udev, &req, buf)); 830 } 831 832 uint8_t 833 urtwn_read_1(void *cookie, uint16_t addr) 834 { 835 struct urtwn_softc *sc = cookie; 836 uint8_t val; 837 838 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 839 return (0xff); 840 return (val); 841 } 842 843 uint16_t 844 urtwn_read_2(void *cookie, uint16_t addr) 845 { 846 struct urtwn_softc *sc = cookie; 847 uint16_t val; 848 849 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 850 return (0xffff); 851 return (letoh16(val)); 852 } 853 854 uint32_t 855 urtwn_read_4(void *cookie, uint16_t addr) 856 { 857 struct urtwn_softc *sc = cookie; 858 uint32_t val; 859 860 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 861 return (0xffffffff); 862 return (letoh32(val)); 863 } 864 865 int 866 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 867 { 868 int ntries; 869 870 urtwn_write_4(sc, R92C_LLT_INIT, 871 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 872 SM(R92C_LLT_INIT_ADDR, addr) | 873 SM(R92C_LLT_INIT_DATA, data)); 874 /* Wait for write operation to complete. */ 875 for (ntries = 0; ntries < 20; ntries++) { 876 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 877 R92C_LLT_INIT_OP_NO_ACTIVE) 878 return (0); 879 DELAY(5); 880 } 881 return (ETIMEDOUT); 882 } 883 884 void 885 urtwn_calib_to(void *arg) 886 { 887 struct urtwn_softc *sc = arg; 888 889 if (usbd_is_dying(sc->sc_udev)) 890 return; 891 892 usbd_ref_incr(sc->sc_udev); 893 894 /* Do it in a process context. */ 895 urtwn_do_async(sc, urtwn_calib_cb, NULL, 0); 896 897 usbd_ref_decr(sc->sc_udev); 898 } 899 900 /* ARGSUSED */ 901 void 902 urtwn_calib_cb(struct urtwn_softc *sc, void *arg) 903 { 904 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 905 int s; 906 907 s = splnet(); 908 if (ic->ic_opmode == IEEE80211_M_STA) { 909 ieee80211_amrr_choose(&sc->amrr, ic->ic_bss, &sc->amn); 910 } 911 splx(s); 912 913 rtwn_calib(&sc->sc_sc); 914 } 915 916 void 917 urtwn_next_calib(void *cookie) 918 { 919 struct urtwn_softc *sc = cookie; 920 921 if (!usbd_is_dying(sc->sc_udev)) 922 timeout_add_sec(&sc->calib_to, 2); 923 } 924 925 void 926 urtwn_cancel_calib(void *cookie) 927 { 928 struct urtwn_softc *sc = cookie; 929 930 if (timeout_initialized(&sc->calib_to)) 931 timeout_del(&sc->calib_to); 932 } 933 934 void 935 urtwn_scan_to(void *arg) 936 { 937 struct urtwn_softc *sc = arg; 938 939 if (usbd_is_dying(sc->sc_udev)) 940 return; 941 942 usbd_ref_incr(sc->sc_udev); 943 rtwn_next_scan(&sc->sc_sc); 944 usbd_ref_decr(sc->sc_udev); 945 } 946 947 void 948 urtwn_next_scan(void *arg) 949 { 950 struct urtwn_softc *sc = arg; 951 952 if (!usbd_is_dying(sc->sc_udev)) 953 timeout_add_msec(&sc->scan_to, 200); 954 } 955 956 void 957 urtwn_cancel_scan(void *cookie) 958 { 959 struct urtwn_softc *sc = cookie; 960 961 if (timeout_initialized(&sc->scan_to)) 962 timeout_del(&sc->scan_to); 963 } 964 965 int 966 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 967 { 968 struct rtwn_softc *sc_sc = ic->ic_softc; 969 struct device *self = sc_sc->sc_pdev; 970 struct urtwn_softc *sc = (struct urtwn_softc *)self; 971 struct urtwn_cmd_newstate cmd; 972 973 /* Do it in a process context. */ 974 cmd.state = nstate; 975 cmd.arg = arg; 976 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 977 return (0); 978 } 979 980 void 981 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 982 { 983 struct urtwn_cmd_newstate *cmd = arg; 984 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 985 986 rtwn_newstate(ic, cmd->state, cmd->arg); 987 } 988 989 void 990 urtwn_updateslot(struct ieee80211com *ic) 991 { 992 struct rtwn_softc *sc_sc = ic->ic_softc; 993 struct device *self = sc_sc->sc_pdev; 994 struct urtwn_softc *sc = (struct urtwn_softc *)self; 995 996 /* Do it in a process context. */ 997 urtwn_do_async(sc, urtwn_updateslot_cb, NULL, 0); 998 } 999 1000 /* ARGSUSED */ 1001 void 1002 urtwn_updateslot_cb(struct urtwn_softc *sc, void *arg) 1003 { 1004 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1005 1006 rtwn_updateslot(ic); 1007 } 1008 1009 void 1010 urtwn_updateedca(struct ieee80211com *ic) 1011 { 1012 struct rtwn_softc *sc_sc = ic->ic_softc; 1013 struct device *self = sc_sc->sc_pdev; 1014 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1015 1016 /* Do it in a process context. */ 1017 urtwn_do_async(sc, urtwn_updateedca_cb, NULL, 0); 1018 } 1019 1020 /* ARGSUSED */ 1021 void 1022 urtwn_updateedca_cb(struct urtwn_softc *sc, void *arg) 1023 { 1024 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1025 1026 rtwn_updateedca(ic); 1027 } 1028 1029 int 1030 urtwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1031 struct ieee80211_key *k) 1032 { 1033 struct rtwn_softc *sc_sc = ic->ic_softc; 1034 struct device *self = sc_sc->sc_pdev; 1035 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1036 struct urtwn_cmd_key cmd; 1037 1038 /* Only handle keys for CCMP */ 1039 if (k->k_cipher != IEEE80211_CIPHER_CCMP) 1040 return ieee80211_set_key(ic, ni, k); 1041 1042 /* Defer setting of WEP keys until interface is brought up. */ 1043 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 1044 (IFF_UP | IFF_RUNNING)) 1045 return (0); 1046 1047 /* Do it in a process context. */ 1048 cmd.key = *k; 1049 cmd.ni = ni; 1050 urtwn_do_async(sc, urtwn_set_key_cb, &cmd, sizeof(cmd)); 1051 sc->sc_key_tasks++; 1052 1053 return (EBUSY); 1054 } 1055 1056 void 1057 urtwn_set_key_cb(struct urtwn_softc *sc, void *arg) 1058 { 1059 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1060 struct urtwn_cmd_key *cmd = arg; 1061 1062 sc->sc_key_tasks--; 1063 1064 if (rtwn_set_key(ic, cmd->ni, &cmd->key) == 0) { 1065 if (sc->sc_key_tasks == 0) { 1066 DPRINTF(("marking port %s valid\n", 1067 ether_sprintf(cmd->ni->ni_macaddr))); 1068 cmd->ni->ni_port_valid = 1; 1069 ieee80211_set_link_state(ic, LINK_STATE_UP); 1070 } 1071 } else { 1072 IEEE80211_SEND_MGMT(ic, cmd->ni, IEEE80211_FC0_SUBTYPE_DEAUTH, 1073 IEEE80211_REASON_AUTH_LEAVE); 1074 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1075 } 1076 } 1077 1078 void 1079 urtwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1080 struct ieee80211_key *k) 1081 { 1082 struct rtwn_softc *sc_sc = ic->ic_softc; 1083 struct device *self = sc_sc->sc_pdev; 1084 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1085 struct urtwn_cmd_key cmd; 1086 1087 /* Only handle keys for CCMP */ 1088 if (k->k_cipher != IEEE80211_CIPHER_CCMP) { 1089 ieee80211_delete_key(ic, ni, k); 1090 return; 1091 } 1092 1093 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 1094 ic->ic_state != IEEE80211_S_RUN) 1095 return; /* Nothing to do. */ 1096 1097 /* Do it in a process context. */ 1098 cmd.key = *k; 1099 cmd.ni = ni; 1100 urtwn_do_async(sc, urtwn_delete_key_cb, &cmd, sizeof(cmd)); 1101 } 1102 1103 void 1104 urtwn_delete_key_cb(struct urtwn_softc *sc, void *arg) 1105 { 1106 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1107 struct urtwn_cmd_key *cmd = arg; 1108 1109 rtwn_delete_key(ic, cmd->ni, &cmd->key); 1110 } 1111 1112 int 1113 urtwn_ccmp_decap(struct urtwn_softc *sc, struct mbuf *m, 1114 struct ieee80211_node *ni) 1115 { 1116 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1117 struct ieee80211_key *k; 1118 struct ieee80211_frame *wh; 1119 uint64_t pn, *prsc; 1120 uint8_t *ivp; 1121 uint8_t tid; 1122 int hdrlen, hasqos; 1123 1124 k = ieee80211_get_rxkey(ic, m, ni); 1125 if (k == NULL) 1126 return 1; 1127 1128 wh = mtod(m, struct ieee80211_frame *); 1129 hdrlen = ieee80211_get_hdrlen(wh); 1130 ivp = (uint8_t *)wh + hdrlen; 1131 1132 /* Check that ExtIV bit is set. */ 1133 if (!(ivp[3] & IEEE80211_WEP_EXTIV)) 1134 return 1; 1135 1136 hasqos = ieee80211_has_qos(wh); 1137 tid = hasqos ? ieee80211_get_qos(wh) & IEEE80211_QOS_TID : 0; 1138 prsc = &k->k_rsc[tid]; 1139 1140 /* Extract the 48-bit PN from the CCMP header. */ 1141 pn = (uint64_t)ivp[0] | 1142 (uint64_t)ivp[1] << 8 | 1143 (uint64_t)ivp[4] << 16 | 1144 (uint64_t)ivp[5] << 24 | 1145 (uint64_t)ivp[6] << 32 | 1146 (uint64_t)ivp[7] << 40; 1147 if (pn <= *prsc) { 1148 ic->ic_stats.is_ccmp_replays++; 1149 return 1; 1150 } 1151 /* Last seen packet number is updated in ieee80211_inputm(). */ 1152 1153 /* Strip MIC. IV will be stripped by ieee80211_inputm(). */ 1154 m_adj(m, -IEEE80211_CCMP_MICLEN); 1155 return 0; 1156 } 1157 1158 void 1159 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, 1160 struct mbuf_list *ml) 1161 { 1162 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1163 struct ifnet *ifp = &ic->ic_if; 1164 struct ieee80211_rxinfo rxi; 1165 struct ieee80211_frame *wh; 1166 struct ieee80211_node *ni; 1167 struct r92c_rx_desc_usb *rxd; 1168 uint32_t rxdw0, rxdw3; 1169 struct mbuf *m; 1170 uint8_t rate; 1171 int8_t rssi = 0; 1172 int s, infosz; 1173 1174 rxd = (struct r92c_rx_desc_usb *)buf; 1175 rxdw0 = letoh32(rxd->rxdw0); 1176 rxdw3 = letoh32(rxd->rxdw3); 1177 1178 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1179 /* 1180 * This should not happen since we setup our Rx filter 1181 * to not receive these frames. 1182 */ 1183 ifp->if_ierrors++; 1184 return; 1185 } 1186 if (__predict_false(pktlen < sizeof(*wh) || pktlen > MCLBYTES)) { 1187 ifp->if_ierrors++; 1188 return; 1189 } 1190 1191 rate = MS(rxdw3, R92C_RXDW3_RATE); 1192 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1193 1194 /* Get RSSI from PHY status descriptor if present. */ 1195 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1196 rssi = rtwn_get_rssi(&sc->sc_sc, rate, &rxd[1]); 1197 /* Update our average RSSI. */ 1198 rtwn_update_avgrssi(&sc->sc_sc, rate, rssi); 1199 } 1200 1201 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 1202 pktlen, rate, infosz, rssi)); 1203 1204 MGETHDR(m, M_DONTWAIT, MT_DATA); 1205 if (__predict_false(m == NULL)) { 1206 ifp->if_ierrors++; 1207 return; 1208 } 1209 if (pktlen > MHLEN) { 1210 MCLGET(m, M_DONTWAIT); 1211 if (__predict_false(!(m->m_flags & M_EXT))) { 1212 ifp->if_ierrors++; 1213 m_freem(m); 1214 return; 1215 } 1216 } 1217 /* Finalize mbuf. */ 1218 wh = (struct ieee80211_frame *)((uint8_t *)&rxd[1] + infosz); 1219 memcpy(mtod(m, uint8_t *), wh, pktlen); 1220 m->m_pkthdr.len = m->m_len = pktlen; 1221 1222 s = splnet(); 1223 #if NBPFILTER > 0 1224 if (__predict_false(sc->sc_drvbpf != NULL)) { 1225 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1226 struct mbuf mb; 1227 1228 tap->wr_flags = 0; 1229 /* Map HW rate index to 802.11 rate. */ 1230 if (!(rxdw3 & R92C_RXDW3_HT)) { 1231 switch (rate) { 1232 /* CCK. */ 1233 case 0: tap->wr_rate = 2; break; 1234 case 1: tap->wr_rate = 4; break; 1235 case 2: tap->wr_rate = 11; break; 1236 case 3: tap->wr_rate = 22; break; 1237 /* OFDM. */ 1238 case 4: tap->wr_rate = 12; break; 1239 case 5: tap->wr_rate = 18; break; 1240 case 6: tap->wr_rate = 24; break; 1241 case 7: tap->wr_rate = 36; break; 1242 case 8: tap->wr_rate = 48; break; 1243 case 9: tap->wr_rate = 72; break; 1244 case 10: tap->wr_rate = 96; break; 1245 case 11: tap->wr_rate = 108; break; 1246 } 1247 if (rate <= 3) 1248 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1249 } else if (rate >= 12) { /* MCS0~15. */ 1250 /* Bit 7 set means HT MCS instead of rate. */ 1251 tap->wr_rate = 0x80 | (rate - 12); 1252 } 1253 tap->wr_dbm_antsignal = rssi; 1254 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1255 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1256 1257 mb.m_data = (caddr_t)tap; 1258 mb.m_len = sc->sc_rxtap_len; 1259 mb.m_next = m; 1260 mb.m_nextpkt = NULL; 1261 mb.m_type = 0; 1262 mb.m_flags = 0; 1263 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1264 } 1265 #endif 1266 1267 ni = ieee80211_find_rxnode(ic, wh); 1268 memset(&rxi, 0, sizeof(rxi)); 1269 rxi.rxi_rssi = rssi; 1270 1271 /* Handle hardware decryption. */ 1272 if (((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) 1273 && (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && 1274 (ni->ni_flags & IEEE80211_NODE_RXPROT) && 1275 ((!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1276 ni->ni_pairwise_key.k_cipher == IEEE80211_CIPHER_CCMP) || 1277 (IEEE80211_IS_MULTICAST(wh->i_addr1) && 1278 ni->ni_rsngroupcipher == IEEE80211_CIPHER_CCMP))) { 1279 if (urtwn_ccmp_decap(sc, m, ni) != 0) { 1280 ifp->if_ierrors++; 1281 m_freem(m); 1282 ieee80211_release_node(ic, ni); 1283 splx(s); 1284 return; 1285 } 1286 rxi.rxi_flags |= IEEE80211_RXI_HWDEC; 1287 } 1288 1289 ieee80211_inputm(ifp, m, ni, &rxi, ml); 1290 /* Node is no longer needed. */ 1291 ieee80211_release_node(ic, ni); 1292 splx(s); 1293 } 1294 1295 void 1296 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, 1297 usbd_status status) 1298 { 1299 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1300 struct urtwn_rx_data *data = priv; 1301 struct urtwn_softc *sc = data->sc; 1302 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1303 struct r92c_rx_desc_usb *rxd; 1304 uint32_t rxdw0; 1305 uint8_t *buf; 1306 int len, totlen, pktlen, infosz, npkts, error, align; 1307 1308 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1309 DPRINTF(("RX status=%d\n", status)); 1310 if (status == USBD_STALLED) 1311 usbd_clear_endpoint_stall_async(sc->rx_pipe); 1312 if (status != USBD_CANCELLED) 1313 goto resubmit; 1314 return; 1315 } 1316 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 1317 1318 if (__predict_false(len < sizeof(*rxd))) { 1319 DPRINTF(("xfer too short %d\n", len)); 1320 goto resubmit; 1321 } 1322 buf = data->buf; 1323 1324 /* Get the number of encapsulated frames. */ 1325 rxd = (struct r92c_rx_desc_usb *)buf; 1326 npkts = MS(letoh32(rxd->rxdw2), R92C_RXDW2_PKTCNT); 1327 DPRINTFN(4, ("Rx %d frames in one chunk\n", npkts)); 1328 1329 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1330 int ntries, type; 1331 struct r88e_tx_rpt_ccx *rxstat; 1332 1333 type = MS(letoh32(rxd->rxdw3), R88E_RXDW3_RPT); 1334 1335 if (type == R88E_RXDW3_RPT_TX1) { 1336 buf += sizeof(struct r92c_rx_desc_usb); 1337 rxstat = (struct r88e_tx_rpt_ccx *)buf; 1338 ntries = MS(letoh32(rxstat->rptb2), 1339 R88E_RPTB2_RETRY_CNT); 1340 1341 if (rxstat->rptb1 & R88E_RPTB1_PKT_OK) 1342 sc->amn.amn_txcnt++; 1343 if (ntries > 0) 1344 sc->amn.amn_retrycnt++; 1345 1346 goto resubmit; 1347 } 1348 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 1349 int type; 1350 struct r92e_c2h_tx_rpt *txrpt; 1351 1352 if (letoh32(rxd->rxdw2) & R92E_RXDW2_RPT_C2H) { 1353 if (len < sizeof(struct r92c_rx_desc_usb) + 2) 1354 goto resubmit; 1355 1356 type = buf[sizeof(struct r92c_rx_desc_usb)]; 1357 switch (type) { 1358 case R92C_C2HEVT_TX_REPORT: 1359 buf += sizeof(struct r92c_rx_desc_usb) + 2; 1360 txrpt = (struct r92e_c2h_tx_rpt *)buf; 1361 if (MS(txrpt->rptb2, R92E_RPTB2_RETRY_CNT) > 0) 1362 sc->amn.amn_retrycnt++; 1363 if ((txrpt->rptb0 & (R92E_RPTB0_RETRY_OVER | 1364 R92E_RPTB0_LIFE_EXPIRE)) == 0) 1365 sc->amn.amn_txcnt++; 1366 break; 1367 default: 1368 break; 1369 } 1370 goto resubmit; 1371 } 1372 } 1373 1374 align = (sc->sc_sc.chip & RTWN_CHIP_92E ? 7 : 127); 1375 1376 /* Process all of them. */ 1377 while (npkts-- > 0) { 1378 if (__predict_false(len < sizeof(*rxd))) 1379 break; 1380 rxd = (struct r92c_rx_desc_usb *)buf; 1381 rxdw0 = letoh32(rxd->rxdw0); 1382 1383 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1384 if (__predict_false(pktlen == 0)) 1385 break; 1386 1387 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1388 1389 /* Make sure everything fits in xfer. */ 1390 totlen = sizeof(*rxd) + infosz + pktlen; 1391 if (__predict_false(totlen > len)) 1392 break; 1393 1394 /* Process 802.11 frame. */ 1395 urtwn_rx_frame(sc, buf, pktlen, &ml); 1396 1397 /* Handle chunk alignment. */ 1398 totlen = (totlen + align) & ~align; 1399 buf += totlen; 1400 len -= totlen; 1401 } 1402 if_input(&ic->ic_if, &ml); 1403 1404 resubmit: 1405 /* Setup a new transfer. */ 1406 usbd_setup_xfer(xfer, sc->rx_pipe, data, data->buf, URTWN_RXBUFSZ, 1407 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, urtwn_rxeof); 1408 error = usbd_transfer(data->xfer); 1409 if (error != 0 && error != USBD_IN_PROGRESS) 1410 DPRINTF(("could not set up new transfer: %d\n", error)); 1411 } 1412 1413 void 1414 urtwn_txeof(struct usbd_xfer *xfer, void *priv, 1415 usbd_status status) 1416 { 1417 struct urtwn_tx_data *data = priv; 1418 struct urtwn_softc *sc = data->sc; 1419 struct ifnet *ifp = &sc->sc_sc.sc_ic.ic_if; 1420 int s; 1421 1422 s = splnet(); 1423 /* Put this Tx buffer back to our free list. */ 1424 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1425 1426 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1427 DPRINTF(("TX status=%d\n", status)); 1428 if (status == USBD_STALLED) 1429 usbd_clear_endpoint_stall_async(data->pipe); 1430 ifp->if_oerrors++; 1431 splx(s); 1432 return; 1433 } 1434 sc->sc_sc.sc_tx_timer = 0; 1435 1436 /* We just released a Tx buffer, notify Tx. */ 1437 if (ifq_is_oactive(&ifp->if_snd)) { 1438 ifq_clr_oactive(&ifp->if_snd); 1439 rtwn_start(ifp); 1440 } 1441 splx(s); 1442 } 1443 1444 void 1445 urtwn_tx_fill_desc(struct urtwn_softc *sc, uint8_t **txdp, struct mbuf *m, 1446 struct ieee80211_frame *wh, struct ieee80211_key *k, 1447 struct ieee80211_node *ni) 1448 { 1449 struct r92c_tx_desc_usb *txd; 1450 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1451 uint8_t raid, type, rtsrate; 1452 uint32_t pktlen; 1453 1454 txd = (struct r92c_tx_desc_usb *)*txdp; 1455 (*txdp) += sizeof(*txd); 1456 memset(txd, 0, sizeof(*txd)); 1457 1458 pktlen = m->m_pkthdr.len; 1459 if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) { 1460 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, 1461 R92C_TXDW1_CIPHER_AES)); 1462 pktlen += IEEE80211_CCMP_HDRLEN; 1463 } 1464 1465 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1466 1467 txd->txdw0 |= htole32( 1468 SM(R92C_TXDW0_PKTLEN, pktlen) | 1469 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1470 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1471 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1472 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1473 1474 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1475 type == IEEE80211_FC0_TYPE_DATA) { 1476 if (ic->ic_curmode == IEEE80211_MODE_11B || 1477 (sc->sc_sc.sc_flags & RTWN_FLAG_FORCE_RAID_11B)) 1478 raid = R92C_RAID_11B; 1479 else 1480 raid = R92C_RAID_11BG; 1481 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1482 txd->txdw1 |= htole32( 1483 SM(R88E_TXDW1_MACID, R92C_MACID_BSS) | 1484 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1485 SM(R92C_TXDW1_RAID, raid)); 1486 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1487 /* Request TX status report for AMRR */ 1488 txd->txdw2 |= htole32(R92C_TXDW2_CCX_RPT); 1489 } else { 1490 txd->txdw1 |= htole32( 1491 SM(R92C_TXDW1_MACID, R92C_MACID_BSS) | 1492 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1493 SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1494 } 1495 1496 if (pktlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 1497 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1498 R92C_TXDW4_HWRTSEN); 1499 } else if (ic->ic_flags & IEEE80211_F_USEPROT) { 1500 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1501 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1502 R92C_TXDW4_HWRTSEN); 1503 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1504 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1505 R92C_TXDW4_HWRTSEN); 1506 } 1507 } 1508 txd->txdw5 |= htole32(0x0001ff00); 1509 1510 if (ic->ic_curmode == IEEE80211_MODE_11B) 1511 rtsrate = 0; /* CCK1 */ 1512 else 1513 rtsrate = 8; /* OFDM24 */ 1514 1515 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1516 /* Use AMRR */ 1517 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1518 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, rtsrate)); 1519 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1520 ni->ni_txrate)); 1521 } else { 1522 /* Send data at OFDM54. */ 1523 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, rtsrate)); 1524 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1525 } 1526 } else { 1527 txd->txdw1 |= htole32( 1528 SM(R92C_TXDW1_MACID, 0) | 1529 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1530 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1531 1532 /* Force CCK1. */ 1533 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1534 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1535 } 1536 /* Set sequence number (already little endian). */ 1537 txd->txdseq |= (*(uint16_t *)wh->i_seq) >> IEEE80211_SEQ_SEQ_SHIFT; 1538 1539 if (!ieee80211_has_qos(wh)) { 1540 /* Use HW sequence numbering for non-QoS frames. */ 1541 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1542 txd->txdseq |= htole16(R92C_TXDW3_HWSEQEN); 1543 } else 1544 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1545 } 1546 1547 void 1548 urtwn_tx_fill_desc_gen2(struct urtwn_softc *sc, uint8_t **txdp, struct mbuf *m, 1549 struct ieee80211_frame *wh, struct ieee80211_key *k, 1550 struct ieee80211_node *ni) 1551 { 1552 struct r92e_tx_desc_usb *txd; 1553 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1554 uint8_t raid, type; 1555 uint32_t pktlen; 1556 1557 txd = (struct r92e_tx_desc_usb *)*txdp; 1558 (*txdp) += sizeof(*txd); 1559 memset(txd, 0, sizeof(*txd)); 1560 1561 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1562 1563 pktlen = m->m_pkthdr.len; 1564 if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) { 1565 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, 1566 R92C_TXDW1_CIPHER_AES)); 1567 pktlen += IEEE80211_CCMP_HDRLEN; 1568 } 1569 1570 txd->txdw0 |= htole32( 1571 SM(R92C_TXDW0_PKTLEN, pktlen) | 1572 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1573 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1574 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1575 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1576 1577 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1578 type == IEEE80211_FC0_TYPE_DATA) { 1579 if (ic->ic_curmode == IEEE80211_MODE_11B || 1580 (sc->sc_sc.sc_flags & RTWN_FLAG_FORCE_RAID_11B)) 1581 raid = R92E_RAID_11B; 1582 else 1583 raid = R92E_RAID_11BG; 1584 txd->txdw1 |= htole32( 1585 SM(R92E_TXDW1_MACID, R92C_MACID_BSS) | 1586 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1587 SM(R92C_TXDW1_RAID, raid)); 1588 /* Request TX status report for AMRR */ 1589 txd->txdw2 |= htole32(R92C_TXDW2_CCX_RPT | R88E_TXDW2_AGGBK); 1590 1591 if (pktlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 1592 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1593 R92C_TXDW4_HWRTSEN); 1594 } else if (ic->ic_flags & IEEE80211_F_USEPROT) { 1595 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1596 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1597 R92C_TXDW4_HWRTSEN); 1598 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1599 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1600 R92C_TXDW4_HWRTSEN); 1601 } 1602 } 1603 txd->txdw5 |= htole32(0x0001ff00); 1604 1605 /* Use AMRR */ 1606 txd->txdw3 |= htole32(R92E_TXDW3_DRVRATE); 1607 txd->txdw4 |= htole32(SM(R92E_TXDW4_RTSRATE, 8)); 1608 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATE, ni->ni_txrate)); 1609 } else { 1610 txd->txdw1 |= htole32( 1611 SM(R92E_TXDW1_MACID, 0) | 1612 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1613 SM(R92C_TXDW1_RAID, R92E_RAID_11B)); 1614 1615 /* Force CCK1. */ 1616 txd->txdw3 |= htole32(R92E_TXDW3_DRVRATE); 1617 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATE, 0)); 1618 } 1619 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATEFB, 0x1f)); 1620 1621 txd->txdseq2 |= htole16(SM(R92E_TXDSEQ2_HWSEQ, *(uint16_t *)wh->i_seq)); 1622 1623 if (!ieee80211_has_qos(wh)) { 1624 /* Use HW sequence numbering for non-QoS frames. */ 1625 txd->txdw7 |= htole16(R92C_TXDW3_HWSEQEN); 1626 } 1627 } 1628 1629 int 1630 urtwn_tx(void *cookie, struct mbuf *m, struct ieee80211_node *ni) 1631 { 1632 struct urtwn_softc *sc = cookie; 1633 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1634 struct ieee80211_frame *wh; 1635 struct ieee80211_key *k = NULL; 1636 struct urtwn_tx_data *data; 1637 struct usbd_pipe *pipe; 1638 uint16_t qos, sum; 1639 uint8_t tid, qid; 1640 int i, xferlen, error, headerlen; 1641 uint8_t *txdp; 1642 1643 wh = mtod(m, struct ieee80211_frame *); 1644 1645 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1646 k = ieee80211_get_txkey(ic, wh, ni); 1647 if (k->k_cipher != IEEE80211_CIPHER_CCMP) { 1648 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1649 return (ENOBUFS); 1650 wh = mtod(m, struct ieee80211_frame *); 1651 } 1652 } 1653 1654 if (ieee80211_has_qos(wh)) { 1655 qos = ieee80211_get_qos(wh); 1656 tid = qos & IEEE80211_QOS_TID; 1657 qid = ieee80211_up_to_ac(ic, tid); 1658 } else if ((wh->i_fc[1] & IEEE80211_FC0_TYPE_MASK) 1659 != IEEE80211_FC0_TYPE_DATA) { 1660 /* Use AC VO for management frames. */ 1661 qid = EDCA_AC_VO; 1662 } else 1663 qid = EDCA_AC_BE; 1664 1665 /* Get the USB pipe to use for this AC. */ 1666 pipe = sc->tx_pipe[sc->ac2idx[qid]]; 1667 1668 /* Grab a Tx buffer from our free list. */ 1669 data = TAILQ_FIRST(&sc->tx_free_list); 1670 TAILQ_REMOVE(&sc->tx_free_list, data, next); 1671 1672 /* Fill Tx descriptor. */ 1673 txdp = data->buf; 1674 if (sc->sc_sc.chip & RTWN_CHIP_92E) 1675 urtwn_tx_fill_desc_gen2(sc, &txdp, m, wh, k, ni); 1676 else 1677 urtwn_tx_fill_desc(sc, &txdp, m, wh, k, ni); 1678 1679 /* Compute Tx descriptor checksum. */ 1680 sum = 0; 1681 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 1682 sum ^= ((uint16_t *)data->buf)[i]; 1683 ((uint16_t *)data->buf)[R92C_TXDESC_SUMOFFSET] = sum; 1684 1685 #if NBPFILTER > 0 1686 if (__predict_false(sc->sc_drvbpf != NULL)) { 1687 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1688 struct mbuf mb; 1689 1690 tap->wt_flags = 0; 1691 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1692 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1693 1694 mb.m_data = (caddr_t)tap; 1695 mb.m_len = sc->sc_txtap_len; 1696 mb.m_next = m; 1697 mb.m_nextpkt = NULL; 1698 mb.m_type = 0; 1699 mb.m_flags = 0; 1700 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1701 } 1702 #endif 1703 1704 if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) { 1705 xferlen = (txdp - data->buf) + m->m_pkthdr.len + 1706 IEEE80211_CCMP_HDRLEN; 1707 headerlen = ieee80211_get_hdrlen(wh); 1708 1709 m_copydata(m, 0, headerlen, txdp); 1710 txdp += headerlen; 1711 1712 k->k_tsc++; 1713 txdp[0] = k->k_tsc; 1714 txdp[1] = k->k_tsc >> 8; 1715 txdp[2] = 0; 1716 txdp[3] = k->k_id | IEEE80211_WEP_EXTIV; 1717 txdp[4] = k->k_tsc >> 16; 1718 txdp[5] = k->k_tsc >> 24; 1719 txdp[6] = k->k_tsc >> 32; 1720 txdp[7] = k->k_tsc >> 40; 1721 txdp += IEEE80211_CCMP_HDRLEN; 1722 1723 m_copydata(m, headerlen, m->m_pkthdr.len - headerlen, txdp); 1724 m_freem(m); 1725 } else { 1726 xferlen = (txdp - data->buf) + m->m_pkthdr.len; 1727 m_copydata(m, 0, m->m_pkthdr.len, txdp); 1728 m_freem(m); 1729 } 1730 1731 data->pipe = pipe; 1732 usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen, 1733 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTWN_TX_TIMEOUT, 1734 urtwn_txeof); 1735 error = usbd_transfer(data->xfer); 1736 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) { 1737 /* Put this Tx buffer back to our free list. */ 1738 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1739 return (error); 1740 } 1741 ieee80211_release_node(ic, ni); 1742 return (0); 1743 } 1744 1745 int 1746 urtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1747 { 1748 struct rtwn_softc *sc_sc = ifp->if_softc; 1749 struct device *self = sc_sc->sc_pdev; 1750 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1751 int error; 1752 1753 if (usbd_is_dying(sc->sc_udev)) 1754 return ENXIO; 1755 1756 usbd_ref_incr(sc->sc_udev); 1757 error = rtwn_ioctl(ifp, cmd, data); 1758 usbd_ref_decr(sc->sc_udev); 1759 1760 return (error); 1761 } 1762 1763 int 1764 urtwn_r92c_power_on(struct urtwn_softc *sc) 1765 { 1766 uint32_t reg; 1767 int ntries; 1768 1769 /* Wait for autoload done bit. */ 1770 for (ntries = 0; ntries < 1000; ntries++) { 1771 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 1772 break; 1773 DELAY(5); 1774 } 1775 if (ntries == 1000) { 1776 printf("%s: timeout waiting for chip autoload\n", 1777 sc->sc_dev.dv_xname); 1778 return (ETIMEDOUT); 1779 } 1780 1781 /* Unlock ISO/CLK/Power control register. */ 1782 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 1783 /* Move SPS into PWM mode. */ 1784 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 1785 DELAY(100); 1786 1787 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 1788 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 1789 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 1790 reg | R92C_LDOV12D_CTRL_LDV12_EN); 1791 DELAY(100); 1792 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 1793 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 1794 ~R92C_SYS_ISO_CTRL_MD2PP); 1795 } 1796 1797 /* Auto enable WLAN. */ 1798 urtwn_write_2(sc, R92C_APS_FSMCO, 1799 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1800 for (ntries = 0; ntries < 1000; ntries++) { 1801 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1802 R92C_APS_FSMCO_APFM_ONMAC)) 1803 break; 1804 DELAY(5); 1805 } 1806 if (ntries == 1000) { 1807 printf("%s: timeout waiting for MAC auto ON\n", 1808 sc->sc_dev.dv_xname); 1809 return (ETIMEDOUT); 1810 } 1811 1812 /* Enable radio, GPIO and LED functions. */ 1813 urtwn_write_2(sc, R92C_APS_FSMCO, 1814 R92C_APS_FSMCO_AFSM_HSUS | 1815 R92C_APS_FSMCO_PDN_EN | 1816 R92C_APS_FSMCO_PFM_ALDN); 1817 /* Release RF digital isolation. */ 1818 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1819 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 1820 1821 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1822 reg = urtwn_read_2(sc, R92C_CR); 1823 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1824 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1825 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 1826 R92C_CR_ENSEC; 1827 urtwn_write_2(sc, R92C_CR, reg); 1828 1829 urtwn_write_1(sc, 0xfe10, 0x19); 1830 return (0); 1831 } 1832 1833 int 1834 urtwn_r92e_power_on(struct urtwn_softc *sc) 1835 { 1836 uint32_t reg; 1837 int ntries; 1838 1839 if (urtwn_read_4(sc, R92C_SYS_CFG) & R92E_SYS_CFG_SPSLDO_SEL) { 1840 /* LDO. */ 1841 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 1842 } else { 1843 reg = urtwn_read_4(sc, R92C_SYS_SWR_CTRL2); 1844 reg &= 0xff0fffff; 1845 reg |= 0x00500000; 1846 urtwn_write_4(sc, R92C_SYS_SWR_CTRL2, reg); 1847 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 1848 } 1849 1850 /* 40MHz crystal source */ 1851 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 1852 urtwn_read_1(sc, R92C_AFE_PLL_CTRL) & 0xfb); 1853 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL_EXT, 1854 urtwn_read_4(sc, R92C_AFE_XTAL_CTRL_EXT) & 0xfffffc7f); 1855 1856 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 1857 urtwn_read_1(sc, R92C_AFE_PLL_CTRL) & 0xbf); 1858 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL_EXT, 1859 urtwn_read_4(sc, R92C_AFE_XTAL_CTRL_EXT) & 0xffdfffff); 1860 1861 /* Disable HWPDN. */ 1862 urtwn_write_2(sc, R92C_APS_FSMCO, 1863 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 1864 for (ntries = 0; ntries < 5000; ntries++) { 1865 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 1866 break; 1867 DELAY(10); 1868 } 1869 if (ntries == 5000) { 1870 printf("%s: timeout waiting for chip power up\n", 1871 sc->sc_dev.dv_xname); 1872 return (ETIMEDOUT); 1873 } 1874 1875 /* Disable WL suspend. */ 1876 urtwn_write_2(sc, R92C_APS_FSMCO, 1877 urtwn_read_2(sc, R92C_APS_FSMCO) & 1878 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 1879 1880 /* Auto enable WLAN. */ 1881 urtwn_write_4(sc, R92C_APS_FSMCO, 1882 urtwn_read_4(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 1883 urtwn_write_2(sc, R92C_APS_FSMCO, 1884 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1885 for (ntries = 0; ntries < 5000; ntries++) { 1886 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1887 R92C_APS_FSMCO_APFM_ONMAC)) 1888 break; 1889 DELAY(10); 1890 } 1891 if (ntries == 5000) { 1892 printf("%s: timeout waiting for MAC auto ON\n", 1893 sc->sc_dev.dv_xname); 1894 return (ETIMEDOUT); 1895 } 1896 1897 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1898 urtwn_write_2(sc, R92C_CR, 0); 1899 reg = urtwn_read_2(sc, R92C_CR); 1900 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1901 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1902 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 1903 urtwn_write_2(sc, R92C_CR, reg); 1904 return (0); 1905 } 1906 1907 int 1908 urtwn_r88e_power_on(struct urtwn_softc *sc) 1909 { 1910 uint32_t reg; 1911 int ntries; 1912 1913 /* Wait for power ready bit. */ 1914 for (ntries = 0; ntries < 5000; ntries++) { 1915 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 1916 break; 1917 DELAY(10); 1918 } 1919 if (ntries == 5000) { 1920 printf("%s: timeout waiting for chip power up\n", 1921 sc->sc_dev.dv_xname); 1922 return (ETIMEDOUT); 1923 } 1924 1925 /* Reset BB. */ 1926 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 1927 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 1928 R92C_SYS_FUNC_EN_BB_GLB_RST)); 1929 1930 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 1931 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 1932 1933 /* Disable HWPDN. */ 1934 urtwn_write_2(sc, R92C_APS_FSMCO, 1935 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 1936 /* Disable WL suspend. */ 1937 urtwn_write_2(sc, R92C_APS_FSMCO, 1938 urtwn_read_2(sc, R92C_APS_FSMCO) & 1939 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 1940 1941 /* Auto enable WLAN. */ 1942 urtwn_write_2(sc, R92C_APS_FSMCO, 1943 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1944 for (ntries = 0; ntries < 5000; ntries++) { 1945 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1946 R92C_APS_FSMCO_APFM_ONMAC)) 1947 break; 1948 DELAY(10); 1949 } 1950 if (ntries == 5000) { 1951 printf("%s: timeout waiting for MAC auto ON\n", 1952 sc->sc_dev.dv_xname); 1953 return (ETIMEDOUT); 1954 } 1955 1956 /* Enable LDO normal mode. */ 1957 urtwn_write_1(sc, R92C_LPLDO_CTRL, 1958 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 1959 1960 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1961 urtwn_write_2(sc, R92C_CR, 0); 1962 reg = urtwn_read_2(sc, R92C_CR); 1963 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1964 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1965 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 1966 urtwn_write_2(sc, R92C_CR, reg); 1967 return (0); 1968 } 1969 1970 int 1971 urtwn_llt_init(struct urtwn_softc *sc, int page_count) 1972 { 1973 int i, error, pktbuf_count; 1974 1975 pktbuf_count = (sc->sc_sc.chip & RTWN_CHIP_88E) ? 1976 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 1977 1978 /* Reserve pages [0; page_count]. */ 1979 for (i = 0; i < page_count; i++) { 1980 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1981 return (error); 1982 } 1983 /* NB: 0xff indicates end-of-list. */ 1984 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 1985 return (error); 1986 /* 1987 * Use pages [page_count + 1; pktbuf_count - 1] 1988 * as ring buffer. 1989 */ 1990 for (++i; i < pktbuf_count - 1; i++) { 1991 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1992 return (error); 1993 } 1994 /* Make the last page point to the beginning of the ring buffer. */ 1995 error = urtwn_llt_write(sc, i, page_count + 1); 1996 return (error); 1997 } 1998 1999 int 2000 urtwn_auto_llt_init(struct urtwn_softc *sc) 2001 { 2002 int ntries; 2003 2004 urtwn_write_4(sc, R92E_AUTO_LLT, urtwn_read_4(sc, 2005 R92E_AUTO_LLT) | R92E_AUTO_LLT_EN); 2006 for (ntries = 0; ntries < 1000; ntries++) { 2007 if (!(urtwn_read_4(sc, R92E_AUTO_LLT) & R92E_AUTO_LLT_EN)) 2008 return (0); 2009 DELAY(2); 2010 } 2011 2012 return (ETIMEDOUT); 2013 } 2014 2015 int 2016 urtwn_fw_loadpage(void *cookie, int page, uint8_t *buf, int len) 2017 { 2018 struct urtwn_softc *sc = cookie; 2019 uint32_t reg; 2020 int off, mlen, error = 0; 2021 2022 reg = urtwn_read_4(sc, R92C_MCUFWDL); 2023 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2024 urtwn_write_4(sc, R92C_MCUFWDL, reg); 2025 2026 off = R92C_FW_START_ADDR; 2027 while (len > 0) { 2028 if (len > 196) 2029 mlen = 196; 2030 else if (len > 4) 2031 mlen = 4; 2032 else 2033 mlen = 1; 2034 error = urtwn_write_region_1(sc, off, buf, mlen); 2035 if (error != 0) 2036 break; 2037 off += mlen; 2038 buf += mlen; 2039 len -= mlen; 2040 } 2041 return (error); 2042 } 2043 2044 int 2045 urtwn_load_firmware(void *cookie, u_char **fw, size_t *len) 2046 { 2047 struct urtwn_softc *sc = cookie; 2048 const char *name; 2049 int error; 2050 2051 if (sc->sc_sc.chip & RTWN_CHIP_92E) 2052 name = "urtwn-rtl8192eu"; 2053 else if (sc->sc_sc.chip & RTWN_CHIP_88E) 2054 name = "urtwn-rtl8188eu"; 2055 else if ((sc->sc_sc.chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2056 RTWN_CHIP_UMC_A_CUT) 2057 name = "urtwn-rtl8192cU"; 2058 else 2059 name = "urtwn-rtl8192cT"; 2060 2061 error = loadfirmware(name, fw, len); 2062 if (error) 2063 printf("%s: could not read firmware %s (error %d)\n", 2064 sc->sc_dev.dv_xname, name, error); 2065 return (error); 2066 } 2067 2068 int 2069 urtwn_dma_init(void *cookie) 2070 { 2071 struct urtwn_softc *sc = cookie; 2072 uint32_t reg; 2073 uint16_t dmasize; 2074 int hqpages, lqpages, nqpages, pagecnt, boundary; 2075 int error, hashq, haslq, hasnq; 2076 2077 /* Default initialization of chipset values. */ 2078 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2079 hqpages = R88E_HQ_NPAGES; 2080 lqpages = R88E_LQ_NPAGES; 2081 nqpages = R88E_NQ_NPAGES; 2082 pagecnt = R88E_TX_PAGE_COUNT; 2083 boundary = R88E_TX_PAGE_BOUNDARY; 2084 dmasize = R88E_MAX_RX_DMA_SIZE; 2085 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2086 hqpages = R92E_HQ_NPAGES; 2087 lqpages = R92E_LQ_NPAGES; 2088 nqpages = R92E_NQ_NPAGES; 2089 pagecnt = R92E_TX_PAGE_COUNT; 2090 boundary = R92E_TX_PAGE_BOUNDARY; 2091 dmasize = R92E_MAX_RX_DMA_SIZE; 2092 } else { 2093 hqpages = R92C_HQ_NPAGES; 2094 lqpages = R92C_LQ_NPAGES; 2095 nqpages = R92C_NQ_NPAGES; 2096 pagecnt = R92C_TX_PAGE_COUNT; 2097 boundary = R92C_TX_PAGE_BOUNDARY; 2098 dmasize = R92C_MAX_RX_DMA_SIZE; 2099 } 2100 2101 /* Initialize LLT table. */ 2102 if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2103 error = urtwn_auto_llt_init(sc); 2104 } else { 2105 error = urtwn_llt_init(sc, pagecnt); 2106 } 2107 if (error != 0) 2108 return (error); 2109 2110 /* Get Tx queues to USB endpoints mapping. */ 2111 hashq = hasnq = haslq = 0; 2112 switch (sc->ntx) { 2113 case 3: 2114 haslq = 1; 2115 pagecnt -= lqpages; 2116 /* FALLTHROUGH */ 2117 case 2: 2118 hasnq = 1; 2119 pagecnt -= nqpages; 2120 /* FALLTHROUGH */ 2121 case 1: 2122 hashq = 1; 2123 pagecnt -= hqpages; 2124 break; 2125 } 2126 2127 /* Set number of pages for normal priority queue. */ 2128 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2129 urtwn_write_4(sc, R92C_RQPN, 2130 /* Set number of pages for public queue. */ 2131 SM(R92C_RQPN_PUBQ, pagecnt) | 2132 /* Set number of pages for high priority queue. */ 2133 SM(R92C_RQPN_HPQ, hashq ? hqpages : 0) | 2134 /* Set number of pages for low priority queue. */ 2135 SM(R92C_RQPN_LPQ, haslq ? lqpages : 0) | 2136 /* Load values. */ 2137 R92C_RQPN_LD); 2138 2139 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, boundary); 2140 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, boundary); 2141 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, boundary); 2142 urtwn_write_1(sc, R92C_TRXFF_BNDY, boundary); 2143 urtwn_write_1(sc, R92C_TDECTRL + 1, boundary); 2144 2145 /* Set queue to USB pipe mapping. */ 2146 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2147 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2148 if (haslq) 2149 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2150 else if (hashq) { 2151 if (!hasnq) 2152 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2153 else 2154 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2155 } 2156 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2157 2158 /* Set Tx/Rx transfer page boundary. */ 2159 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, dmasize - 1); 2160 2161 if (!(sc->sc_sc.chip & RTWN_CHIP_92E)) { 2162 /* Set Tx/Rx transfer page size. */ 2163 urtwn_write_1(sc, R92C_PBP, 2164 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2165 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2166 } 2167 return (error); 2168 } 2169 2170 void 2171 urtwn_aggr_init(void *cookie) 2172 { 2173 struct urtwn_softc *sc = cookie; 2174 uint32_t reg = 0; 2175 int dmasize, dmatiming, ndesc; 2176 2177 /* Set burst packet length. */ 2178 if (sc->sc_sc.chip & RTWN_CHIP_92E) 2179 urtwn_burstlen_init(sc); 2180 2181 if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2182 dmasize = 6; 2183 dmatiming = 32; 2184 ndesc = 3; 2185 } else { 2186 dmasize = 48; 2187 dmatiming = 4; 2188 ndesc = (sc->sc_sc.chip & RTWN_CHIP_88E) ? 1 : 6; 2189 } 2190 2191 /* Tx aggregation setting. */ 2192 if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2193 urtwn_write_1(sc, R92E_DWBCN1_CTRL, ndesc << 1); 2194 } else { 2195 reg = urtwn_read_4(sc, R92C_TDECTRL); 2196 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, ndesc); 2197 urtwn_write_4(sc, R92C_TDECTRL, reg); 2198 } 2199 2200 /* Rx aggregation setting. */ 2201 if (!(sc->sc_sc.chip & RTWN_CHIP_92E)) { 2202 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 2203 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 2204 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 2205 } 2206 2207 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, dmasize); 2208 if (sc->sc_sc.chip & (RTWN_CHIP_92C | RTWN_CHIP_88C)) 2209 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, dmatiming); 2210 else 2211 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, dmatiming); 2212 2213 /* Drop incorrect bulk out. */ 2214 urtwn_write_4(sc, R92C_TXDMA_OFFSET_CHK, 2215 urtwn_read_4(sc, R92C_TXDMA_OFFSET_CHK) | 2216 R92C_TXDMA_OFFSET_CHK_DROP_DATA_EN); 2217 } 2218 2219 void 2220 urtwn_mac_init(void *cookie) 2221 { 2222 struct urtwn_softc *sc = cookie; 2223 int i; 2224 2225 /* Write MAC initialization values. */ 2226 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2227 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2228 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2229 rtl8188eu_mac[i].val); 2230 } 2231 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2232 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2233 for (i = 0; i < nitems(rtl8192eu_mac); i++) { 2234 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 2235 rtl8192eu_mac[i].val); 2236 } 2237 } else { 2238 for (i = 0; i < nitems(rtl8192cu_mac); i++) 2239 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2240 rtl8192cu_mac[i].val); 2241 } 2242 } 2243 2244 void 2245 urtwn_bb_init(void *cookie) 2246 { 2247 struct urtwn_softc *sc = cookie; 2248 const struct r92c_bb_prog *prog; 2249 uint32_t reg; 2250 uint8_t xtal; 2251 int i; 2252 2253 /* Enable BB and RF. */ 2254 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2255 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2256 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2257 R92C_SYS_FUNC_EN_DIO_RF); 2258 2259 if (!(sc->sc_sc.chip & (RTWN_CHIP_88E | RTWN_CHIP_92E))) 2260 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2261 2262 urtwn_write_1(sc, R92C_RF_CTRL, 2263 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2264 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2265 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2266 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2267 2268 if (!(sc->sc_sc.chip & (RTWN_CHIP_88E | RTWN_CHIP_92E))) { 2269 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2270 urtwn_write_1(sc, 0x15, 0xe9); 2271 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2272 } 2273 2274 /* Select BB programming based on board type. */ 2275 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2276 prog = &rtl8188eu_bb_prog; 2277 else if (sc->sc_sc.chip & RTWN_CHIP_92E) 2278 prog = &rtl8192eu_bb_prog; 2279 else if (!(sc->sc_sc.chip & RTWN_CHIP_92C)) { 2280 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD) 2281 prog = &rtl8188ce_bb_prog; 2282 else if (sc->sc_sc.board_type == R92C_BOARD_TYPE_HIGHPA) 2283 prog = &rtl8188ru_bb_prog; 2284 else 2285 prog = &rtl8188cu_bb_prog; 2286 } else { 2287 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD) 2288 prog = &rtl8192ce_bb_prog; 2289 else 2290 prog = &rtl8192cu_bb_prog; 2291 } 2292 /* Write BB initialization values. */ 2293 for (i = 0; i < prog->count; i++) { 2294 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2295 DELAY(1); 2296 } 2297 2298 if (sc->sc_sc.chip & RTWN_CHIP_92C_1T2R) { 2299 /* 8192C 1T only configuration. */ 2300 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2301 reg = (reg & ~0x00000003) | 0x2; 2302 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2303 2304 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2305 reg = (reg & ~0x00300033) | 0x00200022; 2306 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2307 2308 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2309 reg = (reg & ~0xff000000) | 0x45 << 24; 2310 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2311 2312 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2313 reg = (reg & ~0x000000ff) | 0x23; 2314 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2315 2316 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2317 reg = (reg & ~0x00000030) | 1 << 4; 2318 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2319 2320 reg = urtwn_bb_read(sc, 0xe74); 2321 reg = (reg & ~0x0c000000) | 2 << 26; 2322 urtwn_bb_write(sc, 0xe74, reg); 2323 reg = urtwn_bb_read(sc, 0xe78); 2324 reg = (reg & ~0x0c000000) | 2 << 26; 2325 urtwn_bb_write(sc, 0xe78, reg); 2326 reg = urtwn_bb_read(sc, 0xe7c); 2327 reg = (reg & ~0x0c000000) | 2 << 26; 2328 urtwn_bb_write(sc, 0xe7c, reg); 2329 reg = urtwn_bb_read(sc, 0xe80); 2330 reg = (reg & ~0x0c000000) | 2 << 26; 2331 urtwn_bb_write(sc, 0xe80, reg); 2332 reg = urtwn_bb_read(sc, 0xe88); 2333 reg = (reg & ~0x0c000000) | 2 << 26; 2334 urtwn_bb_write(sc, 0xe88, reg); 2335 } 2336 2337 /* Write AGC values. */ 2338 for (i = 0; i < prog->agccount; i++) { 2339 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2340 prog->agcvals[i]); 2341 DELAY(1); 2342 } 2343 2344 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2345 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2346 DELAY(1); 2347 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2348 DELAY(1); 2349 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2350 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040022); 2351 DELAY(1); 2352 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040020); 2353 DELAY(1); 2354 } 2355 2356 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2357 xtal = sc->sc_sc.crystal_cap & 0x3f; 2358 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2359 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2360 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, xtal | xtal << 6)); 2361 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2362 xtal = sc->sc_sc.crystal_cap & 0x3f; 2363 reg = urtwn_read_4(sc, R92C_AFE_CTRL3); 2364 reg &= 0xff000fff; 2365 reg |= (xtal | (xtal << 6)) << 12; 2366 urtwn_write_4(sc, R92C_AFE_CTRL3, reg); 2367 2368 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0x000f81fb); 2369 } 2370 2371 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & R92C_HSSI_PARAM2_CCK_HIPWR) 2372 sc->sc_sc.sc_flags |= RTWN_FLAG_CCK_HIPWR; 2373 } 2374 2375 void 2376 urtwn_burstlen_init(struct urtwn_softc *sc) 2377 { 2378 uint8_t reg; 2379 2380 reg = urtwn_read_1(sc, R92E_RXDMA_PRO); 2381 reg &= ~0x30; 2382 switch (sc->sc_udev->speed) { 2383 case USB_SPEED_HIGH: 2384 urtwn_write_1(sc, R92E_RXDMA_PRO, reg | 0x1e); 2385 break; 2386 default: 2387 urtwn_write_1(sc, R92E_RXDMA_PRO, reg | 0x2e); 2388 break; 2389 } 2390 } 2391 2392 int 2393 urtwn_power_on(void *cookie) 2394 { 2395 struct urtwn_softc *sc = cookie; 2396 2397 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2398 return (urtwn_r88e_power_on(sc)); 2399 else if (sc->sc_sc.chip & RTWN_CHIP_92E) 2400 return (urtwn_r92e_power_on(sc)); 2401 2402 return (urtwn_r92c_power_on(sc)); 2403 } 2404 2405 int 2406 urtwn_alloc_buffers(void *cookie) 2407 { 2408 struct urtwn_softc *sc = cookie; 2409 int error; 2410 2411 /* Init host async commands ring. */ 2412 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 2413 2414 /* Allocate Tx/Rx buffers. */ 2415 error = urtwn_alloc_rx_list(sc); 2416 if (error != 0) { 2417 printf("%s: could not allocate Rx buffers\n", 2418 sc->sc_dev.dv_xname); 2419 return (error); 2420 } 2421 error = urtwn_alloc_tx_list(sc); 2422 if (error != 0) { 2423 printf("%s: could not allocate Tx buffers\n", 2424 sc->sc_dev.dv_xname); 2425 return (error); 2426 } 2427 2428 return (0); 2429 } 2430 2431 int 2432 urtwn_init(void *cookie) 2433 { 2434 struct urtwn_softc *sc = cookie; 2435 int i, error; 2436 2437 if (sc->sc_sc.chip & RTWN_CHIP_92E) 2438 urtwn_write_1(sc, R92C_ACLK_MON, 0); 2439 2440 /* Queue Rx xfers. */ 2441 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 2442 struct urtwn_rx_data *data = &sc->rx_data[i]; 2443 2444 usbd_setup_xfer(data->xfer, sc->rx_pipe, data, data->buf, 2445 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 2446 USBD_NO_TIMEOUT, urtwn_rxeof); 2447 error = usbd_transfer(data->xfer); 2448 if (error != 0 && error != USBD_IN_PROGRESS) 2449 return (error); 2450 } 2451 2452 ieee80211_amrr_node_init(&sc->amrr, &sc->amn); 2453 2454 /* 2455 * Enable TX reports for AMRR. 2456 * In order to get reports we need to explicitly reset the register. 2457 */ 2458 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2459 urtwn_write_1(sc, R88E_TX_RPT_CTRL, (urtwn_read_1(sc, 2460 R88E_TX_RPT_CTRL) & ~0) | R88E_TX_RPT_CTRL_EN); 2461 2462 return (0); 2463 } 2464 2465 void 2466 urtwn_stop(void *cookie) 2467 { 2468 struct urtwn_softc *sc = cookie; 2469 int i; 2470 2471 /* Abort Tx. */ 2472 for (i = 0; i < R92C_MAX_EPOUT; i++) { 2473 if (sc->tx_pipe[i] != NULL) 2474 usbd_abort_pipe(sc->tx_pipe[i]); 2475 } 2476 /* Stop Rx pipe. */ 2477 usbd_abort_pipe(sc->rx_pipe); 2478 /* Free Tx/Rx buffers. */ 2479 urtwn_free_tx_list(sc); 2480 urtwn_free_rx_list(sc); 2481 } 2482 2483 int 2484 urtwn_is_oactive(void *cookie) 2485 { 2486 struct urtwn_softc *sc = cookie; 2487 2488 return (TAILQ_EMPTY(&sc->tx_free_list)); 2489 } 2490