1 /* $OpenBSD: if_urtwn.c,v 1.93 2020/07/31 10:49:33 mglocker Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss@yahoo.com.au> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU/ 23 * RTL8192EU. 24 */ 25 26 #include "bpfilter.h" 27 28 #include <sys/param.h> 29 #include <sys/sockio.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/timeout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 #include <sys/endian.h> 38 39 #include <machine/bus.h> 40 #include <machine/intr.h> 41 42 #if NBPFILTER > 0 43 #include <net/bpf.h> 44 #endif 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 49 #include <netinet/in.h> 50 #include <netinet/if_ether.h> 51 52 #include <net80211/ieee80211_var.h> 53 #include <net80211/ieee80211_amrr.h> 54 #include <net80211/ieee80211_radiotap.h> 55 56 #include <dev/usb/usb.h> 57 #include <dev/usb/usbdi.h> 58 #include <dev/usb/usbdivar.h> 59 #include <dev/usb/usbdi_util.h> 60 #include <dev/usb/usbdevs.h> 61 62 #include <dev/ic/r92creg.h> 63 #include <dev/ic/rtwnvar.h> 64 65 /* Maximum number of output pipes is 3. */ 66 #define R92C_MAX_EPOUT 3 67 68 #define R92C_HQ_NPAGES 12 69 #define R92C_LQ_NPAGES 2 70 #define R92C_NQ_NPAGES 2 71 #define R92C_TXPKTBUF_COUNT 256 72 #define R92C_TX_PAGE_COUNT 248 73 #define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) 74 #define R92C_MAX_RX_DMA_SIZE 0x2800 75 76 #define R88E_HQ_NPAGES 0 77 #define R88E_LQ_NPAGES 9 78 #define R88E_NQ_NPAGES 0 79 #define R88E_TXPKTBUF_COUNT 177 80 #define R88E_TX_PAGE_COUNT 168 81 #define R88E_TX_PAGE_BOUNDARY (R88E_TX_PAGE_COUNT + 1) 82 #define R88E_MAX_RX_DMA_SIZE 0x2400 83 84 #define R92E_HQ_NPAGES 16 85 #define R92E_LQ_NPAGES 16 86 #define R92E_NQ_NPAGES 16 87 #define R92E_TX_PAGE_COUNT 248 88 #define R92E_TX_PAGE_BOUNDARY (R92E_TX_PAGE_COUNT + 1) 89 #define R92E_MAX_RX_DMA_SIZE 0x3fc0 90 91 #define R92C_TXDESC_SUMSIZE 32 92 #define R92C_TXDESC_SUMOFFSET 14 93 94 /* USB Requests. */ 95 #define R92C_REQ_REGS 0x05 96 97 /* 98 * Driver definitions. 99 */ 100 #define URTWN_RX_LIST_COUNT 1 101 #define URTWN_TX_LIST_COUNT 8 102 #define URTWN_HOST_CMD_RING_COUNT 32 103 104 #define URTWN_RXBUFSZ (16 * 1024) 105 #define URTWN_TXBUFSZ (sizeof(struct r92e_tx_desc_usb) + IEEE80211_MAX_LEN) 106 107 #define URTWN_RIDX_COUNT 28 108 109 #define URTWN_TX_TIMEOUT 5000 /* ms */ 110 111 #define URTWN_LED_LINK 0 112 #define URTWN_LED_DATA 1 113 114 struct urtwn_rx_radiotap_header { 115 struct ieee80211_radiotap_header wr_ihdr; 116 uint8_t wr_flags; 117 uint8_t wr_rate; 118 uint16_t wr_chan_freq; 119 uint16_t wr_chan_flags; 120 uint8_t wr_dbm_antsignal; 121 } __packed; 122 123 #define URTWN_RX_RADIOTAP_PRESENT \ 124 (1 << IEEE80211_RADIOTAP_FLAGS | \ 125 1 << IEEE80211_RADIOTAP_RATE | \ 126 1 << IEEE80211_RADIOTAP_CHANNEL | \ 127 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) 128 129 struct urtwn_tx_radiotap_header { 130 struct ieee80211_radiotap_header wt_ihdr; 131 uint8_t wt_flags; 132 uint16_t wt_chan_freq; 133 uint16_t wt_chan_flags; 134 } __packed; 135 136 #define URTWN_TX_RADIOTAP_PRESENT \ 137 (1 << IEEE80211_RADIOTAP_FLAGS | \ 138 1 << IEEE80211_RADIOTAP_CHANNEL) 139 140 struct urtwn_softc; 141 142 struct urtwn_rx_data { 143 struct urtwn_softc *sc; 144 struct usbd_xfer *xfer; 145 uint8_t *buf; 146 }; 147 148 struct urtwn_tx_data { 149 struct urtwn_softc *sc; 150 struct usbd_pipe *pipe; 151 struct usbd_xfer *xfer; 152 uint8_t *buf; 153 TAILQ_ENTRY(urtwn_tx_data) next; 154 }; 155 156 struct urtwn_host_cmd { 157 void (*cb)(struct urtwn_softc *, void *); 158 uint8_t data[256]; 159 }; 160 161 struct urtwn_cmd_newstate { 162 enum ieee80211_state state; 163 int arg; 164 }; 165 166 struct urtwn_cmd_key { 167 struct ieee80211_key key; 168 struct ieee80211_node *ni; 169 }; 170 171 struct urtwn_host_cmd_ring { 172 struct urtwn_host_cmd cmd[URTWN_HOST_CMD_RING_COUNT]; 173 int cur; 174 int next; 175 int queued; 176 }; 177 178 struct urtwn_softc { 179 struct device sc_dev; 180 struct rtwn_softc sc_sc; 181 182 struct usbd_device *sc_udev; 183 struct usbd_interface *sc_iface; 184 struct usb_task sc_task; 185 186 struct timeout scan_to; 187 struct timeout calib_to; 188 189 int ntx; 190 struct usbd_pipe *rx_pipe; 191 struct usbd_pipe *tx_pipe[R92C_MAX_EPOUT]; 192 int ac2idx[EDCA_NUM_AC]; 193 194 struct urtwn_host_cmd_ring cmdq; 195 struct urtwn_rx_data rx_data[URTWN_RX_LIST_COUNT]; 196 struct urtwn_tx_data tx_data[URTWN_TX_LIST_COUNT]; 197 TAILQ_HEAD(, urtwn_tx_data) tx_free_list; 198 199 struct ieee80211_amrr amrr; 200 struct ieee80211_amrr_node amn; 201 202 #if NBPFILTER > 0 203 caddr_t sc_drvbpf; 204 205 union { 206 struct urtwn_rx_radiotap_header th; 207 uint8_t pad[64]; 208 } sc_rxtapu; 209 #define sc_rxtap sc_rxtapu.th 210 int sc_rxtap_len; 211 212 union { 213 struct urtwn_tx_radiotap_header th; 214 uint8_t pad[64]; 215 } sc_txtapu; 216 #define sc_txtap sc_txtapu.th 217 int sc_txtap_len; 218 #endif 219 }; 220 221 #ifdef URTWN_DEBUG 222 #define DPRINTF(x) do { if (urtwn_debug) printf x; } while (0) 223 #define DPRINTFN(n, x) do { if (urtwn_debug >= (n)) printf x; } while (0) 224 int urtwn_debug = 4; 225 #else 226 #define DPRINTF(x) 227 #define DPRINTFN(n, x) 228 #endif 229 230 /* 231 * Various supported device vendors/products. 232 */ 233 #define URTWN_DEV(v, p, f) \ 234 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, (f) | RTWN_CHIP_USB } 235 #define URTWN_DEV_8192CU(v, p) URTWN_DEV(v, p, RTWN_CHIP_92C | RTWN_CHIP_88C) 236 #define URTWN_DEV_8188EU(v, p) URTWN_DEV(v, p, RTWN_CHIP_88E) 237 #define URTWN_DEV_8192EU(v, p) URTWN_DEV(v, p, RTWN_CHIP_92E) 238 static const struct urtwn_type { 239 struct usb_devno dev; 240 uint32_t chip; 241 } urtwn_devs[] = { 242 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_1), 243 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_1), 244 URTWN_DEV_8192CU(ABOCOM, RTL8188CU_2), 245 URTWN_DEV_8192CU(ABOCOM, RTL8192CU), 246 URTWN_DEV_8192CU(ASUS, RTL8192CU), 247 URTWN_DEV_8192CU(ASUS, RTL8192CU_2), 248 URTWN_DEV_8192CU(ASUS, RTL8192CU_3), 249 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CE_1), 250 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CE_2), 251 URTWN_DEV_8192CU(AZUREWAVE, RTL8188CU), 252 URTWN_DEV_8192CU(BELKIN, F7D2102), 253 URTWN_DEV_8192CU(BELKIN, F9L1004V1), 254 URTWN_DEV_8192CU(BELKIN, RTL8188CU), 255 URTWN_DEV_8192CU(BELKIN, RTL8188CUS), 256 URTWN_DEV_8192CU(BELKIN, RTL8192CU), 257 URTWN_DEV_8192CU(BELKIN, RTL8192CU_1), 258 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_1), 259 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_2), 260 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_3), 261 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_4), 262 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_5), 263 URTWN_DEV_8192CU(CHICONY, RTL8188CUS_6), 264 URTWN_DEV_8192CU(COMPARE, RTL8192CU), 265 URTWN_DEV_8192CU(COREGA, RTL8192CU), 266 URTWN_DEV_8192CU(DLINK, DWA131B), 267 URTWN_DEV_8192CU(DLINK, RTL8188CU), 268 URTWN_DEV_8192CU(DLINK, RTL8192CU_1), 269 URTWN_DEV_8192CU(DLINK, RTL8192CU_2), 270 URTWN_DEV_8192CU(DLINK, RTL8192CU_3), 271 URTWN_DEV_8192CU(DLINK, RTL8192CU_4), 272 URTWN_DEV_8192CU(EDIMAX, EW7811UN), 273 URTWN_DEV_8192CU(EDIMAX, RTL8192CU), 274 URTWN_DEV_8192CU(FEIXUN, RTL8188CU), 275 URTWN_DEV_8192CU(FEIXUN, RTL8192CU), 276 URTWN_DEV_8192CU(GUILLEMOT, HWNUP150), 277 URTWN_DEV_8192CU(GUILLEMOT, RTL8192CU), 278 URTWN_DEV_8192CU(HAWKING, RTL8192CU), 279 URTWN_DEV_8192CU(HAWKING, RTL8192CU_2), 280 URTWN_DEV_8192CU(HP3, RTL8188CU), 281 URTWN_DEV_8192CU(IODATA, WNG150UM), 282 URTWN_DEV_8192CU(IODATA, RTL8192CU), 283 URTWN_DEV_8192CU(NETGEAR, N300MA), 284 URTWN_DEV_8192CU(NETGEAR, WNA1000M), 285 URTWN_DEV_8192CU(NETGEAR, WNA1000MV2), 286 URTWN_DEV_8192CU(NETGEAR, RTL8192CU), 287 URTWN_DEV_8192CU(NETGEAR4, RTL8188CU), 288 URTWN_DEV_8192CU(NETWEEN, RTL8192CU), 289 URTWN_DEV_8192CU(NOVATECH, RTL8188CU), 290 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_1), 291 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_2), 292 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_3), 293 URTWN_DEV_8192CU(PLANEX2, RTL8188CU_4), 294 URTWN_DEV_8192CU(PLANEX2, RTL8188CUS), 295 URTWN_DEV_8192CU(PLANEX2, RTL8192CU), 296 URTWN_DEV_8192CU(REALTEK, RTL8188CE_0), 297 URTWN_DEV_8192CU(REALTEK, RTL8188CE_1), 298 URTWN_DEV_8192CU(REALTEK, RTL8188CTV), 299 URTWN_DEV_8192CU(REALTEK, RTL8188CU_0), 300 URTWN_DEV_8192CU(REALTEK, RTL8188CU_1), 301 URTWN_DEV_8192CU(REALTEK, RTL8188CU_2), 302 URTWN_DEV_8192CU(REALTEK, RTL8188CU_3), 303 URTWN_DEV_8192CU(REALTEK, RTL8188CU_4), 304 URTWN_DEV_8192CU(REALTEK, RTL8188CU_5), 305 URTWN_DEV_8192CU(REALTEK, RTL8188CU_COMBO), 306 URTWN_DEV_8192CU(REALTEK, RTL8188CUS), 307 URTWN_DEV_8192CU(REALTEK, RTL8188RU), 308 URTWN_DEV_8192CU(REALTEK, RTL8188RU_2), 309 URTWN_DEV_8192CU(REALTEK, RTL8188RU_3), 310 URTWN_DEV_8192CU(REALTEK, RTL8191CU), 311 URTWN_DEV_8192CU(REALTEK, RTL8192CE), 312 URTWN_DEV_8192CU(REALTEK, RTL8192CE_VAU), 313 URTWN_DEV_8192CU(REALTEK, RTL8192CU), 314 URTWN_DEV_8192CU(SITECOMEU, RTL8188CU), 315 URTWN_DEV_8192CU(SITECOMEU, RTL8188CU_2), 316 URTWN_DEV_8192CU(SITECOMEU, RTL8192CU), 317 URTWN_DEV_8192CU(SITECOMEU, RTL8192CU_2), 318 URTWN_DEV_8192CU(SITECOMEU, WLA2100V2), 319 URTWN_DEV_8192CU(TPLINK, RTL8192CU), 320 URTWN_DEV_8192CU(TRENDNET, RTL8188CU), 321 URTWN_DEV_8192CU(TRENDNET, RTL8192CU), 322 URTWN_DEV_8192CU(ZYXEL, RTL8192CU), 323 /* URTWN_RTL8188E */ 324 URTWN_DEV_8188EU(ABOCOM, RTL8188EU), 325 URTWN_DEV_8188EU(DLINK, DWA121B1), 326 URTWN_DEV_8188EU(DLINK, DWA123D1), 327 URTWN_DEV_8188EU(DLINK, DWA125D1), 328 URTWN_DEV_8188EU(ELECOM, WDC150SU2M), 329 URTWN_DEV_8188EU(REALTEK, RTL8188ETV), 330 URTWN_DEV_8188EU(REALTEK, RTL8188EU), 331 URTWN_DEV_8188EU(TPLINK, RTL8188EUS), 332 /* URTWN_RTL8192EU */ 333 URTWN_DEV_8192EU(DLINK, DWA131E1), 334 URTWN_DEV_8192EU(REALTEK, RTL8192EU), 335 URTWN_DEV_8192EU(TPLINK, RTL8192EU), 336 URTWN_DEV_8192EU(TPLINK, RTL8192EU_2), 337 URTWN_DEV_8192EU(TPLINK, RTL8192EU_3) 338 }; 339 340 #define urtwn_lookup(v, p) \ 341 ((const struct urtwn_type *)usb_lookup(urtwn_devs, v, p)) 342 343 int urtwn_match(struct device *, void *, void *); 344 void urtwn_attach(struct device *, struct device *, void *); 345 int urtwn_detach(struct device *, int); 346 int urtwn_open_pipes(struct urtwn_softc *); 347 void urtwn_close_pipes(struct urtwn_softc *); 348 int urtwn_alloc_rx_list(struct urtwn_softc *); 349 void urtwn_free_rx_list(struct urtwn_softc *); 350 int urtwn_alloc_tx_list(struct urtwn_softc *); 351 void urtwn_free_tx_list(struct urtwn_softc *); 352 void urtwn_task(void *); 353 void urtwn_do_async(struct urtwn_softc *, 354 void (*)(struct urtwn_softc *, void *), void *, int); 355 void urtwn_wait_async(void *); 356 int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 357 int); 358 void urtwn_write_1(void *, uint16_t, uint8_t); 359 void urtwn_write_2(void *, uint16_t, uint16_t); 360 void urtwn_write_4(void *, uint16_t, uint32_t); 361 int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 362 int); 363 uint8_t urtwn_read_1(void *, uint16_t); 364 uint16_t urtwn_read_2(void *, uint16_t); 365 uint32_t urtwn_read_4(void *, uint16_t); 366 int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 367 void urtwn_calib_to(void *); 368 void urtwn_calib_cb(struct urtwn_softc *, void *); 369 void urtwn_scan_to(void *); 370 void urtwn_next_scan(void *); 371 void urtwn_cancel_scan(void *); 372 int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 373 int); 374 void urtwn_newstate_cb(struct urtwn_softc *, void *); 375 void urtwn_updateslot(struct ieee80211com *); 376 void urtwn_updateslot_cb(struct urtwn_softc *, void *); 377 void urtwn_updateedca(struct ieee80211com *); 378 void urtwn_updateedca_cb(struct urtwn_softc *, void *); 379 int urtwn_set_key(struct ieee80211com *, struct ieee80211_node *, 380 struct ieee80211_key *); 381 void urtwn_set_key_cb(struct urtwn_softc *, void *); 382 void urtwn_delete_key(struct ieee80211com *, 383 struct ieee80211_node *, struct ieee80211_key *); 384 void urtwn_delete_key_cb(struct urtwn_softc *, void *); 385 void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 386 struct mbuf_list *); 387 void urtwn_rxeof(struct usbd_xfer *, void *, 388 usbd_status); 389 void urtwn_txeof(struct usbd_xfer *, void *, 390 usbd_status); 391 int urtwn_tx(void *, struct mbuf *, struct ieee80211_node *); 392 int urtwn_ioctl(struct ifnet *, u_long, caddr_t); 393 int urtwn_power_on(void *); 394 int urtwn_alloc_buffers(void *); 395 int urtwn_r92c_power_on(struct urtwn_softc *); 396 int urtwn_r92e_power_on(struct urtwn_softc *); 397 int urtwn_r88e_power_on(struct urtwn_softc *); 398 int urtwn_llt_init(struct urtwn_softc *, int); 399 int urtwn_fw_loadpage(void *, int, uint8_t *, int); 400 int urtwn_load_firmware(void *, u_char **, size_t *); 401 int urtwn_dma_init(void *); 402 void urtwn_aggr_init(void *); 403 void urtwn_mac_init(void *); 404 void urtwn_bb_init(void *); 405 void urtwn_burstlen_init(struct urtwn_softc *); 406 int urtwn_init(void *); 407 void urtwn_stop(void *); 408 int urtwn_is_oactive(void *); 409 void urtwn_next_calib(void *); 410 void urtwn_cancel_calib(void *); 411 412 /* Aliases. */ 413 #define urtwn_bb_write urtwn_write_4 414 #define urtwn_bb_read urtwn_read_4 415 416 struct cfdriver urtwn_cd = { 417 NULL, "urtwn", DV_IFNET 418 }; 419 420 const struct cfattach urtwn_ca = { 421 sizeof(struct urtwn_softc), urtwn_match, urtwn_attach, urtwn_detach 422 }; 423 424 int 425 urtwn_match(struct device *parent, void *match, void *aux) 426 { 427 struct usb_attach_arg *uaa = aux; 428 429 if (uaa->iface == NULL || uaa->configno != 1) 430 return (UMATCH_NONE); 431 432 return ((urtwn_lookup(uaa->vendor, uaa->product) != NULL) ? 433 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 434 } 435 436 void 437 urtwn_attach(struct device *parent, struct device *self, void *aux) 438 { 439 struct urtwn_softc *sc = (struct urtwn_softc *)self; 440 struct usb_attach_arg *uaa = aux; 441 struct ifnet *ifp; 442 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 443 444 sc->sc_udev = uaa->device; 445 sc->sc_iface = uaa->iface; 446 447 sc->sc_sc.chip = urtwn_lookup(uaa->vendor, uaa->product)->chip; 448 449 usb_init_task(&sc->sc_task, urtwn_task, sc, USB_TASK_TYPE_GENERIC); 450 timeout_set(&sc->scan_to, urtwn_scan_to, sc); 451 timeout_set(&sc->calib_to, urtwn_calib_to, sc); 452 if (urtwn_open_pipes(sc) != 0) 453 return; 454 455 sc->amrr.amrr_min_success_threshold = 1; 456 sc->amrr.amrr_max_success_threshold = 10; 457 458 /* Attach the bus-agnostic driver. */ 459 sc->sc_sc.sc_ops.cookie = sc; 460 sc->sc_sc.sc_ops.write_1 = urtwn_write_1; 461 sc->sc_sc.sc_ops.write_2 = urtwn_write_2; 462 sc->sc_sc.sc_ops.write_4 = urtwn_write_4; 463 sc->sc_sc.sc_ops.read_1 = urtwn_read_1; 464 sc->sc_sc.sc_ops.read_2 = urtwn_read_2; 465 sc->sc_sc.sc_ops.read_4 = urtwn_read_4; 466 sc->sc_sc.sc_ops.tx = urtwn_tx; 467 sc->sc_sc.sc_ops.power_on = urtwn_power_on; 468 sc->sc_sc.sc_ops.dma_init = urtwn_dma_init; 469 sc->sc_sc.sc_ops.fw_loadpage = urtwn_fw_loadpage; 470 sc->sc_sc.sc_ops.load_firmware = urtwn_load_firmware; 471 sc->sc_sc.sc_ops.aggr_init = urtwn_aggr_init; 472 sc->sc_sc.sc_ops.mac_init = urtwn_mac_init; 473 sc->sc_sc.sc_ops.bb_init = urtwn_bb_init; 474 sc->sc_sc.sc_ops.alloc_buffers = urtwn_alloc_buffers; 475 sc->sc_sc.sc_ops.init = urtwn_init; 476 sc->sc_sc.sc_ops.stop = urtwn_stop; 477 sc->sc_sc.sc_ops.is_oactive = urtwn_is_oactive; 478 sc->sc_sc.sc_ops.next_calib = urtwn_next_calib; 479 sc->sc_sc.sc_ops.cancel_calib = urtwn_cancel_calib; 480 sc->sc_sc.sc_ops.next_scan = urtwn_next_scan; 481 sc->sc_sc.sc_ops.cancel_scan = urtwn_cancel_scan; 482 sc->sc_sc.sc_ops.wait_async = urtwn_wait_async; 483 if (rtwn_attach(&sc->sc_dev, &sc->sc_sc) != 0) { 484 urtwn_close_pipes(sc); 485 return; 486 } 487 488 /* ifp is now valid */ 489 ifp = &sc->sc_sc.sc_ic.ic_if; 490 ifp->if_ioctl = urtwn_ioctl; 491 492 ic->ic_updateslot = urtwn_updateslot; 493 ic->ic_updateedca = urtwn_updateedca; 494 ic->ic_set_key = urtwn_set_key; 495 ic->ic_delete_key = urtwn_delete_key; 496 /* Override state transition machine. */ 497 ic->ic_newstate = urtwn_newstate; 498 499 #if NBPFILTER > 0 500 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 501 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 502 503 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 504 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 505 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 506 507 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 508 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 509 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 510 #endif 511 } 512 513 int 514 urtwn_detach(struct device *self, int flags) 515 { 516 struct urtwn_softc *sc = (struct urtwn_softc *)self; 517 int s; 518 519 s = splusb(); 520 521 if (timeout_initialized(&sc->scan_to)) 522 timeout_del(&sc->scan_to); 523 if (timeout_initialized(&sc->calib_to)) 524 timeout_del(&sc->calib_to); 525 526 /* Wait for all async commands to complete. */ 527 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 528 529 usbd_ref_wait(sc->sc_udev); 530 531 rtwn_detach(&sc->sc_sc, flags); 532 533 /* Abort and close Tx/Rx pipes. */ 534 urtwn_close_pipes(sc); 535 536 /* Free Tx/Rx buffers. */ 537 urtwn_free_tx_list(sc); 538 urtwn_free_rx_list(sc); 539 splx(s); 540 541 return (0); 542 } 543 544 int 545 urtwn_open_pipes(struct urtwn_softc *sc) 546 { 547 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 548 uint8_t epaddr[R92C_MAX_EPOUT] = { 0, 0, 0 }; 549 uint8_t rx_no; 550 usb_interface_descriptor_t *id; 551 usb_endpoint_descriptor_t *ed; 552 int i, error, nrx = 0; 553 554 /* Find all bulk endpoints. */ 555 id = usbd_get_interface_descriptor(sc->sc_iface); 556 for (i = 0; i < id->bNumEndpoints; i++) { 557 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 558 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) 559 continue; 560 561 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 562 rx_no = ed->bEndpointAddress; 563 nrx++; 564 } else { 565 if (sc->ntx < R92C_MAX_EPOUT) 566 epaddr[sc->ntx] = ed->bEndpointAddress; 567 sc->ntx++; 568 } 569 } 570 if (nrx == 0) { 571 printf("%s: %d: invalid number of Rx bulk pipes\n", 572 sc->sc_dev.dv_xname, nrx); 573 return (EIO); 574 } 575 DPRINTF(("found %d bulk-out pipes\n", sc->ntx)); 576 if (sc->ntx == 0 || sc->ntx > R92C_MAX_EPOUT) { 577 printf("%s: %d: invalid number of Tx bulk pipes\n", 578 sc->sc_dev.dv_xname, sc->ntx); 579 return (EIO); 580 } 581 582 /* Open bulk-in pipe. */ 583 error = usbd_open_pipe(sc->sc_iface, rx_no, 0, &sc->rx_pipe); 584 if (error != 0) { 585 printf("%s: could not open Rx bulk pipe\n", 586 sc->sc_dev.dv_xname); 587 goto fail; 588 } 589 590 /* Open bulk-out pipes (up to 3). */ 591 for (i = 0; i < sc->ntx; i++) { 592 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 0, 593 &sc->tx_pipe[i]); 594 if (error != 0) { 595 printf("%s: could not open Tx bulk pipe 0x%02x\n", 596 sc->sc_dev.dv_xname, epaddr[i]); 597 goto fail; 598 } 599 } 600 601 /* Map 802.11 access categories to USB pipes. */ 602 sc->ac2idx[EDCA_AC_BK] = 603 sc->ac2idx[EDCA_AC_BE] = (sc->ntx == 3) ? 2 : ((sc->ntx == 2) ? 1 : 0); 604 sc->ac2idx[EDCA_AC_VI] = (sc->ntx == 3) ? 1 : 0; 605 sc->ac2idx[EDCA_AC_VO] = 0; /* Always use highest prio. */ 606 607 if (error != 0) 608 fail: urtwn_close_pipes(sc); 609 return (error); 610 } 611 612 void 613 urtwn_close_pipes(struct urtwn_softc *sc) 614 { 615 int i; 616 617 /* Close Rx pipe. */ 618 if (sc->rx_pipe != NULL) 619 usbd_close_pipe(sc->rx_pipe); 620 /* Close Tx pipes. */ 621 for (i = 0; i < R92C_MAX_EPOUT; i++) { 622 if (sc->tx_pipe[i] == NULL) 623 continue; 624 usbd_close_pipe(sc->tx_pipe[i]); 625 } 626 } 627 628 int 629 urtwn_alloc_rx_list(struct urtwn_softc *sc) 630 { 631 struct urtwn_rx_data *data; 632 int i, error = 0; 633 634 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 635 data = &sc->rx_data[i]; 636 637 data->sc = sc; /* Backpointer for callbacks. */ 638 639 data->xfer = usbd_alloc_xfer(sc->sc_udev); 640 if (data->xfer == NULL) { 641 printf("%s: could not allocate xfer\n", 642 sc->sc_dev.dv_xname); 643 error = ENOMEM; 644 break; 645 } 646 data->buf = usbd_alloc_buffer(data->xfer, URTWN_RXBUFSZ); 647 if (data->buf == NULL) { 648 printf("%s: could not allocate xfer buffer\n", 649 sc->sc_dev.dv_xname); 650 error = ENOMEM; 651 break; 652 } 653 } 654 if (error != 0) 655 urtwn_free_rx_list(sc); 656 return (error); 657 } 658 659 void 660 urtwn_free_rx_list(struct urtwn_softc *sc) 661 { 662 int i; 663 664 /* NB: Caller must abort pipe first. */ 665 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 666 if (sc->rx_data[i].xfer != NULL) 667 usbd_free_xfer(sc->rx_data[i].xfer); 668 sc->rx_data[i].xfer = NULL; 669 } 670 } 671 672 int 673 urtwn_alloc_tx_list(struct urtwn_softc *sc) 674 { 675 struct urtwn_tx_data *data; 676 int i, error = 0; 677 678 TAILQ_INIT(&sc->tx_free_list); 679 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 680 data = &sc->tx_data[i]; 681 682 data->sc = sc; /* Backpointer for callbacks. */ 683 684 data->xfer = usbd_alloc_xfer(sc->sc_udev); 685 if (data->xfer == NULL) { 686 printf("%s: could not allocate xfer\n", 687 sc->sc_dev.dv_xname); 688 error = ENOMEM; 689 break; 690 } 691 data->buf = usbd_alloc_buffer(data->xfer, URTWN_TXBUFSZ); 692 if (data->buf == NULL) { 693 printf("%s: could not allocate xfer buffer\n", 694 sc->sc_dev.dv_xname); 695 error = ENOMEM; 696 break; 697 } 698 /* Append this Tx buffer to our free list. */ 699 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 700 } 701 if (error != 0) 702 urtwn_free_tx_list(sc); 703 return (error); 704 } 705 706 void 707 urtwn_free_tx_list(struct urtwn_softc *sc) 708 { 709 int i; 710 711 /* NB: Caller must abort pipe first. */ 712 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 713 if (sc->tx_data[i].xfer != NULL) 714 usbd_free_xfer(sc->tx_data[i].xfer); 715 sc->tx_data[i].xfer = NULL; 716 } 717 } 718 719 void 720 urtwn_task(void *arg) 721 { 722 struct urtwn_softc *sc = arg; 723 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 724 struct urtwn_host_cmd *cmd; 725 int s; 726 727 /* Process host commands. */ 728 s = splusb(); 729 while (ring->next != ring->cur) { 730 cmd = &ring->cmd[ring->next]; 731 splx(s); 732 /* Invoke callback. */ 733 cmd->cb(sc, cmd->data); 734 s = splusb(); 735 ring->queued--; 736 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 737 } 738 splx(s); 739 } 740 741 void 742 urtwn_do_async(struct urtwn_softc *sc, 743 void (*cb)(struct urtwn_softc *, void *), void *arg, int len) 744 { 745 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 746 struct urtwn_host_cmd *cmd; 747 int s; 748 749 s = splusb(); 750 cmd = &ring->cmd[ring->cur]; 751 cmd->cb = cb; 752 KASSERT(len <= sizeof(cmd->data)); 753 memcpy(cmd->data, arg, len); 754 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 755 756 /* If there is no pending command already, schedule a task. */ 757 if (++ring->queued == 1) 758 usb_add_task(sc->sc_udev, &sc->sc_task); 759 splx(s); 760 } 761 762 void 763 urtwn_wait_async(void *cookie) 764 { 765 struct urtwn_softc *sc = cookie; 766 int s; 767 768 s = splusb(); 769 /* Wait for all queued asynchronous commands to complete. */ 770 usb_wait_task(sc->sc_udev, &sc->sc_task); 771 splx(s); 772 } 773 774 int 775 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 776 int len) 777 { 778 usb_device_request_t req; 779 780 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 781 req.bRequest = R92C_REQ_REGS; 782 USETW(req.wValue, addr); 783 USETW(req.wIndex, 0); 784 USETW(req.wLength, len); 785 return (usbd_do_request(sc->sc_udev, &req, buf)); 786 } 787 788 void 789 urtwn_write_1(void *cookie, uint16_t addr, uint8_t val) 790 { 791 struct urtwn_softc *sc = cookie; 792 793 urtwn_write_region_1(sc, addr, &val, 1); 794 } 795 796 void 797 urtwn_write_2(void *cookie, uint16_t addr, uint16_t val) 798 { 799 struct urtwn_softc *sc = cookie; 800 801 val = htole16(val); 802 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 803 } 804 805 void 806 urtwn_write_4(void *cookie, uint16_t addr, uint32_t val) 807 { 808 struct urtwn_softc *sc = cookie; 809 810 val = htole32(val); 811 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 812 } 813 814 int 815 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 816 int len) 817 { 818 usb_device_request_t req; 819 820 req.bmRequestType = UT_READ_VENDOR_DEVICE; 821 req.bRequest = R92C_REQ_REGS; 822 USETW(req.wValue, addr); 823 USETW(req.wIndex, 0); 824 USETW(req.wLength, len); 825 return (usbd_do_request(sc->sc_udev, &req, buf)); 826 } 827 828 uint8_t 829 urtwn_read_1(void *cookie, uint16_t addr) 830 { 831 struct urtwn_softc *sc = cookie; 832 uint8_t val; 833 834 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 835 return (0xff); 836 return (val); 837 } 838 839 uint16_t 840 urtwn_read_2(void *cookie, uint16_t addr) 841 { 842 struct urtwn_softc *sc = cookie; 843 uint16_t val; 844 845 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 846 return (0xffff); 847 return (letoh16(val)); 848 } 849 850 uint32_t 851 urtwn_read_4(void *cookie, uint16_t addr) 852 { 853 struct urtwn_softc *sc = cookie; 854 uint32_t val; 855 856 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 857 return (0xffffffff); 858 return (letoh32(val)); 859 } 860 861 int 862 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 863 { 864 int ntries; 865 866 urtwn_write_4(sc, R92C_LLT_INIT, 867 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 868 SM(R92C_LLT_INIT_ADDR, addr) | 869 SM(R92C_LLT_INIT_DATA, data)); 870 /* Wait for write operation to complete. */ 871 for (ntries = 0; ntries < 20; ntries++) { 872 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 873 R92C_LLT_INIT_OP_NO_ACTIVE) 874 return (0); 875 DELAY(5); 876 } 877 return (ETIMEDOUT); 878 } 879 880 void 881 urtwn_calib_to(void *arg) 882 { 883 struct urtwn_softc *sc = arg; 884 885 if (usbd_is_dying(sc->sc_udev)) 886 return; 887 888 usbd_ref_incr(sc->sc_udev); 889 890 /* Do it in a process context. */ 891 urtwn_do_async(sc, urtwn_calib_cb, NULL, 0); 892 893 usbd_ref_decr(sc->sc_udev); 894 } 895 896 /* ARGSUSED */ 897 void 898 urtwn_calib_cb(struct urtwn_softc *sc, void *arg) 899 { 900 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 901 int s; 902 903 s = splnet(); 904 if (ic->ic_opmode == IEEE80211_M_STA) { 905 ieee80211_amrr_choose(&sc->amrr, ic->ic_bss, &sc->amn); 906 } 907 splx(s); 908 909 rtwn_calib(&sc->sc_sc); 910 } 911 912 void 913 urtwn_next_calib(void *cookie) 914 { 915 struct urtwn_softc *sc = cookie; 916 917 if (!usbd_is_dying(sc->sc_udev)) 918 timeout_add_sec(&sc->calib_to, 2); 919 } 920 921 void 922 urtwn_cancel_calib(void *cookie) 923 { 924 struct urtwn_softc *sc = cookie; 925 926 if (timeout_initialized(&sc->calib_to)) 927 timeout_del(&sc->calib_to); 928 } 929 930 void 931 urtwn_scan_to(void *arg) 932 { 933 struct urtwn_softc *sc = arg; 934 935 if (usbd_is_dying(sc->sc_udev)) 936 return; 937 938 usbd_ref_incr(sc->sc_udev); 939 rtwn_next_scan(&sc->sc_sc); 940 usbd_ref_decr(sc->sc_udev); 941 } 942 943 void 944 urtwn_next_scan(void *arg) 945 { 946 struct urtwn_softc *sc = arg; 947 948 if (!usbd_is_dying(sc->sc_udev)) 949 timeout_add_msec(&sc->scan_to, 200); 950 } 951 952 void 953 urtwn_cancel_scan(void *cookie) 954 { 955 struct urtwn_softc *sc = cookie; 956 957 if (timeout_initialized(&sc->scan_to)) 958 timeout_del(&sc->scan_to); 959 } 960 961 int 962 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 963 { 964 struct rtwn_softc *sc_sc = ic->ic_softc; 965 struct device *self = sc_sc->sc_pdev; 966 struct urtwn_softc *sc = (struct urtwn_softc *)self; 967 struct urtwn_cmd_newstate cmd; 968 969 /* Do it in a process context. */ 970 cmd.state = nstate; 971 cmd.arg = arg; 972 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 973 return (0); 974 } 975 976 void 977 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 978 { 979 struct urtwn_cmd_newstate *cmd = arg; 980 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 981 982 rtwn_newstate(ic, cmd->state, cmd->arg); 983 } 984 985 void 986 urtwn_updateslot(struct ieee80211com *ic) 987 { 988 struct rtwn_softc *sc_sc = ic->ic_softc; 989 struct device *self = sc_sc->sc_pdev; 990 struct urtwn_softc *sc = (struct urtwn_softc *)self; 991 992 /* Do it in a process context. */ 993 urtwn_do_async(sc, urtwn_updateslot_cb, NULL, 0); 994 } 995 996 /* ARGSUSED */ 997 void 998 urtwn_updateslot_cb(struct urtwn_softc *sc, void *arg) 999 { 1000 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1001 1002 rtwn_updateslot(ic); 1003 } 1004 1005 void 1006 urtwn_updateedca(struct ieee80211com *ic) 1007 { 1008 struct rtwn_softc *sc_sc = ic->ic_softc; 1009 struct device *self = sc_sc->sc_pdev; 1010 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1011 1012 /* Do it in a process context. */ 1013 urtwn_do_async(sc, urtwn_updateedca_cb, NULL, 0); 1014 } 1015 1016 /* ARGSUSED */ 1017 void 1018 urtwn_updateedca_cb(struct urtwn_softc *sc, void *arg) 1019 { 1020 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1021 1022 rtwn_updateedca(ic); 1023 } 1024 1025 int 1026 urtwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1027 struct ieee80211_key *k) 1028 { 1029 struct rtwn_softc *sc_sc = ic->ic_softc; 1030 struct device *self = sc_sc->sc_pdev; 1031 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1032 struct urtwn_cmd_key cmd; 1033 1034 /* Only handle keys for CCMP */ 1035 if (k->k_cipher != IEEE80211_CIPHER_CCMP) 1036 return ieee80211_set_key(ic, ni, k); 1037 1038 /* Defer setting of WEP keys until interface is brought up. */ 1039 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 1040 (IFF_UP | IFF_RUNNING)) 1041 return (0); 1042 1043 /* Do it in a process context. */ 1044 cmd.key = *k; 1045 cmd.ni = ni; 1046 urtwn_do_async(sc, urtwn_set_key_cb, &cmd, sizeof(cmd)); 1047 return (0); 1048 } 1049 1050 void 1051 urtwn_set_key_cb(struct urtwn_softc *sc, void *arg) 1052 { 1053 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1054 struct urtwn_cmd_key *cmd = arg; 1055 1056 rtwn_set_key(ic, cmd->ni, &cmd->key); 1057 } 1058 1059 void 1060 urtwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1061 struct ieee80211_key *k) 1062 { 1063 struct rtwn_softc *sc_sc = ic->ic_softc; 1064 struct device *self = sc_sc->sc_pdev; 1065 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1066 struct urtwn_cmd_key cmd; 1067 1068 /* Only handle keys for CCMP */ 1069 if (k->k_cipher != IEEE80211_CIPHER_CCMP) { 1070 ieee80211_delete_key(ic, ni, k); 1071 return; 1072 } 1073 1074 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 1075 ic->ic_state != IEEE80211_S_RUN) 1076 return; /* Nothing to do. */ 1077 1078 /* Do it in a process context. */ 1079 cmd.key = *k; 1080 cmd.ni = ni; 1081 urtwn_do_async(sc, urtwn_delete_key_cb, &cmd, sizeof(cmd)); 1082 } 1083 1084 void 1085 urtwn_delete_key_cb(struct urtwn_softc *sc, void *arg) 1086 { 1087 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1088 struct urtwn_cmd_key *cmd = arg; 1089 1090 rtwn_delete_key(ic, cmd->ni, &cmd->key); 1091 } 1092 1093 int 1094 urtwn_ccmp_decap(struct urtwn_softc *sc, struct mbuf *m, 1095 struct ieee80211_node *ni) 1096 { 1097 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1098 struct ieee80211_key *k; 1099 struct ieee80211_frame *wh; 1100 uint64_t pn, *prsc; 1101 uint8_t *ivp; 1102 uint8_t tid; 1103 int hdrlen, hasqos; 1104 1105 k = ieee80211_get_rxkey(ic, m, ni); 1106 if (k == NULL) 1107 return 1; 1108 1109 wh = mtod(m, struct ieee80211_frame *); 1110 hdrlen = ieee80211_get_hdrlen(wh); 1111 ivp = (uint8_t *)wh + hdrlen; 1112 1113 /* Check that ExtIV bit is set. */ 1114 if (!(ivp[3] & IEEE80211_WEP_EXTIV)) 1115 return 1; 1116 1117 hasqos = ieee80211_has_qos(wh); 1118 tid = hasqos ? ieee80211_get_qos(wh) & IEEE80211_QOS_TID : 0; 1119 prsc = &k->k_rsc[tid]; 1120 1121 /* Extract the 48-bit PN from the CCMP header. */ 1122 pn = (uint64_t)ivp[0] | 1123 (uint64_t)ivp[1] << 8 | 1124 (uint64_t)ivp[4] << 16 | 1125 (uint64_t)ivp[5] << 24 | 1126 (uint64_t)ivp[6] << 32 | 1127 (uint64_t)ivp[7] << 40; 1128 if (pn <= *prsc) { 1129 ic->ic_stats.is_ccmp_replays++; 1130 return 1; 1131 } 1132 /* Last seen packet number is updated in ieee80211_inputm(). */ 1133 1134 /* Strip MIC. IV will be stripped by ieee80211_inputm(). */ 1135 m_adj(m, -IEEE80211_CCMP_MICLEN); 1136 return 0; 1137 } 1138 1139 void 1140 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, 1141 struct mbuf_list *ml) 1142 { 1143 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1144 struct ifnet *ifp = &ic->ic_if; 1145 struct ieee80211_rxinfo rxi; 1146 struct ieee80211_frame *wh; 1147 struct ieee80211_node *ni; 1148 struct r92c_rx_desc_usb *rxd; 1149 uint32_t rxdw0, rxdw3; 1150 struct mbuf *m; 1151 uint8_t rate; 1152 int8_t rssi = 0; 1153 int s, infosz; 1154 1155 rxd = (struct r92c_rx_desc_usb *)buf; 1156 rxdw0 = letoh32(rxd->rxdw0); 1157 rxdw3 = letoh32(rxd->rxdw3); 1158 1159 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1160 /* 1161 * This should not happen since we setup our Rx filter 1162 * to not receive these frames. 1163 */ 1164 ifp->if_ierrors++; 1165 return; 1166 } 1167 if (__predict_false(pktlen < sizeof(*wh) || pktlen > MCLBYTES)) { 1168 ifp->if_ierrors++; 1169 return; 1170 } 1171 1172 rate = MS(rxdw3, R92C_RXDW3_RATE); 1173 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1174 1175 /* Get RSSI from PHY status descriptor if present. */ 1176 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1177 rssi = rtwn_get_rssi(&sc->sc_sc, rate, &rxd[1]); 1178 /* Update our average RSSI. */ 1179 rtwn_update_avgrssi(&sc->sc_sc, rate, rssi); 1180 } 1181 1182 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 1183 pktlen, rate, infosz, rssi)); 1184 1185 MGETHDR(m, M_DONTWAIT, MT_DATA); 1186 if (__predict_false(m == NULL)) { 1187 ifp->if_ierrors++; 1188 return; 1189 } 1190 if (pktlen > MHLEN) { 1191 MCLGET(m, M_DONTWAIT); 1192 if (__predict_false(!(m->m_flags & M_EXT))) { 1193 ifp->if_ierrors++; 1194 m_freem(m); 1195 return; 1196 } 1197 } 1198 /* Finalize mbuf. */ 1199 wh = (struct ieee80211_frame *)((uint8_t *)&rxd[1] + infosz); 1200 memcpy(mtod(m, uint8_t *), wh, pktlen); 1201 m->m_pkthdr.len = m->m_len = pktlen; 1202 1203 s = splnet(); 1204 #if NBPFILTER > 0 1205 if (__predict_false(sc->sc_drvbpf != NULL)) { 1206 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1207 struct mbuf mb; 1208 1209 tap->wr_flags = 0; 1210 /* Map HW rate index to 802.11 rate. */ 1211 if (!(rxdw3 & R92C_RXDW3_HT)) { 1212 switch (rate) { 1213 /* CCK. */ 1214 case 0: tap->wr_rate = 2; break; 1215 case 1: tap->wr_rate = 4; break; 1216 case 2: tap->wr_rate = 11; break; 1217 case 3: tap->wr_rate = 22; break; 1218 /* OFDM. */ 1219 case 4: tap->wr_rate = 12; break; 1220 case 5: tap->wr_rate = 18; break; 1221 case 6: tap->wr_rate = 24; break; 1222 case 7: tap->wr_rate = 36; break; 1223 case 8: tap->wr_rate = 48; break; 1224 case 9: tap->wr_rate = 72; break; 1225 case 10: tap->wr_rate = 96; break; 1226 case 11: tap->wr_rate = 108; break; 1227 } 1228 if (rate <= 3) 1229 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1230 } else if (rate >= 12) { /* MCS0~15. */ 1231 /* Bit 7 set means HT MCS instead of rate. */ 1232 tap->wr_rate = 0x80 | (rate - 12); 1233 } 1234 tap->wr_dbm_antsignal = rssi; 1235 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1236 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1237 1238 mb.m_data = (caddr_t)tap; 1239 mb.m_len = sc->sc_rxtap_len; 1240 mb.m_next = m; 1241 mb.m_nextpkt = NULL; 1242 mb.m_type = 0; 1243 mb.m_flags = 0; 1244 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1245 } 1246 #endif 1247 1248 ni = ieee80211_find_rxnode(ic, wh); 1249 rxi.rxi_flags = 0; 1250 rxi.rxi_rssi = rssi; 1251 rxi.rxi_tstamp = 0; /* Unused. */ 1252 1253 /* Handle hardware decryption. */ 1254 if (((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) 1255 && (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && 1256 (ni->ni_flags & IEEE80211_NODE_RXPROT) && 1257 ni->ni_pairwise_key.k_cipher == IEEE80211_CIPHER_CCMP) { 1258 if (urtwn_ccmp_decap(sc, m, ni) != 0) { 1259 ifp->if_ierrors++; 1260 m_freem(m); 1261 ieee80211_release_node(ic, ni); 1262 return; 1263 } 1264 rxi.rxi_flags |= IEEE80211_RXI_HWDEC; 1265 } 1266 1267 ieee80211_inputm(ifp, m, ni, &rxi, ml); 1268 /* Node is no longer needed. */ 1269 ieee80211_release_node(ic, ni); 1270 splx(s); 1271 } 1272 1273 void 1274 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, 1275 usbd_status status) 1276 { 1277 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1278 struct urtwn_rx_data *data = priv; 1279 struct urtwn_softc *sc = data->sc; 1280 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1281 struct r92c_rx_desc_usb *rxd; 1282 uint32_t rxdw0; 1283 uint8_t *buf; 1284 int len, totlen, pktlen, infosz, npkts, error, align; 1285 1286 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1287 DPRINTF(("RX status=%d\n", status)); 1288 if (status == USBD_STALLED) 1289 usbd_clear_endpoint_stall_async(sc->rx_pipe); 1290 if (status != USBD_CANCELLED) 1291 goto resubmit; 1292 return; 1293 } 1294 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 1295 1296 if (__predict_false(len < sizeof(*rxd))) { 1297 DPRINTF(("xfer too short %d\n", len)); 1298 goto resubmit; 1299 } 1300 buf = data->buf; 1301 1302 /* Get the number of encapsulated frames. */ 1303 rxd = (struct r92c_rx_desc_usb *)buf; 1304 npkts = MS(letoh32(rxd->rxdw2), R92C_RXDW2_PKTCNT); 1305 DPRINTFN(4, ("Rx %d frames in one chunk\n", npkts)); 1306 1307 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1308 int ntries, type; 1309 struct r88e_tx_rpt_ccx *rxstat; 1310 1311 type = MS(letoh32(rxd->rxdw3), R88E_RXDW3_RPT); 1312 1313 if (type == R88E_RXDW3_RPT_TX1) { 1314 buf += sizeof(struct r92c_rx_desc_usb); 1315 rxstat = (struct r88e_tx_rpt_ccx *)buf; 1316 ntries = MS(letoh32(rxstat->rptb2), 1317 R88E_RPTB2_RETRY_CNT); 1318 1319 if (rxstat->rptb1 & R88E_RPTB1_PKT_OK) 1320 sc->amn.amn_txcnt++; 1321 if (ntries > 0) 1322 sc->amn.amn_retrycnt++; 1323 1324 goto resubmit; 1325 } 1326 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 1327 int type; 1328 struct r92e_c2h_tx_rpt *txrpt; 1329 1330 if (letoh32(rxd->rxdw2) & R92E_RXDW2_RPT_C2H) { 1331 if (len < sizeof(struct r92c_rx_desc_usb) + 2) 1332 goto resubmit; 1333 1334 type = buf[sizeof(struct r92c_rx_desc_usb)]; 1335 switch (type) { 1336 case R92C_C2HEVT_TX_REPORT: 1337 buf += sizeof(struct r92c_rx_desc_usb) + 2; 1338 txrpt = (struct r92e_c2h_tx_rpt *)buf; 1339 if (MS(txrpt->rptb2, R92E_RPTB2_RETRY_CNT) > 0) 1340 sc->amn.amn_retrycnt++; 1341 if ((txrpt->rptb0 & (R92E_RPTB0_RETRY_OVER | 1342 R92E_RPTB0_LIFE_EXPIRE)) == 0) 1343 sc->amn.amn_txcnt++; 1344 break; 1345 default: 1346 break; 1347 } 1348 goto resubmit; 1349 } 1350 } 1351 1352 align = (sc->sc_sc.chip & RTWN_CHIP_92E ? 7 : 127); 1353 1354 /* Process all of them. */ 1355 while (npkts-- > 0) { 1356 if (__predict_false(len < sizeof(*rxd))) 1357 break; 1358 rxd = (struct r92c_rx_desc_usb *)buf; 1359 rxdw0 = letoh32(rxd->rxdw0); 1360 1361 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1362 if (__predict_false(pktlen == 0)) 1363 break; 1364 1365 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1366 1367 /* Make sure everything fits in xfer. */ 1368 totlen = sizeof(*rxd) + infosz + pktlen; 1369 if (__predict_false(totlen > len)) 1370 break; 1371 1372 /* Process 802.11 frame. */ 1373 urtwn_rx_frame(sc, buf, pktlen, &ml); 1374 1375 /* Handle chunk alignment. */ 1376 totlen = (totlen + align) & ~align; 1377 buf += totlen; 1378 len -= totlen; 1379 } 1380 if_input(&ic->ic_if, &ml); 1381 1382 resubmit: 1383 /* Setup a new transfer. */ 1384 usbd_setup_xfer(xfer, sc->rx_pipe, data, data->buf, URTWN_RXBUFSZ, 1385 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, urtwn_rxeof); 1386 error = usbd_transfer(data->xfer); 1387 if (error != 0 && error != USBD_IN_PROGRESS) 1388 DPRINTF(("could not set up new transfer: %d\n", error)); 1389 } 1390 1391 void 1392 urtwn_txeof(struct usbd_xfer *xfer, void *priv, 1393 usbd_status status) 1394 { 1395 struct urtwn_tx_data *data = priv; 1396 struct urtwn_softc *sc = data->sc; 1397 struct ifnet *ifp = &sc->sc_sc.sc_ic.ic_if; 1398 int s; 1399 1400 s = splnet(); 1401 /* Put this Tx buffer back to our free list. */ 1402 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1403 1404 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1405 DPRINTF(("TX status=%d\n", status)); 1406 if (status == USBD_STALLED) 1407 usbd_clear_endpoint_stall_async(data->pipe); 1408 ifp->if_oerrors++; 1409 splx(s); 1410 return; 1411 } 1412 sc->sc_sc.sc_tx_timer = 0; 1413 1414 /* We just released a Tx buffer, notify Tx. */ 1415 if (ifq_is_oactive(&ifp->if_snd)) { 1416 ifq_clr_oactive(&ifp->if_snd); 1417 rtwn_start(ifp); 1418 } 1419 splx(s); 1420 } 1421 1422 void 1423 urtwn_tx_fill_desc(struct urtwn_softc *sc, uint8_t **txdp, struct mbuf *m, 1424 struct ieee80211_frame *wh, struct ieee80211_key *k, 1425 struct ieee80211_node *ni) 1426 { 1427 struct r92c_tx_desc_usb *txd; 1428 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1429 uint8_t raid, type; 1430 uint32_t pktlen; 1431 1432 txd = (struct r92c_tx_desc_usb *)*txdp; 1433 (*txdp) += sizeof(*txd); 1434 memset(txd, 0, sizeof(*txd)); 1435 1436 pktlen = m->m_pkthdr.len; 1437 if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) { 1438 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, 1439 R92C_TXDW1_CIPHER_AES)); 1440 pktlen += IEEE80211_CCMP_HDRLEN; 1441 } 1442 1443 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1444 1445 txd->txdw0 |= htole32( 1446 SM(R92C_TXDW0_PKTLEN, pktlen) | 1447 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1448 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1449 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1450 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1451 1452 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1453 type == IEEE80211_FC0_TYPE_DATA) { 1454 if (ic->ic_curmode == IEEE80211_MODE_11B || 1455 (sc->sc_sc.sc_flags & RTWN_FLAG_FORCE_RAID_11B)) 1456 raid = R92C_RAID_11B; 1457 else 1458 raid = R92C_RAID_11BG; 1459 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1460 txd->txdw1 |= htole32( 1461 SM(R88E_TXDW1_MACID, R92C_MACID_BSS) | 1462 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1463 SM(R92C_TXDW1_RAID, raid)); 1464 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1465 /* Request TX status report for AMRR */ 1466 txd->txdw2 |= htole32(R92C_TXDW2_CCX_RPT); 1467 } else { 1468 txd->txdw1 |= htole32( 1469 SM(R92C_TXDW1_MACID, R92C_MACID_BSS) | 1470 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1471 SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1472 } 1473 1474 if (pktlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 1475 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1476 R92C_TXDW4_HWRTSEN); 1477 } else if (ic->ic_flags & IEEE80211_F_USEPROT) { 1478 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1479 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1480 R92C_TXDW4_HWRTSEN); 1481 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1482 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1483 R92C_TXDW4_HWRTSEN); 1484 } 1485 } 1486 txd->txdw5 |= htole32(0x0001ff00); 1487 1488 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1489 /* Use AMRR */ 1490 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1491 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 1492 ni->ni_txrate)); 1493 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 1494 ni->ni_txrate)); 1495 } else { 1496 /* Send RTS at OFDM24 and data at OFDM54. */ 1497 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1498 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1499 } 1500 } else { 1501 txd->txdw1 |= htole32( 1502 SM(R92C_TXDW1_MACID, 0) | 1503 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1504 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1505 1506 /* Force CCK1. */ 1507 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1508 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1509 } 1510 /* Set sequence number (already little endian). */ 1511 txd->txdseq |= (*(uint16_t *)wh->i_seq) >> IEEE80211_SEQ_SEQ_SHIFT; 1512 1513 if (!ieee80211_has_qos(wh)) { 1514 /* Use HW sequence numbering for non-QoS frames. */ 1515 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1516 txd->txdseq |= htole16(R92C_TXDW3_HWSEQEN); 1517 } else 1518 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1519 } 1520 1521 void 1522 urtwn_tx_fill_desc_gen2(struct urtwn_softc *sc, uint8_t **txdp, struct mbuf *m, 1523 struct ieee80211_frame *wh, struct ieee80211_key *k, 1524 struct ieee80211_node *ni) 1525 { 1526 struct r92e_tx_desc_usb *txd; 1527 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1528 uint8_t raid, type; 1529 uint32_t pktlen; 1530 1531 txd = (struct r92e_tx_desc_usb *)*txdp; 1532 (*txdp) += sizeof(*txd); 1533 memset(txd, 0, sizeof(*txd)); 1534 1535 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1536 1537 pktlen = m->m_pkthdr.len; 1538 if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) { 1539 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, 1540 R92C_TXDW1_CIPHER_AES)); 1541 pktlen += IEEE80211_CCMP_HDRLEN; 1542 } 1543 1544 txd->txdw0 |= htole32( 1545 SM(R92C_TXDW0_PKTLEN, pktlen) | 1546 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1547 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1548 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1549 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1550 1551 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1552 type == IEEE80211_FC0_TYPE_DATA) { 1553 if (ic->ic_curmode == IEEE80211_MODE_11B || 1554 (sc->sc_sc.sc_flags & RTWN_FLAG_FORCE_RAID_11B)) 1555 raid = R92E_RAID_11B; 1556 else 1557 raid = R92E_RAID_11BG; 1558 txd->txdw1 |= htole32( 1559 SM(R92E_TXDW1_MACID, R92C_MACID_BSS) | 1560 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1561 SM(R92C_TXDW1_RAID, raid)); 1562 /* Request TX status report for AMRR */ 1563 txd->txdw2 |= htole32(R92C_TXDW2_CCX_RPT | R88E_TXDW2_AGGBK); 1564 1565 if (pktlen + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 1566 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1567 R92C_TXDW4_HWRTSEN); 1568 } else if (ic->ic_flags & IEEE80211_F_USEPROT) { 1569 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1570 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1571 R92C_TXDW4_HWRTSEN); 1572 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1573 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1574 R92C_TXDW4_HWRTSEN); 1575 } 1576 } 1577 txd->txdw5 |= htole32(0x0001ff00); 1578 1579 /* Use AMRR */ 1580 txd->txdw3 |= htole32(R92E_TXDW3_DRVRATE); 1581 txd->txdw4 |= htole32(SM(R92E_TXDW4_RTSRATE, ni->ni_txrate)); 1582 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATE, ni->ni_txrate)); 1583 } else { 1584 txd->txdw1 |= htole32( 1585 SM(R92E_TXDW1_MACID, 0) | 1586 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1587 SM(R92C_TXDW1_RAID, R92E_RAID_11B)); 1588 1589 /* Force CCK1. */ 1590 txd->txdw3 |= htole32(R92E_TXDW3_DRVRATE); 1591 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATE, 0)); 1592 } 1593 txd->txdw4 |= htole32(SM(R92E_TXDW4_DATARATEFB, 0x1f)); 1594 1595 txd->txdseq2 |= htole16(SM(R92E_TXDSEQ2_HWSEQ, *(uint16_t *)wh->i_seq)); 1596 1597 if (!ieee80211_has_qos(wh)) { 1598 /* Use HW sequence numbering for non-QoS frames. */ 1599 txd->txdw7 |= htole16(R92C_TXDW3_HWSEQEN); 1600 } 1601 } 1602 1603 int 1604 urtwn_tx(void *cookie, struct mbuf *m, struct ieee80211_node *ni) 1605 { 1606 struct urtwn_softc *sc = cookie; 1607 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1608 struct ieee80211_frame *wh; 1609 struct ieee80211_key *k = NULL; 1610 struct urtwn_tx_data *data; 1611 struct usbd_pipe *pipe; 1612 uint16_t qos, sum; 1613 uint8_t tid, qid; 1614 int i, xferlen, error, headerlen; 1615 uint8_t *txdp; 1616 1617 wh = mtod(m, struct ieee80211_frame *); 1618 1619 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1620 k = ieee80211_get_txkey(ic, wh, ni); 1621 if (k->k_cipher != IEEE80211_CIPHER_CCMP) { 1622 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1623 return (ENOBUFS); 1624 wh = mtod(m, struct ieee80211_frame *); 1625 } 1626 } 1627 1628 if (ieee80211_has_qos(wh)) { 1629 qos = ieee80211_get_qos(wh); 1630 tid = qos & IEEE80211_QOS_TID; 1631 qid = ieee80211_up_to_ac(ic, tid); 1632 } else if ((wh->i_fc[1] & IEEE80211_FC0_TYPE_MASK) 1633 != IEEE80211_FC0_TYPE_DATA) { 1634 /* Use AC VO for management frames. */ 1635 qid = EDCA_AC_VO; 1636 } else 1637 qid = EDCA_AC_BE; 1638 1639 /* Get the USB pipe to use for this AC. */ 1640 pipe = sc->tx_pipe[sc->ac2idx[qid]]; 1641 1642 /* Grab a Tx buffer from our free list. */ 1643 data = TAILQ_FIRST(&sc->tx_free_list); 1644 TAILQ_REMOVE(&sc->tx_free_list, data, next); 1645 1646 /* Fill Tx descriptor. */ 1647 txdp = data->buf; 1648 if (sc->sc_sc.chip & RTWN_CHIP_92E) 1649 urtwn_tx_fill_desc_gen2(sc, &txdp, m, wh, k, ni); 1650 else 1651 urtwn_tx_fill_desc(sc, &txdp, m, wh, k, ni); 1652 1653 /* Compute Tx descriptor checksum. */ 1654 sum = 0; 1655 for (i = 0; i < R92C_TXDESC_SUMSIZE / 2; i++) 1656 sum ^= ((uint16_t *)data->buf)[i]; 1657 ((uint16_t *)data->buf)[R92C_TXDESC_SUMOFFSET] = sum; 1658 1659 #if NBPFILTER > 0 1660 if (__predict_false(sc->sc_drvbpf != NULL)) { 1661 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1662 struct mbuf mb; 1663 1664 tap->wt_flags = 0; 1665 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1666 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1667 1668 mb.m_data = (caddr_t)tap; 1669 mb.m_len = sc->sc_txtap_len; 1670 mb.m_next = m; 1671 mb.m_nextpkt = NULL; 1672 mb.m_type = 0; 1673 mb.m_flags = 0; 1674 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1675 } 1676 #endif 1677 1678 if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) { 1679 xferlen = (txdp - data->buf) + m->m_pkthdr.len + 1680 IEEE80211_CCMP_HDRLEN; 1681 headerlen = ieee80211_get_hdrlen(wh); 1682 1683 m_copydata(m, 0, headerlen, txdp); 1684 txdp += headerlen; 1685 1686 k->k_tsc++; 1687 txdp[0] = k->k_tsc; 1688 txdp[1] = k->k_tsc >> 8; 1689 txdp[2] = 0; 1690 txdp[3] = k->k_id | IEEE80211_WEP_EXTIV; 1691 txdp[4] = k->k_tsc >> 16; 1692 txdp[5] = k->k_tsc >> 24; 1693 txdp[6] = k->k_tsc >> 32; 1694 txdp[7] = k->k_tsc >> 40; 1695 txdp += IEEE80211_CCMP_HDRLEN; 1696 1697 m_copydata(m, headerlen, m->m_pkthdr.len - headerlen, txdp); 1698 m_freem(m); 1699 } else { 1700 xferlen = (txdp - data->buf) + m->m_pkthdr.len; 1701 m_copydata(m, 0, m->m_pkthdr.len, txdp); 1702 m_freem(m); 1703 } 1704 1705 data->pipe = pipe; 1706 usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen, 1707 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTWN_TX_TIMEOUT, 1708 urtwn_txeof); 1709 error = usbd_transfer(data->xfer); 1710 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) { 1711 /* Put this Tx buffer back to our free list. */ 1712 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1713 return (error); 1714 } 1715 ieee80211_release_node(ic, ni); 1716 return (0); 1717 } 1718 1719 int 1720 urtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1721 { 1722 struct rtwn_softc *sc_sc = ifp->if_softc; 1723 struct device *self = sc_sc->sc_pdev; 1724 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1725 int error; 1726 1727 if (usbd_is_dying(sc->sc_udev)) 1728 return ENXIO; 1729 1730 usbd_ref_incr(sc->sc_udev); 1731 error = rtwn_ioctl(ifp, cmd, data); 1732 usbd_ref_decr(sc->sc_udev); 1733 1734 return (error); 1735 } 1736 1737 int 1738 urtwn_r92c_power_on(struct urtwn_softc *sc) 1739 { 1740 uint32_t reg; 1741 int ntries; 1742 1743 /* Wait for autoload done bit. */ 1744 for (ntries = 0; ntries < 1000; ntries++) { 1745 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 1746 break; 1747 DELAY(5); 1748 } 1749 if (ntries == 1000) { 1750 printf("%s: timeout waiting for chip autoload\n", 1751 sc->sc_dev.dv_xname); 1752 return (ETIMEDOUT); 1753 } 1754 1755 /* Unlock ISO/CLK/Power control register. */ 1756 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 1757 /* Move SPS into PWM mode. */ 1758 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 1759 DELAY(100); 1760 1761 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 1762 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 1763 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 1764 reg | R92C_LDOV12D_CTRL_LDV12_EN); 1765 DELAY(100); 1766 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 1767 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 1768 ~R92C_SYS_ISO_CTRL_MD2PP); 1769 } 1770 1771 /* Auto enable WLAN. */ 1772 urtwn_write_2(sc, R92C_APS_FSMCO, 1773 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1774 for (ntries = 0; ntries < 1000; ntries++) { 1775 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1776 R92C_APS_FSMCO_APFM_ONMAC)) 1777 break; 1778 DELAY(5); 1779 } 1780 if (ntries == 1000) { 1781 printf("%s: timeout waiting for MAC auto ON\n", 1782 sc->sc_dev.dv_xname); 1783 return (ETIMEDOUT); 1784 } 1785 1786 /* Enable radio, GPIO and LED functions. */ 1787 urtwn_write_2(sc, R92C_APS_FSMCO, 1788 R92C_APS_FSMCO_AFSM_HSUS | 1789 R92C_APS_FSMCO_PDN_EN | 1790 R92C_APS_FSMCO_PFM_ALDN); 1791 /* Release RF digital isolation. */ 1792 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1793 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 1794 1795 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1796 reg = urtwn_read_2(sc, R92C_CR); 1797 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1798 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1799 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 1800 R92C_CR_ENSEC; 1801 urtwn_write_2(sc, R92C_CR, reg); 1802 1803 urtwn_write_1(sc, 0xfe10, 0x19); 1804 return (0); 1805 } 1806 1807 int 1808 urtwn_r92e_power_on(struct urtwn_softc *sc) 1809 { 1810 uint32_t reg; 1811 int ntries; 1812 1813 if (urtwn_read_4(sc, R92C_SYS_CFG) & R92E_SYS_CFG_SPSLDO_SEL) { 1814 /* LDO. */ 1815 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0xc3); 1816 } else { 1817 reg = urtwn_read_4(sc, R92C_SYS_SWR_CTRL2); 1818 reg &= 0xff0fffff; 1819 reg |= 0x00500000; 1820 urtwn_write_4(sc, R92C_SYS_SWR_CTRL2, reg); 1821 urtwn_write_1(sc, R92E_LDO_SWR_CTRL, 0x83); 1822 } 1823 1824 /* 40MHz crystal source */ 1825 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 1826 urtwn_read_1(sc, R92C_AFE_PLL_CTRL) & 0xfb); 1827 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL_EXT, 1828 urtwn_read_4(sc, R92C_AFE_XTAL_CTRL_EXT) & 0xfffffc7f); 1829 1830 urtwn_write_1(sc, R92C_AFE_PLL_CTRL, 1831 urtwn_read_1(sc, R92C_AFE_PLL_CTRL) & 0xbf); 1832 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL_EXT, 1833 urtwn_read_4(sc, R92C_AFE_XTAL_CTRL_EXT) & 0xffdfffff); 1834 1835 /* Disable HWPDN. */ 1836 urtwn_write_2(sc, R92C_APS_FSMCO, 1837 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 1838 for (ntries = 0; ntries < 5000; ntries++) { 1839 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 1840 break; 1841 DELAY(10); 1842 } 1843 if (ntries == 5000) { 1844 printf("%s: timeout waiting for chip power up\n", 1845 sc->sc_dev.dv_xname); 1846 return (ETIMEDOUT); 1847 } 1848 1849 /* Disable WL suspend. */ 1850 urtwn_write_2(sc, R92C_APS_FSMCO, 1851 urtwn_read_2(sc, R92C_APS_FSMCO) & 1852 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 1853 1854 /* Auto enable WLAN. */ 1855 urtwn_write_4(sc, R92C_APS_FSMCO, 1856 urtwn_read_4(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_RDY_MACON); 1857 urtwn_write_2(sc, R92C_APS_FSMCO, 1858 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1859 for (ntries = 0; ntries < 5000; ntries++) { 1860 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1861 R92C_APS_FSMCO_APFM_ONMAC)) 1862 break; 1863 DELAY(10); 1864 } 1865 if (ntries == 5000) { 1866 printf("%s: timeout waiting for MAC auto ON\n", 1867 sc->sc_dev.dv_xname); 1868 return (ETIMEDOUT); 1869 } 1870 1871 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1872 urtwn_write_2(sc, R92C_CR, 0); 1873 reg = urtwn_read_2(sc, R92C_CR); 1874 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1875 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1876 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 1877 urtwn_write_2(sc, R92C_CR, reg); 1878 return (0); 1879 } 1880 1881 int 1882 urtwn_r88e_power_on(struct urtwn_softc *sc) 1883 { 1884 uint32_t reg; 1885 int ntries; 1886 1887 /* Wait for power ready bit. */ 1888 for (ntries = 0; ntries < 5000; ntries++) { 1889 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 1890 break; 1891 DELAY(10); 1892 } 1893 if (ntries == 5000) { 1894 printf("%s: timeout waiting for chip power up\n", 1895 sc->sc_dev.dv_xname); 1896 return (ETIMEDOUT); 1897 } 1898 1899 /* Reset BB. */ 1900 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 1901 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 1902 R92C_SYS_FUNC_EN_BB_GLB_RST)); 1903 1904 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 1905 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 1906 1907 /* Disable HWPDN. */ 1908 urtwn_write_2(sc, R92C_APS_FSMCO, 1909 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 1910 /* Disable WL suspend. */ 1911 urtwn_write_2(sc, R92C_APS_FSMCO, 1912 urtwn_read_2(sc, R92C_APS_FSMCO) & 1913 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 1914 1915 /* Auto enable WLAN. */ 1916 urtwn_write_2(sc, R92C_APS_FSMCO, 1917 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1918 for (ntries = 0; ntries < 5000; ntries++) { 1919 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1920 R92C_APS_FSMCO_APFM_ONMAC)) 1921 break; 1922 DELAY(10); 1923 } 1924 if (ntries == 5000) { 1925 printf("%s: timeout waiting for MAC auto ON\n", 1926 sc->sc_dev.dv_xname); 1927 return (ETIMEDOUT); 1928 } 1929 1930 /* Enable LDO normal mode. */ 1931 urtwn_write_1(sc, R92C_LPLDO_CTRL, 1932 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 1933 1934 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1935 urtwn_write_2(sc, R92C_CR, 0); 1936 reg = urtwn_read_2(sc, R92C_CR); 1937 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1938 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1939 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 1940 urtwn_write_2(sc, R92C_CR, reg); 1941 return (0); 1942 } 1943 1944 int 1945 urtwn_llt_init(struct urtwn_softc *sc, int page_count) 1946 { 1947 int i, error, pktbuf_count; 1948 1949 pktbuf_count = (sc->sc_sc.chip & RTWN_CHIP_88E) ? 1950 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 1951 1952 /* Reserve pages [0; page_count]. */ 1953 for (i = 0; i < page_count; i++) { 1954 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1955 return (error); 1956 } 1957 /* NB: 0xff indicates end-of-list. */ 1958 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 1959 return (error); 1960 /* 1961 * Use pages [page_count + 1; pktbuf_count - 1] 1962 * as ring buffer. 1963 */ 1964 for (++i; i < pktbuf_count - 1; i++) { 1965 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1966 return (error); 1967 } 1968 /* Make the last page point to the beginning of the ring buffer. */ 1969 error = urtwn_llt_write(sc, i, page_count + 1); 1970 return (error); 1971 } 1972 1973 int 1974 urtwn_auto_llt_init(struct urtwn_softc *sc) 1975 { 1976 int ntries; 1977 1978 urtwn_write_4(sc, R92E_AUTO_LLT, urtwn_read_4(sc, 1979 R92E_AUTO_LLT) | R92E_AUTO_LLT_EN); 1980 for (ntries = 0; ntries < 1000; ntries++) { 1981 if (!(urtwn_read_4(sc, R92E_AUTO_LLT) & R92E_AUTO_LLT_EN)) 1982 return (0); 1983 DELAY(2); 1984 } 1985 1986 return (ETIMEDOUT); 1987 } 1988 1989 int 1990 urtwn_fw_loadpage(void *cookie, int page, uint8_t *buf, int len) 1991 { 1992 struct urtwn_softc *sc = cookie; 1993 uint32_t reg; 1994 int off, mlen, error = 0; 1995 1996 reg = urtwn_read_4(sc, R92C_MCUFWDL); 1997 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 1998 urtwn_write_4(sc, R92C_MCUFWDL, reg); 1999 2000 off = R92C_FW_START_ADDR; 2001 while (len > 0) { 2002 if (len > 196) 2003 mlen = 196; 2004 else if (len > 4) 2005 mlen = 4; 2006 else 2007 mlen = 1; 2008 error = urtwn_write_region_1(sc, off, buf, mlen); 2009 if (error != 0) 2010 break; 2011 off += mlen; 2012 buf += mlen; 2013 len -= mlen; 2014 } 2015 return (error); 2016 } 2017 2018 int 2019 urtwn_load_firmware(void *cookie, u_char **fw, size_t *len) 2020 { 2021 struct urtwn_softc *sc = cookie; 2022 const char *name; 2023 int error; 2024 2025 if (sc->sc_sc.chip & RTWN_CHIP_92E) 2026 name = "urtwn-rtl8192eu_nic"; 2027 else if (sc->sc_sc.chip & RTWN_CHIP_88E) 2028 name = "urtwn-rtl8188eufw"; 2029 else if ((sc->sc_sc.chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2030 RTWN_CHIP_UMC_A_CUT) 2031 name = "urtwn-rtl8192cfwU"; 2032 else 2033 name = "urtwn-rtl8192cfwT"; 2034 2035 error = loadfirmware(name, fw, len); 2036 if (error) 2037 printf("%s: could not read firmware %s (error %d)\n", 2038 sc->sc_dev.dv_xname, name, error); 2039 return (error); 2040 } 2041 2042 int 2043 urtwn_dma_init(void *cookie) 2044 { 2045 struct urtwn_softc *sc = cookie; 2046 uint32_t reg; 2047 uint16_t dmasize; 2048 int hqpages, lqpages, nqpages, pagecnt, boundary; 2049 int error, hashq, haslq, hasnq; 2050 2051 /* Default initialization of chipset values. */ 2052 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2053 hqpages = R88E_HQ_NPAGES; 2054 lqpages = R88E_LQ_NPAGES; 2055 nqpages = R88E_NQ_NPAGES; 2056 pagecnt = R88E_TX_PAGE_COUNT; 2057 boundary = R88E_TX_PAGE_BOUNDARY; 2058 dmasize = R88E_MAX_RX_DMA_SIZE; 2059 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2060 hqpages = R92E_HQ_NPAGES; 2061 lqpages = R92E_LQ_NPAGES; 2062 nqpages = R92E_NQ_NPAGES; 2063 pagecnt = R92E_TX_PAGE_COUNT; 2064 boundary = R92E_TX_PAGE_BOUNDARY; 2065 dmasize = R92E_MAX_RX_DMA_SIZE; 2066 } else { 2067 hqpages = R92C_HQ_NPAGES; 2068 lqpages = R92C_LQ_NPAGES; 2069 nqpages = R92C_NQ_NPAGES; 2070 pagecnt = R92C_TX_PAGE_COUNT; 2071 boundary = R92C_TX_PAGE_BOUNDARY; 2072 dmasize = R92C_MAX_RX_DMA_SIZE; 2073 } 2074 2075 /* Initialize LLT table. */ 2076 if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2077 error = urtwn_auto_llt_init(sc); 2078 } else { 2079 error = urtwn_llt_init(sc, pagecnt); 2080 } 2081 if (error != 0) 2082 return (error); 2083 2084 /* Get Tx queues to USB endpoints mapping. */ 2085 hashq = hasnq = haslq = 0; 2086 switch (sc->ntx) { 2087 case 3: 2088 haslq = 1; 2089 pagecnt -= lqpages; 2090 /* FALLTHROUGH */ 2091 case 2: 2092 hasnq = 1; 2093 pagecnt -= nqpages; 2094 /* FALLTHROUGH */ 2095 case 1: 2096 hashq = 1; 2097 pagecnt -= hqpages; 2098 break; 2099 } 2100 2101 /* Set number of pages for normal priority queue. */ 2102 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2103 urtwn_write_4(sc, R92C_RQPN, 2104 /* Set number of pages for public queue. */ 2105 SM(R92C_RQPN_PUBQ, pagecnt) | 2106 /* Set number of pages for high priority queue. */ 2107 SM(R92C_RQPN_HPQ, hashq ? hqpages : 0) | 2108 /* Set number of pages for low priority queue. */ 2109 SM(R92C_RQPN_LPQ, haslq ? lqpages : 0) | 2110 /* Load values. */ 2111 R92C_RQPN_LD); 2112 2113 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, boundary); 2114 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, boundary); 2115 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, boundary); 2116 urtwn_write_1(sc, R92C_TRXFF_BNDY, boundary); 2117 urtwn_write_1(sc, R92C_TDECTRL + 1, boundary); 2118 2119 /* Set queue to USB pipe mapping. */ 2120 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2121 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2122 if (haslq) 2123 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2124 else if (hashq) { 2125 if (!hasnq) 2126 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2127 else 2128 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2129 } 2130 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2131 2132 /* Set Tx/Rx transfer page boundary. */ 2133 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, dmasize - 1); 2134 2135 if (!(sc->sc_sc.chip & RTWN_CHIP_92E)) { 2136 /* Set Tx/Rx transfer page size. */ 2137 urtwn_write_1(sc, R92C_PBP, 2138 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2139 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2140 } 2141 return (error); 2142 } 2143 2144 void 2145 urtwn_aggr_init(void *cookie) 2146 { 2147 struct urtwn_softc *sc = cookie; 2148 uint32_t reg = 0; 2149 int dmasize, dmatiming, ndesc; 2150 2151 /* Set burst packet length. */ 2152 if (sc->sc_sc.chip & RTWN_CHIP_92E) 2153 urtwn_burstlen_init(sc); 2154 2155 if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2156 dmasize = 6; 2157 dmatiming = 32; 2158 ndesc = 3; 2159 } else { 2160 dmasize = 48; 2161 dmatiming = 4; 2162 ndesc = (sc->sc_sc.chip & RTWN_CHIP_88E) ? 1 : 6; 2163 } 2164 2165 /* Tx aggregation setting. */ 2166 if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2167 urtwn_write_1(sc, R92E_DWBCN1_CTRL, ndesc << 1); 2168 } else { 2169 reg = urtwn_read_4(sc, R92C_TDECTRL); 2170 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, ndesc); 2171 urtwn_write_4(sc, R92C_TDECTRL, reg); 2172 } 2173 2174 /* Rx aggregation setting. */ 2175 if (!(sc->sc_sc.chip & RTWN_CHIP_92E)) { 2176 urtwn_write_1(sc, R92C_TRXDMA_CTRL, 2177 urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 2178 R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 2179 } 2180 2181 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, dmasize); 2182 if (sc->sc_sc.chip & (RTWN_CHIP_92C | RTWN_CHIP_88C)) 2183 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, dmatiming); 2184 else 2185 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, dmatiming); 2186 2187 /* Drop incorrect bulk out. */ 2188 urtwn_write_4(sc, R92C_TXDMA_OFFSET_CHK, 2189 urtwn_read_4(sc, R92C_TXDMA_OFFSET_CHK) | 2190 R92C_TXDMA_OFFSET_CHK_DROP_DATA_EN); 2191 } 2192 2193 void 2194 urtwn_mac_init(void *cookie) 2195 { 2196 struct urtwn_softc *sc = cookie; 2197 int i; 2198 2199 /* Write MAC initialization values. */ 2200 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2201 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2202 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2203 rtl8188eu_mac[i].val); 2204 } 2205 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2206 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2207 for (i = 0; i < nitems(rtl8192eu_mac); i++) { 2208 urtwn_write_1(sc, rtl8192eu_mac[i].reg, 2209 rtl8192eu_mac[i].val); 2210 } 2211 } else { 2212 for (i = 0; i < nitems(rtl8192cu_mac); i++) 2213 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2214 rtl8192cu_mac[i].val); 2215 } 2216 } 2217 2218 void 2219 urtwn_bb_init(void *cookie) 2220 { 2221 struct urtwn_softc *sc = cookie; 2222 const struct r92c_bb_prog *prog; 2223 uint32_t reg; 2224 uint8_t xtal; 2225 int i; 2226 2227 /* Enable BB and RF. */ 2228 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2229 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2230 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2231 R92C_SYS_FUNC_EN_DIO_RF); 2232 2233 if (!(sc->sc_sc.chip & (RTWN_CHIP_88E | RTWN_CHIP_92E))) 2234 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2235 2236 urtwn_write_1(sc, R92C_RF_CTRL, 2237 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2238 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2239 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2240 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2241 2242 if (!(sc->sc_sc.chip & (RTWN_CHIP_88E | RTWN_CHIP_92E))) { 2243 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2244 urtwn_write_1(sc, 0x15, 0xe9); 2245 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2246 } 2247 2248 /* Select BB programming based on board type. */ 2249 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2250 prog = &rtl8188eu_bb_prog; 2251 else if (sc->sc_sc.chip & RTWN_CHIP_92E) 2252 prog = &rtl8192eu_bb_prog; 2253 else if (!(sc->sc_sc.chip & RTWN_CHIP_92C)) { 2254 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD) 2255 prog = &rtl8188ce_bb_prog; 2256 else if (sc->sc_sc.board_type == R92C_BOARD_TYPE_HIGHPA) 2257 prog = &rtl8188ru_bb_prog; 2258 else 2259 prog = &rtl8188cu_bb_prog; 2260 } else { 2261 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD) 2262 prog = &rtl8192ce_bb_prog; 2263 else 2264 prog = &rtl8192cu_bb_prog; 2265 } 2266 /* Write BB initialization values. */ 2267 for (i = 0; i < prog->count; i++) { 2268 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2269 DELAY(1); 2270 } 2271 2272 if (sc->sc_sc.chip & RTWN_CHIP_92C_1T2R) { 2273 /* 8192C 1T only configuration. */ 2274 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2275 reg = (reg & ~0x00000003) | 0x2; 2276 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2277 2278 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2279 reg = (reg & ~0x00300033) | 0x00200022; 2280 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2281 2282 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2283 reg = (reg & ~0xff000000) | 0x45 << 24; 2284 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2285 2286 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2287 reg = (reg & ~0x000000ff) | 0x23; 2288 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2289 2290 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2291 reg = (reg & ~0x00000030) | 1 << 4; 2292 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2293 2294 reg = urtwn_bb_read(sc, 0xe74); 2295 reg = (reg & ~0x0c000000) | 2 << 26; 2296 urtwn_bb_write(sc, 0xe74, reg); 2297 reg = urtwn_bb_read(sc, 0xe78); 2298 reg = (reg & ~0x0c000000) | 2 << 26; 2299 urtwn_bb_write(sc, 0xe78, reg); 2300 reg = urtwn_bb_read(sc, 0xe7c); 2301 reg = (reg & ~0x0c000000) | 2 << 26; 2302 urtwn_bb_write(sc, 0xe7c, reg); 2303 reg = urtwn_bb_read(sc, 0xe80); 2304 reg = (reg & ~0x0c000000) | 2 << 26; 2305 urtwn_bb_write(sc, 0xe80, reg); 2306 reg = urtwn_bb_read(sc, 0xe88); 2307 reg = (reg & ~0x0c000000) | 2 << 26; 2308 urtwn_bb_write(sc, 0xe88, reg); 2309 } 2310 2311 /* Write AGC values. */ 2312 for (i = 0; i < prog->agccount; i++) { 2313 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2314 prog->agcvals[i]); 2315 DELAY(1); 2316 } 2317 2318 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2319 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2320 DELAY(1); 2321 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2322 DELAY(1); 2323 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2324 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040022); 2325 DELAY(1); 2326 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040020); 2327 DELAY(1); 2328 } 2329 2330 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 2331 xtal = sc->sc_sc.crystal_cap & 0x3f; 2332 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2333 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2334 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, xtal | xtal << 6)); 2335 } else if (sc->sc_sc.chip & RTWN_CHIP_92E) { 2336 xtal = sc->sc_sc.crystal_cap & 0x3f; 2337 reg = urtwn_read_4(sc, R92C_AFE_CTRL3); 2338 reg &= 0xff000fff; 2339 reg |= (xtal | (xtal << 6)) << 12; 2340 urtwn_write_4(sc, R92C_AFE_CTRL3, reg); 2341 2342 urtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 0x000f81fb); 2343 } 2344 2345 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & R92C_HSSI_PARAM2_CCK_HIPWR) 2346 sc->sc_sc.sc_flags |= RTWN_FLAG_CCK_HIPWR; 2347 } 2348 2349 void 2350 urtwn_burstlen_init(struct urtwn_softc *sc) 2351 { 2352 uint8_t reg; 2353 2354 reg = urtwn_read_1(sc, R92E_RXDMA_PRO); 2355 reg &= ~0x30; 2356 switch (sc->sc_udev->speed) { 2357 case USB_SPEED_HIGH: 2358 urtwn_write_1(sc, R92E_RXDMA_PRO, reg | 0x1e); 2359 break; 2360 default: 2361 urtwn_write_1(sc, R92E_RXDMA_PRO, reg | 0x2e); 2362 break; 2363 } 2364 } 2365 2366 int 2367 urtwn_power_on(void *cookie) 2368 { 2369 struct urtwn_softc *sc = cookie; 2370 2371 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2372 return (urtwn_r88e_power_on(sc)); 2373 else if (sc->sc_sc.chip & RTWN_CHIP_92E) 2374 return (urtwn_r92e_power_on(sc)); 2375 2376 return (urtwn_r92c_power_on(sc)); 2377 } 2378 2379 int 2380 urtwn_alloc_buffers(void *cookie) 2381 { 2382 struct urtwn_softc *sc = cookie; 2383 int error; 2384 2385 /* Init host async commands ring. */ 2386 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 2387 2388 /* Allocate Tx/Rx buffers. */ 2389 error = urtwn_alloc_rx_list(sc); 2390 if (error != 0) { 2391 printf("%s: could not allocate Rx buffers\n", 2392 sc->sc_dev.dv_xname); 2393 return (error); 2394 } 2395 error = urtwn_alloc_tx_list(sc); 2396 if (error != 0) { 2397 printf("%s: could not allocate Tx buffers\n", 2398 sc->sc_dev.dv_xname); 2399 return (error); 2400 } 2401 2402 return (0); 2403 } 2404 2405 int 2406 urtwn_init(void *cookie) 2407 { 2408 struct urtwn_softc *sc = cookie; 2409 int i, error; 2410 2411 if (sc->sc_sc.chip & RTWN_CHIP_92E) 2412 urtwn_write_1(sc, R92C_ACLK_MON, 0); 2413 2414 /* Queue Rx xfers. */ 2415 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 2416 struct urtwn_rx_data *data = &sc->rx_data[i]; 2417 2418 usbd_setup_xfer(data->xfer, sc->rx_pipe, data, data->buf, 2419 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 2420 USBD_NO_TIMEOUT, urtwn_rxeof); 2421 error = usbd_transfer(data->xfer); 2422 if (error != 0 && error != USBD_IN_PROGRESS) 2423 return (error); 2424 } 2425 2426 ieee80211_amrr_node_init(&sc->amrr, &sc->amn); 2427 2428 /* 2429 * Enable TX reports for AMRR. 2430 * In order to get reports we need to explicitly reset the register. 2431 */ 2432 if (sc->sc_sc.chip & RTWN_CHIP_88E) 2433 urtwn_write_1(sc, R88E_TX_RPT_CTRL, (urtwn_read_1(sc, 2434 R88E_TX_RPT_CTRL) & ~0) | R88E_TX_RPT_CTRL_EN); 2435 2436 return (0); 2437 } 2438 2439 void 2440 urtwn_stop(void *cookie) 2441 { 2442 struct urtwn_softc *sc = cookie; 2443 int i; 2444 2445 /* Abort Tx. */ 2446 for (i = 0; i < R92C_MAX_EPOUT; i++) { 2447 if (sc->tx_pipe[i] != NULL) 2448 usbd_abort_pipe(sc->tx_pipe[i]); 2449 } 2450 /* Stop Rx pipe. */ 2451 usbd_abort_pipe(sc->rx_pipe); 2452 /* Free Tx/Rx buffers. */ 2453 urtwn_free_tx_list(sc); 2454 urtwn_free_rx_list(sc); 2455 } 2456 2457 int 2458 urtwn_is_oactive(void *cookie) 2459 { 2460 struct urtwn_softc *sc = cookie; 2461 2462 return (TAILQ_EMPTY(&sc->tx_free_list)); 2463 } 2464