1 /* $OpenBSD: if_urtwn.c,v 1.66 2016/07/21 08:38:33 stsp Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 22 */ 23 24 #include "bpfilter.h" 25 26 #include <sys/param.h> 27 #include <sys/sockio.h> 28 #include <sys/mbuf.h> 29 #include <sys/kernel.h> 30 #include <sys/socket.h> 31 #include <sys/systm.h> 32 #include <sys/timeout.h> 33 #include <sys/conf.h> 34 #include <sys/device.h> 35 #include <sys/endian.h> 36 37 #include <machine/intr.h> 38 39 #if NBPFILTER > 0 40 #include <net/bpf.h> 41 #endif 42 #include <net/if.h> 43 #include <net/if_dl.h> 44 #include <net/if_media.h> 45 46 #include <netinet/in.h> 47 #include <netinet/if_ether.h> 48 49 #include <net80211/ieee80211_var.h> 50 #include <net80211/ieee80211_radiotap.h> 51 52 #include <dev/usb/usb.h> 53 #include <dev/usb/usbdi.h> 54 #include <dev/usb/usbdi_util.h> 55 #include <dev/usb/usbdevs.h> 56 57 #include <dev/ic/r92creg.h> 58 #include <dev/ic/rtwnvar.h> 59 60 /* Maximum number of output pipes is 3. */ 61 #define R92C_MAX_EPOUT 3 62 63 #define R92C_PUBQ_NPAGES 231 64 #define R92C_TXPKTBUF_COUNT 256 65 #define R92C_TX_PAGE_COUNT 248 66 #define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) 67 #define R88E_TXPKTBUF_COUNT 177 68 #define R88E_TX_PAGE_COUNT 169 69 #define R88E_TX_PAGE_BOUNDARY (R88E_TX_PAGE_COUNT + 1) 70 71 /* USB Requests. */ 72 #define R92C_REQ_REGS 0x05 73 74 /* 75 * Driver definitions. 76 */ 77 #define URTWN_RX_LIST_COUNT 1 78 #define URTWN_TX_LIST_COUNT 8 79 #define URTWN_HOST_CMD_RING_COUNT 32 80 81 #define URTWN_RXBUFSZ (16 * 1024) 82 #define URTWN_TXBUFSZ (sizeof(struct r92c_tx_desc_usb) + IEEE80211_MAX_LEN) 83 84 #define URTWN_RIDX_COUNT 28 85 86 #define URTWN_TX_TIMEOUT 5000 /* ms */ 87 88 #define URTWN_LED_LINK 0 89 #define URTWN_LED_DATA 1 90 91 struct urtwn_rx_radiotap_header { 92 struct ieee80211_radiotap_header wr_ihdr; 93 uint8_t wr_flags; 94 uint8_t wr_rate; 95 uint16_t wr_chan_freq; 96 uint16_t wr_chan_flags; 97 uint8_t wr_dbm_antsignal; 98 } __packed; 99 100 #define URTWN_RX_RADIOTAP_PRESENT \ 101 (1 << IEEE80211_RADIOTAP_FLAGS | \ 102 1 << IEEE80211_RADIOTAP_RATE | \ 103 1 << IEEE80211_RADIOTAP_CHANNEL | \ 104 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) 105 106 struct urtwn_tx_radiotap_header { 107 struct ieee80211_radiotap_header wt_ihdr; 108 uint8_t wt_flags; 109 uint16_t wt_chan_freq; 110 uint16_t wt_chan_flags; 111 } __packed; 112 113 #define URTWN_TX_RADIOTAP_PRESENT \ 114 (1 << IEEE80211_RADIOTAP_FLAGS | \ 115 1 << IEEE80211_RADIOTAP_CHANNEL) 116 117 struct urtwn_softc; 118 119 struct urtwn_rx_data { 120 struct urtwn_softc *sc; 121 struct usbd_xfer *xfer; 122 uint8_t *buf; 123 }; 124 125 struct urtwn_tx_data { 126 struct urtwn_softc *sc; 127 struct usbd_pipe *pipe; 128 struct usbd_xfer *xfer; 129 uint8_t *buf; 130 TAILQ_ENTRY(urtwn_tx_data) next; 131 }; 132 133 struct urtwn_host_cmd { 134 void (*cb)(struct urtwn_softc *, void *); 135 uint8_t data[256]; 136 }; 137 138 struct urtwn_cmd_newstate { 139 enum ieee80211_state state; 140 int arg; 141 }; 142 143 struct urtwn_cmd_key { 144 struct ieee80211_key key; 145 struct ieee80211_node *ni; 146 }; 147 148 struct urtwn_host_cmd_ring { 149 struct urtwn_host_cmd cmd[URTWN_HOST_CMD_RING_COUNT]; 150 int cur; 151 int next; 152 int queued; 153 }; 154 155 struct urtwn_softc { 156 struct device sc_dev; 157 struct rtwn_softc sc_sc; 158 159 struct usbd_device *sc_udev; 160 struct usbd_interface *sc_iface; 161 struct usb_task sc_task; 162 163 struct timeout scan_to; 164 struct timeout calib_to; 165 166 struct usbd_pipe *rx_pipe; 167 struct usbd_pipe *tx_pipe[R92C_MAX_EPOUT]; 168 int ac2idx[EDCA_NUM_AC]; 169 170 struct urtwn_host_cmd_ring cmdq; 171 struct urtwn_rx_data rx_data[URTWN_RX_LIST_COUNT]; 172 struct urtwn_tx_data tx_data[URTWN_TX_LIST_COUNT]; 173 TAILQ_HEAD(, urtwn_tx_data) tx_free_list; 174 175 #if NBPFILTER > 0 176 caddr_t sc_drvbpf; 177 178 union { 179 struct urtwn_rx_radiotap_header th; 180 uint8_t pad[64]; 181 } sc_rxtapu; 182 #define sc_rxtap sc_rxtapu.th 183 int sc_rxtap_len; 184 185 union { 186 struct urtwn_tx_radiotap_header th; 187 uint8_t pad[64]; 188 } sc_txtapu; 189 #define sc_txtap sc_txtapu.th 190 int sc_txtap_len; 191 #endif 192 }; 193 194 #ifdef URTWN_DEBUG 195 #define DPRINTF(x) do { if (urtwn_debug) printf x; } while (0) 196 #define DPRINTFN(n, x) do { if (urtwn_debug >= (n)) printf x; } while (0) 197 int urtwn_debug = 4; 198 #else 199 #define DPRINTF(x) 200 #define DPRINTFN(n, x) 201 #endif 202 203 static const struct usb_devno urtwn_devs[] = { 204 { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8188CU_1 }, 205 { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8188CU_2 }, 206 { USB_VENDOR_ABOCOM, USB_PRODUCT_ABOCOM_RTL8192CU }, 207 { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_RTL8192CU }, 208 { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_RTL8192CU_2 }, 209 { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_RTL8192CU_3 }, 210 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8188CE_1 }, 211 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8188CE_2 }, 212 { USB_VENDOR_AZUREWAVE, USB_PRODUCT_AZUREWAVE_RTL8188CU }, 213 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F7D2102 }, 214 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_F9L1004V1 }, 215 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8188CU }, 216 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8188CUS }, 217 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8192CU }, 218 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8192CU_1 }, 219 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8192CU_2 }, 220 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_1 }, 221 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_2 }, 222 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_3 }, 223 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_4 }, 224 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_5 }, 225 { USB_VENDOR_CHICONY, USB_PRODUCT_CHICONY_RTL8188CUS_6 }, 226 { USB_VENDOR_COMPARE, USB_PRODUCT_COMPARE_RTL8192CU }, 227 { USB_VENDOR_COREGA, USB_PRODUCT_COREGA_RTL8192CU }, 228 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DWA131B }, 229 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8188CU }, 230 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_1 }, 231 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_2 }, 232 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_3 }, 233 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8192CU_4 }, 234 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_EW7811UN }, 235 { USB_VENDOR_EDIMAX, USB_PRODUCT_EDIMAX_RTL8192CU }, 236 { USB_VENDOR_FEIXUN, USB_PRODUCT_FEIXUN_RTL8188CU }, 237 { USB_VENDOR_FEIXUN, USB_PRODUCT_FEIXUN_RTL8192CU }, 238 { USB_VENDOR_GUILLEMOT, USB_PRODUCT_GUILLEMOT_HWNUP150 }, 239 { USB_VENDOR_GUILLEMOT, USB_PRODUCT_GUILLEMOT_RTL8192CU }, 240 { USB_VENDOR_HAWKING, USB_PRODUCT_HAWKING_RTL8192CU }, 241 { USB_VENDOR_HAWKING, USB_PRODUCT_HAWKING_RTL8192CU_2 }, 242 { USB_VENDOR_HP3, USB_PRODUCT_HP3_RTL8188CU }, 243 { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_WNG150UM }, 244 { USB_VENDOR_IODATA, USB_PRODUCT_IODATA_RTL8192CU }, 245 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_N300MA }, 246 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNA1000M }, 247 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_WNA1000Mv2 }, 248 { USB_VENDOR_NETGEAR, USB_PRODUCT_NETGEAR_RTL8192CU }, 249 { USB_VENDOR_NETGEAR4, USB_PRODUCT_NETGEAR4_RTL8188CU }, 250 { USB_VENDOR_NETWEEN, USB_PRODUCT_NETWEEN_RTL8192CU }, 251 { USB_VENDOR_NOVATECH, USB_PRODUCT_NOVATECH_RTL8188CU }, 252 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_1 }, 253 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_2 }, 254 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_3 }, 255 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CU_4 }, 256 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8188CUS }, 257 { USB_VENDOR_PLANEX2, USB_PRODUCT_PLANEX2_RTL8192CU }, 258 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CE_0 }, 259 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CE_1 }, 260 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CTV }, 261 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_0 }, 262 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_1 }, 263 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_2 }, 264 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_3 }, 265 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_4 }, 266 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_5 }, 267 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CU_COMBO }, 268 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188CUS }, 269 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188RU }, 270 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188RU_2 }, 271 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188RU_3 }, 272 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8191CU }, 273 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8192CE }, 274 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8192CE_VAU }, 275 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8192CU }, 276 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_RTL8188CU }, 277 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_RTL8188CU_2 }, 278 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_RTL8192CU }, 279 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_RTL8192CU_2 }, 280 { USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_WLA2100V2 }, 281 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_RTL8192CU }, 282 { USB_VENDOR_TRENDNET, USB_PRODUCT_TRENDNET_RTL8188CU }, 283 { USB_VENDOR_TRENDNET, USB_PRODUCT_TRENDNET_RTL8192CU }, 284 { USB_VENDOR_ZYXEL, USB_PRODUCT_ZYXEL_RTL8192CU }, 285 /* URTWN_RTL8188E */ 286 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DWA123D1 }, 287 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_DWA125D1 }, 288 { USB_VENDOR_ELECOM, USB_PRODUCT_ELECOM_WDC150SU2M }, 289 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188ETV }, 290 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8188EU } 291 }; 292 293 int urtwn_match(struct device *, void *, void *); 294 void urtwn_attach(struct device *, struct device *, void *); 295 int urtwn_detach(struct device *, int); 296 int urtwn_open_pipes(struct urtwn_softc *); 297 void urtwn_close_pipes(struct urtwn_softc *); 298 int urtwn_alloc_rx_list(struct urtwn_softc *); 299 void urtwn_free_rx_list(struct urtwn_softc *); 300 int urtwn_alloc_tx_list(struct urtwn_softc *); 301 void urtwn_free_tx_list(struct urtwn_softc *); 302 void urtwn_task(void *); 303 void urtwn_do_async(struct urtwn_softc *, 304 void (*)(struct urtwn_softc *, void *), void *, int); 305 void urtwn_wait_async(void *); 306 int urtwn_write_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 307 int); 308 void urtwn_write_1(void *, uint16_t, uint8_t); 309 void urtwn_write_2(void *, uint16_t, uint16_t); 310 void urtwn_write_4(void *, uint16_t, uint32_t); 311 int urtwn_read_region_1(struct urtwn_softc *, uint16_t, uint8_t *, 312 int); 313 uint8_t urtwn_read_1(void *, uint16_t); 314 uint16_t urtwn_read_2(void *, uint16_t); 315 uint32_t urtwn_read_4(void *, uint16_t); 316 int urtwn_llt_write(struct urtwn_softc *, uint32_t, uint32_t); 317 void urtwn_calib_to(void *); 318 void urtwn_calib_cb(struct urtwn_softc *, void *); 319 void urtwn_scan_to(void *); 320 void urtwn_next_scan(void *); 321 void urtwn_cancel_scan(void *); 322 int urtwn_newstate(struct ieee80211com *, enum ieee80211_state, 323 int); 324 void urtwn_newstate_cb(struct urtwn_softc *, void *); 325 void urtwn_updateedca(struct ieee80211com *); 326 void urtwn_updateedca_cb(struct urtwn_softc *, void *); 327 int urtwn_set_key(struct ieee80211com *, struct ieee80211_node *, 328 struct ieee80211_key *); 329 void urtwn_set_key_cb(struct urtwn_softc *, void *); 330 void urtwn_delete_key(struct ieee80211com *, 331 struct ieee80211_node *, struct ieee80211_key *); 332 void urtwn_delete_key_cb(struct urtwn_softc *, void *); 333 void urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int); 334 void urtwn_rxeof(struct usbd_xfer *, void *, 335 usbd_status); 336 void urtwn_txeof(struct usbd_xfer *, void *, 337 usbd_status); 338 int urtwn_tx(void *, struct mbuf *, struct ieee80211_node *); 339 int urtwn_ioctl(struct ifnet *, u_long, caddr_t); 340 int urtwn_power_on(void *); 341 int urtwn_alloc_buffers(void *); 342 int urtwn_r92c_power_on(struct urtwn_softc *); 343 int urtwn_r88e_power_on(struct urtwn_softc *); 344 int urtwn_llt_init(struct urtwn_softc *); 345 int urtwn_fw_loadpage(void *, int, uint8_t *, int); 346 int urtwn_load_firmware(void *, u_char **, size_t *); 347 int urtwn_dma_init(void *); 348 int urtwn_r92c_dma_init(struct urtwn_softc *); 349 int urtwn_r88e_dma_init(struct urtwn_softc *); 350 void urtwn_mac_init(void *); 351 void urtwn_bb_init(void *); 352 int urtwn_init(void *); 353 void urtwn_stop(void *); 354 int urtwn_is_oactive(void *); 355 void urtwn_next_calib(void *); 356 void urtwn_cancel_calib(void *); 357 358 /* Aliases. */ 359 #define urtwn_bb_write urtwn_write_4 360 #define urtwn_bb_read urtwn_read_4 361 362 struct cfdriver urtwn_cd = { 363 NULL, "urtwn", DV_IFNET 364 }; 365 366 const struct cfattach urtwn_ca = { 367 sizeof(struct urtwn_softc), urtwn_match, urtwn_attach, urtwn_detach 368 }; 369 370 int 371 urtwn_match(struct device *parent, void *match, void *aux) 372 { 373 struct usb_attach_arg *uaa = aux; 374 375 if (uaa->iface == NULL || uaa->configno != 1) 376 return (UMATCH_NONE); 377 378 return ((usb_lookup(urtwn_devs, uaa->vendor, uaa->product) != NULL) ? 379 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 380 } 381 382 void 383 urtwn_attach(struct device *parent, struct device *self, void *aux) 384 { 385 struct urtwn_softc *sc = (struct urtwn_softc *)self; 386 struct usb_attach_arg *uaa = aux; 387 struct ifnet *ifp; 388 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 389 uint32_t chip_type; 390 391 sc->sc_udev = uaa->device; 392 sc->sc_iface = uaa->iface; 393 394 usb_init_task(&sc->sc_task, urtwn_task, sc, USB_TASK_TYPE_GENERIC); 395 timeout_set(&sc->scan_to, urtwn_scan_to, sc); 396 timeout_set(&sc->calib_to, urtwn_calib_to, sc); 397 if (urtwn_open_pipes(sc) != 0) 398 return; 399 400 chip_type = RTWN_CHIP_USB; 401 if (uaa->product == USB_PRODUCT_DLINK_DWA123D1 || 402 uaa->product == USB_PRODUCT_DLINK_DWA125D1 || 403 uaa->product == USB_PRODUCT_ELECOM_WDC150SU2M || 404 uaa->product == USB_PRODUCT_REALTEK_RTL8188EU || 405 uaa->product == USB_PRODUCT_REALTEK_RTL8188ETV) 406 chip_type |= RTWN_CHIP_88E; 407 else 408 chip_type |= (RTWN_CHIP_92C | RTWN_CHIP_88C); 409 410 /* Attach the bus-agnostic driver. */ 411 sc->sc_sc.sc_ops.cookie = sc; 412 sc->sc_sc.sc_ops.write_1 = urtwn_write_1; 413 sc->sc_sc.sc_ops.write_2 = urtwn_write_2; 414 sc->sc_sc.sc_ops.write_4 = urtwn_write_4; 415 sc->sc_sc.sc_ops.read_1 = urtwn_read_1; 416 sc->sc_sc.sc_ops.read_2 = urtwn_read_2; 417 sc->sc_sc.sc_ops.read_4 = urtwn_read_4; 418 sc->sc_sc.sc_ops.tx = urtwn_tx; 419 sc->sc_sc.sc_ops.power_on = urtwn_power_on; 420 sc->sc_sc.sc_ops.dma_init = urtwn_dma_init; 421 sc->sc_sc.sc_ops.fw_loadpage = urtwn_fw_loadpage; 422 sc->sc_sc.sc_ops.load_firmware = urtwn_load_firmware; 423 sc->sc_sc.sc_ops.mac_init = urtwn_mac_init; 424 sc->sc_sc.sc_ops.bb_init = urtwn_bb_init; 425 sc->sc_sc.sc_ops.alloc_buffers = urtwn_alloc_buffers; 426 sc->sc_sc.sc_ops.init = urtwn_init; 427 sc->sc_sc.sc_ops.stop = urtwn_stop; 428 sc->sc_sc.sc_ops.is_oactive = urtwn_is_oactive; 429 sc->sc_sc.sc_ops.next_calib = urtwn_next_calib; 430 sc->sc_sc.sc_ops.cancel_calib = urtwn_cancel_calib; 431 sc->sc_sc.sc_ops.next_scan = urtwn_next_scan; 432 sc->sc_sc.sc_ops.cancel_scan = urtwn_cancel_scan; 433 sc->sc_sc.sc_ops.wait_async = urtwn_wait_async; 434 if (rtwn_attach(&sc->sc_dev, &sc->sc_sc, chip_type) != 0) { 435 urtwn_close_pipes(sc); 436 return; 437 } 438 439 /* ifp is now valid */ 440 ifp = &sc->sc_sc.sc_ic.ic_if; 441 ifp->if_ioctl = urtwn_ioctl; 442 443 ic->ic_updateedca = urtwn_updateedca; 444 #ifdef notyet 445 ic->ic_set_key = urtwn_set_key; 446 ic->ic_delete_key = urtwn_delete_key; 447 #endif 448 /* Override state transition machine. */ 449 ic->ic_newstate = urtwn_newstate; 450 451 #if NBPFILTER > 0 452 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 453 sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 454 455 sc->sc_rxtap_len = sizeof(sc->sc_rxtapu); 456 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 457 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTWN_RX_RADIOTAP_PRESENT); 458 459 sc->sc_txtap_len = sizeof(sc->sc_txtapu); 460 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 461 sc->sc_txtap.wt_ihdr.it_present = htole32(URTWN_TX_RADIOTAP_PRESENT); 462 #endif 463 } 464 465 int 466 urtwn_detach(struct device *self, int flags) 467 { 468 struct urtwn_softc *sc = (struct urtwn_softc *)self; 469 int s; 470 471 s = splusb(); 472 473 if (timeout_initialized(&sc->scan_to)) 474 timeout_del(&sc->scan_to); 475 if (timeout_initialized(&sc->calib_to)) 476 timeout_del(&sc->calib_to); 477 478 /* Wait for all async commands to complete. */ 479 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 480 481 usbd_ref_wait(sc->sc_udev); 482 483 rtwn_detach(&sc->sc_sc, flags); 484 485 /* Abort and close Tx/Rx pipes. */ 486 urtwn_close_pipes(sc); 487 488 /* Free Tx/Rx buffers. */ 489 urtwn_free_tx_list(sc); 490 urtwn_free_rx_list(sc); 491 splx(s); 492 493 return (0); 494 } 495 496 int 497 urtwn_open_pipes(struct urtwn_softc *sc) 498 { 499 /* Bulk-out endpoints addresses (from highest to lowest prio). */ 500 const uint8_t epaddr[] = { 0x02, 0x03, 0x05 }; 501 usb_interface_descriptor_t *id; 502 usb_endpoint_descriptor_t *ed; 503 int i, ntx = 0, error; 504 505 /* Determine the number of bulk-out pipes. */ 506 id = usbd_get_interface_descriptor(sc->sc_iface); 507 for (i = 0; i < id->bNumEndpoints; i++) { 508 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 509 if (ed != NULL && 510 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK && 511 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) 512 ntx++; 513 } 514 DPRINTF(("found %d bulk-out pipes\n", ntx)); 515 if (ntx == 0 || ntx > R92C_MAX_EPOUT) { 516 printf("%s: %d: invalid number of Tx bulk pipes\n", 517 sc->sc_dev.dv_xname, ntx); 518 return (EIO); 519 } 520 521 /* Open bulk-in pipe at address 0x81. */ 522 error = usbd_open_pipe(sc->sc_iface, 0x81, 0, &sc->rx_pipe); 523 if (error != 0) { 524 printf("%s: could not open Rx bulk pipe\n", 525 sc->sc_dev.dv_xname); 526 goto fail; 527 } 528 529 /* Open bulk-out pipes (up to 3). */ 530 for (i = 0; i < ntx; i++) { 531 error = usbd_open_pipe(sc->sc_iface, epaddr[i], 0, 532 &sc->tx_pipe[i]); 533 if (error != 0) { 534 printf("%s: could not open Tx bulk pipe 0x%02x\n", 535 sc->sc_dev.dv_xname, epaddr[i]); 536 goto fail; 537 } 538 } 539 540 /* Map 802.11 access categories to USB pipes. */ 541 sc->ac2idx[EDCA_AC_BK] = 542 sc->ac2idx[EDCA_AC_BE] = (ntx == 3) ? 2 : ((ntx == 2) ? 1 : 0); 543 sc->ac2idx[EDCA_AC_VI] = (ntx == 3) ? 1 : 0; 544 sc->ac2idx[EDCA_AC_VO] = 0; /* Always use highest prio. */ 545 546 if (error != 0) 547 fail: urtwn_close_pipes(sc); 548 return (error); 549 } 550 551 void 552 urtwn_close_pipes(struct urtwn_softc *sc) 553 { 554 int i; 555 556 /* Close Rx pipe. */ 557 if (sc->rx_pipe != NULL) { 558 usbd_abort_pipe(sc->rx_pipe); 559 usbd_close_pipe(sc->rx_pipe); 560 } 561 /* Close Tx pipes. */ 562 for (i = 0; i < R92C_MAX_EPOUT; i++) { 563 if (sc->tx_pipe[i] == NULL) 564 continue; 565 usbd_abort_pipe(sc->tx_pipe[i]); 566 usbd_close_pipe(sc->tx_pipe[i]); 567 } 568 } 569 570 int 571 urtwn_alloc_rx_list(struct urtwn_softc *sc) 572 { 573 struct urtwn_rx_data *data; 574 int i, error = 0; 575 576 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 577 data = &sc->rx_data[i]; 578 579 data->sc = sc; /* Backpointer for callbacks. */ 580 581 data->xfer = usbd_alloc_xfer(sc->sc_udev); 582 if (data->xfer == NULL) { 583 printf("%s: could not allocate xfer\n", 584 sc->sc_dev.dv_xname); 585 error = ENOMEM; 586 break; 587 } 588 data->buf = usbd_alloc_buffer(data->xfer, URTWN_RXBUFSZ); 589 if (data->buf == NULL) { 590 printf("%s: could not allocate xfer buffer\n", 591 sc->sc_dev.dv_xname); 592 error = ENOMEM; 593 break; 594 } 595 } 596 if (error != 0) 597 urtwn_free_rx_list(sc); 598 return (error); 599 } 600 601 void 602 urtwn_free_rx_list(struct urtwn_softc *sc) 603 { 604 int i; 605 606 /* NB: Caller must abort pipe first. */ 607 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 608 if (sc->rx_data[i].xfer != NULL) 609 usbd_free_xfer(sc->rx_data[i].xfer); 610 sc->rx_data[i].xfer = NULL; 611 } 612 } 613 614 int 615 urtwn_alloc_tx_list(struct urtwn_softc *sc) 616 { 617 struct urtwn_tx_data *data; 618 int i, error = 0; 619 620 TAILQ_INIT(&sc->tx_free_list); 621 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 622 data = &sc->tx_data[i]; 623 624 data->sc = sc; /* Backpointer for callbacks. */ 625 626 data->xfer = usbd_alloc_xfer(sc->sc_udev); 627 if (data->xfer == NULL) { 628 printf("%s: could not allocate xfer\n", 629 sc->sc_dev.dv_xname); 630 error = ENOMEM; 631 break; 632 } 633 data->buf = usbd_alloc_buffer(data->xfer, URTWN_TXBUFSZ); 634 if (data->buf == NULL) { 635 printf("%s: could not allocate xfer buffer\n", 636 sc->sc_dev.dv_xname); 637 error = ENOMEM; 638 break; 639 } 640 /* Append this Tx buffer to our free list. */ 641 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 642 } 643 if (error != 0) 644 urtwn_free_tx_list(sc); 645 return (error); 646 } 647 648 void 649 urtwn_free_tx_list(struct urtwn_softc *sc) 650 { 651 int i; 652 653 /* NB: Caller must abort pipe first. */ 654 for (i = 0; i < URTWN_TX_LIST_COUNT; i++) { 655 if (sc->tx_data[i].xfer != NULL) 656 usbd_free_xfer(sc->tx_data[i].xfer); 657 sc->tx_data[i].xfer = NULL; 658 } 659 } 660 661 void 662 urtwn_task(void *arg) 663 { 664 struct urtwn_softc *sc = arg; 665 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 666 struct urtwn_host_cmd *cmd; 667 int s; 668 669 /* Process host commands. */ 670 s = splusb(); 671 while (ring->next != ring->cur) { 672 cmd = &ring->cmd[ring->next]; 673 splx(s); 674 /* Invoke callback. */ 675 cmd->cb(sc, cmd->data); 676 s = splusb(); 677 ring->queued--; 678 ring->next = (ring->next + 1) % URTWN_HOST_CMD_RING_COUNT; 679 } 680 splx(s); 681 } 682 683 void 684 urtwn_do_async(struct urtwn_softc *sc, 685 void (*cb)(struct urtwn_softc *, void *), void *arg, int len) 686 { 687 struct urtwn_host_cmd_ring *ring = &sc->cmdq; 688 struct urtwn_host_cmd *cmd; 689 int s; 690 691 s = splusb(); 692 cmd = &ring->cmd[ring->cur]; 693 cmd->cb = cb; 694 KASSERT(len <= sizeof(cmd->data)); 695 memcpy(cmd->data, arg, len); 696 ring->cur = (ring->cur + 1) % URTWN_HOST_CMD_RING_COUNT; 697 698 /* If there is no pending command already, schedule a task. */ 699 if (++ring->queued == 1) 700 usb_add_task(sc->sc_udev, &sc->sc_task); 701 splx(s); 702 } 703 704 void 705 urtwn_wait_async(void *cookie) 706 { 707 struct urtwn_softc *sc = cookie; 708 int s; 709 710 s = splusb(); 711 /* Wait for all queued asynchronous commands to complete. */ 712 usb_wait_task(sc->sc_udev, &sc->sc_task); 713 splx(s); 714 } 715 716 int 717 urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 718 int len) 719 { 720 usb_device_request_t req; 721 722 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 723 req.bRequest = R92C_REQ_REGS; 724 USETW(req.wValue, addr); 725 USETW(req.wIndex, 0); 726 USETW(req.wLength, len); 727 return (usbd_do_request(sc->sc_udev, &req, buf)); 728 } 729 730 void 731 urtwn_write_1(void *cookie, uint16_t addr, uint8_t val) 732 { 733 struct urtwn_softc *sc = cookie; 734 735 urtwn_write_region_1(sc, addr, &val, 1); 736 } 737 738 void 739 urtwn_write_2(void *cookie, uint16_t addr, uint16_t val) 740 { 741 struct urtwn_softc *sc = cookie; 742 743 val = htole16(val); 744 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 745 } 746 747 void 748 urtwn_write_4(void *cookie, uint16_t addr, uint32_t val) 749 { 750 struct urtwn_softc *sc = cookie; 751 752 val = htole32(val); 753 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 754 } 755 756 int 757 urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 758 int len) 759 { 760 usb_device_request_t req; 761 762 req.bmRequestType = UT_READ_VENDOR_DEVICE; 763 req.bRequest = R92C_REQ_REGS; 764 USETW(req.wValue, addr); 765 USETW(req.wIndex, 0); 766 USETW(req.wLength, len); 767 return (usbd_do_request(sc->sc_udev, &req, buf)); 768 } 769 770 uint8_t 771 urtwn_read_1(void *cookie, uint16_t addr) 772 { 773 struct urtwn_softc *sc = cookie; 774 uint8_t val; 775 776 if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 777 return (0xff); 778 return (val); 779 } 780 781 uint16_t 782 urtwn_read_2(void *cookie, uint16_t addr) 783 { 784 struct urtwn_softc *sc = cookie; 785 uint16_t val; 786 787 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 788 return (0xffff); 789 return (letoh16(val)); 790 } 791 792 uint32_t 793 urtwn_read_4(void *cookie, uint16_t addr) 794 { 795 struct urtwn_softc *sc = cookie; 796 uint32_t val; 797 798 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 799 return (0xffffffff); 800 return (letoh32(val)); 801 } 802 803 int 804 urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 805 { 806 int ntries; 807 808 urtwn_write_4(sc, R92C_LLT_INIT, 809 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 810 SM(R92C_LLT_INIT_ADDR, addr) | 811 SM(R92C_LLT_INIT_DATA, data)); 812 /* Wait for write operation to complete. */ 813 for (ntries = 0; ntries < 20; ntries++) { 814 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 815 R92C_LLT_INIT_OP_NO_ACTIVE) 816 return (0); 817 DELAY(5); 818 } 819 return (ETIMEDOUT); 820 } 821 822 void 823 urtwn_calib_to(void *arg) 824 { 825 struct urtwn_softc *sc = arg; 826 827 if (usbd_is_dying(sc->sc_udev)) 828 return; 829 830 usbd_ref_incr(sc->sc_udev); 831 832 /* Do it in a process context. */ 833 urtwn_do_async(sc, urtwn_calib_cb, NULL, 0); 834 835 usbd_ref_decr(sc->sc_udev); 836 } 837 838 /* ARGSUSED */ 839 void 840 urtwn_calib_cb(struct urtwn_softc *sc, void *arg) 841 { 842 rtwn_calib(&sc->sc_sc); 843 } 844 845 void 846 urtwn_next_calib(void *cookie) 847 { 848 struct urtwn_softc *sc = cookie; 849 850 if (!usbd_is_dying(sc->sc_udev)) 851 timeout_add_sec(&sc->calib_to, 2); 852 } 853 854 void 855 urtwn_cancel_calib(void *cookie) 856 { 857 struct urtwn_softc *sc = cookie; 858 859 if (timeout_initialized(&sc->calib_to)) 860 timeout_del(&sc->calib_to); 861 } 862 863 void 864 urtwn_scan_to(void *arg) 865 { 866 struct urtwn_softc *sc = arg; 867 868 if (usbd_is_dying(sc->sc_udev)) 869 return; 870 871 usbd_ref_incr(sc->sc_udev); 872 rtwn_next_scan(&sc->sc_sc); 873 usbd_ref_decr(sc->sc_udev); 874 } 875 876 void 877 urtwn_next_scan(void *arg) 878 { 879 struct urtwn_softc *sc = arg; 880 881 if (!usbd_is_dying(sc->sc_udev)) 882 timeout_add_msec(&sc->scan_to, 200); 883 } 884 885 void 886 urtwn_cancel_scan(void *cookie) 887 { 888 struct urtwn_softc *sc = cookie; 889 890 if (timeout_initialized(&sc->scan_to)) 891 timeout_del(&sc->scan_to); 892 } 893 894 int 895 urtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 896 { 897 struct rtwn_softc *sc_sc = ic->ic_softc; 898 struct device *self = sc_sc->sc_pdev; 899 struct urtwn_softc *sc = (struct urtwn_softc *)self; 900 struct urtwn_cmd_newstate cmd; 901 902 /* Do it in a process context. */ 903 cmd.state = nstate; 904 cmd.arg = arg; 905 urtwn_do_async(sc, urtwn_newstate_cb, &cmd, sizeof(cmd)); 906 return (0); 907 } 908 909 void 910 urtwn_newstate_cb(struct urtwn_softc *sc, void *arg) 911 { 912 struct urtwn_cmd_newstate *cmd = arg; 913 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 914 915 rtwn_newstate(ic, cmd->state, cmd->arg); 916 } 917 918 void 919 urtwn_updateedca(struct ieee80211com *ic) 920 { 921 struct rtwn_softc *sc_sc = ic->ic_softc; 922 struct device *self = sc_sc->sc_pdev; 923 struct urtwn_softc *sc = (struct urtwn_softc *)self; 924 925 /* Do it in a process context. */ 926 urtwn_do_async(sc, urtwn_updateedca_cb, NULL, 0); 927 } 928 929 /* ARGSUSED */ 930 void 931 urtwn_updateedca_cb(struct urtwn_softc *sc, void *arg) 932 { 933 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 934 935 rtwn_updateedca(ic); 936 } 937 938 int 939 urtwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 940 struct ieee80211_key *k) 941 { 942 struct rtwn_softc *sc_sc = ic->ic_softc; 943 struct device *self = sc_sc->sc_pdev; 944 struct urtwn_softc *sc = (struct urtwn_softc *)self; 945 struct urtwn_cmd_key cmd; 946 947 /* Defer setting of WEP keys until interface is brought up. */ 948 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 949 (IFF_UP | IFF_RUNNING)) 950 return (0); 951 952 /* Do it in a process context. */ 953 cmd.key = *k; 954 cmd.ni = ni; 955 urtwn_do_async(sc, urtwn_set_key_cb, &cmd, sizeof(cmd)); 956 return (0); 957 } 958 959 void 960 urtwn_set_key_cb(struct urtwn_softc *sc, void *arg) 961 { 962 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 963 struct urtwn_cmd_key *cmd = arg; 964 965 rtwn_set_key(ic, cmd->ni, &cmd->key); 966 } 967 968 void 969 urtwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 970 struct ieee80211_key *k) 971 { 972 struct rtwn_softc *sc_sc = ic->ic_softc; 973 struct device *self = sc_sc->sc_pdev; 974 struct urtwn_softc *sc = (struct urtwn_softc *)self; 975 struct urtwn_cmd_key cmd; 976 977 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 978 ic->ic_state != IEEE80211_S_RUN) 979 return; /* Nothing to do. */ 980 981 /* Do it in a process context. */ 982 cmd.key = *k; 983 cmd.ni = ni; 984 urtwn_do_async(sc, urtwn_delete_key_cb, &cmd, sizeof(cmd)); 985 } 986 987 void 988 urtwn_delete_key_cb(struct urtwn_softc *sc, void *arg) 989 { 990 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 991 struct urtwn_cmd_key *cmd = arg; 992 993 rtwn_delete_key(ic, cmd->ni, &cmd->key); 994 } 995 996 void 997 urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen) 998 { 999 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1000 struct ifnet *ifp = &ic->ic_if; 1001 struct ieee80211_rxinfo rxi; 1002 struct ieee80211_frame *wh; 1003 struct ieee80211_node *ni; 1004 struct r92c_rx_desc_usb *rxd; 1005 uint32_t rxdw0, rxdw3; 1006 struct mbuf *m; 1007 uint8_t rate; 1008 int8_t rssi = 0; 1009 int s, infosz; 1010 1011 rxd = (struct r92c_rx_desc_usb *)buf; 1012 rxdw0 = letoh32(rxd->rxdw0); 1013 rxdw3 = letoh32(rxd->rxdw3); 1014 1015 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1016 /* 1017 * This should not happen since we setup our Rx filter 1018 * to not receive these frames. 1019 */ 1020 ifp->if_ierrors++; 1021 return; 1022 } 1023 if (__predict_false(pktlen < sizeof(*wh) || pktlen > MCLBYTES)) { 1024 ifp->if_ierrors++; 1025 return; 1026 } 1027 1028 rate = MS(rxdw3, R92C_RXDW3_RATE); 1029 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1030 1031 /* Get RSSI from PHY status descriptor if present. */ 1032 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1033 rssi = rtwn_get_rssi(&sc->sc_sc, rate, &rxd[1]); 1034 /* Update our average RSSI. */ 1035 rtwn_update_avgrssi(&sc->sc_sc, rate, rssi); 1036 } 1037 1038 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d rssi=%d\n", 1039 pktlen, rate, infosz, rssi)); 1040 1041 MGETHDR(m, M_DONTWAIT, MT_DATA); 1042 if (__predict_false(m == NULL)) { 1043 ifp->if_ierrors++; 1044 return; 1045 } 1046 if (pktlen > MHLEN) { 1047 MCLGET(m, M_DONTWAIT); 1048 if (__predict_false(!(m->m_flags & M_EXT))) { 1049 ifp->if_ierrors++; 1050 m_freem(m); 1051 return; 1052 } 1053 } 1054 /* Finalize mbuf. */ 1055 wh = (struct ieee80211_frame *)((uint8_t *)&rxd[1] + infosz); 1056 memcpy(mtod(m, uint8_t *), wh, pktlen); 1057 m->m_pkthdr.len = m->m_len = pktlen; 1058 1059 s = splnet(); 1060 #if NBPFILTER > 0 1061 if (__predict_false(sc->sc_drvbpf != NULL)) { 1062 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1063 struct mbuf mb; 1064 1065 tap->wr_flags = 0; 1066 /* Map HW rate index to 802.11 rate. */ 1067 tap->wr_flags = 2; 1068 if (!(rxdw3 & R92C_RXDW3_HT)) { 1069 switch (rate) { 1070 /* CCK. */ 1071 case 0: tap->wr_rate = 2; break; 1072 case 1: tap->wr_rate = 4; break; 1073 case 2: tap->wr_rate = 11; break; 1074 case 3: tap->wr_rate = 22; break; 1075 /* OFDM. */ 1076 case 4: tap->wr_rate = 12; break; 1077 case 5: tap->wr_rate = 18; break; 1078 case 6: tap->wr_rate = 24; break; 1079 case 7: tap->wr_rate = 36; break; 1080 case 8: tap->wr_rate = 48; break; 1081 case 9: tap->wr_rate = 72; break; 1082 case 10: tap->wr_rate = 96; break; 1083 case 11: tap->wr_rate = 108; break; 1084 } 1085 } else if (rate >= 12) { /* MCS0~15. */ 1086 /* Bit 7 set means HT MCS instead of rate. */ 1087 tap->wr_rate = 0x80 | (rate - 12); 1088 } 1089 tap->wr_dbm_antsignal = rssi; 1090 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 1091 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 1092 1093 mb.m_data = (caddr_t)tap; 1094 mb.m_len = sc->sc_rxtap_len; 1095 mb.m_next = m; 1096 mb.m_nextpkt = NULL; 1097 mb.m_type = 0; 1098 mb.m_flags = 0; 1099 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 1100 } 1101 #endif 1102 1103 ni = ieee80211_find_rxnode(ic, wh); 1104 rxi.rxi_flags = 0; 1105 rxi.rxi_rssi = rssi; 1106 rxi.rxi_tstamp = 0; /* Unused. */ 1107 ieee80211_input(ifp, m, ni, &rxi); 1108 /* Node is no longer needed. */ 1109 ieee80211_release_node(ic, ni); 1110 splx(s); 1111 } 1112 1113 void 1114 urtwn_rxeof(struct usbd_xfer *xfer, void *priv, 1115 usbd_status status) 1116 { 1117 struct urtwn_rx_data *data = priv; 1118 struct urtwn_softc *sc = data->sc; 1119 struct r92c_rx_desc_usb *rxd; 1120 uint32_t rxdw0; 1121 uint8_t *buf; 1122 int len, totlen, pktlen, infosz, npkts, error; 1123 1124 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1125 DPRINTF(("RX status=%d\n", status)); 1126 if (status == USBD_STALLED) 1127 usbd_clear_endpoint_stall_async(sc->rx_pipe); 1128 if (status != USBD_CANCELLED) 1129 goto resubmit; 1130 return; 1131 } 1132 usbd_get_xfer_status(xfer, NULL, NULL, &len, NULL); 1133 1134 if (__predict_false(len < sizeof(*rxd))) { 1135 DPRINTF(("xfer too short %d\n", len)); 1136 goto resubmit; 1137 } 1138 buf = data->buf; 1139 1140 /* Get the number of encapsulated frames. */ 1141 rxd = (struct r92c_rx_desc_usb *)buf; 1142 npkts = MS(letoh32(rxd->rxdw2), R92C_RXDW2_PKTCNT); 1143 DPRINTFN(4, ("Rx %d frames in one chunk\n", npkts)); 1144 1145 /* Process all of them. */ 1146 while (npkts-- > 0) { 1147 if (__predict_false(len < sizeof(*rxd))) 1148 break; 1149 rxd = (struct r92c_rx_desc_usb *)buf; 1150 rxdw0 = letoh32(rxd->rxdw0); 1151 1152 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1153 if (__predict_false(pktlen == 0)) 1154 break; 1155 1156 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1157 1158 /* Make sure everything fits in xfer. */ 1159 totlen = sizeof(*rxd) + infosz + pktlen; 1160 if (__predict_false(totlen > len)) 1161 break; 1162 1163 /* Process 802.11 frame. */ 1164 urtwn_rx_frame(sc, buf, pktlen); 1165 1166 /* Next chunk is 128-byte aligned. */ 1167 totlen = (totlen + 127) & ~127; 1168 buf += totlen; 1169 len -= totlen; 1170 } 1171 1172 resubmit: 1173 /* Setup a new transfer. */ 1174 usbd_setup_xfer(xfer, sc->rx_pipe, data, data->buf, URTWN_RXBUFSZ, 1175 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, urtwn_rxeof); 1176 error = usbd_transfer(data->xfer); 1177 if (error != 0 && error != USBD_IN_PROGRESS) 1178 DPRINTF(("could not set up new transfer: %d\n", error)); 1179 } 1180 1181 void 1182 urtwn_txeof(struct usbd_xfer *xfer, void *priv, 1183 usbd_status status) 1184 { 1185 struct urtwn_tx_data *data = priv; 1186 struct urtwn_softc *sc = data->sc; 1187 struct ifnet *ifp = &sc->sc_sc.sc_ic.ic_if; 1188 int s; 1189 1190 s = splnet(); 1191 /* Put this Tx buffer back to our free list. */ 1192 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1193 1194 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 1195 DPRINTF(("TX status=%d\n", status)); 1196 if (status == USBD_STALLED) 1197 usbd_clear_endpoint_stall_async(data->pipe); 1198 ifp->if_oerrors++; 1199 splx(s); 1200 return; 1201 } 1202 sc->sc_sc.sc_tx_timer = 0; 1203 ifp->if_opackets++; 1204 1205 /* We just released a Tx buffer, notify Tx. */ 1206 if (ifq_is_oactive(&ifp->if_snd)) { 1207 ifq_clr_oactive(&ifp->if_snd); 1208 rtwn_start(ifp); 1209 } 1210 splx(s); 1211 } 1212 1213 int 1214 urtwn_tx(void *cookie, struct mbuf *m, struct ieee80211_node *ni) 1215 { 1216 struct urtwn_softc *sc = cookie; 1217 struct ieee80211com *ic = &sc->sc_sc.sc_ic; 1218 struct ieee80211_frame *wh; 1219 struct ieee80211_key *k = NULL; 1220 struct urtwn_tx_data *data; 1221 struct r92c_tx_desc_usb *txd; 1222 struct usbd_pipe *pipe; 1223 uint16_t qos, sum; 1224 uint8_t raid, type, tid, qid; 1225 int i, hasqos, xferlen, error; 1226 1227 wh = mtod(m, struct ieee80211_frame *); 1228 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1229 1230 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1231 k = ieee80211_get_txkey(ic, wh, ni); 1232 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 1233 return (ENOBUFS); 1234 wh = mtod(m, struct ieee80211_frame *); 1235 } 1236 1237 if ((hasqos = ieee80211_has_qos(wh))) { 1238 qos = ieee80211_get_qos(wh); 1239 tid = qos & IEEE80211_QOS_TID; 1240 qid = ieee80211_up_to_ac(ic, tid); 1241 } else if (type != IEEE80211_FC0_TYPE_DATA) { 1242 /* Use AC VO for management frames. */ 1243 qid = EDCA_AC_VO; 1244 } else 1245 qid = EDCA_AC_BE; 1246 1247 /* Get the USB pipe to use for this AC. */ 1248 pipe = sc->tx_pipe[sc->ac2idx[qid]]; 1249 1250 /* Grab a Tx buffer from our free list. */ 1251 data = TAILQ_FIRST(&sc->tx_free_list); 1252 TAILQ_REMOVE(&sc->tx_free_list, data, next); 1253 1254 /* Fill Tx descriptor. */ 1255 txd = (struct r92c_tx_desc_usb *)data->buf; 1256 memset(txd, 0, sizeof(*txd)); 1257 1258 txd->txdw0 |= htole32( 1259 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 1260 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1261 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1262 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1263 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1264 1265 #ifdef notyet 1266 if (k != NULL) { 1267 switch (k->k_cipher) { 1268 case IEEE80211_CIPHER_WEP40: 1269 case IEEE80211_CIPHER_WEP104: 1270 case IEEE80211_CIPHER_TKIP: 1271 cipher = R92C_TXDW1_CIPHER_RC4; 1272 break; 1273 case IEEE80211_CIPHER_CCMP: 1274 cipher = R92C_TXDW1_CIPHER_AES; 1275 break; 1276 default: 1277 cipher = R92C_TXDW1_CIPHER_NONE; 1278 } 1279 txd->txdw1 |= htole32(SM(R92C_TXDW1_CIPHER, cipher)); 1280 } 1281 #endif 1282 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1283 type == IEEE80211_FC0_TYPE_DATA) { 1284 if (ic->ic_curmode == IEEE80211_MODE_11B || 1285 (sc->sc_sc.sc_flags & RTWN_FLAG_FORCE_RAID_11B)) 1286 raid = R92C_RAID_11B; 1287 else 1288 raid = R92C_RAID_11BG; 1289 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1290 txd->txdw1 |= htole32( 1291 SM(R88E_TXDW1_MACID, R92C_MACID_BSS) | 1292 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1293 SM(R92C_TXDW1_RAID, raid)); 1294 txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1295 } else { 1296 txd->txdw1 |= htole32( 1297 SM(R92C_TXDW1_MACID, R92C_MACID_BSS) | 1298 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1299 SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1300 } 1301 1302 if (m->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold) { 1303 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1304 R92C_TXDW4_HWRTSEN); 1305 } else if (ic->ic_flags & IEEE80211_F_USEPROT) { 1306 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1307 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1308 R92C_TXDW4_HWRTSEN); 1309 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1310 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1311 R92C_TXDW4_HWRTSEN); 1312 } 1313 } 1314 /* Send RTS at OFDM24. */ 1315 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1316 txd->txdw5 |= htole32(0x0001ff00); 1317 /* Send data at OFDM54. */ 1318 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1319 1320 } else { 1321 txd->txdw1 |= htole32( 1322 SM(R92C_TXDW1_MACID, 0) | 1323 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1324 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1325 1326 /* Force CCK1. */ 1327 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1328 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1329 } 1330 /* Set sequence number (already little endian). */ 1331 txd->txdseq |= *(uint16_t *)wh->i_seq; 1332 1333 if (!hasqos) { 1334 /* Use HW sequence numbering for non-QoS frames. */ 1335 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1336 txd->txdseq |= htole16(0x8000); /* WTF? */ 1337 } else 1338 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1339 1340 /* Compute Tx descriptor checksum. */ 1341 sum = 0; 1342 for (i = 0; i < sizeof(*txd) / 2; i++) 1343 sum ^= ((uint16_t *)txd)[i]; 1344 txd->txdsum = sum; /* NB: already little endian. */ 1345 1346 #if NBPFILTER > 0 1347 if (__predict_false(sc->sc_drvbpf != NULL)) { 1348 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1349 struct mbuf mb; 1350 1351 tap->wt_flags = 0; 1352 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 1353 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 1354 1355 mb.m_data = (caddr_t)tap; 1356 mb.m_len = sc->sc_txtap_len; 1357 mb.m_next = m; 1358 mb.m_nextpkt = NULL; 1359 mb.m_type = 0; 1360 mb.m_flags = 0; 1361 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 1362 } 1363 #endif 1364 1365 xferlen = sizeof(*txd) + m->m_pkthdr.len; 1366 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)&txd[1]); 1367 m_freem(m); 1368 1369 data->pipe = pipe; 1370 usbd_setup_xfer(data->xfer, pipe, data, data->buf, xferlen, 1371 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTWN_TX_TIMEOUT, 1372 urtwn_txeof); 1373 error = usbd_transfer(data->xfer); 1374 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) { 1375 /* Put this Tx buffer back to our free list. */ 1376 TAILQ_INSERT_TAIL(&sc->tx_free_list, data, next); 1377 return (error); 1378 } 1379 ieee80211_release_node(ic, ni); 1380 return (0); 1381 } 1382 1383 int 1384 urtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1385 { 1386 struct rtwn_softc *sc_sc = ifp->if_softc; 1387 struct device *self = sc_sc->sc_pdev; 1388 struct urtwn_softc *sc = (struct urtwn_softc *)self; 1389 int error; 1390 1391 if (usbd_is_dying(sc->sc_udev)) 1392 return ENXIO; 1393 1394 usbd_ref_incr(sc->sc_udev); 1395 error = rtwn_ioctl(ifp, cmd, data); 1396 usbd_ref_decr(sc->sc_udev); 1397 1398 return (error); 1399 } 1400 1401 int 1402 urtwn_r92c_power_on(struct urtwn_softc *sc) 1403 { 1404 uint32_t reg; 1405 int ntries; 1406 1407 /* Wait for autoload done bit. */ 1408 for (ntries = 0; ntries < 1000; ntries++) { 1409 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 1410 break; 1411 DELAY(5); 1412 } 1413 if (ntries == 1000) { 1414 printf("%s: timeout waiting for chip autoload\n", 1415 sc->sc_dev.dv_xname); 1416 return (ETIMEDOUT); 1417 } 1418 1419 /* Unlock ISO/CLK/Power control register. */ 1420 urtwn_write_1(sc, R92C_RSV_CTRL, 0); 1421 /* Move SPS into PWM mode. */ 1422 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 1423 DELAY(100); 1424 1425 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 1426 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 1427 urtwn_write_1(sc, R92C_LDOV12D_CTRL, 1428 reg | R92C_LDOV12D_CTRL_LDV12_EN); 1429 DELAY(100); 1430 urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 1431 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 1432 ~R92C_SYS_ISO_CTRL_MD2PP); 1433 } 1434 1435 /* Auto enable WLAN. */ 1436 urtwn_write_2(sc, R92C_APS_FSMCO, 1437 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1438 for (ntries = 0; ntries < 1000; ntries++) { 1439 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1440 R92C_APS_FSMCO_APFM_ONMAC)) 1441 break; 1442 DELAY(5); 1443 } 1444 if (ntries == 1000) { 1445 printf("%s: timeout waiting for MAC auto ON\n", 1446 sc->sc_dev.dv_xname); 1447 return (ETIMEDOUT); 1448 } 1449 1450 /* Enable radio, GPIO and LED functions. */ 1451 urtwn_write_2(sc, R92C_APS_FSMCO, 1452 R92C_APS_FSMCO_AFSM_HSUS | 1453 R92C_APS_FSMCO_PDN_EN | 1454 R92C_APS_FSMCO_PFM_ALDN); 1455 /* Release RF digital isolation. */ 1456 urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1457 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 1458 1459 /* Initialize MAC. */ 1460 urtwn_write_1(sc, R92C_APSD_CTRL, 1461 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 1462 for (ntries = 0; ntries < 200; ntries++) { 1463 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 1464 R92C_APSD_CTRL_OFF_STATUS)) 1465 break; 1466 DELAY(5); 1467 } 1468 if (ntries == 200) { 1469 printf("%s: timeout waiting for MAC initialization\n", 1470 sc->sc_dev.dv_xname); 1471 return (ETIMEDOUT); 1472 } 1473 1474 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1475 reg = urtwn_read_2(sc, R92C_CR); 1476 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1477 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1478 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 1479 R92C_CR_ENSEC; 1480 urtwn_write_2(sc, R92C_CR, reg); 1481 1482 urtwn_write_1(sc, 0xfe10, 0x19); 1483 return (0); 1484 } 1485 1486 int 1487 urtwn_r88e_power_on(struct urtwn_softc *sc) 1488 { 1489 uint32_t reg; 1490 int ntries; 1491 1492 /* Wait for power ready bit. */ 1493 for (ntries = 0; ntries < 5000; ntries++) { 1494 if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 1495 break; 1496 DELAY(10); 1497 } 1498 if (ntries == 5000) { 1499 printf("%s: timeout waiting for chip power up\n", 1500 sc->sc_dev.dv_xname); 1501 return (ETIMEDOUT); 1502 } 1503 1504 /* Reset BB. */ 1505 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 1506 urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 1507 R92C_SYS_FUNC_EN_BB_GLB_RST)); 1508 1509 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 1510 urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 1511 1512 /* Disable HWPDN. */ 1513 urtwn_write_1(sc, 0x5, urtwn_read_1(sc, 0x5) & ~0x80); 1514 urtwn_write_2(sc, R92C_APS_FSMCO, 1515 urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 1516 1517 /* Disable WL suspend. */ 1518 urtwn_write_2(sc, R92C_APS_FSMCO, 1519 urtwn_read_2(sc, R92C_APS_FSMCO) & 1520 ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 1521 1522 urtwn_write_2(sc, R92C_APS_FSMCO, 1523 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1524 for (ntries = 0; ntries < 5000; ntries++) { 1525 if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 1526 R92C_APS_FSMCO_APFM_ONMAC)) 1527 break; 1528 DELAY(10); 1529 } 1530 if (ntries == 5000) 1531 return (ETIMEDOUT); 1532 1533 /* Enable LDO normal mode. */ 1534 urtwn_write_1(sc, R92C_LPLDO_CTRL, 1535 urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 1536 1537 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 1538 urtwn_write_2(sc, R92C_CR, 0); 1539 reg = urtwn_read_2(sc, R92C_CR); 1540 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 1541 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 1542 R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 1543 urtwn_write_2(sc, R92C_CR, reg); 1544 1545 return (0); 1546 } 1547 1548 int 1549 urtwn_llt_init(struct urtwn_softc *sc) 1550 { 1551 int i, error, page_count, pktbuf_count; 1552 1553 page_count = (sc->sc_sc.chip & RTWN_CHIP_88E) ? 1554 R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 1555 pktbuf_count = (sc->sc_sc.chip & RTWN_CHIP_88E) ? 1556 R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 1557 1558 /* Reserve pages [0; page_count]. */ 1559 for (i = 0; i < page_count; i++) { 1560 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1561 return (error); 1562 } 1563 /* NB: 0xff indicates end-of-list. */ 1564 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 1565 return (error); 1566 /* 1567 * Use pages [page_count + 1; pktbuf_count - 1] 1568 * as ring buffer. 1569 */ 1570 for (++i; i < pktbuf_count - 1; i++) { 1571 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 1572 return (error); 1573 } 1574 /* Make the last page point to the beginning of the ring buffer. */ 1575 error = urtwn_llt_write(sc, i, page_count + 1); 1576 return (error); 1577 } 1578 1579 int 1580 urtwn_fw_loadpage(void *cookie, int page, uint8_t *buf, int len) 1581 { 1582 struct urtwn_softc *sc = cookie; 1583 uint32_t reg; 1584 int off, mlen, error = 0; 1585 1586 reg = urtwn_read_4(sc, R92C_MCUFWDL); 1587 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 1588 urtwn_write_4(sc, R92C_MCUFWDL, reg); 1589 1590 off = R92C_FW_START_ADDR; 1591 while (len > 0) { 1592 if (len > 196) 1593 mlen = 196; 1594 else if (len > 4) 1595 mlen = 4; 1596 else 1597 mlen = 1; 1598 error = urtwn_write_region_1(sc, off, buf, mlen); 1599 if (error != 0) 1600 break; 1601 off += mlen; 1602 buf += mlen; 1603 len -= mlen; 1604 } 1605 return (error); 1606 } 1607 1608 int 1609 urtwn_load_firmware(void *cookie, u_char **fw, size_t *len) 1610 { 1611 struct urtwn_softc *sc = cookie; 1612 const char *name; 1613 int error; 1614 1615 if (sc->sc_sc.chip & RTWN_CHIP_88E) 1616 name = "urtwn-rtl8188eufw"; 1617 else if ((sc->sc_sc.chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 1618 RTWN_CHIP_UMC_A_CUT) 1619 name = "urtwn-rtl8192cfwU"; 1620 else 1621 name = "urtwn-rtl8192cfwT"; 1622 1623 error = loadfirmware(name, fw, len); 1624 if (error) 1625 printf("%s: could not read firmware %s (error %d)\n", 1626 sc->sc_dev.dv_xname, name, error); 1627 return (error); 1628 } 1629 1630 int 1631 urtwn_dma_init(void *cookie) 1632 { 1633 struct urtwn_softc *sc = cookie; 1634 1635 if (sc->sc_sc.chip & RTWN_CHIP_88E) 1636 return urtwn_r88e_dma_init(sc); 1637 1638 return urtwn_r92c_dma_init(sc); 1639 } 1640 1641 int 1642 urtwn_r92c_dma_init(struct urtwn_softc *sc) 1643 { 1644 int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 1645 uint32_t reg; 1646 int error; 1647 1648 /* Initialize LLT table. */ 1649 error = urtwn_llt_init(sc); 1650 if (error != 0) 1651 return (error); 1652 1653 /* Get Tx queues to USB endpoints mapping. */ 1654 hashq = hasnq = haslq = 0; 1655 reg = urtwn_read_2(sc, R92C_USB_EP + 1); 1656 DPRINTFN(2, ("USB endpoints mapping 0x%x\n", reg)); 1657 if (MS(reg, R92C_USB_EP_HQ) != 0) 1658 hashq = 1; 1659 if (MS(reg, R92C_USB_EP_NQ) != 0) 1660 hasnq = 1; 1661 if (MS(reg, R92C_USB_EP_LQ) != 0) 1662 haslq = 1; 1663 nqueues = hashq + hasnq + haslq; 1664 if (nqueues == 0) 1665 return (EIO); 1666 /* Get the number of pages for each queue. */ 1667 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 1668 /* The remaining pages are assigned to the high priority queue. */ 1669 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 1670 1671 /* Set number of pages for normal priority queue. */ 1672 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 1673 urtwn_write_4(sc, R92C_RQPN, 1674 /* Set number of pages for public queue. */ 1675 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 1676 /* Set number of pages for high priority queue. */ 1677 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 1678 /* Set number of pages for low priority queue. */ 1679 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 1680 /* Load values. */ 1681 R92C_RQPN_LD); 1682 1683 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 1684 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 1685 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 1686 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 1687 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 1688 1689 /* Set queue to USB pipe mapping. */ 1690 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 1691 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 1692 if (nqueues == 1) { 1693 if (hashq) 1694 reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 1695 else if (hasnq) 1696 reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 1697 else 1698 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 1699 } else if (nqueues == 2) { 1700 /* All 2-endpoints configs have a high priority queue. */ 1701 if (!hashq) 1702 return (EIO); 1703 if (hasnq) 1704 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 1705 else 1706 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 1707 } else 1708 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 1709 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 1710 1711 /* Set Tx/Rx transfer page boundary. */ 1712 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 1713 1714 /* Set Tx/Rx transfer page size. */ 1715 urtwn_write_1(sc, R92C_PBP, 1716 SM(R92C_PBP_PSRX, R92C_PBP_128) | 1717 SM(R92C_PBP_PSTX, R92C_PBP_128)); 1718 return (0); 1719 } 1720 1721 int 1722 urtwn_r88e_dma_init(struct urtwn_softc *sc) 1723 { 1724 usb_interface_descriptor_t *id; 1725 uint32_t reg; 1726 int nqueues = 1; 1727 int error; 1728 1729 /* Initialize LLT table. */ 1730 error = urtwn_llt_init(sc); 1731 if (error != 0) 1732 return (error); 1733 1734 /* Get Tx queues to USB endpoints mapping. */ 1735 id = usbd_get_interface_descriptor(sc->sc_iface); 1736 nqueues = id->bNumEndpoints - 1; 1737 1738 /* Set number of pages for normal priority queue. */ 1739 urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 1740 urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 1741 1742 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 1743 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 1744 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 1745 urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 1746 urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 1747 1748 /* Set queue to USB pipe mapping. */ 1749 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 1750 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 1751 if (nqueues == 1) 1752 reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 1753 else if (nqueues == 2) 1754 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 1755 else 1756 reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 1757 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 1758 1759 /* Set Tx/Rx transfer page boundary. */ 1760 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 1761 1762 /* Set Tx/Rx transfer page size. */ 1763 urtwn_write_1(sc, R92C_PBP, 1764 SM(R92C_PBP_PSRX, R92C_PBP_128) | 1765 SM(R92C_PBP_PSTX, R92C_PBP_128)); 1766 1767 return (0); 1768 } 1769 1770 void 1771 urtwn_mac_init(void *cookie) 1772 { 1773 struct urtwn_softc *sc = cookie; 1774 int i; 1775 1776 /* Write MAC initialization values. */ 1777 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1778 for (i = 0; i < nitems(rtl8188eu_mac); i++) { 1779 urtwn_write_1(sc, rtl8188eu_mac[i].reg, 1780 rtl8188eu_mac[i].val); 1781 } 1782 urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 1783 } else { 1784 for (i = 0; i < nitems(rtl8192cu_mac); i++) 1785 urtwn_write_1(sc, rtl8192cu_mac[i].reg, 1786 rtl8192cu_mac[i].val); 1787 } 1788 } 1789 1790 void 1791 urtwn_bb_init(void *cookie) 1792 { 1793 struct urtwn_softc *sc = cookie; 1794 const struct r92c_bb_prog *prog; 1795 uint32_t reg; 1796 uint8_t crystalcap; 1797 int i; 1798 1799 /* Enable BB and RF. */ 1800 urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1801 urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 1802 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 1803 R92C_SYS_FUNC_EN_DIO_RF); 1804 1805 if (!(sc->sc_sc.chip & RTWN_CHIP_88E)) 1806 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 1807 1808 urtwn_write_1(sc, R92C_RF_CTRL, 1809 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 1810 urtwn_write_1(sc, R92C_SYS_FUNC_EN, 1811 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 1812 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 1813 1814 if (!(sc->sc_sc.chip & RTWN_CHIP_88E)) { 1815 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 1816 urtwn_write_1(sc, 0x15, 0xe9); 1817 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 1818 } 1819 1820 /* Select BB programming based on board type. */ 1821 if (sc->sc_sc.chip & RTWN_CHIP_88E) 1822 prog = &rtl8188eu_bb_prog; 1823 else if (!(sc->sc_sc.chip & RTWN_CHIP_92C)) { 1824 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD) 1825 prog = &rtl8188ce_bb_prog; 1826 else if (sc->sc_sc.board_type == R92C_BOARD_TYPE_HIGHPA) 1827 prog = &rtl8188ru_bb_prog; 1828 else 1829 prog = &rtl8188cu_bb_prog; 1830 } else { 1831 if (sc->sc_sc.board_type == R92C_BOARD_TYPE_MINICARD) 1832 prog = &rtl8192ce_bb_prog; 1833 else 1834 prog = &rtl8192cu_bb_prog; 1835 } 1836 /* Write BB initialization values. */ 1837 for (i = 0; i < prog->count; i++) { 1838 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 1839 DELAY(1); 1840 } 1841 1842 if (sc->sc_sc.chip & RTWN_CHIP_92C_1T2R) { 1843 /* 8192C 1T only configuration. */ 1844 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 1845 reg = (reg & ~0x00000003) | 0x2; 1846 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 1847 1848 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 1849 reg = (reg & ~0x00300033) | 0x00200022; 1850 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 1851 1852 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 1853 reg = (reg & ~0xff000000) | 0x45 << 24; 1854 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 1855 1856 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 1857 reg = (reg & ~0x000000ff) | 0x23; 1858 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 1859 1860 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 1861 reg = (reg & ~0x00000030) | 1 << 4; 1862 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 1863 1864 reg = urtwn_bb_read(sc, 0xe74); 1865 reg = (reg & ~0x0c000000) | 2 << 26; 1866 urtwn_bb_write(sc, 0xe74, reg); 1867 reg = urtwn_bb_read(sc, 0xe78); 1868 reg = (reg & ~0x0c000000) | 2 << 26; 1869 urtwn_bb_write(sc, 0xe78, reg); 1870 reg = urtwn_bb_read(sc, 0xe7c); 1871 reg = (reg & ~0x0c000000) | 2 << 26; 1872 urtwn_bb_write(sc, 0xe7c, reg); 1873 reg = urtwn_bb_read(sc, 0xe80); 1874 reg = (reg & ~0x0c000000) | 2 << 26; 1875 urtwn_bb_write(sc, 0xe80, reg); 1876 reg = urtwn_bb_read(sc, 0xe88); 1877 reg = (reg & ~0x0c000000) | 2 << 26; 1878 urtwn_bb_write(sc, 0xe88, reg); 1879 } 1880 1881 /* Write AGC values. */ 1882 for (i = 0; i < prog->agccount; i++) { 1883 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 1884 prog->agcvals[i]); 1885 DELAY(1); 1886 } 1887 1888 if (sc->sc_sc.chip & RTWN_CHIP_88E) { 1889 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 1890 DELAY(1); 1891 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 1892 DELAY(1); 1893 1894 crystalcap = sc->sc_sc.r88e_rom[0xb9]; 1895 if (crystalcap == 0xff) 1896 crystalcap = 0x20; 1897 crystalcap &= 0x3f; 1898 reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 1899 urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 1900 RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 1901 crystalcap | crystalcap << 6)); 1902 } else { 1903 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 1904 R92C_HSSI_PARAM2_CCK_HIPWR) 1905 sc->sc_sc.sc_flags |= RTWN_FLAG_CCK_HIPWR; 1906 } 1907 } 1908 1909 int 1910 urtwn_power_on(void *cookie) 1911 { 1912 struct urtwn_softc *sc = cookie; 1913 1914 if (sc->sc_sc.chip & RTWN_CHIP_88E) 1915 return urtwn_r88e_power_on(sc); 1916 1917 return urtwn_r92c_power_on(sc); 1918 } 1919 1920 int 1921 urtwn_alloc_buffers(void *cookie) 1922 { 1923 struct urtwn_softc *sc = cookie; 1924 int error; 1925 1926 /* Init host async commands ring. */ 1927 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 1928 1929 /* Allocate Tx/Rx buffers. */ 1930 error = urtwn_alloc_rx_list(sc); 1931 if (error != 0) { 1932 printf("%s: could not allocate Rx buffers\n", 1933 sc->sc_dev.dv_xname); 1934 return (error); 1935 } 1936 error = urtwn_alloc_tx_list(sc); 1937 if (error != 0) { 1938 printf("%s: could not allocate Tx buffers\n", 1939 sc->sc_dev.dv_xname); 1940 return (error); 1941 } 1942 1943 return (0); 1944 } 1945 1946 int 1947 urtwn_init(void *cookie) 1948 { 1949 struct urtwn_softc *sc = cookie; 1950 int i, error; 1951 1952 /* Queue Rx xfers. */ 1953 for (i = 0; i < URTWN_RX_LIST_COUNT; i++) { 1954 struct urtwn_rx_data *data = &sc->rx_data[i]; 1955 1956 usbd_setup_xfer(data->xfer, sc->rx_pipe, data, data->buf, 1957 URTWN_RXBUFSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 1958 USBD_NO_TIMEOUT, urtwn_rxeof); 1959 error = usbd_transfer(data->xfer); 1960 if (error != 0 && error != USBD_IN_PROGRESS) 1961 return (error); 1962 } 1963 1964 return (0); 1965 } 1966 1967 void 1968 urtwn_stop(void *cookie) 1969 { 1970 struct urtwn_softc *sc = cookie; 1971 int i; 1972 1973 /* Abort Tx. */ 1974 for (i = 0; i < R92C_MAX_EPOUT; i++) { 1975 if (sc->tx_pipe[i] != NULL) 1976 usbd_abort_pipe(sc->tx_pipe[i]); 1977 } 1978 /* Stop Rx pipe. */ 1979 usbd_abort_pipe(sc->rx_pipe); 1980 /* Free Tx/Rx buffers. */ 1981 urtwn_free_tx_list(sc); 1982 urtwn_free_rx_list(sc); 1983 } 1984 1985 int 1986 urtwn_is_oactive(void *cookie) 1987 { 1988 struct urtwn_softc *sc = cookie; 1989 1990 return (TAILQ_EMPTY(&sc->tx_free_list)); 1991 } 1992