1 /* $OpenBSD: if_urtw.c,v 1.64 2017/01/22 10:17:39 dlg Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Martynas Venckus <martynas@openbsd.org> 5 * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include "bpfilter.h" 21 22 #include <sys/param.h> 23 #include <sys/sockio.h> 24 #include <sys/mbuf.h> 25 #include <sys/kernel.h> 26 #include <sys/socket.h> 27 #include <sys/systm.h> 28 #include <sys/timeout.h> 29 #include <sys/conf.h> 30 #include <sys/device.h> 31 #include <sys/endian.h> 32 33 #if NBPFILTER > 0 34 #include <net/bpf.h> 35 #endif 36 #include <net/if.h> 37 #include <net/if_dl.h> 38 #include <net/if_media.h> 39 40 #include <netinet/in.h> 41 #include <netinet/if_ether.h> 42 43 #include <net80211/ieee80211_var.h> 44 #include <net80211/ieee80211_radiotap.h> 45 46 #include <dev/usb/usb.h> 47 #include <dev/usb/usbdi.h> 48 #include <dev/usb/usbdi_util.h> 49 #include <dev/usb/usbdevs.h> 50 51 #include <dev/usb/if_urtwreg.h> 52 53 #ifdef URTW_DEBUG 54 #define DPRINTF(x) do { if (urtw_debug) printf x; } while (0) 55 #define DPRINTFN(n, x) do { if (urtw_debug >= (n)) printf x; } while (0) 56 int urtw_debug = 0; 57 #else 58 #define DPRINTF(x) 59 #define DPRINTFN(n, x) 60 #endif 61 62 /* 63 * Recognized device vendors/products. 64 */ 65 static const struct urtw_type { 66 struct usb_devno dev; 67 uint8_t rev; 68 } urtw_devs[] = { 69 #define URTW_DEV_RTL8187(v, p) \ 70 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, URTW_HWREV_8187 } 71 #define URTW_DEV_RTL8187B(v, p) \ 72 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, URTW_HWREV_8187B } 73 /* Realtek RTL8187 devices. */ 74 URTW_DEV_RTL8187(ASUS, P5B_WIFI), 75 URTW_DEV_RTL8187(DICKSMITH, RTL8187), 76 URTW_DEV_RTL8187(LINKSYS4, WUSB54GCV2), 77 URTW_DEV_RTL8187(LOGITEC, RTL8187), 78 URTW_DEV_RTL8187(NETGEAR, WG111V2), 79 URTW_DEV_RTL8187(REALTEK, RTL8187), 80 URTW_DEV_RTL8187(SITECOMEU, WL168V1), 81 URTW_DEV_RTL8187(SPHAIRON, RTL8187), 82 URTW_DEV_RTL8187(SURECOM, EP9001G2A), 83 /* Realtek RTL8187B devices. */ 84 URTW_DEV_RTL8187B(BELKIN, F5D7050E), 85 URTW_DEV_RTL8187B(NETGEAR, WG111V3), 86 URTW_DEV_RTL8187B(REALTEK, RTL8187B_0), 87 URTW_DEV_RTL8187B(REALTEK, RTL8187B_1), 88 URTW_DEV_RTL8187B(REALTEK, RTL8187B_2), 89 URTW_DEV_RTL8187B(SITECOMEU, WL168V4) 90 #undef URTW_DEV_RTL8187 91 #undef URTW_DEV_RTL8187B 92 }; 93 #define urtw_lookup(v, p) \ 94 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p)) 95 96 /* 97 * Helper read/write macros. 98 */ 99 #define urtw_read8_m(sc, val, data) do { \ 100 error = urtw_read8_c(sc, val, data, 0); \ 101 if (error != 0) \ 102 goto fail; \ 103 } while (0) 104 #define urtw_read8_idx_m(sc, val, data, idx) do { \ 105 error = urtw_read8_c(sc, val, data, idx); \ 106 if (error != 0) \ 107 goto fail; \ 108 } while (0) 109 #define urtw_write8_m(sc, val, data) do { \ 110 error = urtw_write8_c(sc, val, data, 0); \ 111 if (error != 0) \ 112 goto fail; \ 113 } while (0) 114 #define urtw_write8_idx_m(sc, val, data, idx) do { \ 115 error = urtw_write8_c(sc, val, data, idx); \ 116 if (error != 0) \ 117 goto fail; \ 118 } while (0) 119 #define urtw_read16_m(sc, val, data) do { \ 120 error = urtw_read16_c(sc, val, data, 0); \ 121 if (error != 0) \ 122 goto fail; \ 123 } while (0) 124 #define urtw_read16_idx_m(sc, val, data, idx) do { \ 125 error = urtw_read16_c(sc, val, data, idx); \ 126 if (error != 0) \ 127 goto fail; \ 128 } while (0) 129 #define urtw_write16_m(sc, val, data) do { \ 130 error = urtw_write16_c(sc, val, data, 0); \ 131 if (error != 0) \ 132 goto fail; \ 133 } while (0) 134 #define urtw_write16_idx_m(sc, val, data, idx) do { \ 135 error = urtw_write16_c(sc, val, data, idx); \ 136 if (error != 0) \ 137 goto fail; \ 138 } while (0) 139 #define urtw_read32_m(sc, val, data) do { \ 140 error = urtw_read32_c(sc, val, data, 0); \ 141 if (error != 0) \ 142 goto fail; \ 143 } while (0) 144 #define urtw_read32_idx_m(sc, val, data, idx) do { \ 145 error = urtw_read32_c(sc, val, data, idx); \ 146 if (error != 0) \ 147 goto fail; \ 148 } while (0) 149 #define urtw_write32_m(sc, val, data) do { \ 150 error = urtw_write32_c(sc, val, data, 0); \ 151 if (error != 0) \ 152 goto fail; \ 153 } while (0) 154 #define urtw_write32_idx_m(sc, val, data, idx) do { \ 155 error = urtw_write32_c(sc, val, data, idx); \ 156 if (error != 0) \ 157 goto fail; \ 158 } while (0) 159 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \ 160 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \ 161 if (error != 0) \ 162 goto fail; \ 163 } while (0) 164 #define urtw_8187_write_phy_cck(sc, val, data) do { \ 165 error = urtw_8187_write_phy_cck_c(sc, val, data); \ 166 if (error != 0) \ 167 goto fail; \ 168 } while (0) 169 #define urtw_8225_write(sc, val, data) do { \ 170 error = urtw_8225_write_c(sc, val, data); \ 171 if (error != 0) \ 172 goto fail; \ 173 } while (0) 174 175 struct urtw_pair { 176 uint32_t reg; 177 uint32_t val; 178 }; 179 180 struct urtw_pair_idx { 181 uint8_t reg; 182 uint8_t val; 183 uint8_t idx; 184 }; 185 186 static struct urtw_pair_idx urtw_8187b_regtbl[] = { 187 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 }, 188 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 }, 189 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 }, 190 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 }, 191 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 }, 192 { 0xff, 0x00, 0 }, 193 194 { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 }, { 0x5a, 0x4b, 1 }, 195 { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 }, { 0x61, 0x09, 1 }, 196 { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 }, { 0xce, 0x0f, 1 }, 197 { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 }, { 0xe1, 0x0f, 1 }, 198 { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 }, { 0xf1, 0x01, 1 }, 199 { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 }, { 0xf4, 0x04, 1 }, 200 { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 }, { 0xf7, 0x07, 1 }, 201 { 0xf8, 0x08, 1 }, 202 203 { 0x4e, 0x00, 2 }, { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, 204 { 0x22, 0x68, 2 }, { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, 205 { 0x25, 0x7d, 2 }, { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, 206 { 0x4d, 0x08, 2 }, { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, 207 { 0x52, 0x04, 2 }, { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, 208 { 0x55, 0x23, 2 }, { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, 209 { 0x58, 0x08, 2 }, { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, 210 { 0x5b, 0x08, 2 }, { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, 211 { 0x62, 0x08, 2 }, { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, 212 { 0x72, 0x56, 2 }, { 0x73, 0x9a, 2 }, 213 214 { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 }, { 0x5b, 0x40, 0 }, 215 { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 }, { 0x88, 0x54, 0 }, 216 { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 }, { 0x8d, 0x00, 0 }, 217 { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 }, { 0x96, 0x00, 0 }, 218 { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 }, { 0x9f, 0x10, 0 }, 219 { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 }, { 0xdb, 0x00, 0 }, 220 { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 }, 221 222 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 }, 223 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 } 224 }; 225 226 static uint8_t urtw_8225_agc[] = { 227 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b, 228 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 229 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85, 230 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 231 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 232 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 233 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 234 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 235 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 236 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 237 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 238 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 239 }; 240 241 static uint32_t urtw_8225_channel[] = { 242 0x0000, /* dummy channel 0 */ 243 0x085c, /* 1 */ 244 0x08dc, /* 2 */ 245 0x095c, /* 3 */ 246 0x09dc, /* 4 */ 247 0x0a5c, /* 5 */ 248 0x0adc, /* 6 */ 249 0x0b5c, /* 7 */ 250 0x0bdc, /* 8 */ 251 0x0c5c, /* 9 */ 252 0x0cdc, /* 10 */ 253 0x0d5c, /* 11 */ 254 0x0ddc, /* 12 */ 255 0x0e5c, /* 13 */ 256 0x0f72, /* 14 */ 257 }; 258 259 static uint8_t urtw_8225_gain[] = { 260 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */ 261 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */ 262 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */ 263 0x33, 0x80, 0x79, 0xc5, /* -78dbm */ 264 0x43, 0x78, 0x76, 0xc5, /* -74dbm */ 265 0x53, 0x60, 0x73, 0xc5, /* -70dbm */ 266 0x63, 0x58, 0x70, 0xc5, /* -66dbm */ 267 }; 268 269 static struct urtw_pair urtw_8225_rf_part1[] = { 270 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 271 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a }, 272 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 }, 273 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 } 274 }; 275 276 static struct urtw_pair urtw_8225_rf_part2[] = { 277 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 278 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 279 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 }, 280 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 }, 281 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 }, 282 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef }, 283 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 }, 284 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 }, 285 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 }, 286 { 0x27, 0x88 } 287 }; 288 289 static struct urtw_pair urtw_8225_rf_part3[] = { 290 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 291 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b }, 292 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, 293 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d }, 294 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e }, 295 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a }, 296 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 } 297 }; 298 299 static uint16_t urtw_8225_rxgain[] = { 300 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 301 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 302 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 303 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 304 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 305 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 306 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 307 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 308 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 309 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 310 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3, 311 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb 312 }; 313 314 static uint8_t urtw_8225_threshold[] = { 315 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd 316 }; 317 318 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = { 319 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e 320 }; 321 322 static uint8_t urtw_8225_txpwr_cck[] = { 323 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02, 324 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02, 325 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02, 326 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02, 327 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03, 328 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03 329 }; 330 331 static uint8_t urtw_8225_txpwr_cck_ch14[] = { 332 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00, 333 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00, 334 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00, 335 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00, 336 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00, 337 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00 338 }; 339 340 static uint8_t urtw_8225_txpwr_ofdm[] = { 341 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4 342 }; 343 344 static uint8_t urtw_8225v2_agc[] = { 345 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 346 0x55, 0x53, 0x51, 0x4f, 0x4d, 0x4b, 0x49, 0x47, 347 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x39, 0x37, 348 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 349 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 350 0x15, 0x13, 0x11, 0x0f, 0x0d, 0x0b, 0x09, 0x07, 351 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 352 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 353 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 354 0x19, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 355 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a, 356 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 357 0x2d, 0x2d, 0x2d, 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 358 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31, 0x31, 0x31, 359 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 360 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31 361 }; 362 363 static uint8_t urtw_8225v2_ofdm[] = { 364 0x10, 0x0d, 0x01, 0x00, 0x14, 0xfb, 0xfb, 0x60, 365 0x00, 0x60, 0x00, 0x00, 0x00, 0x5c, 0x00, 0x00, 366 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xa8, 0x26, 367 0x32, 0x33, 0x07, 0xa5, 0x6f, 0x55, 0xc8, 0xb3, 368 0x0a, 0xe1, 0x2c, 0x8a, 0x86, 0x83, 0x34, 0x0f, 369 0x4f, 0x24, 0x6f, 0xc2, 0x6b, 0x40, 0x80, 0x00, 370 0xc0, 0xc1, 0x58, 0xf1, 0x00, 0xe4, 0x90, 0x3e, 371 0x6d, 0x3c, 0xfb, 0x07 372 }; 373 374 static uint8_t urtw_8225v2_gain_bg[] = { 375 0x23, 0x15, 0xa5, /* -82-1dbm */ 376 0x23, 0x15, 0xb5, /* -82-2dbm */ 377 0x23, 0x15, 0xc5, /* -82-3dbm */ 378 0x33, 0x15, 0xc5, /* -78dbm */ 379 0x43, 0x15, 0xc5, /* -74dbm */ 380 0x53, 0x15, 0xc5, /* -70dbm */ 381 0x63, 0x15, 0xc5, /* -66dbm */ 382 }; 383 384 static struct urtw_pair urtw_8225v2_rf_part1[] = { 385 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 386 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 387 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 388 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 389 }; 390 391 static struct urtw_pair urtw_8225v2_rf_part2[] = { 392 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 393 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 394 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 }, 395 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, 396 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 }, 397 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, 398 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 }, 399 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 }, 400 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 }, 401 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 } 402 }; 403 404 static struct urtw_pair urtw_8225v2_rf_part3[] = { 405 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 406 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 }, 407 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 }, 408 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 }, 409 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d }, 410 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 }, 411 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 }, 412 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 } 413 }; 414 415 static uint16_t urtw_8225v2_rxgain[] = { 416 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 417 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 418 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 419 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 420 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 421 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 422 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 423 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 424 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 425 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 426 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 427 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 428 }; 429 430 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = { 431 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 432 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 433 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 434 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 435 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 436 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23 437 }; 438 439 static uint8_t urtw_8225v2_txpwr_cck[] = { 440 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04, 441 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03, 442 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03, 443 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03 444 }; 445 446 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = { 447 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00, 448 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 449 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 450 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00 451 }; 452 453 static struct urtw_pair urtw_8225v2_b_rf[] = { 454 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 455 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 456 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 457 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }, 458 { 0x00, 0x01b7 } 459 }; 460 461 static struct urtw_pair urtw_ratetable[] = { 462 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 }, 463 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 }, 464 { 96, 10 }, { 108, 11 } 465 }; 466 467 int urtw_init(struct ifnet *); 468 void urtw_stop(struct ifnet *, int); 469 int urtw_ioctl(struct ifnet *, u_long, caddr_t); 470 void urtw_start(struct ifnet *); 471 int urtw_alloc_rx_data_list(struct urtw_softc *); 472 void urtw_free_rx_data_list(struct urtw_softc *); 473 int urtw_alloc_tx_data_list(struct urtw_softc *); 474 void urtw_free_tx_data_list(struct urtw_softc *); 475 void urtw_rxeof(struct usbd_xfer *, void *, 476 usbd_status); 477 int urtw_tx_start(struct urtw_softc *, 478 struct ieee80211_node *, struct mbuf *, int); 479 void urtw_txeof_low(struct usbd_xfer *, void *, 480 usbd_status); 481 void urtw_txeof_normal(struct usbd_xfer *, void *, 482 usbd_status); 483 void urtw_next_scan(void *); 484 void urtw_task(void *); 485 void urtw_ledusbtask(void *); 486 void urtw_ledtask(void *); 487 int urtw_media_change(struct ifnet *); 488 int urtw_newstate(struct ieee80211com *, enum ieee80211_state, int); 489 void urtw_watchdog(struct ifnet *); 490 void urtw_set_multi(struct urtw_softc *); 491 void urtw_set_chan(struct urtw_softc *, struct ieee80211_channel *); 492 int urtw_isbmode(uint16_t); 493 uint16_t urtw_rate2rtl(int rate); 494 uint16_t urtw_rtl2rate(int); 495 usbd_status urtw_set_rate(struct urtw_softc *); 496 usbd_status urtw_update_msr(struct urtw_softc *); 497 usbd_status urtw_read8_c(struct urtw_softc *, int, uint8_t *, uint8_t); 498 usbd_status urtw_read16_c(struct urtw_softc *, int, uint16_t *, uint8_t); 499 usbd_status urtw_read32_c(struct urtw_softc *, int, uint32_t *, uint8_t); 500 usbd_status urtw_write8_c(struct urtw_softc *, int, uint8_t, uint8_t); 501 usbd_status urtw_write16_c(struct urtw_softc *, int, uint16_t, uint8_t); 502 usbd_status urtw_write32_c(struct urtw_softc *, int, uint32_t, uint8_t); 503 usbd_status urtw_eprom_cs(struct urtw_softc *, int); 504 usbd_status urtw_eprom_ck(struct urtw_softc *); 505 usbd_status urtw_eprom_sendbits(struct urtw_softc *, int16_t *, 506 int); 507 usbd_status urtw_eprom_read32(struct urtw_softc *, uint32_t, 508 uint32_t *); 509 usbd_status urtw_eprom_readbit(struct urtw_softc *, int16_t *); 510 usbd_status urtw_eprom_writebit(struct urtw_softc *, int16_t); 511 usbd_status urtw_get_macaddr(struct urtw_softc *); 512 usbd_status urtw_get_txpwr(struct urtw_softc *); 513 usbd_status urtw_get_rfchip(struct urtw_softc *); 514 usbd_status urtw_led_init(struct urtw_softc *); 515 usbd_status urtw_8185_rf_pins_enable(struct urtw_softc *); 516 usbd_status urtw_8185_tx_antenna(struct urtw_softc *, uint8_t); 517 usbd_status urtw_8187_write_phy(struct urtw_softc *, uint8_t, uint32_t); 518 usbd_status urtw_8187_write_phy_ofdm_c(struct urtw_softc *, uint8_t, 519 uint32_t); 520 usbd_status urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t, 521 uint32_t); 522 usbd_status urtw_8225_setgain(struct urtw_softc *, int16_t); 523 usbd_status urtw_8225_usb_init(struct urtw_softc *); 524 usbd_status urtw_8225_write_c(struct urtw_softc *, uint8_t, uint16_t); 525 usbd_status urtw_8225_write_s16(struct urtw_softc *, uint8_t, int, 526 uint16_t); 527 usbd_status urtw_8225_read(struct urtw_softc *, uint8_t, uint32_t *); 528 usbd_status urtw_8225_rf_init(struct urtw_rf *); 529 usbd_status urtw_8225_rf_set_chan(struct urtw_rf *, int); 530 usbd_status urtw_8225_rf_set_sens(struct urtw_rf *); 531 usbd_status urtw_8225_set_txpwrlvl(struct urtw_softc *, int); 532 usbd_status urtw_8225v2_rf_init(struct urtw_rf *); 533 usbd_status urtw_8225v2_rf_set_chan(struct urtw_rf *, int); 534 usbd_status urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int); 535 usbd_status urtw_8225v2_setgain(struct urtw_softc *, int16_t); 536 usbd_status urtw_8225_isv2(struct urtw_softc *, int *); 537 usbd_status urtw_read8e(struct urtw_softc *, int, uint8_t *); 538 usbd_status urtw_write8e(struct urtw_softc *, int, uint8_t); 539 usbd_status urtw_8180_set_anaparam(struct urtw_softc *, uint32_t); 540 usbd_status urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t); 541 usbd_status urtw_open_pipes(struct urtw_softc *); 542 usbd_status urtw_close_pipes(struct urtw_softc *); 543 usbd_status urtw_intr_enable(struct urtw_softc *); 544 usbd_status urtw_intr_disable(struct urtw_softc *); 545 usbd_status urtw_reset(struct urtw_softc *); 546 usbd_status urtw_led_on(struct urtw_softc *, int); 547 usbd_status urtw_led_ctl(struct urtw_softc *, int); 548 usbd_status urtw_led_blink(struct urtw_softc *); 549 usbd_status urtw_led_mode0(struct urtw_softc *, int); 550 usbd_status urtw_led_mode1(struct urtw_softc *, int); 551 usbd_status urtw_led_mode2(struct urtw_softc *, int); 552 usbd_status urtw_led_mode3(struct urtw_softc *, int); 553 usbd_status urtw_rx_setconf(struct urtw_softc *); 554 usbd_status urtw_rx_enable(struct urtw_softc *); 555 usbd_status urtw_tx_enable(struct urtw_softc *); 556 usbd_status urtw_8187b_update_wmm(struct urtw_softc *); 557 usbd_status urtw_8187b_reset(struct urtw_softc *); 558 int urtw_8187b_init(struct ifnet *); 559 usbd_status urtw_8225v2_b_config_mac(struct urtw_softc *); 560 usbd_status urtw_8225v2_b_init_rfe(struct urtw_softc *); 561 usbd_status urtw_8225v2_b_update_chan(struct urtw_softc *); 562 usbd_status urtw_8225v2_b_rf_init(struct urtw_rf *); 563 usbd_status urtw_8225v2_b_rf_set_chan(struct urtw_rf *, int); 564 usbd_status urtw_8225v2_b_set_txpwrlvl(struct urtw_softc *, int); 565 int urtw_set_bssid(struct urtw_softc *, const uint8_t *); 566 int urtw_set_macaddr(struct urtw_softc *, const uint8_t *); 567 568 int urtw_match(struct device *, void *, void *); 569 void urtw_attach(struct device *, struct device *, void *); 570 int urtw_detach(struct device *, int); 571 572 struct cfdriver urtw_cd = { 573 NULL, "urtw", DV_IFNET 574 }; 575 576 const struct cfattach urtw_ca = { 577 sizeof(struct urtw_softc), urtw_match, urtw_attach, urtw_detach 578 }; 579 580 int 581 urtw_match(struct device *parent, void *match, void *aux) 582 { 583 struct usb_attach_arg *uaa = aux; 584 585 if (uaa->iface == NULL || uaa->configno != 1) 586 return (UMATCH_NONE); 587 588 return ((urtw_lookup(uaa->vendor, uaa->product) != NULL) ? 589 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 590 } 591 592 void 593 urtw_attach(struct device *parent, struct device *self, void *aux) 594 { 595 struct urtw_softc *sc = (struct urtw_softc *)self; 596 struct usb_attach_arg *uaa = aux; 597 struct ieee80211com *ic = &sc->sc_ic; 598 struct ifnet *ifp = &ic->ic_if; 599 usbd_status error; 600 uint8_t data8; 601 uint32_t data; 602 int i; 603 604 sc->sc_udev = uaa->device; 605 sc->sc_iface = uaa->iface; 606 sc->sc_hwrev = urtw_lookup(uaa->vendor, uaa->product)->rev; 607 608 printf("%s: ", sc->sc_dev.dv_xname); 609 610 if (sc->sc_hwrev & URTW_HWREV_8187) { 611 urtw_read32_m(sc, URTW_TX_CONF, &data); 612 data &= URTW_TX_HWREV_MASK; 613 switch (data) { 614 case URTW_TX_HWREV_8187_D: 615 sc->sc_hwrev |= URTW_HWREV_8187_D; 616 printf("RTL8187 rev D"); 617 break; 618 case URTW_TX_HWREV_8187B_D: 619 /* 620 * Detect Realtek RTL8187B devices that use 621 * USB IDs of RTL8187. 622 */ 623 sc->sc_hwrev = URTW_HWREV_8187B | URTW_HWREV_8187B_B; 624 printf("RTL8187B rev B (early)"); 625 break; 626 default: 627 sc->sc_hwrev |= URTW_HWREV_8187_B; 628 printf("RTL8187 rev 0x%02x", data >> 25); 629 break; 630 } 631 } else { 632 /* RTL8187B hwrev register. */ 633 urtw_read8_m(sc, URTW_8187B_HWREV, &data8); 634 switch (data8) { 635 case URTW_8187B_HWREV_8187B_B: 636 sc->sc_hwrev |= URTW_HWREV_8187B_B; 637 printf("RTL8187B rev B"); 638 break; 639 case URTW_8187B_HWREV_8187B_D: 640 sc->sc_hwrev |= URTW_HWREV_8187B_D; 641 printf("RTL8187B rev D"); 642 break; 643 case URTW_8187B_HWREV_8187B_E: 644 sc->sc_hwrev |= URTW_HWREV_8187B_E; 645 printf("RTL8187B rev E"); 646 break; 647 default: 648 sc->sc_hwrev |= URTW_HWREV_8187B_B; 649 printf("RTL8187B rev 0x%02x", data8); 650 break; 651 } 652 } 653 654 urtw_read32_m(sc, URTW_RX, &data); 655 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 : 656 URTW_EEPROM_93C46; 657 658 error = urtw_get_rfchip(sc); 659 if (error != 0) 660 goto fail; 661 error = urtw_get_macaddr(sc); 662 if (error != 0) 663 goto fail; 664 error = urtw_get_txpwr(sc); 665 if (error != 0) 666 goto fail; 667 error = urtw_led_init(sc); /* XXX incompleted */ 668 if (error != 0) 669 goto fail; 670 671 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY; 672 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY; 673 sc->sc_currate = 3; 674 /* XXX for what? */ 675 sc->sc_preamble_mode = 2; 676 677 usb_init_task(&sc->sc_task, urtw_task, sc, USB_TASK_TYPE_GENERIC); 678 usb_init_task(&sc->sc_ledtask, urtw_ledusbtask, sc, 679 USB_TASK_TYPE_GENERIC); 680 timeout_set(&sc->scan_to, urtw_next_scan, sc); 681 timeout_set(&sc->sc_led_ch, urtw_ledtask, sc); 682 683 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 684 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 685 ic->ic_state = IEEE80211_S_INIT; 686 687 /* set device capabilities */ 688 ic->ic_caps = 689 IEEE80211_C_MONITOR | /* monitor mode supported */ 690 IEEE80211_C_TXPMGT | /* tx power management */ 691 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 692 IEEE80211_C_SHSLOT | /* short slot time supported */ 693 IEEE80211_C_WEP | /* s/w WEP */ 694 IEEE80211_C_RSN; /* WPA/RSN */ 695 696 /* set supported .11b and .11g rates */ 697 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 698 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 699 700 /* set supported .11b and .11g channels (1 through 14) */ 701 for (i = 1; i <= 14; i++) { 702 ic->ic_channels[i].ic_freq = 703 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 704 ic->ic_channels[i].ic_flags = 705 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 706 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 707 } 708 709 ifp->if_softc = sc; 710 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 711 if (sc->sc_hwrev & URTW_HWREV_8187) { 712 sc->sc_init = urtw_init; 713 } else { 714 sc->sc_init = urtw_8187b_init; 715 } 716 ifp->if_ioctl = urtw_ioctl; 717 ifp->if_start = urtw_start; 718 ifp->if_watchdog = urtw_watchdog; 719 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 720 721 if_attach(ifp); 722 ieee80211_ifattach(ifp); 723 724 /* override state transition machine */ 725 sc->sc_newstate = ic->ic_newstate; 726 ic->ic_newstate = urtw_newstate; 727 ieee80211_media_init(ifp, urtw_media_change, ieee80211_media_status); 728 729 #if NBPFILTER > 0 730 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 731 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 732 733 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 734 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 735 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTW_RX_RADIOTAP_PRESENT); 736 737 sc->sc_txtap_len = sizeof sc->sc_txtapu; 738 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 739 sc->sc_txtap.wt_ihdr.it_present = htole32(URTW_TX_RADIOTAP_PRESENT); 740 #endif 741 742 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 743 744 return; 745 fail: 746 printf(": %s failed!\n", __func__); 747 } 748 749 int 750 urtw_detach(struct device *self, int flags) 751 { 752 struct urtw_softc *sc = (struct urtw_softc *)self; 753 struct ifnet *ifp = &sc->sc_ic.ic_if; 754 int s; 755 756 s = splusb(); 757 758 if (timeout_initialized(&sc->scan_to)) 759 timeout_del(&sc->scan_to); 760 if (timeout_initialized(&sc->sc_led_ch)) 761 timeout_del(&sc->sc_led_ch); 762 763 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 764 usb_rem_wait_task(sc->sc_udev, &sc->sc_ledtask); 765 766 usbd_ref_wait(sc->sc_udev); 767 768 if (ifp->if_softc != NULL) { 769 ieee80211_ifdetach(ifp); /* free all nodes */ 770 if_detach(ifp); 771 } 772 773 /* abort and free xfers */ 774 urtw_free_tx_data_list(sc); 775 urtw_free_rx_data_list(sc); 776 urtw_close_pipes(sc); 777 778 splx(s); 779 780 return (0); 781 } 782 783 usbd_status 784 urtw_close_pipes(struct urtw_softc *sc) 785 { 786 usbd_status error = 0; 787 788 if (sc->sc_rxpipe != NULL) { 789 error = usbd_close_pipe(sc->sc_rxpipe); 790 if (error != 0) 791 goto fail; 792 sc->sc_rxpipe = NULL; 793 } 794 if (sc->sc_txpipe_low != NULL) { 795 error = usbd_close_pipe(sc->sc_txpipe_low); 796 if (error != 0) 797 goto fail; 798 sc->sc_txpipe_low = NULL; 799 } 800 if (sc->sc_txpipe_normal != NULL) { 801 error = usbd_close_pipe(sc->sc_txpipe_normal); 802 if (error != 0) 803 goto fail; 804 sc->sc_txpipe_normal = NULL; 805 } 806 fail: 807 return (error); 808 } 809 810 usbd_status 811 urtw_open_pipes(struct urtw_softc *sc) 812 { 813 usbd_status error; 814 815 /* 816 * NB: there is no way to distinguish each pipes so we need to hardcode 817 * pipe numbers 818 */ 819 820 /* tx pipe - low priority packets */ 821 if (sc->sc_hwrev & URTW_HWREV_8187) 822 error = usbd_open_pipe(sc->sc_iface, 0x2, 823 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_low); 824 else 825 error = usbd_open_pipe(sc->sc_iface, 0x6, 826 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_low); 827 if (error != 0) { 828 printf("%s: could not open Tx low pipe: %s\n", 829 sc->sc_dev.dv_xname, usbd_errstr(error)); 830 goto fail; 831 } 832 /* tx pipe - normal priority packets */ 833 if (sc->sc_hwrev & URTW_HWREV_8187) 834 error = usbd_open_pipe(sc->sc_iface, 0x3, 835 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_normal); 836 else 837 error = usbd_open_pipe(sc->sc_iface, 0x7, 838 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_normal); 839 if (error != 0) { 840 printf("%s: could not open Tx normal pipe: %s\n", 841 sc->sc_dev.dv_xname, usbd_errstr(error)); 842 goto fail; 843 } 844 /* rx pipe */ 845 if (sc->sc_hwrev & URTW_HWREV_8187) 846 error = usbd_open_pipe(sc->sc_iface, 0x81, 847 USBD_EXCLUSIVE_USE, &sc->sc_rxpipe); 848 else 849 error = usbd_open_pipe(sc->sc_iface, 0x83, 850 USBD_EXCLUSIVE_USE, &sc->sc_rxpipe); 851 if (error != 0) { 852 printf("%s: could not open Rx pipe: %s\n", 853 sc->sc_dev.dv_xname, usbd_errstr(error)); 854 goto fail; 855 } 856 857 return (0); 858 fail: 859 (void)urtw_close_pipes(sc); 860 return (error); 861 } 862 863 int 864 urtw_alloc_rx_data_list(struct urtw_softc *sc) 865 { 866 int i, error; 867 868 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 869 struct urtw_rx_data *data = &sc->sc_rx_data[i]; 870 871 data->sc = sc; 872 873 data->xfer = usbd_alloc_xfer(sc->sc_udev); 874 if (data->xfer == NULL) { 875 printf("%s: could not allocate rx xfer\n", 876 sc->sc_dev.dv_xname); 877 error = ENOMEM; 878 goto fail; 879 } 880 881 if (usbd_alloc_buffer(data->xfer, URTW_RX_MAXSIZE) == NULL) { 882 printf("%s: could not allocate rx buffer\n", 883 sc->sc_dev.dv_xname); 884 error = ENOMEM; 885 goto fail; 886 } 887 888 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 889 if (data->m == NULL) { 890 printf("%s: could not allocate rx mbuf\n", 891 sc->sc_dev.dv_xname); 892 error = ENOMEM; 893 goto fail; 894 } 895 MCLGET(data->m, M_DONTWAIT); 896 if (!(data->m->m_flags & M_EXT)) { 897 printf("%s: could not allocate rx mbuf cluster\n", 898 sc->sc_dev.dv_xname); 899 error = ENOMEM; 900 goto fail; 901 } 902 data->buf = mtod(data->m, uint8_t *); 903 } 904 905 return (0); 906 907 fail: 908 urtw_free_rx_data_list(sc); 909 return (error); 910 } 911 912 void 913 urtw_free_rx_data_list(struct urtw_softc *sc) 914 { 915 int i; 916 917 /* Make sure no transfers are pending. */ 918 if (sc->sc_rxpipe != NULL) 919 usbd_abort_pipe(sc->sc_rxpipe); 920 921 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 922 struct urtw_rx_data *data = &sc->sc_rx_data[i]; 923 924 if (data->xfer != NULL) { 925 usbd_free_xfer(data->xfer); 926 data->xfer = NULL; 927 } 928 if (data->m != NULL) { 929 m_freem(data->m); 930 data->m = NULL; 931 } 932 } 933 } 934 935 int 936 urtw_alloc_tx_data_list(struct urtw_softc *sc) 937 { 938 int i, error; 939 940 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) { 941 struct urtw_tx_data *data = &sc->sc_tx_data[i]; 942 943 data->sc = sc; 944 data->ni = NULL; 945 946 data->xfer = usbd_alloc_xfer(sc->sc_udev); 947 if (data->xfer == NULL) { 948 printf("%s: could not allocate tx xfer\n", 949 sc->sc_dev.dv_xname); 950 error = ENOMEM; 951 goto fail; 952 } 953 954 data->buf = usbd_alloc_buffer(data->xfer, URTW_TX_MAXSIZE); 955 if (data->buf == NULL) { 956 printf("%s: could not allocate tx buffer\n", 957 sc->sc_dev.dv_xname); 958 error = ENOMEM; 959 goto fail; 960 } 961 962 if (((unsigned long)data->buf) % 4) 963 printf("%s: warn: unaligned buffer %p\n", 964 sc->sc_dev.dv_xname, data->buf); 965 } 966 967 return (0); 968 969 fail: 970 urtw_free_tx_data_list(sc); 971 return (error); 972 } 973 974 void 975 urtw_free_tx_data_list(struct urtw_softc *sc) 976 { 977 struct ieee80211com *ic = &sc->sc_ic; 978 int i; 979 980 /* Make sure no transfers are pending. */ 981 if (sc->sc_txpipe_low != NULL) 982 usbd_abort_pipe(sc->sc_txpipe_low); 983 if (sc->sc_txpipe_normal != NULL) 984 usbd_abort_pipe(sc->sc_txpipe_normal); 985 986 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) { 987 struct urtw_tx_data *data = &sc->sc_tx_data[i]; 988 989 if (data->xfer != NULL) { 990 usbd_free_xfer(data->xfer); 991 data->xfer = NULL; 992 } 993 if (data->ni != NULL) { 994 ieee80211_release_node(ic, data->ni); 995 data->ni = NULL; 996 } 997 } 998 } 999 1000 int 1001 urtw_media_change(struct ifnet *ifp) 1002 { 1003 struct urtw_softc *sc = ifp->if_softc; 1004 int error; 1005 1006 error = ieee80211_media_change(ifp); 1007 if (error != ENETRESET) 1008 return (error); 1009 1010 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1011 (IFF_UP | IFF_RUNNING)) 1012 sc->sc_init(ifp); 1013 1014 return (0); 1015 } 1016 1017 int 1018 urtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1019 { 1020 struct urtw_softc *sc = ic->ic_if.if_softc; 1021 1022 usb_rem_task(sc->sc_udev, &sc->sc_task); 1023 timeout_del(&sc->scan_to); 1024 1025 /* do it in a process context */ 1026 sc->sc_state = nstate; 1027 sc->sc_arg = arg; 1028 usb_add_task(sc->sc_udev, &sc->sc_task); 1029 1030 return (0); 1031 } 1032 1033 usbd_status 1034 urtw_led_init(struct urtw_softc *sc) 1035 { 1036 uint32_t rev; 1037 usbd_status error; 1038 1039 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr); 1040 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev); 1041 if (error != 0) 1042 goto fail; 1043 1044 switch (rev & URTW_EPROM_CID_MASK) { 1045 case URTW_EPROM_CID_ALPHA0: 1046 sc->sc_strategy = URTW_SW_LED_MODE1; 1047 break; 1048 case URTW_EPROM_CID_SERCOMM_PS: 1049 sc->sc_strategy = URTW_SW_LED_MODE3; 1050 break; 1051 case URTW_EPROM_CID_HW_LED: 1052 sc->sc_strategy = URTW_HW_LED; 1053 break; 1054 case URTW_EPROM_CID_RSVD0: 1055 case URTW_EPROM_CID_RSVD1: 1056 default: 1057 sc->sc_strategy = URTW_SW_LED_MODE0; 1058 break; 1059 } 1060 1061 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0; 1062 1063 fail: 1064 return (error); 1065 } 1066 1067 usbd_status 1068 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index, 1069 uint16_t data) 1070 { 1071 usb_device_request_t req; 1072 1073 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1074 req.bRequest = URTW_8187_SETREGS_REQ; 1075 USETW(req.wValue, addr); 1076 USETW(req.wIndex, index); 1077 USETW(req.wLength, sizeof(uint16_t)); 1078 1079 data = htole16(data); 1080 return (usbd_do_request(sc->sc_udev, &req, &data)); 1081 } 1082 1083 usbd_status 1084 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data) 1085 { 1086 int i; 1087 int16_t bit; 1088 uint8_t rlen = 12, wlen = 6; 1089 uint16_t o1, o2, o3, tmp; 1090 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27; 1091 uint32_t mask = 0x80000000, value = 0; 1092 usbd_status error; 1093 1094 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1); 1095 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2); 1096 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3); 1097 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | 0xf); 1098 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | 0xf); 1099 o1 &= ~0xf; 1100 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN); 1101 DELAY(5); 1102 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1); 1103 DELAY(5); 1104 1105 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) { 1106 bit = ((d2w & mask) != 0) ? 1 : 0; 1107 1108 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 1109 DELAY(2); 1110 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1111 URTW_BB_HOST_BANG_CLK); 1112 DELAY(2); 1113 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1114 URTW_BB_HOST_BANG_CLK); 1115 DELAY(2); 1116 mask = mask >> 1; 1117 if (i == 2) 1118 break; 1119 bit = ((d2w & mask) != 0) ? 1 : 0; 1120 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1121 URTW_BB_HOST_BANG_CLK); 1122 DELAY(2); 1123 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1124 URTW_BB_HOST_BANG_CLK); 1125 DELAY(2); 1126 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 1127 DELAY(1); 1128 } 1129 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW | 1130 URTW_BB_HOST_BANG_CLK); 1131 DELAY(2); 1132 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW); 1133 DELAY(2); 1134 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW); 1135 DELAY(2); 1136 1137 mask = 0x800; 1138 for (i = 0; i < rlen; i++, mask = mask >> 1) { 1139 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1140 o1 | URTW_BB_HOST_BANG_RW); 1141 DELAY(2); 1142 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1143 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1144 DELAY(2); 1145 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1146 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1147 DELAY(2); 1148 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1149 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1150 DELAY(2); 1151 1152 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp); 1153 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0); 1154 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1155 o1 | URTW_BB_HOST_BANG_RW); 1156 DELAY(2); 1157 } 1158 1159 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN | 1160 URTW_BB_HOST_BANG_RW); 1161 DELAY(2); 1162 1163 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2); 1164 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3); 1165 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x3a0); 1166 1167 if (data != NULL) 1168 *data = value; 1169 fail: 1170 return (error); 1171 } 1172 1173 usbd_status 1174 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data) 1175 { 1176 uint16_t d80, d82, d84; 1177 usbd_status error; 1178 1179 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80); 1180 d80 &= 0xfff3; 1181 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82); 1182 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84); 1183 d84 &= 0xfff0; 1184 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | 0x0007); 1185 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | 0x0007); 1186 DELAY(10); 1187 1188 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1189 DELAY(2); 1190 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80); 1191 DELAY(10); 1192 1193 error = urtw_8225_write_s16(sc, addr, 0x8225, data); 1194 if (error != 0) 1195 goto fail; 1196 1197 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1198 DELAY(10); 1199 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1200 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84); 1201 usbd_delay_ms(sc->sc_udev, 2); 1202 fail: 1203 return (error); 1204 } 1205 1206 usbd_status 1207 urtw_8225_isv2(struct urtw_softc *sc, int *ret) 1208 { 1209 uint32_t data; 1210 usbd_status error; 1211 1212 *ret = 1; 1213 1214 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0080); 1215 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x0080); 1216 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x0080); 1217 usbd_delay_ms(sc->sc_udev, 500); 1218 1219 urtw_8225_write(sc, 0x0, 0x1b7); 1220 1221 error = urtw_8225_read(sc, 0x8, &data); 1222 if (error != 0) 1223 goto fail; 1224 if (data != 0x588) 1225 *ret = 0; 1226 else { 1227 error = urtw_8225_read(sc, 0x9, &data); 1228 if (error != 0) 1229 goto fail; 1230 if (data != 0x700) 1231 *ret = 0; 1232 } 1233 1234 urtw_8225_write(sc, 0x0, 0xb7); 1235 fail: 1236 return (error); 1237 } 1238 1239 usbd_status 1240 urtw_get_rfchip(struct urtw_softc *sc) 1241 { 1242 struct urtw_rf *rf = &sc->sc_rf; 1243 int ret; 1244 uint32_t data; 1245 usbd_status error; 1246 1247 rf->rf_sc = sc; 1248 1249 if (sc->sc_hwrev & URTW_HWREV_8187) { 1250 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data); 1251 if (error != 0) 1252 goto fail; 1253 switch (data & 0xff) { 1254 case URTW_EPROM_RFCHIPID_RTL8225U: 1255 error = urtw_8225_isv2(sc, &ret); 1256 if (error != 0) 1257 goto fail; 1258 if (ret == 0) { 1259 rf->init = urtw_8225_rf_init; 1260 rf->set_chan = urtw_8225_rf_set_chan; 1261 rf->set_sens = urtw_8225_rf_set_sens; 1262 printf(", RFv1"); 1263 } else { 1264 rf->init = urtw_8225v2_rf_init; 1265 rf->set_chan = urtw_8225v2_rf_set_chan; 1266 rf->set_sens = NULL; 1267 printf(", RFv2"); 1268 } 1269 break; 1270 default: 1271 goto fail; 1272 } 1273 } else { 1274 rf->init = urtw_8225v2_b_rf_init; 1275 rf->set_chan = urtw_8225v2_b_rf_set_chan; 1276 rf->set_sens = NULL; 1277 } 1278 1279 rf->max_sens = URTW_8225_RF_MAX_SENS; 1280 rf->sens = URTW_8225_RF_DEF_SENS; 1281 1282 return (0); 1283 1284 fail: 1285 printf("unsupported RF chip %d", data & 0xff); 1286 return (error); 1287 } 1288 1289 usbd_status 1290 urtw_get_txpwr(struct urtw_softc *sc) 1291 { 1292 int i, j; 1293 uint32_t data; 1294 usbd_status error; 1295 1296 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data); 1297 if (error != 0) 1298 goto fail; 1299 sc->sc_txpwr_cck_base = data & 0xf; 1300 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf; 1301 1302 for (i = 1, j = 0; i < 6; i += 2, j++) { 1303 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data); 1304 if (error != 0) 1305 goto fail; 1306 sc->sc_txpwr_cck[i] = data & 0xf; 1307 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8; 1308 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4; 1309 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12; 1310 } 1311 for (i = 1, j = 0; i < 4; i += 2, j++) { 1312 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data); 1313 if (error != 0) 1314 goto fail; 1315 sc->sc_txpwr_cck[i + 6] = data & 0xf; 1316 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8; 1317 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4; 1318 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12; 1319 } 1320 if (sc->sc_hwrev & URTW_HWREV_8187) { 1321 for (i = 1, j = 0; i < 4; i += 2, j++) { 1322 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j, 1323 &data); 1324 if (error != 0) 1325 goto fail; 1326 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf; 1327 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8; 1328 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4; 1329 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = 1330 (data & 0xf000) >> 12; 1331 } 1332 } else { 1333 /* Channel 11. */ 1334 error = urtw_eprom_read32(sc, 0x1b, &data); 1335 if (error != 0) 1336 goto fail; 1337 sc->sc_txpwr_cck[11] = data & 0xf; 1338 sc->sc_txpwr_ofdm[11] = (data & 0xf0) >> 4; 1339 1340 /* Channel 12. */ 1341 error = urtw_eprom_read32(sc, 0xa, &data); 1342 if (error != 0) 1343 goto fail; 1344 sc->sc_txpwr_cck[12] = data & 0xf; 1345 sc->sc_txpwr_ofdm[12] = (data & 0xf0) >> 4; 1346 1347 /* Channel 13, 14. */ 1348 error = urtw_eprom_read32(sc, 0x1c, &data); 1349 if (error != 0) 1350 goto fail; 1351 sc->sc_txpwr_cck[13] = data & 0xf; 1352 sc->sc_txpwr_ofdm[13] = (data & 0xf0) >> 4; 1353 sc->sc_txpwr_cck[14] = (data & 0xf00) >> 8; 1354 sc->sc_txpwr_ofdm[14] = (data & 0xf000) >> 12; 1355 } 1356 fail: 1357 return (error); 1358 } 1359 1360 usbd_status 1361 urtw_get_macaddr(struct urtw_softc *sc) 1362 { 1363 struct ieee80211com *ic = &sc->sc_ic; 1364 usbd_status error; 1365 uint32_t data; 1366 1367 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data); 1368 if (error != 0) 1369 goto fail; 1370 ic->ic_myaddr[0] = data & 0xff; 1371 ic->ic_myaddr[1] = (data & 0xff00) >> 8; 1372 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data); 1373 if (error != 0) 1374 goto fail; 1375 ic->ic_myaddr[2] = data & 0xff; 1376 ic->ic_myaddr[3] = (data & 0xff00) >> 8; 1377 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data); 1378 if (error != 0) 1379 goto fail; 1380 ic->ic_myaddr[4] = data & 0xff; 1381 ic->ic_myaddr[5] = (data & 0xff00) >> 8; 1382 fail: 1383 return (error); 1384 } 1385 1386 usbd_status 1387 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data) 1388 { 1389 #define URTW_READCMD_LEN 3 1390 int addrlen, i; 1391 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 }; 1392 usbd_status error; 1393 1394 /* NB: make sure the buffer is initialized */ 1395 *data = 0; 1396 1397 /* enable EPROM programming */ 1398 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE); 1399 DELAY(URTW_EPROM_DELAY); 1400 1401 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE); 1402 if (error != 0) 1403 goto fail; 1404 error = urtw_eprom_ck(sc); 1405 if (error != 0) 1406 goto fail; 1407 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN); 1408 if (error != 0) 1409 goto fail; 1410 if (sc->sc_epromtype == URTW_EEPROM_93C56) { 1411 addrlen = 8; 1412 addrstr[0] = addr & (1 << 7); 1413 addrstr[1] = addr & (1 << 6); 1414 addrstr[2] = addr & (1 << 5); 1415 addrstr[3] = addr & (1 << 4); 1416 addrstr[4] = addr & (1 << 3); 1417 addrstr[5] = addr & (1 << 2); 1418 addrstr[6] = addr & (1 << 1); 1419 addrstr[7] = addr & (1 << 0); 1420 } else { 1421 addrlen=6; 1422 addrstr[0] = addr & (1 << 5); 1423 addrstr[1] = addr & (1 << 4); 1424 addrstr[2] = addr & (1 << 3); 1425 addrstr[3] = addr & (1 << 2); 1426 addrstr[4] = addr & (1 << 1); 1427 addrstr[5] = addr & (1 << 0); 1428 } 1429 error = urtw_eprom_sendbits(sc, addrstr, addrlen); 1430 if (error != 0) 1431 goto fail; 1432 1433 error = urtw_eprom_writebit(sc, 0); 1434 if (error != 0) 1435 goto fail; 1436 1437 for (i = 0; i < 16; i++) { 1438 error = urtw_eprom_ck(sc); 1439 if (error != 0) 1440 goto fail; 1441 error = urtw_eprom_readbit(sc, &data16); 1442 if (error != 0) 1443 goto fail; 1444 1445 (*data) |= (data16 << (15 - i)); 1446 } 1447 1448 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE); 1449 if (error != 0) 1450 goto fail; 1451 error = urtw_eprom_ck(sc); 1452 if (error != 0) 1453 goto fail; 1454 1455 /* now disable EPROM programming */ 1456 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE); 1457 fail: 1458 return (error); 1459 #undef URTW_READCMD_LEN 1460 } 1461 1462 usbd_status 1463 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data) 1464 { 1465 uint8_t data8; 1466 usbd_status error; 1467 1468 urtw_read8_m(sc, URTW_EPROM_CMD, &data8); 1469 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0; 1470 DELAY(URTW_EPROM_DELAY); 1471 1472 fail: 1473 return (error); 1474 } 1475 1476 usbd_status 1477 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen) 1478 { 1479 int i = 0; 1480 usbd_status error = 0; 1481 1482 for (i = 0; i < buflen; i++) { 1483 error = urtw_eprom_writebit(sc, buf[i]); 1484 if (error != 0) 1485 goto fail; 1486 error = urtw_eprom_ck(sc); 1487 if (error != 0) 1488 goto fail; 1489 } 1490 fail: 1491 return (error); 1492 } 1493 1494 usbd_status 1495 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit) 1496 { 1497 uint8_t data; 1498 usbd_status error; 1499 1500 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1501 if (bit != 0) 1502 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT); 1503 else 1504 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT); 1505 DELAY(URTW_EPROM_DELAY); 1506 fail: 1507 return (error); 1508 } 1509 1510 usbd_status 1511 urtw_eprom_ck(struct urtw_softc *sc) 1512 { 1513 uint8_t data; 1514 usbd_status error; 1515 1516 /* masking */ 1517 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1518 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK); 1519 DELAY(URTW_EPROM_DELAY); 1520 /* unmasking */ 1521 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1522 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK); 1523 DELAY(URTW_EPROM_DELAY); 1524 fail: 1525 return (error); 1526 } 1527 1528 usbd_status 1529 urtw_eprom_cs(struct urtw_softc *sc, int able) 1530 { 1531 uint8_t data; 1532 usbd_status error; 1533 1534 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1535 if (able == URTW_EPROM_ENABLE) 1536 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS); 1537 else 1538 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS); 1539 DELAY(URTW_EPROM_DELAY); 1540 fail: 1541 return (error); 1542 } 1543 1544 usbd_status 1545 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data, uint8_t idx) 1546 { 1547 usb_device_request_t req; 1548 usbd_status error; 1549 1550 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1551 req.bRequest = URTW_8187_GETREGS_REQ; 1552 USETW(req.wValue, val | 0xff00); 1553 USETW(req.wIndex, idx & 0x03); 1554 USETW(req.wLength, sizeof(uint8_t)); 1555 1556 error = usbd_do_request(sc->sc_udev, &req, data); 1557 return (error); 1558 } 1559 1560 usbd_status 1561 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data) 1562 { 1563 usb_device_request_t req; 1564 usbd_status error; 1565 1566 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1567 req.bRequest = URTW_8187_GETREGS_REQ; 1568 USETW(req.wValue, val | 0xfe00); 1569 USETW(req.wIndex, 0); 1570 USETW(req.wLength, sizeof(uint8_t)); 1571 1572 error = usbd_do_request(sc->sc_udev, &req, data); 1573 return (error); 1574 } 1575 1576 usbd_status 1577 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data, uint8_t idx) 1578 { 1579 usb_device_request_t req; 1580 usbd_status error; 1581 1582 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1583 req.bRequest = URTW_8187_GETREGS_REQ; 1584 USETW(req.wValue, val | 0xff00); 1585 USETW(req.wIndex, idx & 0x03); 1586 USETW(req.wLength, sizeof(uint16_t)); 1587 1588 error = usbd_do_request(sc->sc_udev, &req, data); 1589 *data = letoh16(*data); 1590 return (error); 1591 } 1592 1593 usbd_status 1594 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data, uint8_t idx) 1595 { 1596 usb_device_request_t req; 1597 usbd_status error; 1598 1599 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1600 req.bRequest = URTW_8187_GETREGS_REQ; 1601 USETW(req.wValue, val | 0xff00); 1602 USETW(req.wIndex, idx & 0x03); 1603 USETW(req.wLength, sizeof(uint32_t)); 1604 1605 error = usbd_do_request(sc->sc_udev, &req, data); 1606 *data = letoh32(*data); 1607 return (error); 1608 } 1609 1610 usbd_status 1611 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data, uint8_t idx) 1612 { 1613 usb_device_request_t req; 1614 1615 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1616 req.bRequest = URTW_8187_SETREGS_REQ; 1617 USETW(req.wValue, val | 0xff00); 1618 USETW(req.wIndex, idx & 0x03); 1619 USETW(req.wLength, sizeof(uint8_t)); 1620 1621 return (usbd_do_request(sc->sc_udev, &req, &data)); 1622 } 1623 1624 usbd_status 1625 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data) 1626 { 1627 usb_device_request_t req; 1628 1629 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1630 req.bRequest = URTW_8187_SETREGS_REQ; 1631 USETW(req.wValue, val | 0xfe00); 1632 USETW(req.wIndex, 0); 1633 USETW(req.wLength, sizeof(uint8_t)); 1634 1635 return (usbd_do_request(sc->sc_udev, &req, &data)); 1636 } 1637 1638 usbd_status 1639 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data, uint8_t idx) 1640 { 1641 usb_device_request_t req; 1642 1643 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1644 req.bRequest = URTW_8187_SETREGS_REQ; 1645 USETW(req.wValue, val | 0xff00); 1646 USETW(req.wIndex, idx & 0x03); 1647 USETW(req.wLength, sizeof(uint16_t)); 1648 1649 data = htole16(data); 1650 return (usbd_do_request(sc->sc_udev, &req, &data)); 1651 } 1652 1653 usbd_status 1654 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data, uint8_t idx) 1655 { 1656 usb_device_request_t req; 1657 1658 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1659 req.bRequest = URTW_8187_SETREGS_REQ; 1660 USETW(req.wValue, val | 0xff00); 1661 USETW(req.wIndex, idx & 0x03); 1662 USETW(req.wLength, sizeof(uint32_t)); 1663 1664 data = htole32(data); 1665 return (usbd_do_request(sc->sc_udev, &req, &data)); 1666 } 1667 1668 static usbd_status 1669 urtw_set_mode(struct urtw_softc *sc, uint32_t mode) 1670 { 1671 uint8_t data; 1672 usbd_status error; 1673 1674 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1675 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT); 1676 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK); 1677 urtw_write8_m(sc, URTW_EPROM_CMD, data); 1678 fail: 1679 return (error); 1680 } 1681 1682 usbd_status 1683 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val) 1684 { 1685 uint8_t data; 1686 usbd_status error; 1687 1688 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1689 if (error) 1690 goto fail; 1691 1692 urtw_read8_m(sc, URTW_CONFIG3, &data); 1693 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 1694 urtw_write32_m(sc, URTW_ANAPARAM, val); 1695 urtw_read8_m(sc, URTW_CONFIG3, &data); 1696 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 1697 1698 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1699 if (error) 1700 goto fail; 1701 fail: 1702 return (error); 1703 } 1704 1705 usbd_status 1706 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val) 1707 { 1708 uint8_t data; 1709 usbd_status error; 1710 1711 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1712 if (error) 1713 goto fail; 1714 1715 urtw_read8_m(sc, URTW_CONFIG3, &data); 1716 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 1717 urtw_write32_m(sc, URTW_ANAPARAM2, val); 1718 urtw_read8_m(sc, URTW_CONFIG3, &data); 1719 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 1720 1721 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1722 if (error) 1723 goto fail; 1724 fail: 1725 return (error); 1726 } 1727 1728 usbd_status 1729 urtw_intr_disable(struct urtw_softc *sc) 1730 { 1731 usbd_status error; 1732 1733 urtw_write16_m(sc, URTW_INTR_MASK, 0); 1734 fail: 1735 return (error); 1736 } 1737 1738 usbd_status 1739 urtw_reset(struct urtw_softc *sc) 1740 { 1741 uint8_t data; 1742 usbd_status error; 1743 1744 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 1745 if (error) 1746 goto fail; 1747 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 1748 if (error) 1749 goto fail; 1750 1751 error = urtw_intr_disable(sc); 1752 if (error) 1753 goto fail; 1754 usbd_delay_ms(sc->sc_udev, 100); 1755 1756 error = urtw_write8e(sc, 0x18, 0x10); 1757 if (error != 0) 1758 goto fail; 1759 error = urtw_write8e(sc, 0x18, 0x11); 1760 if (error != 0) 1761 goto fail; 1762 error = urtw_write8e(sc, 0x18, 0x00); 1763 if (error != 0) 1764 goto fail; 1765 usbd_delay_ms(sc->sc_udev, 100); 1766 1767 urtw_read8_m(sc, URTW_CMD, &data); 1768 data = (data & 2) | URTW_CMD_RST; 1769 urtw_write8_m(sc, URTW_CMD, data); 1770 usbd_delay_ms(sc->sc_udev, 100); 1771 1772 urtw_read8_m(sc, URTW_CMD, &data); 1773 if (data & URTW_CMD_RST) { 1774 printf("%s: reset timeout\n", sc->sc_dev.dv_xname); 1775 goto fail; 1776 } 1777 1778 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD); 1779 if (error) 1780 goto fail; 1781 usbd_delay_ms(sc->sc_udev, 100); 1782 1783 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 1784 if (error) 1785 goto fail; 1786 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 1787 if (error) 1788 goto fail; 1789 fail: 1790 return (error); 1791 } 1792 1793 usbd_status 1794 urtw_led_on(struct urtw_softc *sc, int type) 1795 { 1796 usbd_status error = 0; 1797 1798 if (type == URTW_LED_GPIO) { 1799 switch (sc->sc_gpio_ledpin) { 1800 case URTW_LED_PIN_GPIO0: 1801 urtw_write8_m(sc, URTW_GPIO, 0x01); 1802 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00); 1803 break; 1804 default: 1805 break; 1806 } 1807 } 1808 1809 sc->sc_gpio_ledon = 1; 1810 fail: 1811 return (error); 1812 } 1813 1814 static usbd_status 1815 urtw_led_off(struct urtw_softc *sc, int type) 1816 { 1817 usbd_status error = 0; 1818 1819 if (type == URTW_LED_GPIO) { 1820 switch (sc->sc_gpio_ledpin) { 1821 case URTW_LED_PIN_GPIO0: 1822 urtw_write8_m(sc, URTW_GPIO, 0x01); 1823 urtw_write8_m(sc, URTW_GP_ENABLE, 0x01); 1824 break; 1825 default: 1826 break; 1827 } 1828 } 1829 1830 sc->sc_gpio_ledon = 0; 1831 1832 fail: 1833 return (error); 1834 } 1835 1836 usbd_status 1837 urtw_led_mode0(struct urtw_softc *sc, int mode) 1838 { 1839 struct timeval t; 1840 1841 switch (mode) { 1842 case URTW_LED_CTL_POWER_ON: 1843 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK; 1844 break; 1845 case URTW_LED_CTL_TX: 1846 if (sc->sc_gpio_ledinprogress == 1) 1847 return (0); 1848 1849 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL; 1850 sc->sc_gpio_blinktime = 2; 1851 break; 1852 case URTW_LED_CTL_LINK: 1853 sc->sc_gpio_ledstate = URTW_LED_ON; 1854 break; 1855 default: 1856 break; 1857 } 1858 1859 switch (sc->sc_gpio_ledstate) { 1860 case URTW_LED_ON: 1861 if (sc->sc_gpio_ledinprogress != 0) 1862 break; 1863 urtw_led_on(sc, URTW_LED_GPIO); 1864 break; 1865 case URTW_LED_BLINK_NORMAL: 1866 if (sc->sc_gpio_ledinprogress != 0) 1867 break; 1868 sc->sc_gpio_ledinprogress = 1; 1869 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ? 1870 URTW_LED_OFF : URTW_LED_ON; 1871 t.tv_sec = 0; 1872 t.tv_usec = 100 * 1000L; 1873 if (!usbd_is_dying(sc->sc_udev)) 1874 timeout_add(&sc->sc_led_ch, tvtohz(&t)); 1875 break; 1876 case URTW_LED_POWER_ON_BLINK: 1877 urtw_led_on(sc, URTW_LED_GPIO); 1878 usbd_delay_ms(sc->sc_udev, 100); 1879 urtw_led_off(sc, URTW_LED_GPIO); 1880 break; 1881 default: 1882 break; 1883 } 1884 return (0); 1885 } 1886 1887 usbd_status 1888 urtw_led_mode1(struct urtw_softc *sc, int mode) 1889 { 1890 return (USBD_INVAL); 1891 } 1892 1893 usbd_status 1894 urtw_led_mode2(struct urtw_softc *sc, int mode) 1895 { 1896 return (USBD_INVAL); 1897 } 1898 1899 usbd_status 1900 urtw_led_mode3(struct urtw_softc *sc, int mode) 1901 { 1902 return (USBD_INVAL); 1903 } 1904 1905 void 1906 urtw_ledusbtask(void *arg) 1907 { 1908 struct urtw_softc *sc = arg; 1909 1910 if (sc->sc_strategy != URTW_SW_LED_MODE0) 1911 return; 1912 1913 urtw_led_blink(sc); 1914 } 1915 1916 void 1917 urtw_ledtask(void *arg) 1918 { 1919 struct urtw_softc *sc = arg; 1920 1921 /* 1922 * NB: to change a status of the led we need at least a sleep so we 1923 * can't do it here 1924 */ 1925 usb_add_task(sc->sc_udev, &sc->sc_ledtask); 1926 } 1927 1928 usbd_status 1929 urtw_led_ctl(struct urtw_softc *sc, int mode) 1930 { 1931 usbd_status error = 0; 1932 1933 switch (sc->sc_strategy) { 1934 case URTW_SW_LED_MODE0: 1935 error = urtw_led_mode0(sc, mode); 1936 break; 1937 case URTW_SW_LED_MODE1: 1938 error = urtw_led_mode1(sc, mode); 1939 break; 1940 case URTW_SW_LED_MODE2: 1941 error = urtw_led_mode2(sc, mode); 1942 break; 1943 case URTW_SW_LED_MODE3: 1944 error = urtw_led_mode3(sc, mode); 1945 break; 1946 default: 1947 break; 1948 } 1949 1950 return (error); 1951 } 1952 1953 usbd_status 1954 urtw_led_blink(struct urtw_softc *sc) 1955 { 1956 struct timeval t; 1957 uint8_t ing = 0; 1958 usbd_status error; 1959 1960 if (sc->sc_gpio_blinkstate == URTW_LED_ON) 1961 error = urtw_led_on(sc, URTW_LED_GPIO); 1962 else 1963 error = urtw_led_off(sc, URTW_LED_GPIO); 1964 sc->sc_gpio_blinktime--; 1965 if (sc->sc_gpio_blinktime == 0) 1966 ing = 1; 1967 else { 1968 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL && 1969 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY && 1970 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3) 1971 ing = 1; 1972 } 1973 if (ing == 1) { 1974 if (sc->sc_gpio_ledstate == URTW_LED_ON && 1975 sc->sc_gpio_ledon == 0) 1976 error = urtw_led_on(sc, URTW_LED_GPIO); 1977 else if (sc->sc_gpio_ledstate == URTW_LED_OFF && 1978 sc->sc_gpio_ledon == 1) 1979 error = urtw_led_off(sc, URTW_LED_GPIO); 1980 1981 sc->sc_gpio_blinktime = 0; 1982 sc->sc_gpio_ledinprogress = 0; 1983 return (0); 1984 } 1985 1986 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ? 1987 URTW_LED_ON : URTW_LED_OFF; 1988 1989 switch (sc->sc_gpio_ledstate) { 1990 case URTW_LED_BLINK_NORMAL: 1991 t.tv_sec = 0; 1992 t.tv_usec = 100 * 1000L; 1993 if (!usbd_is_dying(sc->sc_udev)) 1994 timeout_add(&sc->sc_led_ch, tvtohz(&t)); 1995 break; 1996 default: 1997 break; 1998 } 1999 return (0); 2000 } 2001 2002 usbd_status 2003 urtw_update_msr(struct urtw_softc *sc) 2004 { 2005 struct ieee80211com *ic = &sc->sc_ic; 2006 uint8_t data; 2007 usbd_status error; 2008 2009 urtw_read8_m(sc, URTW_MSR, &data); 2010 data &= ~URTW_MSR_LINK_MASK; 2011 2012 /* Should always be set. */ 2013 if (sc->sc_hwrev & URTW_HWREV_8187B) 2014 data |= URTW_MSR_LINK_ENEDCA; 2015 2016 if (sc->sc_state == IEEE80211_S_RUN) { 2017 switch (ic->ic_opmode) { 2018 case IEEE80211_M_STA: 2019 case IEEE80211_M_MONITOR: 2020 data |= URTW_MSR_LINK_STA; 2021 break; 2022 default: 2023 break; 2024 } 2025 } else 2026 data |= URTW_MSR_LINK_NONE; 2027 2028 urtw_write8_m(sc, URTW_MSR, data); 2029 fail: 2030 return (error); 2031 } 2032 2033 uint16_t 2034 urtw_rate2rtl(int rate) 2035 { 2036 int i; 2037 2038 for (i = 0; i < nitems(urtw_ratetable); i++) { 2039 if (rate == urtw_ratetable[i].reg) 2040 return (urtw_ratetable[i].val); 2041 } 2042 2043 return (3); 2044 } 2045 2046 uint16_t 2047 urtw_rtl2rate(int rate) 2048 { 2049 int i; 2050 2051 for (i = 0; i < nitems(urtw_ratetable); i++) { 2052 if (rate == urtw_ratetable[i].val) 2053 return (urtw_ratetable[i].reg); 2054 } 2055 2056 return (0); 2057 } 2058 2059 usbd_status 2060 urtw_set_rate(struct urtw_softc *sc) 2061 { 2062 int i, basic_rate, min_rr_rate, max_rr_rate; 2063 uint16_t data; 2064 usbd_status error; 2065 2066 basic_rate = urtw_rate2rtl(48); 2067 min_rr_rate = urtw_rate2rtl(12); 2068 max_rr_rate = urtw_rate2rtl(48); 2069 2070 urtw_write8_m(sc, URTW_RESP_RATE, 2071 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT | 2072 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT); 2073 2074 urtw_read16_m(sc, URTW_8187_BRSR, &data); 2075 data &= ~URTW_BRSR_MBR_8185; 2076 2077 for (i = 0; i <= basic_rate; i++) 2078 data |= (1 << i); 2079 2080 urtw_write16_m(sc, URTW_8187_BRSR, data); 2081 fail: 2082 return (error); 2083 } 2084 2085 usbd_status 2086 urtw_intr_enable(struct urtw_softc *sc) 2087 { 2088 usbd_status error; 2089 2090 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff); 2091 fail: 2092 return (error); 2093 } 2094 2095 usbd_status 2096 urtw_rx_setconf(struct urtw_softc *sc) 2097 { 2098 struct ifnet *ifp = &sc->sc_ic.ic_if; 2099 struct ieee80211com *ic = &sc->sc_ic; 2100 uint32_t data; 2101 usbd_status error; 2102 2103 urtw_read32_m(sc, URTW_RX, &data); 2104 data = data &~ URTW_RX_FILTER_MASK; 2105 #if 0 2106 data = data | URTW_RX_FILTER_CTL; 2107 #endif 2108 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA; 2109 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST; 2110 2111 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2112 data = data | URTW_RX_FILTER_ICVERR; 2113 data = data | URTW_RX_FILTER_PWR; 2114 } 2115 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR) 2116 data = data | URTW_RX_FILTER_CRCERR; 2117 2118 if (ic->ic_opmode == IEEE80211_M_MONITOR || 2119 (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC))) { 2120 data = data | URTW_RX_FILTER_ALLMAC; 2121 } else { 2122 data = data | URTW_RX_FILTER_NICMAC; 2123 data = data | URTW_RX_CHECK_BSSID; 2124 } 2125 2126 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK; 2127 data = data | URTW_RX_FIFO_THRESHOLD_NONE | URTW_RX_AUTORESETPHY; 2128 data = data &~ URTW_MAX_RX_DMA_MASK; 2129 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT; 2130 2131 urtw_write32_m(sc, URTW_RX, data); 2132 fail: 2133 return (error); 2134 } 2135 2136 usbd_status 2137 urtw_rx_enable(struct urtw_softc *sc) 2138 { 2139 int i; 2140 struct urtw_rx_data *rx_data; 2141 uint8_t data; 2142 usbd_status error; 2143 2144 /* 2145 * Start up the receive pipe. 2146 */ 2147 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 2148 rx_data = &sc->sc_rx_data[i]; 2149 2150 usbd_setup_xfer(rx_data->xfer, sc->sc_rxpipe, rx_data, 2151 rx_data->buf, MCLBYTES, USBD_SHORT_XFER_OK, 2152 USBD_NO_TIMEOUT, urtw_rxeof); 2153 error = usbd_transfer(rx_data->xfer); 2154 if (error != USBD_IN_PROGRESS && error != 0) { 2155 printf("%s: could not queue Rx transfer\n", 2156 sc->sc_dev.dv_xname); 2157 goto fail; 2158 } 2159 } 2160 2161 error = urtw_rx_setconf(sc); 2162 if (error != 0) 2163 goto fail; 2164 2165 urtw_read8_m(sc, URTW_CMD, &data); 2166 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE); 2167 fail: 2168 return (error); 2169 } 2170 2171 usbd_status 2172 urtw_tx_enable(struct urtw_softc *sc) 2173 { 2174 uint8_t data8; 2175 uint32_t data; 2176 usbd_status error; 2177 2178 if (sc->sc_hwrev & URTW_HWREV_8187) { 2179 urtw_read8_m(sc, URTW_CW_CONF, &data8); 2180 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | 2181 URTW_CW_CONF_PERPACKET_RETRY); 2182 urtw_write8_m(sc, URTW_CW_CONF, data8); 2183 2184 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 2185 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN; 2186 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL; 2187 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT; 2188 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 2189 2190 urtw_read32_m(sc, URTW_TX_CONF, &data); 2191 data &= ~URTW_TX_LOOPBACK_MASK; 2192 data |= URTW_TX_LOOPBACK_NONE; 2193 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 2194 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT; 2195 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT; 2196 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 2197 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW; 2198 data &= ~URTW_TX_SWPLCPLEN; 2199 data |= URTW_TX_NOICV; 2200 urtw_write32_m(sc, URTW_TX_CONF, data); 2201 } else { 2202 data = URTW_TX_DURPROCMODE | URTW_TX_DISREQQSIZE | 2203 URTW_TX_MXDMA_2048 | URTW_TX_SHORTRETRY | 2204 URTW_TX_LONGRETRY; 2205 urtw_write32_m(sc, URTW_TX_CONF, data); 2206 } 2207 2208 urtw_read8_m(sc, URTW_CMD, &data8); 2209 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE); 2210 fail: 2211 return (error); 2212 } 2213 2214 int 2215 urtw_init(struct ifnet *ifp) 2216 { 2217 struct urtw_softc *sc = ifp->if_softc; 2218 struct urtw_rf *rf = &sc->sc_rf; 2219 struct ieee80211com *ic = &sc->sc_ic; 2220 usbd_status error; 2221 int ret; 2222 2223 urtw_stop(ifp, 0); 2224 2225 error = urtw_reset(sc); 2226 if (error) 2227 goto fail; 2228 2229 urtw_write8_m(sc, 0x85, 0); 2230 urtw_write8_m(sc, URTW_GPIO, 0); 2231 2232 /* for led */ 2233 urtw_write8_m(sc, 0x85, 4); 2234 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON); 2235 if (error != 0) 2236 goto fail; 2237 2238 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2239 if (error) 2240 goto fail; 2241 2242 /* applying MAC address again. */ 2243 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 2244 error = urtw_set_macaddr(sc, ic->ic_myaddr); 2245 if (error) 2246 goto fail; 2247 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2248 if (error) 2249 goto fail; 2250 2251 error = urtw_update_msr(sc); 2252 if (error) 2253 goto fail; 2254 2255 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0); 2256 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 2257 urtw_write8_m(sc, URTW_RATE_FALLBACK, 0x81); 2258 error = urtw_set_rate(sc); 2259 if (error != 0) 2260 goto fail; 2261 2262 error = rf->init(rf); 2263 if (error != 0) 2264 goto fail; 2265 if (rf->set_sens != NULL) 2266 rf->set_sens(rf); 2267 2268 urtw_write16_m(sc, 0x5e, 1); 2269 urtw_write16_m(sc, 0xfe, 0x10); 2270 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80); 2271 urtw_write8_m(sc, 0xff, 0x60); 2272 urtw_write16_m(sc, 0x5e, 0); 2273 urtw_write8_m(sc, 0x85, 4); 2274 2275 error = urtw_intr_enable(sc); 2276 if (error != 0) 2277 goto fail; 2278 2279 /* reset softc variables */ 2280 sc->sc_txidx = sc->sc_tx_low_queued = sc->sc_tx_normal_queued = 0; 2281 sc->sc_txtimer = 0; 2282 2283 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 2284 error = urtw_open_pipes(sc); 2285 if (error != 0) 2286 goto fail; 2287 ret = urtw_alloc_rx_data_list(sc); 2288 if (error != 0) 2289 goto fail; 2290 ret = urtw_alloc_tx_data_list(sc); 2291 if (error != 0) 2292 goto fail; 2293 sc->sc_flags |= URTW_INIT_ONCE; 2294 } 2295 2296 error = urtw_rx_enable(sc); 2297 if (error != 0) 2298 goto fail; 2299 error = urtw_tx_enable(sc); 2300 if (error != 0) 2301 goto fail; 2302 2303 ifq_clr_oactive(&ifp->if_snd); 2304 ifp->if_flags |= IFF_RUNNING; 2305 2306 ifp->if_timer = 1; 2307 2308 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2309 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2310 else 2311 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2312 2313 return (0); 2314 fail: 2315 return (error); 2316 } 2317 2318 void 2319 urtw_set_multi(struct urtw_softc *sc) 2320 { 2321 struct arpcom *ac = &sc->sc_ic.ic_ac; 2322 struct ifnet *ifp = &ac->ac_if; 2323 2324 /* 2325 * XXX don't know how to set a device. Lack of docs. Just try to set 2326 * IFF_ALLMULTI flag here. 2327 */ 2328 ifp->if_flags |= IFF_ALLMULTI; 2329 } 2330 2331 int 2332 urtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2333 { 2334 struct urtw_softc *sc = ifp->if_softc; 2335 struct ieee80211com *ic = &sc->sc_ic; 2336 struct ifreq *ifr; 2337 int s, error = 0; 2338 2339 if (usbd_is_dying(sc->sc_udev)) 2340 return (ENXIO); 2341 2342 usbd_ref_incr(sc->sc_udev); 2343 2344 s = splnet(); 2345 2346 switch (cmd) { 2347 case SIOCSIFADDR: 2348 ifp->if_flags |= IFF_UP; 2349 /* FALLTHROUGH */ 2350 case SIOCSIFFLAGS: 2351 if (ifp->if_flags & IFF_UP) { 2352 /* 2353 * If only the PROMISC or ALLMULTI flag changes, then 2354 * don't do a full re-init of the chip, just update 2355 * the Rx filter. 2356 */ 2357 if ((ifp->if_flags & IFF_RUNNING) && 2358 ((ifp->if_flags ^ sc->sc_if_flags) & 2359 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 2360 urtw_set_multi(sc); 2361 } else { 2362 if (!(ifp->if_flags & IFF_RUNNING)) 2363 sc->sc_init(ifp); 2364 } 2365 } else { 2366 if (ifp->if_flags & IFF_RUNNING) 2367 urtw_stop(ifp, 1); 2368 } 2369 sc->sc_if_flags = ifp->if_flags; 2370 break; 2371 2372 case SIOCADDMULTI: 2373 case SIOCDELMULTI: 2374 ifr = (struct ifreq *)data; 2375 error = (cmd == SIOCADDMULTI) ? 2376 ether_addmulti(ifr, &ic->ic_ac) : 2377 ether_delmulti(ifr, &ic->ic_ac); 2378 if (error == ENETRESET) { 2379 if (ifp->if_flags & IFF_RUNNING) 2380 urtw_set_multi(sc); 2381 error = 0; 2382 } 2383 break; 2384 2385 case SIOCS80211CHANNEL: 2386 /* 2387 * This allows for fast channel switching in monitor mode 2388 * (used by kismet). In IBSS mode, we must explicitly reset 2389 * the interface to generate a new beacon frame. 2390 */ 2391 error = ieee80211_ioctl(ifp, cmd, data); 2392 if (error == ENETRESET && 2393 ic->ic_opmode == IEEE80211_M_MONITOR) { 2394 urtw_set_chan(sc, ic->ic_ibss_chan); 2395 error = 0; 2396 } 2397 break; 2398 2399 default: 2400 error = ieee80211_ioctl(ifp, cmd, data); 2401 } 2402 2403 if (error == ENETRESET) { 2404 if ((ifp->if_flags & (IFF_RUNNING | IFF_UP)) == 2405 (IFF_RUNNING | IFF_UP)) 2406 sc->sc_init(ifp); 2407 error = 0; 2408 } 2409 2410 splx(s); 2411 2412 usbd_ref_decr(sc->sc_udev); 2413 2414 return (error); 2415 } 2416 2417 void 2418 urtw_start(struct ifnet *ifp) 2419 { 2420 struct urtw_softc *sc = ifp->if_softc; 2421 struct ieee80211com *ic = &sc->sc_ic; 2422 struct ieee80211_node *ni; 2423 struct mbuf *m0; 2424 2425 /* 2426 * net80211 may still try to send management frames even if the 2427 * IFF_RUNNING flag is not set... 2428 */ 2429 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 2430 return; 2431 2432 for (;;) { 2433 if (sc->sc_tx_low_queued >= URTW_TX_DATA_LIST_COUNT || 2434 sc->sc_tx_normal_queued >= URTW_TX_DATA_LIST_COUNT) { 2435 ifq_set_oactive(&ifp->if_snd); 2436 break; 2437 } 2438 2439 m0 = mq_dequeue(&ic->ic_mgtq); 2440 if (m0 != NULL) { 2441 ni = m0->m_pkthdr.ph_cookie; 2442 #if NBPFILTER > 0 2443 if (ic->ic_rawbpf != NULL) 2444 bpf_mtap(ic->ic_rawbpf, m0, BPF_DIRECTION_OUT); 2445 #endif 2446 if (urtw_tx_start(sc, ni, m0, URTW_PRIORITY_NORMAL) 2447 != 0) 2448 break; 2449 } else { 2450 if (ic->ic_state != IEEE80211_S_RUN) 2451 break; 2452 IFQ_DEQUEUE(&ifp->if_snd, m0); 2453 if (m0 == NULL) 2454 break; 2455 #if NBPFILTER > 0 2456 if (ifp->if_bpf != NULL) 2457 bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT); 2458 #endif 2459 m0 = ieee80211_encap(ifp, m0, &ni); 2460 if (m0 == NULL) 2461 continue; 2462 #if NBPFILTER > 0 2463 if (ic->ic_rawbpf != NULL) 2464 bpf_mtap(ic->ic_rawbpf, m0, BPF_DIRECTION_OUT); 2465 #endif 2466 if (urtw_tx_start(sc, ni, m0, URTW_PRIORITY_NORMAL) 2467 != 0) { 2468 if (ni != NULL) 2469 ieee80211_release_node(ic, ni); 2470 ifp->if_oerrors++; 2471 break; 2472 } 2473 } 2474 sc->sc_txtimer = 5; 2475 } 2476 } 2477 2478 void 2479 urtw_watchdog(struct ifnet *ifp) 2480 { 2481 struct urtw_softc *sc = ifp->if_softc; 2482 2483 ifp->if_timer = 0; 2484 2485 if (sc->sc_txtimer > 0) { 2486 if (--sc->sc_txtimer == 0) { 2487 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 2488 ifp->if_oerrors++; 2489 return; 2490 } 2491 ifp->if_timer = 1; 2492 } 2493 2494 ieee80211_watchdog(ifp); 2495 } 2496 2497 void 2498 urtw_txeof_low(struct usbd_xfer *xfer, void *priv, 2499 usbd_status status) 2500 { 2501 struct urtw_tx_data *data = priv; 2502 struct urtw_softc *sc = data->sc; 2503 struct ieee80211com *ic = &sc->sc_ic; 2504 struct ifnet *ifp = &ic->ic_if; 2505 int s; 2506 2507 if (status != USBD_NORMAL_COMPLETION) { 2508 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2509 return; 2510 2511 printf("%s: could not transmit buffer: %s\n", 2512 sc->sc_dev.dv_xname, usbd_errstr(status)); 2513 2514 if (status == USBD_STALLED) 2515 usbd_clear_endpoint_stall_async(sc->sc_txpipe_low); 2516 2517 ifp->if_oerrors++; 2518 return; 2519 } 2520 2521 s = splnet(); 2522 2523 ieee80211_release_node(ic, data->ni); 2524 data->ni = NULL; 2525 2526 sc->sc_txtimer = 0; 2527 2528 sc->sc_tx_low_queued--; 2529 ifq_clr_oactive(&ifp->if_snd); 2530 urtw_start(ifp); 2531 2532 splx(s); 2533 } 2534 2535 void 2536 urtw_txeof_normal(struct usbd_xfer *xfer, void *priv, 2537 usbd_status status) 2538 { 2539 struct urtw_tx_data *data = priv; 2540 struct urtw_softc *sc = data->sc; 2541 struct ieee80211com *ic = &sc->sc_ic; 2542 struct ifnet *ifp = &ic->ic_if; 2543 int s; 2544 2545 if (status != USBD_NORMAL_COMPLETION) { 2546 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2547 return; 2548 2549 printf("%s: could not transmit buffer: %s\n", 2550 sc->sc_dev.dv_xname, usbd_errstr(status)); 2551 2552 if (status == USBD_STALLED) 2553 usbd_clear_endpoint_stall_async(sc->sc_txpipe_normal); 2554 2555 ifp->if_oerrors++; 2556 return; 2557 } 2558 2559 s = splnet(); 2560 2561 ieee80211_release_node(ic, data->ni); 2562 data->ni = NULL; 2563 2564 sc->sc_txtimer = 0; 2565 2566 sc->sc_tx_normal_queued--; 2567 ifq_clr_oactive(&ifp->if_snd); 2568 urtw_start(ifp); 2569 2570 splx(s); 2571 } 2572 2573 int 2574 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0, 2575 int prior) 2576 { 2577 struct ieee80211com *ic = &sc->sc_ic; 2578 struct urtw_tx_data *data; 2579 struct ieee80211_frame *wh; 2580 struct ieee80211_key *k; 2581 usbd_status error; 2582 int xferlen; 2583 2584 wh = mtod(m0, struct ieee80211_frame *); 2585 2586 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2587 k = ieee80211_get_txkey(ic, wh, ni); 2588 2589 if ((m0 = ieee80211_encrypt(ic, m0, k)) == NULL) 2590 return (ENOBUFS); 2591 2592 /* packet header may have moved, reset our local pointer */ 2593 wh = mtod(m0, struct ieee80211_frame *); 2594 } 2595 2596 #if NBPFILTER > 0 2597 if (sc->sc_drvbpf != NULL) { 2598 struct mbuf mb; 2599 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap; 2600 2601 tap->wt_flags = 0; 2602 tap->wt_rate = 0; 2603 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 2604 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 2605 2606 mb.m_data = (caddr_t)tap; 2607 mb.m_len = sc->sc_txtap_len; 2608 mb.m_next = m0; 2609 mb.m_nextpkt = NULL; 2610 mb.m_type = 0; 2611 mb.m_flags = 0; 2612 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 2613 } 2614 #endif 2615 2616 if (sc->sc_hwrev & URTW_HWREV_8187) 2617 xferlen = m0->m_pkthdr.len + 4 * 3; 2618 else 2619 xferlen = m0->m_pkthdr.len + 4 * 8; 2620 2621 if ((0 == xferlen % 64) || (0 == xferlen % 512)) 2622 xferlen += 1; 2623 2624 data = &sc->sc_tx_data[sc->sc_txidx]; 2625 sc->sc_txidx = (sc->sc_txidx + 1) % URTW_TX_DATA_LIST_COUNT; 2626 2627 bzero(data->buf, URTW_TX_MAXSIZE); 2628 data->buf[0] = m0->m_pkthdr.len & 0xff; 2629 data->buf[1] = (m0->m_pkthdr.len & 0x0f00) >> 8; 2630 data->buf[1] |= (1 << 7); 2631 2632 /* XXX sc_preamble_mode is always 2. */ 2633 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 2634 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && 2635 (sc->sc_preamble_mode == 1) && (sc->sc_currate != 0)) 2636 data->buf[2] |= 1; 2637 if ((m0->m_pkthdr.len > ic->ic_rtsthreshold) && 2638 prior == URTW_PRIORITY_LOW) 2639 return ENOTSUP; /* TODO */ 2640 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2641 data->buf[2] |= (1 << 1); 2642 /* RTS rate - 10 means we use a basic rate. */ 2643 data->buf[2] |= (urtw_rate2rtl(2) << 3); 2644 /* 2645 * XXX currently TX rate control depends on the rate value of 2646 * RX descriptor because I don't know how to we can control TX rate 2647 * in more smart way. Please fix me you find a thing. 2648 */ 2649 data->buf[3] = sc->sc_currate; 2650 if (prior == URTW_PRIORITY_NORMAL) { 2651 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2652 data->buf[3] = urtw_rate2rtl(ni->ni_rates.rs_rates[0]); 2653 else if (ic->ic_fixed_rate != -1) 2654 data->buf[3] = urtw_rate2rtl(ic->ic_fixed_rate); 2655 } 2656 2657 if (sc->sc_hwrev & URTW_HWREV_8187) { 2658 data->buf[8] = 3; /* CW minimum */ 2659 data->buf[8] |= (7 << 4); /* CW maximum */ 2660 data->buf[9] |= 11; /* retry limitation */ 2661 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)&data->buf[12]); 2662 } else { 2663 data->buf[21] |= 11; /* retry limitation */ 2664 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)&data->buf[32]); 2665 } 2666 2667 data->ni = ni; 2668 2669 /* mbuf is no longer needed. */ 2670 m_freem(m0); 2671 2672 usbd_setup_xfer(data->xfer, 2673 (prior == URTW_PRIORITY_LOW) ? sc->sc_txpipe_low : 2674 sc->sc_txpipe_normal, data, data->buf, xferlen, 2675 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTW_DATA_TIMEOUT, 2676 (prior == URTW_PRIORITY_LOW) ? urtw_txeof_low : urtw_txeof_normal); 2677 error = usbd_transfer(data->xfer); 2678 if (error != USBD_IN_PROGRESS && error != USBD_NORMAL_COMPLETION) { 2679 printf("%s: could not send frame: %s\n", 2680 sc->sc_dev.dv_xname, usbd_errstr(error)); 2681 return (EIO); 2682 } 2683 2684 error = urtw_led_ctl(sc, URTW_LED_CTL_TX); 2685 if (error != 0) 2686 printf("%s: could not control LED (%d)\n", 2687 sc->sc_dev.dv_xname, error); 2688 2689 if (prior == URTW_PRIORITY_LOW) 2690 sc->sc_tx_low_queued++; 2691 else 2692 sc->sc_tx_normal_queued++; 2693 2694 return (0); 2695 } 2696 2697 usbd_status 2698 urtw_8225_usb_init(struct urtw_softc *sc) 2699 { 2700 uint8_t data; 2701 usbd_status error; 2702 2703 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0); 2704 urtw_write8_m(sc, URTW_GPIO, 0); 2705 error = urtw_read8e(sc, 0x53, &data); 2706 if (error) 2707 goto fail; 2708 error = urtw_write8e(sc, 0x53, data | (1 << 7)); 2709 if (error) 2710 goto fail; 2711 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4); 2712 urtw_write8_m(sc, URTW_GPIO, 0x20); 2713 urtw_write8_m(sc, URTW_GP_ENABLE, 0); 2714 2715 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80); 2716 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80); 2717 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80); 2718 2719 usbd_delay_ms(sc->sc_udev, 500); 2720 fail: 2721 return (error); 2722 } 2723 2724 usbd_status 2725 urtw_8185_rf_pins_enable(struct urtw_softc *sc) 2726 { 2727 usbd_status error = 0; 2728 2729 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7); 2730 fail: 2731 return (error); 2732 } 2733 2734 usbd_status 2735 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2736 { 2737 uint32_t phyw; 2738 usbd_status error; 2739 2740 phyw = ((data << 8) | (addr | 0x80)); 2741 urtw_write8_m(sc, 0x7f, ((phyw & 0xff000000) >> 24)); 2742 urtw_write8_m(sc, 0x7e, ((phyw & 0x00ff0000) >> 16)); 2743 urtw_write8_m(sc, 0x7d, ((phyw & 0x0000ff00) >> 8)); 2744 urtw_write8_m(sc, 0x7c, ((phyw & 0x000000ff))); 2745 /* 2746 * Delay removed from 8185 to 8187. 2747 * usbd_delay_ms(sc->sc_udev, 1); 2748 */ 2749 fail: 2750 return (error); 2751 } 2752 2753 usbd_status 2754 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2755 { 2756 data = data & 0xff; 2757 return (urtw_8187_write_phy(sc, addr, data)); 2758 } 2759 2760 usbd_status 2761 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2762 { 2763 data = data & 0xff; 2764 return (urtw_8187_write_phy(sc, addr, data | 0x10000)); 2765 } 2766 2767 usbd_status 2768 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain) 2769 { 2770 usbd_status error; 2771 2772 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]); 2773 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]); 2774 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]); 2775 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]); 2776 fail: 2777 return (error); 2778 } 2779 2780 usbd_status 2781 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan) 2782 { 2783 int i, idx, set; 2784 uint8_t *cck_pwltable; 2785 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max; 2786 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 2787 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 2788 usbd_status error; 2789 2790 cck_pwrlvl_max = 11; 2791 ofdm_pwrlvl_max = 25; /* 12 -> 25 */ 2792 ofdm_pwrlvl_min = 10; 2793 2794 /* CCK power setting */ 2795 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 2796 idx = cck_pwrlvl % 6; 2797 set = cck_pwrlvl / 6; 2798 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 : 2799 urtw_8225_txpwr_cck; 2800 2801 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 2802 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2803 for (i = 0; i < 8; i++) { 2804 urtw_8187_write_phy_cck(sc, 0x44 + i, 2805 cck_pwltable[idx * 8 + i]); 2806 } 2807 usbd_delay_ms(sc->sc_udev, 1); 2808 2809 /* OFDM power setting */ 2810 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 2811 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 2812 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 2813 2814 idx = ofdm_pwrlvl % 6; 2815 set = ofdm_pwrlvl / 6; 2816 2817 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 2818 if (error) 2819 goto fail; 2820 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 2821 urtw_8187_write_phy_ofdm(sc, 6, 0); 2822 urtw_8187_write_phy_ofdm(sc, 8, 0); 2823 2824 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 2825 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2826 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]); 2827 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]); 2828 usbd_delay_ms(sc->sc_udev, 1); 2829 fail: 2830 return (error); 2831 } 2832 2833 usbd_status 2834 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant) 2835 { 2836 usbd_status error; 2837 2838 urtw_write8_m(sc, URTW_TX_ANTENNA, ant); 2839 usbd_delay_ms(sc->sc_udev, 1); 2840 fail: 2841 return (error); 2842 } 2843 2844 usbd_status 2845 urtw_8225_rf_init(struct urtw_rf *rf) 2846 { 2847 struct urtw_softc *sc = rf->rf_sc; 2848 int i; 2849 uint16_t data; 2850 usbd_status error; 2851 2852 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 2853 if (error) 2854 goto fail; 2855 2856 error = urtw_8225_usb_init(sc); 2857 if (error) 2858 goto fail; 2859 2860 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2861 urtw_read16_m(sc, URTW_8187_BRSR, &data); /* XXX ??? */ 2862 urtw_write16_m(sc, URTW_8187_BRSR, 0xffff); 2863 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2864 2865 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2866 if (error) 2867 goto fail; 2868 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2869 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2870 if (error) 2871 goto fail; 2872 2873 error = urtw_8185_rf_pins_enable(sc); 2874 if (error) 2875 goto fail; 2876 2877 usbd_delay_ms(sc->sc_udev, 500); 2878 2879 for (i = 0; i < nitems(urtw_8225_rf_part1); i++) { 2880 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg, 2881 urtw_8225_rf_part1[i].val); 2882 } 2883 usbd_delay_ms(sc->sc_udev, 50); 2884 urtw_8225_write(sc, 0x2, 0xc4d); 2885 usbd_delay_ms(sc->sc_udev, 200); 2886 urtw_8225_write(sc, 0x2, 0x44d); 2887 usbd_delay_ms(sc->sc_udev, 200); 2888 urtw_8225_write(sc, 0x0, 0x127); 2889 2890 for (i = 0; i < nitems(urtw_8225_rxgain); i++) { 2891 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 2892 urtw_8225_write(sc, 0x2, urtw_8225_rxgain[i]); 2893 } 2894 2895 urtw_8225_write(sc, 0x0, 0x27); 2896 urtw_8225_write(sc, 0x0, 0x22f); 2897 2898 for (i = 0; i < nitems(urtw_8225_agc); i++) { 2899 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2900 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2901 } 2902 2903 for (i = 0; i < nitems(urtw_8225_rf_part2); i++) { 2904 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg, 2905 urtw_8225_rf_part2[i].val); 2906 usbd_delay_ms(sc->sc_udev, 1); 2907 } 2908 2909 error = urtw_8225_setgain(sc, 4); 2910 if (error) 2911 goto fail; 2912 2913 for (i = 0; i < nitems(urtw_8225_rf_part3); i++) { 2914 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg, 2915 urtw_8225_rf_part3[i].val); 2916 usbd_delay_ms(sc->sc_udev, 1); 2917 } 2918 2919 urtw_write8_m(sc, 0x5b, 0x0d); 2920 2921 error = urtw_8225_set_txpwrlvl(sc, 1); 2922 if (error) 2923 goto fail; 2924 2925 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2926 usbd_delay_ms(sc->sc_udev, 1); 2927 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2928 usbd_delay_ms(sc->sc_udev, 1); 2929 2930 /* TX ant A, 0x0 for B */ 2931 error = urtw_8185_tx_antenna(sc, 0x3); 2932 if (error) 2933 goto fail; 2934 urtw_write32_m(sc, 0x94, 0x3dc00002); 2935 2936 error = urtw_8225_rf_set_chan(rf, 1); 2937 fail: 2938 return (error); 2939 } 2940 2941 usbd_status 2942 urtw_8225_rf_set_chan(struct urtw_rf *rf, int chan) 2943 { 2944 struct urtw_softc *sc = rf->rf_sc; 2945 struct ieee80211com *ic = &sc->sc_ic; 2946 struct ieee80211_channel *c = ic->ic_ibss_chan; 2947 usbd_status error; 2948 2949 error = urtw_8225_set_txpwrlvl(sc, chan); 2950 if (error) 2951 goto fail; 2952 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 2953 usbd_delay_ms(sc->sc_udev, 10); 2954 2955 urtw_write8_m(sc, URTW_SIFS, 0x22); 2956 2957 if (sc->sc_state == IEEE80211_S_ASSOC && 2958 ic->ic_flags & IEEE80211_F_SHSLOT) 2959 urtw_write8_m(sc, URTW_SLOT, 0x9); 2960 else 2961 urtw_write8_m(sc, URTW_SLOT, 0x14); 2962 2963 if (IEEE80211_IS_CHAN_G(c)) { 2964 urtw_write8_m(sc, URTW_DIFS, 0x14); 2965 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x14); 2966 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 2967 } else { 2968 urtw_write8_m(sc, URTW_DIFS, 0x24); 2969 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x24); 2970 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 2971 } 2972 2973 fail: 2974 return (error); 2975 } 2976 2977 usbd_status 2978 urtw_8225_rf_set_sens(struct urtw_rf *rf) 2979 { 2980 struct urtw_softc *sc = rf->rf_sc; 2981 usbd_status error; 2982 2983 if (rf->sens > 6) 2984 return (-1); 2985 2986 if (rf->sens > 4) 2987 urtw_8225_write(sc, 0x0c, 0x850); 2988 else 2989 urtw_8225_write(sc, 0x0c, 0x50); 2990 2991 rf->sens = 6 - rf->sens; 2992 error = urtw_8225_setgain(sc, rf->sens); 2993 if (error) 2994 goto fail; 2995 2996 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[rf->sens]); 2997 2998 fail: 2999 return (error); 3000 } 3001 3002 void 3003 urtw_stop(struct ifnet *ifp, int disable) 3004 { 3005 struct urtw_softc *sc = ifp->if_softc; 3006 struct ieee80211com *ic = &sc->sc_ic; 3007 uint8_t data; 3008 usbd_status error; 3009 3010 ifp->if_flags &= ~IFF_RUNNING; 3011 ifq_clr_oactive(&ifp->if_snd); 3012 3013 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3014 3015 timeout_del(&sc->scan_to); 3016 timeout_del(&sc->sc_led_ch); 3017 3018 urtw_intr_disable(sc); 3019 urtw_read8_m(sc, URTW_CMD, &data); 3020 data &= ~URTW_CMD_TX_ENABLE; 3021 data &= ~URTW_CMD_RX_ENABLE; 3022 urtw_write8_m(sc, URTW_CMD, data); 3023 3024 if (sc->sc_rxpipe != NULL) 3025 usbd_abort_pipe(sc->sc_rxpipe); 3026 if (sc->sc_txpipe_low != NULL) 3027 usbd_abort_pipe(sc->sc_txpipe_low); 3028 if (sc->sc_txpipe_normal != NULL) 3029 usbd_abort_pipe(sc->sc_txpipe_normal); 3030 3031 fail: 3032 return; 3033 } 3034 3035 int 3036 urtw_isbmode(uint16_t rate) 3037 { 3038 rate = urtw_rtl2rate(rate); 3039 3040 return (((rate <= 22 && rate != 12 && rate != 18) || 3041 rate == 44) ? (1) : (0)); 3042 } 3043 3044 void 3045 urtw_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 3046 { 3047 struct urtw_rx_data *data = priv; 3048 struct urtw_softc *sc = data->sc; 3049 struct ieee80211com *ic = &sc->sc_ic; 3050 struct ifnet *ifp = &ic->ic_if; 3051 struct ieee80211_frame *wh; 3052 struct ieee80211_node *ni; 3053 struct ieee80211_rxinfo rxi; 3054 struct mbuf *m, *mnew; 3055 uint8_t *desc, quality, rate; 3056 int actlen, flen, len, nf, rssi, s; 3057 3058 if (status != USBD_NORMAL_COMPLETION) { 3059 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 3060 return; 3061 3062 if (status == USBD_STALLED) 3063 usbd_clear_endpoint_stall_async(sc->sc_rxpipe); 3064 ifp->if_ierrors++; 3065 goto skip; 3066 } 3067 3068 usbd_get_xfer_status(xfer, NULL, NULL, &actlen, NULL); 3069 if (actlen < URTW_MIN_RXBUFSZ) { 3070 ifp->if_ierrors++; 3071 goto skip; 3072 } 3073 3074 if (sc->sc_hwrev & URTW_HWREV_8187) 3075 /* 4 dword and 4 byte CRC */ 3076 len = actlen - (4 * 4); 3077 else 3078 /* 5 dword and 4 byte CRC */ 3079 len = actlen - (4 * 5); 3080 3081 desc = data->buf + len; 3082 flen = ((desc[1] & 0x0f) << 8) + (desc[0] & 0xff); 3083 if (flen > actlen) { 3084 ifp->if_ierrors++; 3085 goto skip; 3086 } 3087 3088 rate = (desc[2] & 0xf0) >> 4; 3089 if (sc->sc_hwrev & URTW_HWREV_8187) { 3090 quality = desc[4] & 0xff; 3091 rssi = (desc[6] & 0xfe) >> 1; 3092 3093 /* XXX correct? */ 3094 if (!urtw_isbmode(rate)) { 3095 rssi = (rssi > 90) ? 90 : ((rssi < 25) ? 25 : rssi); 3096 rssi = ((90 - rssi) * 100) / 65; 3097 } else { 3098 rssi = (rssi > 90) ? 95 : ((rssi < 30) ? 30 : rssi); 3099 rssi = ((95 - rssi) * 100) / 65; 3100 } 3101 } else { 3102 quality = desc[12]; 3103 rssi = 14 - desc[14] / 2; 3104 } 3105 3106 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 3107 if (mnew == NULL) { 3108 printf("%s: could not allocate rx mbuf\n", 3109 sc->sc_dev.dv_xname); 3110 ifp->if_ierrors++; 3111 goto skip; 3112 } 3113 MCLGET(mnew, M_DONTWAIT); 3114 if (!(mnew->m_flags & M_EXT)) { 3115 printf("%s: could not allocate rx mbuf cluster\n", 3116 sc->sc_dev.dv_xname); 3117 m_freem(mnew); 3118 ifp->if_ierrors++; 3119 goto skip; 3120 } 3121 3122 m = data->m; 3123 data->m = mnew; 3124 data->buf = mtod(mnew, uint8_t *); 3125 3126 /* finalize mbuf */ 3127 m->m_pkthdr.len = m->m_len = flen - 4; 3128 3129 s = splnet(); 3130 3131 #if NBPFILTER > 0 3132 if (sc->sc_drvbpf != NULL) { 3133 struct mbuf mb; 3134 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap; 3135 3136 /* XXX Are variables correct? */ 3137 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 3138 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 3139 tap->wr_dbm_antsignal = (int8_t)rssi; 3140 3141 mb.m_data = (caddr_t)tap; 3142 mb.m_len = sc->sc_rxtap_len; 3143 mb.m_next = m; 3144 mb.m_nextpkt = NULL; 3145 mb.m_type = 0; 3146 mb.m_flags = 0; 3147 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 3148 } 3149 #endif 3150 wh = mtod(m, struct ieee80211_frame *); 3151 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_DATA) 3152 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate; 3153 ni = ieee80211_find_rxnode(ic, wh); 3154 3155 /* XXX correct? */ 3156 if (!urtw_isbmode(rate)) { 3157 if (quality > 127) 3158 quality = 0; 3159 else if (quality < 27) 3160 quality = 100; 3161 else 3162 quality = 127 - quality; 3163 } else 3164 quality = (quality > 64) ? 0 : ((64 - quality) * 100) / 64; 3165 3166 nf = quality; 3167 3168 /* send the frame to the 802.11 layer */ 3169 rxi.rxi_flags = 0; 3170 rxi.rxi_rssi = rssi; 3171 rxi.rxi_tstamp = 0; 3172 ieee80211_input(ifp, m, ni, &rxi); 3173 3174 /* node is no longer needed */ 3175 ieee80211_release_node(ic, ni); 3176 3177 splx(s); 3178 3179 skip: /* setup a new transfer */ 3180 usbd_setup_xfer(xfer, sc->sc_rxpipe, data, data->buf, MCLBYTES, 3181 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtw_rxeof); 3182 (void)usbd_transfer(xfer); 3183 } 3184 3185 usbd_status 3186 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain) 3187 { 3188 uint8_t *gainp; 3189 usbd_status error; 3190 3191 /* XXX for A? */ 3192 gainp = urtw_8225v2_gain_bg; 3193 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]); 3194 usbd_delay_ms(sc->sc_udev, 1); 3195 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]); 3196 usbd_delay_ms(sc->sc_udev, 1); 3197 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]); 3198 usbd_delay_ms(sc->sc_udev, 1); 3199 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17); 3200 usbd_delay_ms(sc->sc_udev, 1); 3201 fail: 3202 return (error); 3203 } 3204 3205 usbd_status 3206 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan) 3207 { 3208 int i; 3209 uint8_t *cck_pwrtable; 3210 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10; 3211 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3212 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3213 usbd_status error; 3214 3215 /* CCK power setting */ 3216 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 3217 cck_pwrlvl += sc->sc_txpwr_cck_base; 3218 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3219 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3220 urtw_8225v2_txpwr_cck; 3221 3222 for (i = 0; i < 8; i++) { 3223 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3224 } 3225 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3226 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]); 3227 usbd_delay_ms(sc->sc_udev, 1); 3228 3229 /* OFDM power setting */ 3230 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3231 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3232 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3233 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3234 3235 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 3236 if (error) 3237 goto fail; 3238 3239 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 3240 urtw_8187_write_phy_ofdm(sc, 5, 0x0); 3241 urtw_8187_write_phy_ofdm(sc, 6, 0x40); 3242 urtw_8187_write_phy_ofdm(sc, 7, 0x0); 3243 urtw_8187_write_phy_ofdm(sc, 8, 0x40); 3244 3245 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3246 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]); 3247 usbd_delay_ms(sc->sc_udev, 1); 3248 fail: 3249 return (error); 3250 } 3251 3252 usbd_status 3253 urtw_8225v2_rf_init(struct urtw_rf *rf) 3254 { 3255 struct urtw_softc *sc = rf->rf_sc; 3256 int i; 3257 uint16_t data; 3258 uint32_t data32; 3259 usbd_status error; 3260 3261 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 3262 if (error) 3263 goto fail; 3264 3265 error = urtw_8225_usb_init(sc); 3266 if (error) 3267 goto fail; 3268 3269 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 3270 urtw_read16_m(sc, URTW_8187_BRSR, &data); /* XXX ??? */ 3271 urtw_write16_m(sc, URTW_8187_BRSR, 0xffff); 3272 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 3273 3274 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3275 if (error) 3276 goto fail; 3277 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 3278 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3279 if (error) 3280 goto fail; 3281 3282 error = urtw_8185_rf_pins_enable(sc); 3283 if (error) 3284 goto fail; 3285 3286 usbd_delay_ms(sc->sc_udev, 1000); 3287 3288 for (i = 0; i < nitems(urtw_8225v2_rf_part1); i++) { 3289 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg, 3290 urtw_8225v2_rf_part1[i].val); 3291 usbd_delay_ms(sc->sc_udev, 1); 3292 } 3293 usbd_delay_ms(sc->sc_udev, 50); 3294 3295 urtw_8225_write(sc, 0x0, 0x1b7); 3296 3297 for (i = 0; i < nitems(urtw_8225v2_rxgain); i++) { 3298 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 3299 urtw_8225_write(sc, 0x2, urtw_8225v2_rxgain[i]); 3300 } 3301 3302 urtw_8225_write(sc, 0x3, 0x2); 3303 urtw_8225_write(sc, 0x5, 0x4); 3304 urtw_8225_write(sc, 0x0, 0xb7); 3305 urtw_8225_write(sc, 0x2, 0xc4d); 3306 usbd_delay_ms(sc->sc_udev, 100); 3307 urtw_8225_write(sc, 0x2, 0x44d); 3308 usbd_delay_ms(sc->sc_udev, 100); 3309 3310 error = urtw_8225_read(sc, 0x6, &data32); 3311 if (error != 0) 3312 goto fail; 3313 if (data32 != 0xe6) 3314 printf("%s: expect 0xe6!! (0x%x)\n", sc->sc_dev.dv_xname, 3315 data32); 3316 if (!(data32 & 0x80)) { 3317 urtw_8225_write(sc, 0x02, 0x0c4d); 3318 usbd_delay_ms(sc->sc_udev, 200); 3319 urtw_8225_write(sc, 0x02, 0x044d); 3320 usbd_delay_ms(sc->sc_udev, 100); 3321 error = urtw_8225_read(sc, 0x6, &data32); 3322 if (error != 0) 3323 goto fail; 3324 if (!(data32 & 0x80)) 3325 printf("%s: RF calibration failed\n", 3326 sc->sc_dev.dv_xname); 3327 } 3328 usbd_delay_ms(sc->sc_udev, 100); 3329 3330 urtw_8225_write(sc, 0x0, 0x2bf); 3331 for (i = 0; i < nitems(urtw_8225_agc); i++) { 3332 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 3333 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 3334 } 3335 3336 for (i = 0; i < nitems(urtw_8225v2_rf_part2); i++) { 3337 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg, 3338 urtw_8225v2_rf_part2[i].val); 3339 } 3340 3341 error = urtw_8225v2_setgain(sc, 4); 3342 if (error) 3343 goto fail; 3344 3345 for (i = 0; i < nitems(urtw_8225v2_rf_part3); i++) { 3346 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg, 3347 urtw_8225v2_rf_part3[i].val); 3348 } 3349 3350 urtw_write8_m(sc, 0x5b, 0x0d); 3351 3352 error = urtw_8225v2_set_txpwrlvl(sc, 1); 3353 if (error) 3354 goto fail; 3355 3356 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 3357 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 3358 3359 /* TX ant A, 0x0 for B */ 3360 error = urtw_8185_tx_antenna(sc, 0x3); 3361 if (error) 3362 goto fail; 3363 urtw_write32_m(sc, 0x94, 0x3dc00002); 3364 3365 error = urtw_8225_rf_set_chan(rf, 1); 3366 fail: 3367 return (error); 3368 } 3369 3370 usbd_status 3371 urtw_8225v2_rf_set_chan(struct urtw_rf *rf, int chan) 3372 { 3373 struct urtw_softc *sc = rf->rf_sc; 3374 struct ieee80211com *ic = &sc->sc_ic; 3375 struct ieee80211_channel *c = ic->ic_ibss_chan; 3376 usbd_status error; 3377 3378 error = urtw_8225v2_set_txpwrlvl(sc, chan); 3379 if (error) 3380 goto fail; 3381 3382 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 3383 usbd_delay_ms(sc->sc_udev, 10); 3384 3385 urtw_write8_m(sc, URTW_SIFS, 0x22); 3386 3387 if(sc->sc_state == IEEE80211_S_ASSOC && 3388 ic->ic_flags & IEEE80211_F_SHSLOT) 3389 urtw_write8_m(sc, URTW_SLOT, 0x9); 3390 else 3391 urtw_write8_m(sc, URTW_SLOT, 0x14); 3392 3393 if (IEEE80211_IS_CHAN_G(c)) { 3394 urtw_write8_m(sc, URTW_DIFS, 0x14); 3395 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x14); 3396 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 3397 } else { 3398 urtw_write8_m(sc, URTW_DIFS, 0x24); 3399 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x24); 3400 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 3401 } 3402 3403 fail: 3404 return (error); 3405 } 3406 3407 void 3408 urtw_set_chan(struct urtw_softc *sc, struct ieee80211_channel *c) 3409 { 3410 struct urtw_rf *rf = &sc->sc_rf; 3411 struct ieee80211com *ic = &sc->sc_ic; 3412 usbd_status error = 0; 3413 uint32_t data; 3414 u_int chan; 3415 3416 chan = ieee80211_chan2ieee(ic, c); 3417 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3418 return; 3419 /* 3420 * During changing the channel we need to temporary disable 3421 * TX. 3422 */ 3423 urtw_read32_m(sc, URTW_TX_CONF, &data); 3424 data &= ~URTW_TX_LOOPBACK_MASK; 3425 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC); 3426 error = rf->set_chan(rf, chan); 3427 if (error != 0) { 3428 printf("%s could not change the channel\n", 3429 sc->sc_dev.dv_xname); 3430 return; 3431 } 3432 usbd_delay_ms(sc->sc_udev, 10); 3433 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_NONE); 3434 3435 fail: return; 3436 3437 } 3438 3439 void 3440 urtw_next_scan(void *arg) 3441 { 3442 struct urtw_softc *sc = arg; 3443 struct ieee80211com *ic = &sc->sc_ic; 3444 struct ifnet *ifp = &ic->ic_if; 3445 3446 if (usbd_is_dying(sc->sc_udev)) 3447 return; 3448 3449 usbd_ref_incr(sc->sc_udev); 3450 3451 if (ic->ic_state == IEEE80211_S_SCAN) 3452 ieee80211_next_scan(ifp); 3453 3454 usbd_ref_decr(sc->sc_udev); 3455 } 3456 3457 void 3458 urtw_task(void *arg) 3459 { 3460 struct urtw_softc *sc = arg; 3461 struct ieee80211com *ic = &sc->sc_ic; 3462 struct ieee80211_node *ni; 3463 enum ieee80211_state ostate; 3464 usbd_status error = 0; 3465 3466 if (usbd_is_dying(sc->sc_udev)) 3467 return; 3468 3469 ostate = ic->ic_state; 3470 3471 switch (sc->sc_state) { 3472 case IEEE80211_S_INIT: 3473 if (ostate == IEEE80211_S_RUN) { 3474 /* turn link LED off */ 3475 (void)urtw_led_off(sc, URTW_LED_GPIO); 3476 } 3477 break; 3478 3479 case IEEE80211_S_SCAN: 3480 urtw_set_chan(sc, ic->ic_bss->ni_chan); 3481 if (!usbd_is_dying(sc->sc_udev)) 3482 timeout_add_msec(&sc->scan_to, 200); 3483 break; 3484 3485 case IEEE80211_S_AUTH: 3486 case IEEE80211_S_ASSOC: 3487 urtw_set_chan(sc, ic->ic_bss->ni_chan); 3488 break; 3489 3490 case IEEE80211_S_RUN: 3491 ni = ic->ic_bss; 3492 3493 /* setting bssid. */ 3494 error = urtw_set_bssid(sc, ni->ni_bssid); 3495 if (error != 0) 3496 goto fail; 3497 urtw_update_msr(sc); 3498 /* XXX maybe the below would be incorrect. */ 3499 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3500 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 3501 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64); 3502 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 0x3ff); 3503 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK); 3504 if (error != 0) 3505 printf("%s: could not control LED (%d)\n", 3506 sc->sc_dev.dv_xname, error); 3507 break; 3508 } 3509 3510 sc->sc_newstate(ic, sc->sc_state, sc->sc_arg); 3511 3512 fail: 3513 if (error != 0) 3514 DPRINTF(("%s: error duing processing RUN state.", 3515 sc->sc_dev.dv_xname)); 3516 } 3517 3518 usbd_status 3519 urtw_8187b_update_wmm(struct urtw_softc *sc) 3520 { 3521 struct ieee80211com *ic = &sc->sc_ic; 3522 struct ieee80211_channel *c = ic->ic_ibss_chan; 3523 uint32_t data; 3524 uint8_t aifs, sifs, slot, ecwmin, ecwmax; 3525 usbd_status error; 3526 3527 sifs = 0xa; 3528 if (IEEE80211_IS_CHAN_G(c)) 3529 slot = 0x9; 3530 else 3531 slot = 0x14; 3532 3533 aifs = (2 * slot) + sifs; 3534 ecwmin = 3; 3535 ecwmax = 7; 3536 3537 data = ((uint32_t)aifs << 0) | /* AIFS, offset 0 */ 3538 ((uint32_t)ecwmin << 8) | /* ECW minimum, offset 8 */ 3539 ((uint32_t)ecwmax << 12); /* ECW maximum, offset 16 */ 3540 3541 urtw_write32_m(sc, URTW_AC_VO, data); 3542 urtw_write32_m(sc, URTW_AC_VI, data); 3543 urtw_write32_m(sc, URTW_AC_BE, data); 3544 urtw_write32_m(sc, URTW_AC_BK, data); 3545 3546 fail: 3547 return (error); 3548 } 3549 3550 usbd_status 3551 urtw_8187b_reset(struct urtw_softc *sc) 3552 { 3553 uint8_t data; 3554 usbd_status error; 3555 3556 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3557 if (error) 3558 goto fail; 3559 3560 urtw_read8_m(sc, URTW_CONFIG3, &data); 3561 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE | 3562 URTW_CONFIG3_GNT_SELECT); 3563 3564 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON); 3565 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON); 3566 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON); 3567 3568 urtw_write8_m(sc, 0x61, 0x10); 3569 urtw_read8_m(sc, 0x62, &data); 3570 urtw_write8_m(sc, 0x62, data & ~(1 << 5)); 3571 urtw_write8_m(sc, 0x62, data | (1 << 5)); 3572 3573 urtw_read8_m(sc, URTW_CONFIG3, &data); 3574 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3575 3576 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3577 if (error) 3578 goto fail; 3579 3580 urtw_read8_m(sc, URTW_CMD, &data); 3581 data = (data & 2) | URTW_CMD_RST; 3582 urtw_write8_m(sc, URTW_CMD, data); 3583 usbd_delay_ms(sc->sc_udev, 100); 3584 3585 urtw_read8_m(sc, URTW_CMD, &data); 3586 if (data & URTW_CMD_RST) { 3587 printf("%s: reset timeout\n", sc->sc_dev.dv_xname); 3588 goto fail; 3589 } 3590 3591 fail: 3592 return (error); 3593 } 3594 3595 int 3596 urtw_8187b_init(struct ifnet *ifp) 3597 { 3598 struct urtw_softc *sc = ifp->if_softc; 3599 struct urtw_rf *rf = &sc->sc_rf; 3600 struct ieee80211com *ic = &sc->sc_ic; 3601 int ret; 3602 uint8_t data; 3603 usbd_status error; 3604 3605 urtw_stop(ifp, 0); 3606 3607 error = urtw_8187b_update_wmm(sc); 3608 if (error != 0) 3609 goto fail; 3610 error = urtw_8187b_reset(sc); 3611 if (error) 3612 goto fail; 3613 3614 /* Applying MAC address again. */ 3615 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3616 if (error) 3617 goto fail; 3618 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 3619 error = urtw_set_macaddr(sc, ic->ic_myaddr); 3620 if (error) 3621 goto fail; 3622 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3623 if (error) 3624 goto fail; 3625 3626 error = urtw_update_msr(sc); 3627 if (error) 3628 goto fail; 3629 3630 error = rf->init(rf); 3631 if (error != 0) 3632 goto fail; 3633 3634 urtw_write8_m(sc, URTW_CMD, URTW_CMD_TX_ENABLE | 3635 URTW_CMD_RX_ENABLE); 3636 error = urtw_intr_enable(sc); 3637 if (error != 0) 3638 goto fail; 3639 3640 error = urtw_write8e(sc, 0x41, 0xf4); 3641 if (error != 0) 3642 goto fail; 3643 error = urtw_write8e(sc, 0x40, 0x00); 3644 if (error != 0) 3645 goto fail; 3646 error = urtw_write8e(sc, 0x42, 0x00); 3647 if (error != 0) 3648 goto fail; 3649 error = urtw_write8e(sc, 0x42, 0x01); 3650 if (error != 0) 3651 goto fail; 3652 error = urtw_write8e(sc, 0x40, 0x0f); 3653 if (error != 0) 3654 goto fail; 3655 error = urtw_write8e(sc, 0x42, 0x00); 3656 if (error != 0) 3657 goto fail; 3658 error = urtw_write8e(sc, 0x42, 0x01); 3659 if (error != 0) 3660 goto fail; 3661 3662 urtw_read8_m(sc, 0xdb, &data); 3663 urtw_write8_m(sc, 0xdb, data | (1 << 2)); 3664 urtw_write16_idx_m(sc, 0x72, 0x59fa, 3); 3665 urtw_write16_idx_m(sc, 0x74, 0x59d2, 3); 3666 urtw_write16_idx_m(sc, 0x76, 0x59d2, 3); 3667 urtw_write16_idx_m(sc, 0x78, 0x19fa, 3); 3668 urtw_write16_idx_m(sc, 0x7a, 0x19fa, 3); 3669 urtw_write16_idx_m(sc, 0x7c, 0x00d0, 3); 3670 urtw_write8_m(sc, 0x61, 0); 3671 urtw_write8_idx_m(sc, 0x80, 0x0f, 1); 3672 urtw_write8_idx_m(sc, 0x83, 0x03, 1); 3673 urtw_write8_m(sc, 0xda, 0x10); 3674 urtw_write8_idx_m(sc, 0x4d, 0x08, 2); 3675 3676 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321b); 3677 3678 urtw_write16_idx_m(sc, 0xec, 0x0800, 1); 3679 3680 urtw_write8_m(sc, URTW_ACM_CONTROL, 0); 3681 3682 /* Reset softc variables. */ 3683 sc->sc_txidx = sc->sc_tx_low_queued = sc->sc_tx_normal_queued = 0; 3684 sc->sc_txtimer = 0; 3685 3686 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 3687 error = urtw_open_pipes(sc); 3688 if (error != 0) 3689 goto fail; 3690 ret = urtw_alloc_rx_data_list(sc); 3691 if (error != 0) 3692 goto fail; 3693 ret = urtw_alloc_tx_data_list(sc); 3694 if (error != 0) 3695 goto fail; 3696 sc->sc_flags |= URTW_INIT_ONCE; 3697 } 3698 3699 error = urtw_rx_enable(sc); 3700 if (error != 0) 3701 goto fail; 3702 error = urtw_tx_enable(sc); 3703 if (error != 0) 3704 goto fail; 3705 3706 ifp->if_flags |= IFF_RUNNING; 3707 ifq_clr_oactive(&ifp->if_snd); 3708 3709 ifp->if_timer = 1; 3710 3711 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3712 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3713 else 3714 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3715 3716 fail: 3717 return (error); 3718 } 3719 3720 usbd_status 3721 urtw_8225v2_b_config_mac(struct urtw_softc *sc) 3722 { 3723 int i; 3724 usbd_status error; 3725 3726 for (i = 0; i < nitems(urtw_8187b_regtbl); i++) { 3727 urtw_write8_idx_m(sc, urtw_8187b_regtbl[i].reg, 3728 urtw_8187b_regtbl[i].val, urtw_8187b_regtbl[i].idx); 3729 } 3730 3731 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50); 3732 urtw_write16_m(sc, URTW_INT_MIG, 0); 3733 3734 urtw_write32_idx_m(sc, 0xf0, 0, 1); 3735 urtw_write32_idx_m(sc, 0xf4, 0, 1); 3736 urtw_write8_idx_m(sc, 0xf8, 0, 1); 3737 3738 urtw_write32_m(sc, URTW_RF_TIMING, 0x00004001); 3739 3740 fail: 3741 return (error); 3742 } 3743 3744 usbd_status 3745 urtw_8225v2_b_init_rfe(struct urtw_softc *sc) 3746 { 3747 usbd_status error; 3748 3749 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480); 3750 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488); 3751 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff); 3752 usbd_delay_ms(sc->sc_udev, 100); 3753 3754 fail: 3755 return (error); 3756 } 3757 3758 usbd_status 3759 urtw_8225v2_b_update_chan(struct urtw_softc *sc) 3760 { 3761 struct ieee80211com *ic = &sc->sc_ic; 3762 struct ieee80211_channel *c = ic->ic_ibss_chan; 3763 uint8_t aifs, difs, eifs, sifs, slot; 3764 usbd_status error; 3765 3766 urtw_write8_m(sc, URTW_SIFS, 0x22); 3767 3768 sifs = 0xa; 3769 if (IEEE80211_IS_CHAN_G(c)) { 3770 slot = 0x9; 3771 difs = 0x1c; 3772 eifs = 0x5b; 3773 } else { 3774 slot = 0x14; 3775 difs = 0x32; 3776 eifs = 0x5b; 3777 } 3778 aifs = (2 * slot) + sifs; 3779 3780 urtw_write8_m(sc, URTW_SLOT, slot); 3781 3782 urtw_write8_m(sc, URTW_AC_VO, aifs); 3783 urtw_write8_m(sc, URTW_AC_VI, aifs); 3784 urtw_write8_m(sc, URTW_AC_BE, aifs); 3785 urtw_write8_m(sc, URTW_AC_BK, aifs); 3786 3787 urtw_write8_m(sc, URTW_DIFS, difs); 3788 urtw_write8_m(sc, URTW_8187B_EIFS, eifs); 3789 3790 fail: 3791 return (error); 3792 } 3793 3794 usbd_status 3795 urtw_8225v2_b_rf_init(struct urtw_rf *rf) 3796 { 3797 struct urtw_softc *sc = rf->rf_sc; 3798 int i; 3799 uint8_t data; 3800 usbd_status error; 3801 3802 /* Set up ACK rate, retry limit, TX AGC, TX antenna. */ 3803 urtw_write16_m(sc, URTW_8187B_BRSR, 0x0fff); 3804 urtw_read8_m(sc, URTW_CW_CONF, &data); 3805 urtw_write8_m(sc, URTW_CW_CONF, data | 3806 URTW_CW_CONF_PERPACKET_RETRY); 3807 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data); 3808 urtw_write8_m(sc, URTW_TX_AGC_CTL, data | 3809 URTW_TX_AGC_CTL_PERPACKET_GAIN | 3810 URTW_TX_AGC_CTL_PERPACKET_ANTSEL); 3811 3812 /* Auto rate fallback control. */ 3813 urtw_write16_idx_m(sc, URTW_ARFR, 0x0fff, 1); /* 1M ~ 54M */ 3814 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data); 3815 urtw_write8_m(sc, URTW_RATE_FALLBACK, data | 3816 URTW_RATE_FALLBACK_ENABLE); 3817 3818 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 3819 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3820 urtw_write16_idx_m(sc, URTW_FEMR, 0xffff, 1); 3821 3822 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3823 if (error) 3824 goto fail; 3825 urtw_read8_m(sc, URTW_CONFIG1, &data); 3826 urtw_write8_m(sc, URTW_CONFIG1, (data & 0x3f) | 0x80); 3827 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3828 if (error) 3829 goto fail; 3830 3831 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 3832 urtw_8225v2_b_config_mac(sc); 3833 urtw_write16_idx_m(sc, URTW_RFSW_CTRL, 0x569a, 2); 3834 3835 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3836 if (error) 3837 goto fail; 3838 urtw_read8_m(sc, URTW_CONFIG3, &data); 3839 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3840 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3841 if (error) 3842 goto fail; 3843 3844 urtw_8225v2_b_init_rfe(sc); 3845 3846 for (i = 0; i < nitems(urtw_8225v2_b_rf); i++) { 3847 urtw_8225_write(sc, urtw_8225v2_b_rf[i].reg, 3848 urtw_8225v2_b_rf[i].val); 3849 } 3850 3851 for (i = 0; i < nitems(urtw_8225v2_rxgain); i++) { 3852 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 3853 urtw_8225_write(sc, 0x2, urtw_8225v2_rxgain[i]); 3854 } 3855 3856 urtw_8225_write(sc, 0x03, 0x080); 3857 urtw_8225_write(sc, 0x05, 0x004); 3858 urtw_8225_write(sc, 0x00, 0x0b7); 3859 urtw_8225_write(sc, 0x02, 0xc4d); 3860 urtw_8225_write(sc, 0x02, 0x44d); 3861 urtw_8225_write(sc, 0x00, 0x2bf); 3862 3863 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03); 3864 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07); 3865 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03); 3866 3867 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12); 3868 for (i = 0; i < nitems(urtw_8225v2_agc); i++) { 3869 urtw_8187_write_phy_ofdm(sc, 0x0f, urtw_8225v2_agc[i]); 3870 urtw_8187_write_phy_ofdm(sc, 0x0e, (uint8_t)i + 0x80); 3871 urtw_8187_write_phy_ofdm(sc, 0x0e, 0); 3872 } 3873 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10); 3874 3875 for (i = 0; i < nitems(urtw_8225v2_ofdm); i++) 3876 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2_ofdm[i]); 3877 3878 urtw_8225v2_b_update_chan(sc); 3879 3880 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46); 3881 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6); 3882 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc); 3883 urtw_8187_write_phy_cck(sc, 0xc1, 0x88); 3884 3885 error = urtw_8225v2_b_rf_set_chan(rf, 1); 3886 fail: 3887 return (error); 3888 } 3889 3890 usbd_status 3891 urtw_8225v2_b_rf_set_chan(struct urtw_rf *rf, int chan) 3892 { 3893 struct urtw_softc *sc = rf->rf_sc; 3894 usbd_status error; 3895 3896 error = urtw_8225v2_b_set_txpwrlvl(sc, chan); 3897 if (error) 3898 goto fail; 3899 3900 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 3901 /* 3902 * Delay removed from 8185 to 8187. 3903 * usbd_delay_ms(sc->sc_udev, 10); 3904 */ 3905 3906 urtw_write16_m(sc, URTW_AC_VO, 0x5114); 3907 urtw_write16_m(sc, URTW_AC_VI, 0x5114); 3908 urtw_write16_m(sc, URTW_AC_BE, 0x5114); 3909 urtw_write16_m(sc, URTW_AC_BK, 0x5114); 3910 3911 fail: 3912 return (error); 3913 } 3914 3915 usbd_status 3916 urtw_8225v2_b_set_txpwrlvl(struct urtw_softc *sc, int chan) 3917 { 3918 int i; 3919 uint8_t *cck_pwrtable; 3920 uint8_t cck_pwrlvl_min, cck_pwrlvl_max, ofdm_pwrlvl_min, 3921 ofdm_pwrlvl_max; 3922 int8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3923 int8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3924 usbd_status error; 3925 3926 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3927 cck_pwrlvl_min = 0; 3928 cck_pwrlvl_max = 15; 3929 ofdm_pwrlvl_min = 2; 3930 ofdm_pwrlvl_max = 17; 3931 } else { 3932 cck_pwrlvl_min = 7; 3933 cck_pwrlvl_max = 22; 3934 ofdm_pwrlvl_min = 10; 3935 ofdm_pwrlvl_max = 25; 3936 } 3937 3938 /* CCK power setting */ 3939 cck_pwrlvl = (cck_pwrlvl > (cck_pwrlvl_max - cck_pwrlvl_min)) ? 3940 cck_pwrlvl_max : (cck_pwrlvl + cck_pwrlvl_min); 3941 3942 cck_pwrlvl += sc->sc_txpwr_cck_base; 3943 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3944 cck_pwrlvl = (cck_pwrlvl < 0) ? 0 : cck_pwrlvl; 3945 3946 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3947 urtw_8225v2_txpwr_cck; 3948 3949 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3950 if (cck_pwrlvl <= 6) 3951 ; /* do nothing */ 3952 else if (cck_pwrlvl <= 11) 3953 cck_pwrtable += 8; 3954 else 3955 cck_pwrtable += 16; 3956 } else { 3957 if (cck_pwrlvl <= 5) 3958 ; /* do nothing */ 3959 else if (cck_pwrlvl <= 11) 3960 cck_pwrtable += 8; 3961 else if (cck_pwrlvl <= 17) 3962 cck_pwrtable += 16; 3963 else 3964 cck_pwrtable += 24; 3965 } 3966 3967 for (i = 0; i < 8; i++) { 3968 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3969 } 3970 3971 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3972 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1); 3973 /* 3974 * Delay removed from 8185 to 8187. 3975 * usbd_delay_ms(sc->sc_udev, 1); 3976 */ 3977 3978 /* OFDM power setting */ 3979 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3980 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3981 3982 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3983 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3984 ofdm_pwrlvl = (ofdm_pwrlvl < 0) ? 0 : ofdm_pwrlvl; 3985 3986 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3987 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1); 3988 3989 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3990 if (ofdm_pwrlvl <= 11) { 3991 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60); 3992 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60); 3993 } else { 3994 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 3995 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 3996 } 3997 } else { 3998 if (ofdm_pwrlvl <= 11) { 3999 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 4000 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 4001 } else if (ofdm_pwrlvl <= 17) { 4002 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54); 4003 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54); 4004 } else { 4005 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50); 4006 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50); 4007 } 4008 } 4009 4010 /* 4011 * Delay removed from 8185 to 8187. 4012 * usbd_delay_ms(sc->sc_udev, 1); 4013 */ 4014 fail: 4015 return (error); 4016 } 4017 4018 int 4019 urtw_set_bssid(struct urtw_softc *sc, const uint8_t *bssid) 4020 { 4021 int error; 4022 4023 urtw_write32_m(sc, URTW_BSSID, 4024 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 4025 urtw_write16_m(sc, URTW_BSSID + 4, 4026 bssid[4] | bssid[5] << 8); 4027 4028 return 0; 4029 4030 fail: 4031 return error; 4032 } 4033 4034 int 4035 urtw_set_macaddr(struct urtw_softc *sc, const uint8_t *addr) 4036 { 4037 int error; 4038 4039 urtw_write32_m(sc, URTW_MAC0, 4040 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 4041 urtw_write16_m(sc, URTW_MAC4, 4042 addr[4] | addr[5] << 8); 4043 4044 return 0; 4045 4046 fail: 4047 return error; 4048 } 4049