1 /* $OpenBSD: if_urtw.c,v 1.62 2016/04/13 11:03:37 mpi Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Martynas Venckus <martynas@openbsd.org> 5 * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include "bpfilter.h" 21 22 #include <sys/param.h> 23 #include <sys/sockio.h> 24 #include <sys/mbuf.h> 25 #include <sys/kernel.h> 26 #include <sys/socket.h> 27 #include <sys/systm.h> 28 #include <sys/malloc.h> 29 #include <sys/timeout.h> 30 #include <sys/conf.h> 31 #include <sys/device.h> 32 #include <sys/endian.h> 33 34 #if NBPFILTER > 0 35 #include <net/bpf.h> 36 #endif 37 #include <net/if.h> 38 #include <net/if_dl.h> 39 #include <net/if_media.h> 40 41 #include <netinet/in.h> 42 #include <netinet/if_ether.h> 43 44 #include <net80211/ieee80211_var.h> 45 #include <net80211/ieee80211_radiotap.h> 46 47 #include <dev/usb/usb.h> 48 #include <dev/usb/usbdi.h> 49 #include <dev/usb/usbdi_util.h> 50 #include <dev/usb/usbdevs.h> 51 52 #include <dev/usb/if_urtwreg.h> 53 54 #ifdef URTW_DEBUG 55 #define DPRINTF(x) do { if (urtw_debug) printf x; } while (0) 56 #define DPRINTFN(n, x) do { if (urtw_debug >= (n)) printf x; } while (0) 57 int urtw_debug = 0; 58 #else 59 #define DPRINTF(x) 60 #define DPRINTFN(n, x) 61 #endif 62 63 /* 64 * Recognized device vendors/products. 65 */ 66 static const struct urtw_type { 67 struct usb_devno dev; 68 uint8_t rev; 69 } urtw_devs[] = { 70 #define URTW_DEV_RTL8187(v, p) \ 71 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, URTW_HWREV_8187 } 72 #define URTW_DEV_RTL8187B(v, p) \ 73 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, URTW_HWREV_8187B } 74 /* Realtek RTL8187 devices. */ 75 URTW_DEV_RTL8187(ASUS, P5B_WIFI), 76 URTW_DEV_RTL8187(DICKSMITH, RTL8187), 77 URTW_DEV_RTL8187(LINKSYS4, WUSB54GCV2), 78 URTW_DEV_RTL8187(LOGITEC, RTL8187), 79 URTW_DEV_RTL8187(NETGEAR, WG111V2), 80 URTW_DEV_RTL8187(REALTEK, RTL8187), 81 URTW_DEV_RTL8187(SITECOMEU, WL168V1), 82 URTW_DEV_RTL8187(SPHAIRON, RTL8187), 83 URTW_DEV_RTL8187(SURECOM, EP9001G2A), 84 /* Realtek RTL8187B devices. */ 85 URTW_DEV_RTL8187B(BELKIN, F5D7050E), 86 URTW_DEV_RTL8187B(NETGEAR, WG111V3), 87 URTW_DEV_RTL8187B(REALTEK, RTL8187B_0), 88 URTW_DEV_RTL8187B(REALTEK, RTL8187B_1), 89 URTW_DEV_RTL8187B(REALTEK, RTL8187B_2), 90 URTW_DEV_RTL8187B(SITECOMEU, WL168V4) 91 #undef URTW_DEV_RTL8187 92 #undef URTW_DEV_RTL8187B 93 }; 94 #define urtw_lookup(v, p) \ 95 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p)) 96 97 /* 98 * Helper read/write macros. 99 */ 100 #define urtw_read8_m(sc, val, data) do { \ 101 error = urtw_read8_c(sc, val, data, 0); \ 102 if (error != 0) \ 103 goto fail; \ 104 } while (0) 105 #define urtw_read8_idx_m(sc, val, data, idx) do { \ 106 error = urtw_read8_c(sc, val, data, idx); \ 107 if (error != 0) \ 108 goto fail; \ 109 } while (0) 110 #define urtw_write8_m(sc, val, data) do { \ 111 error = urtw_write8_c(sc, val, data, 0); \ 112 if (error != 0) \ 113 goto fail; \ 114 } while (0) 115 #define urtw_write8_idx_m(sc, val, data, idx) do { \ 116 error = urtw_write8_c(sc, val, data, idx); \ 117 if (error != 0) \ 118 goto fail; \ 119 } while (0) 120 #define urtw_read16_m(sc, val, data) do { \ 121 error = urtw_read16_c(sc, val, data, 0); \ 122 if (error != 0) \ 123 goto fail; \ 124 } while (0) 125 #define urtw_read16_idx_m(sc, val, data, idx) do { \ 126 error = urtw_read16_c(sc, val, data, idx); \ 127 if (error != 0) \ 128 goto fail; \ 129 } while (0) 130 #define urtw_write16_m(sc, val, data) do { \ 131 error = urtw_write16_c(sc, val, data, 0); \ 132 if (error != 0) \ 133 goto fail; \ 134 } while (0) 135 #define urtw_write16_idx_m(sc, val, data, idx) do { \ 136 error = urtw_write16_c(sc, val, data, idx); \ 137 if (error != 0) \ 138 goto fail; \ 139 } while (0) 140 #define urtw_read32_m(sc, val, data) do { \ 141 error = urtw_read32_c(sc, val, data, 0); \ 142 if (error != 0) \ 143 goto fail; \ 144 } while (0) 145 #define urtw_read32_idx_m(sc, val, data, idx) do { \ 146 error = urtw_read32_c(sc, val, data, idx); \ 147 if (error != 0) \ 148 goto fail; \ 149 } while (0) 150 #define urtw_write32_m(sc, val, data) do { \ 151 error = urtw_write32_c(sc, val, data, 0); \ 152 if (error != 0) \ 153 goto fail; \ 154 } while (0) 155 #define urtw_write32_idx_m(sc, val, data, idx) do { \ 156 error = urtw_write32_c(sc, val, data, idx); \ 157 if (error != 0) \ 158 goto fail; \ 159 } while (0) 160 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \ 161 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \ 162 if (error != 0) \ 163 goto fail; \ 164 } while (0) 165 #define urtw_8187_write_phy_cck(sc, val, data) do { \ 166 error = urtw_8187_write_phy_cck_c(sc, val, data); \ 167 if (error != 0) \ 168 goto fail; \ 169 } while (0) 170 #define urtw_8225_write(sc, val, data) do { \ 171 error = urtw_8225_write_c(sc, val, data); \ 172 if (error != 0) \ 173 goto fail; \ 174 } while (0) 175 176 struct urtw_pair { 177 uint32_t reg; 178 uint32_t val; 179 }; 180 181 struct urtw_pair_idx { 182 uint8_t reg; 183 uint8_t val; 184 uint8_t idx; 185 }; 186 187 static struct urtw_pair_idx urtw_8187b_regtbl[] = { 188 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 }, 189 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 }, 190 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 }, 191 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 }, 192 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 }, 193 { 0xff, 0x00, 0 }, 194 195 { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 }, { 0x5a, 0x4b, 1 }, 196 { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 }, { 0x61, 0x09, 1 }, 197 { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 }, { 0xce, 0x0f, 1 }, 198 { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 }, { 0xe1, 0x0f, 1 }, 199 { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 }, { 0xf1, 0x01, 1 }, 200 { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 }, { 0xf4, 0x04, 1 }, 201 { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 }, { 0xf7, 0x07, 1 }, 202 { 0xf8, 0x08, 1 }, 203 204 { 0x4e, 0x00, 2 }, { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, 205 { 0x22, 0x68, 2 }, { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, 206 { 0x25, 0x7d, 2 }, { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, 207 { 0x4d, 0x08, 2 }, { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, 208 { 0x52, 0x04, 2 }, { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, 209 { 0x55, 0x23, 2 }, { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, 210 { 0x58, 0x08, 2 }, { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, 211 { 0x5b, 0x08, 2 }, { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, 212 { 0x62, 0x08, 2 }, { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, 213 { 0x72, 0x56, 2 }, { 0x73, 0x9a, 2 }, 214 215 { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 }, { 0x5b, 0x40, 0 }, 216 { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 }, { 0x88, 0x54, 0 }, 217 { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 }, { 0x8d, 0x00, 0 }, 218 { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 }, { 0x96, 0x00, 0 }, 219 { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 }, { 0x9f, 0x10, 0 }, 220 { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 }, { 0xdb, 0x00, 0 }, 221 { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 }, 222 223 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 }, 224 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 } 225 }; 226 227 static uint8_t urtw_8225_agc[] = { 228 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b, 229 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 230 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85, 231 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 232 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 233 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 234 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 235 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 236 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 237 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 238 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 239 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 240 }; 241 242 static uint32_t urtw_8225_channel[] = { 243 0x0000, /* dummy channel 0 */ 244 0x085c, /* 1 */ 245 0x08dc, /* 2 */ 246 0x095c, /* 3 */ 247 0x09dc, /* 4 */ 248 0x0a5c, /* 5 */ 249 0x0adc, /* 6 */ 250 0x0b5c, /* 7 */ 251 0x0bdc, /* 8 */ 252 0x0c5c, /* 9 */ 253 0x0cdc, /* 10 */ 254 0x0d5c, /* 11 */ 255 0x0ddc, /* 12 */ 256 0x0e5c, /* 13 */ 257 0x0f72, /* 14 */ 258 }; 259 260 static uint8_t urtw_8225_gain[] = { 261 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */ 262 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */ 263 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */ 264 0x33, 0x80, 0x79, 0xc5, /* -78dbm */ 265 0x43, 0x78, 0x76, 0xc5, /* -74dbm */ 266 0x53, 0x60, 0x73, 0xc5, /* -70dbm */ 267 0x63, 0x58, 0x70, 0xc5, /* -66dbm */ 268 }; 269 270 static struct urtw_pair urtw_8225_rf_part1[] = { 271 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 272 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a }, 273 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 }, 274 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 } 275 }; 276 277 static struct urtw_pair urtw_8225_rf_part2[] = { 278 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 279 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 280 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 }, 281 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 }, 282 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 }, 283 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef }, 284 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 }, 285 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 }, 286 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 }, 287 { 0x27, 0x88 } 288 }; 289 290 static struct urtw_pair urtw_8225_rf_part3[] = { 291 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 292 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b }, 293 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, 294 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d }, 295 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e }, 296 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a }, 297 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 } 298 }; 299 300 static uint16_t urtw_8225_rxgain[] = { 301 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 302 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 303 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 304 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 305 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 306 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 307 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 308 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 309 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 310 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 311 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3, 312 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb 313 }; 314 315 static uint8_t urtw_8225_threshold[] = { 316 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd 317 }; 318 319 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = { 320 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e 321 }; 322 323 static uint8_t urtw_8225_txpwr_cck[] = { 324 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02, 325 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02, 326 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02, 327 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02, 328 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03, 329 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03 330 }; 331 332 static uint8_t urtw_8225_txpwr_cck_ch14[] = { 333 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00, 334 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00, 335 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00, 336 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00, 337 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00, 338 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00 339 }; 340 341 static uint8_t urtw_8225_txpwr_ofdm[] = { 342 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4 343 }; 344 345 static uint8_t urtw_8225v2_agc[] = { 346 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 347 0x55, 0x53, 0x51, 0x4f, 0x4d, 0x4b, 0x49, 0x47, 348 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x39, 0x37, 349 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 350 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 351 0x15, 0x13, 0x11, 0x0f, 0x0d, 0x0b, 0x09, 0x07, 352 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 353 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 354 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 355 0x19, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 356 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a, 357 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 358 0x2d, 0x2d, 0x2d, 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 359 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31, 0x31, 0x31, 360 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 361 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31 362 }; 363 364 static uint8_t urtw_8225v2_ofdm[] = { 365 0x10, 0x0d, 0x01, 0x00, 0x14, 0xfb, 0xfb, 0x60, 366 0x00, 0x60, 0x00, 0x00, 0x00, 0x5c, 0x00, 0x00, 367 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xa8, 0x26, 368 0x32, 0x33, 0x07, 0xa5, 0x6f, 0x55, 0xc8, 0xb3, 369 0x0a, 0xe1, 0x2c, 0x8a, 0x86, 0x83, 0x34, 0x0f, 370 0x4f, 0x24, 0x6f, 0xc2, 0x6b, 0x40, 0x80, 0x00, 371 0xc0, 0xc1, 0x58, 0xf1, 0x00, 0xe4, 0x90, 0x3e, 372 0x6d, 0x3c, 0xfb, 0x07 373 }; 374 375 static uint8_t urtw_8225v2_gain_bg[] = { 376 0x23, 0x15, 0xa5, /* -82-1dbm */ 377 0x23, 0x15, 0xb5, /* -82-2dbm */ 378 0x23, 0x15, 0xc5, /* -82-3dbm */ 379 0x33, 0x15, 0xc5, /* -78dbm */ 380 0x43, 0x15, 0xc5, /* -74dbm */ 381 0x53, 0x15, 0xc5, /* -70dbm */ 382 0x63, 0x15, 0xc5, /* -66dbm */ 383 }; 384 385 static struct urtw_pair urtw_8225v2_rf_part1[] = { 386 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 387 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 388 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 389 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 390 }; 391 392 static struct urtw_pair urtw_8225v2_rf_part2[] = { 393 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 394 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 395 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 }, 396 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, 397 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 }, 398 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, 399 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 }, 400 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 }, 401 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 }, 402 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 } 403 }; 404 405 static struct urtw_pair urtw_8225v2_rf_part3[] = { 406 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 407 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 }, 408 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 }, 409 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 }, 410 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d }, 411 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 }, 412 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 }, 413 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 } 414 }; 415 416 static uint16_t urtw_8225v2_rxgain[] = { 417 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 418 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 419 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 420 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 421 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 422 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 423 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 424 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 425 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 426 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 427 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 428 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 429 }; 430 431 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = { 432 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 433 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 434 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 435 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 436 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 437 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23 438 }; 439 440 static uint8_t urtw_8225v2_txpwr_cck[] = { 441 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04, 442 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03, 443 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03, 444 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03 445 }; 446 447 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = { 448 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00, 449 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 450 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 451 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00 452 }; 453 454 static struct urtw_pair urtw_8225v2_b_rf[] = { 455 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 456 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 457 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 458 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }, 459 { 0x00, 0x01b7 } 460 }; 461 462 static struct urtw_pair urtw_ratetable[] = { 463 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 }, 464 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 }, 465 { 96, 10 }, { 108, 11 } 466 }; 467 468 int urtw_init(struct ifnet *); 469 void urtw_stop(struct ifnet *, int); 470 int urtw_ioctl(struct ifnet *, u_long, caddr_t); 471 void urtw_start(struct ifnet *); 472 int urtw_alloc_rx_data_list(struct urtw_softc *); 473 void urtw_free_rx_data_list(struct urtw_softc *); 474 int urtw_alloc_tx_data_list(struct urtw_softc *); 475 void urtw_free_tx_data_list(struct urtw_softc *); 476 void urtw_rxeof(struct usbd_xfer *, void *, 477 usbd_status); 478 int urtw_tx_start(struct urtw_softc *, 479 struct ieee80211_node *, struct mbuf *, int); 480 void urtw_txeof_low(struct usbd_xfer *, void *, 481 usbd_status); 482 void urtw_txeof_normal(struct usbd_xfer *, void *, 483 usbd_status); 484 void urtw_next_scan(void *); 485 void urtw_task(void *); 486 void urtw_ledusbtask(void *); 487 void urtw_ledtask(void *); 488 int urtw_media_change(struct ifnet *); 489 int urtw_newstate(struct ieee80211com *, enum ieee80211_state, int); 490 void urtw_watchdog(struct ifnet *); 491 void urtw_set_multi(struct urtw_softc *); 492 void urtw_set_chan(struct urtw_softc *, struct ieee80211_channel *); 493 int urtw_isbmode(uint16_t); 494 uint16_t urtw_rate2rtl(int rate); 495 uint16_t urtw_rtl2rate(int); 496 usbd_status urtw_set_rate(struct urtw_softc *); 497 usbd_status urtw_update_msr(struct urtw_softc *); 498 usbd_status urtw_read8_c(struct urtw_softc *, int, uint8_t *, uint8_t); 499 usbd_status urtw_read16_c(struct urtw_softc *, int, uint16_t *, uint8_t); 500 usbd_status urtw_read32_c(struct urtw_softc *, int, uint32_t *, uint8_t); 501 usbd_status urtw_write8_c(struct urtw_softc *, int, uint8_t, uint8_t); 502 usbd_status urtw_write16_c(struct urtw_softc *, int, uint16_t, uint8_t); 503 usbd_status urtw_write32_c(struct urtw_softc *, int, uint32_t, uint8_t); 504 usbd_status urtw_eprom_cs(struct urtw_softc *, int); 505 usbd_status urtw_eprom_ck(struct urtw_softc *); 506 usbd_status urtw_eprom_sendbits(struct urtw_softc *, int16_t *, 507 int); 508 usbd_status urtw_eprom_read32(struct urtw_softc *, uint32_t, 509 uint32_t *); 510 usbd_status urtw_eprom_readbit(struct urtw_softc *, int16_t *); 511 usbd_status urtw_eprom_writebit(struct urtw_softc *, int16_t); 512 usbd_status urtw_get_macaddr(struct urtw_softc *); 513 usbd_status urtw_get_txpwr(struct urtw_softc *); 514 usbd_status urtw_get_rfchip(struct urtw_softc *); 515 usbd_status urtw_led_init(struct urtw_softc *); 516 usbd_status urtw_8185_rf_pins_enable(struct urtw_softc *); 517 usbd_status urtw_8185_tx_antenna(struct urtw_softc *, uint8_t); 518 usbd_status urtw_8187_write_phy(struct urtw_softc *, uint8_t, uint32_t); 519 usbd_status urtw_8187_write_phy_ofdm_c(struct urtw_softc *, uint8_t, 520 uint32_t); 521 usbd_status urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t, 522 uint32_t); 523 usbd_status urtw_8225_setgain(struct urtw_softc *, int16_t); 524 usbd_status urtw_8225_usb_init(struct urtw_softc *); 525 usbd_status urtw_8225_write_c(struct urtw_softc *, uint8_t, uint16_t); 526 usbd_status urtw_8225_write_s16(struct urtw_softc *, uint8_t, int, 527 uint16_t); 528 usbd_status urtw_8225_read(struct urtw_softc *, uint8_t, uint32_t *); 529 usbd_status urtw_8225_rf_init(struct urtw_rf *); 530 usbd_status urtw_8225_rf_set_chan(struct urtw_rf *, int); 531 usbd_status urtw_8225_rf_set_sens(struct urtw_rf *); 532 usbd_status urtw_8225_set_txpwrlvl(struct urtw_softc *, int); 533 usbd_status urtw_8225v2_rf_init(struct urtw_rf *); 534 usbd_status urtw_8225v2_rf_set_chan(struct urtw_rf *, int); 535 usbd_status urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int); 536 usbd_status urtw_8225v2_setgain(struct urtw_softc *, int16_t); 537 usbd_status urtw_8225_isv2(struct urtw_softc *, int *); 538 usbd_status urtw_read8e(struct urtw_softc *, int, uint8_t *); 539 usbd_status urtw_write8e(struct urtw_softc *, int, uint8_t); 540 usbd_status urtw_8180_set_anaparam(struct urtw_softc *, uint32_t); 541 usbd_status urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t); 542 usbd_status urtw_open_pipes(struct urtw_softc *); 543 usbd_status urtw_close_pipes(struct urtw_softc *); 544 usbd_status urtw_intr_enable(struct urtw_softc *); 545 usbd_status urtw_intr_disable(struct urtw_softc *); 546 usbd_status urtw_reset(struct urtw_softc *); 547 usbd_status urtw_led_on(struct urtw_softc *, int); 548 usbd_status urtw_led_ctl(struct urtw_softc *, int); 549 usbd_status urtw_led_blink(struct urtw_softc *); 550 usbd_status urtw_led_mode0(struct urtw_softc *, int); 551 usbd_status urtw_led_mode1(struct urtw_softc *, int); 552 usbd_status urtw_led_mode2(struct urtw_softc *, int); 553 usbd_status urtw_led_mode3(struct urtw_softc *, int); 554 usbd_status urtw_rx_setconf(struct urtw_softc *); 555 usbd_status urtw_rx_enable(struct urtw_softc *); 556 usbd_status urtw_tx_enable(struct urtw_softc *); 557 usbd_status urtw_8187b_update_wmm(struct urtw_softc *); 558 usbd_status urtw_8187b_reset(struct urtw_softc *); 559 int urtw_8187b_init(struct ifnet *); 560 usbd_status urtw_8225v2_b_config_mac(struct urtw_softc *); 561 usbd_status urtw_8225v2_b_init_rfe(struct urtw_softc *); 562 usbd_status urtw_8225v2_b_update_chan(struct urtw_softc *); 563 usbd_status urtw_8225v2_b_rf_init(struct urtw_rf *); 564 usbd_status urtw_8225v2_b_rf_set_chan(struct urtw_rf *, int); 565 usbd_status urtw_8225v2_b_set_txpwrlvl(struct urtw_softc *, int); 566 int urtw_set_bssid(struct urtw_softc *, const uint8_t *); 567 int urtw_set_macaddr(struct urtw_softc *, const uint8_t *); 568 569 int urtw_match(struct device *, void *, void *); 570 void urtw_attach(struct device *, struct device *, void *); 571 int urtw_detach(struct device *, int); 572 573 struct cfdriver urtw_cd = { 574 NULL, "urtw", DV_IFNET 575 }; 576 577 const struct cfattach urtw_ca = { 578 sizeof(struct urtw_softc), urtw_match, urtw_attach, urtw_detach 579 }; 580 581 int 582 urtw_match(struct device *parent, void *match, void *aux) 583 { 584 struct usb_attach_arg *uaa = aux; 585 586 if (uaa->iface == NULL || uaa->configno != 1) 587 return (UMATCH_NONE); 588 589 return ((urtw_lookup(uaa->vendor, uaa->product) != NULL) ? 590 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 591 } 592 593 void 594 urtw_attach(struct device *parent, struct device *self, void *aux) 595 { 596 struct urtw_softc *sc = (struct urtw_softc *)self; 597 struct usb_attach_arg *uaa = aux; 598 struct ieee80211com *ic = &sc->sc_ic; 599 struct ifnet *ifp = &ic->ic_if; 600 usbd_status error; 601 uint8_t data8; 602 uint32_t data; 603 int i; 604 605 sc->sc_udev = uaa->device; 606 sc->sc_iface = uaa->iface; 607 sc->sc_hwrev = urtw_lookup(uaa->vendor, uaa->product)->rev; 608 609 printf("%s: ", sc->sc_dev.dv_xname); 610 611 if (sc->sc_hwrev & URTW_HWREV_8187) { 612 urtw_read32_m(sc, URTW_TX_CONF, &data); 613 data &= URTW_TX_HWREV_MASK; 614 switch (data) { 615 case URTW_TX_HWREV_8187_D: 616 sc->sc_hwrev |= URTW_HWREV_8187_D; 617 printf("RTL8187 rev D"); 618 break; 619 case URTW_TX_HWREV_8187B_D: 620 /* 621 * Detect Realtek RTL8187B devices that use 622 * USB IDs of RTL8187. 623 */ 624 sc->sc_hwrev = URTW_HWREV_8187B | URTW_HWREV_8187B_B; 625 printf("RTL8187B rev B (early)"); 626 break; 627 default: 628 sc->sc_hwrev |= URTW_HWREV_8187_B; 629 printf("RTL8187 rev 0x%02x", data >> 25); 630 break; 631 } 632 } else { 633 /* RTL8187B hwrev register. */ 634 urtw_read8_m(sc, URTW_8187B_HWREV, &data8); 635 switch (data8) { 636 case URTW_8187B_HWREV_8187B_B: 637 sc->sc_hwrev |= URTW_HWREV_8187B_B; 638 printf("RTL8187B rev B"); 639 break; 640 case URTW_8187B_HWREV_8187B_D: 641 sc->sc_hwrev |= URTW_HWREV_8187B_D; 642 printf("RTL8187B rev D"); 643 break; 644 case URTW_8187B_HWREV_8187B_E: 645 sc->sc_hwrev |= URTW_HWREV_8187B_E; 646 printf("RTL8187B rev E"); 647 break; 648 default: 649 sc->sc_hwrev |= URTW_HWREV_8187B_B; 650 printf("RTL8187B rev 0x%02x", data8); 651 break; 652 } 653 } 654 655 urtw_read32_m(sc, URTW_RX, &data); 656 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 : 657 URTW_EEPROM_93C46; 658 659 error = urtw_get_rfchip(sc); 660 if (error != 0) 661 goto fail; 662 error = urtw_get_macaddr(sc); 663 if (error != 0) 664 goto fail; 665 error = urtw_get_txpwr(sc); 666 if (error != 0) 667 goto fail; 668 error = urtw_led_init(sc); /* XXX incompleted */ 669 if (error != 0) 670 goto fail; 671 672 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY; 673 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY; 674 sc->sc_currate = 3; 675 /* XXX for what? */ 676 sc->sc_preamble_mode = 2; 677 678 usb_init_task(&sc->sc_task, urtw_task, sc, USB_TASK_TYPE_GENERIC); 679 usb_init_task(&sc->sc_ledtask, urtw_ledusbtask, sc, 680 USB_TASK_TYPE_GENERIC); 681 timeout_set(&sc->scan_to, urtw_next_scan, sc); 682 timeout_set(&sc->sc_led_ch, urtw_ledtask, sc); 683 684 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 685 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 686 ic->ic_state = IEEE80211_S_INIT; 687 688 /* set device capabilities */ 689 ic->ic_caps = 690 IEEE80211_C_MONITOR | /* monitor mode supported */ 691 IEEE80211_C_TXPMGT | /* tx power management */ 692 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 693 IEEE80211_C_SHSLOT | /* short slot time supported */ 694 IEEE80211_C_WEP | /* s/w WEP */ 695 IEEE80211_C_RSN; /* WPA/RSN */ 696 697 /* set supported .11b and .11g rates */ 698 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 699 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 700 701 /* set supported .11b and .11g channels (1 through 14) */ 702 for (i = 1; i <= 14; i++) { 703 ic->ic_channels[i].ic_freq = 704 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 705 ic->ic_channels[i].ic_flags = 706 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 707 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 708 } 709 710 ifp->if_softc = sc; 711 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 712 if (sc->sc_hwrev & URTW_HWREV_8187) { 713 sc->sc_init = urtw_init; 714 } else { 715 sc->sc_init = urtw_8187b_init; 716 } 717 ifp->if_ioctl = urtw_ioctl; 718 ifp->if_start = urtw_start; 719 ifp->if_watchdog = urtw_watchdog; 720 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 721 722 if_attach(ifp); 723 ieee80211_ifattach(ifp); 724 725 /* override state transition machine */ 726 sc->sc_newstate = ic->ic_newstate; 727 ic->ic_newstate = urtw_newstate; 728 ieee80211_media_init(ifp, urtw_media_change, ieee80211_media_status); 729 730 #if NBPFILTER > 0 731 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 732 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 733 734 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 735 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 736 sc->sc_rxtap.wr_ihdr.it_present = htole32(URTW_RX_RADIOTAP_PRESENT); 737 738 sc->sc_txtap_len = sizeof sc->sc_txtapu; 739 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 740 sc->sc_txtap.wt_ihdr.it_present = htole32(URTW_TX_RADIOTAP_PRESENT); 741 #endif 742 743 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 744 745 return; 746 fail: 747 printf(": %s failed!\n", __func__); 748 } 749 750 int 751 urtw_detach(struct device *self, int flags) 752 { 753 struct urtw_softc *sc = (struct urtw_softc *)self; 754 struct ifnet *ifp = &sc->sc_ic.ic_if; 755 int s; 756 757 s = splusb(); 758 759 if (timeout_initialized(&sc->scan_to)) 760 timeout_del(&sc->scan_to); 761 if (timeout_initialized(&sc->sc_led_ch)) 762 timeout_del(&sc->sc_led_ch); 763 764 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 765 usb_rem_wait_task(sc->sc_udev, &sc->sc_ledtask); 766 767 usbd_ref_wait(sc->sc_udev); 768 769 if (ifp->if_softc != NULL) { 770 ieee80211_ifdetach(ifp); /* free all nodes */ 771 if_detach(ifp); 772 } 773 774 /* abort and free xfers */ 775 urtw_free_tx_data_list(sc); 776 urtw_free_rx_data_list(sc); 777 urtw_close_pipes(sc); 778 779 splx(s); 780 781 return (0); 782 } 783 784 usbd_status 785 urtw_close_pipes(struct urtw_softc *sc) 786 { 787 usbd_status error = 0; 788 789 if (sc->sc_rxpipe != NULL) { 790 error = usbd_close_pipe(sc->sc_rxpipe); 791 if (error != 0) 792 goto fail; 793 sc->sc_rxpipe = NULL; 794 } 795 if (sc->sc_txpipe_low != NULL) { 796 error = usbd_close_pipe(sc->sc_txpipe_low); 797 if (error != 0) 798 goto fail; 799 sc->sc_txpipe_low = NULL; 800 } 801 if (sc->sc_txpipe_normal != NULL) { 802 error = usbd_close_pipe(sc->sc_txpipe_normal); 803 if (error != 0) 804 goto fail; 805 sc->sc_txpipe_normal = NULL; 806 } 807 fail: 808 return (error); 809 } 810 811 usbd_status 812 urtw_open_pipes(struct urtw_softc *sc) 813 { 814 usbd_status error; 815 816 /* 817 * NB: there is no way to distinguish each pipes so we need to hardcode 818 * pipe numbers 819 */ 820 821 /* tx pipe - low priority packets */ 822 if (sc->sc_hwrev & URTW_HWREV_8187) 823 error = usbd_open_pipe(sc->sc_iface, 0x2, 824 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_low); 825 else 826 error = usbd_open_pipe(sc->sc_iface, 0x6, 827 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_low); 828 if (error != 0) { 829 printf("%s: could not open Tx low pipe: %s\n", 830 sc->sc_dev.dv_xname, usbd_errstr(error)); 831 goto fail; 832 } 833 /* tx pipe - normal priority packets */ 834 if (sc->sc_hwrev & URTW_HWREV_8187) 835 error = usbd_open_pipe(sc->sc_iface, 0x3, 836 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_normal); 837 else 838 error = usbd_open_pipe(sc->sc_iface, 0x7, 839 USBD_EXCLUSIVE_USE, &sc->sc_txpipe_normal); 840 if (error != 0) { 841 printf("%s: could not open Tx normal pipe: %s\n", 842 sc->sc_dev.dv_xname, usbd_errstr(error)); 843 goto fail; 844 } 845 /* rx pipe */ 846 if (sc->sc_hwrev & URTW_HWREV_8187) 847 error = usbd_open_pipe(sc->sc_iface, 0x81, 848 USBD_EXCLUSIVE_USE, &sc->sc_rxpipe); 849 else 850 error = usbd_open_pipe(sc->sc_iface, 0x83, 851 USBD_EXCLUSIVE_USE, &sc->sc_rxpipe); 852 if (error != 0) { 853 printf("%s: could not open Rx pipe: %s\n", 854 sc->sc_dev.dv_xname, usbd_errstr(error)); 855 goto fail; 856 } 857 858 return (0); 859 fail: 860 (void)urtw_close_pipes(sc); 861 return (error); 862 } 863 864 int 865 urtw_alloc_rx_data_list(struct urtw_softc *sc) 866 { 867 int i, error; 868 869 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 870 struct urtw_rx_data *data = &sc->sc_rx_data[i]; 871 872 data->sc = sc; 873 874 data->xfer = usbd_alloc_xfer(sc->sc_udev); 875 if (data->xfer == NULL) { 876 printf("%s: could not allocate rx xfer\n", 877 sc->sc_dev.dv_xname); 878 error = ENOMEM; 879 goto fail; 880 } 881 882 if (usbd_alloc_buffer(data->xfer, URTW_RX_MAXSIZE) == NULL) { 883 printf("%s: could not allocate rx buffer\n", 884 sc->sc_dev.dv_xname); 885 error = ENOMEM; 886 goto fail; 887 } 888 889 MGETHDR(data->m, M_DONTWAIT, MT_DATA); 890 if (data->m == NULL) { 891 printf("%s: could not allocate rx mbuf\n", 892 sc->sc_dev.dv_xname); 893 error = ENOMEM; 894 goto fail; 895 } 896 MCLGET(data->m, M_DONTWAIT); 897 if (!(data->m->m_flags & M_EXT)) { 898 printf("%s: could not allocate rx mbuf cluster\n", 899 sc->sc_dev.dv_xname); 900 error = ENOMEM; 901 goto fail; 902 } 903 data->buf = mtod(data->m, uint8_t *); 904 } 905 906 return (0); 907 908 fail: 909 urtw_free_rx_data_list(sc); 910 return (error); 911 } 912 913 void 914 urtw_free_rx_data_list(struct urtw_softc *sc) 915 { 916 int i; 917 918 /* Make sure no transfers are pending. */ 919 if (sc->sc_rxpipe != NULL) 920 usbd_abort_pipe(sc->sc_rxpipe); 921 922 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 923 struct urtw_rx_data *data = &sc->sc_rx_data[i]; 924 925 if (data->xfer != NULL) { 926 usbd_free_xfer(data->xfer); 927 data->xfer = NULL; 928 } 929 if (data->m != NULL) { 930 m_freem(data->m); 931 data->m = NULL; 932 } 933 } 934 } 935 936 int 937 urtw_alloc_tx_data_list(struct urtw_softc *sc) 938 { 939 int i, error; 940 941 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) { 942 struct urtw_tx_data *data = &sc->sc_tx_data[i]; 943 944 data->sc = sc; 945 data->ni = NULL; 946 947 data->xfer = usbd_alloc_xfer(sc->sc_udev); 948 if (data->xfer == NULL) { 949 printf("%s: could not allocate tx xfer\n", 950 sc->sc_dev.dv_xname); 951 error = ENOMEM; 952 goto fail; 953 } 954 955 data->buf = usbd_alloc_buffer(data->xfer, URTW_TX_MAXSIZE); 956 if (data->buf == NULL) { 957 printf("%s: could not allocate tx buffer\n", 958 sc->sc_dev.dv_xname); 959 error = ENOMEM; 960 goto fail; 961 } 962 963 if (((unsigned long)data->buf) % 4) 964 printf("%s: warn: unaligned buffer %p\n", 965 sc->sc_dev.dv_xname, data->buf); 966 } 967 968 return (0); 969 970 fail: 971 urtw_free_tx_data_list(sc); 972 return (error); 973 } 974 975 void 976 urtw_free_tx_data_list(struct urtw_softc *sc) 977 { 978 struct ieee80211com *ic = &sc->sc_ic; 979 int i; 980 981 /* Make sure no transfers are pending. */ 982 if (sc->sc_txpipe_low != NULL) 983 usbd_abort_pipe(sc->sc_txpipe_low); 984 if (sc->sc_txpipe_normal != NULL) 985 usbd_abort_pipe(sc->sc_txpipe_normal); 986 987 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) { 988 struct urtw_tx_data *data = &sc->sc_tx_data[i]; 989 990 if (data->xfer != NULL) { 991 usbd_free_xfer(data->xfer); 992 data->xfer = NULL; 993 } 994 if (data->ni != NULL) { 995 ieee80211_release_node(ic, data->ni); 996 data->ni = NULL; 997 } 998 } 999 } 1000 1001 int 1002 urtw_media_change(struct ifnet *ifp) 1003 { 1004 struct urtw_softc *sc = ifp->if_softc; 1005 int error; 1006 1007 error = ieee80211_media_change(ifp); 1008 if (error != ENETRESET) 1009 return (error); 1010 1011 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1012 (IFF_UP | IFF_RUNNING)) 1013 sc->sc_init(ifp); 1014 1015 return (0); 1016 } 1017 1018 int 1019 urtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1020 { 1021 struct urtw_softc *sc = ic->ic_if.if_softc; 1022 1023 usb_rem_task(sc->sc_udev, &sc->sc_task); 1024 timeout_del(&sc->scan_to); 1025 1026 /* do it in a process context */ 1027 sc->sc_state = nstate; 1028 sc->sc_arg = arg; 1029 usb_add_task(sc->sc_udev, &sc->sc_task); 1030 1031 return (0); 1032 } 1033 1034 usbd_status 1035 urtw_led_init(struct urtw_softc *sc) 1036 { 1037 uint32_t rev; 1038 usbd_status error; 1039 1040 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr); 1041 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev); 1042 if (error != 0) 1043 goto fail; 1044 1045 switch (rev & URTW_EPROM_CID_MASK) { 1046 case URTW_EPROM_CID_ALPHA0: 1047 sc->sc_strategy = URTW_SW_LED_MODE1; 1048 break; 1049 case URTW_EPROM_CID_SERCOMM_PS: 1050 sc->sc_strategy = URTW_SW_LED_MODE3; 1051 break; 1052 case URTW_EPROM_CID_HW_LED: 1053 sc->sc_strategy = URTW_HW_LED; 1054 break; 1055 case URTW_EPROM_CID_RSVD0: 1056 case URTW_EPROM_CID_RSVD1: 1057 default: 1058 sc->sc_strategy = URTW_SW_LED_MODE0; 1059 break; 1060 } 1061 1062 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0; 1063 1064 fail: 1065 return (error); 1066 } 1067 1068 usbd_status 1069 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index, 1070 uint16_t data) 1071 { 1072 usb_device_request_t req; 1073 1074 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1075 req.bRequest = URTW_8187_SETREGS_REQ; 1076 USETW(req.wValue, addr); 1077 USETW(req.wIndex, index); 1078 USETW(req.wLength, sizeof(uint16_t)); 1079 1080 data = htole16(data); 1081 return (usbd_do_request(sc->sc_udev, &req, &data)); 1082 } 1083 1084 usbd_status 1085 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data) 1086 { 1087 int i; 1088 int16_t bit; 1089 uint8_t rlen = 12, wlen = 6; 1090 uint16_t o1, o2, o3, tmp; 1091 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27; 1092 uint32_t mask = 0x80000000, value = 0; 1093 usbd_status error; 1094 1095 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1); 1096 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2); 1097 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3); 1098 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | 0xf); 1099 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | 0xf); 1100 o1 &= ~0xf; 1101 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN); 1102 DELAY(5); 1103 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1); 1104 DELAY(5); 1105 1106 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) { 1107 bit = ((d2w & mask) != 0) ? 1 : 0; 1108 1109 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 1110 DELAY(2); 1111 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1112 URTW_BB_HOST_BANG_CLK); 1113 DELAY(2); 1114 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1115 URTW_BB_HOST_BANG_CLK); 1116 DELAY(2); 1117 mask = mask >> 1; 1118 if (i == 2) 1119 break; 1120 bit = ((d2w & mask) != 0) ? 1 : 0; 1121 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1122 URTW_BB_HOST_BANG_CLK); 1123 DELAY(2); 1124 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 1125 URTW_BB_HOST_BANG_CLK); 1126 DELAY(2); 1127 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 1128 DELAY(1); 1129 } 1130 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW | 1131 URTW_BB_HOST_BANG_CLK); 1132 DELAY(2); 1133 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW); 1134 DELAY(2); 1135 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW); 1136 DELAY(2); 1137 1138 mask = 0x800; 1139 for (i = 0; i < rlen; i++, mask = mask >> 1) { 1140 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1141 o1 | URTW_BB_HOST_BANG_RW); 1142 DELAY(2); 1143 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1144 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1145 DELAY(2); 1146 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1147 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1148 DELAY(2); 1149 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1150 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 1151 DELAY(2); 1152 1153 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp); 1154 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0); 1155 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 1156 o1 | URTW_BB_HOST_BANG_RW); 1157 DELAY(2); 1158 } 1159 1160 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN | 1161 URTW_BB_HOST_BANG_RW); 1162 DELAY(2); 1163 1164 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2); 1165 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3); 1166 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x3a0); 1167 1168 if (data != NULL) 1169 *data = value; 1170 fail: 1171 return (error); 1172 } 1173 1174 usbd_status 1175 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data) 1176 { 1177 uint16_t d80, d82, d84; 1178 usbd_status error; 1179 1180 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80); 1181 d80 &= 0xfff3; 1182 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82); 1183 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84); 1184 d84 &= 0xfff0; 1185 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | 0x0007); 1186 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | 0x0007); 1187 DELAY(10); 1188 1189 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1190 DELAY(2); 1191 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80); 1192 DELAY(10); 1193 1194 error = urtw_8225_write_s16(sc, addr, 0x8225, data); 1195 if (error != 0) 1196 goto fail; 1197 1198 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1199 DELAY(10); 1200 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 1201 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84); 1202 usbd_delay_ms(sc->sc_udev, 2); 1203 fail: 1204 return (error); 1205 } 1206 1207 usbd_status 1208 urtw_8225_isv2(struct urtw_softc *sc, int *ret) 1209 { 1210 uint32_t data; 1211 usbd_status error; 1212 1213 *ret = 1; 1214 1215 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0080); 1216 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x0080); 1217 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x0080); 1218 usbd_delay_ms(sc->sc_udev, 500); 1219 1220 urtw_8225_write(sc, 0x0, 0x1b7); 1221 1222 error = urtw_8225_read(sc, 0x8, &data); 1223 if (error != 0) 1224 goto fail; 1225 if (data != 0x588) 1226 *ret = 0; 1227 else { 1228 error = urtw_8225_read(sc, 0x9, &data); 1229 if (error != 0) 1230 goto fail; 1231 if (data != 0x700) 1232 *ret = 0; 1233 } 1234 1235 urtw_8225_write(sc, 0x0, 0xb7); 1236 fail: 1237 return (error); 1238 } 1239 1240 usbd_status 1241 urtw_get_rfchip(struct urtw_softc *sc) 1242 { 1243 struct urtw_rf *rf = &sc->sc_rf; 1244 int ret; 1245 uint32_t data; 1246 usbd_status error; 1247 1248 rf->rf_sc = sc; 1249 1250 if (sc->sc_hwrev & URTW_HWREV_8187) { 1251 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data); 1252 if (error != 0) 1253 goto fail; 1254 switch (data & 0xff) { 1255 case URTW_EPROM_RFCHIPID_RTL8225U: 1256 error = urtw_8225_isv2(sc, &ret); 1257 if (error != 0) 1258 goto fail; 1259 if (ret == 0) { 1260 rf->init = urtw_8225_rf_init; 1261 rf->set_chan = urtw_8225_rf_set_chan; 1262 rf->set_sens = urtw_8225_rf_set_sens; 1263 printf(", RFv1"); 1264 } else { 1265 rf->init = urtw_8225v2_rf_init; 1266 rf->set_chan = urtw_8225v2_rf_set_chan; 1267 rf->set_sens = NULL; 1268 printf(", RFv2"); 1269 } 1270 break; 1271 default: 1272 goto fail; 1273 } 1274 } else { 1275 rf->init = urtw_8225v2_b_rf_init; 1276 rf->set_chan = urtw_8225v2_b_rf_set_chan; 1277 rf->set_sens = NULL; 1278 } 1279 1280 rf->max_sens = URTW_8225_RF_MAX_SENS; 1281 rf->sens = URTW_8225_RF_DEF_SENS; 1282 1283 return (0); 1284 1285 fail: 1286 printf("unsupported RF chip %d", data & 0xff); 1287 return (error); 1288 } 1289 1290 usbd_status 1291 urtw_get_txpwr(struct urtw_softc *sc) 1292 { 1293 int i, j; 1294 uint32_t data; 1295 usbd_status error; 1296 1297 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data); 1298 if (error != 0) 1299 goto fail; 1300 sc->sc_txpwr_cck_base = data & 0xf; 1301 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf; 1302 1303 for (i = 1, j = 0; i < 6; i += 2, j++) { 1304 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data); 1305 if (error != 0) 1306 goto fail; 1307 sc->sc_txpwr_cck[i] = data & 0xf; 1308 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8; 1309 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4; 1310 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12; 1311 } 1312 for (i = 1, j = 0; i < 4; i += 2, j++) { 1313 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data); 1314 if (error != 0) 1315 goto fail; 1316 sc->sc_txpwr_cck[i + 6] = data & 0xf; 1317 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8; 1318 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4; 1319 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12; 1320 } 1321 if (sc->sc_hwrev & URTW_HWREV_8187) { 1322 for (i = 1, j = 0; i < 4; i += 2, j++) { 1323 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j, 1324 &data); 1325 if (error != 0) 1326 goto fail; 1327 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf; 1328 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8; 1329 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4; 1330 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = 1331 (data & 0xf000) >> 12; 1332 } 1333 } else { 1334 /* Channel 11. */ 1335 error = urtw_eprom_read32(sc, 0x1b, &data); 1336 if (error != 0) 1337 goto fail; 1338 sc->sc_txpwr_cck[11] = data & 0xf; 1339 sc->sc_txpwr_ofdm[11] = (data & 0xf0) >> 4; 1340 1341 /* Channel 12. */ 1342 error = urtw_eprom_read32(sc, 0xa, &data); 1343 if (error != 0) 1344 goto fail; 1345 sc->sc_txpwr_cck[12] = data & 0xf; 1346 sc->sc_txpwr_ofdm[12] = (data & 0xf0) >> 4; 1347 1348 /* Channel 13, 14. */ 1349 error = urtw_eprom_read32(sc, 0x1c, &data); 1350 if (error != 0) 1351 goto fail; 1352 sc->sc_txpwr_cck[13] = data & 0xf; 1353 sc->sc_txpwr_ofdm[13] = (data & 0xf0) >> 4; 1354 sc->sc_txpwr_cck[14] = (data & 0xf00) >> 8; 1355 sc->sc_txpwr_ofdm[14] = (data & 0xf000) >> 12; 1356 } 1357 fail: 1358 return (error); 1359 } 1360 1361 usbd_status 1362 urtw_get_macaddr(struct urtw_softc *sc) 1363 { 1364 struct ieee80211com *ic = &sc->sc_ic; 1365 usbd_status error; 1366 uint32_t data; 1367 1368 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data); 1369 if (error != 0) 1370 goto fail; 1371 ic->ic_myaddr[0] = data & 0xff; 1372 ic->ic_myaddr[1] = (data & 0xff00) >> 8; 1373 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data); 1374 if (error != 0) 1375 goto fail; 1376 ic->ic_myaddr[2] = data & 0xff; 1377 ic->ic_myaddr[3] = (data & 0xff00) >> 8; 1378 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data); 1379 if (error != 0) 1380 goto fail; 1381 ic->ic_myaddr[4] = data & 0xff; 1382 ic->ic_myaddr[5] = (data & 0xff00) >> 8; 1383 fail: 1384 return (error); 1385 } 1386 1387 usbd_status 1388 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data) 1389 { 1390 #define URTW_READCMD_LEN 3 1391 int addrlen, i; 1392 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 }; 1393 usbd_status error; 1394 1395 /* NB: make sure the buffer is initialized */ 1396 *data = 0; 1397 1398 /* enable EPROM programming */ 1399 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE); 1400 DELAY(URTW_EPROM_DELAY); 1401 1402 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE); 1403 if (error != 0) 1404 goto fail; 1405 error = urtw_eprom_ck(sc); 1406 if (error != 0) 1407 goto fail; 1408 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN); 1409 if (error != 0) 1410 goto fail; 1411 if (sc->sc_epromtype == URTW_EEPROM_93C56) { 1412 addrlen = 8; 1413 addrstr[0] = addr & (1 << 7); 1414 addrstr[1] = addr & (1 << 6); 1415 addrstr[2] = addr & (1 << 5); 1416 addrstr[3] = addr & (1 << 4); 1417 addrstr[4] = addr & (1 << 3); 1418 addrstr[5] = addr & (1 << 2); 1419 addrstr[6] = addr & (1 << 1); 1420 addrstr[7] = addr & (1 << 0); 1421 } else { 1422 addrlen=6; 1423 addrstr[0] = addr & (1 << 5); 1424 addrstr[1] = addr & (1 << 4); 1425 addrstr[2] = addr & (1 << 3); 1426 addrstr[3] = addr & (1 << 2); 1427 addrstr[4] = addr & (1 << 1); 1428 addrstr[5] = addr & (1 << 0); 1429 } 1430 error = urtw_eprom_sendbits(sc, addrstr, addrlen); 1431 if (error != 0) 1432 goto fail; 1433 1434 error = urtw_eprom_writebit(sc, 0); 1435 if (error != 0) 1436 goto fail; 1437 1438 for (i = 0; i < 16; i++) { 1439 error = urtw_eprom_ck(sc); 1440 if (error != 0) 1441 goto fail; 1442 error = urtw_eprom_readbit(sc, &data16); 1443 if (error != 0) 1444 goto fail; 1445 1446 (*data) |= (data16 << (15 - i)); 1447 } 1448 1449 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE); 1450 if (error != 0) 1451 goto fail; 1452 error = urtw_eprom_ck(sc); 1453 if (error != 0) 1454 goto fail; 1455 1456 /* now disable EPROM programming */ 1457 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE); 1458 fail: 1459 return (error); 1460 #undef URTW_READCMD_LEN 1461 } 1462 1463 usbd_status 1464 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data) 1465 { 1466 uint8_t data8; 1467 usbd_status error; 1468 1469 urtw_read8_m(sc, URTW_EPROM_CMD, &data8); 1470 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0; 1471 DELAY(URTW_EPROM_DELAY); 1472 1473 fail: 1474 return (error); 1475 } 1476 1477 usbd_status 1478 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen) 1479 { 1480 int i = 0; 1481 usbd_status error = 0; 1482 1483 for (i = 0; i < buflen; i++) { 1484 error = urtw_eprom_writebit(sc, buf[i]); 1485 if (error != 0) 1486 goto fail; 1487 error = urtw_eprom_ck(sc); 1488 if (error != 0) 1489 goto fail; 1490 } 1491 fail: 1492 return (error); 1493 } 1494 1495 usbd_status 1496 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit) 1497 { 1498 uint8_t data; 1499 usbd_status error; 1500 1501 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1502 if (bit != 0) 1503 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT); 1504 else 1505 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT); 1506 DELAY(URTW_EPROM_DELAY); 1507 fail: 1508 return (error); 1509 } 1510 1511 usbd_status 1512 urtw_eprom_ck(struct urtw_softc *sc) 1513 { 1514 uint8_t data; 1515 usbd_status error; 1516 1517 /* masking */ 1518 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1519 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK); 1520 DELAY(URTW_EPROM_DELAY); 1521 /* unmasking */ 1522 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1523 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK); 1524 DELAY(URTW_EPROM_DELAY); 1525 fail: 1526 return (error); 1527 } 1528 1529 usbd_status 1530 urtw_eprom_cs(struct urtw_softc *sc, int able) 1531 { 1532 uint8_t data; 1533 usbd_status error; 1534 1535 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1536 if (able == URTW_EPROM_ENABLE) 1537 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS); 1538 else 1539 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS); 1540 DELAY(URTW_EPROM_DELAY); 1541 fail: 1542 return (error); 1543 } 1544 1545 usbd_status 1546 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data, uint8_t idx) 1547 { 1548 usb_device_request_t req; 1549 usbd_status error; 1550 1551 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1552 req.bRequest = URTW_8187_GETREGS_REQ; 1553 USETW(req.wValue, val | 0xff00); 1554 USETW(req.wIndex, idx & 0x03); 1555 USETW(req.wLength, sizeof(uint8_t)); 1556 1557 error = usbd_do_request(sc->sc_udev, &req, data); 1558 return (error); 1559 } 1560 1561 usbd_status 1562 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data) 1563 { 1564 usb_device_request_t req; 1565 usbd_status error; 1566 1567 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1568 req.bRequest = URTW_8187_GETREGS_REQ; 1569 USETW(req.wValue, val | 0xfe00); 1570 USETW(req.wIndex, 0); 1571 USETW(req.wLength, sizeof(uint8_t)); 1572 1573 error = usbd_do_request(sc->sc_udev, &req, data); 1574 return (error); 1575 } 1576 1577 usbd_status 1578 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data, uint8_t idx) 1579 { 1580 usb_device_request_t req; 1581 usbd_status error; 1582 1583 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1584 req.bRequest = URTW_8187_GETREGS_REQ; 1585 USETW(req.wValue, val | 0xff00); 1586 USETW(req.wIndex, idx & 0x03); 1587 USETW(req.wLength, sizeof(uint16_t)); 1588 1589 error = usbd_do_request(sc->sc_udev, &req, data); 1590 *data = letoh16(*data); 1591 return (error); 1592 } 1593 1594 usbd_status 1595 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data, uint8_t idx) 1596 { 1597 usb_device_request_t req; 1598 usbd_status error; 1599 1600 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1601 req.bRequest = URTW_8187_GETREGS_REQ; 1602 USETW(req.wValue, val | 0xff00); 1603 USETW(req.wIndex, idx & 0x03); 1604 USETW(req.wLength, sizeof(uint32_t)); 1605 1606 error = usbd_do_request(sc->sc_udev, &req, data); 1607 *data = letoh32(*data); 1608 return (error); 1609 } 1610 1611 usbd_status 1612 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data, uint8_t idx) 1613 { 1614 usb_device_request_t req; 1615 1616 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1617 req.bRequest = URTW_8187_SETREGS_REQ; 1618 USETW(req.wValue, val | 0xff00); 1619 USETW(req.wIndex, idx & 0x03); 1620 USETW(req.wLength, sizeof(uint8_t)); 1621 1622 return (usbd_do_request(sc->sc_udev, &req, &data)); 1623 } 1624 1625 usbd_status 1626 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data) 1627 { 1628 usb_device_request_t req; 1629 1630 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1631 req.bRequest = URTW_8187_SETREGS_REQ; 1632 USETW(req.wValue, val | 0xfe00); 1633 USETW(req.wIndex, 0); 1634 USETW(req.wLength, sizeof(uint8_t)); 1635 1636 return (usbd_do_request(sc->sc_udev, &req, &data)); 1637 } 1638 1639 usbd_status 1640 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data, uint8_t idx) 1641 { 1642 usb_device_request_t req; 1643 1644 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1645 req.bRequest = URTW_8187_SETREGS_REQ; 1646 USETW(req.wValue, val | 0xff00); 1647 USETW(req.wIndex, idx & 0x03); 1648 USETW(req.wLength, sizeof(uint16_t)); 1649 1650 data = htole16(data); 1651 return (usbd_do_request(sc->sc_udev, &req, &data)); 1652 } 1653 1654 usbd_status 1655 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data, uint8_t idx) 1656 { 1657 usb_device_request_t req; 1658 1659 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1660 req.bRequest = URTW_8187_SETREGS_REQ; 1661 USETW(req.wValue, val | 0xff00); 1662 USETW(req.wIndex, idx & 0x03); 1663 USETW(req.wLength, sizeof(uint32_t)); 1664 1665 data = htole32(data); 1666 return (usbd_do_request(sc->sc_udev, &req, &data)); 1667 } 1668 1669 static usbd_status 1670 urtw_set_mode(struct urtw_softc *sc, uint32_t mode) 1671 { 1672 uint8_t data; 1673 usbd_status error; 1674 1675 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1676 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT); 1677 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK); 1678 urtw_write8_m(sc, URTW_EPROM_CMD, data); 1679 fail: 1680 return (error); 1681 } 1682 1683 usbd_status 1684 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val) 1685 { 1686 uint8_t data; 1687 usbd_status error; 1688 1689 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1690 if (error) 1691 goto fail; 1692 1693 urtw_read8_m(sc, URTW_CONFIG3, &data); 1694 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 1695 urtw_write32_m(sc, URTW_ANAPARAM, val); 1696 urtw_read8_m(sc, URTW_CONFIG3, &data); 1697 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 1698 1699 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1700 if (error) 1701 goto fail; 1702 fail: 1703 return (error); 1704 } 1705 1706 usbd_status 1707 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val) 1708 { 1709 uint8_t data; 1710 usbd_status error; 1711 1712 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1713 if (error) 1714 goto fail; 1715 1716 urtw_read8_m(sc, URTW_CONFIG3, &data); 1717 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 1718 urtw_write32_m(sc, URTW_ANAPARAM2, val); 1719 urtw_read8_m(sc, URTW_CONFIG3, &data); 1720 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 1721 1722 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1723 if (error) 1724 goto fail; 1725 fail: 1726 return (error); 1727 } 1728 1729 usbd_status 1730 urtw_intr_disable(struct urtw_softc *sc) 1731 { 1732 usbd_status error; 1733 1734 urtw_write16_m(sc, URTW_INTR_MASK, 0); 1735 fail: 1736 return (error); 1737 } 1738 1739 usbd_status 1740 urtw_reset(struct urtw_softc *sc) 1741 { 1742 uint8_t data; 1743 usbd_status error; 1744 1745 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 1746 if (error) 1747 goto fail; 1748 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 1749 if (error) 1750 goto fail; 1751 1752 error = urtw_intr_disable(sc); 1753 if (error) 1754 goto fail; 1755 usbd_delay_ms(sc->sc_udev, 100); 1756 1757 error = urtw_write8e(sc, 0x18, 0x10); 1758 if (error != 0) 1759 goto fail; 1760 error = urtw_write8e(sc, 0x18, 0x11); 1761 if (error != 0) 1762 goto fail; 1763 error = urtw_write8e(sc, 0x18, 0x00); 1764 if (error != 0) 1765 goto fail; 1766 usbd_delay_ms(sc->sc_udev, 100); 1767 1768 urtw_read8_m(sc, URTW_CMD, &data); 1769 data = (data & 2) | URTW_CMD_RST; 1770 urtw_write8_m(sc, URTW_CMD, data); 1771 usbd_delay_ms(sc->sc_udev, 100); 1772 1773 urtw_read8_m(sc, URTW_CMD, &data); 1774 if (data & URTW_CMD_RST) { 1775 printf("%s: reset timeout\n", sc->sc_dev.dv_xname); 1776 goto fail; 1777 } 1778 1779 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD); 1780 if (error) 1781 goto fail; 1782 usbd_delay_ms(sc->sc_udev, 100); 1783 1784 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 1785 if (error) 1786 goto fail; 1787 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 1788 if (error) 1789 goto fail; 1790 fail: 1791 return (error); 1792 } 1793 1794 usbd_status 1795 urtw_led_on(struct urtw_softc *sc, int type) 1796 { 1797 usbd_status error = 0; 1798 1799 if (type == URTW_LED_GPIO) { 1800 switch (sc->sc_gpio_ledpin) { 1801 case URTW_LED_PIN_GPIO0: 1802 urtw_write8_m(sc, URTW_GPIO, 0x01); 1803 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00); 1804 break; 1805 default: 1806 break; 1807 } 1808 } 1809 1810 sc->sc_gpio_ledon = 1; 1811 fail: 1812 return (error); 1813 } 1814 1815 static usbd_status 1816 urtw_led_off(struct urtw_softc *sc, int type) 1817 { 1818 usbd_status error = 0; 1819 1820 if (type == URTW_LED_GPIO) { 1821 switch (sc->sc_gpio_ledpin) { 1822 case URTW_LED_PIN_GPIO0: 1823 urtw_write8_m(sc, URTW_GPIO, 0x01); 1824 urtw_write8_m(sc, URTW_GP_ENABLE, 0x01); 1825 break; 1826 default: 1827 break; 1828 } 1829 } 1830 1831 sc->sc_gpio_ledon = 0; 1832 1833 fail: 1834 return (error); 1835 } 1836 1837 usbd_status 1838 urtw_led_mode0(struct urtw_softc *sc, int mode) 1839 { 1840 struct timeval t; 1841 1842 switch (mode) { 1843 case URTW_LED_CTL_POWER_ON: 1844 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK; 1845 break; 1846 case URTW_LED_CTL_TX: 1847 if (sc->sc_gpio_ledinprogress == 1) 1848 return (0); 1849 1850 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL; 1851 sc->sc_gpio_blinktime = 2; 1852 break; 1853 case URTW_LED_CTL_LINK: 1854 sc->sc_gpio_ledstate = URTW_LED_ON; 1855 break; 1856 default: 1857 break; 1858 } 1859 1860 switch (sc->sc_gpio_ledstate) { 1861 case URTW_LED_ON: 1862 if (sc->sc_gpio_ledinprogress != 0) 1863 break; 1864 urtw_led_on(sc, URTW_LED_GPIO); 1865 break; 1866 case URTW_LED_BLINK_NORMAL: 1867 if (sc->sc_gpio_ledinprogress != 0) 1868 break; 1869 sc->sc_gpio_ledinprogress = 1; 1870 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ? 1871 URTW_LED_OFF : URTW_LED_ON; 1872 t.tv_sec = 0; 1873 t.tv_usec = 100 * 1000L; 1874 if (!usbd_is_dying(sc->sc_udev)) 1875 timeout_add(&sc->sc_led_ch, tvtohz(&t)); 1876 break; 1877 case URTW_LED_POWER_ON_BLINK: 1878 urtw_led_on(sc, URTW_LED_GPIO); 1879 usbd_delay_ms(sc->sc_udev, 100); 1880 urtw_led_off(sc, URTW_LED_GPIO); 1881 break; 1882 default: 1883 break; 1884 } 1885 return (0); 1886 } 1887 1888 usbd_status 1889 urtw_led_mode1(struct urtw_softc *sc, int mode) 1890 { 1891 return (USBD_INVAL); 1892 } 1893 1894 usbd_status 1895 urtw_led_mode2(struct urtw_softc *sc, int mode) 1896 { 1897 return (USBD_INVAL); 1898 } 1899 1900 usbd_status 1901 urtw_led_mode3(struct urtw_softc *sc, int mode) 1902 { 1903 return (USBD_INVAL); 1904 } 1905 1906 void 1907 urtw_ledusbtask(void *arg) 1908 { 1909 struct urtw_softc *sc = arg; 1910 1911 if (sc->sc_strategy != URTW_SW_LED_MODE0) 1912 return; 1913 1914 urtw_led_blink(sc); 1915 } 1916 1917 void 1918 urtw_ledtask(void *arg) 1919 { 1920 struct urtw_softc *sc = arg; 1921 1922 /* 1923 * NB: to change a status of the led we need at least a sleep so we 1924 * can't do it here 1925 */ 1926 usb_add_task(sc->sc_udev, &sc->sc_ledtask); 1927 } 1928 1929 usbd_status 1930 urtw_led_ctl(struct urtw_softc *sc, int mode) 1931 { 1932 usbd_status error = 0; 1933 1934 switch (sc->sc_strategy) { 1935 case URTW_SW_LED_MODE0: 1936 error = urtw_led_mode0(sc, mode); 1937 break; 1938 case URTW_SW_LED_MODE1: 1939 error = urtw_led_mode1(sc, mode); 1940 break; 1941 case URTW_SW_LED_MODE2: 1942 error = urtw_led_mode2(sc, mode); 1943 break; 1944 case URTW_SW_LED_MODE3: 1945 error = urtw_led_mode3(sc, mode); 1946 break; 1947 default: 1948 break; 1949 } 1950 1951 return (error); 1952 } 1953 1954 usbd_status 1955 urtw_led_blink(struct urtw_softc *sc) 1956 { 1957 struct timeval t; 1958 uint8_t ing = 0; 1959 usbd_status error; 1960 1961 if (sc->sc_gpio_blinkstate == URTW_LED_ON) 1962 error = urtw_led_on(sc, URTW_LED_GPIO); 1963 else 1964 error = urtw_led_off(sc, URTW_LED_GPIO); 1965 sc->sc_gpio_blinktime--; 1966 if (sc->sc_gpio_blinktime == 0) 1967 ing = 1; 1968 else { 1969 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL && 1970 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY && 1971 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3) 1972 ing = 1; 1973 } 1974 if (ing == 1) { 1975 if (sc->sc_gpio_ledstate == URTW_LED_ON && 1976 sc->sc_gpio_ledon == 0) 1977 error = urtw_led_on(sc, URTW_LED_GPIO); 1978 else if (sc->sc_gpio_ledstate == URTW_LED_OFF && 1979 sc->sc_gpio_ledon == 1) 1980 error = urtw_led_off(sc, URTW_LED_GPIO); 1981 1982 sc->sc_gpio_blinktime = 0; 1983 sc->sc_gpio_ledinprogress = 0; 1984 return (0); 1985 } 1986 1987 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ? 1988 URTW_LED_ON : URTW_LED_OFF; 1989 1990 switch (sc->sc_gpio_ledstate) { 1991 case URTW_LED_BLINK_NORMAL: 1992 t.tv_sec = 0; 1993 t.tv_usec = 100 * 1000L; 1994 if (!usbd_is_dying(sc->sc_udev)) 1995 timeout_add(&sc->sc_led_ch, tvtohz(&t)); 1996 break; 1997 default: 1998 break; 1999 } 2000 return (0); 2001 } 2002 2003 usbd_status 2004 urtw_update_msr(struct urtw_softc *sc) 2005 { 2006 struct ieee80211com *ic = &sc->sc_ic; 2007 uint8_t data; 2008 usbd_status error; 2009 2010 urtw_read8_m(sc, URTW_MSR, &data); 2011 data &= ~URTW_MSR_LINK_MASK; 2012 2013 /* Should always be set. */ 2014 if (sc->sc_hwrev & URTW_HWREV_8187B) 2015 data |= URTW_MSR_LINK_ENEDCA; 2016 2017 if (sc->sc_state == IEEE80211_S_RUN) { 2018 switch (ic->ic_opmode) { 2019 case IEEE80211_M_STA: 2020 case IEEE80211_M_MONITOR: 2021 data |= URTW_MSR_LINK_STA; 2022 break; 2023 default: 2024 break; 2025 } 2026 } else 2027 data |= URTW_MSR_LINK_NONE; 2028 2029 urtw_write8_m(sc, URTW_MSR, data); 2030 fail: 2031 return (error); 2032 } 2033 2034 uint16_t 2035 urtw_rate2rtl(int rate) 2036 { 2037 int i; 2038 2039 for (i = 0; i < nitems(urtw_ratetable); i++) { 2040 if (rate == urtw_ratetable[i].reg) 2041 return (urtw_ratetable[i].val); 2042 } 2043 2044 return (3); 2045 } 2046 2047 uint16_t 2048 urtw_rtl2rate(int rate) 2049 { 2050 int i; 2051 2052 for (i = 0; i < nitems(urtw_ratetable); i++) { 2053 if (rate == urtw_ratetable[i].val) 2054 return (urtw_ratetable[i].reg); 2055 } 2056 2057 return (0); 2058 } 2059 2060 usbd_status 2061 urtw_set_rate(struct urtw_softc *sc) 2062 { 2063 int i, basic_rate, min_rr_rate, max_rr_rate; 2064 uint16_t data; 2065 usbd_status error; 2066 2067 basic_rate = urtw_rate2rtl(48); 2068 min_rr_rate = urtw_rate2rtl(12); 2069 max_rr_rate = urtw_rate2rtl(48); 2070 2071 urtw_write8_m(sc, URTW_RESP_RATE, 2072 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT | 2073 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT); 2074 2075 urtw_read16_m(sc, URTW_8187_BRSR, &data); 2076 data &= ~URTW_BRSR_MBR_8185; 2077 2078 for (i = 0; i <= basic_rate; i++) 2079 data |= (1 << i); 2080 2081 urtw_write16_m(sc, URTW_8187_BRSR, data); 2082 fail: 2083 return (error); 2084 } 2085 2086 usbd_status 2087 urtw_intr_enable(struct urtw_softc *sc) 2088 { 2089 usbd_status error; 2090 2091 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff); 2092 fail: 2093 return (error); 2094 } 2095 2096 usbd_status 2097 urtw_rx_setconf(struct urtw_softc *sc) 2098 { 2099 struct ifnet *ifp = &sc->sc_ic.ic_if; 2100 struct ieee80211com *ic = &sc->sc_ic; 2101 uint32_t data; 2102 usbd_status error; 2103 2104 urtw_read32_m(sc, URTW_RX, &data); 2105 data = data &~ URTW_RX_FILTER_MASK; 2106 #if 0 2107 data = data | URTW_RX_FILTER_CTL; 2108 #endif 2109 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA; 2110 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST; 2111 2112 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2113 data = data | URTW_RX_FILTER_ICVERR; 2114 data = data | URTW_RX_FILTER_PWR; 2115 } 2116 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR) 2117 data = data | URTW_RX_FILTER_CRCERR; 2118 2119 if (ic->ic_opmode == IEEE80211_M_MONITOR || 2120 (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC))) { 2121 data = data | URTW_RX_FILTER_ALLMAC; 2122 } else { 2123 data = data | URTW_RX_FILTER_NICMAC; 2124 data = data | URTW_RX_CHECK_BSSID; 2125 } 2126 2127 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK; 2128 data = data | URTW_RX_FIFO_THRESHOLD_NONE | URTW_RX_AUTORESETPHY; 2129 data = data &~ URTW_MAX_RX_DMA_MASK; 2130 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT; 2131 2132 urtw_write32_m(sc, URTW_RX, data); 2133 fail: 2134 return (error); 2135 } 2136 2137 usbd_status 2138 urtw_rx_enable(struct urtw_softc *sc) 2139 { 2140 int i; 2141 struct urtw_rx_data *rx_data; 2142 uint8_t data; 2143 usbd_status error; 2144 2145 /* 2146 * Start up the receive pipe. 2147 */ 2148 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) { 2149 rx_data = &sc->sc_rx_data[i]; 2150 2151 usbd_setup_xfer(rx_data->xfer, sc->sc_rxpipe, rx_data, 2152 rx_data->buf, MCLBYTES, USBD_SHORT_XFER_OK, 2153 USBD_NO_TIMEOUT, urtw_rxeof); 2154 error = usbd_transfer(rx_data->xfer); 2155 if (error != USBD_IN_PROGRESS && error != 0) { 2156 printf("%s: could not queue Rx transfer\n", 2157 sc->sc_dev.dv_xname); 2158 goto fail; 2159 } 2160 } 2161 2162 error = urtw_rx_setconf(sc); 2163 if (error != 0) 2164 goto fail; 2165 2166 urtw_read8_m(sc, URTW_CMD, &data); 2167 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE); 2168 fail: 2169 return (error); 2170 } 2171 2172 usbd_status 2173 urtw_tx_enable(struct urtw_softc *sc) 2174 { 2175 uint8_t data8; 2176 uint32_t data; 2177 usbd_status error; 2178 2179 if (sc->sc_hwrev & URTW_HWREV_8187) { 2180 urtw_read8_m(sc, URTW_CW_CONF, &data8); 2181 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | 2182 URTW_CW_CONF_PERPACKET_RETRY); 2183 urtw_write8_m(sc, URTW_CW_CONF, data8); 2184 2185 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 2186 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN; 2187 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL; 2188 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT; 2189 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 2190 2191 urtw_read32_m(sc, URTW_TX_CONF, &data); 2192 data &= ~URTW_TX_LOOPBACK_MASK; 2193 data |= URTW_TX_LOOPBACK_NONE; 2194 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 2195 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT; 2196 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT; 2197 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 2198 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW; 2199 data &= ~URTW_TX_SWPLCPLEN; 2200 data |= URTW_TX_NOICV; 2201 urtw_write32_m(sc, URTW_TX_CONF, data); 2202 } else { 2203 data = URTW_TX_DURPROCMODE | URTW_TX_DISREQQSIZE | 2204 URTW_TX_MXDMA_2048 | URTW_TX_SHORTRETRY | 2205 URTW_TX_LONGRETRY; 2206 urtw_write32_m(sc, URTW_TX_CONF, data); 2207 } 2208 2209 urtw_read8_m(sc, URTW_CMD, &data8); 2210 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE); 2211 fail: 2212 return (error); 2213 } 2214 2215 int 2216 urtw_init(struct ifnet *ifp) 2217 { 2218 struct urtw_softc *sc = ifp->if_softc; 2219 struct urtw_rf *rf = &sc->sc_rf; 2220 struct ieee80211com *ic = &sc->sc_ic; 2221 usbd_status error; 2222 int ret; 2223 2224 urtw_stop(ifp, 0); 2225 2226 error = urtw_reset(sc); 2227 if (error) 2228 goto fail; 2229 2230 urtw_write8_m(sc, 0x85, 0); 2231 urtw_write8_m(sc, URTW_GPIO, 0); 2232 2233 /* for led */ 2234 urtw_write8_m(sc, 0x85, 4); 2235 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON); 2236 if (error != 0) 2237 goto fail; 2238 2239 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2240 if (error) 2241 goto fail; 2242 2243 /* applying MAC address again. */ 2244 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 2245 error = urtw_set_macaddr(sc, ic->ic_myaddr); 2246 if (error) 2247 goto fail; 2248 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2249 if (error) 2250 goto fail; 2251 2252 error = urtw_update_msr(sc); 2253 if (error) 2254 goto fail; 2255 2256 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0); 2257 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 2258 urtw_write8_m(sc, URTW_RATE_FALLBACK, 0x81); 2259 error = urtw_set_rate(sc); 2260 if (error != 0) 2261 goto fail; 2262 2263 error = rf->init(rf); 2264 if (error != 0) 2265 goto fail; 2266 if (rf->set_sens != NULL) 2267 rf->set_sens(rf); 2268 2269 urtw_write16_m(sc, 0x5e, 1); 2270 urtw_write16_m(sc, 0xfe, 0x10); 2271 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80); 2272 urtw_write8_m(sc, 0xff, 0x60); 2273 urtw_write16_m(sc, 0x5e, 0); 2274 urtw_write8_m(sc, 0x85, 4); 2275 2276 error = urtw_intr_enable(sc); 2277 if (error != 0) 2278 goto fail; 2279 2280 /* reset softc variables */ 2281 sc->sc_txidx = sc->sc_tx_low_queued = sc->sc_tx_normal_queued = 0; 2282 sc->sc_txtimer = 0; 2283 2284 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 2285 error = urtw_open_pipes(sc); 2286 if (error != 0) 2287 goto fail; 2288 ret = urtw_alloc_rx_data_list(sc); 2289 if (error != 0) 2290 goto fail; 2291 ret = urtw_alloc_tx_data_list(sc); 2292 if (error != 0) 2293 goto fail; 2294 sc->sc_flags |= URTW_INIT_ONCE; 2295 } 2296 2297 error = urtw_rx_enable(sc); 2298 if (error != 0) 2299 goto fail; 2300 error = urtw_tx_enable(sc); 2301 if (error != 0) 2302 goto fail; 2303 2304 ifq_clr_oactive(&ifp->if_snd); 2305 ifp->if_flags |= IFF_RUNNING; 2306 2307 ifp->if_timer = 1; 2308 2309 if (ic->ic_opmode == IEEE80211_M_MONITOR) 2310 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 2311 else 2312 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2313 2314 return (0); 2315 fail: 2316 return (error); 2317 } 2318 2319 void 2320 urtw_set_multi(struct urtw_softc *sc) 2321 { 2322 struct arpcom *ac = &sc->sc_ic.ic_ac; 2323 struct ifnet *ifp = &ac->ac_if; 2324 2325 /* 2326 * XXX don't know how to set a device. Lack of docs. Just try to set 2327 * IFF_ALLMULTI flag here. 2328 */ 2329 ifp->if_flags |= IFF_ALLMULTI; 2330 } 2331 2332 int 2333 urtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2334 { 2335 struct urtw_softc *sc = ifp->if_softc; 2336 struct ieee80211com *ic = &sc->sc_ic; 2337 struct ifreq *ifr; 2338 int s, error = 0; 2339 2340 if (usbd_is_dying(sc->sc_udev)) 2341 return (ENXIO); 2342 2343 usbd_ref_incr(sc->sc_udev); 2344 2345 s = splnet(); 2346 2347 switch (cmd) { 2348 case SIOCSIFADDR: 2349 ifp->if_flags |= IFF_UP; 2350 /* FALLTHROUGH */ 2351 case SIOCSIFFLAGS: 2352 if (ifp->if_flags & IFF_UP) { 2353 /* 2354 * If only the PROMISC or ALLMULTI flag changes, then 2355 * don't do a full re-init of the chip, just update 2356 * the Rx filter. 2357 */ 2358 if ((ifp->if_flags & IFF_RUNNING) && 2359 ((ifp->if_flags ^ sc->sc_if_flags) & 2360 (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 2361 urtw_set_multi(sc); 2362 } else { 2363 if (!(ifp->if_flags & IFF_RUNNING)) 2364 sc->sc_init(ifp); 2365 } 2366 } else { 2367 if (ifp->if_flags & IFF_RUNNING) 2368 urtw_stop(ifp, 1); 2369 } 2370 sc->sc_if_flags = ifp->if_flags; 2371 break; 2372 2373 case SIOCADDMULTI: 2374 case SIOCDELMULTI: 2375 ifr = (struct ifreq *)data; 2376 error = (cmd == SIOCADDMULTI) ? 2377 ether_addmulti(ifr, &ic->ic_ac) : 2378 ether_delmulti(ifr, &ic->ic_ac); 2379 if (error == ENETRESET) { 2380 if (ifp->if_flags & IFF_RUNNING) 2381 urtw_set_multi(sc); 2382 error = 0; 2383 } 2384 break; 2385 2386 case SIOCS80211CHANNEL: 2387 /* 2388 * This allows for fast channel switching in monitor mode 2389 * (used by kismet). In IBSS mode, we must explicitly reset 2390 * the interface to generate a new beacon frame. 2391 */ 2392 error = ieee80211_ioctl(ifp, cmd, data); 2393 if (error == ENETRESET && 2394 ic->ic_opmode == IEEE80211_M_MONITOR) { 2395 urtw_set_chan(sc, ic->ic_ibss_chan); 2396 error = 0; 2397 } 2398 break; 2399 2400 default: 2401 error = ieee80211_ioctl(ifp, cmd, data); 2402 } 2403 2404 if (error == ENETRESET) { 2405 if ((ifp->if_flags & (IFF_RUNNING | IFF_UP)) == 2406 (IFF_RUNNING | IFF_UP)) 2407 sc->sc_init(ifp); 2408 error = 0; 2409 } 2410 2411 splx(s); 2412 2413 usbd_ref_decr(sc->sc_udev); 2414 2415 return (error); 2416 } 2417 2418 void 2419 urtw_start(struct ifnet *ifp) 2420 { 2421 struct urtw_softc *sc = ifp->if_softc; 2422 struct ieee80211com *ic = &sc->sc_ic; 2423 struct ieee80211_node *ni; 2424 struct mbuf *m0; 2425 2426 /* 2427 * net80211 may still try to send management frames even if the 2428 * IFF_RUNNING flag is not set... 2429 */ 2430 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 2431 return; 2432 2433 for (;;) { 2434 if (sc->sc_tx_low_queued >= URTW_TX_DATA_LIST_COUNT || 2435 sc->sc_tx_normal_queued >= URTW_TX_DATA_LIST_COUNT) { 2436 ifq_set_oactive(&ifp->if_snd); 2437 break; 2438 } 2439 2440 m0 = mq_dequeue(&ic->ic_mgtq); 2441 if (m0 != NULL) { 2442 ni = m0->m_pkthdr.ph_cookie; 2443 #if NBPFILTER > 0 2444 if (ic->ic_rawbpf != NULL) 2445 bpf_mtap(ic->ic_rawbpf, m0, BPF_DIRECTION_OUT); 2446 #endif 2447 if (urtw_tx_start(sc, ni, m0, URTW_PRIORITY_NORMAL) 2448 != 0) 2449 break; 2450 } else { 2451 if (ic->ic_state != IEEE80211_S_RUN) 2452 break; 2453 IFQ_DEQUEUE(&ifp->if_snd, m0); 2454 if (m0 == NULL) 2455 break; 2456 #if NBPFILTER > 0 2457 if (ifp->if_bpf != NULL) 2458 bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT); 2459 #endif 2460 m0 = ieee80211_encap(ifp, m0, &ni); 2461 if (m0 == NULL) 2462 continue; 2463 #if NBPFILTER > 0 2464 if (ic->ic_rawbpf != NULL) 2465 bpf_mtap(ic->ic_rawbpf, m0, BPF_DIRECTION_OUT); 2466 #endif 2467 if (urtw_tx_start(sc, ni, m0, URTW_PRIORITY_NORMAL) 2468 != 0) { 2469 if (ni != NULL) 2470 ieee80211_release_node(ic, ni); 2471 ifp->if_oerrors++; 2472 break; 2473 } 2474 } 2475 sc->sc_txtimer = 5; 2476 } 2477 } 2478 2479 void 2480 urtw_watchdog(struct ifnet *ifp) 2481 { 2482 struct urtw_softc *sc = ifp->if_softc; 2483 2484 ifp->if_timer = 0; 2485 2486 if (sc->sc_txtimer > 0) { 2487 if (--sc->sc_txtimer == 0) { 2488 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 2489 ifp->if_oerrors++; 2490 return; 2491 } 2492 ifp->if_timer = 1; 2493 } 2494 2495 ieee80211_watchdog(ifp); 2496 } 2497 2498 void 2499 urtw_txeof_low(struct usbd_xfer *xfer, void *priv, 2500 usbd_status status) 2501 { 2502 struct urtw_tx_data *data = priv; 2503 struct urtw_softc *sc = data->sc; 2504 struct ieee80211com *ic = &sc->sc_ic; 2505 struct ifnet *ifp = &ic->ic_if; 2506 int s; 2507 2508 if (status != USBD_NORMAL_COMPLETION) { 2509 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2510 return; 2511 2512 printf("%s: could not transmit buffer: %s\n", 2513 sc->sc_dev.dv_xname, usbd_errstr(status)); 2514 2515 if (status == USBD_STALLED) 2516 usbd_clear_endpoint_stall_async(sc->sc_txpipe_low); 2517 2518 ifp->if_oerrors++; 2519 return; 2520 } 2521 2522 s = splnet(); 2523 2524 ieee80211_release_node(ic, data->ni); 2525 data->ni = NULL; 2526 2527 sc->sc_txtimer = 0; 2528 ifp->if_opackets++; 2529 2530 sc->sc_tx_low_queued--; 2531 ifq_clr_oactive(&ifp->if_snd); 2532 urtw_start(ifp); 2533 2534 splx(s); 2535 } 2536 2537 void 2538 urtw_txeof_normal(struct usbd_xfer *xfer, void *priv, 2539 usbd_status status) 2540 { 2541 struct urtw_tx_data *data = priv; 2542 struct urtw_softc *sc = data->sc; 2543 struct ieee80211com *ic = &sc->sc_ic; 2544 struct ifnet *ifp = &ic->ic_if; 2545 int s; 2546 2547 if (status != USBD_NORMAL_COMPLETION) { 2548 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2549 return; 2550 2551 printf("%s: could not transmit buffer: %s\n", 2552 sc->sc_dev.dv_xname, usbd_errstr(status)); 2553 2554 if (status == USBD_STALLED) 2555 usbd_clear_endpoint_stall_async(sc->sc_txpipe_normal); 2556 2557 ifp->if_oerrors++; 2558 return; 2559 } 2560 2561 s = splnet(); 2562 2563 ieee80211_release_node(ic, data->ni); 2564 data->ni = NULL; 2565 2566 sc->sc_txtimer = 0; 2567 ifp->if_opackets++; 2568 2569 sc->sc_tx_normal_queued--; 2570 ifq_clr_oactive(&ifp->if_snd); 2571 urtw_start(ifp); 2572 2573 splx(s); 2574 } 2575 2576 int 2577 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0, 2578 int prior) 2579 { 2580 struct ieee80211com *ic = &sc->sc_ic; 2581 struct urtw_tx_data *data; 2582 struct ieee80211_frame *wh; 2583 struct ieee80211_key *k; 2584 usbd_status error; 2585 int xferlen; 2586 2587 wh = mtod(m0, struct ieee80211_frame *); 2588 2589 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2590 k = ieee80211_get_txkey(ic, wh, ni); 2591 2592 if ((m0 = ieee80211_encrypt(ic, m0, k)) == NULL) 2593 return (ENOBUFS); 2594 2595 /* packet header may have moved, reset our local pointer */ 2596 wh = mtod(m0, struct ieee80211_frame *); 2597 } 2598 2599 #if NBPFILTER > 0 2600 if (sc->sc_drvbpf != NULL) { 2601 struct mbuf mb; 2602 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap; 2603 2604 tap->wt_flags = 0; 2605 tap->wt_rate = 0; 2606 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 2607 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 2608 2609 mb.m_data = (caddr_t)tap; 2610 mb.m_len = sc->sc_txtap_len; 2611 mb.m_next = m0; 2612 mb.m_nextpkt = NULL; 2613 mb.m_type = 0; 2614 mb.m_flags = 0; 2615 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 2616 } 2617 #endif 2618 2619 if (sc->sc_hwrev & URTW_HWREV_8187) 2620 xferlen = m0->m_pkthdr.len + 4 * 3; 2621 else 2622 xferlen = m0->m_pkthdr.len + 4 * 8; 2623 2624 if ((0 == xferlen % 64) || (0 == xferlen % 512)) 2625 xferlen += 1; 2626 2627 data = &sc->sc_tx_data[sc->sc_txidx]; 2628 sc->sc_txidx = (sc->sc_txidx + 1) % URTW_TX_DATA_LIST_COUNT; 2629 2630 bzero(data->buf, URTW_TX_MAXSIZE); 2631 data->buf[0] = m0->m_pkthdr.len & 0xff; 2632 data->buf[1] = (m0->m_pkthdr.len & 0x0f00) >> 8; 2633 data->buf[1] |= (1 << 7); 2634 2635 /* XXX sc_preamble_mode is always 2. */ 2636 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 2637 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && 2638 (sc->sc_preamble_mode == 1) && (sc->sc_currate != 0)) 2639 data->buf[2] |= 1; 2640 if ((m0->m_pkthdr.len > ic->ic_rtsthreshold) && 2641 prior == URTW_PRIORITY_LOW) 2642 return ENOTSUP; /* TODO */ 2643 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 2644 data->buf[2] |= (1 << 1); 2645 /* RTS rate - 10 means we use a basic rate. */ 2646 data->buf[2] |= (urtw_rate2rtl(2) << 3); 2647 /* 2648 * XXX currently TX rate control depends on the rate value of 2649 * RX descriptor because I don't know how to we can control TX rate 2650 * in more smart way. Please fix me you find a thing. 2651 */ 2652 data->buf[3] = sc->sc_currate; 2653 if (prior == URTW_PRIORITY_NORMAL) { 2654 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 2655 data->buf[3] = urtw_rate2rtl(ni->ni_rates.rs_rates[0]); 2656 else if (ic->ic_fixed_rate != -1) 2657 data->buf[3] = urtw_rate2rtl(ic->ic_fixed_rate); 2658 } 2659 2660 if (sc->sc_hwrev & URTW_HWREV_8187) { 2661 data->buf[8] = 3; /* CW minimum */ 2662 data->buf[8] |= (7 << 4); /* CW maximum */ 2663 data->buf[9] |= 11; /* retry limitation */ 2664 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)&data->buf[12]); 2665 } else { 2666 data->buf[21] |= 11; /* retry limitation */ 2667 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)&data->buf[32]); 2668 } 2669 2670 data->ni = ni; 2671 2672 /* mbuf is no longer needed. */ 2673 m_freem(m0); 2674 2675 usbd_setup_xfer(data->xfer, 2676 (prior == URTW_PRIORITY_LOW) ? sc->sc_txpipe_low : 2677 sc->sc_txpipe_normal, data, data->buf, xferlen, 2678 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, URTW_DATA_TIMEOUT, 2679 (prior == URTW_PRIORITY_LOW) ? urtw_txeof_low : urtw_txeof_normal); 2680 error = usbd_transfer(data->xfer); 2681 if (error != USBD_IN_PROGRESS && error != USBD_NORMAL_COMPLETION) { 2682 printf("%s: could not send frame: %s\n", 2683 sc->sc_dev.dv_xname, usbd_errstr(error)); 2684 return (EIO); 2685 } 2686 2687 error = urtw_led_ctl(sc, URTW_LED_CTL_TX); 2688 if (error != 0) 2689 printf("%s: could not control LED (%d)\n", 2690 sc->sc_dev.dv_xname, error); 2691 2692 if (prior == URTW_PRIORITY_LOW) 2693 sc->sc_tx_low_queued++; 2694 else 2695 sc->sc_tx_normal_queued++; 2696 2697 return (0); 2698 } 2699 2700 usbd_status 2701 urtw_8225_usb_init(struct urtw_softc *sc) 2702 { 2703 uint8_t data; 2704 usbd_status error; 2705 2706 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0); 2707 urtw_write8_m(sc, URTW_GPIO, 0); 2708 error = urtw_read8e(sc, 0x53, &data); 2709 if (error) 2710 goto fail; 2711 error = urtw_write8e(sc, 0x53, data | (1 << 7)); 2712 if (error) 2713 goto fail; 2714 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4); 2715 urtw_write8_m(sc, URTW_GPIO, 0x20); 2716 urtw_write8_m(sc, URTW_GP_ENABLE, 0); 2717 2718 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80); 2719 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80); 2720 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80); 2721 2722 usbd_delay_ms(sc->sc_udev, 500); 2723 fail: 2724 return (error); 2725 } 2726 2727 usbd_status 2728 urtw_8185_rf_pins_enable(struct urtw_softc *sc) 2729 { 2730 usbd_status error = 0; 2731 2732 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7); 2733 fail: 2734 return (error); 2735 } 2736 2737 usbd_status 2738 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2739 { 2740 uint32_t phyw; 2741 usbd_status error; 2742 2743 phyw = ((data << 8) | (addr | 0x80)); 2744 urtw_write8_m(sc, 0x7f, ((phyw & 0xff000000) >> 24)); 2745 urtw_write8_m(sc, 0x7e, ((phyw & 0x00ff0000) >> 16)); 2746 urtw_write8_m(sc, 0x7d, ((phyw & 0x0000ff00) >> 8)); 2747 urtw_write8_m(sc, 0x7c, ((phyw & 0x000000ff))); 2748 /* 2749 * Delay removed from 8185 to 8187. 2750 * usbd_delay_ms(sc->sc_udev, 1); 2751 */ 2752 fail: 2753 return (error); 2754 } 2755 2756 usbd_status 2757 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2758 { 2759 data = data & 0xff; 2760 return (urtw_8187_write_phy(sc, addr, data)); 2761 } 2762 2763 usbd_status 2764 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2765 { 2766 data = data & 0xff; 2767 return (urtw_8187_write_phy(sc, addr, data | 0x10000)); 2768 } 2769 2770 usbd_status 2771 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain) 2772 { 2773 usbd_status error; 2774 2775 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]); 2776 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]); 2777 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]); 2778 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]); 2779 fail: 2780 return (error); 2781 } 2782 2783 usbd_status 2784 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan) 2785 { 2786 int i, idx, set; 2787 uint8_t *cck_pwltable; 2788 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max; 2789 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 2790 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 2791 usbd_status error; 2792 2793 cck_pwrlvl_max = 11; 2794 ofdm_pwrlvl_max = 25; /* 12 -> 25 */ 2795 ofdm_pwrlvl_min = 10; 2796 2797 /* CCK power setting */ 2798 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 2799 idx = cck_pwrlvl % 6; 2800 set = cck_pwrlvl / 6; 2801 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 : 2802 urtw_8225_txpwr_cck; 2803 2804 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 2805 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2806 for (i = 0; i < 8; i++) { 2807 urtw_8187_write_phy_cck(sc, 0x44 + i, 2808 cck_pwltable[idx * 8 + i]); 2809 } 2810 usbd_delay_ms(sc->sc_udev, 1); 2811 2812 /* OFDM power setting */ 2813 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 2814 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 2815 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 2816 2817 idx = ofdm_pwrlvl % 6; 2818 set = ofdm_pwrlvl / 6; 2819 2820 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 2821 if (error) 2822 goto fail; 2823 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 2824 urtw_8187_write_phy_ofdm(sc, 6, 0); 2825 urtw_8187_write_phy_ofdm(sc, 8, 0); 2826 2827 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 2828 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2829 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]); 2830 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]); 2831 usbd_delay_ms(sc->sc_udev, 1); 2832 fail: 2833 return (error); 2834 } 2835 2836 usbd_status 2837 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant) 2838 { 2839 usbd_status error; 2840 2841 urtw_write8_m(sc, URTW_TX_ANTENNA, ant); 2842 usbd_delay_ms(sc->sc_udev, 1); 2843 fail: 2844 return (error); 2845 } 2846 2847 usbd_status 2848 urtw_8225_rf_init(struct urtw_rf *rf) 2849 { 2850 struct urtw_softc *sc = rf->rf_sc; 2851 int i; 2852 uint16_t data; 2853 usbd_status error; 2854 2855 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 2856 if (error) 2857 goto fail; 2858 2859 error = urtw_8225_usb_init(sc); 2860 if (error) 2861 goto fail; 2862 2863 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2864 urtw_read16_m(sc, URTW_8187_BRSR, &data); /* XXX ??? */ 2865 urtw_write16_m(sc, URTW_8187_BRSR, 0xffff); 2866 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2867 2868 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2869 if (error) 2870 goto fail; 2871 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2872 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2873 if (error) 2874 goto fail; 2875 2876 error = urtw_8185_rf_pins_enable(sc); 2877 if (error) 2878 goto fail; 2879 2880 usbd_delay_ms(sc->sc_udev, 500); 2881 2882 for (i = 0; i < nitems(urtw_8225_rf_part1); i++) { 2883 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg, 2884 urtw_8225_rf_part1[i].val); 2885 } 2886 usbd_delay_ms(sc->sc_udev, 50); 2887 urtw_8225_write(sc, 0x2, 0xc4d); 2888 usbd_delay_ms(sc->sc_udev, 200); 2889 urtw_8225_write(sc, 0x2, 0x44d); 2890 usbd_delay_ms(sc->sc_udev, 200); 2891 urtw_8225_write(sc, 0x0, 0x127); 2892 2893 for (i = 0; i < nitems(urtw_8225_rxgain); i++) { 2894 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 2895 urtw_8225_write(sc, 0x2, urtw_8225_rxgain[i]); 2896 } 2897 2898 urtw_8225_write(sc, 0x0, 0x27); 2899 urtw_8225_write(sc, 0x0, 0x22f); 2900 2901 for (i = 0; i < nitems(urtw_8225_agc); i++) { 2902 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2903 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2904 } 2905 2906 for (i = 0; i < nitems(urtw_8225_rf_part2); i++) { 2907 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg, 2908 urtw_8225_rf_part2[i].val); 2909 usbd_delay_ms(sc->sc_udev, 1); 2910 } 2911 2912 error = urtw_8225_setgain(sc, 4); 2913 if (error) 2914 goto fail; 2915 2916 for (i = 0; i < nitems(urtw_8225_rf_part3); i++) { 2917 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg, 2918 urtw_8225_rf_part3[i].val); 2919 usbd_delay_ms(sc->sc_udev, 1); 2920 } 2921 2922 urtw_write8_m(sc, 0x5b, 0x0d); 2923 2924 error = urtw_8225_set_txpwrlvl(sc, 1); 2925 if (error) 2926 goto fail; 2927 2928 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2929 usbd_delay_ms(sc->sc_udev, 1); 2930 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2931 usbd_delay_ms(sc->sc_udev, 1); 2932 2933 /* TX ant A, 0x0 for B */ 2934 error = urtw_8185_tx_antenna(sc, 0x3); 2935 if (error) 2936 goto fail; 2937 urtw_write32_m(sc, 0x94, 0x3dc00002); 2938 2939 error = urtw_8225_rf_set_chan(rf, 1); 2940 fail: 2941 return (error); 2942 } 2943 2944 usbd_status 2945 urtw_8225_rf_set_chan(struct urtw_rf *rf, int chan) 2946 { 2947 struct urtw_softc *sc = rf->rf_sc; 2948 struct ieee80211com *ic = &sc->sc_ic; 2949 struct ieee80211_channel *c = ic->ic_ibss_chan; 2950 usbd_status error; 2951 2952 error = urtw_8225_set_txpwrlvl(sc, chan); 2953 if (error) 2954 goto fail; 2955 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 2956 usbd_delay_ms(sc->sc_udev, 10); 2957 2958 urtw_write8_m(sc, URTW_SIFS, 0x22); 2959 2960 if (sc->sc_state == IEEE80211_S_ASSOC && 2961 ic->ic_flags & IEEE80211_F_SHSLOT) 2962 urtw_write8_m(sc, URTW_SLOT, 0x9); 2963 else 2964 urtw_write8_m(sc, URTW_SLOT, 0x14); 2965 2966 if (IEEE80211_IS_CHAN_G(c)) { 2967 urtw_write8_m(sc, URTW_DIFS, 0x14); 2968 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x14); 2969 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 2970 } else { 2971 urtw_write8_m(sc, URTW_DIFS, 0x24); 2972 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x24); 2973 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 2974 } 2975 2976 fail: 2977 return (error); 2978 } 2979 2980 usbd_status 2981 urtw_8225_rf_set_sens(struct urtw_rf *rf) 2982 { 2983 struct urtw_softc *sc = rf->rf_sc; 2984 usbd_status error; 2985 2986 if (rf->sens > 6) 2987 return (-1); 2988 2989 if (rf->sens > 4) 2990 urtw_8225_write(sc, 0x0c, 0x850); 2991 else 2992 urtw_8225_write(sc, 0x0c, 0x50); 2993 2994 rf->sens = 6 - rf->sens; 2995 error = urtw_8225_setgain(sc, rf->sens); 2996 if (error) 2997 goto fail; 2998 2999 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[rf->sens]); 3000 3001 fail: 3002 return (error); 3003 } 3004 3005 void 3006 urtw_stop(struct ifnet *ifp, int disable) 3007 { 3008 struct urtw_softc *sc = ifp->if_softc; 3009 struct ieee80211com *ic = &sc->sc_ic; 3010 uint8_t data; 3011 usbd_status error; 3012 3013 ifp->if_flags &= ~IFF_RUNNING; 3014 ifq_clr_oactive(&ifp->if_snd); 3015 3016 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3017 3018 timeout_del(&sc->scan_to); 3019 timeout_del(&sc->sc_led_ch); 3020 3021 urtw_intr_disable(sc); 3022 urtw_read8_m(sc, URTW_CMD, &data); 3023 data &= ~URTW_CMD_TX_ENABLE; 3024 data &= ~URTW_CMD_RX_ENABLE; 3025 urtw_write8_m(sc, URTW_CMD, data); 3026 3027 if (sc->sc_rxpipe != NULL) 3028 usbd_abort_pipe(sc->sc_rxpipe); 3029 if (sc->sc_txpipe_low != NULL) 3030 usbd_abort_pipe(sc->sc_txpipe_low); 3031 if (sc->sc_txpipe_normal != NULL) 3032 usbd_abort_pipe(sc->sc_txpipe_normal); 3033 3034 fail: 3035 return; 3036 } 3037 3038 int 3039 urtw_isbmode(uint16_t rate) 3040 { 3041 rate = urtw_rtl2rate(rate); 3042 3043 return (((rate <= 22 && rate != 12 && rate != 18) || 3044 rate == 44) ? (1) : (0)); 3045 } 3046 3047 void 3048 urtw_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 3049 { 3050 struct urtw_rx_data *data = priv; 3051 struct urtw_softc *sc = data->sc; 3052 struct ieee80211com *ic = &sc->sc_ic; 3053 struct ifnet *ifp = &ic->ic_if; 3054 struct ieee80211_frame *wh; 3055 struct ieee80211_node *ni; 3056 struct ieee80211_rxinfo rxi; 3057 struct mbuf *m, *mnew; 3058 uint8_t *desc, quality, rate; 3059 int actlen, flen, len, nf, rssi, s; 3060 3061 if (status != USBD_NORMAL_COMPLETION) { 3062 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 3063 return; 3064 3065 if (status == USBD_STALLED) 3066 usbd_clear_endpoint_stall_async(sc->sc_rxpipe); 3067 ifp->if_ierrors++; 3068 goto skip; 3069 } 3070 3071 usbd_get_xfer_status(xfer, NULL, NULL, &actlen, NULL); 3072 if (actlen < URTW_MIN_RXBUFSZ) { 3073 ifp->if_ierrors++; 3074 goto skip; 3075 } 3076 3077 if (sc->sc_hwrev & URTW_HWREV_8187) 3078 /* 4 dword and 4 byte CRC */ 3079 len = actlen - (4 * 4); 3080 else 3081 /* 5 dword and 4 byte CRC */ 3082 len = actlen - (4 * 5); 3083 3084 desc = data->buf + len; 3085 flen = ((desc[1] & 0x0f) << 8) + (desc[0] & 0xff); 3086 if (flen > actlen) { 3087 ifp->if_ierrors++; 3088 goto skip; 3089 } 3090 3091 rate = (desc[2] & 0xf0) >> 4; 3092 if (sc->sc_hwrev & URTW_HWREV_8187) { 3093 quality = desc[4] & 0xff; 3094 rssi = (desc[6] & 0xfe) >> 1; 3095 3096 /* XXX correct? */ 3097 if (!urtw_isbmode(rate)) { 3098 rssi = (rssi > 90) ? 90 : ((rssi < 25) ? 25 : rssi); 3099 rssi = ((90 - rssi) * 100) / 65; 3100 } else { 3101 rssi = (rssi > 90) ? 95 : ((rssi < 30) ? 30 : rssi); 3102 rssi = ((95 - rssi) * 100) / 65; 3103 } 3104 } else { 3105 quality = desc[12]; 3106 rssi = 14 - desc[14] / 2; 3107 } 3108 3109 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 3110 if (mnew == NULL) { 3111 printf("%s: could not allocate rx mbuf\n", 3112 sc->sc_dev.dv_xname); 3113 ifp->if_ierrors++; 3114 goto skip; 3115 } 3116 MCLGET(mnew, M_DONTWAIT); 3117 if (!(mnew->m_flags & M_EXT)) { 3118 printf("%s: could not allocate rx mbuf cluster\n", 3119 sc->sc_dev.dv_xname); 3120 m_freem(mnew); 3121 ifp->if_ierrors++; 3122 goto skip; 3123 } 3124 3125 m = data->m; 3126 data->m = mnew; 3127 data->buf = mtod(mnew, uint8_t *); 3128 3129 /* finalize mbuf */ 3130 m->m_pkthdr.len = m->m_len = flen - 4; 3131 3132 s = splnet(); 3133 3134 #if NBPFILTER > 0 3135 if (sc->sc_drvbpf != NULL) { 3136 struct mbuf mb; 3137 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap; 3138 3139 /* XXX Are variables correct? */ 3140 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 3141 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 3142 tap->wr_dbm_antsignal = (int8_t)rssi; 3143 3144 mb.m_data = (caddr_t)tap; 3145 mb.m_len = sc->sc_rxtap_len; 3146 mb.m_next = m; 3147 mb.m_nextpkt = NULL; 3148 mb.m_type = 0; 3149 mb.m_flags = 0; 3150 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 3151 } 3152 #endif 3153 wh = mtod(m, struct ieee80211_frame *); 3154 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_DATA) 3155 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate; 3156 ni = ieee80211_find_rxnode(ic, wh); 3157 3158 /* XXX correct? */ 3159 if (!urtw_isbmode(rate)) { 3160 if (quality > 127) 3161 quality = 0; 3162 else if (quality < 27) 3163 quality = 100; 3164 else 3165 quality = 127 - quality; 3166 } else 3167 quality = (quality > 64) ? 0 : ((64 - quality) * 100) / 64; 3168 3169 nf = quality; 3170 3171 /* send the frame to the 802.11 layer */ 3172 rxi.rxi_flags = 0; 3173 rxi.rxi_rssi = rssi; 3174 rxi.rxi_tstamp = 0; 3175 ieee80211_input(ifp, m, ni, &rxi); 3176 3177 /* node is no longer needed */ 3178 ieee80211_release_node(ic, ni); 3179 3180 splx(s); 3181 3182 skip: /* setup a new transfer */ 3183 usbd_setup_xfer(xfer, sc->sc_rxpipe, data, data->buf, MCLBYTES, 3184 USBD_SHORT_XFER_OK, USBD_NO_TIMEOUT, urtw_rxeof); 3185 (void)usbd_transfer(xfer); 3186 } 3187 3188 usbd_status 3189 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain) 3190 { 3191 uint8_t *gainp; 3192 usbd_status error; 3193 3194 /* XXX for A? */ 3195 gainp = urtw_8225v2_gain_bg; 3196 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]); 3197 usbd_delay_ms(sc->sc_udev, 1); 3198 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]); 3199 usbd_delay_ms(sc->sc_udev, 1); 3200 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]); 3201 usbd_delay_ms(sc->sc_udev, 1); 3202 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17); 3203 usbd_delay_ms(sc->sc_udev, 1); 3204 fail: 3205 return (error); 3206 } 3207 3208 usbd_status 3209 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan) 3210 { 3211 int i; 3212 uint8_t *cck_pwrtable; 3213 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10; 3214 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3215 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3216 usbd_status error; 3217 3218 /* CCK power setting */ 3219 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 3220 cck_pwrlvl += sc->sc_txpwr_cck_base; 3221 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3222 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3223 urtw_8225v2_txpwr_cck; 3224 3225 for (i = 0; i < 8; i++) { 3226 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3227 } 3228 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3229 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]); 3230 usbd_delay_ms(sc->sc_udev, 1); 3231 3232 /* OFDM power setting */ 3233 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3234 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3235 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3236 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3237 3238 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON); 3239 if (error) 3240 goto fail; 3241 3242 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 3243 urtw_8187_write_phy_ofdm(sc, 5, 0x0); 3244 urtw_8187_write_phy_ofdm(sc, 6, 0x40); 3245 urtw_8187_write_phy_ofdm(sc, 7, 0x0); 3246 urtw_8187_write_phy_ofdm(sc, 8, 0x40); 3247 3248 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3249 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]); 3250 usbd_delay_ms(sc->sc_udev, 1); 3251 fail: 3252 return (error); 3253 } 3254 3255 usbd_status 3256 urtw_8225v2_rf_init(struct urtw_rf *rf) 3257 { 3258 struct urtw_softc *sc = rf->rf_sc; 3259 int i; 3260 uint16_t data; 3261 uint32_t data32; 3262 usbd_status error; 3263 3264 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON); 3265 if (error) 3266 goto fail; 3267 3268 error = urtw_8225_usb_init(sc); 3269 if (error) 3270 goto fail; 3271 3272 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 3273 urtw_read16_m(sc, URTW_8187_BRSR, &data); /* XXX ??? */ 3274 urtw_write16_m(sc, URTW_8187_BRSR, 0xffff); 3275 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 3276 3277 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3278 if (error) 3279 goto fail; 3280 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 3281 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3282 if (error) 3283 goto fail; 3284 3285 error = urtw_8185_rf_pins_enable(sc); 3286 if (error) 3287 goto fail; 3288 3289 usbd_delay_ms(sc->sc_udev, 1000); 3290 3291 for (i = 0; i < nitems(urtw_8225v2_rf_part1); i++) { 3292 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg, 3293 urtw_8225v2_rf_part1[i].val); 3294 usbd_delay_ms(sc->sc_udev, 1); 3295 } 3296 usbd_delay_ms(sc->sc_udev, 50); 3297 3298 urtw_8225_write(sc, 0x0, 0x1b7); 3299 3300 for (i = 0; i < nitems(urtw_8225v2_rxgain); i++) { 3301 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 3302 urtw_8225_write(sc, 0x2, urtw_8225v2_rxgain[i]); 3303 } 3304 3305 urtw_8225_write(sc, 0x3, 0x2); 3306 urtw_8225_write(sc, 0x5, 0x4); 3307 urtw_8225_write(sc, 0x0, 0xb7); 3308 urtw_8225_write(sc, 0x2, 0xc4d); 3309 usbd_delay_ms(sc->sc_udev, 100); 3310 urtw_8225_write(sc, 0x2, 0x44d); 3311 usbd_delay_ms(sc->sc_udev, 100); 3312 3313 error = urtw_8225_read(sc, 0x6, &data32); 3314 if (error != 0) 3315 goto fail; 3316 if (data32 != 0xe6) 3317 printf("%s: expect 0xe6!! (0x%x)\n", sc->sc_dev.dv_xname, 3318 data32); 3319 if (!(data32 & 0x80)) { 3320 urtw_8225_write(sc, 0x02, 0x0c4d); 3321 usbd_delay_ms(sc->sc_udev, 200); 3322 urtw_8225_write(sc, 0x02, 0x044d); 3323 usbd_delay_ms(sc->sc_udev, 100); 3324 error = urtw_8225_read(sc, 0x6, &data32); 3325 if (error != 0) 3326 goto fail; 3327 if (!(data32 & 0x80)) 3328 printf("%s: RF calibration failed\n", 3329 sc->sc_dev.dv_xname); 3330 } 3331 usbd_delay_ms(sc->sc_udev, 100); 3332 3333 urtw_8225_write(sc, 0x0, 0x2bf); 3334 for (i = 0; i < nitems(urtw_8225_agc); i++) { 3335 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 3336 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 3337 } 3338 3339 for (i = 0; i < nitems(urtw_8225v2_rf_part2); i++) { 3340 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg, 3341 urtw_8225v2_rf_part2[i].val); 3342 } 3343 3344 error = urtw_8225v2_setgain(sc, 4); 3345 if (error) 3346 goto fail; 3347 3348 for (i = 0; i < nitems(urtw_8225v2_rf_part3); i++) { 3349 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg, 3350 urtw_8225v2_rf_part3[i].val); 3351 } 3352 3353 urtw_write8_m(sc, 0x5b, 0x0d); 3354 3355 error = urtw_8225v2_set_txpwrlvl(sc, 1); 3356 if (error) 3357 goto fail; 3358 3359 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 3360 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 3361 3362 /* TX ant A, 0x0 for B */ 3363 error = urtw_8185_tx_antenna(sc, 0x3); 3364 if (error) 3365 goto fail; 3366 urtw_write32_m(sc, 0x94, 0x3dc00002); 3367 3368 error = urtw_8225_rf_set_chan(rf, 1); 3369 fail: 3370 return (error); 3371 } 3372 3373 usbd_status 3374 urtw_8225v2_rf_set_chan(struct urtw_rf *rf, int chan) 3375 { 3376 struct urtw_softc *sc = rf->rf_sc; 3377 struct ieee80211com *ic = &sc->sc_ic; 3378 struct ieee80211_channel *c = ic->ic_ibss_chan; 3379 usbd_status error; 3380 3381 error = urtw_8225v2_set_txpwrlvl(sc, chan); 3382 if (error) 3383 goto fail; 3384 3385 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 3386 usbd_delay_ms(sc->sc_udev, 10); 3387 3388 urtw_write8_m(sc, URTW_SIFS, 0x22); 3389 3390 if(sc->sc_state == IEEE80211_S_ASSOC && 3391 ic->ic_flags & IEEE80211_F_SHSLOT) 3392 urtw_write8_m(sc, URTW_SLOT, 0x9); 3393 else 3394 urtw_write8_m(sc, URTW_SLOT, 0x14); 3395 3396 if (IEEE80211_IS_CHAN_G(c)) { 3397 urtw_write8_m(sc, URTW_DIFS, 0x14); 3398 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x14); 3399 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 3400 } else { 3401 urtw_write8_m(sc, URTW_DIFS, 0x24); 3402 urtw_write8_m(sc, URTW_8187_EIFS, 0x5b - 0x24); 3403 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 3404 } 3405 3406 fail: 3407 return (error); 3408 } 3409 3410 void 3411 urtw_set_chan(struct urtw_softc *sc, struct ieee80211_channel *c) 3412 { 3413 struct urtw_rf *rf = &sc->sc_rf; 3414 struct ieee80211com *ic = &sc->sc_ic; 3415 usbd_status error = 0; 3416 uint32_t data; 3417 u_int chan; 3418 3419 chan = ieee80211_chan2ieee(ic, c); 3420 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3421 return; 3422 /* 3423 * During changing the channel we need to temporary disable 3424 * TX. 3425 */ 3426 urtw_read32_m(sc, URTW_TX_CONF, &data); 3427 data &= ~URTW_TX_LOOPBACK_MASK; 3428 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC); 3429 error = rf->set_chan(rf, chan); 3430 if (error != 0) { 3431 printf("%s could not change the channel\n", 3432 sc->sc_dev.dv_xname); 3433 return; 3434 } 3435 usbd_delay_ms(sc->sc_udev, 10); 3436 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_NONE); 3437 3438 fail: return; 3439 3440 } 3441 3442 void 3443 urtw_next_scan(void *arg) 3444 { 3445 struct urtw_softc *sc = arg; 3446 struct ieee80211com *ic = &sc->sc_ic; 3447 struct ifnet *ifp = &ic->ic_if; 3448 3449 if (usbd_is_dying(sc->sc_udev)) 3450 return; 3451 3452 usbd_ref_incr(sc->sc_udev); 3453 3454 if (ic->ic_state == IEEE80211_S_SCAN) 3455 ieee80211_next_scan(ifp); 3456 3457 usbd_ref_decr(sc->sc_udev); 3458 } 3459 3460 void 3461 urtw_task(void *arg) 3462 { 3463 struct urtw_softc *sc = arg; 3464 struct ieee80211com *ic = &sc->sc_ic; 3465 struct ieee80211_node *ni; 3466 enum ieee80211_state ostate; 3467 usbd_status error = 0; 3468 3469 if (usbd_is_dying(sc->sc_udev)) 3470 return; 3471 3472 ostate = ic->ic_state; 3473 3474 switch (sc->sc_state) { 3475 case IEEE80211_S_INIT: 3476 if (ostate == IEEE80211_S_RUN) { 3477 /* turn link LED off */ 3478 (void)urtw_led_off(sc, URTW_LED_GPIO); 3479 } 3480 break; 3481 3482 case IEEE80211_S_SCAN: 3483 urtw_set_chan(sc, ic->ic_bss->ni_chan); 3484 if (!usbd_is_dying(sc->sc_udev)) 3485 timeout_add_msec(&sc->scan_to, 200); 3486 break; 3487 3488 case IEEE80211_S_AUTH: 3489 case IEEE80211_S_ASSOC: 3490 urtw_set_chan(sc, ic->ic_bss->ni_chan); 3491 break; 3492 3493 case IEEE80211_S_RUN: 3494 ni = ic->ic_bss; 3495 3496 /* setting bssid. */ 3497 error = urtw_set_bssid(sc, ni->ni_bssid); 3498 if (error != 0) 3499 goto fail; 3500 urtw_update_msr(sc); 3501 /* XXX maybe the below would be incorrect. */ 3502 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3503 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 3504 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64); 3505 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 0x3ff); 3506 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK); 3507 if (error != 0) 3508 printf("%s: could not control LED (%d)\n", 3509 sc->sc_dev.dv_xname, error); 3510 break; 3511 } 3512 3513 sc->sc_newstate(ic, sc->sc_state, sc->sc_arg); 3514 3515 fail: 3516 if (error != 0) 3517 DPRINTF(("%s: error duing processing RUN state.", 3518 sc->sc_dev.dv_xname)); 3519 } 3520 3521 usbd_status 3522 urtw_8187b_update_wmm(struct urtw_softc *sc) 3523 { 3524 struct ieee80211com *ic = &sc->sc_ic; 3525 struct ieee80211_channel *c = ic->ic_ibss_chan; 3526 uint32_t data; 3527 uint8_t aifs, sifs, slot, ecwmin, ecwmax; 3528 usbd_status error; 3529 3530 sifs = 0xa; 3531 if (IEEE80211_IS_CHAN_G(c)) 3532 slot = 0x9; 3533 else 3534 slot = 0x14; 3535 3536 aifs = (2 * slot) + sifs; 3537 ecwmin = 3; 3538 ecwmax = 7; 3539 3540 data = ((uint32_t)aifs << 0) | /* AIFS, offset 0 */ 3541 ((uint32_t)ecwmin << 8) | /* ECW minimum, offset 8 */ 3542 ((uint32_t)ecwmax << 12); /* ECW maximum, offset 16 */ 3543 3544 urtw_write32_m(sc, URTW_AC_VO, data); 3545 urtw_write32_m(sc, URTW_AC_VI, data); 3546 urtw_write32_m(sc, URTW_AC_BE, data); 3547 urtw_write32_m(sc, URTW_AC_BK, data); 3548 3549 fail: 3550 return (error); 3551 } 3552 3553 usbd_status 3554 urtw_8187b_reset(struct urtw_softc *sc) 3555 { 3556 uint8_t data; 3557 usbd_status error; 3558 3559 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3560 if (error) 3561 goto fail; 3562 3563 urtw_read8_m(sc, URTW_CONFIG3, &data); 3564 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE | 3565 URTW_CONFIG3_GNT_SELECT); 3566 3567 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON); 3568 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON); 3569 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON); 3570 3571 urtw_write8_m(sc, 0x61, 0x10); 3572 urtw_read8_m(sc, 0x62, &data); 3573 urtw_write8_m(sc, 0x62, data & ~(1 << 5)); 3574 urtw_write8_m(sc, 0x62, data | (1 << 5)); 3575 3576 urtw_read8_m(sc, URTW_CONFIG3, &data); 3577 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3578 3579 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3580 if (error) 3581 goto fail; 3582 3583 urtw_read8_m(sc, URTW_CMD, &data); 3584 data = (data & 2) | URTW_CMD_RST; 3585 urtw_write8_m(sc, URTW_CMD, data); 3586 usbd_delay_ms(sc->sc_udev, 100); 3587 3588 urtw_read8_m(sc, URTW_CMD, &data); 3589 if (data & URTW_CMD_RST) { 3590 printf("%s: reset timeout\n", sc->sc_dev.dv_xname); 3591 goto fail; 3592 } 3593 3594 fail: 3595 return (error); 3596 } 3597 3598 int 3599 urtw_8187b_init(struct ifnet *ifp) 3600 { 3601 struct urtw_softc *sc = ifp->if_softc; 3602 struct urtw_rf *rf = &sc->sc_rf; 3603 struct ieee80211com *ic = &sc->sc_ic; 3604 int ret; 3605 uint8_t data; 3606 usbd_status error; 3607 3608 urtw_stop(ifp, 0); 3609 3610 error = urtw_8187b_update_wmm(sc); 3611 if (error != 0) 3612 goto fail; 3613 error = urtw_8187b_reset(sc); 3614 if (error) 3615 goto fail; 3616 3617 /* Applying MAC address again. */ 3618 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3619 if (error) 3620 goto fail; 3621 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 3622 error = urtw_set_macaddr(sc, ic->ic_myaddr); 3623 if (error) 3624 goto fail; 3625 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3626 if (error) 3627 goto fail; 3628 3629 error = urtw_update_msr(sc); 3630 if (error) 3631 goto fail; 3632 3633 error = rf->init(rf); 3634 if (error != 0) 3635 goto fail; 3636 3637 urtw_write8_m(sc, URTW_CMD, URTW_CMD_TX_ENABLE | 3638 URTW_CMD_RX_ENABLE); 3639 error = urtw_intr_enable(sc); 3640 if (error != 0) 3641 goto fail; 3642 3643 error = urtw_write8e(sc, 0x41, 0xf4); 3644 if (error != 0) 3645 goto fail; 3646 error = urtw_write8e(sc, 0x40, 0x00); 3647 if (error != 0) 3648 goto fail; 3649 error = urtw_write8e(sc, 0x42, 0x00); 3650 if (error != 0) 3651 goto fail; 3652 error = urtw_write8e(sc, 0x42, 0x01); 3653 if (error != 0) 3654 goto fail; 3655 error = urtw_write8e(sc, 0x40, 0x0f); 3656 if (error != 0) 3657 goto fail; 3658 error = urtw_write8e(sc, 0x42, 0x00); 3659 if (error != 0) 3660 goto fail; 3661 error = urtw_write8e(sc, 0x42, 0x01); 3662 if (error != 0) 3663 goto fail; 3664 3665 urtw_read8_m(sc, 0xdb, &data); 3666 urtw_write8_m(sc, 0xdb, data | (1 << 2)); 3667 urtw_write16_idx_m(sc, 0x72, 0x59fa, 3); 3668 urtw_write16_idx_m(sc, 0x74, 0x59d2, 3); 3669 urtw_write16_idx_m(sc, 0x76, 0x59d2, 3); 3670 urtw_write16_idx_m(sc, 0x78, 0x19fa, 3); 3671 urtw_write16_idx_m(sc, 0x7a, 0x19fa, 3); 3672 urtw_write16_idx_m(sc, 0x7c, 0x00d0, 3); 3673 urtw_write8_m(sc, 0x61, 0); 3674 urtw_write8_idx_m(sc, 0x80, 0x0f, 1); 3675 urtw_write8_idx_m(sc, 0x83, 0x03, 1); 3676 urtw_write8_m(sc, 0xda, 0x10); 3677 urtw_write8_idx_m(sc, 0x4d, 0x08, 2); 3678 3679 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321b); 3680 3681 urtw_write16_idx_m(sc, 0xec, 0x0800, 1); 3682 3683 urtw_write8_m(sc, URTW_ACM_CONTROL, 0); 3684 3685 /* Reset softc variables. */ 3686 sc->sc_txidx = sc->sc_tx_low_queued = sc->sc_tx_normal_queued = 0; 3687 sc->sc_txtimer = 0; 3688 3689 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 3690 error = urtw_open_pipes(sc); 3691 if (error != 0) 3692 goto fail; 3693 ret = urtw_alloc_rx_data_list(sc); 3694 if (error != 0) 3695 goto fail; 3696 ret = urtw_alloc_tx_data_list(sc); 3697 if (error != 0) 3698 goto fail; 3699 sc->sc_flags |= URTW_INIT_ONCE; 3700 } 3701 3702 error = urtw_rx_enable(sc); 3703 if (error != 0) 3704 goto fail; 3705 error = urtw_tx_enable(sc); 3706 if (error != 0) 3707 goto fail; 3708 3709 ifp->if_flags |= IFF_RUNNING; 3710 ifq_clr_oactive(&ifp->if_snd); 3711 3712 ifp->if_timer = 1; 3713 3714 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3715 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3716 else 3717 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3718 3719 fail: 3720 return (error); 3721 } 3722 3723 usbd_status 3724 urtw_8225v2_b_config_mac(struct urtw_softc *sc) 3725 { 3726 int i; 3727 usbd_status error; 3728 3729 for (i = 0; i < nitems(urtw_8187b_regtbl); i++) { 3730 urtw_write8_idx_m(sc, urtw_8187b_regtbl[i].reg, 3731 urtw_8187b_regtbl[i].val, urtw_8187b_regtbl[i].idx); 3732 } 3733 3734 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50); 3735 urtw_write16_m(sc, URTW_INT_MIG, 0); 3736 3737 urtw_write32_idx_m(sc, 0xf0, 0, 1); 3738 urtw_write32_idx_m(sc, 0xf4, 0, 1); 3739 urtw_write8_idx_m(sc, 0xf8, 0, 1); 3740 3741 urtw_write32_m(sc, URTW_RF_TIMING, 0x00004001); 3742 3743 fail: 3744 return (error); 3745 } 3746 3747 usbd_status 3748 urtw_8225v2_b_init_rfe(struct urtw_softc *sc) 3749 { 3750 usbd_status error; 3751 3752 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480); 3753 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488); 3754 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff); 3755 usbd_delay_ms(sc->sc_udev, 100); 3756 3757 fail: 3758 return (error); 3759 } 3760 3761 usbd_status 3762 urtw_8225v2_b_update_chan(struct urtw_softc *sc) 3763 { 3764 struct ieee80211com *ic = &sc->sc_ic; 3765 struct ieee80211_channel *c = ic->ic_ibss_chan; 3766 uint8_t aifs, difs, eifs, sifs, slot; 3767 usbd_status error; 3768 3769 urtw_write8_m(sc, URTW_SIFS, 0x22); 3770 3771 sifs = 0xa; 3772 if (IEEE80211_IS_CHAN_G(c)) { 3773 slot = 0x9; 3774 difs = 0x1c; 3775 eifs = 0x5b; 3776 } else { 3777 slot = 0x14; 3778 difs = 0x32; 3779 eifs = 0x5b; 3780 } 3781 aifs = (2 * slot) + sifs; 3782 3783 urtw_write8_m(sc, URTW_SLOT, slot); 3784 3785 urtw_write8_m(sc, URTW_AC_VO, aifs); 3786 urtw_write8_m(sc, URTW_AC_VI, aifs); 3787 urtw_write8_m(sc, URTW_AC_BE, aifs); 3788 urtw_write8_m(sc, URTW_AC_BK, aifs); 3789 3790 urtw_write8_m(sc, URTW_DIFS, difs); 3791 urtw_write8_m(sc, URTW_8187B_EIFS, eifs); 3792 3793 fail: 3794 return (error); 3795 } 3796 3797 usbd_status 3798 urtw_8225v2_b_rf_init(struct urtw_rf *rf) 3799 { 3800 struct urtw_softc *sc = rf->rf_sc; 3801 int i; 3802 uint8_t data; 3803 usbd_status error; 3804 3805 /* Set up ACK rate, retry limit, TX AGC, TX antenna. */ 3806 urtw_write16_m(sc, URTW_8187B_BRSR, 0x0fff); 3807 urtw_read8_m(sc, URTW_CW_CONF, &data); 3808 urtw_write8_m(sc, URTW_CW_CONF, data | 3809 URTW_CW_CONF_PERPACKET_RETRY); 3810 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data); 3811 urtw_write8_m(sc, URTW_TX_AGC_CTL, data | 3812 URTW_TX_AGC_CTL_PERPACKET_GAIN | 3813 URTW_TX_AGC_CTL_PERPACKET_ANTSEL); 3814 3815 /* Auto rate fallback control. */ 3816 urtw_write16_idx_m(sc, URTW_ARFR, 0x0fff, 1); /* 1M ~ 54M */ 3817 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data); 3818 urtw_write8_m(sc, URTW_RATE_FALLBACK, data | 3819 URTW_RATE_FALLBACK_ENABLE); 3820 3821 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 3822 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3823 urtw_write16_idx_m(sc, URTW_FEMR, 0xffff, 1); 3824 3825 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3826 if (error) 3827 goto fail; 3828 urtw_read8_m(sc, URTW_CONFIG1, &data); 3829 urtw_write8_m(sc, URTW_CONFIG1, (data & 0x3f) | 0x80); 3830 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3831 if (error) 3832 goto fail; 3833 3834 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 3835 urtw_8225v2_b_config_mac(sc); 3836 urtw_write16_idx_m(sc, URTW_RFSW_CTRL, 0x569a, 2); 3837 3838 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3839 if (error) 3840 goto fail; 3841 urtw_read8_m(sc, URTW_CONFIG3, &data); 3842 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3843 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3844 if (error) 3845 goto fail; 3846 3847 urtw_8225v2_b_init_rfe(sc); 3848 3849 for (i = 0; i < nitems(urtw_8225v2_b_rf); i++) { 3850 urtw_8225_write(sc, urtw_8225v2_b_rf[i].reg, 3851 urtw_8225v2_b_rf[i].val); 3852 } 3853 3854 for (i = 0; i < nitems(urtw_8225v2_rxgain); i++) { 3855 urtw_8225_write(sc, 0x1, (uint8_t)(i + 1)); 3856 urtw_8225_write(sc, 0x2, urtw_8225v2_rxgain[i]); 3857 } 3858 3859 urtw_8225_write(sc, 0x03, 0x080); 3860 urtw_8225_write(sc, 0x05, 0x004); 3861 urtw_8225_write(sc, 0x00, 0x0b7); 3862 urtw_8225_write(sc, 0x02, 0xc4d); 3863 urtw_8225_write(sc, 0x02, 0x44d); 3864 urtw_8225_write(sc, 0x00, 0x2bf); 3865 3866 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03); 3867 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07); 3868 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03); 3869 3870 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12); 3871 for (i = 0; i < nitems(urtw_8225v2_agc); i++) { 3872 urtw_8187_write_phy_ofdm(sc, 0x0f, urtw_8225v2_agc[i]); 3873 urtw_8187_write_phy_ofdm(sc, 0x0e, (uint8_t)i + 0x80); 3874 urtw_8187_write_phy_ofdm(sc, 0x0e, 0); 3875 } 3876 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10); 3877 3878 for (i = 0; i < nitems(urtw_8225v2_ofdm); i++) 3879 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2_ofdm[i]); 3880 3881 urtw_8225v2_b_update_chan(sc); 3882 3883 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46); 3884 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6); 3885 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc); 3886 urtw_8187_write_phy_cck(sc, 0xc1, 0x88); 3887 3888 error = urtw_8225v2_b_rf_set_chan(rf, 1); 3889 fail: 3890 return (error); 3891 } 3892 3893 usbd_status 3894 urtw_8225v2_b_rf_set_chan(struct urtw_rf *rf, int chan) 3895 { 3896 struct urtw_softc *sc = rf->rf_sc; 3897 usbd_status error; 3898 3899 error = urtw_8225v2_b_set_txpwrlvl(sc, chan); 3900 if (error) 3901 goto fail; 3902 3903 urtw_8225_write(sc, 0x7, urtw_8225_channel[chan]); 3904 /* 3905 * Delay removed from 8185 to 8187. 3906 * usbd_delay_ms(sc->sc_udev, 10); 3907 */ 3908 3909 urtw_write16_m(sc, URTW_AC_VO, 0x5114); 3910 urtw_write16_m(sc, URTW_AC_VI, 0x5114); 3911 urtw_write16_m(sc, URTW_AC_BE, 0x5114); 3912 urtw_write16_m(sc, URTW_AC_BK, 0x5114); 3913 3914 fail: 3915 return (error); 3916 } 3917 3918 usbd_status 3919 urtw_8225v2_b_set_txpwrlvl(struct urtw_softc *sc, int chan) 3920 { 3921 int i; 3922 uint8_t *cck_pwrtable; 3923 uint8_t cck_pwrlvl_min, cck_pwrlvl_max, ofdm_pwrlvl_min, 3924 ofdm_pwrlvl_max; 3925 int8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3926 int8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3927 usbd_status error; 3928 3929 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3930 cck_pwrlvl_min = 0; 3931 cck_pwrlvl_max = 15; 3932 ofdm_pwrlvl_min = 2; 3933 ofdm_pwrlvl_max = 17; 3934 } else { 3935 cck_pwrlvl_min = 7; 3936 cck_pwrlvl_max = 22; 3937 ofdm_pwrlvl_min = 10; 3938 ofdm_pwrlvl_max = 25; 3939 } 3940 3941 /* CCK power setting */ 3942 cck_pwrlvl = (cck_pwrlvl > (cck_pwrlvl_max - cck_pwrlvl_min)) ? 3943 cck_pwrlvl_max : (cck_pwrlvl + cck_pwrlvl_min); 3944 3945 cck_pwrlvl += sc->sc_txpwr_cck_base; 3946 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3947 cck_pwrlvl = (cck_pwrlvl < 0) ? 0 : cck_pwrlvl; 3948 3949 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3950 urtw_8225v2_txpwr_cck; 3951 3952 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3953 if (cck_pwrlvl <= 6) 3954 ; /* do nothing */ 3955 else if (cck_pwrlvl <= 11) 3956 cck_pwrtable += 8; 3957 else 3958 cck_pwrtable += 16; 3959 } else { 3960 if (cck_pwrlvl <= 5) 3961 ; /* do nothing */ 3962 else if (cck_pwrlvl <= 11) 3963 cck_pwrtable += 8; 3964 else if (cck_pwrlvl <= 17) 3965 cck_pwrtable += 16; 3966 else 3967 cck_pwrtable += 24; 3968 } 3969 3970 for (i = 0; i < 8; i++) { 3971 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3972 } 3973 3974 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3975 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1); 3976 /* 3977 * Delay removed from 8185 to 8187. 3978 * usbd_delay_ms(sc->sc_udev, 1); 3979 */ 3980 3981 /* OFDM power setting */ 3982 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3983 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3984 3985 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3986 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3987 ofdm_pwrlvl = (ofdm_pwrlvl < 0) ? 0 : ofdm_pwrlvl; 3988 3989 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3990 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1); 3991 3992 if (sc->sc_hwrev & URTW_HWREV_8187B_B) { 3993 if (ofdm_pwrlvl <= 11) { 3994 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60); 3995 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60); 3996 } else { 3997 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 3998 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 3999 } 4000 } else { 4001 if (ofdm_pwrlvl <= 11) { 4002 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 4003 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 4004 } else if (ofdm_pwrlvl <= 17) { 4005 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54); 4006 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54); 4007 } else { 4008 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50); 4009 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50); 4010 } 4011 } 4012 4013 /* 4014 * Delay removed from 8185 to 8187. 4015 * usbd_delay_ms(sc->sc_udev, 1); 4016 */ 4017 fail: 4018 return (error); 4019 } 4020 4021 int 4022 urtw_set_bssid(struct urtw_softc *sc, const uint8_t *bssid) 4023 { 4024 int error; 4025 4026 urtw_write32_m(sc, URTW_BSSID, 4027 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 4028 urtw_write16_m(sc, URTW_BSSID + 4, 4029 bssid[4] | bssid[5] << 8); 4030 4031 return 0; 4032 4033 fail: 4034 return error; 4035 } 4036 4037 int 4038 urtw_set_macaddr(struct urtw_softc *sc, const uint8_t *addr) 4039 { 4040 int error; 4041 4042 urtw_write32_m(sc, URTW_MAC0, 4043 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 4044 urtw_write16_m(sc, URTW_MAC4, 4045 addr[4] | addr[5] << 8); 4046 4047 return 0; 4048 4049 fail: 4050 return error; 4051 } 4052