1 /* $OpenBSD: if_urereg.h,v 1.2 2016/08/07 00:21:57 jmatthew Exp $ */ 2 /*- 3 * Copyright (c) 2015 Kevin Lo <kevlo@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #define URE_CONFIG_IDX 0 /* config number 1 */ 31 #define URE_IFACE_IDX 0 32 33 #define URE_CTL_READ 0x01 34 #define URE_CTL_WRITE 0x02 35 36 #define URE_TIMEOUT 1000 37 #define URE_PHY_TIMEOUT 2000 38 39 #define URE_BYTE_EN_DWORD 0xff 40 #define URE_BYTE_EN_WORD 0x33 41 #define URE_BYTE_EN_BYTE 0x11 42 #define URE_BYTE_EN_SIX_BYTES 0x3f 43 44 #define URE_MAX_FRAMELEN (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) 45 46 #define URE_PLA_IDR 0xc000 47 #define URE_PLA_RCR 0xc010 48 #define URE_PLA_RMS 0xc016 49 #define URE_PLA_RXFIFO_CTRL0 0xc0a0 50 #define URE_PLA_RXFIFO_CTRL1 0xc0a4 51 #define URE_PLA_RXFIFO_CTRL2 0xc0a8 52 #define URE_PLA_DMY_REG0 0xc0b0 53 #define URE_PLA_FMC 0xc0b4 54 #define URE_PLA_CFG_WOL 0xc0b6 55 #define URE_PLA_TEREDO_CFG 0xc0bc 56 #define URE_PLA_MAR0 0xcd00 57 #define URE_PLA_MAR4 0xcd04 58 #define URE_PLA_BACKUP 0xd000 59 #define URE_PLA_BDC_CR 0xd1a0 60 #define URE_PLA_TEREDO_TIMER 0xd2cc 61 #define URE_PLA_REALWOW_TIMER 0xd2e8 62 #define URE_PLA_LEDSEL 0xdd90 63 #define URE_PLA_LED_FEATURE 0xdd92 64 #define URE_PLA_PHYAR 0xde00 65 #define URE_PLA_BOOT_CTRL 0xe004 66 #define URE_PLA_GPHY_INTR_IMR 0xe022 67 #define URE_PLA_EEE_CR 0xe040 68 #define URE_PLA_EEEP_CR 0xe080 69 #define URE_PLA_MAC_PWR_CTRL 0xe0c0 70 #define URE_PLA_MAC_PWR_CTRL2 0xe0ca 71 #define URE_PLA_MAC_PWR_CTRL3 0xe0cc 72 #define URE_PLA_MAC_PWR_CTRL4 0xe0ce 73 #define URE_PLA_WDT6_CTRL 0xe428 74 #define URE_PLA_TCR0 0xe610 75 #define URE_PLA_TCR1 0xe612 76 #define URE_PLA_MTPS 0xe615 77 #define URE_PLA_TXFIFO_CTRL 0xe618 78 #define URE_PLA_RSTTELLY 0xe800 79 #define URE_PLA_CR 0xe813 80 #define URE_PLA_CRWECR 0xe81c 81 #define URE_PLA_CONFIG5 0xe822 82 #define URE_PLA_PHY_PWR 0xe84c 83 #define URE_PLA_OOB_CTRL 0xe84f 84 #define URE_PLA_CPCR 0xe854 85 #define URE_PLA_MISC_0 0xe858 86 #define URE_PLA_MISC_1 0xe85a 87 #define URE_PLA_OCP_GPHY_BASE 0xe86c 88 #define URE_PLA_TELLYCNT 0xe890 89 #define URE_PLA_SFF_STS_7 0xe8de 90 #define URE_PLA_PHYSTATUS 0xe908 91 92 #define URE_USB_USB2PHY 0xb41e 93 #define URE_USB_SSPHYLINK2 0xb428 94 #define URE_USB_U2P3_CTRL 0xb460 95 #define URE_USB_CSR_DUMMY1 0xb464 96 #define URE_USB_CSR_DUMMY2 0xb466 97 #define URE_USB_DEV_STAT 0xb808 98 #define URE_USB_CONNECT_TIMER 0xcbf8 99 #define URE_USB_BURST_SIZE 0xcfc0 100 #define URE_USB_USB_CTRL 0xd406 101 #define URE_USB_PHY_CTRL 0xd408 102 #define URE_USB_TX_AGG 0xd40a 103 #define URE_USB_RX_BUF_TH 0xd40c 104 #define URE_USB_USB_TIMER 0xd428 105 #define URE_USB_RX_EARLY_AGG 0xd42c 106 #define URE_USB_PM_CTRL_STATUS 0xd432 107 #define URE_USB_TX_DMA 0xd434 108 #define URE_USB_TOLERANCE 0xd490 109 #define URE_USB_LPM_CTRL 0xd41a 110 #define URE_USB_UPS_CTRL 0xd800 111 #define URE_USB_MISC_0 0xd81a 112 #define URE_USB_POWER_CUT 0xd80a 113 #define URE_USB_AFE_CTRL2 0xd824 114 #define URE_USB_WDT11_CTRL 0xe43c 115 116 /* OCP Registers. */ 117 #define URE_OCP_ALDPS_CONFIG 0x2010 118 #define URE_OCP_EEE_CONFIG1 0x2080 119 #define URE_OCP_EEE_CONFIG2 0x2092 120 #define URE_OCP_EEE_CONFIG3 0x2094 121 #define URE_OCP_BASE_MII 0xa400 122 #define URE_OCP_EEE_AR 0xa41a 123 #define URE_OCP_EEE_DATA 0xa41c 124 #define URE_OCP_PHY_STATUS 0xa420 125 #define URE_OCP_POWER_CFG 0xa430 126 #define URE_OCP_EEE_CFG 0xa432 127 #define URE_OCP_SRAM_ADDR 0xa436 128 #define URE_OCP_SRAM_DATA 0xa438 129 #define URE_OCP_DOWN_SPEED 0xa442 130 #define URE_OCP_EEE_ABLE 0xa5c4 131 #define URE_OCP_EEE_ADV 0xa5d0 132 #define URE_OCP_EEE_LPABLE 0xa5d2 133 #define URE_OCP_PHY_STATE 0xa708 134 #define URE_OCP_ADC_CFG 0xbc06 135 136 /* SRAM Register. */ 137 #define URE_SRAM_LPF_CFG 0x8012 138 #define URE_SRAM_10M_AMP1 0x8080 139 #define URE_SRAM_10M_AMP2 0x8082 140 #define URE_SRAM_IMPEDANCE 0x8084 141 142 /* PLA_RCR */ 143 #define URE_RCR_AAP 0x00000001 144 #define URE_RCR_APM 0x00000002 145 #define URE_RCR_AM 0x00000004 146 #define URE_RCR_AB 0x00000008 147 #define URE_RCR_ACPT_ALL \ 148 (URE_RCR_AAP | URE_RCR_APM | URE_RCR_AM | URE_RCR_AB) 149 150 /* PLA_RXFIFO_CTRL0 */ 151 #define URE_RXFIFO_THR1_NORMAL 0x00080002 152 #define URE_RXFIFO_THR1_OOB 0x01800003 153 154 /* PLA_RXFIFO_CTRL1 */ 155 #define URE_RXFIFO_THR2_FULL 0x00000060 156 #define URE_RXFIFO_THR2_HIGH 0x00000038 157 #define URE_RXFIFO_THR2_OOB 0x0000004a 158 #define URE_RXFIFO_THR2_NORMAL 0x00a0 159 160 /* PLA_RXFIFO_CTRL2 */ 161 #define URE_RXFIFO_THR3_FULL 0x00000078 162 #define URE_RXFIFO_THR3_HIGH 0x00000048 163 #define URE_RXFIFO_THR3_OOB 0x0000005a 164 #define URE_RXFIFO_THR3_NORMAL 0x0110 165 166 /* PLA_TXFIFO_CTRL */ 167 #define URE_TXFIFO_THR_NORMAL 0x00400008 168 #define URE_TXFIFO_THR_NORMAL2 0x01000008 169 170 /* PLA_DMY_REG0 */ 171 #define URE_ECM_ALDPS 0x0002 172 173 /* PLA_FMC */ 174 #define URE_FMC_FCR_MCU_EN 0x0001 175 176 /* PLA_EEEP_CR */ 177 #define URE_EEEP_CR_EEEP_TX 0x0002 178 179 /* PLA_WDT6_CTRL */ 180 #define URE_WDT6_SET_MODE 0x001 181 182 /* PLA_TCR0 */ 183 #define URE_TCR0_TX_EMPTY 0x0800 184 #define URE_TCR0_AUTO_FIFO 0x0080 185 186 /* PLA_TCR1 */ 187 #define URE_VERSION_MASK 0x7cf0 188 189 /* PLA_CR */ 190 #define URE_CR_RST 0x10 191 #define URE_CR_RE 0x08 192 #define URE_CR_TE 0x04 193 194 /* PLA_CRWECR */ 195 #define URE_CRWECR_NORAML 0x00 196 #define URE_CRWECR_CONFIG 0xc0 197 198 /* PLA_OOB_CTRL */ 199 #define URE_NOW_IS_OOB 0x80 200 #define URE_TXFIFO_EMPTY 0x20 201 #define URE_RXFIFO_EMPTY 0x10 202 #define URE_LINK_LIST_READY 0x02 203 #define URE_DIS_MCU_CLROOB 0x01 204 #define URE_FIFO_EMPTY (URE_TXFIFO_EMPTY | URE_RXFIFO_EMPTY) 205 206 /* PLA_MISC_1 */ 207 #define URE_RXDY_GATED_EN 0x0008 208 209 /* PLA_SFF_STS_7 */ 210 #define URE_RE_INIT_LL 0x8000 211 #define URE_MCU_BORW_EN 0x4000 212 213 /* PLA_CPCR */ 214 #define URE_CPCR_RX_VLAN 0x0040 215 216 /* PLA_TEREDO_CFG */ 217 #define URE_TEREDO_SEL 0x8000 218 #define URE_TEREDO_WAKE_MASK 0x7f00 219 #define URE_TEREDO_RS_EVENT_MASK 0x00fe 220 #define URE_OOB_TEREDO_EN 0x0001 221 222 /* PAL_BDC_CR */ 223 #define URE_ALDPS_PROXY_MODE 0x0001 224 225 /* PLA_CONFIG5 */ 226 #define URE_LAN_WAKE_EN 0x0002 227 228 /* PLA_LED_FEATURE */ 229 #define URE_LED_MODE_MASK 0x0700 230 231 /* PLA_PHY_PWR */ 232 #define URE_TX_10M_IDLE_EN 0x0080 233 #define URE_PFM_PWM_SWITCH 0x0040 234 235 /* PLA_MAC_PWR_CTRL */ 236 #define URE_D3_CLK_GATED_EN 0x00004000 237 #define URE_MCU_CLK_RATIO 0x07010f07 238 #define URE_MCU_CLK_RATIO_MASK 0x0f0f0f0f 239 #define URE_ALDPS_SPDWN_RATIO 0x0f87 240 241 /* PLA_MAC_PWR_CTRL2 */ 242 #define URE_EEE_SPDWN_RATIO 0x8007 243 244 /* PLA_MAC_PWR_CTRL3 */ 245 #define URE_PKT_AVAIL_SPDWN_EN 0x0100 246 #define URE_SUSPEND_SPDWN_EN 0x0004 247 #define URE_U1U2_SPDWN_EN 0x0002 248 #define URE_L1_SPDWN_EN 0x0001 249 250 /* PLA_MAC_PWR_CTRL4 */ 251 #define URE_PWRSAVE_SPDWN_EN 0x1000 252 #define URE_RXDV_SPDWN_EN 0x0800 253 #define URE_TX10MIDLE_EN 0x0100 254 #define URE_TP100_SPDWN_EN 0x0020 255 #define URE_TP500_SPDWN_EN 0x0010 256 #define URE_TP1000_SPDWN_EN 0x0008 257 #define URE_EEE_SPDWN_EN 0x0001 258 259 /* PLA_GPHY_INTR_IMR */ 260 #define URE_GPHY_STS_MSK 0x0001 261 #define URE_SPEED_DOWN_MSK 0x0002 262 #define URE_SPDWN_RXDV_MSK 0x0004 263 #define URE_SPDWN_LINKCHG_MSK 0x0008 264 265 /* PLA_PHYAR */ 266 #define URE_PHYAR_PHYDATA 0x0000ffff 267 #define URE_PHYAR_BUSY 0x80000000 268 269 /* PLA_EEE_CR */ 270 #define URE_EEE_RX_EN 0x0001 271 #define URE_EEE_TX_EN 0x0002 272 273 /* PLA_BOOT_CTRL */ 274 #define URE_AUTOLOAD_DONE 0x0002 275 276 /* USB_USB2PHY */ 277 #define URE_USB2PHY_SUSPEND 0x0001 278 #define URE_USB2PHY_L1 0x0002 279 280 /* USB_SSPHYLINK2 */ 281 #define URE_PWD_DN_SCALE_MASK 0x3ffe 282 #define URE_PWD_DN_SCALE(x) ((x) << 1) 283 284 /* USB_CSR_DUMMY1 */ 285 #define URE_DYNAMIC_BURST 0x0001 286 287 /* USB_CSR_DUMMY2 */ 288 #define URE_EP4_FULL_FC 0x0001 289 290 /* USB_DEV_STAT */ 291 #define URE_STAT_SPEED_MASK 0x0006 292 #define URE_STAT_SPEED_HIGH 0x0000 293 #define URE_STAT_SPEED_FULL 0x0001 294 295 /* USB_TX_AGG */ 296 #define URE_TX_AGG_MAX_THRESHOLD 0x03 297 298 /* USB_RX_BUF_TH */ 299 #define URE_RX_THR_SUPER 0x0c350180 300 #define URE_RX_THR_HIGH 0x7a120180 301 #define URE_RX_THR_SLOW 0xffff0180 302 303 /* USB_TX_DMA */ 304 #define URE_TEST_MODE_DISABLE 0x00000001 305 #define URE_TX_SIZE_ADJUST1 0x00000100 306 307 /* USB_UPS_CTRL */ 308 #define URE_POWER_CUT 0x0100 309 310 /* USB_PM_CTRL_STATUS */ 311 #define URE_RESUME_INDICATE 0x0001 312 313 /* USB_USB_CTRL */ 314 #define URE_RX_AGG_DISABLE 0x0010 315 #define URE_RX_ZERO_EN 0x0080 316 317 /* USB_U2P3_CTRL */ 318 #define URE_U2P3_ENABLE 0x0001 319 320 /* USB_POWER_CUT */ 321 #define URE_PWR_EN 0x0001 322 #define URE_PHASE2_EN 0x0008 323 324 /* USB_MISC_0 */ 325 #define URE_PCUT_STATUS 0x0001 326 327 /* USB_RX_EARLY_TIMEOUT */ 328 #define URE_COALESCE_SUPER 85000U 329 #define URE_COALESCE_HIGH 250000U 330 #define URE_COALESCE_SLOW 524280U 331 332 /* USB_WDT11_CTRL */ 333 #define URE_TIMER11_EN 0x0001 334 335 /* USB_LPM_CTRL */ 336 #define URE_FIFO_EMPTY_1FB 0x30 337 #define URE_LPM_TIMER_MASK 0x0c 338 #define URE_LPM_TIMER_500MS 0x04 339 #define URE_LPM_TIMER_500US 0x0c 340 #define URE_ROK_EXIT_LPM 0x02 341 342 /* USB_AFE_CTRL2 */ 343 #define URE_SEN_VAL_MASK 0xf800 344 #define URE_SEN_VAL_NORMAL 0xa000 345 #define URE_SEL_RXIDLE 0x0100 346 347 /* OCP_ALDPS_CONFIG */ 348 #define URE_ENPWRSAVE 0x8000 349 #define URE_ENPDNPS 0x0200 350 #define URE_LINKENA 0x0100 351 #define URE_DIS_SDSAVE 0x0010 352 353 /* OCP_PHY_STATUS */ 354 #define URE_PHY_STAT_MASK 0x0007 355 #define URE_PHY_STAT_LAN_ON 3 356 #define URE_PHY_STAT_PWRDN 5 357 358 /* OCP_POWER_CFG */ 359 #define URE_EEE_CLKDIV_EN 0x8000 360 #define URE_EN_ALDPS 0x0004 361 #define URE_EN_10M_PLLOFF 0x0001 362 363 /* OCP_EEE_CFG */ 364 #define URE_CTAP_SHORT_EN 0x0040 365 #define URE_EEE10_EN 0x0010 366 367 /* OCP_DOWN_SPEED */ 368 #define URE_EN_10M_BGOFF 0x0080 369 370 /* OCP_PHY_STATE */ 371 #define URE_TXDIS_STATE 0x01 372 #define URE_ABD_STATE 0x02 373 374 /* OCP_ADC_CFG */ 375 #define URE_CKADSEL_L 0x0100 376 #define URE_ADC_EN 0x0080 377 #define URE_EN_EMI_L 0x0040 378 379 #define URE_MCU_TYPE_PLA 0x0100 380 #define URE_MCU_TYPE_USB 0x0000 381 382 #define GET_MII(sc) uether_getmii(&(sc)->sc_ue) 383 384 struct ure_intrpkt { 385 uint8_t ure_tsr; 386 uint8_t ure_rsr; 387 uint8_t ure_gep_msr; 388 uint8_t ure_waksr; 389 uint8_t ure_txok_cnt; 390 uint8_t ure_rxlost_cnt; 391 uint8_t ure_crcerr_cnt; 392 uint8_t ure_col_cnt; 393 } __packed; 394 395 struct ure_rxpkt { 396 uint32_t ure_pktlen; 397 #define URE_RXPKT_LEN_MASK 0x7fff 398 uint32_t ure_rsvd0; 399 uint32_t ure_rsvd1; 400 uint32_t ure_rsvd2; 401 uint32_t ure_rsvd3; 402 uint32_t ure_rsvd4; 403 } __packed; 404 405 struct ure_txpkt { 406 uint32_t ure_pktlen; 407 #define URE_TXPKT_TX_FS (1 << 31) 408 #define URE_TXPKT_TX_LS (1 << 30) 409 #define URE_TXPKT_LEN_MASK 0xffff 410 uint32_t ure_rsvd0; 411 } __packed; 412 413 #define URE_ENDPT_RX 0 414 #define URE_ENDPT_TX 1 415 #define URE_ENDPT_MAX 2 416 417 #define URE_TX_LIST_CNT 1 418 #define URE_RX_LIST_CNT 1 419 420 struct ure_chain { 421 struct ure_softc *uc_sc; 422 struct usbd_xfer *uc_xfer; 423 char *uc_buf; 424 struct mbuf *uc_mbuf; 425 int uc_accum; 426 int uc_idx; 427 }; 428 429 struct ure_cdata { 430 struct ure_chain tx_chain[URE_TX_LIST_CNT]; 431 struct ure_chain rx_chain[URE_RX_LIST_CNT]; 432 int tx_prod; 433 int tx_const; 434 int tx_cnt; 435 int rx_prod; 436 }; 437 438 struct ure_softc { 439 struct device ure_dev; 440 struct usbd_device *ure_udev; 441 442 /* usb */ 443 struct usbd_interface *ure_iface; 444 struct usb_task ure_tick_task; 445 struct usb_task ure_stop_task; 446 int ure_ed[URE_ENDPT_MAX]; 447 struct usbd_pipe *ure_ep[URE_ENDPT_MAX]; 448 449 /* ethernet */ 450 struct arpcom ure_ac; 451 struct mii_data ure_mii; 452 struct rwlock ure_mii_lock; 453 int ure_refcnt; 454 455 struct ure_cdata ure_cdata; 456 struct timeout ure_stat_ch; 457 458 struct timeval ure_rx_notice; 459 int ure_bufsz; 460 461 int ure_phyno; 462 463 u_int ure_flags; 464 #define URE_FLAG_LINK 0x0001 465 466 u_int ure_chip; 467 #define URE_CHIP_VER_4C00 0x01 468 #define URE_CHIP_VER_4C10 0x02 469 }; 470 471