1 /* $OpenBSD: if_ure.c,v 1.32 2023/05/06 08:07:10 kevlo Exp $ */ 2 /*- 3 * Copyright (c) 2015, 2016, 2019 Kevin Lo <kevlo@openbsd.org> 4 * Copyright (c) 2020 Jonathon Fletcher <jonathon.fletcher@gmail.com> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "bpfilter.h" 30 #include "vlan.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/sockio.h> 35 #include <sys/rwlock.h> 36 #include <sys/mbuf.h> 37 #include <sys/kernel.h> 38 #include <sys/socket.h> 39 #include <sys/device.h> 40 41 #include <machine/bus.h> 42 43 #include <net/if.h> 44 #include <net/if_media.h> 45 46 #if NBPFILTER > 0 47 #include <net/bpf.h> 48 #endif 49 50 #include <netinet/in.h> 51 #include <netinet/if_ether.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 56 #include <dev/usb/usb.h> 57 #include <dev/usb/usbdi.h> 58 #include <dev/usb/usbdi_util.h> 59 #include <dev/usb/usbdivar.h> 60 #include <dev/usb/usbdevs.h> 61 62 #include <dev/ic/rtl81x9reg.h> 63 #include <dev/usb/if_urereg.h> 64 65 #ifdef URE_DEBUG 66 #define DPRINTF(x) do { if (uredebug) printf x; } while (0) 67 #define DPRINTFN(n,x) do { if (uredebug >= (n)) printf x; } while (0) 68 int uredebug = 0; 69 #else 70 #define DPRINTF(x) 71 #define DPRINTFN(n,x) 72 #endif 73 74 const struct usb_devno ure_devs[] = { 75 { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_RTL8156 }, 76 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8152B }, 77 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8153 }, 78 { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB3GIGV1 }, 79 { USB_VENDOR_CLEVO, USB_PRODUCT_CLEVO_RTL8153B }, 80 { USB_VENDOR_CLUB3D, USB_PRODUCT_CLUB3D_RTL8153 }, 81 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8153_1 }, 82 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8153_2 }, 83 { USB_VENDOR_DYNABOOK, USB_PRODUCT_DYNABOOK_RTL8153B_1 }, 84 { USB_VENDOR_DYNABOOK, USB_PRODUCT_DYNABOOK_RTL8153B_2 }, 85 { USB_VENDOR_ELECOM, USB_PRODUCT_ELECOM_RTL8153B }, 86 { USB_VENDOR_ELECOM, USB_PRODUCT_ELECOM_RTL8156B }, 87 { USB_VENDOR_IOI, USB_PRODUCT_IOI_RTL8153 }, 88 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_DOCK_ETHERNET }, 89 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ONELINK }, 90 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ONELINKPLUS }, 91 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ONELINKPRO }, 92 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_1 }, 93 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_2 }, 94 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_3 }, 95 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_4 }, 96 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_5 }, 97 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_6 }, 98 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_7 }, 99 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_8 }, 100 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_9 }, 101 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153_1 }, 102 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153_2 }, 103 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153_3 }, 104 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TABLETDOCK }, 105 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TB3DOCK }, 106 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TB3DOCKGEN2 }, 107 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TB3GFXDOCK }, 108 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_USBCDOCKGEN2 }, 109 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_WIGIGDOCK }, 110 { USB_VENDOR_LG, USB_PRODUCT_LG_RTL8153 }, 111 { USB_VENDOR_LG, USB_PRODUCT_LG_RTL8153B }, 112 { USB_VENDOR_LUXSHARE, USB_PRODUCT_LUXSHARE_RTL8153 }, 113 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_DOCKETH }, 114 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_DOCKETH2 }, 115 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_SURFETH }, 116 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_WINDEVETH }, 117 { USB_VENDOR_NVIDIA, USB_PRODUCT_NVIDIA_TEGRAETH }, 118 { USB_VENDOR_PIONEERDJ, USB_PRODUCT_PIONEERDJ_RTL8152B }, 119 { USB_VENDOR_PIONEERDJ, USB_PRODUCT_PIONEERDJ_RTL8153B }, 120 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 }, 121 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152B }, 122 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8153 }, 123 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8156 }, 124 { USB_VENDOR_SAMSUNG2, USB_PRODUCT_SAMSUNG2_RTL8153 }, 125 { USB_VENDOR_TOSHIBA, USB_PRODUCT_TOSHIBA_RTL8153B }, 126 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_EU300 }, 127 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_RTL8152B_1 }, 128 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_RTL8152B_2 }, 129 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_RTL8153 }, 130 { USB_VENDOR_TRENDNET, USB_PRODUCT_TRENDNET_RTL8156 }, 131 { USB_VENDOR_TTL, USB_PRODUCT_TTL_RTL8153 }, 132 { USB_VENDOR_TWINHEAD, USB_PRODUCT_TWINHEAD_RTL8153B }, 133 { USB_VENDOR_XIAOMI, USB_PRODUCT_XIAOMI_RTL8152B }, 134 }; 135 136 int ure_match(struct device *, void *, void *); 137 void ure_attach(struct device *, struct device *, void *); 138 int ure_detach(struct device *, int); 139 140 struct cfdriver ure_cd = { 141 NULL, "ure", DV_IFNET 142 }; 143 144 const struct cfattach ure_ca = { 145 sizeof(struct ure_softc), ure_match, ure_attach, ure_detach 146 }; 147 148 int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t, 149 void *, int); 150 int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *, 151 int); 152 int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *, 153 int); 154 uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t); 155 uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t); 156 uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t); 157 int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t); 158 int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t); 159 int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t); 160 uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t); 161 void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t); 162 163 void ure_init(void *); 164 void ure_stop(struct ure_softc *); 165 void ure_start(struct ifnet *); 166 void ure_reset(struct ure_softc *); 167 void ure_watchdog(struct ifnet *); 168 169 void ure_miibus_statchg(struct device *); 170 int ure_miibus_readreg(struct device *, int, int); 171 void ure_miibus_writereg(struct device *, int, int, int); 172 void ure_lock_mii(struct ure_softc *); 173 void ure_unlock_mii(struct ure_softc *); 174 175 int ure_encap_txpkt(struct mbuf *, char *, uint32_t); 176 int ure_encap_xfer(struct ifnet *, struct ure_softc *, 177 struct ure_chain *); 178 void ure_rxeof(struct usbd_xfer *, void *, usbd_status); 179 void ure_txeof(struct usbd_xfer *, void *, usbd_status); 180 int ure_xfer_list_init(struct ure_softc *, struct ure_chain *, 181 uint32_t, int); 182 void ure_xfer_list_free(struct ure_softc *, struct ure_chain *, int); 183 184 void ure_tick_task(void *); 185 void ure_tick(void *); 186 187 void ure_ifmedia_init(struct ifnet *); 188 int ure_ifmedia_upd(struct ifnet *); 189 void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *); 190 void ure_add_media_types(struct ure_softc *); 191 void ure_link_state(struct ure_softc *); 192 int ure_get_link_status(struct ure_softc *); 193 void ure_iff(struct ure_softc *); 194 void ure_rxvlan(struct ure_softc *); 195 int ure_ioctl(struct ifnet *, u_long, caddr_t); 196 void ure_rtl8152_init(struct ure_softc *); 197 void ure_rtl8153_init(struct ure_softc *); 198 void ure_rtl8153b_init(struct ure_softc *); 199 void ure_rtl8152_nic_reset(struct ure_softc *); 200 void ure_rtl8153_nic_reset(struct ure_softc *); 201 uint16_t ure_rtl8153_phy_status(struct ure_softc *, int); 202 void ure_wait_for_flash(struct ure_softc *); 203 void ure_reset_bmu(struct ure_softc *); 204 void ure_disable_teredo(struct ure_softc *); 205 206 #define URE_SETBIT_1(sc, reg, index, x) \ 207 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x)) 208 #define URE_SETBIT_2(sc, reg, index, x) \ 209 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x)) 210 #define URE_SETBIT_4(sc, reg, index, x) \ 211 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x)) 212 213 #define URE_CLRBIT_1(sc, reg, index, x) \ 214 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~(x)) 215 #define URE_CLRBIT_2(sc, reg, index, x) \ 216 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~(x)) 217 #define URE_CLRBIT_4(sc, reg, index, x) \ 218 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~(x)) 219 220 int 221 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index, 222 void *buf, int len) 223 { 224 usb_device_request_t req; 225 usbd_status err; 226 227 if (usbd_is_dying(sc->ure_udev)) 228 return 0; 229 230 if (rw == URE_CTL_WRITE) 231 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 232 else 233 req.bmRequestType = UT_READ_VENDOR_DEVICE; 234 req.bRequest = UR_SET_ADDRESS; 235 USETW(req.wValue, val); 236 USETW(req.wIndex, index); 237 USETW(req.wLength, len); 238 239 DPRINTFN(5, ("ure_ctl: rw %d, val 0x%04hu, index 0x%04hu, len %d\n", 240 rw, val, index, len)); 241 err = usbd_do_request(sc->ure_udev, &req, buf); 242 if (err) { 243 DPRINTF(("ure_ctl: error %d\n", err)); 244 return -1; 245 } 246 247 return 0; 248 } 249 250 int 251 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 252 void *buf, int len) 253 { 254 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len)); 255 } 256 257 int 258 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 259 void *buf, int len) 260 { 261 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len)); 262 } 263 264 uint8_t 265 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index) 266 { 267 uint32_t val; 268 uint8_t temp[4]; 269 uint8_t shift; 270 271 shift = (reg & 3) << 3; 272 reg &= ~3; 273 274 ure_read_mem(sc, reg, index, &temp, 4); 275 val = UGETDW(temp); 276 val >>= shift; 277 278 return (val & 0xff); 279 } 280 281 uint16_t 282 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index) 283 { 284 uint32_t val; 285 uint8_t temp[4]; 286 uint8_t shift; 287 288 shift = (reg & 2) << 3; 289 reg &= ~3; 290 291 ure_read_mem(sc, reg, index, &temp, 4); 292 val = UGETDW(temp); 293 val >>= shift; 294 295 return (val & 0xffff); 296 } 297 298 uint32_t 299 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index) 300 { 301 uint8_t temp[4]; 302 303 ure_read_mem(sc, reg, index, &temp, 4); 304 return (UGETDW(temp)); 305 } 306 307 int 308 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 309 { 310 uint16_t byen; 311 uint8_t temp[4]; 312 uint8_t shift; 313 314 byen = URE_BYTE_EN_BYTE; 315 shift = reg & 3; 316 val &= 0xff; 317 318 if (reg & 3) { 319 byen <<= shift; 320 val <<= (shift << 3); 321 reg &= ~3; 322 } 323 324 USETDW(temp, val); 325 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 326 } 327 328 int 329 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 330 { 331 uint16_t byen; 332 uint8_t temp[4]; 333 uint8_t shift; 334 335 byen = URE_BYTE_EN_WORD; 336 shift = reg & 2; 337 val &= 0xffff; 338 339 if (reg & 2) { 340 byen <<= shift; 341 val <<= (shift << 3); 342 reg &= ~3; 343 } 344 345 USETDW(temp, val); 346 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 347 } 348 349 int 350 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 351 { 352 uint8_t temp[4]; 353 354 USETDW(temp, val); 355 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4)); 356 } 357 358 uint16_t 359 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr) 360 { 361 uint16_t reg; 362 363 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 364 reg = (addr & 0x0fff) | 0xb000; 365 366 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA)); 367 } 368 369 void 370 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 371 { 372 uint16_t reg; 373 374 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 375 reg = (addr & 0x0fff) | 0xb000; 376 377 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data); 378 } 379 380 int 381 ure_miibus_readreg(struct device *dev, int phy, int reg) 382 { 383 struct ure_softc *sc = (void *)dev; 384 uint16_t val; 385 386 if (usbd_is_dying(sc->ure_udev)) 387 return 0; 388 389 /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */ 390 if (reg == RL_GMEDIASTAT) 391 return ure_read_1(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA); 392 393 ure_lock_mii(sc); 394 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2); 395 ure_unlock_mii(sc); 396 397 return val; /* letoh16? */ 398 } 399 400 void 401 ure_miibus_writereg(struct device *dev, int phy, int reg, int val) 402 { 403 struct ure_softc *sc = (void *)dev; 404 405 ure_lock_mii(sc); 406 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val); /* htole16? */ 407 ure_unlock_mii(sc); 408 } 409 410 void 411 ure_miibus_statchg(struct device *dev) 412 { 413 struct ure_softc *sc = (void *)dev; 414 struct mii_data *mii = &sc->ure_mii; 415 struct ifnet *ifp = &sc->ure_ac.ac_if; 416 417 if ((ifp->if_flags & IFF_RUNNING) == 0) 418 return; 419 420 sc->ure_flags &= ~URE_FLAG_LINK; 421 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 422 (IFM_ACTIVE | IFM_AVALID)) { 423 switch (IFM_SUBTYPE(mii->mii_media_active)) { 424 case IFM_10_T: 425 case IFM_100_TX: 426 sc->ure_flags |= URE_FLAG_LINK; 427 break; 428 case IFM_1000_T: 429 if ((sc->ure_flags & URE_FLAG_8152) != 0) 430 break; 431 sc->ure_flags |= URE_FLAG_LINK; 432 break; 433 default: 434 break; 435 } 436 } 437 438 /* Lost link, do nothing. */ 439 if ((sc->ure_flags & URE_FLAG_LINK) == 0) 440 return; 441 442 /* 443 * After a link change the media settings are getting reset on the 444 * hardware, and need to be re-initialized again for communication 445 * to continue work. 446 */ 447 ure_ifmedia_init(ifp); 448 } 449 450 void 451 ure_ifmedia_init(struct ifnet *ifp) 452 { 453 struct ure_softc *sc = ifp->if_softc; 454 uint32_t reg = 0; 455 456 /* Set MAC address. */ 457 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 458 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 459 sc->ure_ac.ac_enaddr, 8); 460 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 461 462 if (!(sc->ure_flags & URE_FLAG_8152)) { 463 if (sc->ure_flags & URE_FLAG_8156B) 464 URE_CLRBIT_2(sc, URE_USB_RX_AGGR_NUM, URE_MCU_TYPE_USB, 465 URE_RX_AGGR_NUM_MASK); 466 467 reg = sc->ure_rxbufsz - URE_FRAMELEN(ifp->if_mtu) - 468 sizeof(struct ure_rxpkt) - URE_RX_BUF_ALIGN; 469 if (sc->ure_flags & 470 (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) { 471 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, 472 reg / 8); 473 474 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 475 (sc->ure_flags & URE_FLAG_8153B) ? 158 : 80); 476 ure_write_2(sc, URE_USB_PM_CTRL_STATUS, 477 URE_MCU_TYPE_USB, 1875); 478 } else { 479 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, 480 reg / 4); 481 switch (sc->ure_udev->speed) { 482 case USB_SPEED_SUPER: 483 reg = URE_COALESCE_SUPER / 8; 484 break; 485 case USB_SPEED_HIGH: 486 reg = URE_COALESCE_HIGH / 8; 487 break; 488 default: 489 reg = URE_COALESCE_SLOW / 8; 490 break; 491 } 492 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 493 reg); 494 } 495 496 if (sc->ure_chip & URE_CHIP_VER_7420) { 497 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL4, 498 URE_MCU_TYPE_PLA, URE_IDLE_SPDWN_EN); 499 } 500 501 if ((sc->ure_chip & URE_CHIP_VER_6010) || 502 (sc->ure_flags & URE_FLAG_8156B)) { 503 URE_CLRBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, 504 URE_FC_PATCH_TASK); 505 usbd_delay_ms(sc->ure_udev, 1); 506 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, 507 URE_FC_PATCH_TASK); 508 } 509 } 510 511 /* Reset the packet filter. */ 512 URE_CLRBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN); 513 URE_SETBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN); 514 515 /* Enable transmit and receive. */ 516 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE); 517 518 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) { 519 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB, 520 URE_OWN_UPDATE | URE_OWN_CLEAR); 521 } 522 523 URE_CLRBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 524 } 525 526 int 527 ure_ifmedia_upd(struct ifnet *ifp) 528 { 529 struct ure_softc *sc = ifp->if_softc; 530 struct mii_data *mii = &sc->ure_mii; 531 struct ifmedia *ifm = &sc->ure_ifmedia; 532 int anar, gig, err, reg; 533 534 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 535 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 536 return (EINVAL); 537 538 if (!(sc->ure_chip & URE_CHIP_VER_7420)) { 539 reg = ure_ocp_reg_read(sc, URE_OCP_10GBT_CTRL); 540 reg &= ~URE_ADV_2500TFDX; 541 } 542 543 anar = gig = 0; 544 switch (IFM_SUBTYPE(ifm->ifm_media)) { 545 case IFM_AUTO: 546 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 547 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 548 if (!(sc->ure_chip & URE_CHIP_VER_7420)) 549 reg |= URE_ADV_2500TFDX; 550 break; 551 case IFM_2500_T: 552 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 553 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 554 reg |= URE_ADV_2500TFDX; 555 ifp->if_baudrate = IF_Mbps(2500); 556 break; 557 case IFM_1000_T: 558 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 559 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 560 ifp->if_baudrate = IF_Gbps(1); 561 break; 562 case IFM_100_TX: 563 anar |= ANAR_TX | ANAR_TX_FD; 564 ifp->if_baudrate = IF_Mbps(100); 565 break; 566 case IFM_10_T: 567 anar |= ANAR_10 | ANAR_10_FD; 568 ifp->if_baudrate = IF_Mbps(10); 569 break; 570 default: 571 printf("%s: unsupported media type\n", 572 sc->ure_dev.dv_xname); 573 return (EINVAL); 574 } 575 576 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_ANAR * 2, 577 anar | ANAR_PAUSE_ASYM | ANAR_FC); 578 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_100T2CR * 2, gig); 579 if (!(sc->ure_chip & URE_CHIP_VER_7420)) 580 ure_ocp_reg_write(sc, URE_OCP_10GBT_CTRL, reg); 581 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR, 582 BMCR_AUTOEN | BMCR_STARTNEG); 583 584 return (0); 585 } 586 587 if (mii->mii_instance) { 588 struct mii_softc *miisc; 589 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 590 PHY_RESET(miisc); 591 } 592 593 err = mii_mediachg(mii); 594 if (err == ENXIO) 595 return (0); 596 else 597 return (err); 598 } 599 600 void 601 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 602 { 603 struct ure_softc *sc = ifp->if_softc; 604 struct mii_data *mii = &sc->ure_mii; 605 uint16_t status = 0; 606 607 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 608 ifmr->ifm_status = IFM_AVALID; 609 if (ure_get_link_status(sc)) { 610 ifmr->ifm_status |= IFM_ACTIVE; 611 status = ure_read_2(sc, URE_PLA_PHYSTATUS, 612 URE_MCU_TYPE_PLA); 613 if ((status & URE_PHYSTATUS_FDX) || 614 (status & URE_PHYSTATUS_2500MBPS)) 615 ifmr->ifm_active |= IFM_FDX; 616 else 617 ifmr->ifm_active |= IFM_HDX; 618 if (status & URE_PHYSTATUS_10MBPS) 619 ifmr->ifm_active |= IFM_10_T; 620 else if (status & URE_PHYSTATUS_100MBPS) 621 ifmr->ifm_active |= IFM_100_TX; 622 else if (status & URE_PHYSTATUS_1000MBPS) 623 ifmr->ifm_active |= IFM_1000_T; 624 else if (status & URE_PHYSTATUS_2500MBPS) 625 ifmr->ifm_active |= IFM_2500_T; 626 } 627 return; 628 } 629 630 mii_pollstat(mii); 631 ifmr->ifm_active = mii->mii_media_active; 632 ifmr->ifm_status = mii->mii_media_status; 633 } 634 635 void 636 ure_add_media_types(struct ure_softc *sc) 637 { 638 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 639 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 640 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 641 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, 642 NULL); 643 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 644 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, 645 NULL); 646 if (!(sc->ure_chip & URE_CHIP_VER_7420)) { 647 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_2500_T, 0, NULL); 648 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_2500_T | IFM_FDX, 649 0, NULL); 650 } 651 } 652 653 void 654 ure_link_state(struct ure_softc *sc) 655 { 656 struct ifnet *ifp = &sc->ure_ac.ac_if; 657 int link = LINK_STATE_DOWN; 658 659 if (ure_get_link_status(sc)) 660 link = LINK_STATE_UP; 661 662 if (ifp->if_link_state != link) { 663 ifp->if_link_state = link; 664 if_link_state_change(ifp); 665 } 666 } 667 668 int 669 ure_get_link_status(struct ure_softc *sc) 670 { 671 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & 672 URE_PHYSTATUS_LINK) { 673 sc->ure_flags |= URE_FLAG_LINK; 674 return (1); 675 } else { 676 sc->ure_flags &= ~URE_FLAG_LINK; 677 return (0); 678 } 679 } 680 681 void 682 ure_iff(struct ure_softc *sc) 683 { 684 struct ifnet *ifp = &sc->ure_ac.ac_if; 685 struct ether_multi *enm; 686 struct ether_multistep step; 687 uint32_t hashes[2] = { 0, 0 }; 688 uint32_t hash; 689 uint32_t rxmode; 690 691 if (usbd_is_dying(sc->ure_udev)) 692 return; 693 694 rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA); 695 rxmode &= ~URE_RCR_ACPT_ALL; 696 ifp->if_flags &= ~IFF_ALLMULTI; 697 698 /* 699 * Always accept frames destined to our station address. 700 * Always accept broadcast frames. 701 */ 702 rxmode |= URE_RCR_APM | URE_RCR_AB; 703 704 if (ifp->if_flags & IFF_PROMISC || sc->ure_ac.ac_multirangecnt > 0) { 705 ifp->if_flags |= IFF_ALLMULTI; 706 rxmode |= URE_RCR_AM; 707 if (ifp->if_flags & IFF_PROMISC) 708 rxmode |= URE_RCR_AAP; 709 hashes[0] = hashes[1] = 0xffffffff; 710 } else { 711 rxmode |= URE_RCR_AM; 712 713 ETHER_FIRST_MULTI(step, &sc->ure_ac, enm); 714 while (enm != NULL) { 715 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) 716 >> 26; 717 if (hash < 32) 718 hashes[0] |= (1 << hash); 719 else 720 hashes[1] |= (1 << (hash - 32)); 721 722 ETHER_NEXT_MULTI(step, enm); 723 } 724 725 hash = swap32(hashes[0]); 726 hashes[0] = swap32(hashes[1]); 727 hashes[1] = hash; 728 } 729 730 ure_write_mem(sc, URE_PLA_MAR, URE_MCU_TYPE_PLA | URE_BYTE_EN_DWORD, 731 hashes, sizeof(hashes)); 732 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 733 } 734 735 void 736 ure_rxvlan(struct ure_softc *sc) 737 { 738 struct ifnet *ifp = &sc->ure_ac.ac_if; 739 uint16_t reg; 740 741 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 742 reg = ure_read_2(sc, URE_PLA_RCR1, URE_MCU_TYPE_PLA); 743 reg &= ~(URE_INNER_VLAN | URE_OUTER_VLAN); 744 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 745 reg |= (URE_INNER_VLAN | URE_OUTER_VLAN); 746 ure_write_2(sc, URE_PLA_RCR1, URE_MCU_TYPE_PLA, reg); 747 } else { 748 reg = ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA); 749 reg &= ~URE_CPCR_RX_VLAN; 750 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 751 reg |= URE_CPCR_RX_VLAN; 752 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, reg); 753 } 754 } 755 756 void 757 ure_reset(struct ure_softc *sc) 758 { 759 int i; 760 761 if (sc->ure_flags & URE_FLAG_8156) { 762 URE_CLRBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_TE); 763 URE_CLRBIT_2(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, 764 BMU_RESET_EP_IN); 765 URE_SETBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 766 URE_CDC_ECM_EN); 767 URE_CLRBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE); 768 URE_SETBIT_2(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, 769 BMU_RESET_EP_IN); 770 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 771 URE_CDC_ECM_EN); 772 } else { 773 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 774 775 for (i = 0; i < URE_TIMEOUT; i++) { 776 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) & 777 URE_CR_RST)) 778 break; 779 DELAY(100); 780 } 781 if (i == URE_TIMEOUT) 782 printf("%s: reset never completed\n", 783 sc->ure_dev.dv_xname); 784 } 785 } 786 787 void 788 ure_watchdog(struct ifnet *ifp) 789 { 790 struct ure_softc *sc = ifp->if_softc; 791 struct ure_chain *c; 792 usbd_status err; 793 int i, s; 794 795 ifp->if_timer = 0; 796 797 if (usbd_is_dying(sc->ure_udev)) 798 return; 799 800 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) 801 return; 802 803 sc = ifp->if_softc; 804 s = splnet(); 805 806 ifp->if_oerrors++; 807 DPRINTF(("%s: watchdog timeout\n", sc->ure_dev.dv_xname)); 808 809 for (i = 0; i < URE_TX_LIST_CNT; i++) { 810 c = &sc->ure_cdata.ure_tx_chain[i]; 811 if (c->uc_cnt > 0) { 812 usbd_get_xfer_status(c->uc_xfer, NULL, NULL, NULL, 813 &err); 814 ure_txeof(c->uc_xfer, c, err); 815 } 816 } 817 818 if (ifq_is_oactive(&ifp->if_snd)) 819 ifq_restart(&ifp->if_snd); 820 splx(s); 821 } 822 823 void 824 ure_init(void *xsc) 825 { 826 struct ure_softc *sc = xsc; 827 struct ure_chain *c; 828 struct ifnet *ifp = &sc->ure_ac.ac_if; 829 usbd_status err; 830 int s, i; 831 832 s = splnet(); 833 834 /* Cancel pending I/O. */ 835 ure_stop(sc); 836 837 if (sc->ure_flags & URE_FLAG_8152) 838 ure_rtl8152_nic_reset(sc); 839 else 840 ure_rtl8153_nic_reset(sc); 841 842 if (ure_xfer_list_init(sc, sc->ure_cdata.ure_rx_chain, 843 sc->ure_rxbufsz, URE_RX_LIST_CNT) == ENOBUFS) { 844 printf("%s: rx list init failed\n", sc->ure_dev.dv_xname); 845 splx(s); 846 return; 847 } 848 849 if (ure_xfer_list_init(sc, sc->ure_cdata.ure_tx_chain, 850 sc->ure_txbufsz, URE_TX_LIST_CNT) == ENOBUFS) { 851 printf("%s: tx list init failed\n", sc->ure_dev.dv_xname); 852 splx(s); 853 return; 854 } 855 856 /* Initialize the SLIST we are using for the multiple tx buffers */ 857 SLIST_INIT(&sc->ure_cdata.ure_tx_free); 858 for (i = 0; i < URE_TX_LIST_CNT; i++) 859 SLIST_INSERT_HEAD(&sc->ure_cdata.ure_tx_free, 860 &sc->ure_cdata.ure_tx_chain[i], uc_list); 861 862 /* Setup MAC address, and enable TX/RX. */ 863 ure_ifmedia_init(ifp); 864 865 /* Load the multicast filter. */ 866 ure_iff(sc); 867 868 /* Open RX and TX pipes. */ 869 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_RX], 870 USBD_EXCLUSIVE_USE, &sc->ure_ep[URE_ENDPT_RX]); 871 if (err) { 872 printf("%s: open rx pipe failed: %s\n", 873 sc->ure_dev.dv_xname, usbd_errstr(err)); 874 splx(s); 875 return; 876 } 877 878 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_TX], 879 USBD_EXCLUSIVE_USE, &sc->ure_ep[URE_ENDPT_TX]); 880 if (err) { 881 printf("%s: open tx pipe failed: %s\n", 882 sc->ure_dev.dv_xname, usbd_errstr(err)); 883 splx(s); 884 return; 885 } 886 887 /* Start up the receive pipe. */ 888 for (i = 0; i < URE_RX_LIST_CNT; i++) { 889 c = &sc->ure_cdata.ure_rx_chain[i]; 890 usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_RX], 891 c, c->uc_buf, c->uc_bufmax, 892 USBD_SHORT_XFER_OK | USBD_NO_COPY, 893 USBD_NO_TIMEOUT, ure_rxeof); 894 usbd_transfer(c->uc_xfer); 895 } 896 897 ure_ifmedia_upd(ifp); 898 899 /* Indicate we are up and running. */ 900 sc->ure_flags &= ~URE_FLAG_LINK; 901 ifp->if_flags |= IFF_RUNNING; 902 ifq_clr_oactive(&ifp->if_snd); 903 904 timeout_add_sec(&sc->ure_stat_ch, 1); 905 906 splx(s); 907 } 908 909 void 910 ure_start(struct ifnet *ifp) 911 { 912 struct ure_softc *sc = ifp->if_softc; 913 struct ure_cdata *cd = &sc->ure_cdata; 914 struct ure_chain *c; 915 struct mbuf *m = NULL; 916 uint32_t new_buflen; 917 int s, mlen; 918 919 if (!(sc->ure_flags & URE_FLAG_LINK) || 920 (ifp->if_flags & (IFF_RUNNING|IFF_UP)) != 921 (IFF_RUNNING|IFF_UP)) { 922 return; 923 } 924 925 s = splnet(); 926 927 c = SLIST_FIRST(&cd->ure_tx_free); 928 while (c != NULL) { 929 m = ifq_deq_begin(&ifp->if_snd); 930 if (m == NULL) 931 break; 932 933 mlen = m->m_pkthdr.len; 934 935 /* Discard packet larger than buffer. */ 936 if (mlen + sizeof(struct ure_txpkt) >= c->uc_bufmax) { 937 ifq_deq_commit(&ifp->if_snd, m); 938 m_freem(m); 939 ifp->if_oerrors++; 940 continue; 941 } 942 943 /* 944 * If packet larger than remaining space, send buffer and 945 * continue. 946 */ 947 new_buflen = roundup(c->uc_buflen, URE_TX_BUF_ALIGN); 948 if (new_buflen + sizeof(struct ure_txpkt) + mlen >= 949 c->uc_bufmax) { 950 ifq_deq_rollback(&ifp->if_snd, m); 951 SLIST_REMOVE_HEAD(&cd->ure_tx_free, uc_list); 952 if (ure_encap_xfer(ifp, sc, c)) { 953 SLIST_INSERT_HEAD(&cd->ure_tx_free, c, 954 uc_list); 955 break; 956 } 957 c = SLIST_FIRST(&cd->ure_tx_free); 958 continue; 959 } 960 961 /* Append packet to current buffer. */ 962 mlen = ure_encap_txpkt(m, c->uc_buf + new_buflen, 963 c->uc_bufmax - new_buflen); 964 if (mlen <= 0) { 965 ifq_deq_rollback(&ifp->if_snd, m); 966 break; 967 } 968 969 ifq_deq_commit(&ifp->if_snd, m); 970 c->uc_cnt += 1; 971 c->uc_buflen = new_buflen + mlen; 972 973 #if NBPFILTER > 0 974 if (ifp->if_bpf) 975 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 976 #endif 977 978 m_freem(m); 979 } 980 981 if (c != NULL) { 982 /* Send current buffer unless empty */ 983 if (c->uc_buflen > 0 && c->uc_cnt > 0) { 984 SLIST_REMOVE_HEAD(&cd->ure_tx_free, uc_list); 985 if (ure_encap_xfer(ifp, sc, c)) { 986 SLIST_INSERT_HEAD(&cd->ure_tx_free, c, 987 uc_list); 988 } 989 c = SLIST_FIRST(&cd->ure_tx_free); 990 } 991 } 992 993 ifp->if_timer = 5; 994 if (c == NULL) 995 ifq_set_oactive(&ifp->if_snd); 996 splx(s); 997 } 998 999 void 1000 ure_tick(void *xsc) 1001 { 1002 struct ure_softc *sc = xsc; 1003 1004 if (sc == NULL) 1005 return; 1006 1007 if (usbd_is_dying(sc->ure_udev)) 1008 return; 1009 1010 usb_add_task(sc->ure_udev, &sc->ure_tick_task); 1011 } 1012 1013 void 1014 ure_stop(struct ure_softc *sc) 1015 { 1016 struct ure_cdata *cd; 1017 struct ifnet *ifp; 1018 usbd_status err; 1019 1020 ure_reset(sc); 1021 1022 ifp = &sc->ure_ac.ac_if; 1023 ifp->if_timer = 0; 1024 ifp->if_flags &= ~IFF_RUNNING; 1025 ifq_clr_oactive(&ifp->if_snd); 1026 1027 timeout_del(&sc->ure_stat_ch); 1028 sc->ure_flags &= ~URE_FLAG_LINK; 1029 1030 if (sc->ure_ep[URE_ENDPT_RX] != NULL) { 1031 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_RX]); 1032 if (err) { 1033 printf("%s: close rx pipe failed: %s\n", 1034 sc->ure_dev.dv_xname, usbd_errstr(err)); 1035 } 1036 sc->ure_ep[URE_ENDPT_RX] = NULL; 1037 } 1038 1039 if (sc->ure_ep[URE_ENDPT_TX] != NULL) { 1040 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_TX]); 1041 if (err) { 1042 printf("%s: close tx pipe failed: %s\n", 1043 sc->ure_dev.dv_xname, usbd_errstr(err)); 1044 } 1045 sc->ure_ep[URE_ENDPT_TX] = NULL; 1046 } 1047 1048 cd = &sc->ure_cdata; 1049 ure_xfer_list_free(sc, cd->ure_rx_chain, URE_RX_LIST_CNT); 1050 ure_xfer_list_free(sc, cd->ure_tx_chain, URE_TX_LIST_CNT); 1051 } 1052 1053 int 1054 ure_xfer_list_init(struct ure_softc *sc, struct ure_chain *ch, 1055 uint32_t bufsize, int listlen) 1056 { 1057 struct ure_chain *c; 1058 int i; 1059 1060 for (i = 0; i < listlen; i++) { 1061 c = &ch[i]; 1062 c->uc_sc = sc; 1063 c->uc_idx = i; 1064 c->uc_buflen = 0; 1065 c->uc_bufmax = bufsize; 1066 c->uc_cnt = 0; 1067 if (c->uc_xfer == NULL) { 1068 c->uc_xfer = usbd_alloc_xfer(sc->ure_udev); 1069 if (c->uc_xfer == NULL) 1070 return (ENOBUFS); 1071 c->uc_buf = usbd_alloc_buffer(c->uc_xfer, c->uc_bufmax); 1072 if (c->uc_buf == NULL) { 1073 usbd_free_xfer(c->uc_xfer); 1074 c->uc_xfer = NULL; 1075 return (ENOBUFS); 1076 } 1077 } 1078 } 1079 1080 return (0); 1081 } 1082 1083 void 1084 ure_xfer_list_free(struct ure_softc *sc, struct ure_chain *ch, int listlen) 1085 { 1086 int i; 1087 1088 for (i = 0; i < listlen; i++) { 1089 if (ch[i].uc_buf != NULL) { 1090 ch[i].uc_buf = NULL; 1091 } 1092 ch[i].uc_cnt = 0; 1093 if (ch[i].uc_xfer != NULL) { 1094 usbd_free_xfer(ch[i].uc_xfer); 1095 ch[i].uc_xfer = NULL; 1096 } 1097 } 1098 } 1099 1100 void 1101 ure_rtl8152_init(struct ure_softc *sc) 1102 { 1103 uint32_t pwrctrl; 1104 1105 /* Disable ALDPS. */ 1106 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 1107 URE_DIS_SDSAVE); 1108 usbd_delay_ms(sc->ure_udev, 20); 1109 1110 if (sc->ure_chip & URE_CHIP_VER_4C00) 1111 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 1112 URE_LED_MODE_MASK); 1113 1114 URE_CLRBIT_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, URE_POWER_CUT); 1115 URE_CLRBIT_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 1116 URE_RESUME_INDICATE); 1117 1118 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 1119 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 1120 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 1121 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 1122 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 1123 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 1124 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 1125 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 1126 URE_SPDWN_LINKCHG_MSK); 1127 1128 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET); 1129 1130 /* Enable Rx aggregation. */ 1131 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1132 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1133 } 1134 1135 void 1136 ure_rtl8153_init(struct ure_softc *sc) 1137 { 1138 uint16_t reg; 1139 uint8_t u1u2[8]; 1140 int i; 1141 1142 memset(u1u2, 0x00, sizeof(u1u2)); 1143 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, u1u2, 1144 sizeof(u1u2)); 1145 1146 for (i = 0; i < 500; i++) { 1147 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 1148 URE_AUTOLOAD_DONE) 1149 break; 1150 usbd_delay_ms(sc->ure_udev, 20); 1151 } 1152 if (i == 500) 1153 printf("%s: timeout waiting for chip autoload\n", 1154 sc->ure_dev.dv_xname); 1155 1156 ure_rtl8153_phy_status(sc, 0); 1157 1158 if (sc->ure_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 | 1159 URE_CHIP_VER_5C20)) { 1160 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG, 1161 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 1162 } 1163 1164 ure_rtl8153_phy_status(sc, URE_PHY_STAT_LAN_ON); 1165 1166 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1167 1168 if (sc->ure_chip & URE_CHIP_VER_5C10) { 1169 reg = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 1170 reg &= ~URE_PWD_DN_SCALE_MASK; 1171 reg |= URE_PWD_DN_SCALE(96); 1172 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, reg); 1173 1174 URE_SETBIT_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 1175 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 1176 } else if (sc->ure_chip & URE_CHIP_VER_5C20) { 1177 URE_CLRBIT_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 1178 URE_ECM_ALDPS); 1179 } 1180 if (sc->ure_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) { 1181 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB)) 1182 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, 1183 URE_DYNAMIC_BURST); 1184 else 1185 URE_CLRBIT_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, 1186 URE_DYNAMIC_BURST); 1187 } 1188 1189 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, URE_EP4_FULL_FC); 1190 1191 URE_CLRBIT_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, URE_TIMER11_EN); 1192 1193 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 1194 URE_LED_MODE_MASK); 1195 1196 if ((sc->ure_chip & URE_CHIP_VER_5C10) && 1197 sc->ure_udev->speed != USB_SPEED_SUPER) 1198 reg = URE_LPM_TIMER_500MS; 1199 else 1200 reg = URE_LPM_TIMER_500US; 1201 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 1202 URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM | reg); 1203 1204 reg = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 1205 reg &= ~URE_SEN_VAL_MASK; 1206 reg |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 1207 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, reg); 1208 1209 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 1210 1211 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 1212 URE_PWR_EN | URE_PHASE2_EN); 1213 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS); 1214 1215 memset(u1u2, 0xff, sizeof(u1u2)); 1216 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, u1u2, 1217 sizeof(u1u2)); 1218 1219 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0); 1220 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 0); 1221 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 0); 1222 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0); 1223 1224 /* Enable Rx aggregation. */ 1225 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1226 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1227 1228 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET); 1229 } 1230 1231 void 1232 ure_rtl8153b_init(struct ure_softc *sc) 1233 { 1234 uint16_t reg; 1235 int i; 1236 1237 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1238 URE_CLRBIT_1(sc, URE_USB_ECM_OP, URE_MCU_TYPE_USB, 1239 URE_EN_ALL_SPEED); 1240 ure_write_2(sc, URE_USB_SPEED_OPTION, URE_MCU_TYPE_USB, 0); 1241 URE_SETBIT_2(sc, URE_USB_ECM_OPTION, URE_MCU_TYPE_USB, 1242 URE_BYPASS_MAC_RESET); 1243 1244 if (sc->ure_flags & URE_FLAG_8156B) 1245 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 1246 URE_RX_DETECT8); 1247 } 1248 1249 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, LPM_U1U2_EN); 1250 1251 if (sc->ure_flags & URE_FLAG_8156B) 1252 ure_wait_for_flash(sc); 1253 1254 for (i = 0; i < 500; i++) { 1255 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 1256 URE_AUTOLOAD_DONE) 1257 break; 1258 usbd_delay_ms(sc->ure_udev, 20); 1259 } 1260 if (i == 500) 1261 printf("%s: timeout waiting for chip autoload\n", 1262 sc->ure_dev.dv_xname); 1263 1264 ure_rtl8153_phy_status(sc, 0); 1265 ure_rtl8153_phy_status(sc, URE_PHY_STAT_LAN_ON); 1266 1267 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1268 1269 /* MSC timer, 32760 ms. */ 1270 ure_write_2(sc, URE_USB_MSC_TIMER, URE_MCU_TYPE_USB, 4095); 1271 1272 if (!(sc->ure_flags & URE_FLAG_8153B)) { 1273 /* U1/U2/L1 idle timer, 500 us. */ 1274 ure_write_2(sc, URE_USB_U1U2_TIMER, URE_MCU_TYPE_USB, 500); 1275 } 1276 1277 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN); 1278 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS); 1279 1280 URE_CLRBIT_1(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 1281 URE_UPS_EN | URE_USP_PREWAKE); 1282 URE_CLRBIT_1(sc, URE_USB_MISC_2, URE_MCU_TYPE_USB, 1283 URE_UPS_FORCE_PWR_DOWN | URE_UPS_NO_UPS); 1284 1285 URE_CLRBIT_1(sc, URE_PLA_INDICATE_FALG, URE_MCU_TYPE_PLA, 1286 URE_UPCOMING_RUNTIME_D3); 1287 URE_CLRBIT_1(sc, URE_PLA_SUSPEND_FLAG, URE_MCU_TYPE_PLA, 1288 URE_LINK_CHG_EVENT); 1289 URE_CLRBIT_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, 1290 URE_LINK_CHANGE_FLAG); 1291 1292 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 1293 URE_CLRBIT_2(sc, URE_PLA_CONFIG34, URE_MCU_TYPE_PLA, 1294 URE_LINK_OFF_WAKE_EN); 1295 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 1296 1297 if (sc->ure_flags & URE_FLAG_8153B) { 1298 reg = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA); 1299 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & 1300 URE_PHYSTATUS_LINK) 1301 reg |= URE_CUR_LINK_OK; 1302 else 1303 reg &= ~URE_CUR_LINK_OK; 1304 ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, 1305 reg | URE_POLL_LINK_CHG); 1306 } 1307 1308 if (sc->ure_udev->speed == USB_SPEED_SUPER) { 1309 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, 1310 LPM_U1U2_EN); 1311 } 1312 1313 if (sc->ure_flags & URE_FLAG_8156B) { 1314 URE_CLRBIT_2(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_SLOT_EN); 1315 URE_SETBIT_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 1316 URE_FLOW_CTRL_EN); 1317 1318 /* Enable fc timer and set timer to 600 ms. */ 1319 ure_write_2(sc, URE_USB_FC_TIMER, URE_MCU_TYPE_USB, 1320 URE_CTRL_TIMER_EN | 75); 1321 1322 reg = ure_read_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB); 1323 if (!(ure_read_2(sc, URE_PLA_POL_GPIO_CTRL, URE_MCU_TYPE_PLA) & 1324 URE_DACK_DET_EN)) 1325 reg |= URE_FLOW_CTRL_PATCH_2; 1326 reg &= ~URE_AUTO_SPEEDUP; 1327 ure_write_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB, reg); 1328 1329 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, 1330 URE_FC_PATCH_TASK); 1331 } 1332 1333 /* MAC clock speed down. */ 1334 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1335 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0x0403); 1336 reg = ure_read_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA); 1337 reg &= ~URE_EEE_SPDWN_RATIO_MASK; 1338 reg |= URE_MAC_CLK_SPDWN_EN | 0x0003; 1339 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, reg); 1340 1341 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 1342 URE_PLA_MCU_SPDWN_EN); 1343 1344 reg = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA); 1345 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & 1346 URE_PHYSTATUS_LINK) 1347 reg |= URE_CUR_LINK_OK; 1348 else 1349 reg &= ~URE_CUR_LINK_OK; 1350 ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, 1351 reg | URE_POLL_LINK_CHG); 1352 } else 1353 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 1354 URE_MAC_CLK_SPDWN_EN); 1355 1356 /* Enable Rx aggregation. */ 1357 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1358 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1359 1360 if (sc->ure_flags & URE_FLAG_8156) 1361 URE_SETBIT_1(sc, URE_USB_BMU_CONFIG, URE_MCU_TYPE_USB, 1362 URE_ACT_ODMA); 1363 1364 if (!(sc->ure_flags & URE_FLAG_8153B)) { 1365 /* 1366 * Select force mode through 0xa5b4 bit 15 1367 * 0: MDIO force mode 1368 * 1: MMD force mode 1369 */ 1370 reg = ure_ocp_reg_read(sc, 0xa5b4); 1371 if (reg & 0x8000) 1372 ure_ocp_reg_write(sc, 0xa5b4, reg & ~0x8000); 1373 } 1374 1375 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET); 1376 } 1377 1378 void 1379 ure_rtl8152_nic_reset(struct ure_softc *sc) 1380 { 1381 uint32_t rx_fifo1, rx_fifo2; 1382 int i; 1383 1384 /* Disable ALDPS. */ 1385 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 1386 URE_DIS_SDSAVE); 1387 usbd_delay_ms(sc->ure_udev, 20); 1388 1389 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL); 1390 1391 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 1392 ure_disable_teredo(sc); 1393 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 1394 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 1395 1396 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB); 1397 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN); 1398 for (i = 0; i < URE_TIMEOUT; i++) { 1399 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1400 URE_LINK_LIST_READY) 1401 break; 1402 usbd_delay_ms(sc->ure_udev, 1); 1403 } 1404 if (i == URE_TIMEOUT) 1405 printf("%s: timeout waiting for OOB control\n", 1406 sc->ure_dev.dv_xname); 1407 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL); 1408 for (i = 0; i < URE_TIMEOUT; i++) { 1409 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1410 URE_LINK_LIST_READY) 1411 break; 1412 usbd_delay_ms(sc->ure_udev, 1); 1413 } 1414 if (i == URE_TIMEOUT) 1415 printf("%s: timeout waiting for OOB control\n", 1416 sc->ure_dev.dv_xname); 1417 1418 ure_reset(sc); 1419 1420 /* Configure Rx FIFO threshold. */ 1421 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 1422 URE_RXFIFO_THR1_NORMAL); 1423 if (sc->ure_udev->speed == USB_SPEED_FULL) { 1424 rx_fifo1 = URE_RXFIFO_THR2_FULL; 1425 rx_fifo2 = URE_RXFIFO_THR3_FULL; 1426 } else { 1427 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 1428 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 1429 } 1430 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 1431 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 1432 1433 /* Configure Tx FIFO threshold. */ 1434 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 1435 URE_TXFIFO_THR_NORMAL); 1436 1437 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 1438 URE_TX_AGG_MAX_THRESHOLD); 1439 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 1440 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 1441 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 1442 1443 ure_rxvlan(sc); 1444 ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA, 1445 ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1446 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO); 1447 1448 /* Enable ALDPS. */ 1449 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, 1450 URE_ENPWRSAVE | URE_ENPDNPS | URE_LINKENA | URE_DIS_SDSAVE); 1451 } 1452 1453 void 1454 ure_rtl8153_nic_reset(struct ure_softc *sc) 1455 { 1456 struct ifnet *ifp = &sc->ure_ac.ac_if; 1457 uint32_t reg = 0; 1458 uint8_t u1u2[8] = { 0 }; 1459 int i; 1460 1461 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) { 1462 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, 1463 LPM_U1U2_EN); 1464 } else { 1465 memset(u1u2, 0x00, sizeof(u1u2)); 1466 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, 1467 u1u2, sizeof(u1u2)); 1468 } 1469 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1470 1471 /* Disable ALDPS. */ 1472 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1473 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 1474 for (i = 0; i < 20; i++) { 1475 usbd_delay_ms(sc->ure_udev, 1); 1476 if (ure_read_2(sc, 0xe000, URE_MCU_TYPE_PLA) & 0x0100) 1477 break; 1478 } 1479 1480 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 1481 ure_disable_teredo(sc); 1482 1483 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL); 1484 1485 ure_reset(sc); 1486 ure_reset_bmu(sc); 1487 1488 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB); 1489 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN); 1490 1491 if (!(sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B))) { 1492 for (i = 0; i < URE_TIMEOUT; i++) { 1493 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1494 URE_LINK_LIST_READY) 1495 break; 1496 usbd_delay_ms(sc->ure_udev, 1); 1497 } 1498 if (i == URE_TIMEOUT) 1499 printf("%s: timeout waiting for OOB control\n", 1500 sc->ure_dev.dv_xname); 1501 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 1502 URE_RE_INIT_LL); 1503 for (i = 0; i < URE_TIMEOUT; i++) { 1504 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1505 URE_LINK_LIST_READY) 1506 break; 1507 usbd_delay_ms(sc->ure_udev, 1); 1508 } 1509 if (i == URE_TIMEOUT) 1510 printf("%s: timeout waiting for OOB control\n", 1511 sc->ure_dev.dv_xname); 1512 } 1513 1514 ure_rxvlan(sc); 1515 1516 ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA, 1517 URE_FRAMELEN(ifp->if_mtu)); 1518 ure_write_1(sc, URE_PLA_MTPS, URE_MCU_TYPE_PLA, MTPS_JUMBO); 1519 1520 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1521 ure_write_2(sc, URE_PLA_RX_FIFO_FULL, URE_MCU_TYPE_PLA, 1522 (sc->ure_flags & URE_FLAG_8156) ? 1024 : 512); 1523 ure_write_2(sc, URE_PLA_RX_FIFO_EMPTY, URE_MCU_TYPE_PLA, 1524 (sc->ure_flags & URE_FLAG_8156) ? 2048 : 1024); 1525 1526 /* Tx share fifo free credit full threshold. */ 1527 ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 8); 1528 ure_write_2(sc, URE_PLA_TXFIFO_FULL, URE_MCU_TYPE_PLA, 128); 1529 1530 if (sc->ure_flags & URE_FLAG_8156) 1531 URE_SETBIT_2(sc, URE_USB_BMU_CONFIG, URE_MCU_TYPE_USB, 1532 URE_ACT_ODMA); 1533 1534 /* FIFO settings */ 1535 reg = ure_read_2(sc, URE_PLA_RXFIFO_FULL, URE_MCU_TYPE_PLA); 1536 reg &= ~URE_RXFIFO_FULL_MASK; 1537 ure_write_2(sc, URE_PLA_RXFIFO_FULL, URE_MCU_TYPE_PLA, 1538 reg | 0x0008); 1539 1540 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 1541 URE_PLA_MCU_SPDWN_EN); 1542 1543 URE_CLRBIT_2(sc, URE_USB_SPEED_OPTION, URE_MCU_TYPE_USB, 1544 URE_RG_PWRDN_EN | URE_ALL_SPEED_OFF); 1545 1546 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, 1547 0x00600400); 1548 } else { 1549 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 1550 URE_TCR0_AUTO_FIFO); 1551 ure_reset(sc); 1552 1553 /* Configure Rx FIFO threshold. */ 1554 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 1555 URE_RXFIFO_THR1_NORMAL); 1556 ure_write_2(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, 1557 URE_RXFIFO_THR2_NORMAL); 1558 ure_write_2(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, 1559 URE_RXFIFO_THR3_NORMAL); 1560 1561 /* Configure Tx FIFO threshold. */ 1562 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 1563 URE_TXFIFO_THR_NORMAL2); 1564 1565 if (sc->ure_flags & URE_FLAG_8153B) { 1566 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, 1567 URE_RX_THR_B); 1568 1569 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, 1570 URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN); 1571 } else { 1572 URE_SETBIT_1(sc, URE_PLA_CONFIG6, URE_MCU_TYPE_PLA, 1573 URE_LANWAKE_CLR_EN); 1574 URE_CLRBIT_1(sc, URE_PLA_LWAKE_CTRL_REG, 1575 URE_MCU_TYPE_PLA, URE_LANWAKE_PIN); 1576 URE_CLRBIT_2(sc, URE_USB_SSPHYLINK1, URE_MCU_TYPE_USB, 1577 URE_DELAY_PHY_PWR_CHG); 1578 } 1579 } 1580 1581 /* Enable ALDPS. */ 1582 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1583 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | URE_EN_ALDPS); 1584 1585 if ((sc->ure_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) || 1586 (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B))) 1587 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 1588 URE_U2P3_ENABLE); 1589 1590 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) { 1591 if (sc->ure_udev->speed == USB_SPEED_SUPER) 1592 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, 1593 LPM_U1U2_EN); 1594 } else { 1595 memset(u1u2, 0xff, sizeof(u1u2)); 1596 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, 1597 u1u2, sizeof(u1u2)); 1598 } 1599 } 1600 1601 uint16_t 1602 ure_rtl8153_phy_status(struct ure_softc *sc, int desired) 1603 { 1604 uint16_t reg; 1605 int i; 1606 1607 for (i = 0; i < 500; i++) { 1608 reg = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & 1609 URE_PHY_STAT_MASK; 1610 if (desired) { 1611 if (reg == desired) 1612 break; 1613 } else { 1614 if (reg == URE_PHY_STAT_LAN_ON || 1615 reg == URE_PHY_STAT_PWRDN || 1616 reg == URE_PHY_STAT_EXT_INIT) 1617 break; 1618 } 1619 usbd_delay_ms(sc->ure_udev, 20); 1620 } 1621 if (i == 500) 1622 printf("%s: timeout waiting for phy to stabilize\n", 1623 sc->ure_dev.dv_xname); 1624 1625 return reg; 1626 } 1627 1628 void 1629 ure_wait_for_flash(struct ure_softc *sc) 1630 { 1631 int i; 1632 1633 if ((ure_read_2(sc, URE_PLA_GPHY_CTRL, URE_MCU_TYPE_PLA) & 1634 URE_GPHY_FLASH) && 1635 !(ure_read_2(sc, URE_USB_GPHY_CTRL, URE_MCU_TYPE_USB) & 1636 URE_BYPASS_FLASH)) { 1637 for (i = 0; i < 100; i++) { 1638 if (ure_read_2(sc, URE_USB_GPHY_CTRL, 1639 URE_MCU_TYPE_USB) & URE_GPHY_PATCH_DONE) 1640 break; 1641 DELAY(1000); 1642 } 1643 if (i == 100) 1644 printf("%s: timeout waiting for loading flash\n", 1645 sc->ure_dev.dv_xname); 1646 } 1647 } 1648 1649 void 1650 ure_reset_bmu(struct ure_softc *sc) 1651 { 1652 uint8_t reg; 1653 1654 reg = ure_read_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB); 1655 reg &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); 1656 ure_write_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, reg); 1657 reg |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; 1658 ure_write_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, reg); 1659 } 1660 1661 void 1662 ure_disable_teredo(struct ure_softc *sc) 1663 { 1664 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) 1665 ure_write_1(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 0xff); 1666 else { 1667 URE_CLRBIT_2(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 1668 URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | 1669 URE_OOB_TEREDO_EN); 1670 } 1671 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, URE_WDT6_SET_MODE); 1672 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 1673 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 1674 } 1675 1676 int 1677 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1678 { 1679 struct ure_softc *sc = ifp->if_softc; 1680 struct ifreq *ifr = (struct ifreq *)data; 1681 int s, error = 0; 1682 1683 s = splnet(); 1684 1685 switch (cmd) { 1686 case SIOCSIFADDR: 1687 ifp->if_flags |= IFF_UP; 1688 if (!(ifp->if_flags & IFF_RUNNING)) 1689 ure_init(sc); 1690 break; 1691 1692 case SIOCSIFFLAGS: 1693 if (ifp->if_flags & IFF_UP) { 1694 if (ifp->if_flags & IFF_RUNNING) 1695 error = ENETRESET; 1696 else 1697 ure_init(sc); 1698 } else { 1699 if (ifp->if_flags & IFF_RUNNING) 1700 ure_stop(sc); 1701 } 1702 break; 1703 1704 case SIOCGIFMEDIA: 1705 case SIOCSIFMEDIA: 1706 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) 1707 error = ifmedia_ioctl(ifp, ifr, &sc->ure_ifmedia, cmd); 1708 else 1709 error = ifmedia_ioctl(ifp, ifr, &sc->ure_mii.mii_media, 1710 cmd); 1711 break; 1712 1713 default: 1714 error = ether_ioctl(ifp, &sc->ure_ac, cmd, data); 1715 } 1716 1717 if (error == ENETRESET) { 1718 if (ifp->if_flags & IFF_RUNNING) 1719 ure_iff(sc); 1720 error = 0; 1721 } 1722 1723 splx(s); 1724 1725 return (error); 1726 } 1727 1728 int 1729 ure_match(struct device *parent, void *match, void *aux) 1730 { 1731 struct usb_attach_arg *uaa = aux; 1732 1733 if (uaa->iface == NULL || uaa->configno != 1) 1734 return (UMATCH_NONE); 1735 1736 return (usb_lookup(ure_devs, uaa->vendor, uaa->product) != NULL ? 1737 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 1738 } 1739 1740 void 1741 ure_attach(struct device *parent, struct device *self, void *aux) 1742 { 1743 struct ure_softc *sc = (struct ure_softc *)self; 1744 struct usb_attach_arg *uaa = aux; 1745 usb_interface_descriptor_t *id; 1746 usb_endpoint_descriptor_t *ed; 1747 u_char eaddr[8]; /* 4byte padded */ 1748 struct ifnet *ifp; 1749 int i, mii_flags = 0, s; 1750 uint16_t ver; 1751 1752 sc->ure_udev = uaa->device; 1753 sc->ure_iface = uaa->iface; 1754 1755 usb_init_task(&sc->ure_tick_task, ure_tick_task, sc, 1756 USB_TASK_TYPE_GENERIC); 1757 1758 id = usbd_get_interface_descriptor(sc->ure_iface); 1759 1760 for (i = 0; i < id->bNumEndpoints; i++) { 1761 ed = usbd_interface2endpoint_descriptor(sc->ure_iface, i); 1762 if (!ed) { 1763 printf("%s: couldn't get ep %d\n", 1764 sc->ure_dev.dv_xname, i); 1765 return; 1766 } 1767 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 1768 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 1769 sc->ure_ed[URE_ENDPT_RX] = ed->bEndpointAddress; 1770 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 1771 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 1772 sc->ure_ed[URE_ENDPT_TX] = ed->bEndpointAddress; 1773 } 1774 } 1775 1776 sc->ure_txbufsz = URE_TX_BUFSZ; 1777 sc->ure_rxbufsz = URE_8153_RX_BUFSZ; 1778 1779 s = splnet(); 1780 1781 sc->ure_phyno = 0; 1782 printf("%s: ", sc->ure_dev.dv_xname); 1783 1784 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 1785 switch (ver) { 1786 case 0x4c00: 1787 sc->ure_flags = URE_FLAG_8152; 1788 sc->ure_rxbufsz = URE_8152_RX_BUFSZ; 1789 sc->ure_chip |= URE_CHIP_VER_4C00; 1790 printf("RTL8152 (0x4c00)"); 1791 break; 1792 case 0x4c10: 1793 sc->ure_flags = URE_FLAG_8152; 1794 sc->ure_rxbufsz = URE_8152_RX_BUFSZ; 1795 sc->ure_chip |= URE_CHIP_VER_4C10; 1796 printf("RTL8152 (0x4c10)"); 1797 break; 1798 case 0x5c00: 1799 sc->ure_chip |= URE_CHIP_VER_5C00; 1800 printf("RTL8153 (0x5c00)"); 1801 break; 1802 case 0x5c10: 1803 sc->ure_chip |= URE_CHIP_VER_5C10; 1804 printf("RTL8153 (0x5c10)"); 1805 break; 1806 case 0x5c20: 1807 sc->ure_chip |= URE_CHIP_VER_5C20; 1808 printf("RTL8153 (0x5c20)"); 1809 break; 1810 case 0x5c30: 1811 sc->ure_chip |= URE_CHIP_VER_5C30; 1812 printf("RTL8153 (0x5c30)"); 1813 break; 1814 case 0x6000: 1815 sc->ure_flags = URE_FLAG_8153B; 1816 printf("RTL8153B (0x6000)"); 1817 break; 1818 case 0x6010: 1819 sc->ure_flags = URE_FLAG_8153B; 1820 printf("RTL8153B (0x6010)"); 1821 break; 1822 case 0x7020: 1823 sc->ure_flags = URE_FLAG_8156; 1824 printf("RTL8156 (0x7020)"); 1825 break; 1826 case 0x7030: 1827 sc->ure_flags = URE_FLAG_8156; 1828 printf("RTL8156 (0x7030)"); 1829 break; 1830 case 0x7410: 1831 sc->ure_flags = URE_FLAG_8156B; 1832 printf("RTL8156B (0x7410)"); 1833 break; 1834 case 0x7420: 1835 sc->ure_flags = URE_FLAG_8156B; 1836 sc->ure_chip = URE_CHIP_VER_7420; 1837 printf("RTL8153D (0x7420)"); 1838 break; 1839 default: 1840 printf(", unknown ver %02x", ver); 1841 break; 1842 } 1843 1844 if (sc->ure_flags & URE_FLAG_8152) 1845 ure_rtl8152_init(sc); 1846 else if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | 1847 URE_FLAG_8156B)) 1848 ure_rtl8153b_init(sc); 1849 else 1850 ure_rtl8153_init(sc); 1851 1852 if (sc->ure_chip & URE_CHIP_VER_4C00) 1853 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr, 1854 sizeof(eaddr)); 1855 else 1856 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr, 1857 sizeof(eaddr)); 1858 1859 printf(", address %s\n", ether_sprintf(eaddr)); 1860 1861 bcopy(eaddr, (char *)&sc->ure_ac.ac_enaddr, ETHER_ADDR_LEN); 1862 1863 ifp = &sc->ure_ac.ac_if; 1864 ifp->if_softc = sc; 1865 strlcpy(ifp->if_xname, sc->ure_dev.dv_xname, IFNAMSIZ); 1866 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1867 ifp->if_ioctl = ure_ioctl; 1868 ifp->if_start = ure_start; 1869 ifp->if_watchdog = ure_watchdog; 1870 1871 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 | 1872 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1873 1874 #if NVLAN > 0 1875 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1876 #endif 1877 1878 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1879 ifmedia_init(&sc->ure_ifmedia, IFM_IMASK, ure_ifmedia_upd, 1880 ure_ifmedia_sts); 1881 ure_add_media_types(sc); 1882 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1883 ifmedia_set(&sc->ure_ifmedia, IFM_ETHER | IFM_AUTO); 1884 sc->ure_ifmedia.ifm_media = sc->ure_ifmedia.ifm_cur->ifm_media; 1885 } else { 1886 rw_init(&sc->ure_mii_lock, "uremii"); 1887 1888 sc->ure_mii.mii_ifp = ifp; 1889 sc->ure_mii.mii_readreg = ure_miibus_readreg; 1890 sc->ure_mii.mii_writereg = ure_miibus_writereg; 1891 sc->ure_mii.mii_statchg = ure_miibus_statchg; 1892 sc->ure_mii.mii_flags = MIIF_AUTOTSLEEP; 1893 1894 ifmedia_init(&sc->ure_mii.mii_media, 0, ure_ifmedia_upd, 1895 ure_ifmedia_sts); 1896 if (!(sc->ure_flags & URE_FLAG_8152)) 1897 mii_flags |= MIIF_DOPAUSE; 1898 mii_attach(self, &sc->ure_mii, 0xffffffff, sc->ure_phyno, 1899 MII_OFFSET_ANY, mii_flags); 1900 if (LIST_FIRST(&sc->ure_mii.mii_phys) == NULL) { 1901 ifmedia_add(&sc->ure_mii.mii_media, 1902 IFM_ETHER | IFM_NONE, 0, NULL); 1903 ifmedia_set(&sc->ure_mii.mii_media, 1904 IFM_ETHER | IFM_NONE); 1905 } else 1906 ifmedia_set(&sc->ure_mii.mii_media, 1907 IFM_ETHER | IFM_AUTO); 1908 } 1909 1910 if_attach(ifp); 1911 ether_ifattach(ifp); 1912 1913 timeout_set(&sc->ure_stat_ch, ure_tick, sc); 1914 1915 splx(s); 1916 } 1917 1918 int 1919 ure_detach(struct device *self, int flags) 1920 { 1921 struct ure_softc *sc = (struct ure_softc *)self; 1922 struct ifnet *ifp = &sc->ure_ac.ac_if; 1923 int s; 1924 1925 if (timeout_initialized(&sc->ure_stat_ch)) 1926 timeout_del(&sc->ure_stat_ch); 1927 1928 if (sc->ure_ep[URE_ENDPT_TX] != NULL) 1929 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_TX]); 1930 if (sc->ure_ep[URE_ENDPT_RX] != NULL) 1931 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_RX]); 1932 1933 usb_rem_task(sc->ure_udev, &sc->ure_tick_task); 1934 1935 s = splusb(); 1936 1937 if (--sc->ure_refcnt >= 0) { 1938 usb_detach_wait(&sc->ure_dev); 1939 } 1940 1941 if (ifp->if_flags & IFF_RUNNING) 1942 ure_stop(sc); 1943 1944 mii_detach(&sc->ure_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1945 ifmedia_delete_instance(&sc->ure_mii.mii_media, IFM_INST_ANY); 1946 if (ifp->if_softc != NULL) { 1947 ether_ifdetach(ifp); 1948 if_detach(ifp); 1949 } 1950 1951 splx(s); 1952 1953 return 0; 1954 } 1955 1956 void 1957 ure_tick_task(void *xsc) 1958 { 1959 struct ure_softc *sc = xsc; 1960 struct mii_data *mii; 1961 int s; 1962 1963 if (sc == NULL) 1964 return; 1965 1966 if (usbd_is_dying(sc->ure_udev)) 1967 return; 1968 mii = &sc->ure_mii; 1969 1970 s = splnet(); 1971 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) 1972 ure_link_state(sc); 1973 else { 1974 mii_tick(mii); 1975 if ((sc->ure_flags & URE_FLAG_LINK) == 0) 1976 ure_miibus_statchg(&sc->ure_dev); 1977 } 1978 timeout_add_sec(&sc->ure_stat_ch, 1); 1979 splx(s); 1980 } 1981 1982 void 1983 ure_lock_mii(struct ure_softc *sc) 1984 { 1985 sc->ure_refcnt++; 1986 rw_enter_write(&sc->ure_mii_lock); 1987 } 1988 1989 void 1990 ure_unlock_mii(struct ure_softc *sc) 1991 { 1992 rw_exit_write(&sc->ure_mii_lock); 1993 if (--sc->ure_refcnt < 0) 1994 usb_detach_wakeup(&sc->ure_dev); 1995 } 1996 1997 void 1998 ure_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1999 { 2000 struct ure_chain *c = (struct ure_chain *)priv; 2001 struct ure_softc *sc = c->uc_sc; 2002 struct ifnet *ifp = &sc->ure_ac.ac_if; 2003 u_char *buf = c->uc_buf; 2004 uint32_t cflags, rxvlan, total_len; 2005 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 2006 struct mbuf *m; 2007 int pktlen = 0, s; 2008 struct ure_rxpkt rxhdr; 2009 2010 if (usbd_is_dying(sc->ure_udev)) 2011 return; 2012 2013 if (!(ifp->if_flags & IFF_RUNNING)) 2014 return; 2015 2016 if (status != USBD_NORMAL_COMPLETION) { 2017 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2018 return; 2019 if (usbd_ratecheck(&sc->ure_rx_notice)) { 2020 printf("%s: usb errors on rx: %s\n", 2021 sc->ure_dev.dv_xname, usbd_errstr(status)); 2022 } 2023 if (status == USBD_STALLED) 2024 usbd_clear_endpoint_stall_async( 2025 sc->ure_ep[URE_ENDPT_RX]); 2026 goto done; 2027 } 2028 2029 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL); 2030 DPRINTFN(3, ("received %d bytes\n", total_len)); 2031 2032 do { 2033 if (total_len < sizeof(rxhdr)) { 2034 DPRINTF(("too few bytes left for a packet header\n")); 2035 ifp->if_ierrors++; 2036 goto done; 2037 } 2038 2039 buf += roundup(pktlen, URE_RX_BUF_ALIGN); 2040 2041 memcpy(&rxhdr, buf, sizeof(rxhdr)); 2042 total_len -= sizeof(rxhdr); 2043 2044 pktlen = letoh32(rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK; 2045 DPRINTFN(4, ("next packet is %d bytes\n", pktlen)); 2046 if (pktlen > total_len) { 2047 DPRINTF(("not enough bytes left for next packet\n")); 2048 ifp->if_ierrors++; 2049 goto done; 2050 } 2051 2052 total_len -= roundup(pktlen, URE_RX_BUF_ALIGN); 2053 buf += sizeof(rxhdr); 2054 2055 m = m_devget(buf, pktlen - ETHER_CRC_LEN, ETHER_ALIGN); 2056 if (m == NULL) { 2057 DPRINTF(("unable to allocate mbuf for next packet\n")); 2058 ifp->if_ierrors++; 2059 goto done; 2060 } 2061 2062 cflags = letoh32(rxhdr.ure_csum); 2063 rxvlan = letoh32(rxhdr.ure_vlan); 2064 2065 /* Check IP header checksum. */ 2066 if ((rxvlan & URE_RXPKT_IPV4) && 2067 !(cflags & URE_RXPKT_IPSUMBAD)) 2068 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 2069 2070 /* Check TCP/UDP checksum. */ 2071 if ((rxvlan & (URE_RXPKT_IPV4 | URE_RXPKT_IPV6)) && 2072 (((rxvlan & URE_RXPKT_TCP) && 2073 !(cflags & URE_RXPKT_TCPSUMBAD)) || 2074 ((rxvlan & URE_RXPKT_UDP) && 2075 !(cflags & URE_RXPKT_UDPSUMBAD)))) 2076 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | 2077 M_UDP_CSUM_IN_OK; 2078 #if NVLAN > 0 2079 if (rxvlan & URE_RXPKT_VLAN_TAG) { 2080 m->m_pkthdr.ether_vtag = 2081 swap16(rxvlan & URE_RXPKT_VLAN_DATA); 2082 m->m_flags |= M_VLANTAG; 2083 } 2084 #endif 2085 2086 ml_enqueue(&ml, m); 2087 } while (total_len > 0); 2088 2089 done: 2090 s = splnet(); 2091 if_input(ifp, &ml); 2092 splx(s); 2093 memset(c->uc_buf, 0, sc->ure_rxbufsz); 2094 2095 usbd_setup_xfer(xfer, sc->ure_ep[URE_ENDPT_RX], c, c->uc_buf, 2096 sc->ure_rxbufsz, USBD_SHORT_XFER_OK | USBD_NO_COPY, 2097 USBD_NO_TIMEOUT, ure_rxeof); 2098 usbd_transfer(xfer); 2099 } 2100 2101 2102 void 2103 ure_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2104 { 2105 struct ure_softc *sc; 2106 struct ure_chain *c; 2107 struct ifnet *ifp; 2108 int s; 2109 2110 c = priv; 2111 sc = c->uc_sc; 2112 ifp = &sc->ure_ac.ac_if; 2113 2114 if (usbd_is_dying(sc->ure_udev)) 2115 return; 2116 2117 if (status != USBD_NORMAL_COMPLETION) 2118 DPRINTF(("%s: %s uc_idx=%u : %s\n", sc->ure_dev.dv_xname, 2119 __func__, c->uc_idx, usbd_errstr(status))); 2120 2121 s = splnet(); 2122 2123 c->uc_cnt = 0; 2124 c->uc_buflen = 0; 2125 2126 SLIST_INSERT_HEAD(&sc->ure_cdata.ure_tx_free, c, uc_list); 2127 2128 if (status != USBD_NORMAL_COMPLETION) { 2129 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) { 2130 splx(s); 2131 return; 2132 } 2133 2134 ifp->if_oerrors++; 2135 printf("%s: usb error on tx: %s\n", sc->ure_dev.dv_xname, 2136 usbd_errstr(status)); 2137 2138 if (status == USBD_STALLED) 2139 usbd_clear_endpoint_stall_async( 2140 sc->ure_ep[URE_ENDPT_TX]); 2141 splx(s); 2142 return; 2143 } 2144 2145 ifp->if_timer = 0; 2146 if (ifq_is_oactive(&ifp->if_snd)) 2147 ifq_restart(&ifp->if_snd); 2148 splx(s); 2149 } 2150 2151 int 2152 ure_encap_txpkt(struct mbuf *m, char *buf, uint32_t maxlen) 2153 { 2154 struct ure_txpkt txhdr; 2155 uint32_t len = sizeof(txhdr), cflags = 0; 2156 2157 if (len + m->m_pkthdr.len > maxlen) 2158 return (-1); 2159 2160 if ((m->m_pkthdr.csum_flags & 2161 (M_IPV4_CSUM_OUT | M_TCP_CSUM_OUT | M_UDP_CSUM_OUT)) != 0) { 2162 cflags |= URE_TXPKT_IPV4; 2163 if (m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) 2164 cflags |= URE_TXPKT_TCP; 2165 if (m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) 2166 cflags |= URE_TXPKT_UDP; 2167 } 2168 2169 #if NVLAN > 0 2170 if (m->m_flags & M_VLANTAG) 2171 cflags |= URE_TXPKT_VLAN_TAG | swap16(m->m_pkthdr.ether_vtag); 2172 #endif 2173 2174 txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS | 2175 URE_TXPKT_TX_LS); 2176 txhdr.ure_vlan = htole32(cflags); 2177 memcpy(buf, &txhdr, len); 2178 2179 m_copydata(m, 0, m->m_pkthdr.len, buf + len); 2180 len += m->m_pkthdr.len; 2181 2182 return (len); 2183 } 2184 2185 int 2186 ure_encap_xfer(struct ifnet *ifp, struct ure_softc *sc, struct ure_chain *c) 2187 { 2188 usbd_status err; 2189 2190 usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_TX], c, c->uc_buf, 2191 c->uc_buflen, USBD_FORCE_SHORT_XFER | USBD_NO_COPY, 10000, 2192 ure_txeof); 2193 2194 err = usbd_transfer(c->uc_xfer); 2195 if (err != USBD_IN_PROGRESS) { 2196 c->uc_cnt = 0; 2197 c->uc_buflen = 0; 2198 ure_stop(sc); 2199 return (EIO); 2200 } 2201 2202 return (0); 2203 } 2204