1 /* $OpenBSD: if_ure.c,v 1.33 2023/09/09 14:23:37 kevlo Exp $ */ 2 /*- 3 * Copyright (c) 2015, 2016, 2019 Kevin Lo <kevlo@openbsd.org> 4 * Copyright (c) 2020 Jonathon Fletcher <jonathon.fletcher@gmail.com> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "bpfilter.h" 30 #include "vlan.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/sockio.h> 35 #include <sys/rwlock.h> 36 #include <sys/mbuf.h> 37 #include <sys/kernel.h> 38 #include <sys/socket.h> 39 #include <sys/device.h> 40 41 #include <machine/bus.h> 42 43 #include <net/if.h> 44 #include <net/if_media.h> 45 46 #if NBPFILTER > 0 47 #include <net/bpf.h> 48 #endif 49 50 #include <netinet/in.h> 51 #include <netinet/if_ether.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 56 #include <dev/usb/usb.h> 57 #include <dev/usb/usbdi.h> 58 #include <dev/usb/usbdi_util.h> 59 #include <dev/usb/usbdivar.h> 60 #include <dev/usb/usbdevs.h> 61 62 #include <dev/ic/rtl81x9reg.h> 63 #include <dev/usb/if_urereg.h> 64 65 #ifdef URE_DEBUG 66 #define DPRINTF(x) do { if (uredebug) printf x; } while (0) 67 #define DPRINTFN(n,x) do { if (uredebug >= (n)) printf x; } while (0) 68 int uredebug = 0; 69 #else 70 #define DPRINTF(x) 71 #define DPRINTFN(n,x) 72 #endif 73 74 const struct usb_devno ure_devs[] = { 75 { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_RTL8156 }, 76 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8152B }, 77 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8153 }, 78 { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB3GIGV1 }, 79 { USB_VENDOR_CLEVO, USB_PRODUCT_CLEVO_RTL8153B }, 80 { USB_VENDOR_CLUB3D, USB_PRODUCT_CLUB3D_RTL8153 }, 81 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8153_1 }, 82 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8153_2 }, 83 { USB_VENDOR_DYNABOOK, USB_PRODUCT_DYNABOOK_RTL8153B_1 }, 84 { USB_VENDOR_DYNABOOK, USB_PRODUCT_DYNABOOK_RTL8153B_2 }, 85 { USB_VENDOR_ELECOM, USB_PRODUCT_ELECOM_RTL8153B }, 86 { USB_VENDOR_ELECOM, USB_PRODUCT_ELECOM_RTL8156B }, 87 { USB_VENDOR_IOI, USB_PRODUCT_IOI_RTL8153 }, 88 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_DOCK_ETHERNET }, 89 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ONELINK }, 90 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ONELINKPLUS }, 91 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ONELINKPRO }, 92 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_1 }, 93 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_2 }, 94 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_3 }, 95 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_4 }, 96 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_5 }, 97 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_6 }, 98 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_7 }, 99 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_8 }, 100 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_9 }, 101 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153_1 }, 102 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153_2 }, 103 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153_3 }, 104 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TABLETDOCK }, 105 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TB3DOCK }, 106 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TB3DOCKGEN2 }, 107 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TB3GFXDOCK }, 108 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_USBCDOCKGEN2 }, 109 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_WIGIGDOCK }, 110 { USB_VENDOR_LG, USB_PRODUCT_LG_RTL8153 }, 111 { USB_VENDOR_LG, USB_PRODUCT_LG_RTL8153B }, 112 { USB_VENDOR_LUXSHARE, USB_PRODUCT_LUXSHARE_RTL8153 }, 113 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_DOCKETH }, 114 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_DOCKETH2 }, 115 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_SURFETH }, 116 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_WINDEVETH }, 117 { USB_VENDOR_NVIDIA, USB_PRODUCT_NVIDIA_TEGRAETH }, 118 { USB_VENDOR_PIONEERDJ, USB_PRODUCT_PIONEERDJ_RTL8152B }, 119 { USB_VENDOR_PIONEERDJ, USB_PRODUCT_PIONEERDJ_RTL8153B }, 120 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 }, 121 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152B }, 122 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8153 }, 123 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8156 }, 124 { USB_VENDOR_SAMSUNG2, USB_PRODUCT_SAMSUNG2_RTL8153 }, 125 { USB_VENDOR_TOSHIBA, USB_PRODUCT_TOSHIBA_RTL8153B }, 126 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_EU300 }, 127 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_RTL8152B_1 }, 128 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_RTL8152B_2 }, 129 { USB_VENDOR_TRENDNET, USB_PRODUCT_TRENDNET_RTL8156 }, 130 { USB_VENDOR_TTL, USB_PRODUCT_TTL_RTL8153 }, 131 { USB_VENDOR_TWINHEAD, USB_PRODUCT_TWINHEAD_RTL8153B }, 132 { USB_VENDOR_XIAOMI, USB_PRODUCT_XIAOMI_RTL8152B }, 133 }; 134 135 int ure_match(struct device *, void *, void *); 136 void ure_attach(struct device *, struct device *, void *); 137 int ure_detach(struct device *, int); 138 139 struct cfdriver ure_cd = { 140 NULL, "ure", DV_IFNET 141 }; 142 143 const struct cfattach ure_ca = { 144 sizeof(struct ure_softc), ure_match, ure_attach, ure_detach 145 }; 146 147 int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t, 148 void *, int); 149 int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *, 150 int); 151 int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *, 152 int); 153 uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t); 154 uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t); 155 uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t); 156 int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t); 157 int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t); 158 int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t); 159 uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t); 160 void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t); 161 162 void ure_init(void *); 163 void ure_stop(struct ure_softc *); 164 void ure_start(struct ifnet *); 165 void ure_reset(struct ure_softc *); 166 void ure_watchdog(struct ifnet *); 167 168 void ure_miibus_statchg(struct device *); 169 int ure_miibus_readreg(struct device *, int, int); 170 void ure_miibus_writereg(struct device *, int, int, int); 171 void ure_lock_mii(struct ure_softc *); 172 void ure_unlock_mii(struct ure_softc *); 173 174 int ure_encap_txpkt(struct mbuf *, char *, uint32_t); 175 int ure_encap_xfer(struct ifnet *, struct ure_softc *, 176 struct ure_chain *); 177 void ure_rxeof(struct usbd_xfer *, void *, usbd_status); 178 void ure_txeof(struct usbd_xfer *, void *, usbd_status); 179 int ure_xfer_list_init(struct ure_softc *, struct ure_chain *, 180 uint32_t, int); 181 void ure_xfer_list_free(struct ure_softc *, struct ure_chain *, int); 182 183 void ure_tick_task(void *); 184 void ure_tick(void *); 185 186 void ure_ifmedia_init(struct ifnet *); 187 int ure_ifmedia_upd(struct ifnet *); 188 void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *); 189 void ure_add_media_types(struct ure_softc *); 190 void ure_link_state(struct ure_softc *); 191 int ure_get_link_status(struct ure_softc *); 192 void ure_iff(struct ure_softc *); 193 void ure_rxvlan(struct ure_softc *); 194 int ure_ioctl(struct ifnet *, u_long, caddr_t); 195 void ure_rtl8152_init(struct ure_softc *); 196 void ure_rtl8153_init(struct ure_softc *); 197 void ure_rtl8153b_init(struct ure_softc *); 198 void ure_rtl8152_nic_reset(struct ure_softc *); 199 void ure_rtl8153_nic_reset(struct ure_softc *); 200 uint16_t ure_rtl8153_phy_status(struct ure_softc *, int); 201 void ure_wait_for_flash(struct ure_softc *); 202 void ure_reset_bmu(struct ure_softc *); 203 void ure_disable_teredo(struct ure_softc *); 204 205 #define URE_SETBIT_1(sc, reg, index, x) \ 206 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x)) 207 #define URE_SETBIT_2(sc, reg, index, x) \ 208 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x)) 209 #define URE_SETBIT_4(sc, reg, index, x) \ 210 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x)) 211 212 #define URE_CLRBIT_1(sc, reg, index, x) \ 213 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~(x)) 214 #define URE_CLRBIT_2(sc, reg, index, x) \ 215 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~(x)) 216 #define URE_CLRBIT_4(sc, reg, index, x) \ 217 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~(x)) 218 219 int 220 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index, 221 void *buf, int len) 222 { 223 usb_device_request_t req; 224 usbd_status err; 225 226 if (usbd_is_dying(sc->ure_udev)) 227 return 0; 228 229 if (rw == URE_CTL_WRITE) 230 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 231 else 232 req.bmRequestType = UT_READ_VENDOR_DEVICE; 233 req.bRequest = UR_SET_ADDRESS; 234 USETW(req.wValue, val); 235 USETW(req.wIndex, index); 236 USETW(req.wLength, len); 237 238 DPRINTFN(5, ("ure_ctl: rw %d, val 0x%04hu, index 0x%04hu, len %d\n", 239 rw, val, index, len)); 240 err = usbd_do_request(sc->ure_udev, &req, buf); 241 if (err) { 242 DPRINTF(("ure_ctl: error %d\n", err)); 243 return -1; 244 } 245 246 return 0; 247 } 248 249 int 250 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 251 void *buf, int len) 252 { 253 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len)); 254 } 255 256 int 257 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 258 void *buf, int len) 259 { 260 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len)); 261 } 262 263 uint8_t 264 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index) 265 { 266 uint32_t val; 267 uint8_t temp[4]; 268 uint8_t shift; 269 270 shift = (reg & 3) << 3; 271 reg &= ~3; 272 273 ure_read_mem(sc, reg, index, &temp, 4); 274 val = UGETDW(temp); 275 val >>= shift; 276 277 return (val & 0xff); 278 } 279 280 uint16_t 281 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index) 282 { 283 uint32_t val; 284 uint8_t temp[4]; 285 uint8_t shift; 286 287 shift = (reg & 2) << 3; 288 reg &= ~3; 289 290 ure_read_mem(sc, reg, index, &temp, 4); 291 val = UGETDW(temp); 292 val >>= shift; 293 294 return (val & 0xffff); 295 } 296 297 uint32_t 298 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index) 299 { 300 uint8_t temp[4]; 301 302 ure_read_mem(sc, reg, index, &temp, 4); 303 return (UGETDW(temp)); 304 } 305 306 int 307 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 308 { 309 uint16_t byen; 310 uint8_t temp[4]; 311 uint8_t shift; 312 313 byen = URE_BYTE_EN_BYTE; 314 shift = reg & 3; 315 val &= 0xff; 316 317 if (reg & 3) { 318 byen <<= shift; 319 val <<= (shift << 3); 320 reg &= ~3; 321 } 322 323 USETDW(temp, val); 324 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 325 } 326 327 int 328 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 329 { 330 uint16_t byen; 331 uint8_t temp[4]; 332 uint8_t shift; 333 334 byen = URE_BYTE_EN_WORD; 335 shift = reg & 2; 336 val &= 0xffff; 337 338 if (reg & 2) { 339 byen <<= shift; 340 val <<= (shift << 3); 341 reg &= ~3; 342 } 343 344 USETDW(temp, val); 345 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 346 } 347 348 int 349 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 350 { 351 uint8_t temp[4]; 352 353 USETDW(temp, val); 354 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4)); 355 } 356 357 uint16_t 358 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr) 359 { 360 uint16_t reg; 361 362 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 363 reg = (addr & 0x0fff) | 0xb000; 364 365 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA)); 366 } 367 368 void 369 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 370 { 371 uint16_t reg; 372 373 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 374 reg = (addr & 0x0fff) | 0xb000; 375 376 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data); 377 } 378 379 int 380 ure_miibus_readreg(struct device *dev, int phy, int reg) 381 { 382 struct ure_softc *sc = (void *)dev; 383 uint16_t val; 384 385 if (usbd_is_dying(sc->ure_udev)) 386 return 0; 387 388 /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */ 389 if (reg == RL_GMEDIASTAT) 390 return ure_read_1(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA); 391 392 ure_lock_mii(sc); 393 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2); 394 ure_unlock_mii(sc); 395 396 return val; /* letoh16? */ 397 } 398 399 void 400 ure_miibus_writereg(struct device *dev, int phy, int reg, int val) 401 { 402 struct ure_softc *sc = (void *)dev; 403 404 ure_lock_mii(sc); 405 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val); /* htole16? */ 406 ure_unlock_mii(sc); 407 } 408 409 void 410 ure_miibus_statchg(struct device *dev) 411 { 412 struct ure_softc *sc = (void *)dev; 413 struct mii_data *mii = &sc->ure_mii; 414 struct ifnet *ifp = &sc->ure_ac.ac_if; 415 416 if ((ifp->if_flags & IFF_RUNNING) == 0) 417 return; 418 419 sc->ure_flags &= ~URE_FLAG_LINK; 420 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 421 (IFM_ACTIVE | IFM_AVALID)) { 422 switch (IFM_SUBTYPE(mii->mii_media_active)) { 423 case IFM_10_T: 424 case IFM_100_TX: 425 sc->ure_flags |= URE_FLAG_LINK; 426 break; 427 case IFM_1000_T: 428 if ((sc->ure_flags & URE_FLAG_8152) != 0) 429 break; 430 sc->ure_flags |= URE_FLAG_LINK; 431 break; 432 default: 433 break; 434 } 435 } 436 437 /* Lost link, do nothing. */ 438 if ((sc->ure_flags & URE_FLAG_LINK) == 0) 439 return; 440 441 /* 442 * After a link change the media settings are getting reset on the 443 * hardware, and need to be re-initialized again for communication 444 * to continue work. 445 */ 446 ure_ifmedia_init(ifp); 447 } 448 449 void 450 ure_ifmedia_init(struct ifnet *ifp) 451 { 452 struct ure_softc *sc = ifp->if_softc; 453 uint32_t reg = 0; 454 455 /* Set MAC address. */ 456 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 457 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 458 sc->ure_ac.ac_enaddr, 8); 459 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 460 461 if (!(sc->ure_flags & URE_FLAG_8152)) { 462 if (sc->ure_flags & URE_FLAG_8156B) 463 URE_CLRBIT_2(sc, URE_USB_RX_AGGR_NUM, URE_MCU_TYPE_USB, 464 URE_RX_AGGR_NUM_MASK); 465 466 reg = sc->ure_rxbufsz - URE_FRAMELEN(ifp->if_mtu) - 467 sizeof(struct ure_rxpkt) - URE_RX_BUF_ALIGN; 468 if (sc->ure_flags & 469 (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) { 470 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, 471 reg / 8); 472 473 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 474 (sc->ure_flags & URE_FLAG_8153B) ? 158 : 80); 475 ure_write_2(sc, URE_USB_PM_CTRL_STATUS, 476 URE_MCU_TYPE_USB, 1875); 477 } else { 478 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, 479 reg / 4); 480 switch (sc->ure_udev->speed) { 481 case USB_SPEED_SUPER: 482 reg = URE_COALESCE_SUPER / 8; 483 break; 484 case USB_SPEED_HIGH: 485 reg = URE_COALESCE_HIGH / 8; 486 break; 487 default: 488 reg = URE_COALESCE_SLOW / 8; 489 break; 490 } 491 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 492 reg); 493 } 494 495 if (sc->ure_chip & URE_CHIP_VER_7420) { 496 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL4, 497 URE_MCU_TYPE_PLA, URE_IDLE_SPDWN_EN); 498 } 499 500 if ((sc->ure_chip & URE_CHIP_VER_6010) || 501 (sc->ure_flags & URE_FLAG_8156B)) { 502 URE_CLRBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, 503 URE_FC_PATCH_TASK); 504 usbd_delay_ms(sc->ure_udev, 1); 505 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, 506 URE_FC_PATCH_TASK); 507 } 508 } 509 510 /* Reset the packet filter. */ 511 URE_CLRBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN); 512 URE_SETBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN); 513 514 /* Enable transmit and receive. */ 515 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE); 516 517 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) { 518 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB, 519 URE_OWN_UPDATE | URE_OWN_CLEAR); 520 } 521 522 URE_CLRBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 523 } 524 525 int 526 ure_ifmedia_upd(struct ifnet *ifp) 527 { 528 struct ure_softc *sc = ifp->if_softc; 529 struct mii_data *mii = &sc->ure_mii; 530 struct ifmedia *ifm = &sc->ure_ifmedia; 531 int anar, gig, err, reg; 532 533 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 534 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 535 return (EINVAL); 536 537 if (!(sc->ure_chip & URE_CHIP_VER_7420)) { 538 reg = ure_ocp_reg_read(sc, URE_OCP_10GBT_CTRL); 539 reg &= ~URE_ADV_2500TFDX; 540 } 541 542 anar = gig = 0; 543 switch (IFM_SUBTYPE(ifm->ifm_media)) { 544 case IFM_AUTO: 545 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 546 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 547 if (!(sc->ure_chip & URE_CHIP_VER_7420)) 548 reg |= URE_ADV_2500TFDX; 549 break; 550 case IFM_2500_T: 551 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 552 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 553 reg |= URE_ADV_2500TFDX; 554 ifp->if_baudrate = IF_Mbps(2500); 555 break; 556 case IFM_1000_T: 557 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 558 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 559 ifp->if_baudrate = IF_Gbps(1); 560 break; 561 case IFM_100_TX: 562 anar |= ANAR_TX | ANAR_TX_FD; 563 ifp->if_baudrate = IF_Mbps(100); 564 break; 565 case IFM_10_T: 566 anar |= ANAR_10 | ANAR_10_FD; 567 ifp->if_baudrate = IF_Mbps(10); 568 break; 569 default: 570 printf("%s: unsupported media type\n", 571 sc->ure_dev.dv_xname); 572 return (EINVAL); 573 } 574 575 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_ANAR * 2, 576 anar | ANAR_PAUSE_ASYM | ANAR_FC); 577 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_100T2CR * 2, gig); 578 if (!(sc->ure_chip & URE_CHIP_VER_7420)) 579 ure_ocp_reg_write(sc, URE_OCP_10GBT_CTRL, reg); 580 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR, 581 BMCR_AUTOEN | BMCR_STARTNEG); 582 583 return (0); 584 } 585 586 if (mii->mii_instance) { 587 struct mii_softc *miisc; 588 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 589 PHY_RESET(miisc); 590 } 591 592 err = mii_mediachg(mii); 593 if (err == ENXIO) 594 return (0); 595 else 596 return (err); 597 } 598 599 void 600 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 601 { 602 struct ure_softc *sc = ifp->if_softc; 603 struct mii_data *mii = &sc->ure_mii; 604 uint16_t status = 0; 605 606 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 607 ifmr->ifm_status = IFM_AVALID; 608 if (ure_get_link_status(sc)) { 609 ifmr->ifm_status |= IFM_ACTIVE; 610 status = ure_read_2(sc, URE_PLA_PHYSTATUS, 611 URE_MCU_TYPE_PLA); 612 if ((status & URE_PHYSTATUS_FDX) || 613 (status & URE_PHYSTATUS_2500MBPS)) 614 ifmr->ifm_active |= IFM_FDX; 615 else 616 ifmr->ifm_active |= IFM_HDX; 617 if (status & URE_PHYSTATUS_10MBPS) 618 ifmr->ifm_active |= IFM_10_T; 619 else if (status & URE_PHYSTATUS_100MBPS) 620 ifmr->ifm_active |= IFM_100_TX; 621 else if (status & URE_PHYSTATUS_1000MBPS) 622 ifmr->ifm_active |= IFM_1000_T; 623 else if (status & URE_PHYSTATUS_2500MBPS) 624 ifmr->ifm_active |= IFM_2500_T; 625 } 626 return; 627 } 628 629 mii_pollstat(mii); 630 ifmr->ifm_active = mii->mii_media_active; 631 ifmr->ifm_status = mii->mii_media_status; 632 } 633 634 void 635 ure_add_media_types(struct ure_softc *sc) 636 { 637 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 638 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 639 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 640 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, 641 NULL); 642 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 643 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, 644 NULL); 645 if (!(sc->ure_chip & URE_CHIP_VER_7420)) { 646 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_2500_T, 0, NULL); 647 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_2500_T | IFM_FDX, 648 0, NULL); 649 } 650 } 651 652 void 653 ure_link_state(struct ure_softc *sc) 654 { 655 struct ifnet *ifp = &sc->ure_ac.ac_if; 656 int link = LINK_STATE_DOWN; 657 658 if (ure_get_link_status(sc)) 659 link = LINK_STATE_UP; 660 661 if (ifp->if_link_state != link) { 662 ifp->if_link_state = link; 663 if_link_state_change(ifp); 664 } 665 } 666 667 int 668 ure_get_link_status(struct ure_softc *sc) 669 { 670 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & 671 URE_PHYSTATUS_LINK) { 672 sc->ure_flags |= URE_FLAG_LINK; 673 return (1); 674 } else { 675 sc->ure_flags &= ~URE_FLAG_LINK; 676 return (0); 677 } 678 } 679 680 void 681 ure_iff(struct ure_softc *sc) 682 { 683 struct ifnet *ifp = &sc->ure_ac.ac_if; 684 struct ether_multi *enm; 685 struct ether_multistep step; 686 uint32_t hashes[2] = { 0, 0 }; 687 uint32_t hash; 688 uint32_t rxmode; 689 690 if (usbd_is_dying(sc->ure_udev)) 691 return; 692 693 rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA); 694 rxmode &= ~URE_RCR_ACPT_ALL; 695 ifp->if_flags &= ~IFF_ALLMULTI; 696 697 /* 698 * Always accept frames destined to our station address. 699 * Always accept broadcast frames. 700 */ 701 rxmode |= URE_RCR_APM | URE_RCR_AB; 702 703 if (ifp->if_flags & IFF_PROMISC || sc->ure_ac.ac_multirangecnt > 0) { 704 ifp->if_flags |= IFF_ALLMULTI; 705 rxmode |= URE_RCR_AM; 706 if (ifp->if_flags & IFF_PROMISC) 707 rxmode |= URE_RCR_AAP; 708 hashes[0] = hashes[1] = 0xffffffff; 709 } else { 710 rxmode |= URE_RCR_AM; 711 712 ETHER_FIRST_MULTI(step, &sc->ure_ac, enm); 713 while (enm != NULL) { 714 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) 715 >> 26; 716 if (hash < 32) 717 hashes[0] |= (1 << hash); 718 else 719 hashes[1] |= (1 << (hash - 32)); 720 721 ETHER_NEXT_MULTI(step, enm); 722 } 723 724 hash = swap32(hashes[0]); 725 hashes[0] = swap32(hashes[1]); 726 hashes[1] = hash; 727 } 728 729 ure_write_mem(sc, URE_PLA_MAR, URE_MCU_TYPE_PLA | URE_BYTE_EN_DWORD, 730 hashes, sizeof(hashes)); 731 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 732 } 733 734 void 735 ure_rxvlan(struct ure_softc *sc) 736 { 737 struct ifnet *ifp = &sc->ure_ac.ac_if; 738 uint16_t reg; 739 740 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 741 reg = ure_read_2(sc, URE_PLA_RCR1, URE_MCU_TYPE_PLA); 742 reg &= ~(URE_INNER_VLAN | URE_OUTER_VLAN); 743 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 744 reg |= (URE_INNER_VLAN | URE_OUTER_VLAN); 745 ure_write_2(sc, URE_PLA_RCR1, URE_MCU_TYPE_PLA, reg); 746 } else { 747 reg = ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA); 748 reg &= ~URE_CPCR_RX_VLAN; 749 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 750 reg |= URE_CPCR_RX_VLAN; 751 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, reg); 752 } 753 } 754 755 void 756 ure_reset(struct ure_softc *sc) 757 { 758 int i; 759 760 if (sc->ure_flags & URE_FLAG_8156) { 761 URE_CLRBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_TE); 762 URE_CLRBIT_2(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, 763 BMU_RESET_EP_IN); 764 URE_SETBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 765 URE_CDC_ECM_EN); 766 URE_CLRBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE); 767 URE_SETBIT_2(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, 768 BMU_RESET_EP_IN); 769 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 770 URE_CDC_ECM_EN); 771 } else { 772 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 773 774 for (i = 0; i < URE_TIMEOUT; i++) { 775 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) & 776 URE_CR_RST)) 777 break; 778 DELAY(100); 779 } 780 if (i == URE_TIMEOUT) 781 printf("%s: reset never completed\n", 782 sc->ure_dev.dv_xname); 783 } 784 } 785 786 void 787 ure_watchdog(struct ifnet *ifp) 788 { 789 struct ure_softc *sc = ifp->if_softc; 790 struct ure_chain *c; 791 usbd_status err; 792 int i, s; 793 794 ifp->if_timer = 0; 795 796 if (usbd_is_dying(sc->ure_udev)) 797 return; 798 799 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) 800 return; 801 802 sc = ifp->if_softc; 803 s = splnet(); 804 805 ifp->if_oerrors++; 806 DPRINTF(("%s: watchdog timeout\n", sc->ure_dev.dv_xname)); 807 808 for (i = 0; i < URE_TX_LIST_CNT; i++) { 809 c = &sc->ure_cdata.ure_tx_chain[i]; 810 if (c->uc_cnt > 0) { 811 usbd_get_xfer_status(c->uc_xfer, NULL, NULL, NULL, 812 &err); 813 ure_txeof(c->uc_xfer, c, err); 814 } 815 } 816 817 if (ifq_is_oactive(&ifp->if_snd)) 818 ifq_restart(&ifp->if_snd); 819 splx(s); 820 } 821 822 void 823 ure_init(void *xsc) 824 { 825 struct ure_softc *sc = xsc; 826 struct ure_chain *c; 827 struct ifnet *ifp = &sc->ure_ac.ac_if; 828 usbd_status err; 829 int s, i; 830 831 s = splnet(); 832 833 /* Cancel pending I/O. */ 834 ure_stop(sc); 835 836 if (sc->ure_flags & URE_FLAG_8152) 837 ure_rtl8152_nic_reset(sc); 838 else 839 ure_rtl8153_nic_reset(sc); 840 841 if (ure_xfer_list_init(sc, sc->ure_cdata.ure_rx_chain, 842 sc->ure_rxbufsz, URE_RX_LIST_CNT) == ENOBUFS) { 843 printf("%s: rx list init failed\n", sc->ure_dev.dv_xname); 844 splx(s); 845 return; 846 } 847 848 if (ure_xfer_list_init(sc, sc->ure_cdata.ure_tx_chain, 849 sc->ure_txbufsz, URE_TX_LIST_CNT) == ENOBUFS) { 850 printf("%s: tx list init failed\n", sc->ure_dev.dv_xname); 851 splx(s); 852 return; 853 } 854 855 /* Initialize the SLIST we are using for the multiple tx buffers */ 856 SLIST_INIT(&sc->ure_cdata.ure_tx_free); 857 for (i = 0; i < URE_TX_LIST_CNT; i++) 858 SLIST_INSERT_HEAD(&sc->ure_cdata.ure_tx_free, 859 &sc->ure_cdata.ure_tx_chain[i], uc_list); 860 861 /* Setup MAC address, and enable TX/RX. */ 862 ure_ifmedia_init(ifp); 863 864 /* Load the multicast filter. */ 865 ure_iff(sc); 866 867 /* Open RX and TX pipes. */ 868 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_RX], 869 USBD_EXCLUSIVE_USE, &sc->ure_ep[URE_ENDPT_RX]); 870 if (err) { 871 printf("%s: open rx pipe failed: %s\n", 872 sc->ure_dev.dv_xname, usbd_errstr(err)); 873 splx(s); 874 return; 875 } 876 877 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_TX], 878 USBD_EXCLUSIVE_USE, &sc->ure_ep[URE_ENDPT_TX]); 879 if (err) { 880 printf("%s: open tx pipe failed: %s\n", 881 sc->ure_dev.dv_xname, usbd_errstr(err)); 882 splx(s); 883 return; 884 } 885 886 /* Start up the receive pipe. */ 887 for (i = 0; i < URE_RX_LIST_CNT; i++) { 888 c = &sc->ure_cdata.ure_rx_chain[i]; 889 usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_RX], 890 c, c->uc_buf, c->uc_bufmax, 891 USBD_SHORT_XFER_OK | USBD_NO_COPY, 892 USBD_NO_TIMEOUT, ure_rxeof); 893 usbd_transfer(c->uc_xfer); 894 } 895 896 ure_ifmedia_upd(ifp); 897 898 /* Indicate we are up and running. */ 899 sc->ure_flags &= ~URE_FLAG_LINK; 900 ifp->if_flags |= IFF_RUNNING; 901 ifq_clr_oactive(&ifp->if_snd); 902 903 timeout_add_sec(&sc->ure_stat_ch, 1); 904 905 splx(s); 906 } 907 908 void 909 ure_start(struct ifnet *ifp) 910 { 911 struct ure_softc *sc = ifp->if_softc; 912 struct ure_cdata *cd = &sc->ure_cdata; 913 struct ure_chain *c; 914 struct mbuf *m = NULL; 915 uint32_t new_buflen; 916 int s, mlen; 917 918 if (!(sc->ure_flags & URE_FLAG_LINK) || 919 (ifp->if_flags & (IFF_RUNNING|IFF_UP)) != 920 (IFF_RUNNING|IFF_UP)) { 921 return; 922 } 923 924 s = splnet(); 925 926 c = SLIST_FIRST(&cd->ure_tx_free); 927 while (c != NULL) { 928 m = ifq_deq_begin(&ifp->if_snd); 929 if (m == NULL) 930 break; 931 932 mlen = m->m_pkthdr.len; 933 934 /* Discard packet larger than buffer. */ 935 if (mlen + sizeof(struct ure_txpkt) >= c->uc_bufmax) { 936 ifq_deq_commit(&ifp->if_snd, m); 937 m_freem(m); 938 ifp->if_oerrors++; 939 continue; 940 } 941 942 /* 943 * If packet larger than remaining space, send buffer and 944 * continue. 945 */ 946 new_buflen = roundup(c->uc_buflen, URE_TX_BUF_ALIGN); 947 if (new_buflen + sizeof(struct ure_txpkt) + mlen >= 948 c->uc_bufmax) { 949 ifq_deq_rollback(&ifp->if_snd, m); 950 SLIST_REMOVE_HEAD(&cd->ure_tx_free, uc_list); 951 if (ure_encap_xfer(ifp, sc, c)) { 952 SLIST_INSERT_HEAD(&cd->ure_tx_free, c, 953 uc_list); 954 break; 955 } 956 c = SLIST_FIRST(&cd->ure_tx_free); 957 continue; 958 } 959 960 /* Append packet to current buffer. */ 961 mlen = ure_encap_txpkt(m, c->uc_buf + new_buflen, 962 c->uc_bufmax - new_buflen); 963 if (mlen <= 0) { 964 ifq_deq_rollback(&ifp->if_snd, m); 965 break; 966 } 967 968 ifq_deq_commit(&ifp->if_snd, m); 969 c->uc_cnt += 1; 970 c->uc_buflen = new_buflen + mlen; 971 972 #if NBPFILTER > 0 973 if (ifp->if_bpf) 974 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 975 #endif 976 977 m_freem(m); 978 } 979 980 if (c != NULL) { 981 /* Send current buffer unless empty */ 982 if (c->uc_buflen > 0 && c->uc_cnt > 0) { 983 SLIST_REMOVE_HEAD(&cd->ure_tx_free, uc_list); 984 if (ure_encap_xfer(ifp, sc, c)) { 985 SLIST_INSERT_HEAD(&cd->ure_tx_free, c, 986 uc_list); 987 } 988 c = SLIST_FIRST(&cd->ure_tx_free); 989 } 990 } 991 992 ifp->if_timer = 5; 993 if (c == NULL) 994 ifq_set_oactive(&ifp->if_snd); 995 splx(s); 996 } 997 998 void 999 ure_tick(void *xsc) 1000 { 1001 struct ure_softc *sc = xsc; 1002 1003 if (sc == NULL) 1004 return; 1005 1006 if (usbd_is_dying(sc->ure_udev)) 1007 return; 1008 1009 usb_add_task(sc->ure_udev, &sc->ure_tick_task); 1010 } 1011 1012 void 1013 ure_stop(struct ure_softc *sc) 1014 { 1015 struct ure_cdata *cd; 1016 struct ifnet *ifp; 1017 usbd_status err; 1018 1019 ure_reset(sc); 1020 1021 ifp = &sc->ure_ac.ac_if; 1022 ifp->if_timer = 0; 1023 ifp->if_flags &= ~IFF_RUNNING; 1024 ifq_clr_oactive(&ifp->if_snd); 1025 1026 timeout_del(&sc->ure_stat_ch); 1027 sc->ure_flags &= ~URE_FLAG_LINK; 1028 1029 if (sc->ure_ep[URE_ENDPT_RX] != NULL) { 1030 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_RX]); 1031 if (err) { 1032 printf("%s: close rx pipe failed: %s\n", 1033 sc->ure_dev.dv_xname, usbd_errstr(err)); 1034 } 1035 sc->ure_ep[URE_ENDPT_RX] = NULL; 1036 } 1037 1038 if (sc->ure_ep[URE_ENDPT_TX] != NULL) { 1039 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_TX]); 1040 if (err) { 1041 printf("%s: close tx pipe failed: %s\n", 1042 sc->ure_dev.dv_xname, usbd_errstr(err)); 1043 } 1044 sc->ure_ep[URE_ENDPT_TX] = NULL; 1045 } 1046 1047 cd = &sc->ure_cdata; 1048 ure_xfer_list_free(sc, cd->ure_rx_chain, URE_RX_LIST_CNT); 1049 ure_xfer_list_free(sc, cd->ure_tx_chain, URE_TX_LIST_CNT); 1050 } 1051 1052 int 1053 ure_xfer_list_init(struct ure_softc *sc, struct ure_chain *ch, 1054 uint32_t bufsize, int listlen) 1055 { 1056 struct ure_chain *c; 1057 int i; 1058 1059 for (i = 0; i < listlen; i++) { 1060 c = &ch[i]; 1061 c->uc_sc = sc; 1062 c->uc_idx = i; 1063 c->uc_buflen = 0; 1064 c->uc_bufmax = bufsize; 1065 c->uc_cnt = 0; 1066 if (c->uc_xfer == NULL) { 1067 c->uc_xfer = usbd_alloc_xfer(sc->ure_udev); 1068 if (c->uc_xfer == NULL) 1069 return (ENOBUFS); 1070 c->uc_buf = usbd_alloc_buffer(c->uc_xfer, c->uc_bufmax); 1071 if (c->uc_buf == NULL) { 1072 usbd_free_xfer(c->uc_xfer); 1073 c->uc_xfer = NULL; 1074 return (ENOBUFS); 1075 } 1076 } 1077 } 1078 1079 return (0); 1080 } 1081 1082 void 1083 ure_xfer_list_free(struct ure_softc *sc, struct ure_chain *ch, int listlen) 1084 { 1085 int i; 1086 1087 for (i = 0; i < listlen; i++) { 1088 if (ch[i].uc_buf != NULL) { 1089 ch[i].uc_buf = NULL; 1090 } 1091 ch[i].uc_cnt = 0; 1092 if (ch[i].uc_xfer != NULL) { 1093 usbd_free_xfer(ch[i].uc_xfer); 1094 ch[i].uc_xfer = NULL; 1095 } 1096 } 1097 } 1098 1099 void 1100 ure_rtl8152_init(struct ure_softc *sc) 1101 { 1102 uint32_t pwrctrl; 1103 1104 /* Disable ALDPS. */ 1105 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 1106 URE_DIS_SDSAVE); 1107 usbd_delay_ms(sc->ure_udev, 20); 1108 1109 if (sc->ure_chip & URE_CHIP_VER_4C00) 1110 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 1111 URE_LED_MODE_MASK); 1112 1113 URE_CLRBIT_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, URE_POWER_CUT); 1114 URE_CLRBIT_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 1115 URE_RESUME_INDICATE); 1116 1117 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 1118 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 1119 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 1120 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 1121 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 1122 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 1123 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 1124 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 1125 URE_SPDWN_LINKCHG_MSK); 1126 1127 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET); 1128 1129 /* Enable Rx aggregation. */ 1130 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1131 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1132 } 1133 1134 void 1135 ure_rtl8153_init(struct ure_softc *sc) 1136 { 1137 uint16_t reg; 1138 uint8_t u1u2[8]; 1139 int i; 1140 1141 memset(u1u2, 0x00, sizeof(u1u2)); 1142 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, u1u2, 1143 sizeof(u1u2)); 1144 1145 for (i = 0; i < 500; i++) { 1146 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 1147 URE_AUTOLOAD_DONE) 1148 break; 1149 usbd_delay_ms(sc->ure_udev, 20); 1150 } 1151 if (i == 500) 1152 printf("%s: timeout waiting for chip autoload\n", 1153 sc->ure_dev.dv_xname); 1154 1155 ure_rtl8153_phy_status(sc, 0); 1156 1157 if (sc->ure_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 | 1158 URE_CHIP_VER_5C20)) { 1159 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG, 1160 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 1161 } 1162 1163 ure_rtl8153_phy_status(sc, URE_PHY_STAT_LAN_ON); 1164 1165 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1166 1167 if (sc->ure_chip & URE_CHIP_VER_5C10) { 1168 reg = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 1169 reg &= ~URE_PWD_DN_SCALE_MASK; 1170 reg |= URE_PWD_DN_SCALE(96); 1171 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, reg); 1172 1173 URE_SETBIT_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 1174 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 1175 } else if (sc->ure_chip & URE_CHIP_VER_5C20) { 1176 URE_CLRBIT_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 1177 URE_ECM_ALDPS); 1178 } 1179 if (sc->ure_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) { 1180 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB)) 1181 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, 1182 URE_DYNAMIC_BURST); 1183 else 1184 URE_CLRBIT_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, 1185 URE_DYNAMIC_BURST); 1186 } 1187 1188 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, URE_EP4_FULL_FC); 1189 1190 URE_CLRBIT_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, URE_TIMER11_EN); 1191 1192 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 1193 URE_LED_MODE_MASK); 1194 1195 if ((sc->ure_chip & URE_CHIP_VER_5C10) && 1196 sc->ure_udev->speed != USB_SPEED_SUPER) 1197 reg = URE_LPM_TIMER_500MS; 1198 else 1199 reg = URE_LPM_TIMER_500US; 1200 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 1201 URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM | reg); 1202 1203 reg = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 1204 reg &= ~URE_SEN_VAL_MASK; 1205 reg |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 1206 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, reg); 1207 1208 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 1209 1210 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 1211 URE_PWR_EN | URE_PHASE2_EN); 1212 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS); 1213 1214 memset(u1u2, 0xff, sizeof(u1u2)); 1215 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, u1u2, 1216 sizeof(u1u2)); 1217 1218 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0); 1219 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 0); 1220 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 0); 1221 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0); 1222 1223 /* Enable Rx aggregation. */ 1224 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1225 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1226 1227 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET); 1228 } 1229 1230 void 1231 ure_rtl8153b_init(struct ure_softc *sc) 1232 { 1233 uint16_t reg; 1234 int i; 1235 1236 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1237 URE_CLRBIT_1(sc, URE_USB_ECM_OP, URE_MCU_TYPE_USB, 1238 URE_EN_ALL_SPEED); 1239 ure_write_2(sc, URE_USB_SPEED_OPTION, URE_MCU_TYPE_USB, 0); 1240 URE_SETBIT_2(sc, URE_USB_ECM_OPTION, URE_MCU_TYPE_USB, 1241 URE_BYPASS_MAC_RESET); 1242 1243 if (sc->ure_flags & URE_FLAG_8156B) 1244 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 1245 URE_RX_DETECT8); 1246 } 1247 1248 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, LPM_U1U2_EN); 1249 1250 if (sc->ure_flags & URE_FLAG_8156B) 1251 ure_wait_for_flash(sc); 1252 1253 for (i = 0; i < 500; i++) { 1254 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 1255 URE_AUTOLOAD_DONE) 1256 break; 1257 usbd_delay_ms(sc->ure_udev, 20); 1258 } 1259 if (i == 500) 1260 printf("%s: timeout waiting for chip autoload\n", 1261 sc->ure_dev.dv_xname); 1262 1263 ure_rtl8153_phy_status(sc, 0); 1264 ure_rtl8153_phy_status(sc, URE_PHY_STAT_LAN_ON); 1265 1266 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1267 1268 /* MSC timer, 32760 ms. */ 1269 ure_write_2(sc, URE_USB_MSC_TIMER, URE_MCU_TYPE_USB, 4095); 1270 1271 if (!(sc->ure_flags & URE_FLAG_8153B)) { 1272 /* U1/U2/L1 idle timer, 500 us. */ 1273 ure_write_2(sc, URE_USB_U1U2_TIMER, URE_MCU_TYPE_USB, 500); 1274 } 1275 1276 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN); 1277 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS); 1278 1279 URE_CLRBIT_1(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 1280 URE_UPS_EN | URE_USP_PREWAKE); 1281 URE_CLRBIT_1(sc, URE_USB_MISC_2, URE_MCU_TYPE_USB, 1282 URE_UPS_FORCE_PWR_DOWN | URE_UPS_NO_UPS); 1283 1284 URE_CLRBIT_1(sc, URE_PLA_INDICATE_FALG, URE_MCU_TYPE_PLA, 1285 URE_UPCOMING_RUNTIME_D3); 1286 URE_CLRBIT_1(sc, URE_PLA_SUSPEND_FLAG, URE_MCU_TYPE_PLA, 1287 URE_LINK_CHG_EVENT); 1288 URE_CLRBIT_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, 1289 URE_LINK_CHANGE_FLAG); 1290 1291 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 1292 URE_CLRBIT_2(sc, URE_PLA_CONFIG34, URE_MCU_TYPE_PLA, 1293 URE_LINK_OFF_WAKE_EN); 1294 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 1295 1296 if (sc->ure_flags & URE_FLAG_8153B) { 1297 reg = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA); 1298 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & 1299 URE_PHYSTATUS_LINK) 1300 reg |= URE_CUR_LINK_OK; 1301 else 1302 reg &= ~URE_CUR_LINK_OK; 1303 ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, 1304 reg | URE_POLL_LINK_CHG); 1305 } 1306 1307 if (sc->ure_udev->speed == USB_SPEED_SUPER) { 1308 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, 1309 LPM_U1U2_EN); 1310 } 1311 1312 if (sc->ure_flags & URE_FLAG_8156B) { 1313 URE_CLRBIT_2(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_SLOT_EN); 1314 URE_SETBIT_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 1315 URE_FLOW_CTRL_EN); 1316 1317 /* Enable fc timer and set timer to 600 ms. */ 1318 ure_write_2(sc, URE_USB_FC_TIMER, URE_MCU_TYPE_USB, 1319 URE_CTRL_TIMER_EN | 75); 1320 1321 reg = ure_read_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB); 1322 if (!(ure_read_2(sc, URE_PLA_POL_GPIO_CTRL, URE_MCU_TYPE_PLA) & 1323 URE_DACK_DET_EN)) 1324 reg |= URE_FLOW_CTRL_PATCH_2; 1325 reg &= ~URE_AUTO_SPEEDUP; 1326 ure_write_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB, reg); 1327 1328 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, 1329 URE_FC_PATCH_TASK); 1330 } 1331 1332 /* MAC clock speed down. */ 1333 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1334 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0x0403); 1335 reg = ure_read_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA); 1336 reg &= ~URE_EEE_SPDWN_RATIO_MASK; 1337 reg |= URE_MAC_CLK_SPDWN_EN | 0x0003; 1338 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, reg); 1339 1340 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 1341 URE_PLA_MCU_SPDWN_EN); 1342 1343 reg = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA); 1344 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & 1345 URE_PHYSTATUS_LINK) 1346 reg |= URE_CUR_LINK_OK; 1347 else 1348 reg &= ~URE_CUR_LINK_OK; 1349 ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, 1350 reg | URE_POLL_LINK_CHG); 1351 } else 1352 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 1353 URE_MAC_CLK_SPDWN_EN); 1354 1355 /* Enable Rx aggregation. */ 1356 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1357 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1358 1359 if (sc->ure_flags & URE_FLAG_8156) 1360 URE_SETBIT_1(sc, URE_USB_BMU_CONFIG, URE_MCU_TYPE_USB, 1361 URE_ACT_ODMA); 1362 1363 if (!(sc->ure_flags & URE_FLAG_8153B)) { 1364 /* 1365 * Select force mode through 0xa5b4 bit 15 1366 * 0: MDIO force mode 1367 * 1: MMD force mode 1368 */ 1369 reg = ure_ocp_reg_read(sc, 0xa5b4); 1370 if (reg & 0x8000) 1371 ure_ocp_reg_write(sc, 0xa5b4, reg & ~0x8000); 1372 } 1373 1374 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET); 1375 } 1376 1377 void 1378 ure_rtl8152_nic_reset(struct ure_softc *sc) 1379 { 1380 uint32_t rx_fifo1, rx_fifo2; 1381 int i; 1382 1383 /* Disable ALDPS. */ 1384 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 1385 URE_DIS_SDSAVE); 1386 usbd_delay_ms(sc->ure_udev, 20); 1387 1388 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL); 1389 1390 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 1391 ure_disable_teredo(sc); 1392 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 1393 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 1394 1395 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB); 1396 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN); 1397 for (i = 0; i < URE_TIMEOUT; i++) { 1398 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1399 URE_LINK_LIST_READY) 1400 break; 1401 usbd_delay_ms(sc->ure_udev, 1); 1402 } 1403 if (i == URE_TIMEOUT) 1404 printf("%s: timeout waiting for OOB control\n", 1405 sc->ure_dev.dv_xname); 1406 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL); 1407 for (i = 0; i < URE_TIMEOUT; i++) { 1408 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1409 URE_LINK_LIST_READY) 1410 break; 1411 usbd_delay_ms(sc->ure_udev, 1); 1412 } 1413 if (i == URE_TIMEOUT) 1414 printf("%s: timeout waiting for OOB control\n", 1415 sc->ure_dev.dv_xname); 1416 1417 ure_reset(sc); 1418 1419 /* Configure Rx FIFO threshold. */ 1420 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 1421 URE_RXFIFO_THR1_NORMAL); 1422 if (sc->ure_udev->speed == USB_SPEED_FULL) { 1423 rx_fifo1 = URE_RXFIFO_THR2_FULL; 1424 rx_fifo2 = URE_RXFIFO_THR3_FULL; 1425 } else { 1426 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 1427 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 1428 } 1429 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 1430 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 1431 1432 /* Configure Tx FIFO threshold. */ 1433 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 1434 URE_TXFIFO_THR_NORMAL); 1435 1436 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 1437 URE_TX_AGG_MAX_THRESHOLD); 1438 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 1439 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 1440 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 1441 1442 ure_rxvlan(sc); 1443 ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA, 1444 ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1445 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO); 1446 1447 /* Enable ALDPS. */ 1448 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, 1449 URE_ENPWRSAVE | URE_ENPDNPS | URE_LINKENA | URE_DIS_SDSAVE); 1450 } 1451 1452 void 1453 ure_rtl8153_nic_reset(struct ure_softc *sc) 1454 { 1455 struct ifnet *ifp = &sc->ure_ac.ac_if; 1456 uint32_t reg = 0; 1457 uint8_t u1u2[8] = { 0 }; 1458 int i; 1459 1460 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) { 1461 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, 1462 LPM_U1U2_EN); 1463 } else { 1464 memset(u1u2, 0x00, sizeof(u1u2)); 1465 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, 1466 u1u2, sizeof(u1u2)); 1467 } 1468 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1469 1470 /* Disable ALDPS. */ 1471 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1472 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 1473 for (i = 0; i < 20; i++) { 1474 usbd_delay_ms(sc->ure_udev, 1); 1475 if (ure_read_2(sc, 0xe000, URE_MCU_TYPE_PLA) & 0x0100) 1476 break; 1477 } 1478 1479 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 1480 ure_disable_teredo(sc); 1481 1482 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL); 1483 1484 ure_reset(sc); 1485 ure_reset_bmu(sc); 1486 1487 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB); 1488 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN); 1489 1490 if (!(sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B))) { 1491 for (i = 0; i < URE_TIMEOUT; i++) { 1492 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1493 URE_LINK_LIST_READY) 1494 break; 1495 usbd_delay_ms(sc->ure_udev, 1); 1496 } 1497 if (i == URE_TIMEOUT) 1498 printf("%s: timeout waiting for OOB control\n", 1499 sc->ure_dev.dv_xname); 1500 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 1501 URE_RE_INIT_LL); 1502 for (i = 0; i < URE_TIMEOUT; i++) { 1503 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1504 URE_LINK_LIST_READY) 1505 break; 1506 usbd_delay_ms(sc->ure_udev, 1); 1507 } 1508 if (i == URE_TIMEOUT) 1509 printf("%s: timeout waiting for OOB control\n", 1510 sc->ure_dev.dv_xname); 1511 } 1512 1513 ure_rxvlan(sc); 1514 1515 ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA, 1516 URE_FRAMELEN(ifp->if_mtu)); 1517 ure_write_1(sc, URE_PLA_MTPS, URE_MCU_TYPE_PLA, MTPS_JUMBO); 1518 1519 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1520 ure_write_2(sc, URE_PLA_RX_FIFO_FULL, URE_MCU_TYPE_PLA, 1521 (sc->ure_flags & URE_FLAG_8156) ? 1024 : 512); 1522 ure_write_2(sc, URE_PLA_RX_FIFO_EMPTY, URE_MCU_TYPE_PLA, 1523 (sc->ure_flags & URE_FLAG_8156) ? 2048 : 1024); 1524 1525 /* Tx share fifo free credit full threshold. */ 1526 ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 8); 1527 ure_write_2(sc, URE_PLA_TXFIFO_FULL, URE_MCU_TYPE_PLA, 128); 1528 1529 if (sc->ure_flags & URE_FLAG_8156) 1530 URE_SETBIT_2(sc, URE_USB_BMU_CONFIG, URE_MCU_TYPE_USB, 1531 URE_ACT_ODMA); 1532 1533 /* FIFO settings */ 1534 reg = ure_read_2(sc, URE_PLA_RXFIFO_FULL, URE_MCU_TYPE_PLA); 1535 reg &= ~URE_RXFIFO_FULL_MASK; 1536 ure_write_2(sc, URE_PLA_RXFIFO_FULL, URE_MCU_TYPE_PLA, 1537 reg | 0x0008); 1538 1539 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 1540 URE_PLA_MCU_SPDWN_EN); 1541 1542 URE_CLRBIT_2(sc, URE_USB_SPEED_OPTION, URE_MCU_TYPE_USB, 1543 URE_RG_PWRDN_EN | URE_ALL_SPEED_OFF); 1544 1545 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, 1546 0x00600400); 1547 } else { 1548 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 1549 URE_TCR0_AUTO_FIFO); 1550 ure_reset(sc); 1551 1552 /* Configure Rx FIFO threshold. */ 1553 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 1554 URE_RXFIFO_THR1_NORMAL); 1555 ure_write_2(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, 1556 URE_RXFIFO_THR2_NORMAL); 1557 ure_write_2(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, 1558 URE_RXFIFO_THR3_NORMAL); 1559 1560 /* Configure Tx FIFO threshold. */ 1561 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 1562 URE_TXFIFO_THR_NORMAL2); 1563 1564 if (sc->ure_flags & URE_FLAG_8153B) { 1565 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, 1566 URE_RX_THR_B); 1567 1568 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, 1569 URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN); 1570 } else { 1571 URE_SETBIT_1(sc, URE_PLA_CONFIG6, URE_MCU_TYPE_PLA, 1572 URE_LANWAKE_CLR_EN); 1573 URE_CLRBIT_1(sc, URE_PLA_LWAKE_CTRL_REG, 1574 URE_MCU_TYPE_PLA, URE_LANWAKE_PIN); 1575 URE_CLRBIT_2(sc, URE_USB_SSPHYLINK1, URE_MCU_TYPE_USB, 1576 URE_DELAY_PHY_PWR_CHG); 1577 } 1578 } 1579 1580 /* Enable ALDPS. */ 1581 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1582 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | URE_EN_ALDPS); 1583 1584 if ((sc->ure_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) || 1585 (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B))) 1586 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 1587 URE_U2P3_ENABLE); 1588 1589 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) { 1590 if (sc->ure_udev->speed == USB_SPEED_SUPER) 1591 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, 1592 LPM_U1U2_EN); 1593 } else { 1594 memset(u1u2, 0xff, sizeof(u1u2)); 1595 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, 1596 u1u2, sizeof(u1u2)); 1597 } 1598 } 1599 1600 uint16_t 1601 ure_rtl8153_phy_status(struct ure_softc *sc, int desired) 1602 { 1603 uint16_t reg; 1604 int i; 1605 1606 for (i = 0; i < 500; i++) { 1607 reg = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & 1608 URE_PHY_STAT_MASK; 1609 if (desired) { 1610 if (reg == desired) 1611 break; 1612 } else { 1613 if (reg == URE_PHY_STAT_LAN_ON || 1614 reg == URE_PHY_STAT_PWRDN || 1615 reg == URE_PHY_STAT_EXT_INIT) 1616 break; 1617 } 1618 usbd_delay_ms(sc->ure_udev, 20); 1619 } 1620 if (i == 500) 1621 printf("%s: timeout waiting for phy to stabilize\n", 1622 sc->ure_dev.dv_xname); 1623 1624 return reg; 1625 } 1626 1627 void 1628 ure_wait_for_flash(struct ure_softc *sc) 1629 { 1630 int i; 1631 1632 if ((ure_read_2(sc, URE_PLA_GPHY_CTRL, URE_MCU_TYPE_PLA) & 1633 URE_GPHY_FLASH) && 1634 !(ure_read_2(sc, URE_USB_GPHY_CTRL, URE_MCU_TYPE_USB) & 1635 URE_BYPASS_FLASH)) { 1636 for (i = 0; i < 100; i++) { 1637 if (ure_read_2(sc, URE_USB_GPHY_CTRL, 1638 URE_MCU_TYPE_USB) & URE_GPHY_PATCH_DONE) 1639 break; 1640 DELAY(1000); 1641 } 1642 if (i == 100) 1643 printf("%s: timeout waiting for loading flash\n", 1644 sc->ure_dev.dv_xname); 1645 } 1646 } 1647 1648 void 1649 ure_reset_bmu(struct ure_softc *sc) 1650 { 1651 uint8_t reg; 1652 1653 reg = ure_read_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB); 1654 reg &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); 1655 ure_write_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, reg); 1656 reg |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; 1657 ure_write_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, reg); 1658 } 1659 1660 void 1661 ure_disable_teredo(struct ure_softc *sc) 1662 { 1663 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) 1664 ure_write_1(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 0xff); 1665 else { 1666 URE_CLRBIT_2(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 1667 URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | 1668 URE_OOB_TEREDO_EN); 1669 } 1670 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, URE_WDT6_SET_MODE); 1671 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 1672 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 1673 } 1674 1675 int 1676 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1677 { 1678 struct ure_softc *sc = ifp->if_softc; 1679 struct ifreq *ifr = (struct ifreq *)data; 1680 int s, error = 0; 1681 1682 s = splnet(); 1683 1684 switch (cmd) { 1685 case SIOCSIFADDR: 1686 ifp->if_flags |= IFF_UP; 1687 if (!(ifp->if_flags & IFF_RUNNING)) 1688 ure_init(sc); 1689 break; 1690 1691 case SIOCSIFFLAGS: 1692 if (ifp->if_flags & IFF_UP) { 1693 if (ifp->if_flags & IFF_RUNNING) 1694 error = ENETRESET; 1695 else 1696 ure_init(sc); 1697 } else { 1698 if (ifp->if_flags & IFF_RUNNING) 1699 ure_stop(sc); 1700 } 1701 break; 1702 1703 case SIOCGIFMEDIA: 1704 case SIOCSIFMEDIA: 1705 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) 1706 error = ifmedia_ioctl(ifp, ifr, &sc->ure_ifmedia, cmd); 1707 else 1708 error = ifmedia_ioctl(ifp, ifr, &sc->ure_mii.mii_media, 1709 cmd); 1710 break; 1711 1712 default: 1713 error = ether_ioctl(ifp, &sc->ure_ac, cmd, data); 1714 } 1715 1716 if (error == ENETRESET) { 1717 if (ifp->if_flags & IFF_RUNNING) 1718 ure_iff(sc); 1719 error = 0; 1720 } 1721 1722 splx(s); 1723 1724 return (error); 1725 } 1726 1727 int 1728 ure_match(struct device *parent, void *match, void *aux) 1729 { 1730 struct usb_attach_arg *uaa = aux; 1731 1732 if (uaa->iface == NULL || uaa->configno != 1) 1733 return (UMATCH_NONE); 1734 1735 return (usb_lookup(ure_devs, uaa->vendor, uaa->product) != NULL ? 1736 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 1737 } 1738 1739 void 1740 ure_attach(struct device *parent, struct device *self, void *aux) 1741 { 1742 struct ure_softc *sc = (struct ure_softc *)self; 1743 struct usb_attach_arg *uaa = aux; 1744 usb_interface_descriptor_t *id; 1745 usb_endpoint_descriptor_t *ed; 1746 u_char eaddr[8]; /* 4byte padded */ 1747 struct ifnet *ifp; 1748 int i, mii_flags = 0, s; 1749 uint16_t ver; 1750 1751 sc->ure_udev = uaa->device; 1752 sc->ure_iface = uaa->iface; 1753 1754 usb_init_task(&sc->ure_tick_task, ure_tick_task, sc, 1755 USB_TASK_TYPE_GENERIC); 1756 1757 id = usbd_get_interface_descriptor(sc->ure_iface); 1758 1759 for (i = 0; i < id->bNumEndpoints; i++) { 1760 ed = usbd_interface2endpoint_descriptor(sc->ure_iface, i); 1761 if (!ed) { 1762 printf("%s: couldn't get ep %d\n", 1763 sc->ure_dev.dv_xname, i); 1764 return; 1765 } 1766 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 1767 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 1768 sc->ure_ed[URE_ENDPT_RX] = ed->bEndpointAddress; 1769 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 1770 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 1771 sc->ure_ed[URE_ENDPT_TX] = ed->bEndpointAddress; 1772 } 1773 } 1774 1775 sc->ure_txbufsz = URE_TX_BUFSZ; 1776 sc->ure_rxbufsz = URE_8153_RX_BUFSZ; 1777 1778 s = splnet(); 1779 1780 sc->ure_phyno = 0; 1781 printf("%s: ", sc->ure_dev.dv_xname); 1782 1783 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 1784 switch (ver) { 1785 case 0x4c00: 1786 sc->ure_flags = URE_FLAG_8152; 1787 sc->ure_rxbufsz = URE_8152_RX_BUFSZ; 1788 sc->ure_chip |= URE_CHIP_VER_4C00; 1789 printf("RTL8152 (0x4c00)"); 1790 break; 1791 case 0x4c10: 1792 sc->ure_flags = URE_FLAG_8152; 1793 sc->ure_rxbufsz = URE_8152_RX_BUFSZ; 1794 sc->ure_chip |= URE_CHIP_VER_4C10; 1795 printf("RTL8152 (0x4c10)"); 1796 break; 1797 case 0x5c00: 1798 sc->ure_chip |= URE_CHIP_VER_5C00; 1799 printf("RTL8153 (0x5c00)"); 1800 break; 1801 case 0x5c10: 1802 sc->ure_chip |= URE_CHIP_VER_5C10; 1803 printf("RTL8153 (0x5c10)"); 1804 break; 1805 case 0x5c20: 1806 sc->ure_chip |= URE_CHIP_VER_5C20; 1807 printf("RTL8153 (0x5c20)"); 1808 break; 1809 case 0x5c30: 1810 sc->ure_chip |= URE_CHIP_VER_5C30; 1811 printf("RTL8153 (0x5c30)"); 1812 break; 1813 case 0x6000: 1814 sc->ure_flags = URE_FLAG_8153B; 1815 printf("RTL8153B (0x6000)"); 1816 break; 1817 case 0x6010: 1818 sc->ure_flags = URE_FLAG_8153B; 1819 printf("RTL8153B (0x6010)"); 1820 break; 1821 case 0x7020: 1822 sc->ure_flags = URE_FLAG_8156; 1823 printf("RTL8156 (0x7020)"); 1824 break; 1825 case 0x7030: 1826 sc->ure_flags = URE_FLAG_8156; 1827 printf("RTL8156 (0x7030)"); 1828 break; 1829 case 0x7410: 1830 sc->ure_flags = URE_FLAG_8156B; 1831 printf("RTL8156B (0x7410)"); 1832 break; 1833 case 0x7420: 1834 sc->ure_flags = URE_FLAG_8156B; 1835 sc->ure_chip = URE_CHIP_VER_7420; 1836 printf("RTL8153D (0x7420)"); 1837 break; 1838 default: 1839 printf(", unknown ver %02x", ver); 1840 break; 1841 } 1842 1843 if (sc->ure_flags & URE_FLAG_8152) 1844 ure_rtl8152_init(sc); 1845 else if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | 1846 URE_FLAG_8156B)) 1847 ure_rtl8153b_init(sc); 1848 else 1849 ure_rtl8153_init(sc); 1850 1851 if (sc->ure_chip & URE_CHIP_VER_4C00) 1852 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr, 1853 sizeof(eaddr)); 1854 else 1855 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr, 1856 sizeof(eaddr)); 1857 1858 printf(", address %s\n", ether_sprintf(eaddr)); 1859 1860 bcopy(eaddr, (char *)&sc->ure_ac.ac_enaddr, ETHER_ADDR_LEN); 1861 1862 ifp = &sc->ure_ac.ac_if; 1863 ifp->if_softc = sc; 1864 strlcpy(ifp->if_xname, sc->ure_dev.dv_xname, IFNAMSIZ); 1865 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1866 ifp->if_ioctl = ure_ioctl; 1867 ifp->if_start = ure_start; 1868 ifp->if_watchdog = ure_watchdog; 1869 1870 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 | 1871 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1872 1873 #if NVLAN > 0 1874 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1875 #endif 1876 1877 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1878 ifmedia_init(&sc->ure_ifmedia, IFM_IMASK, ure_ifmedia_upd, 1879 ure_ifmedia_sts); 1880 ure_add_media_types(sc); 1881 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1882 ifmedia_set(&sc->ure_ifmedia, IFM_ETHER | IFM_AUTO); 1883 sc->ure_ifmedia.ifm_media = sc->ure_ifmedia.ifm_cur->ifm_media; 1884 } else { 1885 rw_init(&sc->ure_mii_lock, "uremii"); 1886 1887 sc->ure_mii.mii_ifp = ifp; 1888 sc->ure_mii.mii_readreg = ure_miibus_readreg; 1889 sc->ure_mii.mii_writereg = ure_miibus_writereg; 1890 sc->ure_mii.mii_statchg = ure_miibus_statchg; 1891 sc->ure_mii.mii_flags = MIIF_AUTOTSLEEP; 1892 1893 ifmedia_init(&sc->ure_mii.mii_media, 0, ure_ifmedia_upd, 1894 ure_ifmedia_sts); 1895 if (!(sc->ure_flags & URE_FLAG_8152)) 1896 mii_flags |= MIIF_DOPAUSE; 1897 mii_attach(self, &sc->ure_mii, 0xffffffff, sc->ure_phyno, 1898 MII_OFFSET_ANY, mii_flags); 1899 if (LIST_FIRST(&sc->ure_mii.mii_phys) == NULL) { 1900 ifmedia_add(&sc->ure_mii.mii_media, 1901 IFM_ETHER | IFM_NONE, 0, NULL); 1902 ifmedia_set(&sc->ure_mii.mii_media, 1903 IFM_ETHER | IFM_NONE); 1904 } else 1905 ifmedia_set(&sc->ure_mii.mii_media, 1906 IFM_ETHER | IFM_AUTO); 1907 } 1908 1909 if_attach(ifp); 1910 ether_ifattach(ifp); 1911 1912 timeout_set(&sc->ure_stat_ch, ure_tick, sc); 1913 1914 splx(s); 1915 } 1916 1917 int 1918 ure_detach(struct device *self, int flags) 1919 { 1920 struct ure_softc *sc = (struct ure_softc *)self; 1921 struct ifnet *ifp = &sc->ure_ac.ac_if; 1922 int s; 1923 1924 if (timeout_initialized(&sc->ure_stat_ch)) 1925 timeout_del(&sc->ure_stat_ch); 1926 1927 if (sc->ure_ep[URE_ENDPT_TX] != NULL) 1928 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_TX]); 1929 if (sc->ure_ep[URE_ENDPT_RX] != NULL) 1930 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_RX]); 1931 1932 usb_rem_task(sc->ure_udev, &sc->ure_tick_task); 1933 1934 s = splusb(); 1935 1936 if (--sc->ure_refcnt >= 0) { 1937 usb_detach_wait(&sc->ure_dev); 1938 } 1939 1940 if (ifp->if_flags & IFF_RUNNING) 1941 ure_stop(sc); 1942 1943 mii_detach(&sc->ure_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1944 ifmedia_delete_instance(&sc->ure_mii.mii_media, IFM_INST_ANY); 1945 if (ifp->if_softc != NULL) { 1946 ether_ifdetach(ifp); 1947 if_detach(ifp); 1948 } 1949 1950 splx(s); 1951 1952 return 0; 1953 } 1954 1955 void 1956 ure_tick_task(void *xsc) 1957 { 1958 struct ure_softc *sc = xsc; 1959 struct mii_data *mii; 1960 int s; 1961 1962 if (sc == NULL) 1963 return; 1964 1965 if (usbd_is_dying(sc->ure_udev)) 1966 return; 1967 mii = &sc->ure_mii; 1968 1969 s = splnet(); 1970 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) 1971 ure_link_state(sc); 1972 else { 1973 mii_tick(mii); 1974 if ((sc->ure_flags & URE_FLAG_LINK) == 0) 1975 ure_miibus_statchg(&sc->ure_dev); 1976 } 1977 timeout_add_sec(&sc->ure_stat_ch, 1); 1978 splx(s); 1979 } 1980 1981 void 1982 ure_lock_mii(struct ure_softc *sc) 1983 { 1984 sc->ure_refcnt++; 1985 rw_enter_write(&sc->ure_mii_lock); 1986 } 1987 1988 void 1989 ure_unlock_mii(struct ure_softc *sc) 1990 { 1991 rw_exit_write(&sc->ure_mii_lock); 1992 if (--sc->ure_refcnt < 0) 1993 usb_detach_wakeup(&sc->ure_dev); 1994 } 1995 1996 void 1997 ure_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1998 { 1999 struct ure_chain *c = (struct ure_chain *)priv; 2000 struct ure_softc *sc = c->uc_sc; 2001 struct ifnet *ifp = &sc->ure_ac.ac_if; 2002 u_char *buf = c->uc_buf; 2003 uint32_t cflags, rxvlan, total_len; 2004 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 2005 struct mbuf *m; 2006 int pktlen = 0, s; 2007 struct ure_rxpkt rxhdr; 2008 2009 if (usbd_is_dying(sc->ure_udev)) 2010 return; 2011 2012 if (!(ifp->if_flags & IFF_RUNNING)) 2013 return; 2014 2015 if (status != USBD_NORMAL_COMPLETION) { 2016 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2017 return; 2018 if (usbd_ratecheck(&sc->ure_rx_notice)) { 2019 printf("%s: usb errors on rx: %s\n", 2020 sc->ure_dev.dv_xname, usbd_errstr(status)); 2021 } 2022 if (status == USBD_STALLED) 2023 usbd_clear_endpoint_stall_async( 2024 sc->ure_ep[URE_ENDPT_RX]); 2025 goto done; 2026 } 2027 2028 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL); 2029 DPRINTFN(3, ("received %d bytes\n", total_len)); 2030 2031 do { 2032 if (total_len < sizeof(rxhdr)) { 2033 DPRINTF(("too few bytes left for a packet header\n")); 2034 ifp->if_ierrors++; 2035 goto done; 2036 } 2037 2038 buf += roundup(pktlen, URE_RX_BUF_ALIGN); 2039 2040 memcpy(&rxhdr, buf, sizeof(rxhdr)); 2041 total_len -= sizeof(rxhdr); 2042 2043 pktlen = letoh32(rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK; 2044 DPRINTFN(4, ("next packet is %d bytes\n", pktlen)); 2045 if (pktlen > total_len) { 2046 DPRINTF(("not enough bytes left for next packet\n")); 2047 ifp->if_ierrors++; 2048 goto done; 2049 } 2050 2051 total_len -= roundup(pktlen, URE_RX_BUF_ALIGN); 2052 buf += sizeof(rxhdr); 2053 2054 m = m_devget(buf, pktlen - ETHER_CRC_LEN, ETHER_ALIGN); 2055 if (m == NULL) { 2056 DPRINTF(("unable to allocate mbuf for next packet\n")); 2057 ifp->if_ierrors++; 2058 goto done; 2059 } 2060 2061 cflags = letoh32(rxhdr.ure_csum); 2062 rxvlan = letoh32(rxhdr.ure_vlan); 2063 2064 /* Check IP header checksum. */ 2065 if ((rxvlan & URE_RXPKT_IPV4) && 2066 !(cflags & URE_RXPKT_IPSUMBAD)) 2067 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 2068 2069 /* Check TCP/UDP checksum. */ 2070 if ((rxvlan & (URE_RXPKT_IPV4 | URE_RXPKT_IPV6)) && 2071 (((rxvlan & URE_RXPKT_TCP) && 2072 !(cflags & URE_RXPKT_TCPSUMBAD)) || 2073 ((rxvlan & URE_RXPKT_UDP) && 2074 !(cflags & URE_RXPKT_UDPSUMBAD)))) 2075 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | 2076 M_UDP_CSUM_IN_OK; 2077 #if NVLAN > 0 2078 if (rxvlan & URE_RXPKT_VLAN_TAG) { 2079 m->m_pkthdr.ether_vtag = 2080 swap16(rxvlan & URE_RXPKT_VLAN_DATA); 2081 m->m_flags |= M_VLANTAG; 2082 } 2083 #endif 2084 2085 ml_enqueue(&ml, m); 2086 } while (total_len > 0); 2087 2088 done: 2089 s = splnet(); 2090 if_input(ifp, &ml); 2091 splx(s); 2092 memset(c->uc_buf, 0, sc->ure_rxbufsz); 2093 2094 usbd_setup_xfer(xfer, sc->ure_ep[URE_ENDPT_RX], c, c->uc_buf, 2095 sc->ure_rxbufsz, USBD_SHORT_XFER_OK | USBD_NO_COPY, 2096 USBD_NO_TIMEOUT, ure_rxeof); 2097 usbd_transfer(xfer); 2098 } 2099 2100 2101 void 2102 ure_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2103 { 2104 struct ure_softc *sc; 2105 struct ure_chain *c; 2106 struct ifnet *ifp; 2107 int s; 2108 2109 c = priv; 2110 sc = c->uc_sc; 2111 ifp = &sc->ure_ac.ac_if; 2112 2113 if (usbd_is_dying(sc->ure_udev)) 2114 return; 2115 2116 if (status != USBD_NORMAL_COMPLETION) 2117 DPRINTF(("%s: %s uc_idx=%u : %s\n", sc->ure_dev.dv_xname, 2118 __func__, c->uc_idx, usbd_errstr(status))); 2119 2120 s = splnet(); 2121 2122 c->uc_cnt = 0; 2123 c->uc_buflen = 0; 2124 2125 SLIST_INSERT_HEAD(&sc->ure_cdata.ure_tx_free, c, uc_list); 2126 2127 if (status != USBD_NORMAL_COMPLETION) { 2128 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) { 2129 splx(s); 2130 return; 2131 } 2132 2133 ifp->if_oerrors++; 2134 printf("%s: usb error on tx: %s\n", sc->ure_dev.dv_xname, 2135 usbd_errstr(status)); 2136 2137 if (status == USBD_STALLED) 2138 usbd_clear_endpoint_stall_async( 2139 sc->ure_ep[URE_ENDPT_TX]); 2140 splx(s); 2141 return; 2142 } 2143 2144 ifp->if_timer = 0; 2145 if (ifq_is_oactive(&ifp->if_snd)) 2146 ifq_restart(&ifp->if_snd); 2147 splx(s); 2148 } 2149 2150 int 2151 ure_encap_txpkt(struct mbuf *m, char *buf, uint32_t maxlen) 2152 { 2153 struct ure_txpkt txhdr; 2154 uint32_t len = sizeof(txhdr), cflags = 0; 2155 2156 if (len + m->m_pkthdr.len > maxlen) 2157 return (-1); 2158 2159 if ((m->m_pkthdr.csum_flags & 2160 (M_IPV4_CSUM_OUT | M_TCP_CSUM_OUT | M_UDP_CSUM_OUT)) != 0) { 2161 cflags |= URE_TXPKT_IPV4; 2162 if (m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) 2163 cflags |= URE_TXPKT_TCP; 2164 if (m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) 2165 cflags |= URE_TXPKT_UDP; 2166 } 2167 2168 #if NVLAN > 0 2169 if (m->m_flags & M_VLANTAG) 2170 cflags |= URE_TXPKT_VLAN_TAG | swap16(m->m_pkthdr.ether_vtag); 2171 #endif 2172 2173 txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS | 2174 URE_TXPKT_TX_LS); 2175 txhdr.ure_vlan = htole32(cflags); 2176 memcpy(buf, &txhdr, len); 2177 2178 m_copydata(m, 0, m->m_pkthdr.len, buf + len); 2179 len += m->m_pkthdr.len; 2180 2181 return (len); 2182 } 2183 2184 int 2185 ure_encap_xfer(struct ifnet *ifp, struct ure_softc *sc, struct ure_chain *c) 2186 { 2187 usbd_status err; 2188 2189 usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_TX], c, c->uc_buf, 2190 c->uc_buflen, USBD_FORCE_SHORT_XFER | USBD_NO_COPY, 10000, 2191 ure_txeof); 2192 2193 err = usbd_transfer(c->uc_xfer); 2194 if (err != USBD_IN_PROGRESS) { 2195 c->uc_cnt = 0; 2196 c->uc_buflen = 0; 2197 ure_stop(sc); 2198 return (EIO); 2199 } 2200 2201 return (0); 2202 } 2203