1 /* $OpenBSD: if_ure.c,v 1.2 2016/08/07 00:21:57 jmatthew Exp $ */ 2 /*- 3 * Copyright (c) 2015 Kevin Lo <kevlo@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include "bpfilter.h" 29 30 #include <sys/cdefs.h> 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/sockio.h> 35 #include <sys/rwlock.h> 36 #include <sys/mbuf.h> 37 #include <sys/kernel.h> 38 #include <sys/socket.h> 39 #include <sys/device.h> 40 41 #include <machine/bus.h> 42 43 #include <net/if.h> 44 #include <net/if_media.h> 45 46 #if NBPFILTER > 0 47 #include <net/bpf.h> 48 #endif 49 50 #include <netinet/in.h> 51 #include <netinet/if_ether.h> 52 53 #include <dev/mii/miivar.h> 54 55 #include <dev/usb/usb.h> 56 #include <dev/usb/usbdi.h> 57 #include <dev/usb/usbdi_util.h> 58 #include <dev/usb/usbdivar.h> 59 #include <dev/usb/usbdevs.h> 60 61 #include "if_urereg.h" 62 63 #ifdef URE_DEBUG 64 #define DPRINTF(x) do { if (uredebug) printf x; } while (0) 65 #define DPRINTFN(n,x) do { if (uredebug >= (n)) printf x; } while (0) 66 int uredebug = 0; 67 #else 68 #define DPRINTF(x) 69 #define DPRINTFN(n,x) 70 #endif 71 72 73 const struct usb_devno ure_devs[] = { 74 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 } 75 }; 76 77 int ure_match(struct device *, void *, void *); 78 void ure_attach(struct device *, struct device *, void *); 79 int ure_detach(struct device *, int); 80 81 struct cfdriver ure_cd = { 82 NULL, "ure", DV_IFNET 83 }; 84 85 const struct cfattach ure_ca = { 86 sizeof(struct ure_softc), ure_match, ure_attach, ure_detach 87 }; 88 89 int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t, 90 void *, int); 91 int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *, 92 int); 93 int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *, 94 int); 95 uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t); 96 uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t); 97 uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t); 98 int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t); 99 int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t); 100 int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t); 101 uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t); 102 void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t); 103 104 void ure_init(void *); 105 void ure_stop(struct ure_softc *); 106 void ure_start(struct ifnet *); 107 void ure_reset(struct ure_softc *); 108 109 void ure_miibus_statchg(struct device *); 110 int ure_miibus_readreg(struct device *, int, int); 111 void ure_miibus_writereg(struct device *, int, int, int); 112 void ure_lock_mii(struct ure_softc *); 113 void ure_unlock_mii(struct ure_softc *); 114 115 int ure_encap(struct ure_softc *, struct mbuf *, int); 116 void ure_rxeof(struct usbd_xfer *, void *, usbd_status); 117 void ure_txeof(struct usbd_xfer *, void *, usbd_status); 118 int ure_rx_list_init(struct ure_softc *); 119 int ure_tx_list_init(struct ure_softc *); 120 struct mbuf * ure_newbuf(void); 121 122 void ure_tick_task(void *); 123 void ure_tick(void *); 124 125 int ure_ifmedia_upd(struct ifnet *); 126 void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *); 127 int ure_ioctl(struct ifnet *, u_long, caddr_t); 128 void ure_rtl8152_init(struct ure_softc *); 129 void ure_disable_teredo(struct ure_softc *); 130 void ure_init_fifo(struct ure_softc *); 131 132 133 134 int 135 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index, 136 void *buf, int len) 137 { 138 usb_device_request_t req; 139 usbd_status err; 140 141 if (usbd_is_dying(sc->ure_udev)) 142 return 0; 143 144 if (rw == URE_CTL_WRITE) 145 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 146 else 147 req.bmRequestType = UT_READ_VENDOR_DEVICE; 148 req.bRequest = UR_SET_ADDRESS; 149 USETW(req.wValue, val); 150 USETW(req.wIndex, index); 151 USETW(req.wLength, len); 152 153 DPRINTFN(5, ("ure_ctl: rw %d, val 0x%04hu, index 0x%04hu, len %d\n", 154 rw, val, index, len)); 155 err = usbd_do_request(sc->ure_udev, &req, buf); 156 if (err) { 157 DPRINTF(("ure_ctl: error %d\n", err)); 158 return -1; 159 } 160 161 return 0; 162 } 163 164 int 165 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 166 void *buf, int len) 167 { 168 169 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len)); 170 } 171 172 int 173 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 174 void *buf, int len) 175 { 176 177 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len)); 178 } 179 180 uint8_t 181 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index) 182 { 183 uint32_t val; 184 uint8_t temp[4]; 185 uint8_t shift; 186 187 shift = (reg & 3) << 3; 188 reg &= ~3; 189 190 ure_read_mem(sc, reg, index, &temp, 4); 191 val = UGETDW(temp); 192 val >>= shift; 193 194 return (val & 0xff); 195 } 196 197 uint16_t 198 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index) 199 { 200 uint32_t val; 201 uint8_t temp[4]; 202 uint8_t shift; 203 204 shift = (reg & 2) << 3; 205 reg &= ~3; 206 207 ure_read_mem(sc, reg, index, &temp, 4); 208 val = UGETDW(temp); 209 val >>= shift; 210 211 return (val & 0xffff); 212 } 213 214 uint32_t 215 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index) 216 { 217 uint8_t temp[4]; 218 219 ure_read_mem(sc, reg, index, &temp, 4); 220 return (UGETDW(temp)); 221 } 222 223 int 224 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 225 { 226 uint16_t byen; 227 uint8_t temp[4]; 228 uint8_t shift; 229 230 byen = URE_BYTE_EN_BYTE; 231 shift = reg & 3; 232 val &= 0xff; 233 234 if (reg & 3) { 235 byen <<= shift; 236 val <<= (shift << 3); 237 reg &= ~3; 238 } 239 240 USETDW(temp, val); 241 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 242 } 243 244 int 245 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 246 { 247 uint16_t byen; 248 uint8_t temp[4]; 249 uint8_t shift; 250 251 byen = URE_BYTE_EN_WORD; 252 shift = reg & 2; 253 val &= 0xffff; 254 255 if (reg & 2) { 256 byen <<= shift; 257 val <<= (shift << 3); 258 reg &= ~3; 259 } 260 261 USETDW(temp, val); 262 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 263 } 264 265 int 266 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 267 { 268 uint8_t temp[4]; 269 270 USETDW(temp, val); 271 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4)); 272 } 273 274 uint16_t 275 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr) 276 { 277 uint16_t reg; 278 279 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 280 reg = (addr & 0x0fff) | 0xb000; 281 282 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA)); 283 } 284 285 void 286 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 287 { 288 uint16_t reg; 289 290 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 291 reg = (addr & 0x0fff) | 0xb000; 292 293 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data); 294 } 295 296 int 297 ure_miibus_readreg(struct device *dev, int phy, int reg) 298 { 299 struct ure_softc *sc = (void *)dev; 300 uint16_t val; 301 302 if (usbd_is_dying(sc->ure_udev)) 303 return 0; 304 305 ure_lock_mii(sc); 306 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2); 307 ure_unlock_mii(sc); 308 309 return val; /* letoh16? */ 310 } 311 312 void 313 ure_miibus_writereg(struct device *dev, int phy, int reg, int val) 314 { 315 struct ure_softc *sc = (void *)dev; 316 317 ure_lock_mii(sc); 318 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val); /* htole16? */ 319 ure_unlock_mii(sc); 320 } 321 322 void 323 ure_miibus_statchg(struct device *dev) 324 { 325 struct ure_softc *sc = (void *)dev; 326 struct mii_data *mii = &sc->ure_mii; 327 struct ifnet *ifp = &sc->ure_ac.ac_if; 328 329 if ((ifp->if_flags & IFF_RUNNING) == 0) 330 return; 331 332 sc->ure_flags &= ~URE_FLAG_LINK; 333 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 334 (IFM_ACTIVE | IFM_AVALID)) { 335 switch (IFM_SUBTYPE(mii->mii_media_active)) { 336 case IFM_10_T: 337 case IFM_100_TX: 338 sc->ure_flags |= URE_FLAG_LINK; 339 break; 340 default: 341 break; 342 } 343 } 344 } 345 346 int 347 ure_ifmedia_upd(struct ifnet *ifp) 348 { 349 struct ure_softc *sc = ifp->if_softc; 350 struct mii_data *mii = &sc->ure_mii; 351 int err; 352 353 sc->ure_flags &= ~URE_FLAG_LINK; 354 if (mii->mii_instance) { 355 struct mii_softc *miisc; 356 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 357 PHY_RESET(miisc); 358 } 359 360 err = mii_mediachg(mii); 361 if (err == ENXIO) 362 return 0; 363 else 364 return err; 365 } 366 367 void 368 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 369 { 370 struct ure_softc *sc = ifp->if_softc; 371 struct mii_data *mii = &sc->ure_mii; 372 373 mii_pollstat(mii); 374 ifmr->ifm_active = mii->mii_media_active; 375 ifmr->ifm_status = mii->mii_media_status; 376 } 377 378 void 379 ure_iff(struct ure_softc *sc) 380 { 381 struct ifnet *ifp = &sc->ure_ac.ac_if; 382 struct ether_multi *enm; 383 struct ether_multistep step; 384 uint32_t hashes[2] = { 0, 0 }; 385 uint32_t hash; 386 uint32_t rxmode; 387 388 if (usbd_is_dying(sc->ure_udev)) 389 return; 390 391 ifp->if_flags &= ~IFF_ALLMULTI; 392 rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA); 393 if (ifp->if_flags & IFF_PROMISC || sc->ure_ac.ac_multirangecnt > 0) { 394 ifp->if_flags |= IFF_ALLMULTI; 395 if (ifp->if_flags & IFF_PROMISC) 396 rxmode |= URE_RCR_AAP; 397 rxmode |= URE_RCR_AM; 398 hashes[0] = hashes[1] = 0xffffffff; 399 } else { 400 ETHER_FIRST_MULTI(step, &sc->ure_ac, enm); 401 while (enm != NULL) { 402 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) 403 >> 26; 404 if (hash < 32) 405 hashes[0] |= (1 << hash); 406 else 407 hashes[1] |= (1 << (hash - 32)); 408 409 ETHER_NEXT_MULTI(step, enm); 410 } 411 412 hash = swap32(hashes[0]); 413 hashes[0] = swap32(hashes[1]); 414 hashes[1] = hash; 415 rxmode |= URE_RCR_AM; 416 } 417 418 ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]); 419 ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]); 420 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 421 } 422 423 void 424 ure_reset(struct ure_softc *sc) 425 { 426 int i; 427 428 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 429 430 for (i = 0; i < URE_TIMEOUT; i++) { 431 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) & 432 URE_CR_RST)) 433 break; 434 usbd_delay_ms(sc->ure_udev, 10); 435 } 436 if (i == URE_TIMEOUT) 437 printf("%s: reset never completed\n", sc->ure_dev.dv_xname); 438 } 439 440 void 441 ure_init(void *xsc) 442 { 443 struct ure_softc *sc = xsc; 444 struct ure_chain *c; 445 struct ifnet *ifp = &sc->ure_ac.ac_if; 446 uint32_t rxmode; 447 usbd_status err; 448 int s, i; 449 450 s = splnet(); 451 452 /* Cancel pending I/O. */ 453 ure_stop(sc); 454 455 ure_reset(sc); 456 457 if (ure_rx_list_init(sc) == ENOBUFS) { 458 printf("%s: rx list init failed\n", sc->ure_dev.dv_xname); 459 splx(s); 460 return; 461 } 462 463 if (ure_tx_list_init(sc) == ENOBUFS) { 464 printf("%s: tx list init failed\n", sc->ure_dev.dv_xname); 465 splx(s); 466 return; 467 } 468 469 /* Set MAC address. */ 470 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 471 sc->ure_ac.ac_enaddr, 8); 472 473 /* Reset the packet filter. */ 474 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, 475 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) & 476 ~URE_FMC_FCR_MCU_EN); 477 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, 478 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) | 479 URE_FMC_FCR_MCU_EN); 480 481 /* Enable transmit and receive. */ 482 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 483 ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | 484 URE_CR_TE); 485 486 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 487 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & 488 ~URE_RXDY_GATED_EN); 489 490 /* Set Rx mode. */ 491 rxmode = URE_RCR_APM; 492 493 /* If we want promiscuous mode, set the allframes bit. */ 494 if (ifp->if_flags & IFF_PROMISC) 495 rxmode |= URE_RCR_AAP; 496 497 if (ifp->if_flags & IFF_BROADCAST) 498 rxmode |= URE_RCR_AB; 499 500 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 501 502 /* Load the multicast filter. */ 503 ure_iff(sc); 504 505 /* Open RX and TX pipes. */ 506 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_RX], 507 USBD_EXCLUSIVE_USE, &sc->ure_ep[URE_ENDPT_RX]); 508 if (err) { 509 printf("%s: open rx pipe failed: %s\n", 510 sc->ure_dev.dv_xname, usbd_errstr(err)); 511 splx(s); 512 return; 513 } 514 515 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_TX], 516 USBD_EXCLUSIVE_USE, &sc->ure_ep[URE_ENDPT_TX]); 517 if (err) { 518 printf("%s: open tx pipe failed: %s\n", 519 sc->ure_dev.dv_xname, usbd_errstr(err)); 520 splx(s); 521 return; 522 } 523 524 /* Start up the receive pipe. */ 525 for (i = 0; i < URE_RX_LIST_CNT; i++) { 526 c = &sc->ure_cdata.rx_chain[i]; 527 usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_RX], 528 c, c->uc_buf, sc->ure_bufsz, 529 USBD_SHORT_XFER_OK | USBD_NO_COPY, 530 USBD_NO_TIMEOUT, ure_rxeof); 531 usbd_transfer(c->uc_xfer); 532 } 533 534 /* Indicate we are up and running. */ 535 ifp->if_flags |= IFF_RUNNING; 536 ifq_clr_oactive(&ifp->if_snd); 537 538 timeout_add_sec(&sc->ure_stat_ch, 1); 539 540 splx(s); 541 } 542 543 void 544 ure_start(struct ifnet *ifp) 545 { 546 struct ure_softc *sc = ifp->if_softc; 547 struct mbuf *m_head = NULL; 548 549 if ((sc->ure_flags & URE_FLAG_LINK) == 0 || 550 ifq_is_oactive(&ifp->if_snd)) { 551 return; 552 } 553 554 m_head = ifq_deq_begin(&ifp->if_snd); 555 if (m_head == NULL) { 556 return; 557 } 558 559 if (ure_encap(sc, m_head, 0)) { 560 ifq_deq_rollback(&ifp->if_snd, m_head); 561 ifq_set_oactive(&ifp->if_snd); 562 return; 563 } 564 ifq_deq_commit(&ifp->if_snd, m_head); 565 566 #if NBPFILTER > 0 567 if (ifp->if_bpf) 568 bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 569 #endif 570 ifq_set_oactive(&ifp->if_snd); 571 } 572 573 void 574 ure_tick(void *xsc) 575 { 576 struct ure_softc *sc = xsc; 577 578 if (sc == NULL) 579 return; 580 581 if (usbd_is_dying(sc->ure_udev)) 582 return; 583 584 usb_add_task(sc->ure_udev, &sc->ure_tick_task); 585 } 586 587 void 588 ure_stop(struct ure_softc *sc) 589 { 590 usbd_status err; 591 struct ifnet *ifp; 592 int i; 593 594 ure_reset(sc); 595 596 ifp = &sc->ure_ac.ac_if; 597 ifp->if_timer = 0; 598 ifp->if_flags &= ~IFF_RUNNING; 599 ifq_clr_oactive(&ifp->if_snd); 600 601 timeout_del(&sc->ure_stat_ch); 602 603 if (sc->ure_ep[URE_ENDPT_RX] != NULL) { 604 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_RX]); 605 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_RX]); 606 if (err) { 607 printf("%s: close rx pipe failed: %s\n", 608 sc->ure_dev.dv_xname, usbd_errstr(err)); 609 } 610 sc->ure_ep[URE_ENDPT_RX] = NULL; 611 } 612 613 if (sc->ure_ep[URE_ENDPT_TX] != NULL) { 614 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_TX]); 615 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_TX]); 616 if (err) { 617 printf("%s: close tx pipe failed: %s\n", 618 sc->ure_dev.dv_xname, usbd_errstr(err)); 619 } 620 sc->ure_ep[URE_ENDPT_TX] = NULL; 621 } 622 623 for (i = 0; i < URE_RX_LIST_CNT; i++) { 624 if (sc->ure_cdata.rx_chain[i].uc_mbuf != NULL) { 625 m_freem(sc->ure_cdata.rx_chain[i].uc_mbuf); 626 sc->ure_cdata.rx_chain[i].uc_mbuf = NULL; 627 } 628 if (sc->ure_cdata.rx_chain[i].uc_xfer != NULL) { 629 usbd_free_xfer(sc->ure_cdata.rx_chain[i].uc_xfer); 630 sc->ure_cdata.rx_chain[i].uc_xfer = NULL; 631 } 632 } 633 634 for (i = 0; i < URE_TX_LIST_CNT; i++) { 635 if (sc->ure_cdata.tx_chain[i].uc_mbuf != NULL) { 636 m_freem(sc->ure_cdata.tx_chain[i].uc_mbuf); 637 sc->ure_cdata.tx_chain[i].uc_mbuf = NULL; 638 } 639 if (sc->ure_cdata.tx_chain[i].uc_xfer != NULL) { 640 usbd_free_xfer(sc->ure_cdata.tx_chain[i].uc_xfer); 641 sc->ure_cdata.tx_chain[i].uc_xfer = NULL; 642 } 643 } 644 } 645 646 void 647 ure_rtl8152_init(struct ure_softc *sc) 648 { 649 uint32_t pwrctrl; 650 651 /* Disable ALDPS. */ 652 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 653 URE_DIS_SDSAVE); 654 usbd_delay_ms(sc->ure_udev, 20); 655 656 if (sc->ure_chip & URE_CHIP_VER_4C00) { 657 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 658 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 659 ~URE_LED_MODE_MASK); 660 } 661 662 ure_write_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, 663 ure_read_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & 664 ~URE_POWER_CUT); 665 ure_write_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 666 ure_read_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & 667 ~URE_RESUME_INDICATE); 668 669 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 670 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 671 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 672 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 673 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 674 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 675 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 676 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 677 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 678 URE_SPDWN_LINKCHG_MSK); 679 680 /* Disable Rx aggregation. */ 681 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 682 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) | 683 URE_RX_AGG_DISABLE); 684 685 /* Disable ALDPS. */ 686 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 687 URE_DIS_SDSAVE); 688 usbd_delay_ms(sc->ure_udev, 20); 689 690 ure_init_fifo(sc); 691 692 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 693 URE_TX_AGG_MAX_THRESHOLD); 694 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 695 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 696 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 697 } 698 699 void 700 ure_disable_teredo(struct ure_softc *sc) 701 { 702 ure_write_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 703 ure_read_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & 704 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 705 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, 706 URE_WDT6_SET_MODE); 707 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 708 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 709 } 710 711 void 712 ure_init_fifo(struct ure_softc *sc) 713 { 714 uint32_t rx_fifo1, rx_fifo2; 715 int i; 716 717 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 718 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | 719 URE_RXDY_GATED_EN); 720 721 ure_disable_teredo(sc); 722 723 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, 724 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA) & 725 ~URE_RCR_ACPT_ALL); 726 727 ure_reset(sc); 728 729 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 730 731 ure_write_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, 732 ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 733 ~URE_NOW_IS_OOB); 734 735 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 736 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & 737 ~URE_MCU_BORW_EN); 738 for (i = 0; i < URE_TIMEOUT; i++) { 739 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 740 URE_LINK_LIST_READY) 741 break; 742 usbd_delay_ms(sc->ure_udev, 10); 743 } 744 if (i == URE_TIMEOUT) 745 printf("%s timeout waiting for OOB control\n", 746 sc->ure_dev.dv_xname); 747 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 748 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | 749 URE_RE_INIT_LL); 750 for (i = 0; i < URE_TIMEOUT; i++) { 751 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 752 URE_LINK_LIST_READY) 753 break; 754 usbd_delay_ms(sc->ure_udev, 10); 755 } 756 if (i == URE_TIMEOUT) 757 printf("%s: timeout waiting for OOB control\n", 758 sc->ure_dev.dv_xname); 759 760 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 761 ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & 762 ~URE_CPCR_RX_VLAN); 763 ure_write_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 764 ure_read_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | 765 URE_TCR0_AUTO_FIFO); 766 767 /* Configure Rx FIFO threshold and coalescing. */ 768 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 769 URE_RXFIFO_THR1_NORMAL); 770 if (sc->ure_udev->speed == USB_SPEED_FULL) { 771 rx_fifo1 = URE_RXFIFO_THR2_FULL; 772 rx_fifo2 = URE_RXFIFO_THR3_FULL; 773 } else { 774 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 775 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 776 } 777 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 778 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 779 780 /* Configure Tx FIFO threshold. */ 781 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 782 URE_TXFIFO_THR_NORMAL); 783 } 784 785 int 786 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 787 { 788 struct ure_softc *sc = ifp->if_softc;; 789 struct ifreq *ifr = (struct ifreq *)data; 790 int s, error = 0; 791 792 s = splnet(); 793 794 switch (cmd) { 795 case SIOCSIFADDR: 796 ifp->if_flags |= IFF_UP; 797 if (!(ifp->if_flags & IFF_RUNNING)) 798 ure_init(sc); 799 break; 800 801 case SIOCSIFFLAGS: 802 if (ifp->if_flags & IFF_UP) { 803 if (ifp->if_flags & IFF_RUNNING) 804 error = ENETRESET; 805 else 806 ure_init(sc); 807 } else { 808 if (ifp->if_flags & IFF_RUNNING) 809 ure_stop(sc); 810 } 811 break; 812 813 case SIOCGIFMEDIA: 814 case SIOCSIFMEDIA: 815 error = ifmedia_ioctl(ifp, ifr, &sc->ure_mii.mii_media, cmd); 816 break; 817 818 default: 819 error = ether_ioctl(ifp, &sc->ure_ac, cmd, data); 820 } 821 822 if (error == ENETRESET) { 823 if (ifp->if_flags & IFF_RUNNING) 824 ure_iff(sc); 825 error = 0; 826 } 827 828 splx(s); 829 830 return (error); 831 } 832 833 int 834 ure_match(struct device *parent, void *match, void *aux) 835 { 836 struct usb_attach_arg *uaa = aux; 837 838 /* 839 if (uaa->configno != URE_CONFIG_IDX) 840 return UMATCH_NONE; 841 if (uaa->ifaceno != URE_IFACE_IDX) 842 return UMATCH_NONE; 843 */ 844 if (uaa->iface == NULL || uaa->configno != 1) 845 return UMATCH_NONE; 846 847 return (usb_lookup(ure_devs, uaa->vendor, uaa->product) != NULL ? 848 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 849 } 850 851 void 852 ure_attach(struct device *parent, struct device *self, void *aux) 853 { 854 struct ure_softc *sc = (struct ure_softc *)self; 855 struct usb_attach_arg *uaa = aux; 856 usb_interface_descriptor_t *id; 857 usb_endpoint_descriptor_t *ed; 858 struct mii_data *mii; 859 u_char eaddr[8]; /* 4byte padded */ 860 struct ifnet *ifp; 861 int i, s; 862 uint16_t ver; 863 864 sc->ure_udev = uaa->device; 865 sc->ure_iface = uaa->iface; 866 867 usb_init_task(&sc->ure_tick_task, ure_tick_task, sc, 868 USB_TASK_TYPE_GENERIC); 869 rw_init(&sc->ure_mii_lock, "uremii"); 870 usb_init_task(&sc->ure_stop_task, (void (*)(void *))ure_stop, sc, 871 USB_TASK_TYPE_GENERIC); 872 873 id = usbd_get_interface_descriptor(sc->ure_iface); 874 875 sc->ure_bufsz = 16 * 1024; 876 877 for (i = 0; i < id->bNumEndpoints; i++) { 878 ed = usbd_interface2endpoint_descriptor(sc->ure_iface, i); 879 if (!ed) { 880 printf("%s: couldn't get ep %d\n", 881 sc->ure_dev.dv_xname, i); 882 return; 883 } 884 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 885 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 886 sc->ure_ed[URE_ENDPT_RX] = ed->bEndpointAddress; 887 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 888 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 889 sc->ure_ed[URE_ENDPT_TX] = ed->bEndpointAddress; 890 } 891 } 892 893 s = splnet(); 894 895 sc->ure_phyno = 0; 896 printf("%s: ", sc->ure_dev.dv_xname); 897 898 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 899 switch (ver) { 900 case 0x4c00: 901 sc->ure_chip |= URE_CHIP_VER_4C00; 902 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr, 903 sizeof(eaddr)); 904 printf("ver 4c00"); 905 break; 906 case 0x4c10: 907 sc->ure_chip |= URE_CHIP_VER_4C10; 908 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr, 909 sizeof(eaddr)); 910 printf("ver 4c01"); 911 break; 912 default: 913 printf(", unknown ver %02x", ver); 914 /* fake addr? or just fail? */ 915 break; 916 } 917 918 printf(", address %s\n", ether_sprintf(eaddr)); 919 920 bcopy(eaddr, (char *)&sc->ure_ac.ac_enaddr, ETHER_ADDR_LEN); 921 922 ure_rtl8152_init(sc); 923 924 ifp = &sc->ure_ac.ac_if; 925 ifp->if_softc = sc; 926 strlcpy(ifp->if_xname, sc->ure_dev.dv_xname, IFNAMSIZ); 927 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 928 ifp->if_ioctl = ure_ioctl; 929 ifp->if_start = ure_start; 930 ifp->if_capabilities = 0; 931 932 mii = &sc->ure_mii; 933 mii->mii_ifp = ifp; 934 mii->mii_readreg = ure_miibus_readreg; 935 mii->mii_writereg = ure_miibus_writereg; 936 mii->mii_statchg = ure_miibus_statchg; 937 mii->mii_flags = MIIF_AUTOTSLEEP; 938 939 ifmedia_init(&mii->mii_media, 0, ure_ifmedia_upd, ure_ifmedia_sts); 940 mii_attach(self, mii, 0xffffffff, sc->ure_phyno, MII_OFFSET_ANY, 0); 941 942 if (LIST_FIRST(&mii->mii_phys) == NULL) { 943 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 944 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 945 } else 946 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 947 948 if_attach(ifp); 949 ether_ifattach(ifp); 950 951 timeout_set(&sc->ure_stat_ch, ure_tick, sc); 952 953 splx(s); 954 } 955 956 int 957 ure_detach(struct device *self, int flags) 958 { 959 struct ure_softc *sc = (struct ure_softc *)self; 960 struct ifnet *ifp = &sc->ure_ac.ac_if; 961 int s; 962 963 if (timeout_initialized(&sc->ure_stat_ch)) 964 timeout_del(&sc->ure_stat_ch); 965 966 if (sc->ure_ep[URE_ENDPT_TX] != NULL) 967 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_TX]); 968 if (sc->ure_ep[URE_ENDPT_RX] != NULL) 969 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_RX]); 970 971 usb_rem_task(sc->ure_udev, &sc->ure_tick_task); 972 usb_rem_task(sc->ure_udev, &sc->ure_stop_task); 973 974 s = splusb(); 975 976 if (--sc->ure_refcnt >= 0) { 977 usb_detach_wait(&sc->ure_dev); 978 } 979 980 if (ifp->if_flags & IFF_RUNNING) 981 ure_stop(sc); 982 983 mii_detach(&sc->ure_mii, MII_PHY_ANY, MII_OFFSET_ANY); 984 ifmedia_delete_instance(&sc->ure_mii.mii_media, IFM_INST_ANY); 985 if (ifp->if_softc != NULL) { 986 ether_ifdetach(ifp); 987 if_detach(ifp); 988 } 989 990 splx(s); 991 992 return 0; 993 } 994 995 void 996 ure_tick_task(void *xsc) 997 { 998 int s; 999 struct ure_softc *sc = xsc; 1000 struct mii_data *mii; 1001 1002 if (sc == NULL) 1003 return; 1004 1005 if (usbd_is_dying(sc->ure_udev)) 1006 return; 1007 mii = &sc->ure_mii; 1008 1009 s = splnet(); 1010 mii_tick(mii); 1011 if ((sc->ure_flags & URE_FLAG_LINK) == 0) 1012 ure_miibus_statchg(&sc->ure_dev); 1013 timeout_add_sec(&sc->ure_stat_ch, 1); 1014 splx(s); 1015 } 1016 1017 void 1018 ure_lock_mii(struct ure_softc *sc) 1019 { 1020 sc->ure_refcnt++; 1021 rw_enter_write(&sc->ure_mii_lock); 1022 } 1023 1024 void 1025 ure_unlock_mii(struct ure_softc *sc) 1026 { 1027 rw_exit_write(&sc->ure_mii_lock); 1028 if (--sc->ure_refcnt < 0) 1029 usb_detach_wakeup(&sc->ure_dev); 1030 } 1031 1032 void 1033 ure_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1034 { 1035 struct ure_chain *c = (struct ure_chain *)priv; 1036 struct ure_softc *sc = c->uc_sc; 1037 struct ifnet *ifp = &sc->ure_ac.ac_if; 1038 u_char *buf = c->uc_buf; 1039 uint32_t total_len; 1040 uint16_t pktlen = 0; 1041 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1042 struct mbuf *m; 1043 int s; 1044 struct ure_rxpkt rxhdr; 1045 1046 if (usbd_is_dying(sc->ure_udev)) 1047 return; 1048 1049 if (!(ifp->if_flags & IFF_RUNNING)) 1050 return; 1051 1052 if (status != USBD_NORMAL_COMPLETION) { 1053 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 1054 return; 1055 if (usbd_ratecheck(&sc->ure_rx_notice)) { 1056 printf("%s: usb errors on rx: %s\n", 1057 sc->ure_dev.dv_xname, usbd_errstr(status)); 1058 } 1059 if (status == USBD_STALLED) 1060 usbd_clear_endpoint_stall_async(sc->ure_ep[URE_ENDPT_RX]); 1061 goto done; 1062 } 1063 1064 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL); 1065 DPRINTFN(3, ("received %d bytes\n", total_len)); 1066 1067 do { 1068 if (total_len < sizeof(rxhdr)) { 1069 DPRINTF(("too few bytes left for a packet header\n")); 1070 ifp->if_ierrors++; 1071 goto done; 1072 } 1073 1074 buf += pktlen; 1075 1076 memcpy(&rxhdr, buf, sizeof(rxhdr)); 1077 total_len -= sizeof(rxhdr); 1078 1079 pktlen = lemtoh32(&rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK; 1080 DPRINTFN(4, ("next packet is %d bytes\n", pktlen)); 1081 if (pktlen > total_len) { 1082 DPRINTF(("not enough bytes left for next packet\n")); 1083 ifp->if_ierrors++; 1084 goto done; 1085 } 1086 1087 total_len -= pktlen; 1088 buf += sizeof(rxhdr); 1089 1090 m = ure_newbuf(); 1091 if (m == NULL) { 1092 DPRINTF(("unable to allocate mbuf for next packet\n")); 1093 ifp->if_ierrors++; 1094 goto done; 1095 } 1096 1097 m->m_pkthdr.len = m->m_len = pktlen; 1098 m_adj(m, ETHER_ALIGN); 1099 1100 memcpy(mtod(m, char *), buf, pktlen); 1101 ml_enqueue(&ml, m); 1102 } while (total_len > 0); 1103 1104 done: 1105 s = splnet(); 1106 if_input(ifp, &ml); 1107 splx(s); 1108 memset(c->uc_buf, 0, sc->ure_bufsz); 1109 1110 usbd_setup_xfer(xfer, sc->ure_ep[URE_ENDPT_RX], c, c->uc_buf, 1111 sc->ure_bufsz, USBD_SHORT_XFER_OK | USBD_NO_COPY, 1112 USBD_NO_TIMEOUT, ure_rxeof); 1113 usbd_transfer(xfer); 1114 } 1115 1116 1117 void 1118 ure_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1119 { 1120 struct ure_softc *sc; 1121 struct ure_chain *c; 1122 struct ifnet *ifp; 1123 int s; 1124 1125 c = priv; 1126 sc = c->uc_sc; 1127 ifp = &sc->ure_ac.ac_if; 1128 1129 if (usbd_is_dying(sc->ure_udev)) 1130 return; 1131 1132 DPRINTFN(2, ("tx completion\n")); 1133 1134 s = splnet(); 1135 1136 if (status != USBD_NORMAL_COMPLETION) { 1137 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) { 1138 splx(s); 1139 return; 1140 } 1141 ifp->if_oerrors++; 1142 printf("%s: usb error on tx: %s\n", sc->ure_dev.dv_xname, 1143 usbd_errstr(status)); 1144 if (status == USBD_STALLED) 1145 usbd_clear_endpoint_stall_async(sc->ure_ep[URE_ENDPT_TX]); 1146 splx(s); 1147 return; 1148 } 1149 1150 ifp->if_timer = 0; 1151 ifq_clr_oactive(&ifp->if_snd); 1152 1153 m_freem(c->uc_mbuf); 1154 c->uc_mbuf = NULL; 1155 1156 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 1157 ure_start(ifp); 1158 1159 ifp->if_opackets++; 1160 splx(s); 1161 1162 } 1163 1164 int 1165 ure_tx_list_init(struct ure_softc *sc) 1166 { 1167 struct ure_cdata *cd; 1168 struct ure_chain *c; 1169 int i; 1170 1171 cd = &sc->ure_cdata; 1172 for (i = 0; i < URE_TX_LIST_CNT; i++) { 1173 c = &cd->tx_chain[i]; 1174 c->uc_sc = sc; 1175 c->uc_idx = i; 1176 c->uc_mbuf = NULL; 1177 if (c->uc_xfer == NULL) { 1178 c->uc_xfer = usbd_alloc_xfer(sc->ure_udev); 1179 if (c->uc_xfer == NULL) 1180 return ENOBUFS; 1181 c->uc_buf = usbd_alloc_buffer(c->uc_xfer, 1182 sc->ure_bufsz); 1183 if (c->uc_buf == NULL) { 1184 usbd_free_xfer(c->uc_xfer); 1185 return ENOBUFS; 1186 } 1187 } 1188 } 1189 1190 return 0; 1191 } 1192 1193 int 1194 ure_rx_list_init(struct ure_softc *sc) 1195 { 1196 struct ure_cdata *cd; 1197 struct ure_chain *c; 1198 int i; 1199 1200 cd = &sc->ure_cdata; 1201 for (i = 0; i < URE_RX_LIST_CNT; i++) { 1202 c = &cd->rx_chain[i]; 1203 c->uc_sc = sc; 1204 c->uc_idx = i; 1205 c->uc_mbuf = NULL; 1206 if (c->uc_xfer == NULL) { 1207 c->uc_xfer = usbd_alloc_xfer(sc->ure_udev); 1208 if (c->uc_xfer == NULL) 1209 return ENOBUFS; 1210 c->uc_buf = usbd_alloc_buffer(c->uc_xfer, 1211 sc->ure_bufsz); 1212 if (c->uc_buf == NULL) { 1213 usbd_free_xfer(c->uc_xfer); 1214 return ENOBUFS; 1215 } 1216 } 1217 } 1218 1219 return 0; 1220 } 1221 1222 struct mbuf * 1223 ure_newbuf(void) 1224 { 1225 struct mbuf *m; 1226 1227 MGETHDR(m, M_DONTWAIT, MT_DATA); 1228 if (m == NULL) 1229 return NULL; 1230 1231 MCLGET(m, M_DONTWAIT); 1232 if (!(m->m_flags & M_EXT)) { 1233 m_freem(m); 1234 return NULL; 1235 } 1236 1237 return m; 1238 } 1239 1240 int 1241 ure_encap(struct ure_softc *sc, struct mbuf *m, int idx) 1242 { 1243 struct ure_chain *c; 1244 usbd_status err; 1245 struct ure_txpkt txhdr; 1246 uint32_t frm_len = 0; 1247 u_char *buf; 1248 1249 c = &sc->ure_cdata.tx_chain[idx]; 1250 buf = c->uc_buf; 1251 1252 /* header */ 1253 htolem32(&txhdr.ure_pktlen, m->m_pkthdr.len | URE_TXPKT_TX_FS | 1254 URE_TXPKT_TX_LS); 1255 txhdr.ure_rsvd0 = 0; 1256 memcpy(buf, &txhdr, sizeof(txhdr)); 1257 buf += sizeof(txhdr); 1258 frm_len = sizeof(txhdr); 1259 1260 /* packet */ 1261 m_copydata(m, 0, m->m_pkthdr.len, buf); 1262 frm_len += m->m_pkthdr.len; 1263 1264 c->uc_mbuf = m; 1265 1266 DPRINTFN(2, ("tx %d bytes\n", frm_len)); 1267 usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_TX], c, c->uc_buf, 1268 frm_len, USBD_FORCE_SHORT_XFER | USBD_NO_COPY, 10000, ure_txeof); 1269 1270 err = usbd_transfer(c->uc_xfer); 1271 if (err != USBD_IN_PROGRESS) { 1272 ure_stop(sc); 1273 return EIO; 1274 } 1275 1276 sc->ure_cdata.tx_cnt++; 1277 return 0; 1278 } 1279