1 /* $OpenBSD: if_ure.c,v 1.30 2022/04/02 15:35:06 sthen Exp $ */ 2 /*- 3 * Copyright (c) 2015, 2016, 2019 Kevin Lo <kevlo@openbsd.org> 4 * Copyright (c) 2020 Jonathon Fletcher <jonathon.fletcher@gmail.com> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "bpfilter.h" 30 #include "vlan.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/sockio.h> 35 #include <sys/rwlock.h> 36 #include <sys/mbuf.h> 37 #include <sys/kernel.h> 38 #include <sys/socket.h> 39 #include <sys/device.h> 40 41 #include <machine/bus.h> 42 43 #include <net/if.h> 44 #include <net/if_media.h> 45 46 #if NBPFILTER > 0 47 #include <net/bpf.h> 48 #endif 49 50 #include <netinet/in.h> 51 #include <netinet/if_ether.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 56 #include <dev/usb/usb.h> 57 #include <dev/usb/usbdi.h> 58 #include <dev/usb/usbdi_util.h> 59 #include <dev/usb/usbdivar.h> 60 #include <dev/usb/usbdevs.h> 61 62 #include <dev/ic/rtl81x9reg.h> 63 #include <dev/usb/if_urereg.h> 64 65 #ifdef URE_DEBUG 66 #define DPRINTF(x) do { if (uredebug) printf x; } while (0) 67 #define DPRINTFN(n,x) do { if (uredebug >= (n)) printf x; } while (0) 68 int uredebug = 0; 69 #else 70 #define DPRINTF(x) 71 #define DPRINTFN(n,x) 72 #endif 73 74 const struct usb_devno ure_devs[] = { 75 { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_RTL8156 }, 76 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8152B }, 77 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8153 }, 78 { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB3GIGV1 }, 79 { USB_VENDOR_CLEVO, USB_PRODUCT_CLEVO_RTL8153B }, 80 { USB_VENDOR_CLUB3D, USB_PRODUCT_CLUB3D_RTL8153 }, 81 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8153_1 }, 82 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8153_2 }, 83 { USB_VENDOR_DYNABOOK, USB_PRODUCT_DYNABOOK_RTL8153B_1 }, 84 { USB_VENDOR_DYNABOOK, USB_PRODUCT_DYNABOOK_RTL8153B_2 }, 85 { USB_VENDOR_ELECOM, USB_PRODUCT_ELECOM_RTL8153B }, 86 { USB_VENDOR_ELECOM, USB_PRODUCT_ELECOM_RTL8156B }, 87 { USB_VENDOR_IOI, USB_PRODUCT_IOI_RTL8153 }, 88 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_DOCK_ETHERNET }, 89 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ONELINK }, 90 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ONELINKPLUS }, 91 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ONELINKPRO }, 92 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_1 }, 93 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_2 }, 94 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_3 }, 95 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_4 }, 96 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_5 }, 97 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_6 }, 98 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_7 }, 99 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_8 }, 100 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_9 }, 101 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153_1 }, 102 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153_2 }, 103 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153_3 }, 104 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TABLETDOCK }, 105 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TB3DOCK }, 106 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TB3DOCKGEN2 }, 107 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TB3GFXDOCK }, 108 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_USBCDOCKGEN2 }, 109 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_WIGIGDOCK }, 110 { USB_VENDOR_LG, USB_PRODUCT_LG_RTL8153 }, 111 { USB_VENDOR_LG, USB_PRODUCT_LG_RTL8153B }, 112 { USB_VENDOR_LUXSHARE, USB_PRODUCT_LUXSHARE_RTL8153 }, 113 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_DOCKETH }, 114 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_DOCKETH2 }, 115 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_SURFETH }, 116 { USB_VENDOR_NVIDIA, USB_PRODUCT_NVIDIA_TEGRAETH }, 117 { USB_VENDOR_PIONEERDJ, USB_PRODUCT_PIONEERDJ_RTL8152B }, 118 { USB_VENDOR_PIONEERDJ, USB_PRODUCT_PIONEERDJ_RTL8153B }, 119 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 }, 120 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152B }, 121 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8153 }, 122 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8156 }, 123 { USB_VENDOR_SAMSUNG2, USB_PRODUCT_SAMSUNG2_RTL8153 }, 124 { USB_VENDOR_TOSHIBA, USB_PRODUCT_TOSHIBA_RTL8153B }, 125 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_EU300 }, 126 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_RTL8152B_1 }, 127 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_RTL8152B_2 }, 128 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_RTL8153 }, 129 { USB_VENDOR_TRENDNET, USB_PRODUCT_TRENDNET_RTL8156 }, 130 { USB_VENDOR_TTL, USB_PRODUCT_TTL_RTL8153 }, 131 { USB_VENDOR_TWINHEAD, USB_PRODUCT_TWINHEAD_RTL8153B }, 132 { USB_VENDOR_XIAOMI, USB_PRODUCT_XIAOMI_RTL8152B }, 133 }; 134 135 int ure_match(struct device *, void *, void *); 136 void ure_attach(struct device *, struct device *, void *); 137 int ure_detach(struct device *, int); 138 139 struct cfdriver ure_cd = { 140 NULL, "ure", DV_IFNET 141 }; 142 143 const struct cfattach ure_ca = { 144 sizeof(struct ure_softc), ure_match, ure_attach, ure_detach 145 }; 146 147 int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t, 148 void *, int); 149 int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *, 150 int); 151 int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *, 152 int); 153 uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t); 154 uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t); 155 uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t); 156 int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t); 157 int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t); 158 int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t); 159 uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t); 160 void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t); 161 162 void ure_init(void *); 163 void ure_stop(struct ure_softc *); 164 void ure_start(struct ifnet *); 165 void ure_reset(struct ure_softc *); 166 void ure_watchdog(struct ifnet *); 167 168 void ure_miibus_statchg(struct device *); 169 int ure_miibus_readreg(struct device *, int, int); 170 void ure_miibus_writereg(struct device *, int, int, int); 171 void ure_lock_mii(struct ure_softc *); 172 void ure_unlock_mii(struct ure_softc *); 173 174 int ure_encap_txpkt(struct mbuf *, char *, uint32_t); 175 int ure_encap_xfer(struct ifnet *, struct ure_softc *, 176 struct ure_chain *); 177 void ure_rxeof(struct usbd_xfer *, void *, usbd_status); 178 void ure_txeof(struct usbd_xfer *, void *, usbd_status); 179 int ure_xfer_list_init(struct ure_softc *, struct ure_chain *, 180 uint32_t, int); 181 void ure_xfer_list_free(struct ure_softc *, struct ure_chain *, int); 182 183 void ure_tick_task(void *); 184 void ure_tick(void *); 185 186 void ure_ifmedia_init(struct ifnet *); 187 int ure_ifmedia_upd(struct ifnet *); 188 void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *); 189 void ure_add_media_types(struct ure_softc *); 190 void ure_link_state(struct ure_softc *); 191 int ure_get_link_status(struct ure_softc *); 192 void ure_iff(struct ure_softc *); 193 void ure_rxvlan(struct ure_softc *); 194 int ure_ioctl(struct ifnet *, u_long, caddr_t); 195 void ure_rtl8152_init(struct ure_softc *); 196 void ure_rtl8153_init(struct ure_softc *); 197 void ure_rtl8153b_init(struct ure_softc *); 198 void ure_rtl8152_nic_reset(struct ure_softc *); 199 void ure_rtl8153_nic_reset(struct ure_softc *); 200 uint16_t ure_rtl8153_phy_status(struct ure_softc *, int); 201 void ure_wait_for_flash(struct ure_softc *); 202 void ure_reset_bmu(struct ure_softc *); 203 void ure_disable_teredo(struct ure_softc *); 204 205 #define URE_SETBIT_1(sc, reg, index, x) \ 206 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x)) 207 #define URE_SETBIT_2(sc, reg, index, x) \ 208 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x)) 209 #define URE_SETBIT_4(sc, reg, index, x) \ 210 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x)) 211 212 #define URE_CLRBIT_1(sc, reg, index, x) \ 213 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~(x)) 214 #define URE_CLRBIT_2(sc, reg, index, x) \ 215 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~(x)) 216 #define URE_CLRBIT_4(sc, reg, index, x) \ 217 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~(x)) 218 219 int 220 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index, 221 void *buf, int len) 222 { 223 usb_device_request_t req; 224 usbd_status err; 225 226 if (usbd_is_dying(sc->ure_udev)) 227 return 0; 228 229 if (rw == URE_CTL_WRITE) 230 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 231 else 232 req.bmRequestType = UT_READ_VENDOR_DEVICE; 233 req.bRequest = UR_SET_ADDRESS; 234 USETW(req.wValue, val); 235 USETW(req.wIndex, index); 236 USETW(req.wLength, len); 237 238 DPRINTFN(5, ("ure_ctl: rw %d, val 0x%04hu, index 0x%04hu, len %d\n", 239 rw, val, index, len)); 240 err = usbd_do_request(sc->ure_udev, &req, buf); 241 if (err) { 242 DPRINTF(("ure_ctl: error %d\n", err)); 243 return -1; 244 } 245 246 return 0; 247 } 248 249 int 250 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 251 void *buf, int len) 252 { 253 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len)); 254 } 255 256 int 257 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 258 void *buf, int len) 259 { 260 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len)); 261 } 262 263 uint8_t 264 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index) 265 { 266 uint32_t val; 267 uint8_t temp[4]; 268 uint8_t shift; 269 270 shift = (reg & 3) << 3; 271 reg &= ~3; 272 273 ure_read_mem(sc, reg, index, &temp, 4); 274 val = UGETDW(temp); 275 val >>= shift; 276 277 return (val & 0xff); 278 } 279 280 uint16_t 281 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index) 282 { 283 uint32_t val; 284 uint8_t temp[4]; 285 uint8_t shift; 286 287 shift = (reg & 2) << 3; 288 reg &= ~3; 289 290 ure_read_mem(sc, reg, index, &temp, 4); 291 val = UGETDW(temp); 292 val >>= shift; 293 294 return (val & 0xffff); 295 } 296 297 uint32_t 298 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index) 299 { 300 uint8_t temp[4]; 301 302 ure_read_mem(sc, reg, index, &temp, 4); 303 return (UGETDW(temp)); 304 } 305 306 int 307 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 308 { 309 uint16_t byen; 310 uint8_t temp[4]; 311 uint8_t shift; 312 313 byen = URE_BYTE_EN_BYTE; 314 shift = reg & 3; 315 val &= 0xff; 316 317 if (reg & 3) { 318 byen <<= shift; 319 val <<= (shift << 3); 320 reg &= ~3; 321 } 322 323 USETDW(temp, val); 324 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 325 } 326 327 int 328 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 329 { 330 uint16_t byen; 331 uint8_t temp[4]; 332 uint8_t shift; 333 334 byen = URE_BYTE_EN_WORD; 335 shift = reg & 2; 336 val &= 0xffff; 337 338 if (reg & 2) { 339 byen <<= shift; 340 val <<= (shift << 3); 341 reg &= ~3; 342 } 343 344 USETDW(temp, val); 345 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 346 } 347 348 int 349 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 350 { 351 uint8_t temp[4]; 352 353 USETDW(temp, val); 354 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4)); 355 } 356 357 uint16_t 358 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr) 359 { 360 uint16_t reg; 361 362 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 363 reg = (addr & 0x0fff) | 0xb000; 364 365 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA)); 366 } 367 368 void 369 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 370 { 371 uint16_t reg; 372 373 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 374 reg = (addr & 0x0fff) | 0xb000; 375 376 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data); 377 } 378 379 int 380 ure_miibus_readreg(struct device *dev, int phy, int reg) 381 { 382 struct ure_softc *sc = (void *)dev; 383 uint16_t val; 384 385 if (usbd_is_dying(sc->ure_udev)) 386 return 0; 387 388 /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */ 389 if (reg == RL_GMEDIASTAT) 390 return ure_read_1(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA); 391 392 ure_lock_mii(sc); 393 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2); 394 ure_unlock_mii(sc); 395 396 return val; /* letoh16? */ 397 } 398 399 void 400 ure_miibus_writereg(struct device *dev, int phy, int reg, int val) 401 { 402 struct ure_softc *sc = (void *)dev; 403 404 ure_lock_mii(sc); 405 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val); /* htole16? */ 406 ure_unlock_mii(sc); 407 } 408 409 void 410 ure_miibus_statchg(struct device *dev) 411 { 412 struct ure_softc *sc = (void *)dev; 413 struct mii_data *mii = &sc->ure_mii; 414 struct ifnet *ifp = &sc->ure_ac.ac_if; 415 416 if ((ifp->if_flags & IFF_RUNNING) == 0) 417 return; 418 419 sc->ure_flags &= ~URE_FLAG_LINK; 420 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 421 (IFM_ACTIVE | IFM_AVALID)) { 422 switch (IFM_SUBTYPE(mii->mii_media_active)) { 423 case IFM_10_T: 424 case IFM_100_TX: 425 sc->ure_flags |= URE_FLAG_LINK; 426 break; 427 case IFM_1000_T: 428 if ((sc->ure_flags & URE_FLAG_8152) != 0) 429 break; 430 sc->ure_flags |= URE_FLAG_LINK; 431 break; 432 default: 433 break; 434 } 435 } 436 437 /* Lost link, do nothing. */ 438 if ((sc->ure_flags & URE_FLAG_LINK) == 0) 439 return; 440 441 /* 442 * After a link change the media settings are getting reset on the 443 * hardware, and need to be re-initialized again for communication 444 * to continue work. 445 */ 446 ure_ifmedia_init(ifp); 447 } 448 449 void 450 ure_ifmedia_init(struct ifnet *ifp) 451 { 452 struct ure_softc *sc = ifp->if_softc; 453 uint32_t reg = 0; 454 455 /* Set MAC address. */ 456 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 457 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 458 sc->ure_ac.ac_enaddr, 8); 459 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 460 461 if (!(sc->ure_flags & URE_FLAG_8152)) { 462 if (sc->ure_flags & URE_FLAG_8156B) 463 URE_CLRBIT_2(sc, URE_USB_RX_AGGR_NUM, URE_MCU_TYPE_USB, 464 URE_RX_AGGR_NUM_MASK); 465 466 reg = sc->ure_rxbufsz - URE_FRAMELEN(ifp->if_mtu) - 467 sizeof(struct ure_rxpkt) - URE_RX_BUF_ALIGN; 468 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | 469 URE_FLAG_8156B)) { 470 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, 471 reg / 8); 472 473 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 474 (sc->ure_flags & URE_FLAG_8153B) ? 158 : 80); 475 ure_write_2(sc, URE_USB_PM_CTRL_STATUS, 476 URE_MCU_TYPE_USB, 1875); 477 } else { 478 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, 479 reg / 4); 480 switch (sc->ure_udev->speed) { 481 case USB_SPEED_SUPER: 482 reg = URE_COALESCE_SUPER / 8; 483 break; 484 case USB_SPEED_HIGH: 485 reg = URE_COALESCE_HIGH / 8; 486 break; 487 default: 488 reg = URE_COALESCE_SLOW / 8; 489 break; 490 } 491 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 492 reg); 493 } 494 495 if ((sc->ure_chip & URE_CHIP_VER_6010) || 496 (sc->ure_flags & URE_FLAG_8156B)) { 497 URE_CLRBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, 498 URE_FC_PATCH_TASK); 499 usbd_delay_ms(sc->ure_udev, 1); 500 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, 501 URE_FC_PATCH_TASK); 502 } 503 } 504 505 /* Reset the packet filter. */ 506 URE_CLRBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN); 507 URE_SETBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN); 508 509 /* Enable transmit and receive. */ 510 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE); 511 512 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) { 513 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB, 514 URE_OWN_UPDATE | URE_OWN_CLEAR); 515 } 516 517 URE_CLRBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 518 } 519 520 int 521 ure_ifmedia_upd(struct ifnet *ifp) 522 { 523 struct ure_softc *sc = ifp->if_softc; 524 struct mii_data *mii = &sc->ure_mii; 525 struct ifmedia *ifm = &sc->ure_ifmedia; 526 int anar, gig, err, reg; 527 528 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 529 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 530 return (EINVAL); 531 532 reg = ure_ocp_reg_read(sc, 0xa5d4); 533 reg &= ~URE_ADV_2500TFDX; 534 535 anar = gig = 0; 536 switch (IFM_SUBTYPE(ifm->ifm_media)) { 537 case IFM_AUTO: 538 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 539 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 540 reg |= URE_ADV_2500TFDX; 541 break; 542 case IFM_2500_T: 543 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 544 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 545 reg |= URE_ADV_2500TFDX; 546 ifp->if_baudrate = IF_Mbps(2500); 547 break; 548 case IFM_1000_T: 549 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 550 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 551 ifp->if_baudrate = IF_Gbps(1); 552 break; 553 case IFM_100_TX: 554 anar |= ANAR_TX | ANAR_TX_FD; 555 ifp->if_baudrate = IF_Mbps(100); 556 break; 557 case IFM_10_T: 558 anar |= ANAR_10 | ANAR_10_FD; 559 ifp->if_baudrate = IF_Mbps(10); 560 break; 561 default: 562 printf("%s: unsupported media type\n", 563 sc->ure_dev.dv_xname); 564 return (EINVAL); 565 } 566 567 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_ANAR * 2, 568 anar | ANAR_PAUSE_ASYM | ANAR_FC); 569 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_100T2CR * 2, gig); 570 ure_ocp_reg_write(sc, 0xa5d4, reg); 571 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR, 572 BMCR_AUTOEN | BMCR_STARTNEG); 573 574 return (0); 575 } 576 577 if (mii->mii_instance) { 578 struct mii_softc *miisc; 579 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 580 PHY_RESET(miisc); 581 } 582 583 err = mii_mediachg(mii); 584 if (err == ENXIO) 585 return (0); 586 else 587 return (err); 588 } 589 590 void 591 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 592 { 593 struct ure_softc *sc = ifp->if_softc; 594 struct mii_data *mii = &sc->ure_mii; 595 uint16_t status = 0; 596 597 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 598 ifmr->ifm_status = IFM_AVALID; 599 if (ure_get_link_status(sc)) { 600 ifmr->ifm_status |= IFM_ACTIVE; 601 status = ure_read_2(sc, URE_PLA_PHYSTATUS, 602 URE_MCU_TYPE_PLA); 603 if ((status & URE_PHYSTATUS_FDX) || 604 (status & URE_PHYSTATUS_2500MBPS)) 605 ifmr->ifm_active |= IFM_FDX; 606 else 607 ifmr->ifm_active |= IFM_HDX; 608 if (status & URE_PHYSTATUS_10MBPS) 609 ifmr->ifm_active |= IFM_10_T; 610 else if (status & URE_PHYSTATUS_100MBPS) 611 ifmr->ifm_active |= IFM_100_TX; 612 else if (status & URE_PHYSTATUS_1000MBPS) 613 ifmr->ifm_active |= IFM_1000_T; 614 else if (status & URE_PHYSTATUS_2500MBPS) 615 ifmr->ifm_active |= IFM_2500_T; 616 } 617 return; 618 } 619 620 mii_pollstat(mii); 621 ifmr->ifm_active = mii->mii_media_active; 622 ifmr->ifm_status = mii->mii_media_status; 623 } 624 625 void 626 ure_add_media_types(struct ure_softc *sc) 627 { 628 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 629 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 630 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 631 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, 632 NULL); 633 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 634 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, 635 NULL); 636 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_2500_T, 0, NULL); 637 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_2500_T | IFM_FDX, 0, 638 NULL); 639 } 640 641 void 642 ure_link_state(struct ure_softc *sc) 643 { 644 struct ifnet *ifp = &sc->ure_ac.ac_if; 645 int link = LINK_STATE_DOWN; 646 647 if (ure_get_link_status(sc)) 648 link = LINK_STATE_UP; 649 650 if (ifp->if_link_state != link) { 651 ifp->if_link_state = link; 652 if_link_state_change(ifp); 653 } 654 } 655 656 int 657 ure_get_link_status(struct ure_softc *sc) 658 { 659 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & 660 URE_PHYSTATUS_LINK) { 661 sc->ure_flags |= URE_FLAG_LINK; 662 return (1); 663 } else { 664 sc->ure_flags &= ~URE_FLAG_LINK; 665 return (0); 666 } 667 } 668 669 void 670 ure_iff(struct ure_softc *sc) 671 { 672 struct ifnet *ifp = &sc->ure_ac.ac_if; 673 struct ether_multi *enm; 674 struct ether_multistep step; 675 uint32_t hashes[2] = { 0, 0 }; 676 uint32_t hash; 677 uint32_t rxmode; 678 679 if (usbd_is_dying(sc->ure_udev)) 680 return; 681 682 rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA); 683 rxmode &= ~URE_RCR_ACPT_ALL; 684 ifp->if_flags &= ~IFF_ALLMULTI; 685 686 /* 687 * Always accept frames destined to our station address. 688 * Always accept broadcast frames. 689 */ 690 rxmode |= URE_RCR_APM | URE_RCR_AB; 691 692 if (ifp->if_flags & IFF_PROMISC || sc->ure_ac.ac_multirangecnt > 0) { 693 ifp->if_flags |= IFF_ALLMULTI; 694 rxmode |= URE_RCR_AM; 695 if (ifp->if_flags & IFF_PROMISC) 696 rxmode |= URE_RCR_AAP; 697 hashes[0] = hashes[1] = 0xffffffff; 698 } else { 699 rxmode |= URE_RCR_AM; 700 701 ETHER_FIRST_MULTI(step, &sc->ure_ac, enm); 702 while (enm != NULL) { 703 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) 704 >> 26; 705 if (hash < 32) 706 hashes[0] |= (1 << hash); 707 else 708 hashes[1] |= (1 << (hash - 32)); 709 710 ETHER_NEXT_MULTI(step, enm); 711 } 712 713 hash = swap32(hashes[0]); 714 hashes[0] = swap32(hashes[1]); 715 hashes[1] = hash; 716 } 717 718 ure_write_mem(sc, URE_PLA_MAR, URE_MCU_TYPE_PLA | URE_BYTE_EN_DWORD, 719 hashes, sizeof(hashes)); 720 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 721 } 722 723 void 724 ure_rxvlan(struct ure_softc *sc) 725 { 726 struct ifnet *ifp = &sc->ure_ac.ac_if; 727 uint16_t reg; 728 729 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 730 reg = ure_read_2(sc, URE_PLA_RCR1, URE_MCU_TYPE_PLA); 731 reg &= ~(URE_INNER_VLAN | URE_OUTER_VLAN); 732 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 733 reg |= (URE_INNER_VLAN | URE_OUTER_VLAN); 734 ure_write_2(sc, URE_PLA_RCR1, URE_MCU_TYPE_PLA, reg); 735 } else { 736 reg = ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA); 737 reg &= ~URE_CPCR_RX_VLAN; 738 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 739 reg |= URE_CPCR_RX_VLAN; 740 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, reg); 741 } 742 } 743 744 void 745 ure_reset(struct ure_softc *sc) 746 { 747 int i; 748 749 if (sc->ure_flags & URE_FLAG_8156) { 750 URE_CLRBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_TE); 751 URE_CLRBIT_2(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, 752 BMU_RESET_EP_IN); 753 URE_SETBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 754 URE_CDC_ECM_EN); 755 URE_CLRBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE); 756 URE_SETBIT_2(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, 757 BMU_RESET_EP_IN); 758 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 759 URE_CDC_ECM_EN); 760 } else { 761 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 762 763 for (i = 0; i < URE_TIMEOUT; i++) { 764 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) & 765 URE_CR_RST)) 766 break; 767 DELAY(100); 768 } 769 if (i == URE_TIMEOUT) 770 printf("%s: reset never completed\n", 771 sc->ure_dev.dv_xname); 772 } 773 } 774 775 void 776 ure_watchdog(struct ifnet *ifp) 777 { 778 struct ure_softc *sc = ifp->if_softc; 779 struct ure_chain *c; 780 usbd_status err; 781 int i, s; 782 783 ifp->if_timer = 0; 784 785 if (usbd_is_dying(sc->ure_udev)) 786 return; 787 788 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) 789 return; 790 791 sc = ifp->if_softc; 792 s = splnet(); 793 794 ifp->if_oerrors++; 795 DPRINTF(("%s: watchdog timeout\n", sc->ure_dev.dv_xname)); 796 797 for (i = 0; i < URE_TX_LIST_CNT; i++) { 798 c = &sc->ure_cdata.ure_tx_chain[i]; 799 if (c->uc_cnt > 0) { 800 usbd_get_xfer_status(c->uc_xfer, NULL, NULL, NULL, 801 &err); 802 ure_txeof(c->uc_xfer, c, err); 803 } 804 } 805 806 if (ifq_is_oactive(&ifp->if_snd)) 807 ifq_restart(&ifp->if_snd); 808 splx(s); 809 } 810 811 void 812 ure_init(void *xsc) 813 { 814 struct ure_softc *sc = xsc; 815 struct ure_chain *c; 816 struct ifnet *ifp = &sc->ure_ac.ac_if; 817 usbd_status err; 818 int s, i; 819 820 s = splnet(); 821 822 /* Cancel pending I/O. */ 823 ure_stop(sc); 824 825 if (sc->ure_flags & URE_FLAG_8152) 826 ure_rtl8152_nic_reset(sc); 827 else 828 ure_rtl8153_nic_reset(sc); 829 830 if (ure_xfer_list_init(sc, sc->ure_cdata.ure_rx_chain, 831 sc->ure_rxbufsz, URE_RX_LIST_CNT) == ENOBUFS) { 832 printf("%s: rx list init failed\n", sc->ure_dev.dv_xname); 833 splx(s); 834 return; 835 } 836 837 if (ure_xfer_list_init(sc, sc->ure_cdata.ure_tx_chain, 838 sc->ure_txbufsz, URE_TX_LIST_CNT) == ENOBUFS) { 839 printf("%s: tx list init failed\n", sc->ure_dev.dv_xname); 840 splx(s); 841 return; 842 } 843 844 /* Initialize the SLIST we are using for the multiple tx buffers */ 845 SLIST_INIT(&sc->ure_cdata.ure_tx_free); 846 for (i = 0; i < URE_TX_LIST_CNT; i++) 847 SLIST_INSERT_HEAD(&sc->ure_cdata.ure_tx_free, 848 &sc->ure_cdata.ure_tx_chain[i], uc_list); 849 850 /* Setup MAC address, and enable TX/RX. */ 851 ure_ifmedia_init(ifp); 852 853 /* Load the multicast filter. */ 854 ure_iff(sc); 855 856 /* Open RX and TX pipes. */ 857 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_RX], 858 USBD_EXCLUSIVE_USE, &sc->ure_ep[URE_ENDPT_RX]); 859 if (err) { 860 printf("%s: open rx pipe failed: %s\n", 861 sc->ure_dev.dv_xname, usbd_errstr(err)); 862 splx(s); 863 return; 864 } 865 866 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_TX], 867 USBD_EXCLUSIVE_USE, &sc->ure_ep[URE_ENDPT_TX]); 868 if (err) { 869 printf("%s: open tx pipe failed: %s\n", 870 sc->ure_dev.dv_xname, usbd_errstr(err)); 871 splx(s); 872 return; 873 } 874 875 /* Start up the receive pipe. */ 876 for (i = 0; i < URE_RX_LIST_CNT; i++) { 877 c = &sc->ure_cdata.ure_rx_chain[i]; 878 usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_RX], 879 c, c->uc_buf, c->uc_bufmax, 880 USBD_SHORT_XFER_OK | USBD_NO_COPY, 881 USBD_NO_TIMEOUT, ure_rxeof); 882 usbd_transfer(c->uc_xfer); 883 } 884 885 ure_ifmedia_upd(ifp); 886 887 /* Indicate we are up and running. */ 888 sc->ure_flags &= ~URE_FLAG_LINK; 889 ifp->if_flags |= IFF_RUNNING; 890 ifq_clr_oactive(&ifp->if_snd); 891 892 timeout_add_sec(&sc->ure_stat_ch, 1); 893 894 splx(s); 895 } 896 897 void 898 ure_start(struct ifnet *ifp) 899 { 900 struct ure_softc *sc = ifp->if_softc; 901 struct ure_cdata *cd = &sc->ure_cdata; 902 struct ure_chain *c; 903 struct mbuf *m = NULL; 904 uint32_t new_buflen; 905 int s, mlen; 906 907 if (!(sc->ure_flags & URE_FLAG_LINK) || 908 (ifp->if_flags & (IFF_RUNNING|IFF_UP)) != 909 (IFF_RUNNING|IFF_UP)) { 910 return; 911 } 912 913 s = splnet(); 914 915 c = SLIST_FIRST(&cd->ure_tx_free); 916 while (c != NULL) { 917 m = ifq_deq_begin(&ifp->if_snd); 918 if (m == NULL) 919 break; 920 921 mlen = m->m_pkthdr.len; 922 923 /* Discard packet larger than buffer. */ 924 if (mlen + sizeof(struct ure_txpkt) >= c->uc_bufmax) { 925 ifq_deq_commit(&ifp->if_snd, m); 926 m_freem(m); 927 ifp->if_oerrors++; 928 continue; 929 } 930 931 /* 932 * If packet larger than remaining space, send buffer and 933 * continue. 934 */ 935 new_buflen = roundup(c->uc_buflen, URE_TX_BUF_ALIGN); 936 if (new_buflen + sizeof(struct ure_txpkt) + mlen >= 937 c->uc_bufmax) { 938 ifq_deq_rollback(&ifp->if_snd, m); 939 SLIST_REMOVE_HEAD(&cd->ure_tx_free, uc_list); 940 if (ure_encap_xfer(ifp, sc, c)) { 941 SLIST_INSERT_HEAD(&cd->ure_tx_free, c, 942 uc_list); 943 break; 944 } 945 c = SLIST_FIRST(&cd->ure_tx_free); 946 continue; 947 } 948 949 /* Append packet to current buffer. */ 950 mlen = ure_encap_txpkt(m, c->uc_buf + new_buflen, 951 c->uc_bufmax - new_buflen); 952 if (mlen <= 0) { 953 ifq_deq_rollback(&ifp->if_snd, m); 954 break; 955 } 956 957 ifq_deq_commit(&ifp->if_snd, m); 958 c->uc_cnt += 1; 959 c->uc_buflen = new_buflen + mlen; 960 961 #if NBPFILTER > 0 962 if (ifp->if_bpf) 963 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 964 #endif 965 966 m_freem(m); 967 } 968 969 if (c != NULL) { 970 /* Send current buffer unless empty */ 971 if (c->uc_buflen > 0 && c->uc_cnt > 0) { 972 SLIST_REMOVE_HEAD(&cd->ure_tx_free, uc_list); 973 if (ure_encap_xfer(ifp, sc, c)) { 974 SLIST_INSERT_HEAD(&cd->ure_tx_free, c, 975 uc_list); 976 } 977 c = SLIST_FIRST(&cd->ure_tx_free); 978 } 979 } 980 981 ifp->if_timer = 5; 982 if (c == NULL) 983 ifq_set_oactive(&ifp->if_snd); 984 splx(s); 985 } 986 987 void 988 ure_tick(void *xsc) 989 { 990 struct ure_softc *sc = xsc; 991 992 if (sc == NULL) 993 return; 994 995 if (usbd_is_dying(sc->ure_udev)) 996 return; 997 998 usb_add_task(sc->ure_udev, &sc->ure_tick_task); 999 } 1000 1001 void 1002 ure_stop(struct ure_softc *sc) 1003 { 1004 struct ure_cdata *cd; 1005 struct ifnet *ifp; 1006 usbd_status err; 1007 1008 ure_reset(sc); 1009 1010 ifp = &sc->ure_ac.ac_if; 1011 ifp->if_timer = 0; 1012 ifp->if_flags &= ~IFF_RUNNING; 1013 ifq_clr_oactive(&ifp->if_snd); 1014 1015 timeout_del(&sc->ure_stat_ch); 1016 sc->ure_flags &= ~URE_FLAG_LINK; 1017 1018 if (sc->ure_ep[URE_ENDPT_RX] != NULL) { 1019 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_RX]); 1020 if (err) { 1021 printf("%s: close rx pipe failed: %s\n", 1022 sc->ure_dev.dv_xname, usbd_errstr(err)); 1023 } 1024 sc->ure_ep[URE_ENDPT_RX] = NULL; 1025 } 1026 1027 if (sc->ure_ep[URE_ENDPT_TX] != NULL) { 1028 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_TX]); 1029 if (err) { 1030 printf("%s: close tx pipe failed: %s\n", 1031 sc->ure_dev.dv_xname, usbd_errstr(err)); 1032 } 1033 sc->ure_ep[URE_ENDPT_TX] = NULL; 1034 } 1035 1036 cd = &sc->ure_cdata; 1037 ure_xfer_list_free(sc, cd->ure_rx_chain, URE_RX_LIST_CNT); 1038 ure_xfer_list_free(sc, cd->ure_tx_chain, URE_TX_LIST_CNT); 1039 } 1040 1041 int 1042 ure_xfer_list_init(struct ure_softc *sc, struct ure_chain *ch, 1043 uint32_t bufsize, int listlen) 1044 { 1045 struct ure_chain *c; 1046 int i; 1047 1048 for (i = 0; i < listlen; i++) { 1049 c = &ch[i]; 1050 c->uc_sc = sc; 1051 c->uc_idx = i; 1052 c->uc_buflen = 0; 1053 c->uc_bufmax = bufsize; 1054 c->uc_cnt = 0; 1055 if (c->uc_xfer == NULL) { 1056 c->uc_xfer = usbd_alloc_xfer(sc->ure_udev); 1057 if (c->uc_xfer == NULL) 1058 return (ENOBUFS); 1059 c->uc_buf = usbd_alloc_buffer(c->uc_xfer, c->uc_bufmax); 1060 if (c->uc_buf == NULL) { 1061 usbd_free_xfer(c->uc_xfer); 1062 c->uc_xfer = NULL; 1063 return (ENOBUFS); 1064 } 1065 } 1066 } 1067 1068 return (0); 1069 } 1070 1071 void 1072 ure_xfer_list_free(struct ure_softc *sc, struct ure_chain *ch, int listlen) 1073 { 1074 int i; 1075 1076 for (i = 0; i < listlen; i++) { 1077 if (ch[i].uc_buf != NULL) { 1078 ch[i].uc_buf = NULL; 1079 } 1080 ch[i].uc_cnt = 0; 1081 if (ch[i].uc_xfer != NULL) { 1082 usbd_free_xfer(ch[i].uc_xfer); 1083 ch[i].uc_xfer = NULL; 1084 } 1085 } 1086 } 1087 1088 void 1089 ure_rtl8152_init(struct ure_softc *sc) 1090 { 1091 uint32_t pwrctrl; 1092 1093 /* Disable ALDPS. */ 1094 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 1095 URE_DIS_SDSAVE); 1096 usbd_delay_ms(sc->ure_udev, 20); 1097 1098 if (sc->ure_chip & URE_CHIP_VER_4C00) 1099 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 1100 URE_LED_MODE_MASK); 1101 1102 URE_CLRBIT_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, URE_POWER_CUT); 1103 URE_CLRBIT_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 1104 URE_RESUME_INDICATE); 1105 1106 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 1107 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 1108 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 1109 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 1110 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 1111 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 1112 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 1113 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 1114 URE_SPDWN_LINKCHG_MSK); 1115 1116 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET); 1117 1118 /* Enable Rx aggregation. */ 1119 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1120 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1121 } 1122 1123 void 1124 ure_rtl8153_init(struct ure_softc *sc) 1125 { 1126 uint16_t reg; 1127 uint8_t u1u2[8]; 1128 int i; 1129 1130 memset(u1u2, 0x00, sizeof(u1u2)); 1131 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, u1u2, 1132 sizeof(u1u2)); 1133 1134 for (i = 0; i < 500; i++) { 1135 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 1136 URE_AUTOLOAD_DONE) 1137 break; 1138 usbd_delay_ms(sc->ure_udev, 20); 1139 } 1140 if (i == 500) 1141 printf("%s: timeout waiting for chip autoload\n", 1142 sc->ure_dev.dv_xname); 1143 1144 ure_rtl8153_phy_status(sc, 0); 1145 1146 if (sc->ure_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 | 1147 URE_CHIP_VER_5C20)) { 1148 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG, 1149 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 1150 } 1151 1152 ure_rtl8153_phy_status(sc, URE_PHY_STAT_LAN_ON); 1153 1154 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1155 1156 if (sc->ure_chip & URE_CHIP_VER_5C10) { 1157 reg = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 1158 reg &= ~URE_PWD_DN_SCALE_MASK; 1159 reg |= URE_PWD_DN_SCALE(96); 1160 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, reg); 1161 1162 URE_SETBIT_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 1163 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 1164 } else if (sc->ure_chip & URE_CHIP_VER_5C20) { 1165 URE_CLRBIT_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 1166 URE_ECM_ALDPS); 1167 } 1168 if (sc->ure_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) { 1169 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB)) 1170 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, 1171 URE_DYNAMIC_BURST); 1172 else 1173 URE_CLRBIT_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, 1174 URE_DYNAMIC_BURST); 1175 } 1176 1177 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, URE_EP4_FULL_FC); 1178 1179 URE_CLRBIT_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, URE_TIMER11_EN); 1180 1181 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 1182 URE_LED_MODE_MASK); 1183 1184 if ((sc->ure_chip & URE_CHIP_VER_5C10) && 1185 sc->ure_udev->speed != USB_SPEED_SUPER) 1186 reg = URE_LPM_TIMER_500MS; 1187 else 1188 reg = URE_LPM_TIMER_500US; 1189 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 1190 URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM | reg); 1191 1192 reg = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 1193 reg &= ~URE_SEN_VAL_MASK; 1194 reg |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 1195 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, reg); 1196 1197 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 1198 1199 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 1200 URE_PWR_EN | URE_PHASE2_EN); 1201 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS); 1202 1203 memset(u1u2, 0xff, sizeof(u1u2)); 1204 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, u1u2, 1205 sizeof(u1u2)); 1206 1207 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0); 1208 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 0); 1209 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 0); 1210 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0); 1211 1212 /* Enable Rx aggregation. */ 1213 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1214 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1215 1216 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET); 1217 } 1218 1219 void 1220 ure_rtl8153b_init(struct ure_softc *sc) 1221 { 1222 uint16_t reg; 1223 int i; 1224 1225 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1226 URE_CLRBIT_1(sc, URE_USB_ECM_OP, URE_MCU_TYPE_USB, 1227 URE_EN_ALL_SPEED); 1228 ure_write_2(sc, URE_USB_SPEED_OPTION, URE_MCU_TYPE_USB, 0); 1229 URE_SETBIT_2(sc, URE_USB_ECM_OPTION, URE_MCU_TYPE_USB, 1230 URE_BYPASS_MAC_RESET); 1231 1232 if (sc->ure_flags & URE_FLAG_8156B) 1233 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 1234 URE_RX_DETECT8); 1235 } 1236 1237 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, LPM_U1U2_EN); 1238 1239 if (sc->ure_flags & URE_FLAG_8156B) 1240 ure_wait_for_flash(sc); 1241 1242 for (i = 0; i < 500; i++) { 1243 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 1244 URE_AUTOLOAD_DONE) 1245 break; 1246 usbd_delay_ms(sc->ure_udev, 20); 1247 } 1248 if (i == 500) 1249 printf("%s: timeout waiting for chip autoload\n", 1250 sc->ure_dev.dv_xname); 1251 1252 ure_rtl8153_phy_status(sc, 0); 1253 ure_rtl8153_phy_status(sc, URE_PHY_STAT_LAN_ON); 1254 1255 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1256 1257 /* MSC timer, 32760 ms. */ 1258 ure_write_2(sc, URE_USB_MSC_TIMER, URE_MCU_TYPE_USB, 4095); 1259 1260 if (!(sc->ure_flags & URE_FLAG_8153B)) { 1261 /* U1/U2/L1 idle timer, 500 us. */ 1262 ure_write_2(sc, URE_USB_U1U2_TIMER, URE_MCU_TYPE_USB, 500); 1263 } 1264 1265 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN); 1266 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS); 1267 1268 URE_CLRBIT_1(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 1269 URE_UPS_EN | URE_USP_PREWAKE); 1270 URE_CLRBIT_1(sc, URE_USB_MISC_2, URE_MCU_TYPE_USB, 1271 URE_UPS_FORCE_PWR_DOWN); 1272 1273 URE_CLRBIT_1(sc, URE_PLA_INDICATE_FALG, URE_MCU_TYPE_PLA, 1274 URE_UPCOMING_RUNTIME_D3); 1275 URE_CLRBIT_1(sc, URE_PLA_SUSPEND_FLAG, URE_MCU_TYPE_PLA, 1276 URE_LINK_CHG_EVENT); 1277 URE_CLRBIT_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, 1278 URE_LINK_CHANGE_FLAG); 1279 1280 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 1281 URE_CLRBIT_2(sc, URE_PLA_CONFIG34, URE_MCU_TYPE_PLA, 1282 URE_LINK_OFF_WAKE_EN); 1283 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 1284 1285 if (sc->ure_flags & URE_FLAG_8153B) { 1286 reg = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA); 1287 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & 1288 URE_PHYSTATUS_LINK) 1289 reg |= URE_CUR_LINK_OK; 1290 else 1291 reg &= ~URE_CUR_LINK_OK; 1292 ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, 1293 reg | URE_POLL_LINK_CHG); 1294 } 1295 1296 if (sc->ure_udev->speed == USB_SPEED_SUPER) { 1297 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, 1298 LPM_U1U2_EN); 1299 } 1300 1301 if (sc->ure_flags & URE_FLAG_8156B) { 1302 URE_CLRBIT_2(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_SLOT_EN); 1303 URE_SETBIT_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 1304 URE_FLOW_CTRL_EN); 1305 1306 /* Enable fc timer and set timer to 600 ms. */ 1307 ure_write_2(sc, URE_USB_FC_TIMER, URE_MCU_TYPE_USB, 1308 URE_CTRL_TIMER_EN | 75); 1309 1310 reg = ure_read_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB); 1311 if (!(ure_read_2(sc, URE_PLA_POL_GPIO_CTRL, URE_MCU_TYPE_PLA) & 1312 URE_DACK_DET_EN)) 1313 reg |= URE_FLOW_CTRL_PATCH_2; 1314 reg &= ~URE_AUTO_SPEEDUP; 1315 ure_write_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB, reg); 1316 1317 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, 1318 URE_FC_PATCH_TASK); 1319 } 1320 1321 /* MAC clock speed down. */ 1322 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1323 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0x0403); 1324 reg = ure_read_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA); 1325 reg &= ~URE_EEE_SPDWN_RATIO_MASK; 1326 reg |= URE_MAC_CLK_SPDWN_EN | 0x0003; 1327 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, reg); 1328 1329 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 1330 URE_PLA_MCU_SPDWN_EN); 1331 1332 reg = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA); 1333 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & 1334 URE_PHYSTATUS_LINK) 1335 reg |= URE_CUR_LINK_OK; 1336 else 1337 reg &= ~URE_CUR_LINK_OK; 1338 ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, 1339 reg | URE_POLL_LINK_CHG); 1340 } else 1341 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 1342 URE_MAC_CLK_SPDWN_EN); 1343 1344 /* Enable Rx aggregation. */ 1345 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1346 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1347 1348 if (sc->ure_flags & URE_FLAG_8156) 1349 URE_SETBIT_1(sc, URE_USB_BMU_CONFIG, URE_MCU_TYPE_USB, 1350 URE_ACT_ODMA); 1351 1352 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET); 1353 } 1354 1355 void 1356 ure_rtl8152_nic_reset(struct ure_softc *sc) 1357 { 1358 uint32_t rx_fifo1, rx_fifo2; 1359 int i; 1360 1361 /* Disable ALDPS. */ 1362 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 1363 URE_DIS_SDSAVE); 1364 usbd_delay_ms(sc->ure_udev, 20); 1365 1366 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL); 1367 1368 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 1369 ure_disable_teredo(sc); 1370 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 1371 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 1372 1373 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB); 1374 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN); 1375 for (i = 0; i < URE_TIMEOUT; i++) { 1376 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1377 URE_LINK_LIST_READY) 1378 break; 1379 usbd_delay_ms(sc->ure_udev, 1); 1380 } 1381 if (i == URE_TIMEOUT) 1382 printf("%s: timeout waiting for OOB control\n", 1383 sc->ure_dev.dv_xname); 1384 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL); 1385 for (i = 0; i < URE_TIMEOUT; i++) { 1386 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1387 URE_LINK_LIST_READY) 1388 break; 1389 usbd_delay_ms(sc->ure_udev, 1); 1390 } 1391 if (i == URE_TIMEOUT) 1392 printf("%s: timeout waiting for OOB control\n", 1393 sc->ure_dev.dv_xname); 1394 1395 ure_reset(sc); 1396 1397 /* Configure Rx FIFO threshold. */ 1398 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 1399 URE_RXFIFO_THR1_NORMAL); 1400 if (sc->ure_udev->speed == USB_SPEED_FULL) { 1401 rx_fifo1 = URE_RXFIFO_THR2_FULL; 1402 rx_fifo2 = URE_RXFIFO_THR3_FULL; 1403 } else { 1404 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 1405 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 1406 } 1407 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 1408 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 1409 1410 /* Configure Tx FIFO threshold. */ 1411 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 1412 URE_TXFIFO_THR_NORMAL); 1413 1414 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 1415 URE_TX_AGG_MAX_THRESHOLD); 1416 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 1417 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 1418 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 1419 1420 ure_rxvlan(sc); 1421 ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA, 1422 ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1423 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO); 1424 1425 /* Enable ALDPS. */ 1426 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, 1427 URE_ENPWRSAVE | URE_ENPDNPS | URE_LINKENA | URE_DIS_SDSAVE); 1428 } 1429 1430 void 1431 ure_rtl8153_nic_reset(struct ure_softc *sc) 1432 { 1433 struct ifnet *ifp = &sc->ure_ac.ac_if; 1434 uint32_t reg = 0; 1435 uint8_t u1u2[8] = { 0 }; 1436 int i; 1437 1438 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) { 1439 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, 1440 LPM_U1U2_EN); 1441 } else { 1442 memset(u1u2, 0x00, sizeof(u1u2)); 1443 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, 1444 u1u2, sizeof(u1u2)); 1445 } 1446 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1447 1448 /* Disable ALDPS. */ 1449 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1450 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 1451 for (i = 0; i < 20; i++) { 1452 usbd_delay_ms(sc->ure_udev, 1); 1453 if (ure_read_2(sc, 0xe000, URE_MCU_TYPE_PLA) & 0x0100) 1454 break; 1455 } 1456 1457 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 1458 ure_disable_teredo(sc); 1459 1460 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL); 1461 1462 ure_reset(sc); 1463 ure_reset_bmu(sc); 1464 1465 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB); 1466 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN); 1467 1468 if (!(sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B))) { 1469 for (i = 0; i < URE_TIMEOUT; i++) { 1470 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1471 URE_LINK_LIST_READY) 1472 break; 1473 usbd_delay_ms(sc->ure_udev, 1); 1474 } 1475 if (i == URE_TIMEOUT) 1476 printf("%s: timeout waiting for OOB control\n", 1477 sc->ure_dev.dv_xname); 1478 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 1479 URE_RE_INIT_LL); 1480 for (i = 0; i < URE_TIMEOUT; i++) { 1481 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1482 URE_LINK_LIST_READY) 1483 break; 1484 usbd_delay_ms(sc->ure_udev, 1); 1485 } 1486 if (i == URE_TIMEOUT) 1487 printf("%s: timeout waiting for OOB control\n", 1488 sc->ure_dev.dv_xname); 1489 } 1490 1491 ure_rxvlan(sc); 1492 1493 ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA, 1494 URE_FRAMELEN(ifp->if_mtu)); 1495 ure_write_1(sc, URE_PLA_MTPS, URE_MCU_TYPE_PLA, MTPS_JUMBO); 1496 1497 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1498 ure_write_2(sc, URE_PLA_RX_FIFO_FULL, URE_MCU_TYPE_PLA, 1499 (sc->ure_flags & URE_FLAG_8156) ? 1024 : 512); 1500 ure_write_2(sc, URE_PLA_RX_FIFO_EMPTY, URE_MCU_TYPE_PLA, 1501 (sc->ure_flags & URE_FLAG_8156) ? 2048 : 1024); 1502 1503 /* Tx share fifo free credit full threshold. */ 1504 ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 8); 1505 ure_write_2(sc, URE_PLA_TXFIFO_FULL, URE_MCU_TYPE_PLA, 128); 1506 1507 if (sc->ure_flags & URE_FLAG_8156) 1508 URE_SETBIT_2(sc, URE_USB_BMU_CONFIG, URE_MCU_TYPE_USB, 1509 URE_ACT_ODMA); 1510 1511 /* FIFO settings */ 1512 reg = ure_read_2(sc, URE_PLA_RXFIFO_FULL, URE_MCU_TYPE_PLA); 1513 reg &= ~URE_RXFIFO_FULL_MASK; 1514 ure_write_2(sc, URE_PLA_RXFIFO_FULL, URE_MCU_TYPE_PLA, 1515 reg | 0x0008); 1516 1517 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 1518 URE_PLA_MCU_SPDWN_EN); 1519 1520 URE_CLRBIT_2(sc, URE_USB_SPEED_OPTION, URE_MCU_TYPE_USB, 1521 URE_RG_PWRDN_EN | URE_ALL_SPEED_OFF); 1522 1523 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, 1524 0x00600400); 1525 } 1526 1527 if (!(sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B))) { 1528 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 1529 URE_TCR0_AUTO_FIFO); 1530 ure_reset(sc); 1531 1532 /* Configure Rx FIFO threshold. */ 1533 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 1534 URE_RXFIFO_THR1_NORMAL); 1535 ure_write_2(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, 1536 URE_RXFIFO_THR2_NORMAL); 1537 ure_write_2(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, 1538 URE_RXFIFO_THR3_NORMAL); 1539 1540 /* Configure Tx FIFO threshold. */ 1541 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 1542 URE_TXFIFO_THR_NORMAL2); 1543 1544 if (sc->ure_flags & URE_FLAG_8153B) { 1545 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, 1546 URE_RX_THR_B); 1547 1548 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, 1549 URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN); 1550 } else { 1551 URE_SETBIT_1(sc, URE_PLA_CONFIG6, URE_MCU_TYPE_PLA, 1552 URE_LANWAKE_CLR_EN); 1553 URE_CLRBIT_1(sc, URE_PLA_LWAKE_CTRL_REG, 1554 URE_MCU_TYPE_PLA, URE_LANWAKE_PIN); 1555 URE_CLRBIT_2(sc, URE_USB_SSPHYLINK1, URE_MCU_TYPE_USB, 1556 URE_DELAY_PHY_PWR_CHG); 1557 } 1558 } 1559 1560 /* Enable ALDPS. */ 1561 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1562 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | URE_EN_ALDPS); 1563 1564 if ((sc->ure_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) || 1565 (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B))) 1566 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 1567 URE_U2P3_ENABLE); 1568 1569 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) { 1570 if (sc->ure_udev->speed == USB_SPEED_SUPER) 1571 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, 1572 LPM_U1U2_EN); 1573 } else { 1574 memset(u1u2, 0xff, sizeof(u1u2)); 1575 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, 1576 u1u2, sizeof(u1u2)); 1577 } 1578 } 1579 1580 uint16_t 1581 ure_rtl8153_phy_status(struct ure_softc *sc, int desired) 1582 { 1583 uint16_t reg; 1584 int i; 1585 1586 for (i = 0; i < 500; i++) { 1587 reg = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & 1588 URE_PHY_STAT_MASK; 1589 if (desired) { 1590 if (reg == desired) 1591 break; 1592 } else { 1593 if (reg == URE_PHY_STAT_LAN_ON || 1594 reg == URE_PHY_STAT_PWRDN || 1595 reg == URE_PHY_STAT_EXT_INIT) 1596 break; 1597 } 1598 usbd_delay_ms(sc->ure_udev, 20); 1599 } 1600 if (i == 500) 1601 printf("%s: timeout waiting for phy to stabilize\n", 1602 sc->ure_dev.dv_xname); 1603 1604 return reg; 1605 } 1606 1607 void 1608 ure_wait_for_flash(struct ure_softc *sc) 1609 { 1610 int i; 1611 1612 if ((ure_read_2(sc, URE_PLA_GPHY_CTRL, URE_MCU_TYPE_PLA) & 1613 URE_GPHY_FLASH) && 1614 !(ure_read_2(sc, URE_USB_GPHY_CTRL, URE_MCU_TYPE_USB) & 1615 URE_BYPASS_FLASH)) { 1616 for (i = 0; i < 100; i++) { 1617 if (ure_read_2(sc, URE_USB_GPHY_CTRL, 1618 URE_MCU_TYPE_USB) & URE_GPHY_PATCH_DONE) 1619 break; 1620 DELAY(1000); 1621 } 1622 if (i == 100) 1623 printf("%s: timeout waiting for loading flash\n", 1624 sc->ure_dev.dv_xname); 1625 } 1626 } 1627 1628 void 1629 ure_reset_bmu(struct ure_softc *sc) 1630 { 1631 uint8_t reg; 1632 1633 reg = ure_read_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB); 1634 reg &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); 1635 ure_write_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, reg); 1636 reg |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; 1637 ure_write_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, reg); 1638 } 1639 1640 void 1641 ure_disable_teredo(struct ure_softc *sc) 1642 { 1643 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) 1644 ure_write_1(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 0xff); 1645 else { 1646 URE_CLRBIT_2(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 1647 URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | 1648 URE_OOB_TEREDO_EN); 1649 } 1650 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, URE_WDT6_SET_MODE); 1651 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 1652 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 1653 } 1654 1655 int 1656 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1657 { 1658 struct ure_softc *sc = ifp->if_softc; 1659 struct ifreq *ifr = (struct ifreq *)data; 1660 int s, error = 0; 1661 1662 s = splnet(); 1663 1664 switch (cmd) { 1665 case SIOCSIFADDR: 1666 ifp->if_flags |= IFF_UP; 1667 if (!(ifp->if_flags & IFF_RUNNING)) 1668 ure_init(sc); 1669 break; 1670 1671 case SIOCSIFFLAGS: 1672 if (ifp->if_flags & IFF_UP) { 1673 if (ifp->if_flags & IFF_RUNNING) 1674 error = ENETRESET; 1675 else 1676 ure_init(sc); 1677 } else { 1678 if (ifp->if_flags & IFF_RUNNING) 1679 ure_stop(sc); 1680 } 1681 break; 1682 1683 case SIOCGIFMEDIA: 1684 case SIOCSIFMEDIA: 1685 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) 1686 error = ifmedia_ioctl(ifp, ifr, &sc->ure_ifmedia, cmd); 1687 else 1688 error = ifmedia_ioctl(ifp, ifr, &sc->ure_mii.mii_media, 1689 cmd); 1690 break; 1691 1692 default: 1693 error = ether_ioctl(ifp, &sc->ure_ac, cmd, data); 1694 } 1695 1696 if (error == ENETRESET) { 1697 if (ifp->if_flags & IFF_RUNNING) 1698 ure_iff(sc); 1699 error = 0; 1700 } 1701 1702 splx(s); 1703 1704 return (error); 1705 } 1706 1707 int 1708 ure_match(struct device *parent, void *match, void *aux) 1709 { 1710 struct usb_attach_arg *uaa = aux; 1711 1712 if (uaa->iface == NULL || uaa->configno != 1) 1713 return (UMATCH_NONE); 1714 1715 return (usb_lookup(ure_devs, uaa->vendor, uaa->product) != NULL ? 1716 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 1717 } 1718 1719 void 1720 ure_attach(struct device *parent, struct device *self, void *aux) 1721 { 1722 struct ure_softc *sc = (struct ure_softc *)self; 1723 struct usb_attach_arg *uaa = aux; 1724 usb_interface_descriptor_t *id; 1725 usb_endpoint_descriptor_t *ed; 1726 u_char eaddr[8]; /* 4byte padded */ 1727 struct ifnet *ifp; 1728 int i, mii_flags = 0, s; 1729 uint16_t ver; 1730 1731 sc->ure_udev = uaa->device; 1732 sc->ure_iface = uaa->iface; 1733 1734 usb_init_task(&sc->ure_tick_task, ure_tick_task, sc, 1735 USB_TASK_TYPE_GENERIC); 1736 1737 id = usbd_get_interface_descriptor(sc->ure_iface); 1738 1739 for (i = 0; i < id->bNumEndpoints; i++) { 1740 ed = usbd_interface2endpoint_descriptor(sc->ure_iface, i); 1741 if (!ed) { 1742 printf("%s: couldn't get ep %d\n", 1743 sc->ure_dev.dv_xname, i); 1744 return; 1745 } 1746 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 1747 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 1748 sc->ure_ed[URE_ENDPT_RX] = ed->bEndpointAddress; 1749 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 1750 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 1751 sc->ure_ed[URE_ENDPT_TX] = ed->bEndpointAddress; 1752 } 1753 } 1754 1755 sc->ure_txbufsz = URE_TX_BUFSZ; 1756 sc->ure_rxbufsz = URE_8153_RX_BUFSZ; 1757 1758 s = splnet(); 1759 1760 sc->ure_phyno = 0; 1761 printf("%s: ", sc->ure_dev.dv_xname); 1762 1763 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 1764 switch (ver) { 1765 case 0x4c00: 1766 sc->ure_flags = URE_FLAG_8152; 1767 sc->ure_rxbufsz = URE_8152_RX_BUFSZ; 1768 sc->ure_chip |= URE_CHIP_VER_4C00; 1769 printf("RTL8152 (0x4c00)"); 1770 break; 1771 case 0x4c10: 1772 sc->ure_flags = URE_FLAG_8152; 1773 sc->ure_rxbufsz = URE_8152_RX_BUFSZ; 1774 sc->ure_chip |= URE_CHIP_VER_4C10; 1775 printf("RTL8152 (0x4c10)"); 1776 break; 1777 case 0x5c00: 1778 sc->ure_chip |= URE_CHIP_VER_5C00; 1779 printf("RTL8153 (0x5c00)"); 1780 break; 1781 case 0x5c10: 1782 sc->ure_chip |= URE_CHIP_VER_5C10; 1783 printf("RTL8153 (0x5c10)"); 1784 break; 1785 case 0x5c20: 1786 sc->ure_chip |= URE_CHIP_VER_5C20; 1787 printf("RTL8153 (0x5c20)"); 1788 break; 1789 case 0x5c30: 1790 sc->ure_chip |= URE_CHIP_VER_5C30; 1791 printf("RTL8153 (0x5c30)"); 1792 break; 1793 case 0x6000: 1794 sc->ure_flags = URE_FLAG_8153B; 1795 printf("RTL8153B (0x6000)"); 1796 break; 1797 case 0x6010: 1798 sc->ure_flags = URE_FLAG_8153B; 1799 printf("RTL8153B (0x6010)"); 1800 break; 1801 case 0x7020: 1802 sc->ure_flags = URE_FLAG_8156; 1803 printf("RTL8156 (0x7020)"); 1804 break; 1805 case 0x7030: 1806 sc->ure_flags = URE_FLAG_8156; 1807 printf("RTL8156 (0x7030)"); 1808 break; 1809 case 0x7410: 1810 sc->ure_flags = URE_FLAG_8156B; 1811 printf("RTL8156B (0x7410)"); 1812 break; 1813 default: 1814 printf(", unknown ver %02x", ver); 1815 break; 1816 } 1817 1818 if (sc->ure_flags & URE_FLAG_8152) 1819 ure_rtl8152_init(sc); 1820 else if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | 1821 URE_FLAG_8156B)) 1822 ure_rtl8153b_init(sc); 1823 else 1824 ure_rtl8153_init(sc); 1825 1826 if (sc->ure_chip & URE_CHIP_VER_4C00) 1827 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr, 1828 sizeof(eaddr)); 1829 else 1830 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr, 1831 sizeof(eaddr)); 1832 1833 printf(", address %s\n", ether_sprintf(eaddr)); 1834 1835 bcopy(eaddr, (char *)&sc->ure_ac.ac_enaddr, ETHER_ADDR_LEN); 1836 1837 ifp = &sc->ure_ac.ac_if; 1838 ifp->if_softc = sc; 1839 strlcpy(ifp->if_xname, sc->ure_dev.dv_xname, IFNAMSIZ); 1840 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1841 ifp->if_ioctl = ure_ioctl; 1842 ifp->if_start = ure_start; 1843 ifp->if_watchdog = ure_watchdog; 1844 1845 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 | 1846 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1847 1848 #if NVLAN > 0 1849 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1850 #endif 1851 1852 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1853 ifmedia_init(&sc->ure_ifmedia, IFM_IMASK, ure_ifmedia_upd, 1854 ure_ifmedia_sts); 1855 ure_add_media_types(sc); 1856 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1857 ifmedia_set(&sc->ure_ifmedia, IFM_ETHER | IFM_AUTO); 1858 sc->ure_ifmedia.ifm_media = sc->ure_ifmedia.ifm_cur->ifm_media; 1859 } else { 1860 rw_init(&sc->ure_mii_lock, "uremii"); 1861 1862 sc->ure_mii.mii_ifp = ifp; 1863 sc->ure_mii.mii_readreg = ure_miibus_readreg; 1864 sc->ure_mii.mii_writereg = ure_miibus_writereg; 1865 sc->ure_mii.mii_statchg = ure_miibus_statchg; 1866 sc->ure_mii.mii_flags = MIIF_AUTOTSLEEP; 1867 1868 ifmedia_init(&sc->ure_mii.mii_media, 0, ure_ifmedia_upd, 1869 ure_ifmedia_sts); 1870 if (!(sc->ure_flags & URE_FLAG_8152)) 1871 mii_flags |= MIIF_DOPAUSE; 1872 mii_attach(self, &sc->ure_mii, 0xffffffff, sc->ure_phyno, 1873 MII_OFFSET_ANY, mii_flags); 1874 if (LIST_FIRST(&sc->ure_mii.mii_phys) == NULL) { 1875 ifmedia_add(&sc->ure_mii.mii_media, 1876 IFM_ETHER | IFM_NONE, 0, NULL); 1877 ifmedia_set(&sc->ure_mii.mii_media, 1878 IFM_ETHER | IFM_NONE); 1879 } else 1880 ifmedia_set(&sc->ure_mii.mii_media, 1881 IFM_ETHER | IFM_AUTO); 1882 } 1883 1884 if_attach(ifp); 1885 ether_ifattach(ifp); 1886 1887 timeout_set(&sc->ure_stat_ch, ure_tick, sc); 1888 1889 splx(s); 1890 } 1891 1892 int 1893 ure_detach(struct device *self, int flags) 1894 { 1895 struct ure_softc *sc = (struct ure_softc *)self; 1896 struct ifnet *ifp = &sc->ure_ac.ac_if; 1897 int s; 1898 1899 if (timeout_initialized(&sc->ure_stat_ch)) 1900 timeout_del(&sc->ure_stat_ch); 1901 1902 if (sc->ure_ep[URE_ENDPT_TX] != NULL) 1903 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_TX]); 1904 if (sc->ure_ep[URE_ENDPT_RX] != NULL) 1905 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_RX]); 1906 1907 usb_rem_task(sc->ure_udev, &sc->ure_tick_task); 1908 1909 s = splusb(); 1910 1911 if (--sc->ure_refcnt >= 0) { 1912 usb_detach_wait(&sc->ure_dev); 1913 } 1914 1915 if (ifp->if_flags & IFF_RUNNING) 1916 ure_stop(sc); 1917 1918 mii_detach(&sc->ure_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1919 ifmedia_delete_instance(&sc->ure_mii.mii_media, IFM_INST_ANY); 1920 if (ifp->if_softc != NULL) { 1921 ether_ifdetach(ifp); 1922 if_detach(ifp); 1923 } 1924 1925 splx(s); 1926 1927 return 0; 1928 } 1929 1930 void 1931 ure_tick_task(void *xsc) 1932 { 1933 struct ure_softc *sc = xsc; 1934 struct mii_data *mii; 1935 int s; 1936 1937 if (sc == NULL) 1938 return; 1939 1940 if (usbd_is_dying(sc->ure_udev)) 1941 return; 1942 mii = &sc->ure_mii; 1943 1944 s = splnet(); 1945 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) 1946 ure_link_state(sc); 1947 else { 1948 mii_tick(mii); 1949 if ((sc->ure_flags & URE_FLAG_LINK) == 0) 1950 ure_miibus_statchg(&sc->ure_dev); 1951 } 1952 timeout_add_sec(&sc->ure_stat_ch, 1); 1953 splx(s); 1954 } 1955 1956 void 1957 ure_lock_mii(struct ure_softc *sc) 1958 { 1959 sc->ure_refcnt++; 1960 rw_enter_write(&sc->ure_mii_lock); 1961 } 1962 1963 void 1964 ure_unlock_mii(struct ure_softc *sc) 1965 { 1966 rw_exit_write(&sc->ure_mii_lock); 1967 if (--sc->ure_refcnt < 0) 1968 usb_detach_wakeup(&sc->ure_dev); 1969 } 1970 1971 void 1972 ure_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1973 { 1974 struct ure_chain *c = (struct ure_chain *)priv; 1975 struct ure_softc *sc = c->uc_sc; 1976 struct ifnet *ifp = &sc->ure_ac.ac_if; 1977 u_char *buf = c->uc_buf; 1978 uint32_t cflags, rxvlan, total_len; 1979 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1980 struct mbuf *m; 1981 int pktlen = 0, s; 1982 struct ure_rxpkt rxhdr; 1983 1984 if (usbd_is_dying(sc->ure_udev)) 1985 return; 1986 1987 if (!(ifp->if_flags & IFF_RUNNING)) 1988 return; 1989 1990 if (status != USBD_NORMAL_COMPLETION) { 1991 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 1992 return; 1993 if (usbd_ratecheck(&sc->ure_rx_notice)) { 1994 printf("%s: usb errors on rx: %s\n", 1995 sc->ure_dev.dv_xname, usbd_errstr(status)); 1996 } 1997 if (status == USBD_STALLED) 1998 usbd_clear_endpoint_stall_async( 1999 sc->ure_ep[URE_ENDPT_RX]); 2000 goto done; 2001 } 2002 2003 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL); 2004 DPRINTFN(3, ("received %d bytes\n", total_len)); 2005 2006 do { 2007 if (total_len < sizeof(rxhdr)) { 2008 DPRINTF(("too few bytes left for a packet header\n")); 2009 ifp->if_ierrors++; 2010 goto done; 2011 } 2012 2013 buf += roundup(pktlen, URE_RX_BUF_ALIGN); 2014 2015 memcpy(&rxhdr, buf, sizeof(rxhdr)); 2016 total_len -= sizeof(rxhdr); 2017 2018 pktlen = letoh32(rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK; 2019 DPRINTFN(4, ("next packet is %d bytes\n", pktlen)); 2020 if (pktlen > total_len) { 2021 DPRINTF(("not enough bytes left for next packet\n")); 2022 ifp->if_ierrors++; 2023 goto done; 2024 } 2025 2026 total_len -= roundup(pktlen, URE_RX_BUF_ALIGN); 2027 buf += sizeof(rxhdr); 2028 2029 m = m_devget(buf, pktlen - ETHER_CRC_LEN, ETHER_ALIGN); 2030 if (m == NULL) { 2031 DPRINTF(("unable to allocate mbuf for next packet\n")); 2032 ifp->if_ierrors++; 2033 goto done; 2034 } 2035 2036 cflags = letoh32(rxhdr.ure_csum); 2037 rxvlan = letoh32(rxhdr.ure_vlan); 2038 2039 /* Check IP header checksum. */ 2040 if ((rxvlan & URE_RXPKT_IPV4) && 2041 !(cflags & URE_RXPKT_IPSUMBAD)) 2042 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 2043 2044 /* Check TCP/UDP checksum. */ 2045 if ((rxvlan & (URE_RXPKT_IPV4 | URE_RXPKT_IPV6)) && 2046 (((rxvlan & URE_RXPKT_TCP) && 2047 !(cflags & URE_RXPKT_TCPSUMBAD)) || 2048 ((rxvlan & URE_RXPKT_UDP) && 2049 !(cflags & URE_RXPKT_UDPSUMBAD)))) 2050 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | 2051 M_UDP_CSUM_IN_OK; 2052 #if NVLAN > 0 2053 if (rxvlan & URE_RXPKT_VLAN_TAG) { 2054 m->m_pkthdr.ether_vtag = 2055 swap16(rxvlan & URE_RXPKT_VLAN_DATA); 2056 m->m_flags |= M_VLANTAG; 2057 } 2058 #endif 2059 2060 ml_enqueue(&ml, m); 2061 } while (total_len > 0); 2062 2063 done: 2064 s = splnet(); 2065 if_input(ifp, &ml); 2066 splx(s); 2067 memset(c->uc_buf, 0, sc->ure_rxbufsz); 2068 2069 usbd_setup_xfer(xfer, sc->ure_ep[URE_ENDPT_RX], c, c->uc_buf, 2070 sc->ure_rxbufsz, USBD_SHORT_XFER_OK | USBD_NO_COPY, 2071 USBD_NO_TIMEOUT, ure_rxeof); 2072 usbd_transfer(xfer); 2073 } 2074 2075 2076 void 2077 ure_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2078 { 2079 struct ure_softc *sc; 2080 struct ure_chain *c; 2081 struct ifnet *ifp; 2082 int s; 2083 2084 c = priv; 2085 sc = c->uc_sc; 2086 ifp = &sc->ure_ac.ac_if; 2087 2088 if (usbd_is_dying(sc->ure_udev)) 2089 return; 2090 2091 if (status != USBD_NORMAL_COMPLETION) 2092 DPRINTF(("%s: %s uc_idx=%u : %s\n", sc->ure_dev.dv_xname, 2093 __func__, c->uc_idx, usbd_errstr(status))); 2094 2095 s = splnet(); 2096 2097 c->uc_cnt = 0; 2098 c->uc_buflen = 0; 2099 2100 SLIST_INSERT_HEAD(&sc->ure_cdata.ure_tx_free, c, uc_list); 2101 2102 if (status != USBD_NORMAL_COMPLETION) { 2103 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) { 2104 splx(s); 2105 return; 2106 } 2107 2108 ifp->if_oerrors++; 2109 printf("%s: usb error on tx: %s\n", sc->ure_dev.dv_xname, 2110 usbd_errstr(status)); 2111 2112 if (status == USBD_STALLED) 2113 usbd_clear_endpoint_stall_async( 2114 sc->ure_ep[URE_ENDPT_TX]); 2115 splx(s); 2116 return; 2117 } 2118 2119 ifp->if_timer = 0; 2120 if (ifq_is_oactive(&ifp->if_snd)) 2121 ifq_restart(&ifp->if_snd); 2122 splx(s); 2123 } 2124 2125 int 2126 ure_encap_txpkt(struct mbuf *m, char *buf, uint32_t maxlen) 2127 { 2128 struct ure_txpkt txhdr; 2129 uint32_t len = sizeof(txhdr), cflags = 0; 2130 2131 if (len + m->m_pkthdr.len > maxlen) 2132 return (-1); 2133 2134 if ((m->m_pkthdr.csum_flags & 2135 (M_IPV4_CSUM_OUT | M_TCP_CSUM_OUT | M_UDP_CSUM_OUT)) != 0) { 2136 cflags |= URE_TXPKT_IPV4; 2137 if (m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) 2138 cflags |= URE_TXPKT_TCP; 2139 if (m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) 2140 cflags |= URE_TXPKT_UDP; 2141 } 2142 2143 #if NVLAN > 0 2144 if (m->m_flags & M_VLANTAG) 2145 cflags |= URE_TXPKT_VLAN_TAG | swap16(m->m_pkthdr.ether_vtag); 2146 #endif 2147 2148 txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS | 2149 URE_TXPKT_TX_LS); 2150 txhdr.ure_vlan = htole32(cflags); 2151 memcpy(buf, &txhdr, len); 2152 2153 m_copydata(m, 0, m->m_pkthdr.len, buf + len); 2154 len += m->m_pkthdr.len; 2155 2156 return (len); 2157 } 2158 2159 int 2160 ure_encap_xfer(struct ifnet *ifp, struct ure_softc *sc, struct ure_chain *c) 2161 { 2162 usbd_status err; 2163 2164 usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_TX], c, c->uc_buf, 2165 c->uc_buflen, USBD_FORCE_SHORT_XFER | USBD_NO_COPY, 10000, 2166 ure_txeof); 2167 2168 err = usbd_transfer(c->uc_xfer); 2169 if (err != USBD_IN_PROGRESS) { 2170 c->uc_cnt = 0; 2171 c->uc_buflen = 0; 2172 ure_stop(sc); 2173 return (EIO); 2174 } 2175 2176 return (0); 2177 } 2178