1 /* $OpenBSD: if_ure.c,v 1.8 2017/07/20 08:30:34 mpi Exp $ */ 2 /*- 3 * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include "bpfilter.h" 29 30 #include <sys/cdefs.h> 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/sockio.h> 35 #include <sys/rwlock.h> 36 #include <sys/mbuf.h> 37 #include <sys/kernel.h> 38 #include <sys/socket.h> 39 #include <sys/device.h> 40 41 #include <machine/bus.h> 42 43 #include <net/if.h> 44 #include <net/if_media.h> 45 46 #if NBPFILTER > 0 47 #include <net/bpf.h> 48 #endif 49 50 #include <netinet/in.h> 51 #include <netinet/if_ether.h> 52 53 #include <dev/mii/miivar.h> 54 55 #include <dev/usb/usb.h> 56 #include <dev/usb/usbdi.h> 57 #include <dev/usb/usbdi_util.h> 58 #include <dev/usb/usbdivar.h> 59 #include <dev/usb/usbdevs.h> 60 61 #include <dev/ic/rtl81x9reg.h> 62 #include <dev/usb/if_urereg.h> 63 64 #ifdef URE_DEBUG 65 #define DPRINTF(x) do { if (uredebug) printf x; } while (0) 66 #define DPRINTFN(n,x) do { if (uredebug >= (n)) printf x; } while (0) 67 int uredebug = 0; 68 #else 69 #define DPRINTF(x) 70 #define DPRINTFN(n,x) 71 #endif 72 73 const struct usb_devno ure_devs[] = { 74 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 }, 75 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8153 } 76 }; 77 78 int ure_match(struct device *, void *, void *); 79 void ure_attach(struct device *, struct device *, void *); 80 int ure_detach(struct device *, int); 81 82 struct cfdriver ure_cd = { 83 NULL, "ure", DV_IFNET 84 }; 85 86 const struct cfattach ure_ca = { 87 sizeof(struct ure_softc), ure_match, ure_attach, ure_detach 88 }; 89 90 int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t, 91 void *, int); 92 int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *, 93 int); 94 int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *, 95 int); 96 uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t); 97 uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t); 98 uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t); 99 int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t); 100 int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t); 101 int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t); 102 uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t); 103 void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t); 104 105 void ure_init(void *); 106 void ure_stop(struct ure_softc *); 107 void ure_start(struct ifnet *); 108 void ure_reset(struct ure_softc *); 109 110 void ure_miibus_statchg(struct device *); 111 int ure_miibus_readreg(struct device *, int, int); 112 void ure_miibus_writereg(struct device *, int, int, int); 113 void ure_lock_mii(struct ure_softc *); 114 void ure_unlock_mii(struct ure_softc *); 115 116 int ure_encap(struct ure_softc *, struct mbuf *, int); 117 void ure_rxeof(struct usbd_xfer *, void *, usbd_status); 118 void ure_txeof(struct usbd_xfer *, void *, usbd_status); 119 int ure_rx_list_init(struct ure_softc *); 120 int ure_tx_list_init(struct ure_softc *); 121 122 void ure_tick_task(void *); 123 void ure_tick(void *); 124 125 int ure_ifmedia_upd(struct ifnet *); 126 void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *); 127 int ure_ioctl(struct ifnet *, u_long, caddr_t); 128 void ure_rtl8152_init(struct ure_softc *); 129 void ure_rtl8153_init(struct ure_softc *); 130 void ure_disable_teredo(struct ure_softc *); 131 void ure_init_fifo(struct ure_softc *); 132 133 134 135 int 136 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index, 137 void *buf, int len) 138 { 139 usb_device_request_t req; 140 usbd_status err; 141 142 if (usbd_is_dying(sc->ure_udev)) 143 return 0; 144 145 if (rw == URE_CTL_WRITE) 146 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 147 else 148 req.bmRequestType = UT_READ_VENDOR_DEVICE; 149 req.bRequest = UR_SET_ADDRESS; 150 USETW(req.wValue, val); 151 USETW(req.wIndex, index); 152 USETW(req.wLength, len); 153 154 DPRINTFN(5, ("ure_ctl: rw %d, val 0x%04hu, index 0x%04hu, len %d\n", 155 rw, val, index, len)); 156 err = usbd_do_request(sc->ure_udev, &req, buf); 157 if (err) { 158 DPRINTF(("ure_ctl: error %d\n", err)); 159 return -1; 160 } 161 162 return 0; 163 } 164 165 int 166 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 167 void *buf, int len) 168 { 169 170 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len)); 171 } 172 173 int 174 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 175 void *buf, int len) 176 { 177 178 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len)); 179 } 180 181 uint8_t 182 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index) 183 { 184 uint32_t val; 185 uint8_t temp[4]; 186 uint8_t shift; 187 188 shift = (reg & 3) << 3; 189 reg &= ~3; 190 191 ure_read_mem(sc, reg, index, &temp, 4); 192 val = UGETDW(temp); 193 val >>= shift; 194 195 return (val & 0xff); 196 } 197 198 uint16_t 199 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index) 200 { 201 uint32_t val; 202 uint8_t temp[4]; 203 uint8_t shift; 204 205 shift = (reg & 2) << 3; 206 reg &= ~3; 207 208 ure_read_mem(sc, reg, index, &temp, 4); 209 val = UGETDW(temp); 210 val >>= shift; 211 212 return (val & 0xffff); 213 } 214 215 uint32_t 216 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index) 217 { 218 uint8_t temp[4]; 219 220 ure_read_mem(sc, reg, index, &temp, 4); 221 return (UGETDW(temp)); 222 } 223 224 int 225 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 226 { 227 uint16_t byen; 228 uint8_t temp[4]; 229 uint8_t shift; 230 231 byen = URE_BYTE_EN_BYTE; 232 shift = reg & 3; 233 val &= 0xff; 234 235 if (reg & 3) { 236 byen <<= shift; 237 val <<= (shift << 3); 238 reg &= ~3; 239 } 240 241 USETDW(temp, val); 242 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 243 } 244 245 int 246 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 247 { 248 uint16_t byen; 249 uint8_t temp[4]; 250 uint8_t shift; 251 252 byen = URE_BYTE_EN_WORD; 253 shift = reg & 2; 254 val &= 0xffff; 255 256 if (reg & 2) { 257 byen <<= shift; 258 val <<= (shift << 3); 259 reg &= ~3; 260 } 261 262 USETDW(temp, val); 263 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 264 } 265 266 int 267 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 268 { 269 uint8_t temp[4]; 270 271 USETDW(temp, val); 272 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4)); 273 } 274 275 uint16_t 276 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr) 277 { 278 uint16_t reg; 279 280 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 281 reg = (addr & 0x0fff) | 0xb000; 282 283 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA)); 284 } 285 286 void 287 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 288 { 289 uint16_t reg; 290 291 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 292 reg = (addr & 0x0fff) | 0xb000; 293 294 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data); 295 } 296 297 int 298 ure_miibus_readreg(struct device *dev, int phy, int reg) 299 { 300 struct ure_softc *sc = (void *)dev; 301 uint16_t val; 302 303 if (usbd_is_dying(sc->ure_udev)) 304 return 0; 305 306 /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */ 307 if (reg == RL_GMEDIASTAT) 308 return ure_read_1(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA); 309 310 ure_lock_mii(sc); 311 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2); 312 ure_unlock_mii(sc); 313 314 return val; /* letoh16? */ 315 } 316 317 void 318 ure_miibus_writereg(struct device *dev, int phy, int reg, int val) 319 { 320 struct ure_softc *sc = (void *)dev; 321 322 ure_lock_mii(sc); 323 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val); /* htole16? */ 324 ure_unlock_mii(sc); 325 } 326 327 void 328 ure_miibus_statchg(struct device *dev) 329 { 330 struct ure_softc *sc = (void *)dev; 331 struct mii_data *mii = &sc->ure_mii; 332 struct ifnet *ifp = &sc->ure_ac.ac_if; 333 334 if ((ifp->if_flags & IFF_RUNNING) == 0) 335 return; 336 337 sc->ure_flags &= ~URE_FLAG_LINK; 338 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 339 (IFM_ACTIVE | IFM_AVALID)) { 340 switch (IFM_SUBTYPE(mii->mii_media_active)) { 341 case IFM_10_T: 342 case IFM_100_TX: 343 sc->ure_flags |= URE_FLAG_LINK; 344 break; 345 case IFM_1000_T: 346 if ((sc->ure_flags & URE_FLAG_8152) != 0) 347 break; 348 sc->ure_flags |= URE_FLAG_LINK; 349 break; 350 default: 351 break; 352 } 353 } 354 } 355 356 int 357 ure_ifmedia_upd(struct ifnet *ifp) 358 { 359 struct ure_softc *sc = ifp->if_softc; 360 struct mii_data *mii = &sc->ure_mii; 361 int err; 362 363 sc->ure_flags &= ~URE_FLAG_LINK; 364 if (mii->mii_instance) { 365 struct mii_softc *miisc; 366 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 367 PHY_RESET(miisc); 368 } 369 370 err = mii_mediachg(mii); 371 if (err == ENXIO) 372 return 0; 373 else 374 return err; 375 } 376 377 void 378 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 379 { 380 struct ure_softc *sc = ifp->if_softc; 381 struct mii_data *mii = &sc->ure_mii; 382 383 mii_pollstat(mii); 384 ifmr->ifm_active = mii->mii_media_active; 385 ifmr->ifm_status = mii->mii_media_status; 386 } 387 388 void 389 ure_iff(struct ure_softc *sc) 390 { 391 struct ifnet *ifp = &sc->ure_ac.ac_if; 392 struct ether_multi *enm; 393 struct ether_multistep step; 394 uint32_t hashes[2] = { 0, 0 }; 395 uint32_t hash; 396 uint32_t rxmode; 397 398 if (usbd_is_dying(sc->ure_udev)) 399 return; 400 401 rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA); 402 rxmode &= ~URE_RCR_ACPT_ALL; 403 ifp->if_flags &= ~IFF_ALLMULTI; 404 405 /* 406 * Always accept frames destined to our station address. 407 * Always accept broadcast frames. 408 */ 409 rxmode |= URE_RCR_APM | URE_RCR_AB; 410 411 if (ifp->if_flags & IFF_PROMISC || sc->ure_ac.ac_multirangecnt > 0) { 412 ifp->if_flags |= IFF_ALLMULTI; 413 rxmode |= URE_RCR_AM; 414 if (ifp->if_flags & IFF_PROMISC) 415 rxmode |= URE_RCR_AAP; 416 hashes[0] = hashes[1] = 0xffffffff; 417 } else { 418 rxmode |= URE_RCR_AM; 419 420 ETHER_FIRST_MULTI(step, &sc->ure_ac, enm); 421 while (enm != NULL) { 422 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) 423 >> 26; 424 if (hash < 32) 425 hashes[0] |= (1 << hash); 426 else 427 hashes[1] |= (1 << (hash - 32)); 428 429 ETHER_NEXT_MULTI(step, enm); 430 } 431 432 hash = swap32(hashes[0]); 433 hashes[0] = swap32(hashes[1]); 434 hashes[1] = hash; 435 } 436 437 ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]); 438 ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]); 439 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 440 } 441 442 void 443 ure_reset(struct ure_softc *sc) 444 { 445 int i; 446 447 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 448 449 for (i = 0; i < URE_TIMEOUT; i++) { 450 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) & 451 URE_CR_RST)) 452 break; 453 usbd_delay_ms(sc->ure_udev, 10); 454 } 455 if (i == URE_TIMEOUT) 456 printf("%s: reset never completed\n", sc->ure_dev.dv_xname); 457 } 458 459 void 460 ure_init(void *xsc) 461 { 462 struct ure_softc *sc = xsc; 463 struct ure_chain *c; 464 struct ifnet *ifp = &sc->ure_ac.ac_if; 465 usbd_status err; 466 int s, i; 467 468 s = splnet(); 469 470 /* Cancel pending I/O. */ 471 ure_stop(sc); 472 473 if (ure_rx_list_init(sc) == ENOBUFS) { 474 printf("%s: rx list init failed\n", sc->ure_dev.dv_xname); 475 splx(s); 476 return; 477 } 478 479 if (ure_tx_list_init(sc) == ENOBUFS) { 480 printf("%s: tx list init failed\n", sc->ure_dev.dv_xname); 481 splx(s); 482 return; 483 } 484 485 /* Set MAC address. */ 486 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 487 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 488 sc->ure_ac.ac_enaddr, 8); 489 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 490 491 /* Reset the packet filter. */ 492 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, 493 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) & 494 ~URE_FMC_FCR_MCU_EN); 495 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, 496 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) | 497 URE_FMC_FCR_MCU_EN); 498 499 /* Enable transmit and receive. */ 500 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 501 ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | 502 URE_CR_TE); 503 504 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 505 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & 506 ~URE_RXDY_GATED_EN); 507 508 /* Load the multicast filter. */ 509 ure_iff(sc); 510 511 /* Open RX and TX pipes. */ 512 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_RX], 513 USBD_EXCLUSIVE_USE, &sc->ure_ep[URE_ENDPT_RX]); 514 if (err) { 515 printf("%s: open rx pipe failed: %s\n", 516 sc->ure_dev.dv_xname, usbd_errstr(err)); 517 splx(s); 518 return; 519 } 520 521 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_TX], 522 USBD_EXCLUSIVE_USE, &sc->ure_ep[URE_ENDPT_TX]); 523 if (err) { 524 printf("%s: open tx pipe failed: %s\n", 525 sc->ure_dev.dv_xname, usbd_errstr(err)); 526 splx(s); 527 return; 528 } 529 530 /* Start up the receive pipe. */ 531 for (i = 0; i < URE_RX_LIST_CNT; i++) { 532 c = &sc->ure_cdata.rx_chain[i]; 533 usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_RX], 534 c, c->uc_buf, sc->ure_bufsz, 535 USBD_SHORT_XFER_OK | USBD_NO_COPY, 536 USBD_NO_TIMEOUT, ure_rxeof); 537 usbd_transfer(c->uc_xfer); 538 } 539 540 /* Indicate we are up and running. */ 541 ifp->if_flags |= IFF_RUNNING; 542 ifq_clr_oactive(&ifp->if_snd); 543 544 timeout_add_sec(&sc->ure_stat_ch, 1); 545 546 splx(s); 547 } 548 549 void 550 ure_start(struct ifnet *ifp) 551 { 552 struct ure_softc *sc = ifp->if_softc; 553 struct mbuf *m_head = NULL; 554 555 if ((sc->ure_flags & URE_FLAG_LINK) == 0 || 556 ifq_is_oactive(&ifp->if_snd)) { 557 return; 558 } 559 560 m_head = ifq_deq_begin(&ifp->if_snd); 561 if (m_head == NULL) { 562 return; 563 } 564 565 if (ure_encap(sc, m_head, 0)) { 566 ifq_deq_rollback(&ifp->if_snd, m_head); 567 ifq_set_oactive(&ifp->if_snd); 568 return; 569 } 570 ifq_deq_commit(&ifp->if_snd, m_head); 571 572 #if NBPFILTER > 0 573 if (ifp->if_bpf) 574 bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 575 #endif 576 ifq_set_oactive(&ifp->if_snd); 577 } 578 579 void 580 ure_tick(void *xsc) 581 { 582 struct ure_softc *sc = xsc; 583 584 if (sc == NULL) 585 return; 586 587 if (usbd_is_dying(sc->ure_udev)) 588 return; 589 590 usb_add_task(sc->ure_udev, &sc->ure_tick_task); 591 } 592 593 void 594 ure_stop(struct ure_softc *sc) 595 { 596 usbd_status err; 597 struct ifnet *ifp; 598 int i; 599 600 ure_reset(sc); 601 602 ifp = &sc->ure_ac.ac_if; 603 ifp->if_timer = 0; 604 ifp->if_flags &= ~IFF_RUNNING; 605 ifq_clr_oactive(&ifp->if_snd); 606 607 timeout_del(&sc->ure_stat_ch); 608 609 if (sc->ure_ep[URE_ENDPT_RX] != NULL) { 610 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_RX]); 611 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_RX]); 612 if (err) { 613 printf("%s: close rx pipe failed: %s\n", 614 sc->ure_dev.dv_xname, usbd_errstr(err)); 615 } 616 sc->ure_ep[URE_ENDPT_RX] = NULL; 617 } 618 619 if (sc->ure_ep[URE_ENDPT_TX] != NULL) { 620 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_TX]); 621 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_TX]); 622 if (err) { 623 printf("%s: close tx pipe failed: %s\n", 624 sc->ure_dev.dv_xname, usbd_errstr(err)); 625 } 626 sc->ure_ep[URE_ENDPT_TX] = NULL; 627 } 628 629 for (i = 0; i < URE_RX_LIST_CNT; i++) { 630 if (sc->ure_cdata.rx_chain[i].uc_mbuf != NULL) { 631 m_freem(sc->ure_cdata.rx_chain[i].uc_mbuf); 632 sc->ure_cdata.rx_chain[i].uc_mbuf = NULL; 633 } 634 if (sc->ure_cdata.rx_chain[i].uc_xfer != NULL) { 635 usbd_free_xfer(sc->ure_cdata.rx_chain[i].uc_xfer); 636 sc->ure_cdata.rx_chain[i].uc_xfer = NULL; 637 } 638 } 639 640 for (i = 0; i < URE_TX_LIST_CNT; i++) { 641 if (sc->ure_cdata.tx_chain[i].uc_mbuf != NULL) { 642 m_freem(sc->ure_cdata.tx_chain[i].uc_mbuf); 643 sc->ure_cdata.tx_chain[i].uc_mbuf = NULL; 644 } 645 if (sc->ure_cdata.tx_chain[i].uc_xfer != NULL) { 646 usbd_free_xfer(sc->ure_cdata.tx_chain[i].uc_xfer); 647 sc->ure_cdata.tx_chain[i].uc_xfer = NULL; 648 } 649 } 650 } 651 652 void 653 ure_rtl8152_init(struct ure_softc *sc) 654 { 655 uint32_t pwrctrl; 656 657 /* Disable ALDPS. */ 658 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 659 URE_DIS_SDSAVE); 660 usbd_delay_ms(sc->ure_udev, 20); 661 662 if (sc->ure_chip & URE_CHIP_VER_4C00) { 663 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 664 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 665 ~URE_LED_MODE_MASK); 666 } 667 668 ure_write_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, 669 ure_read_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & 670 ~URE_POWER_CUT); 671 ure_write_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 672 ure_read_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & 673 ~URE_RESUME_INDICATE); 674 675 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 676 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 677 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 678 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 679 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 680 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 681 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 682 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 683 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 684 URE_SPDWN_LINKCHG_MSK); 685 686 /* Enable Rx aggregation. */ 687 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 688 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 689 ~URE_RX_AGG_DISABLE); 690 691 /* Disable ALDPS. */ 692 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 693 URE_DIS_SDSAVE); 694 usbd_delay_ms(sc->ure_udev, 20); 695 696 ure_init_fifo(sc); 697 698 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 699 URE_TX_AGG_MAX_THRESHOLD); 700 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 701 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 702 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 703 } 704 705 void 706 ure_rtl8153_init(struct ure_softc *sc) 707 { 708 uint16_t val; 709 uint8_t u1u2[8]; 710 int i; 711 712 /* Disable ALDPS. */ 713 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 714 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 715 usbd_delay_ms(sc->ure_udev, 20); 716 717 memset(u1u2, 0x00, sizeof(u1u2)); 718 ure_write_mem(sc, URE_USB_TOLERANCE, 719 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 720 721 for (i = 0; i < URE_TIMEOUT; i++) { 722 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 723 URE_AUTOLOAD_DONE) 724 break; 725 usbd_delay_ms(sc->ure_udev, 10); 726 } 727 if (i == URE_TIMEOUT) 728 printf("%s: timeout waiting for chip autoload\n", 729 sc->ure_dev.dv_xname); 730 731 for (i = 0; i < URE_TIMEOUT; i++) { 732 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & 733 URE_PHY_STAT_MASK; 734 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 735 break; 736 usbd_delay_ms(sc->ure_udev, 10); 737 } 738 if (i == URE_TIMEOUT) 739 printf("%s: timeout waiting for phy to stabilize\n", 740 sc->ure_dev.dv_xname); 741 742 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 743 ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) & 744 ~URE_U2P3_ENABLE); 745 746 if (sc->ure_chip & URE_CHIP_VER_5C10) { 747 val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 748 val &= ~URE_PWD_DN_SCALE_MASK; 749 val |= URE_PWD_DN_SCALE(96); 750 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 751 752 ure_write_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 753 ure_read_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB) | 754 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 755 } else if (sc->ure_chip & URE_CHIP_VER_5C20) { 756 ure_write_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 757 ure_read_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) & 758 ~URE_ECM_ALDPS); 759 } 760 if (sc->ure_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) { 761 val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 762 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 763 0) 764 val &= ~URE_DYNAMIC_BURST; 765 else 766 val |= URE_DYNAMIC_BURST; 767 ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 768 } 769 770 ure_write_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, 771 ure_read_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) | 772 URE_EP4_FULL_FC); 773 774 ure_write_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, 775 ure_read_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) & 776 ~URE_TIMER11_EN); 777 778 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 779 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 780 ~URE_LED_MODE_MASK); 781 782 if ((sc->ure_chip & URE_CHIP_VER_5C10) && 783 sc->ure_udev->speed != USB_SPEED_SUPER) 784 val = URE_LPM_TIMER_500MS; 785 else 786 val = URE_LPM_TIMER_500US; 787 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 788 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 789 790 val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 791 val &= ~URE_SEN_VAL_MASK; 792 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 793 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 794 795 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 796 797 ure_write_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 798 ure_read_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) & 799 ~(URE_PWR_EN | URE_PHASE2_EN)); 800 ure_write_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, 801 ure_read_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB) & 802 ~URE_PCUT_STATUS); 803 804 memset(u1u2, 0xff, sizeof(u1u2)); 805 ure_write_mem(sc, URE_USB_TOLERANCE, 806 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 807 808 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 809 URE_ALDPS_SPDWN_RATIO); 810 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 811 URE_EEE_SPDWN_RATIO); 812 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 813 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 814 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 815 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 816 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 817 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 818 URE_EEE_SPDWN_EN); 819 820 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 821 if (!(sc->ure_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 822 val |= URE_U2P3_ENABLE; 823 else 824 val &= ~URE_U2P3_ENABLE; 825 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 826 827 memset(u1u2, 0x00, sizeof(u1u2)); 828 ure_write_mem(sc, URE_USB_TOLERANCE, 829 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 830 831 /* Disable ALDPS. */ 832 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 833 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 834 usbd_delay_ms(sc->ure_udev, 20); 835 836 ure_init_fifo(sc); 837 838 /* Enable Rx aggregation. */ 839 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 840 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 841 ~URE_RX_AGG_DISABLE); 842 843 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 844 if (!(sc->ure_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 845 val |= URE_U2P3_ENABLE; 846 else 847 val &= ~URE_U2P3_ENABLE; 848 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 849 850 memset(u1u2, 0xff, sizeof(u1u2)); 851 ure_write_mem(sc, URE_USB_TOLERANCE, 852 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 853 } 854 855 void 856 ure_disable_teredo(struct ure_softc *sc) 857 { 858 ure_write_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 859 ure_read_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & 860 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 861 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, 862 URE_WDT6_SET_MODE); 863 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 864 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 865 } 866 867 void 868 ure_init_fifo(struct ure_softc *sc) 869 { 870 uint32_t rx_fifo1, rx_fifo2; 871 int i; 872 873 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 874 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | 875 URE_RXDY_GATED_EN); 876 877 ure_disable_teredo(sc); 878 879 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, 880 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA) & 881 ~URE_RCR_ACPT_ALL); 882 883 if (!(sc->ure_flags & URE_FLAG_8152)) { 884 if (sc->ure_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 | 885 URE_CHIP_VER_5C20)) { 886 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG, 887 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 888 } 889 if (sc->ure_chip & URE_CHIP_VER_5C00) { 890 ure_ocp_reg_write(sc, URE_OCP_EEE_CFG, 891 ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) & 892 ~URE_CTAP_SHORT_EN); 893 } 894 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 895 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 896 URE_EEE_CLKDIV_EN); 897 ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED, 898 ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) | 899 URE_EN_10M_BGOFF); 900 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 901 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 902 URE_EN_10M_PLLOFF); 903 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE); 904 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0b13); 905 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 906 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 907 URE_PFM_PWM_SWITCH); 908 909 /* Enable LPF corner auto tune. */ 910 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG); 911 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0xf70f); 912 913 /* Adjust 10M amplitude. */ 914 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1); 915 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x00af); 916 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2); 917 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0208); 918 } 919 920 ure_reset(sc); 921 922 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 923 924 ure_write_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, 925 ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 926 ~URE_NOW_IS_OOB); 927 928 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 929 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & 930 ~URE_MCU_BORW_EN); 931 for (i = 0; i < URE_TIMEOUT; i++) { 932 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 933 URE_LINK_LIST_READY) 934 break; 935 usbd_delay_ms(sc->ure_udev, 10); 936 } 937 if (i == URE_TIMEOUT) 938 printf("%s: timeout waiting for OOB control\n", 939 sc->ure_dev.dv_xname); 940 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 941 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | 942 URE_RE_INIT_LL); 943 for (i = 0; i < URE_TIMEOUT; i++) { 944 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 945 URE_LINK_LIST_READY) 946 break; 947 usbd_delay_ms(sc->ure_udev, 10); 948 } 949 if (i == URE_TIMEOUT) 950 printf("%s: timeout waiting for OOB control\n", 951 sc->ure_dev.dv_xname); 952 953 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 954 ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & 955 ~URE_CPCR_RX_VLAN); 956 ure_write_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 957 ure_read_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | 958 URE_TCR0_AUTO_FIFO); 959 960 /* Configure Rx FIFO threshold and coalescing. */ 961 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 962 URE_RXFIFO_THR1_NORMAL); 963 if (sc->ure_udev->speed == USB_SPEED_FULL) { 964 rx_fifo1 = URE_RXFIFO_THR2_FULL; 965 rx_fifo2 = URE_RXFIFO_THR3_FULL; 966 } else { 967 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 968 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 969 } 970 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 971 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 972 973 /* Configure Tx FIFO threshold. */ 974 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 975 URE_TXFIFO_THR_NORMAL); 976 } 977 978 int 979 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 980 { 981 struct ure_softc *sc = ifp->if_softc; 982 struct ifreq *ifr = (struct ifreq *)data; 983 int s, error = 0; 984 985 s = splnet(); 986 987 switch (cmd) { 988 case SIOCSIFADDR: 989 ifp->if_flags |= IFF_UP; 990 if (!(ifp->if_flags & IFF_RUNNING)) 991 ure_init(sc); 992 break; 993 994 case SIOCSIFFLAGS: 995 if (ifp->if_flags & IFF_UP) { 996 if (ifp->if_flags & IFF_RUNNING) 997 error = ENETRESET; 998 else 999 ure_init(sc); 1000 } else { 1001 if (ifp->if_flags & IFF_RUNNING) 1002 ure_stop(sc); 1003 } 1004 break; 1005 1006 case SIOCGIFMEDIA: 1007 case SIOCSIFMEDIA: 1008 error = ifmedia_ioctl(ifp, ifr, &sc->ure_mii.mii_media, cmd); 1009 break; 1010 1011 default: 1012 error = ether_ioctl(ifp, &sc->ure_ac, cmd, data); 1013 } 1014 1015 if (error == ENETRESET) { 1016 if (ifp->if_flags & IFF_RUNNING) 1017 ure_iff(sc); 1018 error = 0; 1019 } 1020 1021 splx(s); 1022 1023 return (error); 1024 } 1025 1026 int 1027 ure_match(struct device *parent, void *match, void *aux) 1028 { 1029 struct usb_attach_arg *uaa = aux; 1030 1031 /* 1032 if (uaa->configno != URE_CONFIG_IDX) 1033 return UMATCH_NONE; 1034 if (uaa->ifaceno != URE_IFACE_IDX) 1035 return UMATCH_NONE; 1036 */ 1037 if (uaa->iface == NULL || uaa->configno != 1) 1038 return UMATCH_NONE; 1039 1040 return (usb_lookup(ure_devs, uaa->vendor, uaa->product) != NULL ? 1041 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 1042 } 1043 1044 void 1045 ure_attach(struct device *parent, struct device *self, void *aux) 1046 { 1047 struct ure_softc *sc = (struct ure_softc *)self; 1048 struct usb_attach_arg *uaa = aux; 1049 usb_interface_descriptor_t *id; 1050 usb_endpoint_descriptor_t *ed; 1051 struct mii_data *mii; 1052 u_char eaddr[8]; /* 4byte padded */ 1053 struct ifnet *ifp; 1054 int i, s; 1055 uint16_t ver; 1056 1057 sc->ure_udev = uaa->device; 1058 sc->ure_iface = uaa->iface; 1059 1060 if (uaa->product == USB_PRODUCT_REALTEK_RTL8152) 1061 sc->ure_flags |= URE_FLAG_8152; 1062 1063 usb_init_task(&sc->ure_tick_task, ure_tick_task, sc, 1064 USB_TASK_TYPE_GENERIC); 1065 rw_init(&sc->ure_mii_lock, "uremii"); 1066 usb_init_task(&sc->ure_stop_task, (void (*)(void *))ure_stop, sc, 1067 USB_TASK_TYPE_GENERIC); 1068 1069 id = usbd_get_interface_descriptor(sc->ure_iface); 1070 1071 sc->ure_bufsz = 16 * 1024; 1072 1073 for (i = 0; i < id->bNumEndpoints; i++) { 1074 ed = usbd_interface2endpoint_descriptor(sc->ure_iface, i); 1075 if (!ed) { 1076 printf("%s: couldn't get ep %d\n", 1077 sc->ure_dev.dv_xname, i); 1078 return; 1079 } 1080 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 1081 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 1082 sc->ure_ed[URE_ENDPT_RX] = ed->bEndpointAddress; 1083 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 1084 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 1085 sc->ure_ed[URE_ENDPT_TX] = ed->bEndpointAddress; 1086 } 1087 } 1088 1089 s = splnet(); 1090 1091 sc->ure_phyno = 0; 1092 printf("%s: ", sc->ure_dev.dv_xname); 1093 1094 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 1095 switch (ver) { 1096 case 0x4c00: 1097 sc->ure_chip |= URE_CHIP_VER_4C00; 1098 printf("ver 4c00"); 1099 break; 1100 case 0x4c10: 1101 sc->ure_chip |= URE_CHIP_VER_4C10; 1102 printf("ver 4c10"); 1103 break; 1104 case 0x5c00: 1105 sc->ure_chip |= URE_CHIP_VER_5C00; 1106 printf("ver 5c00"); 1107 break; 1108 case 0x5c10: 1109 sc->ure_chip |= URE_CHIP_VER_5C10; 1110 printf("ver 5c10"); 1111 break; 1112 case 0x5c20: 1113 sc->ure_chip |= URE_CHIP_VER_5C20; 1114 printf("ver 5c20"); 1115 break; 1116 case 0x5c30: 1117 sc->ure_chip |= URE_CHIP_VER_5C30; 1118 printf("ver 5c30"); 1119 break; 1120 default: 1121 printf(", unknown ver %02x", ver); 1122 /* fake addr? or just fail? */ 1123 break; 1124 } 1125 1126 if (sc->ure_flags & URE_FLAG_8152) 1127 ure_rtl8152_init(sc); 1128 else 1129 ure_rtl8153_init(sc); 1130 1131 if (sc->ure_chip & URE_CHIP_VER_4C00) 1132 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr, 1133 sizeof(eaddr)); 1134 else 1135 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr, 1136 sizeof(eaddr)); 1137 1138 printf(", address %s\n", ether_sprintf(eaddr)); 1139 1140 bcopy(eaddr, (char *)&sc->ure_ac.ac_enaddr, ETHER_ADDR_LEN); 1141 1142 ifp = &sc->ure_ac.ac_if; 1143 ifp->if_softc = sc; 1144 strlcpy(ifp->if_xname, sc->ure_dev.dv_xname, IFNAMSIZ); 1145 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1146 ifp->if_ioctl = ure_ioctl; 1147 ifp->if_start = ure_start; 1148 ifp->if_capabilities = 0; 1149 1150 mii = &sc->ure_mii; 1151 mii->mii_ifp = ifp; 1152 mii->mii_readreg = ure_miibus_readreg; 1153 mii->mii_writereg = ure_miibus_writereg; 1154 mii->mii_statchg = ure_miibus_statchg; 1155 mii->mii_flags = MIIF_AUTOTSLEEP; 1156 1157 ifmedia_init(&mii->mii_media, 0, ure_ifmedia_upd, ure_ifmedia_sts); 1158 mii_attach(self, mii, 0xffffffff, sc->ure_phyno, MII_OFFSET_ANY, 0); 1159 1160 if (LIST_FIRST(&mii->mii_phys) == NULL) { 1161 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 1162 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 1163 } else 1164 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 1165 1166 if_attach(ifp); 1167 ether_ifattach(ifp); 1168 1169 timeout_set(&sc->ure_stat_ch, ure_tick, sc); 1170 1171 splx(s); 1172 } 1173 1174 int 1175 ure_detach(struct device *self, int flags) 1176 { 1177 struct ure_softc *sc = (struct ure_softc *)self; 1178 struct ifnet *ifp = &sc->ure_ac.ac_if; 1179 int s; 1180 1181 if (timeout_initialized(&sc->ure_stat_ch)) 1182 timeout_del(&sc->ure_stat_ch); 1183 1184 if (sc->ure_ep[URE_ENDPT_TX] != NULL) 1185 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_TX]); 1186 if (sc->ure_ep[URE_ENDPT_RX] != NULL) 1187 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_RX]); 1188 1189 usb_rem_task(sc->ure_udev, &sc->ure_tick_task); 1190 usb_rem_task(sc->ure_udev, &sc->ure_stop_task); 1191 1192 s = splusb(); 1193 1194 if (--sc->ure_refcnt >= 0) { 1195 usb_detach_wait(&sc->ure_dev); 1196 } 1197 1198 if (ifp->if_flags & IFF_RUNNING) 1199 ure_stop(sc); 1200 1201 mii_detach(&sc->ure_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1202 ifmedia_delete_instance(&sc->ure_mii.mii_media, IFM_INST_ANY); 1203 if (ifp->if_softc != NULL) { 1204 ether_ifdetach(ifp); 1205 if_detach(ifp); 1206 } 1207 1208 splx(s); 1209 1210 return 0; 1211 } 1212 1213 void 1214 ure_tick_task(void *xsc) 1215 { 1216 int s; 1217 struct ure_softc *sc = xsc; 1218 struct mii_data *mii; 1219 1220 if (sc == NULL) 1221 return; 1222 1223 if (usbd_is_dying(sc->ure_udev)) 1224 return; 1225 mii = &sc->ure_mii; 1226 1227 s = splnet(); 1228 mii_tick(mii); 1229 if ((sc->ure_flags & URE_FLAG_LINK) == 0) 1230 ure_miibus_statchg(&sc->ure_dev); 1231 timeout_add_sec(&sc->ure_stat_ch, 1); 1232 splx(s); 1233 } 1234 1235 void 1236 ure_lock_mii(struct ure_softc *sc) 1237 { 1238 sc->ure_refcnt++; 1239 rw_enter_write(&sc->ure_mii_lock); 1240 } 1241 1242 void 1243 ure_unlock_mii(struct ure_softc *sc) 1244 { 1245 rw_exit_write(&sc->ure_mii_lock); 1246 if (--sc->ure_refcnt < 0) 1247 usb_detach_wakeup(&sc->ure_dev); 1248 } 1249 1250 void 1251 ure_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1252 { 1253 struct ure_chain *c = (struct ure_chain *)priv; 1254 struct ure_softc *sc = c->uc_sc; 1255 struct ifnet *ifp = &sc->ure_ac.ac_if; 1256 u_char *buf = c->uc_buf; 1257 uint32_t total_len; 1258 uint16_t pktlen = 0; 1259 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1260 struct mbuf *m; 1261 int s; 1262 struct ure_rxpkt rxhdr; 1263 1264 if (usbd_is_dying(sc->ure_udev)) 1265 return; 1266 1267 if (!(ifp->if_flags & IFF_RUNNING)) 1268 return; 1269 1270 if (status != USBD_NORMAL_COMPLETION) { 1271 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 1272 return; 1273 if (usbd_ratecheck(&sc->ure_rx_notice)) { 1274 printf("%s: usb errors on rx: %s\n", 1275 sc->ure_dev.dv_xname, usbd_errstr(status)); 1276 } 1277 if (status == USBD_STALLED) 1278 usbd_clear_endpoint_stall_async(sc->ure_ep[URE_ENDPT_RX]); 1279 goto done; 1280 } 1281 1282 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL); 1283 DPRINTFN(3, ("received %d bytes\n", total_len)); 1284 1285 do { 1286 if (total_len < sizeof(rxhdr)) { 1287 DPRINTF(("too few bytes left for a packet header\n")); 1288 ifp->if_ierrors++; 1289 goto done; 1290 } 1291 1292 buf += roundup(pktlen, 8); 1293 1294 memcpy(&rxhdr, buf, sizeof(rxhdr)); 1295 total_len -= sizeof(rxhdr); 1296 1297 pktlen = lemtoh32(&rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK; 1298 DPRINTFN(4, ("next packet is %d bytes\n", pktlen)); 1299 if (pktlen > total_len) { 1300 DPRINTF(("not enough bytes left for next packet\n")); 1301 ifp->if_ierrors++; 1302 goto done; 1303 } 1304 1305 total_len -= roundup(pktlen, 8); 1306 buf += sizeof(rxhdr); 1307 1308 m = m_devget(buf, pktlen, ETHER_ALIGN); 1309 if (m == NULL) { 1310 DPRINTF(("unable to allocate mbuf for next packet\n")); 1311 ifp->if_ierrors++; 1312 goto done; 1313 } 1314 1315 ml_enqueue(&ml, m); 1316 } while (total_len > 0); 1317 1318 done: 1319 s = splnet(); 1320 if_input(ifp, &ml); 1321 splx(s); 1322 memset(c->uc_buf, 0, sc->ure_bufsz); 1323 1324 usbd_setup_xfer(xfer, sc->ure_ep[URE_ENDPT_RX], c, c->uc_buf, 1325 sc->ure_bufsz, USBD_SHORT_XFER_OK | USBD_NO_COPY, 1326 USBD_NO_TIMEOUT, ure_rxeof); 1327 usbd_transfer(xfer); 1328 } 1329 1330 1331 void 1332 ure_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1333 { 1334 struct ure_softc *sc; 1335 struct ure_chain *c; 1336 struct ifnet *ifp; 1337 int s; 1338 1339 c = priv; 1340 sc = c->uc_sc; 1341 ifp = &sc->ure_ac.ac_if; 1342 1343 if (usbd_is_dying(sc->ure_udev)) 1344 return; 1345 1346 DPRINTFN(2, ("tx completion\n")); 1347 1348 s = splnet(); 1349 1350 if (status != USBD_NORMAL_COMPLETION) { 1351 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) { 1352 splx(s); 1353 return; 1354 } 1355 ifp->if_oerrors++; 1356 printf("%s: usb error on tx: %s\n", sc->ure_dev.dv_xname, 1357 usbd_errstr(status)); 1358 if (status == USBD_STALLED) 1359 usbd_clear_endpoint_stall_async(sc->ure_ep[URE_ENDPT_TX]); 1360 splx(s); 1361 return; 1362 } 1363 1364 ifp->if_timer = 0; 1365 ifq_clr_oactive(&ifp->if_snd); 1366 1367 m_freem(c->uc_mbuf); 1368 c->uc_mbuf = NULL; 1369 1370 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 1371 ure_start(ifp); 1372 1373 splx(s); 1374 1375 } 1376 1377 int 1378 ure_tx_list_init(struct ure_softc *sc) 1379 { 1380 struct ure_cdata *cd; 1381 struct ure_chain *c; 1382 int i; 1383 1384 cd = &sc->ure_cdata; 1385 for (i = 0; i < URE_TX_LIST_CNT; i++) { 1386 c = &cd->tx_chain[i]; 1387 c->uc_sc = sc; 1388 c->uc_idx = i; 1389 c->uc_mbuf = NULL; 1390 if (c->uc_xfer == NULL) { 1391 c->uc_xfer = usbd_alloc_xfer(sc->ure_udev); 1392 if (c->uc_xfer == NULL) 1393 return ENOBUFS; 1394 c->uc_buf = usbd_alloc_buffer(c->uc_xfer, 1395 sc->ure_bufsz); 1396 if (c->uc_buf == NULL) { 1397 usbd_free_xfer(c->uc_xfer); 1398 return ENOBUFS; 1399 } 1400 } 1401 } 1402 1403 return 0; 1404 } 1405 1406 int 1407 ure_rx_list_init(struct ure_softc *sc) 1408 { 1409 struct ure_cdata *cd; 1410 struct ure_chain *c; 1411 int i; 1412 1413 cd = &sc->ure_cdata; 1414 for (i = 0; i < URE_RX_LIST_CNT; i++) { 1415 c = &cd->rx_chain[i]; 1416 c->uc_sc = sc; 1417 c->uc_idx = i; 1418 c->uc_mbuf = NULL; 1419 if (c->uc_xfer == NULL) { 1420 c->uc_xfer = usbd_alloc_xfer(sc->ure_udev); 1421 if (c->uc_xfer == NULL) 1422 return ENOBUFS; 1423 c->uc_buf = usbd_alloc_buffer(c->uc_xfer, 1424 sc->ure_bufsz); 1425 if (c->uc_buf == NULL) { 1426 usbd_free_xfer(c->uc_xfer); 1427 return ENOBUFS; 1428 } 1429 } 1430 } 1431 1432 return 0; 1433 } 1434 1435 int 1436 ure_encap(struct ure_softc *sc, struct mbuf *m, int idx) 1437 { 1438 struct ure_chain *c; 1439 usbd_status err; 1440 struct ure_txpkt txhdr; 1441 uint32_t frm_len = 0; 1442 u_char *buf; 1443 1444 c = &sc->ure_cdata.tx_chain[idx]; 1445 buf = c->uc_buf; 1446 1447 /* header */ 1448 htolem32(&txhdr.ure_pktlen, m->m_pkthdr.len | URE_TXPKT_TX_FS | 1449 URE_TXPKT_TX_LS); 1450 txhdr.ure_rsvd0 = 0; 1451 memcpy(buf, &txhdr, sizeof(txhdr)); 1452 buf += sizeof(txhdr); 1453 frm_len = sizeof(txhdr); 1454 1455 /* packet */ 1456 m_copydata(m, 0, m->m_pkthdr.len, buf); 1457 frm_len += m->m_pkthdr.len; 1458 1459 c->uc_mbuf = m; 1460 1461 DPRINTFN(2, ("tx %d bytes\n", frm_len)); 1462 usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_TX], c, c->uc_buf, 1463 frm_len, USBD_FORCE_SHORT_XFER | USBD_NO_COPY, 10000, ure_txeof); 1464 1465 err = usbd_transfer(c->uc_xfer); 1466 if (err != USBD_IN_PROGRESS) { 1467 ure_stop(sc); 1468 return EIO; 1469 } 1470 1471 sc->ure_cdata.tx_cnt++; 1472 return 0; 1473 } 1474