1 /* $OpenBSD: if_ure.c,v 1.35 2024/05/23 03:21:09 jsg Exp $ */ 2 /*- 3 * Copyright (c) 2015, 2016, 2019 Kevin Lo <kevlo@openbsd.org> 4 * Copyright (c) 2020 Jonathon Fletcher <jonathon.fletcher@gmail.com> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "bpfilter.h" 30 #include "vlan.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/sockio.h> 35 #include <sys/rwlock.h> 36 #include <sys/mbuf.h> 37 #include <sys/device.h> 38 39 #include <machine/bus.h> 40 41 #include <net/if.h> 42 #include <net/if_media.h> 43 44 #if NBPFILTER > 0 45 #include <net/bpf.h> 46 #endif 47 48 #include <netinet/in.h> 49 #include <netinet/if_ether.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 54 #include <dev/usb/usb.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdi_util.h> 57 #include <dev/usb/usbdivar.h> 58 #include <dev/usb/usbdevs.h> 59 60 #include <dev/ic/rtl81x9reg.h> 61 #include <dev/usb/if_urereg.h> 62 63 #ifdef URE_DEBUG 64 #define DPRINTF(x) do { if (uredebug) printf x; } while (0) 65 #define DPRINTFN(n,x) do { if (uredebug >= (n)) printf x; } while (0) 66 int uredebug = 0; 67 #else 68 #define DPRINTF(x) 69 #define DPRINTFN(n,x) 70 #endif 71 72 const struct usb_devno ure_devs[] = { 73 { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_RTL8156 }, 74 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8152B }, 75 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8153 }, 76 { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB3GIGV1 }, 77 { USB_VENDOR_CLEVO, USB_PRODUCT_CLEVO_RTL8153B }, 78 { USB_VENDOR_CLUB3D, USB_PRODUCT_CLUB3D_RTL8153 }, 79 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8153_1 }, 80 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8153_2 }, 81 { USB_VENDOR_DYNABOOK, USB_PRODUCT_DYNABOOK_RTL8153B_1 }, 82 { USB_VENDOR_DYNABOOK, USB_PRODUCT_DYNABOOK_RTL8153B_2 }, 83 { USB_VENDOR_ELECOM, USB_PRODUCT_ELECOM_RTL8153B }, 84 { USB_VENDOR_ELECOM, USB_PRODUCT_ELECOM_RTL8156B }, 85 { USB_VENDOR_IOI, USB_PRODUCT_IOI_RTL8153 }, 86 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_DOCK_ETHERNET }, 87 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ONELINK }, 88 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ONELINKPLUS }, 89 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ONELINKPRO }, 90 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_1 }, 91 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_2 }, 92 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_3 }, 93 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_4 }, 94 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_5 }, 95 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_6 }, 96 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_7 }, 97 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_8 }, 98 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_9 }, 99 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153_1 }, 100 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153_2 }, 101 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153_3 }, 102 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TABLETDOCK }, 103 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TB3DOCK }, 104 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TB3DOCKGEN2 }, 105 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TB3GFXDOCK }, 106 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_USBCDOCKGEN2 }, 107 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_WIGIGDOCK }, 108 { USB_VENDOR_LG, USB_PRODUCT_LG_RTL8153 }, 109 { USB_VENDOR_LG, USB_PRODUCT_LG_RTL8153B }, 110 { USB_VENDOR_LUXSHARE, USB_PRODUCT_LUXSHARE_RTL8153 }, 111 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_DOCKETH }, 112 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_DOCKETH2 }, 113 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_SURFETH }, 114 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_WINDEVETH }, 115 { USB_VENDOR_NVIDIA, USB_PRODUCT_NVIDIA_TEGRAETH }, 116 { USB_VENDOR_PIONEERDJ, USB_PRODUCT_PIONEERDJ_RTL8152B }, 117 { USB_VENDOR_PIONEERDJ, USB_PRODUCT_PIONEERDJ_RTL8153B }, 118 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 }, 119 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152B }, 120 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8153 }, 121 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8156 }, 122 { USB_VENDOR_SAMSUNG2, USB_PRODUCT_SAMSUNG2_RTL8153 }, 123 { USB_VENDOR_TOSHIBA, USB_PRODUCT_TOSHIBA_RTL8153B }, 124 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_EU300 }, 125 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_RTL8152B_1 }, 126 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_RTL8152B_2 }, 127 { USB_VENDOR_TRENDNET, USB_PRODUCT_TRENDNET_RTL8156 }, 128 { USB_VENDOR_TTL, USB_PRODUCT_TTL_RTL8153 }, 129 { USB_VENDOR_TWINHEAD, USB_PRODUCT_TWINHEAD_RTL8153B }, 130 { USB_VENDOR_XIAOMI, USB_PRODUCT_XIAOMI_RTL8152B }, 131 }; 132 133 int ure_match(struct device *, void *, void *); 134 void ure_attach(struct device *, struct device *, void *); 135 int ure_detach(struct device *, int); 136 137 struct cfdriver ure_cd = { 138 NULL, "ure", DV_IFNET 139 }; 140 141 const struct cfattach ure_ca = { 142 sizeof(struct ure_softc), ure_match, ure_attach, ure_detach 143 }; 144 145 int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t, 146 void *, int); 147 int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *, 148 int); 149 int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *, 150 int); 151 uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t); 152 uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t); 153 uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t); 154 int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t); 155 int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t); 156 int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t); 157 uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t); 158 void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t); 159 160 void ure_init(void *); 161 void ure_stop(struct ure_softc *); 162 void ure_start(struct ifnet *); 163 void ure_reset(struct ure_softc *); 164 void ure_watchdog(struct ifnet *); 165 166 void ure_miibus_statchg(struct device *); 167 int ure_miibus_readreg(struct device *, int, int); 168 void ure_miibus_writereg(struct device *, int, int, int); 169 void ure_lock_mii(struct ure_softc *); 170 void ure_unlock_mii(struct ure_softc *); 171 172 int ure_encap_txpkt(struct mbuf *, char *, uint32_t); 173 int ure_encap_xfer(struct ifnet *, struct ure_softc *, 174 struct ure_chain *); 175 void ure_rxeof(struct usbd_xfer *, void *, usbd_status); 176 void ure_txeof(struct usbd_xfer *, void *, usbd_status); 177 int ure_xfer_list_init(struct ure_softc *, struct ure_chain *, 178 uint32_t, int); 179 void ure_xfer_list_free(struct ure_softc *, struct ure_chain *, int); 180 181 void ure_tick_task(void *); 182 void ure_tick(void *); 183 184 void ure_ifmedia_init(struct ifnet *); 185 int ure_ifmedia_upd(struct ifnet *); 186 void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *); 187 void ure_add_media_types(struct ure_softc *); 188 void ure_link_state(struct ure_softc *); 189 int ure_get_link_status(struct ure_softc *); 190 void ure_iff(struct ure_softc *); 191 void ure_rxvlan(struct ure_softc *); 192 int ure_ioctl(struct ifnet *, u_long, caddr_t); 193 void ure_rtl8152_init(struct ure_softc *); 194 void ure_rtl8153_init(struct ure_softc *); 195 void ure_rtl8153b_init(struct ure_softc *); 196 void ure_rtl8152_nic_reset(struct ure_softc *); 197 void ure_rtl8153_nic_reset(struct ure_softc *); 198 uint16_t ure_rtl8153_phy_status(struct ure_softc *, int); 199 void ure_wait_for_flash(struct ure_softc *); 200 void ure_reset_bmu(struct ure_softc *); 201 void ure_disable_teredo(struct ure_softc *); 202 203 #define URE_SETBIT_1(sc, reg, index, x) \ 204 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x)) 205 #define URE_SETBIT_2(sc, reg, index, x) \ 206 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x)) 207 #define URE_SETBIT_4(sc, reg, index, x) \ 208 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x)) 209 210 #define URE_CLRBIT_1(sc, reg, index, x) \ 211 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~(x)) 212 #define URE_CLRBIT_2(sc, reg, index, x) \ 213 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~(x)) 214 #define URE_CLRBIT_4(sc, reg, index, x) \ 215 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~(x)) 216 217 int 218 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index, 219 void *buf, int len) 220 { 221 usb_device_request_t req; 222 usbd_status err; 223 224 if (usbd_is_dying(sc->ure_udev)) 225 return 0; 226 227 if (rw == URE_CTL_WRITE) 228 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 229 else 230 req.bmRequestType = UT_READ_VENDOR_DEVICE; 231 req.bRequest = UR_SET_ADDRESS; 232 USETW(req.wValue, val); 233 USETW(req.wIndex, index); 234 USETW(req.wLength, len); 235 236 DPRINTFN(5, ("ure_ctl: rw %d, val 0x%04hu, index 0x%04hu, len %d\n", 237 rw, val, index, len)); 238 err = usbd_do_request(sc->ure_udev, &req, buf); 239 if (err) { 240 DPRINTF(("ure_ctl: error %d\n", err)); 241 return -1; 242 } 243 244 return 0; 245 } 246 247 int 248 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 249 void *buf, int len) 250 { 251 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len)); 252 } 253 254 int 255 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 256 void *buf, int len) 257 { 258 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len)); 259 } 260 261 uint8_t 262 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index) 263 { 264 uint32_t val; 265 uint8_t temp[4]; 266 uint8_t shift; 267 268 shift = (reg & 3) << 3; 269 reg &= ~3; 270 271 ure_read_mem(sc, reg, index, &temp, 4); 272 val = UGETDW(temp); 273 val >>= shift; 274 275 return (val & 0xff); 276 } 277 278 uint16_t 279 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index) 280 { 281 uint32_t val; 282 uint8_t temp[4]; 283 uint8_t shift; 284 285 shift = (reg & 2) << 3; 286 reg &= ~3; 287 288 ure_read_mem(sc, reg, index, &temp, 4); 289 val = UGETDW(temp); 290 val >>= shift; 291 292 return (val & 0xffff); 293 } 294 295 uint32_t 296 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index) 297 { 298 uint8_t temp[4]; 299 300 ure_read_mem(sc, reg, index, &temp, 4); 301 return (UGETDW(temp)); 302 } 303 304 int 305 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 306 { 307 uint16_t byen; 308 uint8_t temp[4]; 309 uint8_t shift; 310 311 byen = URE_BYTE_EN_BYTE; 312 shift = reg & 3; 313 val &= 0xff; 314 315 if (reg & 3) { 316 byen <<= shift; 317 val <<= (shift << 3); 318 reg &= ~3; 319 } 320 321 USETDW(temp, val); 322 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 323 } 324 325 int 326 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 327 { 328 uint16_t byen; 329 uint8_t temp[4]; 330 uint8_t shift; 331 332 byen = URE_BYTE_EN_WORD; 333 shift = reg & 2; 334 val &= 0xffff; 335 336 if (reg & 2) { 337 byen <<= shift; 338 val <<= (shift << 3); 339 reg &= ~3; 340 } 341 342 USETDW(temp, val); 343 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 344 } 345 346 int 347 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 348 { 349 uint8_t temp[4]; 350 351 USETDW(temp, val); 352 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4)); 353 } 354 355 uint16_t 356 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr) 357 { 358 uint16_t reg; 359 360 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 361 reg = (addr & 0x0fff) | 0xb000; 362 363 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA)); 364 } 365 366 void 367 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 368 { 369 uint16_t reg; 370 371 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 372 reg = (addr & 0x0fff) | 0xb000; 373 374 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data); 375 } 376 377 int 378 ure_miibus_readreg(struct device *dev, int phy, int reg) 379 { 380 struct ure_softc *sc = (void *)dev; 381 uint16_t val; 382 383 if (usbd_is_dying(sc->ure_udev)) 384 return 0; 385 386 /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */ 387 if (reg == RL_GMEDIASTAT) 388 return ure_read_1(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA); 389 390 ure_lock_mii(sc); 391 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2); 392 ure_unlock_mii(sc); 393 394 return val; /* letoh16? */ 395 } 396 397 void 398 ure_miibus_writereg(struct device *dev, int phy, int reg, int val) 399 { 400 struct ure_softc *sc = (void *)dev; 401 402 ure_lock_mii(sc); 403 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val); /* htole16? */ 404 ure_unlock_mii(sc); 405 } 406 407 void 408 ure_miibus_statchg(struct device *dev) 409 { 410 struct ure_softc *sc = (void *)dev; 411 struct mii_data *mii = &sc->ure_mii; 412 struct ifnet *ifp = &sc->ure_ac.ac_if; 413 414 if ((ifp->if_flags & IFF_RUNNING) == 0) 415 return; 416 417 sc->ure_flags &= ~URE_FLAG_LINK; 418 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 419 (IFM_ACTIVE | IFM_AVALID)) { 420 switch (IFM_SUBTYPE(mii->mii_media_active)) { 421 case IFM_10_T: 422 case IFM_100_TX: 423 sc->ure_flags |= URE_FLAG_LINK; 424 break; 425 case IFM_1000_T: 426 if ((sc->ure_flags & URE_FLAG_8152) != 0) 427 break; 428 sc->ure_flags |= URE_FLAG_LINK; 429 break; 430 default: 431 break; 432 } 433 } 434 435 /* Lost link, do nothing. */ 436 if ((sc->ure_flags & URE_FLAG_LINK) == 0) 437 return; 438 439 /* 440 * After a link change the media settings are getting reset on the 441 * hardware, and need to be re-initialized again for communication 442 * to continue work. 443 */ 444 ure_ifmedia_init(ifp); 445 } 446 447 void 448 ure_ifmedia_init(struct ifnet *ifp) 449 { 450 struct ure_softc *sc = ifp->if_softc; 451 uint32_t reg = 0; 452 453 /* Set MAC address. */ 454 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 455 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 456 sc->ure_ac.ac_enaddr, 8); 457 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 458 459 if (!(sc->ure_flags & URE_FLAG_8152)) { 460 if (sc->ure_flags & URE_FLAG_8156B) 461 URE_CLRBIT_2(sc, URE_USB_RX_AGGR_NUM, URE_MCU_TYPE_USB, 462 URE_RX_AGGR_NUM_MASK); 463 464 reg = sc->ure_rxbufsz - URE_FRAMELEN(ifp->if_mtu) - 465 sizeof(struct ure_rxpkt) - URE_RX_BUF_ALIGN; 466 if (sc->ure_flags & 467 (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) { 468 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, 469 reg / 8); 470 471 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 472 (sc->ure_flags & URE_FLAG_8153B) ? 158 : 80); 473 ure_write_2(sc, URE_USB_PM_CTRL_STATUS, 474 URE_MCU_TYPE_USB, 1875); 475 } else { 476 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, 477 reg / 4); 478 switch (sc->ure_udev->speed) { 479 case USB_SPEED_SUPER: 480 reg = URE_COALESCE_SUPER / 8; 481 break; 482 case USB_SPEED_HIGH: 483 reg = URE_COALESCE_HIGH / 8; 484 break; 485 default: 486 reg = URE_COALESCE_SLOW / 8; 487 break; 488 } 489 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 490 reg); 491 } 492 493 if (sc->ure_chip & URE_CHIP_VER_7420) { 494 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL4, 495 URE_MCU_TYPE_PLA, URE_IDLE_SPDWN_EN); 496 } 497 498 if ((sc->ure_chip & URE_CHIP_VER_6010) || 499 (sc->ure_flags & URE_FLAG_8156B)) { 500 URE_CLRBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, 501 URE_FC_PATCH_TASK); 502 usbd_delay_ms(sc->ure_udev, 1); 503 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, 504 URE_FC_PATCH_TASK); 505 } 506 } 507 508 /* Reset the packet filter. */ 509 URE_CLRBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN); 510 URE_SETBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN); 511 512 /* Enable transmit and receive. */ 513 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE); 514 515 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) { 516 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB, 517 URE_OWN_UPDATE | URE_OWN_CLEAR); 518 } 519 520 URE_CLRBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 521 } 522 523 int 524 ure_ifmedia_upd(struct ifnet *ifp) 525 { 526 struct ure_softc *sc = ifp->if_softc; 527 struct mii_data *mii = &sc->ure_mii; 528 struct ifmedia *ifm = &sc->ure_ifmedia; 529 int anar, gig, err, reg; 530 531 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 532 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 533 return (EINVAL); 534 535 if (!(sc->ure_chip & URE_CHIP_VER_7420)) { 536 reg = ure_ocp_reg_read(sc, URE_OCP_10GBT_CTRL); 537 reg &= ~URE_ADV_2500TFDX; 538 } 539 540 anar = gig = 0; 541 switch (IFM_SUBTYPE(ifm->ifm_media)) { 542 case IFM_AUTO: 543 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 544 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 545 if (!(sc->ure_chip & URE_CHIP_VER_7420)) 546 reg |= URE_ADV_2500TFDX; 547 break; 548 case IFM_2500_T: 549 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 550 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 551 reg |= URE_ADV_2500TFDX; 552 ifp->if_baudrate = IF_Mbps(2500); 553 break; 554 case IFM_1000_T: 555 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 556 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 557 ifp->if_baudrate = IF_Gbps(1); 558 break; 559 case IFM_100_TX: 560 anar |= ANAR_TX | ANAR_TX_FD; 561 ifp->if_baudrate = IF_Mbps(100); 562 break; 563 case IFM_10_T: 564 anar |= ANAR_10 | ANAR_10_FD; 565 ifp->if_baudrate = IF_Mbps(10); 566 break; 567 default: 568 printf("%s: unsupported media type\n", 569 sc->ure_dev.dv_xname); 570 return (EINVAL); 571 } 572 573 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_ANAR * 2, 574 anar | ANAR_PAUSE_ASYM | ANAR_FC); 575 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_100T2CR * 2, gig); 576 if (!(sc->ure_chip & URE_CHIP_VER_7420)) 577 ure_ocp_reg_write(sc, URE_OCP_10GBT_CTRL, reg); 578 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR, 579 BMCR_AUTOEN | BMCR_STARTNEG); 580 581 return (0); 582 } 583 584 if (mii->mii_instance) { 585 struct mii_softc *miisc; 586 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 587 PHY_RESET(miisc); 588 } 589 590 err = mii_mediachg(mii); 591 if (err == ENXIO) 592 return (0); 593 else 594 return (err); 595 } 596 597 void 598 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 599 { 600 struct ure_softc *sc = ifp->if_softc; 601 struct mii_data *mii = &sc->ure_mii; 602 uint16_t status = 0; 603 604 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 605 ifmr->ifm_status = IFM_AVALID; 606 if (ure_get_link_status(sc)) { 607 ifmr->ifm_status |= IFM_ACTIVE; 608 status = ure_read_2(sc, URE_PLA_PHYSTATUS, 609 URE_MCU_TYPE_PLA); 610 if ((status & URE_PHYSTATUS_FDX) || 611 (status & URE_PHYSTATUS_2500MBPS)) 612 ifmr->ifm_active |= IFM_FDX; 613 else 614 ifmr->ifm_active |= IFM_HDX; 615 if (status & URE_PHYSTATUS_10MBPS) 616 ifmr->ifm_active |= IFM_10_T; 617 else if (status & URE_PHYSTATUS_100MBPS) 618 ifmr->ifm_active |= IFM_100_TX; 619 else if (status & URE_PHYSTATUS_1000MBPS) 620 ifmr->ifm_active |= IFM_1000_T; 621 else if (status & URE_PHYSTATUS_2500MBPS) 622 ifmr->ifm_active |= IFM_2500_T; 623 } 624 return; 625 } 626 627 mii_pollstat(mii); 628 ifmr->ifm_active = mii->mii_media_active; 629 ifmr->ifm_status = mii->mii_media_status; 630 } 631 632 void 633 ure_add_media_types(struct ure_softc *sc) 634 { 635 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 636 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 637 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 638 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, 639 NULL); 640 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 641 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, 642 NULL); 643 if (!(sc->ure_chip & URE_CHIP_VER_7420)) { 644 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_2500_T, 0, NULL); 645 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_2500_T | IFM_FDX, 646 0, NULL); 647 } 648 } 649 650 void 651 ure_link_state(struct ure_softc *sc) 652 { 653 struct ifnet *ifp = &sc->ure_ac.ac_if; 654 int link = LINK_STATE_DOWN; 655 656 if (ure_get_link_status(sc)) 657 link = LINK_STATE_UP; 658 659 if (ifp->if_link_state != link) { 660 ifp->if_link_state = link; 661 if_link_state_change(ifp); 662 } 663 } 664 665 int 666 ure_get_link_status(struct ure_softc *sc) 667 { 668 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & 669 URE_PHYSTATUS_LINK) { 670 sc->ure_flags |= URE_FLAG_LINK; 671 return (1); 672 } else { 673 sc->ure_flags &= ~URE_FLAG_LINK; 674 return (0); 675 } 676 } 677 678 void 679 ure_iff(struct ure_softc *sc) 680 { 681 struct ifnet *ifp = &sc->ure_ac.ac_if; 682 struct ether_multi *enm; 683 struct ether_multistep step; 684 uint32_t hashes[2] = { 0, 0 }; 685 uint32_t hash; 686 uint32_t rxmode; 687 688 if (usbd_is_dying(sc->ure_udev)) 689 return; 690 691 rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA); 692 rxmode &= ~URE_RCR_ACPT_ALL; 693 ifp->if_flags &= ~IFF_ALLMULTI; 694 695 /* 696 * Always accept frames destined to our station address. 697 * Always accept broadcast frames. 698 */ 699 rxmode |= URE_RCR_APM | URE_RCR_AB; 700 701 if (ifp->if_flags & IFF_PROMISC || sc->ure_ac.ac_multirangecnt > 0) { 702 ifp->if_flags |= IFF_ALLMULTI; 703 rxmode |= URE_RCR_AM; 704 if (ifp->if_flags & IFF_PROMISC) 705 rxmode |= URE_RCR_AAP; 706 hashes[0] = hashes[1] = 0xffffffff; 707 } else { 708 rxmode |= URE_RCR_AM; 709 710 ETHER_FIRST_MULTI(step, &sc->ure_ac, enm); 711 while (enm != NULL) { 712 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) 713 >> 26; 714 if (hash < 32) 715 hashes[0] |= (1 << hash); 716 else 717 hashes[1] |= (1 << (hash - 32)); 718 719 ETHER_NEXT_MULTI(step, enm); 720 } 721 722 hash = swap32(hashes[0]); 723 hashes[0] = swap32(hashes[1]); 724 hashes[1] = hash; 725 } 726 727 ure_write_mem(sc, URE_PLA_MAR, URE_MCU_TYPE_PLA | URE_BYTE_EN_DWORD, 728 hashes, sizeof(hashes)); 729 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 730 } 731 732 void 733 ure_rxvlan(struct ure_softc *sc) 734 { 735 struct ifnet *ifp = &sc->ure_ac.ac_if; 736 uint16_t reg; 737 738 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 739 reg = ure_read_2(sc, URE_PLA_RCR1, URE_MCU_TYPE_PLA); 740 reg &= ~(URE_INNER_VLAN | URE_OUTER_VLAN); 741 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 742 reg |= (URE_INNER_VLAN | URE_OUTER_VLAN); 743 ure_write_2(sc, URE_PLA_RCR1, URE_MCU_TYPE_PLA, reg); 744 } else { 745 reg = ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA); 746 reg &= ~URE_CPCR_RX_VLAN; 747 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 748 reg |= URE_CPCR_RX_VLAN; 749 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, reg); 750 } 751 } 752 753 void 754 ure_reset(struct ure_softc *sc) 755 { 756 int i; 757 758 if (sc->ure_flags & URE_FLAG_8156) { 759 URE_CLRBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_TE); 760 URE_CLRBIT_2(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, 761 BMU_RESET_EP_IN); 762 URE_SETBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 763 URE_CDC_ECM_EN); 764 URE_CLRBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE); 765 URE_SETBIT_2(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, 766 BMU_RESET_EP_IN); 767 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 768 URE_CDC_ECM_EN); 769 } else { 770 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 771 772 for (i = 0; i < URE_TIMEOUT; i++) { 773 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) & 774 URE_CR_RST)) 775 break; 776 DELAY(100); 777 } 778 if (i == URE_TIMEOUT) 779 printf("%s: reset never completed\n", 780 sc->ure_dev.dv_xname); 781 } 782 } 783 784 void 785 ure_watchdog(struct ifnet *ifp) 786 { 787 struct ure_softc *sc = ifp->if_softc; 788 struct ure_chain *c; 789 usbd_status err; 790 int i, s; 791 792 ifp->if_timer = 0; 793 794 if (usbd_is_dying(sc->ure_udev)) 795 return; 796 797 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) 798 return; 799 800 sc = ifp->if_softc; 801 s = splnet(); 802 803 ifp->if_oerrors++; 804 DPRINTF(("%s: watchdog timeout\n", sc->ure_dev.dv_xname)); 805 806 for (i = 0; i < URE_TX_LIST_CNT; i++) { 807 c = &sc->ure_cdata.ure_tx_chain[i]; 808 if (c->uc_cnt > 0) { 809 usbd_get_xfer_status(c->uc_xfer, NULL, NULL, NULL, 810 &err); 811 ure_txeof(c->uc_xfer, c, err); 812 } 813 } 814 815 if (ifq_is_oactive(&ifp->if_snd)) 816 ifq_restart(&ifp->if_snd); 817 splx(s); 818 } 819 820 void 821 ure_init(void *xsc) 822 { 823 struct ure_softc *sc = xsc; 824 struct ure_chain *c; 825 struct ifnet *ifp = &sc->ure_ac.ac_if; 826 usbd_status err; 827 int s, i; 828 829 s = splnet(); 830 831 /* Cancel pending I/O. */ 832 ure_stop(sc); 833 834 if (sc->ure_flags & URE_FLAG_8152) 835 ure_rtl8152_nic_reset(sc); 836 else 837 ure_rtl8153_nic_reset(sc); 838 839 if (ure_xfer_list_init(sc, sc->ure_cdata.ure_rx_chain, 840 sc->ure_rxbufsz, URE_RX_LIST_CNT) == ENOBUFS) { 841 printf("%s: rx list init failed\n", sc->ure_dev.dv_xname); 842 splx(s); 843 return; 844 } 845 846 if (ure_xfer_list_init(sc, sc->ure_cdata.ure_tx_chain, 847 sc->ure_txbufsz, URE_TX_LIST_CNT) == ENOBUFS) { 848 printf("%s: tx list init failed\n", sc->ure_dev.dv_xname); 849 splx(s); 850 return; 851 } 852 853 /* Initialize the SLIST we are using for the multiple tx buffers */ 854 SLIST_INIT(&sc->ure_cdata.ure_tx_free); 855 for (i = 0; i < URE_TX_LIST_CNT; i++) 856 SLIST_INSERT_HEAD(&sc->ure_cdata.ure_tx_free, 857 &sc->ure_cdata.ure_tx_chain[i], uc_list); 858 859 /* Setup MAC address, and enable TX/RX. */ 860 ure_ifmedia_init(ifp); 861 862 /* Load the multicast filter. */ 863 ure_iff(sc); 864 865 /* Open RX and TX pipes. */ 866 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_RX], 867 USBD_EXCLUSIVE_USE, &sc->ure_ep[URE_ENDPT_RX]); 868 if (err) { 869 printf("%s: open rx pipe failed: %s\n", 870 sc->ure_dev.dv_xname, usbd_errstr(err)); 871 splx(s); 872 return; 873 } 874 875 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_TX], 876 USBD_EXCLUSIVE_USE, &sc->ure_ep[URE_ENDPT_TX]); 877 if (err) { 878 printf("%s: open tx pipe failed: %s\n", 879 sc->ure_dev.dv_xname, usbd_errstr(err)); 880 splx(s); 881 return; 882 } 883 884 /* Start up the receive pipe. */ 885 for (i = 0; i < URE_RX_LIST_CNT; i++) { 886 c = &sc->ure_cdata.ure_rx_chain[i]; 887 usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_RX], 888 c, c->uc_buf, c->uc_bufmax, 889 USBD_SHORT_XFER_OK | USBD_NO_COPY, 890 USBD_NO_TIMEOUT, ure_rxeof); 891 usbd_transfer(c->uc_xfer); 892 } 893 894 ure_ifmedia_upd(ifp); 895 896 /* Indicate we are up and running. */ 897 sc->ure_flags &= ~URE_FLAG_LINK; 898 ifp->if_flags |= IFF_RUNNING; 899 ifq_clr_oactive(&ifp->if_snd); 900 901 timeout_add_sec(&sc->ure_stat_ch, 1); 902 903 splx(s); 904 } 905 906 void 907 ure_start(struct ifnet *ifp) 908 { 909 struct ure_softc *sc = ifp->if_softc; 910 struct ure_cdata *cd = &sc->ure_cdata; 911 struct ure_chain *c; 912 struct mbuf *m = NULL; 913 uint32_t new_buflen; 914 int s, mlen; 915 916 if (!(sc->ure_flags & URE_FLAG_LINK) || 917 (ifp->if_flags & (IFF_RUNNING|IFF_UP)) != 918 (IFF_RUNNING|IFF_UP)) { 919 return; 920 } 921 922 s = splnet(); 923 924 c = SLIST_FIRST(&cd->ure_tx_free); 925 while (c != NULL) { 926 m = ifq_deq_begin(&ifp->if_snd); 927 if (m == NULL) 928 break; 929 930 mlen = m->m_pkthdr.len; 931 932 /* Discard packet larger than buffer. */ 933 if (mlen + sizeof(struct ure_txpkt) >= c->uc_bufmax) { 934 ifq_deq_commit(&ifp->if_snd, m); 935 m_freem(m); 936 ifp->if_oerrors++; 937 continue; 938 } 939 940 /* 941 * If packet larger than remaining space, send buffer and 942 * continue. 943 */ 944 new_buflen = roundup(c->uc_buflen, URE_TX_BUF_ALIGN); 945 if (new_buflen + sizeof(struct ure_txpkt) + mlen >= 946 c->uc_bufmax) { 947 ifq_deq_rollback(&ifp->if_snd, m); 948 SLIST_REMOVE_HEAD(&cd->ure_tx_free, uc_list); 949 if (ure_encap_xfer(ifp, sc, c)) { 950 SLIST_INSERT_HEAD(&cd->ure_tx_free, c, 951 uc_list); 952 break; 953 } 954 c = SLIST_FIRST(&cd->ure_tx_free); 955 continue; 956 } 957 958 /* Append packet to current buffer. */ 959 mlen = ure_encap_txpkt(m, c->uc_buf + new_buflen, 960 c->uc_bufmax - new_buflen); 961 if (mlen <= 0) { 962 ifq_deq_rollback(&ifp->if_snd, m); 963 break; 964 } 965 966 ifq_deq_commit(&ifp->if_snd, m); 967 c->uc_cnt += 1; 968 c->uc_buflen = new_buflen + mlen; 969 970 #if NBPFILTER > 0 971 if (ifp->if_bpf) 972 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 973 #endif 974 975 m_freem(m); 976 } 977 978 if (c != NULL) { 979 /* Send current buffer unless empty */ 980 if (c->uc_buflen > 0 && c->uc_cnt > 0) { 981 SLIST_REMOVE_HEAD(&cd->ure_tx_free, uc_list); 982 if (ure_encap_xfer(ifp, sc, c)) { 983 SLIST_INSERT_HEAD(&cd->ure_tx_free, c, 984 uc_list); 985 } 986 c = SLIST_FIRST(&cd->ure_tx_free); 987 } 988 } 989 990 ifp->if_timer = 5; 991 if (c == NULL) 992 ifq_set_oactive(&ifp->if_snd); 993 splx(s); 994 } 995 996 void 997 ure_tick(void *xsc) 998 { 999 struct ure_softc *sc = xsc; 1000 1001 if (sc == NULL) 1002 return; 1003 1004 if (usbd_is_dying(sc->ure_udev)) 1005 return; 1006 1007 usb_add_task(sc->ure_udev, &sc->ure_tick_task); 1008 } 1009 1010 void 1011 ure_stop(struct ure_softc *sc) 1012 { 1013 struct ure_cdata *cd; 1014 struct ifnet *ifp; 1015 usbd_status err; 1016 1017 ure_reset(sc); 1018 1019 ifp = &sc->ure_ac.ac_if; 1020 ifp->if_timer = 0; 1021 ifp->if_flags &= ~IFF_RUNNING; 1022 ifq_clr_oactive(&ifp->if_snd); 1023 1024 timeout_del(&sc->ure_stat_ch); 1025 sc->ure_flags &= ~URE_FLAG_LINK; 1026 1027 if (sc->ure_ep[URE_ENDPT_RX] != NULL) { 1028 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_RX]); 1029 if (err) { 1030 printf("%s: close rx pipe failed: %s\n", 1031 sc->ure_dev.dv_xname, usbd_errstr(err)); 1032 } 1033 sc->ure_ep[URE_ENDPT_RX] = NULL; 1034 } 1035 1036 if (sc->ure_ep[URE_ENDPT_TX] != NULL) { 1037 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_TX]); 1038 if (err) { 1039 printf("%s: close tx pipe failed: %s\n", 1040 sc->ure_dev.dv_xname, usbd_errstr(err)); 1041 } 1042 sc->ure_ep[URE_ENDPT_TX] = NULL; 1043 } 1044 1045 cd = &sc->ure_cdata; 1046 ure_xfer_list_free(sc, cd->ure_rx_chain, URE_RX_LIST_CNT); 1047 ure_xfer_list_free(sc, cd->ure_tx_chain, URE_TX_LIST_CNT); 1048 } 1049 1050 int 1051 ure_xfer_list_init(struct ure_softc *sc, struct ure_chain *ch, 1052 uint32_t bufsize, int listlen) 1053 { 1054 struct ure_chain *c; 1055 int i; 1056 1057 for (i = 0; i < listlen; i++) { 1058 c = &ch[i]; 1059 c->uc_sc = sc; 1060 c->uc_idx = i; 1061 c->uc_buflen = 0; 1062 c->uc_bufmax = bufsize; 1063 c->uc_cnt = 0; 1064 if (c->uc_xfer == NULL) { 1065 c->uc_xfer = usbd_alloc_xfer(sc->ure_udev); 1066 if (c->uc_xfer == NULL) 1067 return (ENOBUFS); 1068 c->uc_buf = usbd_alloc_buffer(c->uc_xfer, c->uc_bufmax); 1069 if (c->uc_buf == NULL) { 1070 usbd_free_xfer(c->uc_xfer); 1071 c->uc_xfer = NULL; 1072 return (ENOBUFS); 1073 } 1074 } 1075 } 1076 1077 return (0); 1078 } 1079 1080 void 1081 ure_xfer_list_free(struct ure_softc *sc, struct ure_chain *ch, int listlen) 1082 { 1083 int i; 1084 1085 for (i = 0; i < listlen; i++) { 1086 if (ch[i].uc_buf != NULL) { 1087 ch[i].uc_buf = NULL; 1088 } 1089 ch[i].uc_cnt = 0; 1090 if (ch[i].uc_xfer != NULL) { 1091 usbd_free_xfer(ch[i].uc_xfer); 1092 ch[i].uc_xfer = NULL; 1093 } 1094 } 1095 } 1096 1097 void 1098 ure_rtl8152_init(struct ure_softc *sc) 1099 { 1100 uint32_t pwrctrl; 1101 1102 /* Disable ALDPS. */ 1103 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 1104 URE_DIS_SDSAVE); 1105 usbd_delay_ms(sc->ure_udev, 20); 1106 1107 if (sc->ure_chip & URE_CHIP_VER_4C00) 1108 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 1109 URE_LED_MODE_MASK); 1110 1111 URE_CLRBIT_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, URE_POWER_CUT); 1112 URE_CLRBIT_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 1113 URE_RESUME_INDICATE); 1114 1115 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 1116 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 1117 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 1118 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 1119 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 1120 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 1121 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 1122 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 1123 URE_SPDWN_LINKCHG_MSK); 1124 1125 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET); 1126 1127 /* Enable Rx aggregation. */ 1128 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1129 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1130 } 1131 1132 void 1133 ure_rtl8153_init(struct ure_softc *sc) 1134 { 1135 uint16_t reg; 1136 uint8_t u1u2[8]; 1137 int i; 1138 1139 memset(u1u2, 0x00, sizeof(u1u2)); 1140 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, u1u2, 1141 sizeof(u1u2)); 1142 1143 for (i = 0; i < 500; i++) { 1144 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 1145 URE_AUTOLOAD_DONE) 1146 break; 1147 usbd_delay_ms(sc->ure_udev, 20); 1148 } 1149 if (i == 500) 1150 printf("%s: timeout waiting for chip autoload\n", 1151 sc->ure_dev.dv_xname); 1152 1153 ure_rtl8153_phy_status(sc, 0); 1154 1155 if (sc->ure_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 | 1156 URE_CHIP_VER_5C20)) { 1157 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG, 1158 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 1159 } 1160 1161 ure_rtl8153_phy_status(sc, URE_PHY_STAT_LAN_ON); 1162 1163 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1164 1165 if (sc->ure_chip & URE_CHIP_VER_5C10) { 1166 reg = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 1167 reg &= ~URE_PWD_DN_SCALE_MASK; 1168 reg |= URE_PWD_DN_SCALE(96); 1169 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, reg); 1170 1171 URE_SETBIT_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 1172 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 1173 } else if (sc->ure_chip & URE_CHIP_VER_5C20) { 1174 URE_CLRBIT_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 1175 URE_ECM_ALDPS); 1176 } 1177 if (sc->ure_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) { 1178 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB)) 1179 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, 1180 URE_DYNAMIC_BURST); 1181 else 1182 URE_CLRBIT_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, 1183 URE_DYNAMIC_BURST); 1184 } 1185 1186 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, URE_EP4_FULL_FC); 1187 1188 URE_CLRBIT_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, URE_TIMER11_EN); 1189 1190 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 1191 URE_LED_MODE_MASK); 1192 1193 if ((sc->ure_chip & URE_CHIP_VER_5C10) && 1194 sc->ure_udev->speed != USB_SPEED_SUPER) 1195 reg = URE_LPM_TIMER_500MS; 1196 else 1197 reg = URE_LPM_TIMER_500US; 1198 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 1199 URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM | reg); 1200 1201 reg = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 1202 reg &= ~URE_SEN_VAL_MASK; 1203 reg |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 1204 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, reg); 1205 1206 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 1207 1208 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 1209 URE_PWR_EN | URE_PHASE2_EN); 1210 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS); 1211 1212 memset(u1u2, 0xff, sizeof(u1u2)); 1213 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, u1u2, 1214 sizeof(u1u2)); 1215 1216 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0); 1217 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 0); 1218 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 0); 1219 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0); 1220 1221 /* Enable Rx aggregation. */ 1222 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1223 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1224 1225 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET); 1226 } 1227 1228 void 1229 ure_rtl8153b_init(struct ure_softc *sc) 1230 { 1231 uint16_t reg; 1232 int i; 1233 1234 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1235 URE_CLRBIT_1(sc, URE_USB_ECM_OP, URE_MCU_TYPE_USB, 1236 URE_EN_ALL_SPEED); 1237 ure_write_2(sc, URE_USB_SPEED_OPTION, URE_MCU_TYPE_USB, 0); 1238 URE_SETBIT_2(sc, URE_USB_ECM_OPTION, URE_MCU_TYPE_USB, 1239 URE_BYPASS_MAC_RESET); 1240 1241 if (sc->ure_flags & URE_FLAG_8156B) 1242 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 1243 URE_RX_DETECT8); 1244 } 1245 1246 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, LPM_U1U2_EN); 1247 1248 if (sc->ure_flags & URE_FLAG_8156B) 1249 ure_wait_for_flash(sc); 1250 1251 for (i = 0; i < 500; i++) { 1252 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 1253 URE_AUTOLOAD_DONE) 1254 break; 1255 usbd_delay_ms(sc->ure_udev, 20); 1256 } 1257 if (i == 500) 1258 printf("%s: timeout waiting for chip autoload\n", 1259 sc->ure_dev.dv_xname); 1260 1261 ure_rtl8153_phy_status(sc, 0); 1262 ure_rtl8153_phy_status(sc, URE_PHY_STAT_LAN_ON); 1263 1264 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1265 1266 /* MSC timer, 32760 ms. */ 1267 ure_write_2(sc, URE_USB_MSC_TIMER, URE_MCU_TYPE_USB, 4095); 1268 1269 if (!(sc->ure_flags & URE_FLAG_8153B)) { 1270 /* U1/U2/L1 idle timer, 500 us. */ 1271 ure_write_2(sc, URE_USB_U1U2_TIMER, URE_MCU_TYPE_USB, 500); 1272 } 1273 1274 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN); 1275 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS); 1276 1277 URE_CLRBIT_1(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 1278 URE_UPS_EN | URE_USP_PREWAKE); 1279 URE_CLRBIT_1(sc, URE_USB_MISC_2, URE_MCU_TYPE_USB, 1280 URE_UPS_FORCE_PWR_DOWN | URE_UPS_NO_UPS); 1281 1282 URE_CLRBIT_1(sc, URE_PLA_INDICATE_FALG, URE_MCU_TYPE_PLA, 1283 URE_UPCOMING_RUNTIME_D3); 1284 URE_CLRBIT_1(sc, URE_PLA_SUSPEND_FLAG, URE_MCU_TYPE_PLA, 1285 URE_LINK_CHG_EVENT); 1286 URE_CLRBIT_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, 1287 URE_LINK_CHANGE_FLAG); 1288 1289 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 1290 URE_CLRBIT_2(sc, URE_PLA_CONFIG34, URE_MCU_TYPE_PLA, 1291 URE_LINK_OFF_WAKE_EN); 1292 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 1293 1294 if (sc->ure_flags & URE_FLAG_8153B) { 1295 reg = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA); 1296 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & 1297 URE_PHYSTATUS_LINK) 1298 reg |= URE_CUR_LINK_OK; 1299 else 1300 reg &= ~URE_CUR_LINK_OK; 1301 ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, 1302 reg | URE_POLL_LINK_CHG); 1303 } 1304 1305 if (sc->ure_udev->speed == USB_SPEED_SUPER) { 1306 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, 1307 LPM_U1U2_EN); 1308 } 1309 1310 if (sc->ure_flags & URE_FLAG_8156B) { 1311 URE_CLRBIT_2(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_SLOT_EN); 1312 URE_SETBIT_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 1313 URE_FLOW_CTRL_EN); 1314 1315 /* Enable fc timer and set timer to 600 ms. */ 1316 ure_write_2(sc, URE_USB_FC_TIMER, URE_MCU_TYPE_USB, 1317 URE_CTRL_TIMER_EN | 75); 1318 1319 reg = ure_read_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB); 1320 if (!(ure_read_2(sc, URE_PLA_POL_GPIO_CTRL, URE_MCU_TYPE_PLA) & 1321 URE_DACK_DET_EN)) 1322 reg |= URE_FLOW_CTRL_PATCH_2; 1323 reg &= ~URE_AUTO_SPEEDUP; 1324 ure_write_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB, reg); 1325 1326 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, 1327 URE_FC_PATCH_TASK); 1328 } 1329 1330 /* MAC clock speed down. */ 1331 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1332 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0x0403); 1333 reg = ure_read_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA); 1334 reg &= ~URE_EEE_SPDWN_RATIO_MASK; 1335 reg |= URE_MAC_CLK_SPDWN_EN | 0x0003; 1336 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, reg); 1337 1338 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 1339 URE_PLA_MCU_SPDWN_EN); 1340 1341 reg = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA); 1342 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & 1343 URE_PHYSTATUS_LINK) 1344 reg |= URE_CUR_LINK_OK; 1345 else 1346 reg &= ~URE_CUR_LINK_OK; 1347 ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, 1348 reg | URE_POLL_LINK_CHG); 1349 } else 1350 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 1351 URE_MAC_CLK_SPDWN_EN); 1352 1353 /* Enable Rx aggregation. */ 1354 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1355 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1356 1357 if (sc->ure_flags & URE_FLAG_8156) 1358 URE_SETBIT_1(sc, URE_USB_BMU_CONFIG, URE_MCU_TYPE_USB, 1359 URE_ACT_ODMA); 1360 1361 if (!(sc->ure_flags & URE_FLAG_8153B)) { 1362 /* 1363 * Select force mode through 0xa5b4 bit 15 1364 * 0: MDIO force mode 1365 * 1: MMD force mode 1366 */ 1367 reg = ure_ocp_reg_read(sc, 0xa5b4); 1368 if (reg & 0x8000) 1369 ure_ocp_reg_write(sc, 0xa5b4, reg & ~0x8000); 1370 } 1371 1372 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET); 1373 } 1374 1375 void 1376 ure_rtl8152_nic_reset(struct ure_softc *sc) 1377 { 1378 uint32_t rx_fifo1, rx_fifo2; 1379 int i; 1380 1381 /* Disable ALDPS. */ 1382 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 1383 URE_DIS_SDSAVE); 1384 usbd_delay_ms(sc->ure_udev, 20); 1385 1386 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL); 1387 1388 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 1389 ure_disable_teredo(sc); 1390 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 1391 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 1392 1393 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB); 1394 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN); 1395 for (i = 0; i < URE_TIMEOUT; i++) { 1396 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1397 URE_LINK_LIST_READY) 1398 break; 1399 usbd_delay_ms(sc->ure_udev, 1); 1400 } 1401 if (i == URE_TIMEOUT) 1402 printf("%s: timeout waiting for OOB control\n", 1403 sc->ure_dev.dv_xname); 1404 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL); 1405 for (i = 0; i < URE_TIMEOUT; i++) { 1406 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1407 URE_LINK_LIST_READY) 1408 break; 1409 usbd_delay_ms(sc->ure_udev, 1); 1410 } 1411 if (i == URE_TIMEOUT) 1412 printf("%s: timeout waiting for OOB control\n", 1413 sc->ure_dev.dv_xname); 1414 1415 ure_reset(sc); 1416 1417 /* Configure Rx FIFO threshold. */ 1418 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 1419 URE_RXFIFO_THR1_NORMAL); 1420 if (sc->ure_udev->speed == USB_SPEED_FULL) { 1421 rx_fifo1 = URE_RXFIFO_THR2_FULL; 1422 rx_fifo2 = URE_RXFIFO_THR3_FULL; 1423 } else { 1424 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 1425 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 1426 } 1427 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 1428 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 1429 1430 /* Configure Tx FIFO threshold. */ 1431 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 1432 URE_TXFIFO_THR_NORMAL); 1433 1434 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 1435 URE_TX_AGG_MAX_THRESHOLD); 1436 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 1437 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 1438 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 1439 1440 ure_rxvlan(sc); 1441 ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA, 1442 ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1443 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO); 1444 1445 /* Enable ALDPS. */ 1446 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, 1447 URE_ENPWRSAVE | URE_ENPDNPS | URE_LINKENA | URE_DIS_SDSAVE); 1448 } 1449 1450 void 1451 ure_rtl8153_nic_reset(struct ure_softc *sc) 1452 { 1453 struct ifnet *ifp = &sc->ure_ac.ac_if; 1454 uint32_t reg = 0; 1455 uint8_t u1u2[8] = { 0 }; 1456 int i; 1457 1458 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) { 1459 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, 1460 LPM_U1U2_EN); 1461 } else { 1462 memset(u1u2, 0x00, sizeof(u1u2)); 1463 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, 1464 u1u2, sizeof(u1u2)); 1465 } 1466 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1467 1468 /* Disable ALDPS. */ 1469 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1470 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 1471 for (i = 0; i < 20; i++) { 1472 usbd_delay_ms(sc->ure_udev, 1); 1473 if (ure_read_2(sc, 0xe000, URE_MCU_TYPE_PLA) & 0x0100) 1474 break; 1475 } 1476 1477 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 1478 ure_disable_teredo(sc); 1479 1480 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL); 1481 1482 ure_reset(sc); 1483 ure_reset_bmu(sc); 1484 1485 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB); 1486 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN); 1487 1488 if (!(sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B))) { 1489 for (i = 0; i < URE_TIMEOUT; i++) { 1490 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1491 URE_LINK_LIST_READY) 1492 break; 1493 usbd_delay_ms(sc->ure_udev, 1); 1494 } 1495 if (i == URE_TIMEOUT) 1496 printf("%s: timeout waiting for OOB control\n", 1497 sc->ure_dev.dv_xname); 1498 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 1499 URE_RE_INIT_LL); 1500 for (i = 0; i < URE_TIMEOUT; i++) { 1501 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1502 URE_LINK_LIST_READY) 1503 break; 1504 usbd_delay_ms(sc->ure_udev, 1); 1505 } 1506 if (i == URE_TIMEOUT) 1507 printf("%s: timeout waiting for OOB control\n", 1508 sc->ure_dev.dv_xname); 1509 } 1510 1511 ure_rxvlan(sc); 1512 1513 ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA, 1514 URE_FRAMELEN(ifp->if_mtu)); 1515 ure_write_1(sc, URE_PLA_MTPS, URE_MCU_TYPE_PLA, MTPS_JUMBO); 1516 1517 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1518 ure_write_2(sc, URE_PLA_RX_FIFO_FULL, URE_MCU_TYPE_PLA, 1519 (sc->ure_flags & URE_FLAG_8156) ? 1024 : 512); 1520 ure_write_2(sc, URE_PLA_RX_FIFO_EMPTY, URE_MCU_TYPE_PLA, 1521 (sc->ure_flags & URE_FLAG_8156) ? 2048 : 1024); 1522 1523 /* Tx share fifo free credit full threshold. */ 1524 ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 8); 1525 ure_write_2(sc, URE_PLA_TXFIFO_FULL, URE_MCU_TYPE_PLA, 128); 1526 1527 if (sc->ure_flags & URE_FLAG_8156) 1528 URE_SETBIT_2(sc, URE_USB_BMU_CONFIG, URE_MCU_TYPE_USB, 1529 URE_ACT_ODMA); 1530 1531 /* FIFO settings */ 1532 reg = ure_read_2(sc, URE_PLA_RXFIFO_FULL, URE_MCU_TYPE_PLA); 1533 reg &= ~URE_RXFIFO_FULL_MASK; 1534 ure_write_2(sc, URE_PLA_RXFIFO_FULL, URE_MCU_TYPE_PLA, 1535 reg | 0x0008); 1536 1537 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 1538 URE_PLA_MCU_SPDWN_EN); 1539 1540 URE_CLRBIT_2(sc, URE_USB_SPEED_OPTION, URE_MCU_TYPE_USB, 1541 URE_RG_PWRDN_EN | URE_ALL_SPEED_OFF); 1542 1543 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, 1544 0x00600400); 1545 } else { 1546 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 1547 URE_TCR0_AUTO_FIFO); 1548 ure_reset(sc); 1549 1550 /* Configure Rx FIFO threshold. */ 1551 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 1552 URE_RXFIFO_THR1_NORMAL); 1553 ure_write_2(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, 1554 URE_RXFIFO_THR2_NORMAL); 1555 ure_write_2(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, 1556 URE_RXFIFO_THR3_NORMAL); 1557 1558 /* Configure Tx FIFO threshold. */ 1559 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 1560 URE_TXFIFO_THR_NORMAL2); 1561 1562 if (sc->ure_flags & URE_FLAG_8153B) { 1563 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, 1564 URE_RX_THR_B); 1565 1566 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, 1567 URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN); 1568 } else { 1569 URE_SETBIT_1(sc, URE_PLA_CONFIG6, URE_MCU_TYPE_PLA, 1570 URE_LANWAKE_CLR_EN); 1571 URE_CLRBIT_1(sc, URE_PLA_LWAKE_CTRL_REG, 1572 URE_MCU_TYPE_PLA, URE_LANWAKE_PIN); 1573 URE_CLRBIT_2(sc, URE_USB_SSPHYLINK1, URE_MCU_TYPE_USB, 1574 URE_DELAY_PHY_PWR_CHG); 1575 } 1576 } 1577 1578 /* Enable ALDPS. */ 1579 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1580 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | URE_EN_ALDPS); 1581 1582 if ((sc->ure_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) || 1583 (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B))) 1584 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 1585 URE_U2P3_ENABLE); 1586 1587 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) { 1588 if (sc->ure_udev->speed == USB_SPEED_SUPER) 1589 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, 1590 LPM_U1U2_EN); 1591 } else { 1592 memset(u1u2, 0xff, sizeof(u1u2)); 1593 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, 1594 u1u2, sizeof(u1u2)); 1595 } 1596 } 1597 1598 uint16_t 1599 ure_rtl8153_phy_status(struct ure_softc *sc, int desired) 1600 { 1601 uint16_t reg; 1602 int i; 1603 1604 for (i = 0; i < 500; i++) { 1605 reg = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & 1606 URE_PHY_STAT_MASK; 1607 if (desired) { 1608 if (reg == desired) 1609 break; 1610 } else { 1611 if (reg == URE_PHY_STAT_LAN_ON || 1612 reg == URE_PHY_STAT_PWRDN || 1613 reg == URE_PHY_STAT_EXT_INIT) 1614 break; 1615 } 1616 usbd_delay_ms(sc->ure_udev, 20); 1617 } 1618 if (i == 500) 1619 printf("%s: timeout waiting for phy to stabilize\n", 1620 sc->ure_dev.dv_xname); 1621 1622 return reg; 1623 } 1624 1625 void 1626 ure_wait_for_flash(struct ure_softc *sc) 1627 { 1628 int i; 1629 1630 if ((ure_read_2(sc, URE_PLA_GPHY_CTRL, URE_MCU_TYPE_PLA) & 1631 URE_GPHY_FLASH) && 1632 !(ure_read_2(sc, URE_USB_GPHY_CTRL, URE_MCU_TYPE_USB) & 1633 URE_BYPASS_FLASH)) { 1634 for (i = 0; i < 100; i++) { 1635 if (ure_read_2(sc, URE_USB_GPHY_CTRL, 1636 URE_MCU_TYPE_USB) & URE_GPHY_PATCH_DONE) 1637 break; 1638 DELAY(1000); 1639 } 1640 if (i == 100) 1641 printf("%s: timeout waiting for loading flash\n", 1642 sc->ure_dev.dv_xname); 1643 } 1644 } 1645 1646 void 1647 ure_reset_bmu(struct ure_softc *sc) 1648 { 1649 uint8_t reg; 1650 1651 reg = ure_read_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB); 1652 reg &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); 1653 ure_write_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, reg); 1654 reg |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; 1655 ure_write_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, reg); 1656 } 1657 1658 void 1659 ure_disable_teredo(struct ure_softc *sc) 1660 { 1661 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) 1662 ure_write_1(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 0xff); 1663 else { 1664 URE_CLRBIT_2(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 1665 URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | 1666 URE_OOB_TEREDO_EN); 1667 } 1668 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, URE_WDT6_SET_MODE); 1669 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 1670 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 1671 } 1672 1673 int 1674 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1675 { 1676 struct ure_softc *sc = ifp->if_softc; 1677 struct ifreq *ifr = (struct ifreq *)data; 1678 int s, error = 0; 1679 1680 s = splnet(); 1681 1682 switch (cmd) { 1683 case SIOCSIFADDR: 1684 ifp->if_flags |= IFF_UP; 1685 if (!(ifp->if_flags & IFF_RUNNING)) 1686 ure_init(sc); 1687 break; 1688 1689 case SIOCSIFFLAGS: 1690 if (ifp->if_flags & IFF_UP) { 1691 if (ifp->if_flags & IFF_RUNNING) 1692 error = ENETRESET; 1693 else 1694 ure_init(sc); 1695 } else { 1696 if (ifp->if_flags & IFF_RUNNING) 1697 ure_stop(sc); 1698 } 1699 break; 1700 1701 case SIOCGIFMEDIA: 1702 case SIOCSIFMEDIA: 1703 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) 1704 error = ifmedia_ioctl(ifp, ifr, &sc->ure_ifmedia, cmd); 1705 else 1706 error = ifmedia_ioctl(ifp, ifr, &sc->ure_mii.mii_media, 1707 cmd); 1708 break; 1709 1710 default: 1711 error = ether_ioctl(ifp, &sc->ure_ac, cmd, data); 1712 } 1713 1714 if (error == ENETRESET) { 1715 if (ifp->if_flags & IFF_RUNNING) 1716 ure_iff(sc); 1717 error = 0; 1718 } 1719 1720 splx(s); 1721 1722 return (error); 1723 } 1724 1725 int 1726 ure_match(struct device *parent, void *match, void *aux) 1727 { 1728 struct usb_attach_arg *uaa = aux; 1729 1730 if (uaa->iface == NULL || uaa->configno != 1) 1731 return (UMATCH_NONE); 1732 1733 return (usb_lookup(ure_devs, uaa->vendor, uaa->product) != NULL ? 1734 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 1735 } 1736 1737 void 1738 ure_attach(struct device *parent, struct device *self, void *aux) 1739 { 1740 struct ure_softc *sc = (struct ure_softc *)self; 1741 struct usb_attach_arg *uaa = aux; 1742 usb_interface_descriptor_t *id; 1743 usb_endpoint_descriptor_t *ed; 1744 u_char eaddr[8]; /* 4byte padded */ 1745 struct ifnet *ifp; 1746 int i, mii_flags = 0, s; 1747 uint16_t ver; 1748 1749 sc->ure_udev = uaa->device; 1750 sc->ure_iface = uaa->iface; 1751 1752 usb_init_task(&sc->ure_tick_task, ure_tick_task, sc, 1753 USB_TASK_TYPE_GENERIC); 1754 1755 id = usbd_get_interface_descriptor(sc->ure_iface); 1756 1757 for (i = 0; i < id->bNumEndpoints; i++) { 1758 ed = usbd_interface2endpoint_descriptor(sc->ure_iface, i); 1759 if (!ed) { 1760 printf("%s: couldn't get ep %d\n", 1761 sc->ure_dev.dv_xname, i); 1762 return; 1763 } 1764 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 1765 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 1766 sc->ure_ed[URE_ENDPT_RX] = ed->bEndpointAddress; 1767 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 1768 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 1769 sc->ure_ed[URE_ENDPT_TX] = ed->bEndpointAddress; 1770 } 1771 } 1772 1773 sc->ure_txbufsz = URE_TX_BUFSZ; 1774 sc->ure_rxbufsz = URE_8153_RX_BUFSZ; 1775 1776 s = splnet(); 1777 1778 sc->ure_phyno = 0; 1779 printf("%s: ", sc->ure_dev.dv_xname); 1780 1781 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 1782 switch (ver) { 1783 case 0x4c00: 1784 sc->ure_flags = URE_FLAG_8152; 1785 sc->ure_rxbufsz = URE_8152_RX_BUFSZ; 1786 sc->ure_chip |= URE_CHIP_VER_4C00; 1787 printf("RTL8152 (0x4c00)"); 1788 break; 1789 case 0x4c10: 1790 sc->ure_flags = URE_FLAG_8152; 1791 sc->ure_rxbufsz = URE_8152_RX_BUFSZ; 1792 sc->ure_chip |= URE_CHIP_VER_4C10; 1793 printf("RTL8152 (0x4c10)"); 1794 break; 1795 case 0x5c00: 1796 sc->ure_chip |= URE_CHIP_VER_5C00; 1797 printf("RTL8153 (0x5c00)"); 1798 break; 1799 case 0x5c10: 1800 sc->ure_chip |= URE_CHIP_VER_5C10; 1801 printf("RTL8153 (0x5c10)"); 1802 break; 1803 case 0x5c20: 1804 sc->ure_chip |= URE_CHIP_VER_5C20; 1805 printf("RTL8153 (0x5c20)"); 1806 break; 1807 case 0x5c30: 1808 sc->ure_chip |= URE_CHIP_VER_5C30; 1809 printf("RTL8153 (0x5c30)"); 1810 break; 1811 case 0x6000: 1812 sc->ure_flags = URE_FLAG_8153B; 1813 printf("RTL8153B (0x6000)"); 1814 break; 1815 case 0x6010: 1816 sc->ure_flags = URE_FLAG_8153B; 1817 printf("RTL8153B (0x6010)"); 1818 break; 1819 case 0x7020: 1820 sc->ure_flags = URE_FLAG_8156; 1821 printf("RTL8156 (0x7020)"); 1822 break; 1823 case 0x7030: 1824 sc->ure_flags = URE_FLAG_8156; 1825 printf("RTL8156 (0x7030)"); 1826 break; 1827 case 0x7410: 1828 sc->ure_flags = URE_FLAG_8156B; 1829 printf("RTL8156B (0x7410)"); 1830 break; 1831 case 0x7420: 1832 sc->ure_flags = URE_FLAG_8156B; 1833 sc->ure_chip = URE_CHIP_VER_7420; 1834 printf("RTL8153D (0x7420)"); 1835 break; 1836 default: 1837 printf(", unknown ver %02x", ver); 1838 break; 1839 } 1840 1841 if (sc->ure_flags & URE_FLAG_8152) 1842 ure_rtl8152_init(sc); 1843 else if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | 1844 URE_FLAG_8156B)) 1845 ure_rtl8153b_init(sc); 1846 else 1847 ure_rtl8153_init(sc); 1848 1849 if (sc->ure_chip & URE_CHIP_VER_4C00) 1850 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr, 1851 sizeof(eaddr)); 1852 else 1853 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr, 1854 sizeof(eaddr)); 1855 1856 printf(", address %s\n", ether_sprintf(eaddr)); 1857 1858 bcopy(eaddr, (char *)&sc->ure_ac.ac_enaddr, ETHER_ADDR_LEN); 1859 1860 ifp = &sc->ure_ac.ac_if; 1861 ifp->if_softc = sc; 1862 strlcpy(ifp->if_xname, sc->ure_dev.dv_xname, IFNAMSIZ); 1863 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1864 ifp->if_ioctl = ure_ioctl; 1865 ifp->if_start = ure_start; 1866 ifp->if_watchdog = ure_watchdog; 1867 1868 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 | 1869 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1870 1871 #if NVLAN > 0 1872 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1873 #endif 1874 1875 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1876 ifmedia_init(&sc->ure_ifmedia, IFM_IMASK, ure_ifmedia_upd, 1877 ure_ifmedia_sts); 1878 ure_add_media_types(sc); 1879 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1880 ifmedia_set(&sc->ure_ifmedia, IFM_ETHER | IFM_AUTO); 1881 sc->ure_ifmedia.ifm_media = sc->ure_ifmedia.ifm_cur->ifm_media; 1882 } else { 1883 rw_init(&sc->ure_mii_lock, "uremii"); 1884 1885 sc->ure_mii.mii_ifp = ifp; 1886 sc->ure_mii.mii_readreg = ure_miibus_readreg; 1887 sc->ure_mii.mii_writereg = ure_miibus_writereg; 1888 sc->ure_mii.mii_statchg = ure_miibus_statchg; 1889 sc->ure_mii.mii_flags = MIIF_AUTOTSLEEP; 1890 1891 ifmedia_init(&sc->ure_mii.mii_media, 0, ure_ifmedia_upd, 1892 ure_ifmedia_sts); 1893 if (!(sc->ure_flags & URE_FLAG_8152)) 1894 mii_flags |= MIIF_DOPAUSE; 1895 mii_attach(self, &sc->ure_mii, 0xffffffff, sc->ure_phyno, 1896 MII_OFFSET_ANY, mii_flags); 1897 if (LIST_FIRST(&sc->ure_mii.mii_phys) == NULL) { 1898 ifmedia_add(&sc->ure_mii.mii_media, 1899 IFM_ETHER | IFM_NONE, 0, NULL); 1900 ifmedia_set(&sc->ure_mii.mii_media, 1901 IFM_ETHER | IFM_NONE); 1902 } else 1903 ifmedia_set(&sc->ure_mii.mii_media, 1904 IFM_ETHER | IFM_AUTO); 1905 } 1906 1907 if_attach(ifp); 1908 ether_ifattach(ifp); 1909 1910 timeout_set(&sc->ure_stat_ch, ure_tick, sc); 1911 1912 splx(s); 1913 } 1914 1915 int 1916 ure_detach(struct device *self, int flags) 1917 { 1918 struct ure_softc *sc = (struct ure_softc *)self; 1919 struct ifnet *ifp = &sc->ure_ac.ac_if; 1920 int s; 1921 1922 if (timeout_initialized(&sc->ure_stat_ch)) 1923 timeout_del(&sc->ure_stat_ch); 1924 1925 if (sc->ure_ep[URE_ENDPT_TX] != NULL) 1926 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_TX]); 1927 if (sc->ure_ep[URE_ENDPT_RX] != NULL) 1928 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_RX]); 1929 1930 usb_rem_task(sc->ure_udev, &sc->ure_tick_task); 1931 1932 s = splusb(); 1933 1934 if (--sc->ure_refcnt >= 0) { 1935 usb_detach_wait(&sc->ure_dev); 1936 } 1937 1938 if (ifp->if_flags & IFF_RUNNING) 1939 ure_stop(sc); 1940 1941 mii_detach(&sc->ure_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1942 ifmedia_delete_instance(&sc->ure_mii.mii_media, IFM_INST_ANY); 1943 if (ifp->if_softc != NULL) { 1944 ether_ifdetach(ifp); 1945 if_detach(ifp); 1946 } 1947 1948 splx(s); 1949 1950 return 0; 1951 } 1952 1953 void 1954 ure_tick_task(void *xsc) 1955 { 1956 struct ure_softc *sc = xsc; 1957 struct mii_data *mii; 1958 int s; 1959 1960 if (sc == NULL) 1961 return; 1962 1963 if (usbd_is_dying(sc->ure_udev)) 1964 return; 1965 mii = &sc->ure_mii; 1966 1967 s = splnet(); 1968 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) 1969 ure_link_state(sc); 1970 else { 1971 mii_tick(mii); 1972 if ((sc->ure_flags & URE_FLAG_LINK) == 0) 1973 ure_miibus_statchg(&sc->ure_dev); 1974 } 1975 timeout_add_sec(&sc->ure_stat_ch, 1); 1976 splx(s); 1977 } 1978 1979 void 1980 ure_lock_mii(struct ure_softc *sc) 1981 { 1982 sc->ure_refcnt++; 1983 rw_enter_write(&sc->ure_mii_lock); 1984 } 1985 1986 void 1987 ure_unlock_mii(struct ure_softc *sc) 1988 { 1989 rw_exit_write(&sc->ure_mii_lock); 1990 if (--sc->ure_refcnt < 0) 1991 usb_detach_wakeup(&sc->ure_dev); 1992 } 1993 1994 void 1995 ure_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1996 { 1997 struct ure_chain *c = (struct ure_chain *)priv; 1998 struct ure_softc *sc = c->uc_sc; 1999 struct ifnet *ifp = &sc->ure_ac.ac_if; 2000 u_char *buf = c->uc_buf; 2001 uint32_t cflags, rxvlan, total_len; 2002 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 2003 struct mbuf *m; 2004 int pktlen = 0, s; 2005 struct ure_rxpkt rxhdr; 2006 2007 if (usbd_is_dying(sc->ure_udev)) 2008 return; 2009 2010 if (!(ifp->if_flags & IFF_RUNNING)) 2011 return; 2012 2013 if (status != USBD_NORMAL_COMPLETION) { 2014 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 2015 return; 2016 if (usbd_ratecheck(&sc->ure_rx_notice)) { 2017 printf("%s: usb errors on rx: %s\n", 2018 sc->ure_dev.dv_xname, usbd_errstr(status)); 2019 } 2020 if (status == USBD_STALLED) 2021 usbd_clear_endpoint_stall_async( 2022 sc->ure_ep[URE_ENDPT_RX]); 2023 goto done; 2024 } 2025 2026 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL); 2027 DPRINTFN(3, ("received %d bytes\n", total_len)); 2028 2029 do { 2030 if (total_len < sizeof(rxhdr)) { 2031 DPRINTF(("too few bytes left for a packet header\n")); 2032 ifp->if_ierrors++; 2033 goto done; 2034 } 2035 2036 buf += roundup(pktlen, URE_RX_BUF_ALIGN); 2037 2038 memcpy(&rxhdr, buf, sizeof(rxhdr)); 2039 total_len -= sizeof(rxhdr); 2040 2041 pktlen = letoh32(rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK; 2042 DPRINTFN(4, ("next packet is %d bytes\n", pktlen)); 2043 if (pktlen > total_len) { 2044 DPRINTF(("not enough bytes left for next packet\n")); 2045 ifp->if_ierrors++; 2046 goto done; 2047 } 2048 2049 total_len -= roundup(pktlen, URE_RX_BUF_ALIGN); 2050 buf += sizeof(rxhdr); 2051 2052 m = m_devget(buf, pktlen - ETHER_CRC_LEN, ETHER_ALIGN); 2053 if (m == NULL) { 2054 DPRINTF(("unable to allocate mbuf for next packet\n")); 2055 ifp->if_ierrors++; 2056 goto done; 2057 } 2058 2059 cflags = letoh32(rxhdr.ure_csum); 2060 rxvlan = letoh32(rxhdr.ure_vlan); 2061 2062 /* Check IP header checksum. */ 2063 if ((rxvlan & URE_RXPKT_IPV4) && 2064 !(cflags & URE_RXPKT_IPSUMBAD)) 2065 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 2066 2067 /* Check TCP/UDP checksum. */ 2068 if ((rxvlan & (URE_RXPKT_IPV4 | URE_RXPKT_IPV6)) && 2069 (((rxvlan & URE_RXPKT_TCP) && 2070 !(cflags & URE_RXPKT_TCPSUMBAD)) || 2071 ((rxvlan & URE_RXPKT_UDP) && 2072 !(cflags & URE_RXPKT_UDPSUMBAD)))) 2073 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | 2074 M_UDP_CSUM_IN_OK; 2075 #if NVLAN > 0 2076 if (rxvlan & URE_RXPKT_VLAN_TAG) { 2077 m->m_pkthdr.ether_vtag = 2078 swap16(rxvlan & URE_RXPKT_VLAN_DATA); 2079 m->m_flags |= M_VLANTAG; 2080 } 2081 #endif 2082 2083 ml_enqueue(&ml, m); 2084 } while (total_len > 0); 2085 2086 done: 2087 s = splnet(); 2088 if_input(ifp, &ml); 2089 splx(s); 2090 memset(c->uc_buf, 0, sc->ure_rxbufsz); 2091 2092 usbd_setup_xfer(xfer, sc->ure_ep[URE_ENDPT_RX], c, c->uc_buf, 2093 sc->ure_rxbufsz, USBD_SHORT_XFER_OK | USBD_NO_COPY, 2094 USBD_NO_TIMEOUT, ure_rxeof); 2095 usbd_transfer(xfer); 2096 } 2097 2098 2099 void 2100 ure_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2101 { 2102 struct ure_softc *sc; 2103 struct ure_chain *c; 2104 struct ifnet *ifp; 2105 int s; 2106 2107 c = priv; 2108 sc = c->uc_sc; 2109 ifp = &sc->ure_ac.ac_if; 2110 2111 if (usbd_is_dying(sc->ure_udev)) 2112 return; 2113 2114 if (status != USBD_NORMAL_COMPLETION) 2115 DPRINTF(("%s: %s uc_idx=%u : %s\n", sc->ure_dev.dv_xname, 2116 __func__, c->uc_idx, usbd_errstr(status))); 2117 2118 s = splnet(); 2119 2120 c->uc_cnt = 0; 2121 c->uc_buflen = 0; 2122 2123 SLIST_INSERT_HEAD(&sc->ure_cdata.ure_tx_free, c, uc_list); 2124 2125 if (status != USBD_NORMAL_COMPLETION) { 2126 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) { 2127 splx(s); 2128 return; 2129 } 2130 2131 ifp->if_oerrors++; 2132 printf("%s: usb error on tx: %s\n", sc->ure_dev.dv_xname, 2133 usbd_errstr(status)); 2134 2135 if (status == USBD_STALLED) 2136 usbd_clear_endpoint_stall_async( 2137 sc->ure_ep[URE_ENDPT_TX]); 2138 splx(s); 2139 return; 2140 } 2141 2142 ifp->if_timer = 0; 2143 if (ifq_is_oactive(&ifp->if_snd)) 2144 ifq_restart(&ifp->if_snd); 2145 splx(s); 2146 } 2147 2148 int 2149 ure_encap_txpkt(struct mbuf *m, char *buf, uint32_t maxlen) 2150 { 2151 struct ure_txpkt txhdr; 2152 uint32_t len = sizeof(txhdr), cflags = 0; 2153 2154 if (len + m->m_pkthdr.len > maxlen) 2155 return (-1); 2156 2157 if ((m->m_pkthdr.csum_flags & 2158 (M_IPV4_CSUM_OUT | M_TCP_CSUM_OUT | M_UDP_CSUM_OUT)) != 0) { 2159 cflags |= URE_TXPKT_IPV4; 2160 if (m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) 2161 cflags |= URE_TXPKT_TCP; 2162 if (m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) 2163 cflags |= URE_TXPKT_UDP; 2164 } 2165 2166 #if NVLAN > 0 2167 if (m->m_flags & M_VLANTAG) 2168 cflags |= URE_TXPKT_VLAN_TAG | swap16(m->m_pkthdr.ether_vtag); 2169 #endif 2170 2171 txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS | 2172 URE_TXPKT_TX_LS); 2173 txhdr.ure_vlan = htole32(cflags); 2174 memcpy(buf, &txhdr, len); 2175 2176 m_copydata(m, 0, m->m_pkthdr.len, buf + len); 2177 len += m->m_pkthdr.len; 2178 2179 return (len); 2180 } 2181 2182 int 2183 ure_encap_xfer(struct ifnet *ifp, struct ure_softc *sc, struct ure_chain *c) 2184 { 2185 usbd_status err; 2186 2187 usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_TX], c, c->uc_buf, 2188 c->uc_buflen, USBD_FORCE_SHORT_XFER | USBD_NO_COPY, 10000, 2189 ure_txeof); 2190 2191 err = usbd_transfer(c->uc_xfer); 2192 if (err != USBD_IN_PROGRESS) { 2193 c->uc_cnt = 0; 2194 c->uc_buflen = 0; 2195 ure_stop(sc); 2196 return (EIO); 2197 } 2198 2199 return (0); 2200 } 2201