1 /* $OpenBSD: if_ure.c,v 1.16 2020/07/10 13:26:41 patrick Exp $ */ 2 /*- 3 * Copyright (c) 2015, 2016, 2019 Kevin Lo <kevlo@openbsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include "bpfilter.h" 29 #include "vlan.h" 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/sockio.h> 34 #include <sys/rwlock.h> 35 #include <sys/mbuf.h> 36 #include <sys/kernel.h> 37 #include <sys/socket.h> 38 #include <sys/device.h> 39 40 #include <machine/bus.h> 41 42 #include <net/if.h> 43 #include <net/if_media.h> 44 45 #if NBPFILTER > 0 46 #include <net/bpf.h> 47 #endif 48 49 #include <netinet/in.h> 50 #include <netinet/if_ether.h> 51 52 #include <dev/mii/mii.h> 53 #include <dev/mii/miivar.h> 54 55 #include <dev/usb/usb.h> 56 #include <dev/usb/usbdi.h> 57 #include <dev/usb/usbdi_util.h> 58 #include <dev/usb/usbdivar.h> 59 #include <dev/usb/usbdevs.h> 60 61 #include <dev/ic/rtl81x9reg.h> 62 #include <dev/usb/if_urereg.h> 63 64 #ifdef URE_DEBUG 65 #define DPRINTF(x) do { if (uredebug) printf x; } while (0) 66 #define DPRINTFN(n,x) do { if (uredebug >= (n)) printf x; } while (0) 67 int uredebug = 0; 68 #else 69 #define DPRINTF(x) 70 #define DPRINTFN(n,x) 71 #endif 72 73 const struct usb_devno ure_devs[] = { 74 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ONELINKPLUS }, 75 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_DOCK_ETHERNET }, 76 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 }, 77 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8153 }, 78 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8156 } 79 }; 80 81 int ure_match(struct device *, void *, void *); 82 void ure_attach(struct device *, struct device *, void *); 83 int ure_detach(struct device *, int); 84 85 struct cfdriver ure_cd = { 86 NULL, "ure", DV_IFNET 87 }; 88 89 const struct cfattach ure_ca = { 90 sizeof(struct ure_softc), ure_match, ure_attach, ure_detach 91 }; 92 93 int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t, 94 void *, int); 95 int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *, 96 int); 97 int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *, 98 int); 99 uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t); 100 uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t); 101 uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t); 102 int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t); 103 int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t); 104 int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t); 105 uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t); 106 void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t); 107 108 void ure_init(void *); 109 void ure_stop(struct ure_softc *); 110 void ure_start(struct ifnet *); 111 void ure_reset(struct ure_softc *); 112 void ure_watchdog(struct ifnet *); 113 114 void ure_miibus_statchg(struct device *); 115 int ure_miibus_readreg(struct device *, int, int); 116 void ure_miibus_writereg(struct device *, int, int, int); 117 void ure_lock_mii(struct ure_softc *); 118 void ure_unlock_mii(struct ure_softc *); 119 120 int ure_encap(struct ure_softc *, struct mbuf *); 121 void ure_rxeof(struct usbd_xfer *, void *, usbd_status); 122 void ure_txeof(struct usbd_xfer *, void *, usbd_status); 123 int ure_rx_list_init(struct ure_softc *); 124 int ure_tx_list_init(struct ure_softc *); 125 126 void ure_tick_task(void *); 127 void ure_tick(void *); 128 129 int ure_ifmedia_upd(struct ifnet *); 130 void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *); 131 void ure_add_media_types(struct ure_softc *); 132 void ure_link_state(struct ure_softc *); 133 int ure_get_link_status(struct ure_softc *); 134 void ure_iff(struct ure_softc *); 135 void ure_rxvlan(struct ure_softc *); 136 int ure_ioctl(struct ifnet *, u_long, caddr_t); 137 void ure_rtl8152_init(struct ure_softc *); 138 void ure_rtl8153_init(struct ure_softc *); 139 void ure_rtl8153b_init(struct ure_softc *); 140 void ure_rtl8152_nic_reset(struct ure_softc *); 141 void ure_rtl8153_nic_reset(struct ure_softc *); 142 void ure_rtl8153_phy_status(struct ure_softc *, int); 143 void ure_reset_bmu(struct ure_softc *); 144 void ure_disable_teredo(struct ure_softc *); 145 146 #define URE_SETBIT_1(sc, reg, index, x) \ 147 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x)) 148 #define URE_SETBIT_2(sc, reg, index, x) \ 149 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x)) 150 #define URE_SETBIT_4(sc, reg, index, x) \ 151 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x)) 152 153 #define URE_CLRBIT_1(sc, reg, index, x) \ 154 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~(x)) 155 #define URE_CLRBIT_2(sc, reg, index, x) \ 156 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~(x)) 157 #define URE_CLRBIT_4(sc, reg, index, x) \ 158 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~(x)) 159 160 int 161 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index, 162 void *buf, int len) 163 { 164 usb_device_request_t req; 165 usbd_status err; 166 167 if (usbd_is_dying(sc->ure_udev)) 168 return 0; 169 170 if (rw == URE_CTL_WRITE) 171 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 172 else 173 req.bmRequestType = UT_READ_VENDOR_DEVICE; 174 req.bRequest = UR_SET_ADDRESS; 175 USETW(req.wValue, val); 176 USETW(req.wIndex, index); 177 USETW(req.wLength, len); 178 179 DPRINTFN(5, ("ure_ctl: rw %d, val 0x%04hu, index 0x%04hu, len %d\n", 180 rw, val, index, len)); 181 err = usbd_do_request(sc->ure_udev, &req, buf); 182 if (err) { 183 DPRINTF(("ure_ctl: error %d\n", err)); 184 return -1; 185 } 186 187 return 0; 188 } 189 190 int 191 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 192 void *buf, int len) 193 { 194 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len)); 195 } 196 197 int 198 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 199 void *buf, int len) 200 { 201 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len)); 202 } 203 204 uint8_t 205 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index) 206 { 207 uint32_t val; 208 uint8_t temp[4]; 209 uint8_t shift; 210 211 shift = (reg & 3) << 3; 212 reg &= ~3; 213 214 ure_read_mem(sc, reg, index, &temp, 4); 215 val = UGETDW(temp); 216 val >>= shift; 217 218 return (val & 0xff); 219 } 220 221 uint16_t 222 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index) 223 { 224 uint32_t val; 225 uint8_t temp[4]; 226 uint8_t shift; 227 228 shift = (reg & 2) << 3; 229 reg &= ~3; 230 231 ure_read_mem(sc, reg, index, &temp, 4); 232 val = UGETDW(temp); 233 val >>= shift; 234 235 return (val & 0xffff); 236 } 237 238 uint32_t 239 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index) 240 { 241 uint8_t temp[4]; 242 243 ure_read_mem(sc, reg, index, &temp, 4); 244 return (UGETDW(temp)); 245 } 246 247 int 248 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 249 { 250 uint16_t byen; 251 uint8_t temp[4]; 252 uint8_t shift; 253 254 byen = URE_BYTE_EN_BYTE; 255 shift = reg & 3; 256 val &= 0xff; 257 258 if (reg & 3) { 259 byen <<= shift; 260 val <<= (shift << 3); 261 reg &= ~3; 262 } 263 264 USETDW(temp, val); 265 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 266 } 267 268 int 269 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 270 { 271 uint16_t byen; 272 uint8_t temp[4]; 273 uint8_t shift; 274 275 byen = URE_BYTE_EN_WORD; 276 shift = reg & 2; 277 val &= 0xffff; 278 279 if (reg & 2) { 280 byen <<= shift; 281 val <<= (shift << 3); 282 reg &= ~3; 283 } 284 285 USETDW(temp, val); 286 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 287 } 288 289 int 290 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 291 { 292 uint8_t temp[4]; 293 294 USETDW(temp, val); 295 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4)); 296 } 297 298 uint16_t 299 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr) 300 { 301 uint16_t reg; 302 303 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 304 reg = (addr & 0x0fff) | 0xb000; 305 306 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA)); 307 } 308 309 void 310 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 311 { 312 uint16_t reg; 313 314 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 315 reg = (addr & 0x0fff) | 0xb000; 316 317 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data); 318 } 319 320 int 321 ure_miibus_readreg(struct device *dev, int phy, int reg) 322 { 323 struct ure_softc *sc = (void *)dev; 324 uint16_t val; 325 326 if (usbd_is_dying(sc->ure_udev)) 327 return 0; 328 329 /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */ 330 if (reg == RL_GMEDIASTAT) 331 return ure_read_1(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA); 332 333 ure_lock_mii(sc); 334 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2); 335 ure_unlock_mii(sc); 336 337 return val; /* letoh16? */ 338 } 339 340 void 341 ure_miibus_writereg(struct device *dev, int phy, int reg, int val) 342 { 343 struct ure_softc *sc = (void *)dev; 344 345 ure_lock_mii(sc); 346 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val); /* htole16? */ 347 ure_unlock_mii(sc); 348 } 349 350 void 351 ure_miibus_statchg(struct device *dev) 352 { 353 struct ure_softc *sc = (void *)dev; 354 struct mii_data *mii = &sc->ure_mii; 355 struct ifnet *ifp = &sc->ure_ac.ac_if; 356 357 if ((ifp->if_flags & IFF_RUNNING) == 0) 358 return; 359 360 sc->ure_flags &= ~URE_FLAG_LINK; 361 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 362 (IFM_ACTIVE | IFM_AVALID)) { 363 switch (IFM_SUBTYPE(mii->mii_media_active)) { 364 case IFM_10_T: 365 case IFM_100_TX: 366 sc->ure_flags |= URE_FLAG_LINK; 367 break; 368 case IFM_1000_T: 369 if ((sc->ure_flags & URE_FLAG_8152) != 0) 370 break; 371 sc->ure_flags |= URE_FLAG_LINK; 372 break; 373 default: 374 break; 375 } 376 } 377 378 /* Lost link, do nothing. */ 379 if ((sc->ure_flags & URE_FLAG_LINK) == 0) 380 return; 381 } 382 383 int 384 ure_ifmedia_upd(struct ifnet *ifp) 385 { 386 struct ure_softc *sc = ifp->if_softc; 387 struct mii_data *mii = &sc->ure_mii; 388 struct ifmedia *ifm = &sc->ure_ifmedia; 389 int anar, gig, err, reg; 390 391 if (sc->ure_flags & URE_FLAG_8156) { 392 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 393 return (EINVAL); 394 395 reg = ure_ocp_reg_read(sc, 0xa5d4); 396 reg &= ~URE_ADV_2500TFDX; 397 398 anar = gig = 0; 399 switch (IFM_SUBTYPE(ifm->ifm_media)) { 400 case IFM_AUTO: 401 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 402 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 403 reg |= URE_ADV_2500TFDX; 404 break; 405 case IFM_2500_T: 406 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 407 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 408 reg |= URE_ADV_2500TFDX; 409 ifp->if_baudrate = IF_Mbps(2500); 410 break; 411 case IFM_1000_T: 412 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 413 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 414 ifp->if_baudrate = IF_Gbps(1); 415 break; 416 case IFM_100_TX: 417 anar |= ANAR_TX | ANAR_TX_FD; 418 ifp->if_baudrate = IF_Mbps(100); 419 break; 420 case IFM_10_T: 421 anar |= ANAR_10 | ANAR_10_FD; 422 ifp->if_baudrate = IF_Mbps(10); 423 break; 424 default: 425 printf("%s: unsupported media type\n", 426 sc->ure_dev.dv_xname); 427 return (EINVAL); 428 } 429 430 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_ANAR * 2, 431 anar | ANAR_PAUSE_ASYM | ANAR_FC); 432 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_100T2CR * 2, gig); 433 ure_ocp_reg_write(sc, 0xa5d4, reg); 434 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR, 435 BMCR_AUTOEN | BMCR_STARTNEG); 436 437 return (0); 438 } 439 440 if (mii->mii_instance) { 441 struct mii_softc *miisc; 442 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 443 PHY_RESET(miisc); 444 } 445 446 err = mii_mediachg(mii); 447 if (err == ENXIO) 448 return (0); 449 else 450 return (err); 451 } 452 453 void 454 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 455 { 456 struct ure_softc *sc = ifp->if_softc; 457 struct mii_data *mii = &sc->ure_mii; 458 uint16_t status = 0; 459 460 if (sc->ure_flags & URE_FLAG_8156) { 461 ifmr->ifm_status = IFM_AVALID; 462 if (ure_get_link_status(sc)) { 463 ifmr->ifm_status |= IFM_ACTIVE; 464 status = ure_read_2(sc, URE_PLA_PHYSTATUS, 465 URE_MCU_TYPE_PLA); 466 if ((status & URE_PHYSTATUS_FDX) || 467 (status & URE_PHYSTATUS_2500MBPS)) 468 ifmr->ifm_active |= IFM_FDX; 469 else 470 ifmr->ifm_active |= IFM_HDX; 471 if (status & URE_PHYSTATUS_10MBPS) 472 ifmr->ifm_active |= IFM_10_T; 473 else if (status & URE_PHYSTATUS_100MBPS) 474 ifmr->ifm_active |= IFM_100_TX; 475 else if (status & URE_PHYSTATUS_1000MBPS) 476 ifmr->ifm_active |= IFM_1000_T; 477 else if (status & URE_PHYSTATUS_2500MBPS) 478 ifmr->ifm_active |= IFM_2500_T; 479 } 480 return; 481 } 482 483 mii_pollstat(mii); 484 ifmr->ifm_active = mii->mii_media_active; 485 ifmr->ifm_status = mii->mii_media_status; 486 } 487 488 void 489 ure_add_media_types(struct ure_softc *sc) 490 { 491 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 492 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 493 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 494 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, 495 NULL); 496 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 497 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, 498 NULL); 499 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_2500_T, 0, NULL); 500 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_2500_T | IFM_FDX, 0, 501 NULL); 502 } 503 504 void 505 ure_link_state(struct ure_softc *sc) 506 { 507 struct ifnet *ifp = &sc->ure_ac.ac_if; 508 int link = LINK_STATE_DOWN; 509 510 if (ure_get_link_status(sc)) 511 link = LINK_STATE_UP; 512 513 if (ifp->if_link_state != link) { 514 ifp->if_link_state = link; 515 if_link_state_change(ifp); 516 } 517 } 518 519 int 520 ure_get_link_status(struct ure_softc *sc) 521 { 522 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & 523 URE_PHYSTATUS_LINK) { 524 sc->ure_flags |= URE_FLAG_LINK; 525 return (1); 526 } else { 527 sc->ure_flags &= ~URE_FLAG_LINK; 528 return (0); 529 } 530 } 531 532 void 533 ure_iff(struct ure_softc *sc) 534 { 535 struct ifnet *ifp = &sc->ure_ac.ac_if; 536 struct ether_multi *enm; 537 struct ether_multistep step; 538 uint32_t hashes[2] = { 0, 0 }; 539 uint32_t hash; 540 uint32_t rxmode; 541 542 if (usbd_is_dying(sc->ure_udev)) 543 return; 544 545 rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA); 546 rxmode &= ~URE_RCR_ACPT_ALL; 547 ifp->if_flags &= ~IFF_ALLMULTI; 548 549 /* 550 * Always accept frames destined to our station address. 551 * Always accept broadcast frames. 552 */ 553 rxmode |= URE_RCR_APM | URE_RCR_AB; 554 555 if (ifp->if_flags & IFF_PROMISC || sc->ure_ac.ac_multirangecnt > 0) { 556 ifp->if_flags |= IFF_ALLMULTI; 557 rxmode |= URE_RCR_AM; 558 if (ifp->if_flags & IFF_PROMISC) 559 rxmode |= URE_RCR_AAP; 560 hashes[0] = hashes[1] = 0xffffffff; 561 } else { 562 rxmode |= URE_RCR_AM; 563 564 ETHER_FIRST_MULTI(step, &sc->ure_ac, enm); 565 while (enm != NULL) { 566 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) 567 >> 26; 568 if (hash < 32) 569 hashes[0] |= (1 << hash); 570 else 571 hashes[1] |= (1 << (hash - 32)); 572 573 ETHER_NEXT_MULTI(step, enm); 574 } 575 576 hash = swap32(hashes[0]); 577 hashes[0] = swap32(hashes[1]); 578 hashes[1] = hash; 579 } 580 581 ure_write_mem(sc, URE_PLA_MAR, URE_MCU_TYPE_PLA | URE_BYTE_EN_DWORD, 582 hashes, sizeof(hashes)); 583 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 584 } 585 586 void 587 ure_rxvlan(struct ure_softc *sc) 588 { 589 struct ifnet *ifp = &sc->ure_ac.ac_if; 590 uint16_t reg; 591 592 if (sc->ure_flags & URE_FLAG_8156) { 593 reg = ure_read_2(sc, 0xc012, URE_MCU_TYPE_PLA); 594 reg &= ~0x00c0; 595 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 596 reg |= 0x00c0; 597 ure_write_2(sc, 0xc012, URE_MCU_TYPE_PLA, reg); 598 } else { 599 reg = ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA); 600 reg &= ~URE_CPCR_RX_VLAN; 601 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 602 reg |= URE_CPCR_RX_VLAN; 603 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, reg); 604 } 605 } 606 607 void 608 ure_reset(struct ure_softc *sc) 609 { 610 int i; 611 612 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 613 614 for (i = 0; i < URE_TIMEOUT; i++) { 615 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) & 616 URE_CR_RST)) 617 break; 618 DELAY(100); 619 } 620 if (i == URE_TIMEOUT) 621 printf("%s: reset never completed\n", sc->ure_dev.dv_xname); 622 } 623 624 void 625 ure_watchdog(struct ifnet *ifp) 626 { 627 struct ure_softc *sc = ifp->if_softc; 628 629 if (usbd_is_dying(sc->ure_udev)) 630 return; 631 632 ifp->if_oerrors++; 633 printf("%s: watchdog timeout\n", sc->ure_dev.dv_xname); 634 } 635 636 void 637 ure_init(void *xsc) 638 { 639 struct ure_softc *sc = xsc; 640 struct ure_chain *c; 641 struct ifnet *ifp = &sc->ure_ac.ac_if; 642 usbd_status err; 643 uint32_t reg = 0; 644 int s, i; 645 646 s = splnet(); 647 648 /* Cancel pending I/O. */ 649 ure_stop(sc); 650 651 if (sc->ure_flags & URE_FLAG_8152) 652 ure_rtl8152_nic_reset(sc); 653 else 654 ure_rtl8153_nic_reset(sc); 655 656 if (ure_rx_list_init(sc) == ENOBUFS) { 657 printf("%s: rx list init failed\n", sc->ure_dev.dv_xname); 658 splx(s); 659 return; 660 } 661 662 if (ure_tx_list_init(sc) == ENOBUFS) { 663 printf("%s: tx list init failed\n", sc->ure_dev.dv_xname); 664 splx(s); 665 return; 666 } 667 668 /* Set MAC address. */ 669 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 670 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 671 sc->ure_ac.ac_enaddr, 8); 672 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 673 674 if (!(sc->ure_flags & URE_FLAG_8152)) { 675 reg = sc->ure_rxbufsz - URE_FRAMELEN(ifp->if_mtu) + 676 sizeof(struct ure_rxpkt) + URE_RX_BUF_ALIGN; 677 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156)) { 678 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, 679 reg / 8); 680 681 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 682 (sc->ure_flags & URE_FLAG_8153B) ? 16 : 80); 683 ure_write_2(sc, URE_USB_PM_CTRL_STATUS, 684 URE_MCU_TYPE_USB, 1875); 685 } else { 686 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, 687 reg / 4); 688 switch (sc->ure_udev->speed) { 689 case USB_SPEED_SUPER: 690 reg = URE_COALESCE_SUPER / 8; 691 break; 692 case USB_SPEED_HIGH: 693 reg = URE_COALESCE_HIGH / 8; 694 break; 695 default: 696 reg = URE_COALESCE_SLOW / 8; 697 break; 698 } 699 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 700 reg); 701 } 702 } 703 704 /* Reset the packet filter. */ 705 URE_CLRBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN); 706 URE_SETBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN); 707 708 /* Enable transmit and receive. */ 709 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE); 710 711 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156)) { 712 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB, 713 URE_OWN_UPDATE | URE_OWN_CLEAR); 714 } 715 716 URE_CLRBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 717 718 /* Load the multicast filter. */ 719 ure_iff(sc); 720 721 /* Open RX and TX pipes. */ 722 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_RX], 723 USBD_EXCLUSIVE_USE, &sc->ure_ep[URE_ENDPT_RX]); 724 if (err) { 725 printf("%s: open rx pipe failed: %s\n", 726 sc->ure_dev.dv_xname, usbd_errstr(err)); 727 splx(s); 728 return; 729 } 730 731 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_TX], 732 USBD_EXCLUSIVE_USE, &sc->ure_ep[URE_ENDPT_TX]); 733 if (err) { 734 printf("%s: open tx pipe failed: %s\n", 735 sc->ure_dev.dv_xname, usbd_errstr(err)); 736 splx(s); 737 return; 738 } 739 740 /* Start up the receive pipe. */ 741 for (i = 0; i < URE_RX_LIST_CNT; i++) { 742 c = &sc->ure_cdata.rx_chain[i]; 743 usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_RX], 744 c, c->uc_buf, sc->ure_rxbufsz, 745 USBD_SHORT_XFER_OK | USBD_NO_COPY, 746 USBD_NO_TIMEOUT, ure_rxeof); 747 usbd_transfer(c->uc_xfer); 748 } 749 750 ure_ifmedia_upd(ifp); 751 752 /* Indicate we are up and running. */ 753 sc->ure_flags &= ~URE_FLAG_LINK; 754 ifp->if_flags |= IFF_RUNNING; 755 ifq_clr_oactive(&ifp->if_snd); 756 757 timeout_add_sec(&sc->ure_stat_ch, 1); 758 759 splx(s); 760 } 761 762 void 763 ure_start(struct ifnet *ifp) 764 { 765 struct ure_softc *sc = ifp->if_softc; 766 struct mbuf *m_head = NULL; 767 768 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd) || 769 !(sc->ure_flags & URE_FLAG_LINK)) 770 return; 771 772 for (;;) { 773 if (sc->ure_cdata.tx_cnt == sc->ure_tx_list_cnt) { 774 ifq_set_oactive(&ifp->if_snd); 775 break; 776 } 777 778 m_head = ifq_dequeue(&ifp->if_snd); 779 if (m_head == NULL) 780 break; 781 782 if (ure_encap(sc, m_head)) { 783 m_freem(m_head); 784 ifq_set_oactive(&ifp->if_snd); 785 break; 786 } 787 788 #if NBPFILTER > 0 789 if (ifp->if_bpf) 790 bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 791 #endif 792 ifp->if_timer = 5; 793 } 794 } 795 796 void 797 ure_tick(void *xsc) 798 { 799 struct ure_softc *sc = xsc; 800 801 if (sc == NULL) 802 return; 803 804 if (usbd_is_dying(sc->ure_udev)) 805 return; 806 807 usb_add_task(sc->ure_udev, &sc->ure_tick_task); 808 } 809 810 void 811 ure_stop(struct ure_softc *sc) 812 { 813 usbd_status err; 814 struct ifnet *ifp; 815 int i; 816 817 ure_reset(sc); 818 819 ifp = &sc->ure_ac.ac_if; 820 ifp->if_timer = 0; 821 ifp->if_flags &= ~IFF_RUNNING; 822 ifq_clr_oactive(&ifp->if_snd); 823 824 timeout_del(&sc->ure_stat_ch); 825 sc->ure_flags &= ~URE_FLAG_LINK; 826 827 if (sc->ure_ep[URE_ENDPT_RX] != NULL) { 828 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_RX]); 829 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_RX]); 830 if (err) { 831 printf("%s: close rx pipe failed: %s\n", 832 sc->ure_dev.dv_xname, usbd_errstr(err)); 833 } 834 sc->ure_ep[URE_ENDPT_RX] = NULL; 835 } 836 837 if (sc->ure_ep[URE_ENDPT_TX] != NULL) { 838 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_TX]); 839 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_TX]); 840 if (err) { 841 printf("%s: close tx pipe failed: %s\n", 842 sc->ure_dev.dv_xname, usbd_errstr(err)); 843 } 844 sc->ure_ep[URE_ENDPT_TX] = NULL; 845 } 846 847 for (i = 0; i < URE_RX_LIST_CNT; i++) { 848 if (sc->ure_cdata.rx_chain[i].uc_mbuf != NULL) { 849 m_freem(sc->ure_cdata.rx_chain[i].uc_mbuf); 850 sc->ure_cdata.rx_chain[i].uc_mbuf = NULL; 851 } 852 if (sc->ure_cdata.rx_chain[i].uc_xfer != NULL) { 853 usbd_free_xfer(sc->ure_cdata.rx_chain[i].uc_xfer); 854 sc->ure_cdata.rx_chain[i].uc_xfer = NULL; 855 } 856 } 857 858 for (i = 0; i < sc->ure_tx_list_cnt; i++) { 859 if (sc->ure_cdata.tx_chain[i].uc_mbuf != NULL) { 860 m_freem(sc->ure_cdata.tx_chain[i].uc_mbuf); 861 sc->ure_cdata.tx_chain[i].uc_mbuf = NULL; 862 } 863 if (sc->ure_cdata.tx_chain[i].uc_xfer != NULL) { 864 usbd_free_xfer(sc->ure_cdata.tx_chain[i].uc_xfer); 865 sc->ure_cdata.tx_chain[i].uc_xfer = NULL; 866 } 867 } 868 } 869 870 void 871 ure_rtl8152_init(struct ure_softc *sc) 872 { 873 uint32_t pwrctrl; 874 875 /* Disable ALDPS. */ 876 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 877 URE_DIS_SDSAVE); 878 usbd_delay_ms(sc->ure_udev, 20); 879 880 if (sc->ure_chip & URE_CHIP_VER_4C00) 881 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 882 URE_LED_MODE_MASK); 883 884 URE_CLRBIT_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, URE_POWER_CUT); 885 URE_CLRBIT_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 886 URE_RESUME_INDICATE); 887 888 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 889 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 890 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 891 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 892 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 893 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 894 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 895 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 896 URE_SPDWN_LINKCHG_MSK); 897 898 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET); 899 900 /* Enable Rx aggregation. */ 901 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 902 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 903 } 904 905 void 906 ure_rtl8153_init(struct ure_softc *sc) 907 { 908 uint16_t reg; 909 uint8_t u1u2[8]; 910 int i; 911 912 memset(u1u2, 0x00, sizeof(u1u2)); 913 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, u1u2, 914 sizeof(u1u2)); 915 916 for (i = 0; i < 500; i++) { 917 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 918 URE_AUTOLOAD_DONE) 919 break; 920 usbd_delay_ms(sc->ure_udev, 20); 921 } 922 if (i == 500) 923 printf("%s: timeout waiting for chip autoload\n", 924 sc->ure_dev.dv_xname); 925 926 ure_rtl8153_phy_status(sc, 0); 927 928 if (sc->ure_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 | 929 URE_CHIP_VER_5C20)) { 930 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG, 931 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 932 } 933 934 ure_rtl8153_phy_status(sc, 1); 935 936 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 937 938 if (sc->ure_chip & URE_CHIP_VER_5C10) { 939 reg = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 940 reg &= ~URE_PWD_DN_SCALE_MASK; 941 reg |= URE_PWD_DN_SCALE(96); 942 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, reg); 943 944 URE_SETBIT_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 945 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 946 } else if (sc->ure_chip & URE_CHIP_VER_5C20) { 947 URE_CLRBIT_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 948 URE_ECM_ALDPS); 949 } 950 if (sc->ure_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) { 951 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB)) 952 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, 953 URE_DYNAMIC_BURST); 954 else 955 URE_CLRBIT_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, 956 URE_DYNAMIC_BURST); 957 } 958 959 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, URE_EP4_FULL_FC); 960 961 URE_CLRBIT_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, URE_TIMER11_EN); 962 963 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 964 URE_LED_MODE_MASK); 965 966 if ((sc->ure_chip & URE_CHIP_VER_5C10) && 967 sc->ure_udev->speed != USB_SPEED_SUPER) 968 reg = URE_LPM_TIMER_500MS; 969 else 970 reg = URE_LPM_TIMER_500US; 971 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 972 URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM | reg); 973 974 reg = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 975 reg &= ~URE_SEN_VAL_MASK; 976 reg |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 977 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, reg); 978 979 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 980 981 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 982 URE_PWR_EN | URE_PHASE2_EN); 983 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS); 984 985 memset(u1u2, 0xff, sizeof(u1u2)); 986 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, u1u2, 987 sizeof(u1u2)); 988 989 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0); 990 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 0); 991 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 0); 992 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0); 993 994 /* Enable Rx aggregation. */ 995 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 996 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 997 998 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET); 999 } 1000 1001 void 1002 ure_rtl8153b_init(struct ure_softc *sc) 1003 { 1004 uint16_t reg; 1005 int i; 1006 1007 if (sc->ure_flags & URE_FLAG_8156) { 1008 URE_CLRBIT_1(sc, 0xd26b, URE_MCU_TYPE_USB, 0x01); 1009 ure_write_2(sc, 0xd32a, URE_MCU_TYPE_USB, 0); 1010 URE_SETBIT_2(sc, 0xcfee, URE_MCU_TYPE_USB, 0x0020); 1011 } 1012 1013 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, LPM_U1U2_EN); 1014 1015 for (i = 0; i < 500; i++) { 1016 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 1017 URE_AUTOLOAD_DONE) 1018 break; 1019 usbd_delay_ms(sc->ure_udev, 20); 1020 } 1021 if (i == 500) 1022 printf("%s: timeout waiting for chip autoload\n", 1023 sc->ure_dev.dv_xname); 1024 1025 ure_rtl8153_phy_status(sc, 0); 1026 ure_rtl8153_phy_status(sc, 1); 1027 1028 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1029 1030 /* MSC timer, 32760 ms. */ 1031 ure_write_2(sc, URE_USB_MSC_TIMER, URE_MCU_TYPE_USB, 0x0fff); 1032 1033 /* U1/U2/L1 idle timer, 500 us. */ 1034 ure_write_2(sc, URE_USB_U1U2_TIMER, URE_MCU_TYPE_USB, 500); 1035 1036 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN); 1037 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS); 1038 1039 URE_CLRBIT_1(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 1040 URE_UPS_EN | URE_USP_PREWAKE); 1041 URE_CLRBIT_1(sc, 0xcfff, URE_MCU_TYPE_USB, 0x01); 1042 1043 if (!(sc->ure_flags & URE_FLAG_8156)) { 1044 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, 1045 URE_PCUT_STATUS); 1046 ure_rtl8153_phy_status(sc, 0); 1047 } 1048 1049 URE_CLRBIT_1(sc, URE_PLA_INDICATE_FALG, URE_MCU_TYPE_PLA, 1050 URE_UPCOMING_RUNTIME_D3); 1051 URE_CLRBIT_1(sc, URE_PLA_SUSPEND_FLAG, URE_MCU_TYPE_PLA, 1052 URE_LINK_CHG_EVENT); 1053 URE_CLRBIT_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, 1054 URE_LINK_CHANGE_FLAG); 1055 1056 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 1057 URE_CLRBIT_2(sc, URE_PLA_CONFIG34, URE_MCU_TYPE_PLA, 1058 URE_LINK_OFF_WAKE_EN); 1059 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 1060 1061 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, LPM_U1U2_EN); 1062 1063 /* MAC clock speed down. */ 1064 if (sc->ure_flags & URE_FLAG_8156) { 1065 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0x0403); 1066 reg = ure_read_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA) & 1067 ~0xff; 1068 reg |= URE_MAC_CLK_SPDWN_EN | 0x0003; 1069 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, reg); 1070 1071 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 1072 0x4000); 1073 1074 reg = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA); 1075 if (ure_get_link_status(sc)) 1076 reg |= 0x8000; 1077 else 1078 reg &= ~0x8000; 1079 reg |= 0x0001; 1080 ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, reg); 1081 } else 1082 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 1083 URE_MAC_CLK_SPDWN_EN); 1084 1085 /* Enable Rx aggregation. */ 1086 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1087 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1088 1089 if (sc->ure_flags & URE_FLAG_8156) 1090 URE_SETBIT_1(sc, 0xcfd9, URE_MCU_TYPE_USB, 0x04); 1091 1092 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET); 1093 } 1094 1095 void 1096 ure_rtl8152_nic_reset(struct ure_softc *sc) 1097 { 1098 uint32_t rx_fifo1, rx_fifo2; 1099 int i; 1100 1101 /* Disable ALDPS. */ 1102 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 1103 URE_DIS_SDSAVE); 1104 usbd_delay_ms(sc->ure_udev, 20); 1105 1106 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL); 1107 1108 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 1109 ure_disable_teredo(sc); 1110 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 1111 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 1112 1113 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB); 1114 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN); 1115 for (i = 0; i < URE_TIMEOUT; i++) { 1116 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1117 URE_LINK_LIST_READY) 1118 break; 1119 usbd_delay_ms(sc->ure_udev, 1); 1120 } 1121 if (i == URE_TIMEOUT) 1122 printf("%s: timeout waiting for OOB control\n", 1123 sc->ure_dev.dv_xname); 1124 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL); 1125 for (i = 0; i < URE_TIMEOUT; i++) { 1126 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1127 URE_LINK_LIST_READY) 1128 break; 1129 usbd_delay_ms(sc->ure_udev, 1); 1130 } 1131 if (i == URE_TIMEOUT) 1132 printf("%s: timeout waiting for OOB control\n", 1133 sc->ure_dev.dv_xname); 1134 1135 ure_reset(sc); 1136 1137 /* Configure Rx FIFO threshold. */ 1138 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 1139 URE_RXFIFO_THR1_NORMAL); 1140 if (sc->ure_udev->speed == USB_SPEED_FULL) { 1141 rx_fifo1 = URE_RXFIFO_THR2_FULL; 1142 rx_fifo2 = URE_RXFIFO_THR3_FULL; 1143 } else { 1144 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 1145 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 1146 } 1147 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 1148 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 1149 1150 /* Configure Tx FIFO threshold. */ 1151 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 1152 URE_TXFIFO_THR_NORMAL); 1153 1154 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 1155 URE_TX_AGG_MAX_THRESHOLD); 1156 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 1157 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 1158 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 1159 1160 ure_rxvlan(sc); 1161 ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA, 1162 ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1163 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO); 1164 1165 /* Enable ALDPS. */ 1166 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, 1167 URE_ENPWRSAVE | URE_ENPDNPS | URE_LINKENA | URE_DIS_SDSAVE); 1168 } 1169 1170 void 1171 ure_rtl8153_nic_reset(struct ure_softc *sc) 1172 { 1173 struct ifnet *ifp = &sc->ure_ac.ac_if; 1174 uint32_t reg = 0; 1175 uint8_t u1u2[8] = { 0 }; 1176 int i; 1177 1178 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156)) { 1179 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, 1180 LPM_U1U2_EN); 1181 } else { 1182 memset(u1u2, 0x00, sizeof(u1u2)); 1183 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, 1184 u1u2, sizeof(u1u2)); 1185 } 1186 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1187 1188 /* Disable ALDPS. */ 1189 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1190 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 1191 for (i = 0; i < 20; i++) { 1192 usbd_delay_ms(sc->ure_udev, 1); 1193 if (ure_read_2(sc, 0xe000, URE_MCU_TYPE_PLA) & 0x0100) 1194 break; 1195 } 1196 if (sc->ure_flags & URE_FLAG_8153B) { 1197 URE_CLRBIT_4(sc, URE_USB_UPS_FLAGS, URE_MCU_TYPE_USB, 1198 URE_UPS_FLAGS_EN_ALDPS); 1199 } 1200 1201 if (!(sc->ure_flags & URE_FLAG_8156)) { 1202 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0); 1203 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 0); 1204 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 0); 1205 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0); 1206 } 1207 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 1208 ure_disable_teredo(sc); 1209 1210 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL); 1211 1212 if (sc->ure_flags & URE_FLAG_8156) 1213 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 1214 else 1215 ure_reset(sc); 1216 1217 ure_reset_bmu(sc); 1218 1219 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB); 1220 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN); 1221 1222 if (!(sc->ure_flags & URE_FLAG_8156)) { 1223 for (i = 0; i < URE_TIMEOUT; i++) { 1224 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1225 URE_LINK_LIST_READY) 1226 break; 1227 usbd_delay_ms(sc->ure_udev, 1); 1228 } 1229 if (i == URE_TIMEOUT) 1230 printf("%s: timeout waiting for OOB control\n", 1231 sc->ure_dev.dv_xname); 1232 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 1233 URE_RE_INIT_LL); 1234 for (i = 0; i < URE_TIMEOUT; i++) { 1235 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1236 URE_LINK_LIST_READY) 1237 break; 1238 usbd_delay_ms(sc->ure_udev, 1); 1239 } 1240 if (i == URE_TIMEOUT) 1241 printf("%s: timeout waiting for OOB control\n", 1242 sc->ure_dev.dv_xname); 1243 } 1244 ure_rxvlan(sc); 1245 ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA, 1246 URE_FRAMELEN(ifp->if_mtu)); 1247 ure_write_1(sc, URE_PLA_MTPS, URE_MCU_TYPE_PLA, MTPS_JUMBO); 1248 1249 if (!(sc->ure_flags & URE_FLAG_8156)) { 1250 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 1251 URE_TCR0_AUTO_FIFO); 1252 ure_reset(sc); 1253 } 1254 1255 /* Configure Rx FIFO threshold. */ 1256 if (sc->ure_flags & URE_FLAG_8156) { 1257 ure_write_2(sc, URE_PLA_RXFIFO_CTRL0 + 2, URE_MCU_TYPE_PLA, 1258 0x0008); 1259 ure_write_2(sc, URE_PLA_RXFIFO_CTRL1 + 2, URE_MCU_TYPE_PLA, 1260 0x0100); 1261 ure_write_2(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, 0); 1262 } else { 1263 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 1264 URE_RXFIFO_THR1_NORMAL); 1265 ure_write_2(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, 1266 URE_RXFIFO_THR2_NORMAL); 1267 ure_write_2(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, 1268 URE_RXFIFO_THR3_NORMAL); 1269 } 1270 1271 /* Configure Tx FIFO threshold. */ 1272 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 1273 URE_TXFIFO_THR_NORMAL2); 1274 1275 if (sc->ure_flags & URE_FLAG_8156) { 1276 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 1277 0x4000); 1278 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, 1279 0x00600400); 1280 } else if (sc->ure_flags & URE_FLAG_8153B) { 1281 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, 1282 URE_RX_THR_B); 1283 } 1284 1285 /* Enable ALDPS. */ 1286 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1287 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | URE_EN_ALDPS); 1288 if (sc->ure_flags & URE_FLAG_8153B) { 1289 reg = ure_read_4(sc, URE_USB_UPS_FLAGS, URE_MCU_TYPE_USB) & 1290 URE_UPS_FLAGS_MASK; 1291 ure_write_4(sc, URE_USB_UPS_FLAGS, URE_MCU_TYPE_USB, 1292 reg | URE_UPS_FLAGS_EN_ALDPS); 1293 } 1294 1295 if ((sc->ure_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) || 1296 (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156))) 1297 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 1298 URE_U2P3_ENABLE); 1299 1300 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156)) { 1301 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, 1302 LPM_U1U2_EN); 1303 } else { 1304 memset(u1u2, 0xff, sizeof(u1u2)); 1305 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, 1306 u1u2, sizeof(u1u2)); 1307 } 1308 } 1309 1310 void 1311 ure_rtl8153_phy_status(struct ure_softc *sc, int enable) 1312 { 1313 uint16_t reg; 1314 int i; 1315 1316 for (i = 0; i < 500; i++) { 1317 reg = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & 1318 URE_PHY_STAT_MASK; 1319 if (enable) { 1320 if (reg == URE_PHY_STAT_LAN_ON) 1321 break; 1322 } else { 1323 if (reg == URE_PHY_STAT_LAN_ON || 1324 reg == URE_PHY_STAT_PWRDN || 1325 reg == URE_PHY_STAT_EXT_INIT) 1326 break; 1327 } 1328 usbd_delay_ms(sc->ure_udev, 20); 1329 } 1330 if (i == 500) 1331 printf("%s: timeout waiting for phy to stabilize\n", 1332 sc->ure_dev.dv_xname); 1333 } 1334 1335 void 1336 ure_reset_bmu(struct ure_softc *sc) 1337 { 1338 URE_CLRBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, 1339 BMU_RESET_EP_IN | BMU_RESET_EP_OUT); 1340 URE_SETBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, 1341 BMU_RESET_EP_IN | BMU_RESET_EP_OUT); 1342 } 1343 1344 void 1345 ure_disable_teredo(struct ure_softc *sc) 1346 { 1347 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156)) 1348 ure_write_1(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 0xff); 1349 else { 1350 URE_CLRBIT_2(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 1351 URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | 1352 URE_OOB_TEREDO_EN); 1353 } 1354 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, URE_WDT6_SET_MODE); 1355 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 1356 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 1357 } 1358 1359 int 1360 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1361 { 1362 struct ure_softc *sc = ifp->if_softc; 1363 struct ifreq *ifr = (struct ifreq *)data; 1364 int s, error = 0; 1365 1366 s = splnet(); 1367 1368 switch (cmd) { 1369 case SIOCSIFADDR: 1370 ifp->if_flags |= IFF_UP; 1371 if (!(ifp->if_flags & IFF_RUNNING)) 1372 ure_init(sc); 1373 break; 1374 1375 case SIOCSIFFLAGS: 1376 if (ifp->if_flags & IFF_UP) { 1377 if (ifp->if_flags & IFF_RUNNING) 1378 error = ENETRESET; 1379 else 1380 ure_init(sc); 1381 } else { 1382 if (ifp->if_flags & IFF_RUNNING) 1383 ure_stop(sc); 1384 } 1385 break; 1386 1387 case SIOCGIFMEDIA: 1388 case SIOCSIFMEDIA: 1389 if (sc->ure_flags & URE_FLAG_8156) 1390 error = ifmedia_ioctl(ifp, ifr, &sc->ure_ifmedia, cmd); 1391 else 1392 error = ifmedia_ioctl(ifp, ifr, &sc->ure_mii.mii_media, 1393 cmd); 1394 break; 1395 1396 default: 1397 error = ether_ioctl(ifp, &sc->ure_ac, cmd, data); 1398 } 1399 1400 if (error == ENETRESET) { 1401 if (ifp->if_flags & IFF_RUNNING) 1402 ure_iff(sc); 1403 error = 0; 1404 } 1405 1406 splx(s); 1407 1408 return (error); 1409 } 1410 1411 int 1412 ure_match(struct device *parent, void *match, void *aux) 1413 { 1414 struct usb_attach_arg *uaa = aux; 1415 1416 if (uaa->iface == NULL || uaa->configno != 1) 1417 return (UMATCH_NONE); 1418 1419 return (usb_lookup(ure_devs, uaa->vendor, uaa->product) != NULL ? 1420 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 1421 } 1422 1423 void 1424 ure_attach(struct device *parent, struct device *self, void *aux) 1425 { 1426 struct ure_softc *sc = (struct ure_softc *)self; 1427 struct usb_attach_arg *uaa = aux; 1428 usb_interface_descriptor_t *id; 1429 usb_endpoint_descriptor_t *ed; 1430 u_char eaddr[8]; /* 4byte padded */ 1431 struct ifnet *ifp; 1432 int i, mii_flags = 0, s; 1433 uint16_t ver; 1434 1435 sc->ure_udev = uaa->device; 1436 sc->ure_iface = uaa->iface; 1437 1438 usb_init_task(&sc->ure_tick_task, ure_tick_task, sc, 1439 USB_TASK_TYPE_GENERIC); 1440 usb_init_task(&sc->ure_stop_task, (void (*)(void *))ure_stop, sc, 1441 USB_TASK_TYPE_GENERIC); 1442 1443 id = usbd_get_interface_descriptor(sc->ure_iface); 1444 1445 for (i = 0; i < id->bNumEndpoints; i++) { 1446 ed = usbd_interface2endpoint_descriptor(sc->ure_iface, i); 1447 if (!ed) { 1448 printf("%s: couldn't get ep %d\n", 1449 sc->ure_dev.dv_xname, i); 1450 return; 1451 } 1452 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 1453 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 1454 sc->ure_ed[URE_ENDPT_RX] = ed->bEndpointAddress; 1455 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 1456 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 1457 sc->ure_ed[URE_ENDPT_TX] = ed->bEndpointAddress; 1458 } 1459 } 1460 1461 switch (uaa->product) { 1462 case USB_PRODUCT_REALTEK_RTL8152: 1463 sc->ure_flags |= URE_FLAG_8152; 1464 sc->ure_rxbufsz = URE_8152_RXBUFSZ; 1465 sc->ure_tx_list_cnt = 1; 1466 break; 1467 case USB_PRODUCT_REALTEK_RTL8156: 1468 sc->ure_flags |= URE_FLAG_8156; 1469 sc->ure_rxbufsz = URE_8153_RXBUFSZ; 1470 sc->ure_tx_list_cnt = URE_TX_LIST_CNT; 1471 break; 1472 default: 1473 sc->ure_rxbufsz = URE_8153_RXBUFSZ; 1474 sc->ure_tx_list_cnt = 1; 1475 } 1476 1477 s = splnet(); 1478 1479 sc->ure_phyno = 0; 1480 printf("%s: ", sc->ure_dev.dv_xname); 1481 1482 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 1483 switch (ver) { 1484 case 0x4c00: 1485 sc->ure_chip |= URE_CHIP_VER_4C00; 1486 printf("RTL8152 (0x4c00)"); 1487 break; 1488 case 0x4c10: 1489 sc->ure_chip |= URE_CHIP_VER_4C10; 1490 printf("RTL8152 (0x4c10)"); 1491 break; 1492 case 0x5c00: 1493 sc->ure_chip |= URE_CHIP_VER_5C00; 1494 printf("RTL8153 (0x5c00)"); 1495 break; 1496 case 0x5c10: 1497 sc->ure_chip |= URE_CHIP_VER_5C10; 1498 printf("RTL8153 (0x5c10)"); 1499 break; 1500 case 0x5c20: 1501 sc->ure_chip |= URE_CHIP_VER_5C20; 1502 printf("RTL8153 (0x5c20)"); 1503 break; 1504 case 0x5c30: 1505 sc->ure_chip |= URE_CHIP_VER_5C30; 1506 printf("RTL8153 (0x5c30)"); 1507 break; 1508 case 0x6000: 1509 sc->ure_flags = URE_FLAG_8153B; 1510 sc->ure_tx_list_cnt = URE_TX_LIST_CNT; 1511 printf("RTL8153B (0x6000)"); 1512 break; 1513 case 0x6010: 1514 sc->ure_flags = URE_FLAG_8153B; 1515 sc->ure_tx_list_cnt = URE_TX_LIST_CNT; 1516 printf("RTL8153B (0x6010)"); 1517 break; 1518 case 0x7020: 1519 printf("RTL8156 (0x7020)"); 1520 break; 1521 case 0x7030: 1522 printf("RTL8156 (0x7030)"); 1523 break; 1524 default: 1525 printf(", unknown ver %02x", ver); 1526 break; 1527 } 1528 1529 if (sc->ure_flags & URE_FLAG_8152) 1530 ure_rtl8152_init(sc); 1531 else if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156)) 1532 ure_rtl8153b_init(sc); 1533 else 1534 ure_rtl8153_init(sc); 1535 1536 if (sc->ure_chip & URE_CHIP_VER_4C00) 1537 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr, 1538 sizeof(eaddr)); 1539 else 1540 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr, 1541 sizeof(eaddr)); 1542 1543 printf(", address %s\n", ether_sprintf(eaddr)); 1544 1545 bcopy(eaddr, (char *)&sc->ure_ac.ac_enaddr, ETHER_ADDR_LEN); 1546 1547 ifp = &sc->ure_ac.ac_if; 1548 ifp->if_softc = sc; 1549 strlcpy(ifp->if_xname, sc->ure_dev.dv_xname, IFNAMSIZ); 1550 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1551 ifp->if_ioctl = ure_ioctl; 1552 ifp->if_start = ure_start; 1553 ifp->if_watchdog = ure_watchdog; 1554 1555 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 | 1556 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1557 1558 #if NVLAN > 0 1559 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1560 #endif 1561 1562 if (sc->ure_flags & URE_FLAG_8156) { 1563 ifmedia_init(&sc->ure_ifmedia, IFM_IMASK, ure_ifmedia_upd, 1564 ure_ifmedia_sts); 1565 ure_add_media_types(sc); 1566 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1567 ifmedia_set(&sc->ure_ifmedia, IFM_ETHER | IFM_AUTO); 1568 sc->ure_ifmedia.ifm_media = sc->ure_ifmedia.ifm_cur->ifm_media; 1569 } else { 1570 rw_init(&sc->ure_mii_lock, "uremii"); 1571 1572 sc->ure_mii.mii_ifp = ifp; 1573 sc->ure_mii.mii_readreg = ure_miibus_readreg; 1574 sc->ure_mii.mii_writereg = ure_miibus_writereg; 1575 sc->ure_mii.mii_statchg = ure_miibus_statchg; 1576 sc->ure_mii.mii_flags = MIIF_AUTOTSLEEP; 1577 1578 ifmedia_init(&sc->ure_mii.mii_media, 0, ure_ifmedia_upd, 1579 ure_ifmedia_sts); 1580 if (!(sc->ure_flags & URE_FLAG_8152)) 1581 mii_flags |= MIIF_DOPAUSE; 1582 mii_attach(self, &sc->ure_mii, 0xffffffff, sc->ure_phyno, 1583 MII_OFFSET_ANY, mii_flags); 1584 if (LIST_FIRST(&sc->ure_mii.mii_phys) == NULL) { 1585 ifmedia_add(&sc->ure_mii.mii_media, 1586 IFM_ETHER | IFM_NONE, 0, NULL); 1587 ifmedia_set(&sc->ure_mii.mii_media, 1588 IFM_ETHER | IFM_NONE); 1589 } else 1590 ifmedia_set(&sc->ure_mii.mii_media, 1591 IFM_ETHER | IFM_AUTO); 1592 } 1593 1594 if_attach(ifp); 1595 ether_ifattach(ifp); 1596 1597 timeout_set(&sc->ure_stat_ch, ure_tick, sc); 1598 1599 splx(s); 1600 } 1601 1602 int 1603 ure_detach(struct device *self, int flags) 1604 { 1605 struct ure_softc *sc = (struct ure_softc *)self; 1606 struct ifnet *ifp = &sc->ure_ac.ac_if; 1607 int s; 1608 1609 if (timeout_initialized(&sc->ure_stat_ch)) 1610 timeout_del(&sc->ure_stat_ch); 1611 1612 if (sc->ure_ep[URE_ENDPT_TX] != NULL) 1613 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_TX]); 1614 if (sc->ure_ep[URE_ENDPT_RX] != NULL) 1615 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_RX]); 1616 1617 usb_rem_task(sc->ure_udev, &sc->ure_tick_task); 1618 usb_rem_task(sc->ure_udev, &sc->ure_stop_task); 1619 1620 s = splusb(); 1621 1622 if (--sc->ure_refcnt >= 0) { 1623 usb_detach_wait(&sc->ure_dev); 1624 } 1625 1626 if (ifp->if_flags & IFF_RUNNING) 1627 ure_stop(sc); 1628 1629 mii_detach(&sc->ure_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1630 ifmedia_delete_instance(&sc->ure_mii.mii_media, IFM_INST_ANY); 1631 if (ifp->if_softc != NULL) { 1632 ether_ifdetach(ifp); 1633 if_detach(ifp); 1634 } 1635 1636 splx(s); 1637 1638 return 0; 1639 } 1640 1641 void 1642 ure_tick_task(void *xsc) 1643 { 1644 int s; 1645 struct ure_softc *sc = xsc; 1646 struct mii_data *mii; 1647 1648 if (sc == NULL) 1649 return; 1650 1651 if (usbd_is_dying(sc->ure_udev)) 1652 return; 1653 mii = &sc->ure_mii; 1654 1655 s = splnet(); 1656 if (sc->ure_flags & URE_FLAG_8156) 1657 ure_link_state(sc); 1658 else { 1659 mii_tick(mii); 1660 if ((sc->ure_flags & URE_FLAG_LINK) == 0) 1661 ure_miibus_statchg(&sc->ure_dev); 1662 } 1663 timeout_add_sec(&sc->ure_stat_ch, 1); 1664 splx(s); 1665 } 1666 1667 void 1668 ure_lock_mii(struct ure_softc *sc) 1669 { 1670 sc->ure_refcnt++; 1671 rw_enter_write(&sc->ure_mii_lock); 1672 } 1673 1674 void 1675 ure_unlock_mii(struct ure_softc *sc) 1676 { 1677 rw_exit_write(&sc->ure_mii_lock); 1678 if (--sc->ure_refcnt < 0) 1679 usb_detach_wakeup(&sc->ure_dev); 1680 } 1681 1682 void 1683 ure_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1684 { 1685 struct ure_chain *c = (struct ure_chain *)priv; 1686 struct ure_softc *sc = c->uc_sc; 1687 struct ifnet *ifp = &sc->ure_ac.ac_if; 1688 u_char *buf = c->uc_buf; 1689 uint32_t cflags, rxvlan, total_len; 1690 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1691 struct mbuf *m; 1692 int pktlen = 0, s; 1693 struct ure_rxpkt rxhdr; 1694 1695 if (usbd_is_dying(sc->ure_udev)) 1696 return; 1697 1698 if (!(ifp->if_flags & IFF_RUNNING)) 1699 return; 1700 1701 if (status != USBD_NORMAL_COMPLETION) { 1702 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 1703 return; 1704 if (usbd_ratecheck(&sc->ure_rx_notice)) { 1705 printf("%s: usb errors on rx: %s\n", 1706 sc->ure_dev.dv_xname, usbd_errstr(status)); 1707 } 1708 if (status == USBD_STALLED) 1709 usbd_clear_endpoint_stall_async( 1710 sc->ure_ep[URE_ENDPT_RX]); 1711 goto done; 1712 } 1713 1714 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL); 1715 DPRINTFN(3, ("received %d bytes\n", total_len)); 1716 1717 do { 1718 if (total_len < sizeof(rxhdr)) { 1719 DPRINTF(("too few bytes left for a packet header\n")); 1720 ifp->if_ierrors++; 1721 goto done; 1722 } 1723 1724 buf += roundup(pktlen, 8); 1725 1726 memcpy(&rxhdr, buf, sizeof(rxhdr)); 1727 total_len -= sizeof(rxhdr); 1728 1729 pktlen = letoh32(rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK; 1730 DPRINTFN(4, ("next packet is %d bytes\n", pktlen)); 1731 if (pktlen > total_len) { 1732 DPRINTF(("not enough bytes left for next packet\n")); 1733 ifp->if_ierrors++; 1734 goto done; 1735 } 1736 1737 total_len -= roundup(pktlen, 8); 1738 buf += sizeof(rxhdr); 1739 1740 m = m_devget(buf, pktlen, ETHER_ALIGN); 1741 if (m == NULL) { 1742 DPRINTF(("unable to allocate mbuf for next packet\n")); 1743 ifp->if_ierrors++; 1744 goto done; 1745 } 1746 1747 cflags = letoh32(rxhdr.ure_csum); 1748 rxvlan = letoh32(rxhdr.ure_vlan); 1749 1750 /* Check IP header checksum. */ 1751 if ((rxvlan & URE_RXPKT_IPV4) && 1752 !(cflags & URE_RXPKT_IPSUMBAD)) 1753 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1754 1755 /* Check TCP/UDP checksum. */ 1756 if ((rxvlan & (URE_RXPKT_IPV4 | URE_RXPKT_IPV6)) && 1757 (((rxvlan & URE_RXPKT_TCP) && 1758 !(cflags & URE_RXPKT_TCPSUMBAD)) || 1759 ((rxvlan & URE_RXPKT_UDP) && 1760 !(cflags & URE_RXPKT_UDPSUMBAD)))) 1761 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | 1762 M_UDP_CSUM_IN_OK; 1763 #if NVLAN > 0 1764 if (rxvlan & URE_RXPKT_VLAN_TAG) { 1765 m->m_pkthdr.ether_vtag = 1766 swap16(rxvlan & URE_RXPKT_VLAN_DATA); 1767 m->m_flags |= M_VLANTAG; 1768 } 1769 #endif 1770 1771 ml_enqueue(&ml, m); 1772 } while (total_len > 0); 1773 1774 done: 1775 s = splnet(); 1776 if_input(ifp, &ml); 1777 splx(s); 1778 memset(c->uc_buf, 0, sc->ure_rxbufsz); 1779 1780 usbd_setup_xfer(xfer, sc->ure_ep[URE_ENDPT_RX], c, c->uc_buf, 1781 sc->ure_rxbufsz, USBD_SHORT_XFER_OK | USBD_NO_COPY, 1782 USBD_NO_TIMEOUT, ure_rxeof); 1783 usbd_transfer(xfer); 1784 } 1785 1786 1787 void 1788 ure_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1789 { 1790 struct ure_softc *sc; 1791 struct ure_chain *c; 1792 struct ifnet *ifp; 1793 int s; 1794 1795 c = priv; 1796 sc = c->uc_sc; 1797 ifp = &sc->ure_ac.ac_if; 1798 1799 if (usbd_is_dying(sc->ure_udev)) 1800 return; 1801 1802 DPRINTFN(2, ("tx completion\n")); 1803 1804 s = splnet(); 1805 sc->ure_cdata.tx_cnt--; 1806 if (status != USBD_NORMAL_COMPLETION) { 1807 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) { 1808 splx(s); 1809 return; 1810 } 1811 ifp->if_oerrors++; 1812 printf("%s: usb error on tx: %s\n", sc->ure_dev.dv_xname, 1813 usbd_errstr(status)); 1814 if (status == USBD_STALLED) 1815 usbd_clear_endpoint_stall_async( 1816 sc->ure_ep[URE_ENDPT_TX]); 1817 splx(s); 1818 return; 1819 } 1820 1821 ifp->if_timer = 0; 1822 ifq_clr_oactive(&ifp->if_snd); 1823 1824 m_freem(c->uc_mbuf); 1825 c->uc_mbuf = NULL; 1826 1827 if (!ifq_empty(&ifp->if_snd)) 1828 ure_start(ifp); 1829 1830 splx(s); 1831 } 1832 1833 int 1834 ure_tx_list_init(struct ure_softc *sc) 1835 { 1836 struct ure_cdata *cd; 1837 struct ure_chain *c; 1838 int i; 1839 1840 cd = &sc->ure_cdata; 1841 for (i = 0; i < sc->ure_tx_list_cnt; i++) { 1842 c = &cd->tx_chain[i]; 1843 c->uc_sc = sc; 1844 c->uc_idx = i; 1845 c->uc_mbuf = NULL; 1846 if (c->uc_xfer == NULL) { 1847 c->uc_xfer = usbd_alloc_xfer(sc->ure_udev); 1848 if (c->uc_xfer == NULL) 1849 return ENOBUFS; 1850 c->uc_buf = usbd_alloc_buffer(c->uc_xfer, URE_TXBUFSZ); 1851 if (c->uc_buf == NULL) { 1852 usbd_free_xfer(c->uc_xfer); 1853 return ENOBUFS; 1854 } 1855 } 1856 } 1857 1858 cd->tx_prod = cd->tx_cnt = 0; 1859 1860 return (0); 1861 } 1862 1863 int 1864 ure_rx_list_init(struct ure_softc *sc) 1865 { 1866 struct ure_cdata *cd; 1867 struct ure_chain *c; 1868 int i; 1869 1870 cd = &sc->ure_cdata; 1871 for (i = 0; i < URE_RX_LIST_CNT; i++) { 1872 c = &cd->rx_chain[i]; 1873 c->uc_sc = sc; 1874 c->uc_idx = i; 1875 c->uc_mbuf = NULL; 1876 if (c->uc_xfer == NULL) { 1877 c->uc_xfer = usbd_alloc_xfer(sc->ure_udev); 1878 if (c->uc_xfer == NULL) 1879 return ENOBUFS; 1880 c->uc_buf = usbd_alloc_buffer(c->uc_xfer, 1881 sc->ure_rxbufsz); 1882 if (c->uc_buf == NULL) { 1883 usbd_free_xfer(c->uc_xfer); 1884 return ENOBUFS; 1885 } 1886 } 1887 } 1888 1889 return (0); 1890 } 1891 1892 int 1893 ure_encap(struct ure_softc *sc, struct mbuf *m) 1894 { 1895 struct ure_chain *c; 1896 usbd_status err; 1897 struct ure_txpkt txhdr; 1898 uint32_t frm_len = 0, cflags = 0; 1899 1900 if ((m->m_pkthdr.csum_flags & 1901 (M_IPV4_CSUM_OUT | M_TCP_CSUM_OUT | M_UDP_CSUM_OUT)) != 0) { 1902 cflags |= URE_TXPKT_IPV4; 1903 if (m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) 1904 cflags |= URE_TXPKT_TCP; 1905 if (m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) 1906 cflags |= URE_TXPKT_UDP; 1907 } 1908 1909 #if NVLAN > 0 1910 if (m->m_flags & M_VLANTAG) 1911 cflags |= swap16(m->m_pkthdr.ether_vtag | URE_TXPKT_VLAN_TAG); 1912 #endif 1913 1914 c = &sc->ure_cdata.tx_chain[sc->ure_cdata.tx_prod]; 1915 1916 /* header */ 1917 txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS | 1918 URE_TXPKT_TX_LS); 1919 txhdr.ure_vlan = htole32(cflags); 1920 memcpy(c->uc_buf, &txhdr, sizeof(txhdr)); 1921 frm_len = sizeof(txhdr); 1922 1923 /* packet */ 1924 m_copydata(m, 0, m->m_pkthdr.len, c->uc_buf + frm_len); 1925 frm_len += m->m_pkthdr.len; 1926 1927 c->uc_mbuf = m; 1928 1929 DPRINTFN(2, ("tx %d bytes\n", frm_len)); 1930 usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_TX], c, c->uc_buf, 1931 frm_len, USBD_FORCE_SHORT_XFER | USBD_NO_COPY, 10000, ure_txeof); 1932 1933 err = usbd_transfer(c->uc_xfer); 1934 if (err != 0 && err != USBD_IN_PROGRESS) { 1935 c->uc_mbuf = NULL; 1936 ure_stop(sc); 1937 return (EIO); 1938 } 1939 1940 sc->ure_cdata.tx_cnt++; 1941 sc->ure_cdata.tx_prod = (sc->ure_cdata.tx_prod + 1) % 1942 sc->ure_tx_list_cnt; 1943 1944 return (0); 1945 } 1946