1 /* $OpenBSD: if_ure.c,v 1.31 2022/10/27 13:21:14 patrick Exp $ */ 2 /*- 3 * Copyright (c) 2015, 2016, 2019 Kevin Lo <kevlo@openbsd.org> 4 * Copyright (c) 2020 Jonathon Fletcher <jonathon.fletcher@gmail.com> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "bpfilter.h" 30 #include "vlan.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/sockio.h> 35 #include <sys/rwlock.h> 36 #include <sys/mbuf.h> 37 #include <sys/kernel.h> 38 #include <sys/socket.h> 39 #include <sys/device.h> 40 41 #include <machine/bus.h> 42 43 #include <net/if.h> 44 #include <net/if_media.h> 45 46 #if NBPFILTER > 0 47 #include <net/bpf.h> 48 #endif 49 50 #include <netinet/in.h> 51 #include <netinet/if_ether.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 56 #include <dev/usb/usb.h> 57 #include <dev/usb/usbdi.h> 58 #include <dev/usb/usbdi_util.h> 59 #include <dev/usb/usbdivar.h> 60 #include <dev/usb/usbdevs.h> 61 62 #include <dev/ic/rtl81x9reg.h> 63 #include <dev/usb/if_urereg.h> 64 65 #ifdef URE_DEBUG 66 #define DPRINTF(x) do { if (uredebug) printf x; } while (0) 67 #define DPRINTFN(n,x) do { if (uredebug >= (n)) printf x; } while (0) 68 int uredebug = 0; 69 #else 70 #define DPRINTF(x) 71 #define DPRINTFN(n,x) 72 #endif 73 74 const struct usb_devno ure_devs[] = { 75 { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_RTL8156 }, 76 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8152B }, 77 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8153 }, 78 { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB3GIGV1 }, 79 { USB_VENDOR_CLEVO, USB_PRODUCT_CLEVO_RTL8153B }, 80 { USB_VENDOR_CLUB3D, USB_PRODUCT_CLUB3D_RTL8153 }, 81 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8153_1 }, 82 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8153_2 }, 83 { USB_VENDOR_DYNABOOK, USB_PRODUCT_DYNABOOK_RTL8153B_1 }, 84 { USB_VENDOR_DYNABOOK, USB_PRODUCT_DYNABOOK_RTL8153B_2 }, 85 { USB_VENDOR_ELECOM, USB_PRODUCT_ELECOM_RTL8153B }, 86 { USB_VENDOR_ELECOM, USB_PRODUCT_ELECOM_RTL8156B }, 87 { USB_VENDOR_IOI, USB_PRODUCT_IOI_RTL8153 }, 88 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_DOCK_ETHERNET }, 89 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ONELINK }, 90 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ONELINKPLUS }, 91 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ONELINKPRO }, 92 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_1 }, 93 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_2 }, 94 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_3 }, 95 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_4 }, 96 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_5 }, 97 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_6 }, 98 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_7 }, 99 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_8 }, 100 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_9 }, 101 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153_1 }, 102 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153_2 }, 103 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153_3 }, 104 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TABLETDOCK }, 105 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TB3DOCK }, 106 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TB3DOCKGEN2 }, 107 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TB3GFXDOCK }, 108 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_USBCDOCKGEN2 }, 109 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_WIGIGDOCK }, 110 { USB_VENDOR_LG, USB_PRODUCT_LG_RTL8153 }, 111 { USB_VENDOR_LG, USB_PRODUCT_LG_RTL8153B }, 112 { USB_VENDOR_LUXSHARE, USB_PRODUCT_LUXSHARE_RTL8153 }, 113 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_DOCKETH }, 114 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_DOCKETH2 }, 115 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_SURFETH }, 116 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_WINDEVETH }, 117 { USB_VENDOR_NVIDIA, USB_PRODUCT_NVIDIA_TEGRAETH }, 118 { USB_VENDOR_PIONEERDJ, USB_PRODUCT_PIONEERDJ_RTL8152B }, 119 { USB_VENDOR_PIONEERDJ, USB_PRODUCT_PIONEERDJ_RTL8153B }, 120 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 }, 121 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152B }, 122 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8153 }, 123 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8156 }, 124 { USB_VENDOR_SAMSUNG2, USB_PRODUCT_SAMSUNG2_RTL8153 }, 125 { USB_VENDOR_TOSHIBA, USB_PRODUCT_TOSHIBA_RTL8153B }, 126 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_EU300 }, 127 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_RTL8152B_1 }, 128 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_RTL8152B_2 }, 129 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_RTL8153 }, 130 { USB_VENDOR_TRENDNET, USB_PRODUCT_TRENDNET_RTL8156 }, 131 { USB_VENDOR_TTL, USB_PRODUCT_TTL_RTL8153 }, 132 { USB_VENDOR_TWINHEAD, USB_PRODUCT_TWINHEAD_RTL8153B }, 133 { USB_VENDOR_XIAOMI, USB_PRODUCT_XIAOMI_RTL8152B }, 134 }; 135 136 int ure_match(struct device *, void *, void *); 137 void ure_attach(struct device *, struct device *, void *); 138 int ure_detach(struct device *, int); 139 140 struct cfdriver ure_cd = { 141 NULL, "ure", DV_IFNET 142 }; 143 144 const struct cfattach ure_ca = { 145 sizeof(struct ure_softc), ure_match, ure_attach, ure_detach 146 }; 147 148 int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t, 149 void *, int); 150 int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *, 151 int); 152 int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *, 153 int); 154 uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t); 155 uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t); 156 uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t); 157 int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t); 158 int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t); 159 int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t); 160 uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t); 161 void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t); 162 163 void ure_init(void *); 164 void ure_stop(struct ure_softc *); 165 void ure_start(struct ifnet *); 166 void ure_reset(struct ure_softc *); 167 void ure_watchdog(struct ifnet *); 168 169 void ure_miibus_statchg(struct device *); 170 int ure_miibus_readreg(struct device *, int, int); 171 void ure_miibus_writereg(struct device *, int, int, int); 172 void ure_lock_mii(struct ure_softc *); 173 void ure_unlock_mii(struct ure_softc *); 174 175 int ure_encap_txpkt(struct mbuf *, char *, uint32_t); 176 int ure_encap_xfer(struct ifnet *, struct ure_softc *, 177 struct ure_chain *); 178 void ure_rxeof(struct usbd_xfer *, void *, usbd_status); 179 void ure_txeof(struct usbd_xfer *, void *, usbd_status); 180 int ure_xfer_list_init(struct ure_softc *, struct ure_chain *, 181 uint32_t, int); 182 void ure_xfer_list_free(struct ure_softc *, struct ure_chain *, int); 183 184 void ure_tick_task(void *); 185 void ure_tick(void *); 186 187 void ure_ifmedia_init(struct ifnet *); 188 int ure_ifmedia_upd(struct ifnet *); 189 void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *); 190 void ure_add_media_types(struct ure_softc *); 191 void ure_link_state(struct ure_softc *); 192 int ure_get_link_status(struct ure_softc *); 193 void ure_iff(struct ure_softc *); 194 void ure_rxvlan(struct ure_softc *); 195 int ure_ioctl(struct ifnet *, u_long, caddr_t); 196 void ure_rtl8152_init(struct ure_softc *); 197 void ure_rtl8153_init(struct ure_softc *); 198 void ure_rtl8153b_init(struct ure_softc *); 199 void ure_rtl8152_nic_reset(struct ure_softc *); 200 void ure_rtl8153_nic_reset(struct ure_softc *); 201 uint16_t ure_rtl8153_phy_status(struct ure_softc *, int); 202 void ure_wait_for_flash(struct ure_softc *); 203 void ure_reset_bmu(struct ure_softc *); 204 void ure_disable_teredo(struct ure_softc *); 205 206 #define URE_SETBIT_1(sc, reg, index, x) \ 207 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x)) 208 #define URE_SETBIT_2(sc, reg, index, x) \ 209 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x)) 210 #define URE_SETBIT_4(sc, reg, index, x) \ 211 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x)) 212 213 #define URE_CLRBIT_1(sc, reg, index, x) \ 214 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~(x)) 215 #define URE_CLRBIT_2(sc, reg, index, x) \ 216 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~(x)) 217 #define URE_CLRBIT_4(sc, reg, index, x) \ 218 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~(x)) 219 220 int 221 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index, 222 void *buf, int len) 223 { 224 usb_device_request_t req; 225 usbd_status err; 226 227 if (usbd_is_dying(sc->ure_udev)) 228 return 0; 229 230 if (rw == URE_CTL_WRITE) 231 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 232 else 233 req.bmRequestType = UT_READ_VENDOR_DEVICE; 234 req.bRequest = UR_SET_ADDRESS; 235 USETW(req.wValue, val); 236 USETW(req.wIndex, index); 237 USETW(req.wLength, len); 238 239 DPRINTFN(5, ("ure_ctl: rw %d, val 0x%04hu, index 0x%04hu, len %d\n", 240 rw, val, index, len)); 241 err = usbd_do_request(sc->ure_udev, &req, buf); 242 if (err) { 243 DPRINTF(("ure_ctl: error %d\n", err)); 244 return -1; 245 } 246 247 return 0; 248 } 249 250 int 251 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 252 void *buf, int len) 253 { 254 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len)); 255 } 256 257 int 258 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 259 void *buf, int len) 260 { 261 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len)); 262 } 263 264 uint8_t 265 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index) 266 { 267 uint32_t val; 268 uint8_t temp[4]; 269 uint8_t shift; 270 271 shift = (reg & 3) << 3; 272 reg &= ~3; 273 274 ure_read_mem(sc, reg, index, &temp, 4); 275 val = UGETDW(temp); 276 val >>= shift; 277 278 return (val & 0xff); 279 } 280 281 uint16_t 282 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index) 283 { 284 uint32_t val; 285 uint8_t temp[4]; 286 uint8_t shift; 287 288 shift = (reg & 2) << 3; 289 reg &= ~3; 290 291 ure_read_mem(sc, reg, index, &temp, 4); 292 val = UGETDW(temp); 293 val >>= shift; 294 295 return (val & 0xffff); 296 } 297 298 uint32_t 299 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index) 300 { 301 uint8_t temp[4]; 302 303 ure_read_mem(sc, reg, index, &temp, 4); 304 return (UGETDW(temp)); 305 } 306 307 int 308 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 309 { 310 uint16_t byen; 311 uint8_t temp[4]; 312 uint8_t shift; 313 314 byen = URE_BYTE_EN_BYTE; 315 shift = reg & 3; 316 val &= 0xff; 317 318 if (reg & 3) { 319 byen <<= shift; 320 val <<= (shift << 3); 321 reg &= ~3; 322 } 323 324 USETDW(temp, val); 325 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 326 } 327 328 int 329 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 330 { 331 uint16_t byen; 332 uint8_t temp[4]; 333 uint8_t shift; 334 335 byen = URE_BYTE_EN_WORD; 336 shift = reg & 2; 337 val &= 0xffff; 338 339 if (reg & 2) { 340 byen <<= shift; 341 val <<= (shift << 3); 342 reg &= ~3; 343 } 344 345 USETDW(temp, val); 346 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 347 } 348 349 int 350 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 351 { 352 uint8_t temp[4]; 353 354 USETDW(temp, val); 355 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4)); 356 } 357 358 uint16_t 359 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr) 360 { 361 uint16_t reg; 362 363 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 364 reg = (addr & 0x0fff) | 0xb000; 365 366 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA)); 367 } 368 369 void 370 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 371 { 372 uint16_t reg; 373 374 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 375 reg = (addr & 0x0fff) | 0xb000; 376 377 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data); 378 } 379 380 int 381 ure_miibus_readreg(struct device *dev, int phy, int reg) 382 { 383 struct ure_softc *sc = (void *)dev; 384 uint16_t val; 385 386 if (usbd_is_dying(sc->ure_udev)) 387 return 0; 388 389 /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */ 390 if (reg == RL_GMEDIASTAT) 391 return ure_read_1(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA); 392 393 ure_lock_mii(sc); 394 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2); 395 ure_unlock_mii(sc); 396 397 return val; /* letoh16? */ 398 } 399 400 void 401 ure_miibus_writereg(struct device *dev, int phy, int reg, int val) 402 { 403 struct ure_softc *sc = (void *)dev; 404 405 ure_lock_mii(sc); 406 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val); /* htole16? */ 407 ure_unlock_mii(sc); 408 } 409 410 void 411 ure_miibus_statchg(struct device *dev) 412 { 413 struct ure_softc *sc = (void *)dev; 414 struct mii_data *mii = &sc->ure_mii; 415 struct ifnet *ifp = &sc->ure_ac.ac_if; 416 417 if ((ifp->if_flags & IFF_RUNNING) == 0) 418 return; 419 420 sc->ure_flags &= ~URE_FLAG_LINK; 421 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 422 (IFM_ACTIVE | IFM_AVALID)) { 423 switch (IFM_SUBTYPE(mii->mii_media_active)) { 424 case IFM_10_T: 425 case IFM_100_TX: 426 sc->ure_flags |= URE_FLAG_LINK; 427 break; 428 case IFM_1000_T: 429 if ((sc->ure_flags & URE_FLAG_8152) != 0) 430 break; 431 sc->ure_flags |= URE_FLAG_LINK; 432 break; 433 default: 434 break; 435 } 436 } 437 438 /* Lost link, do nothing. */ 439 if ((sc->ure_flags & URE_FLAG_LINK) == 0) 440 return; 441 442 /* 443 * After a link change the media settings are getting reset on the 444 * hardware, and need to be re-initialized again for communication 445 * to continue work. 446 */ 447 ure_ifmedia_init(ifp); 448 } 449 450 void 451 ure_ifmedia_init(struct ifnet *ifp) 452 { 453 struct ure_softc *sc = ifp->if_softc; 454 uint32_t reg = 0; 455 456 /* Set MAC address. */ 457 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 458 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 459 sc->ure_ac.ac_enaddr, 8); 460 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 461 462 if (!(sc->ure_flags & URE_FLAG_8152)) { 463 if (sc->ure_flags & URE_FLAG_8156B) 464 URE_CLRBIT_2(sc, URE_USB_RX_AGGR_NUM, URE_MCU_TYPE_USB, 465 URE_RX_AGGR_NUM_MASK); 466 467 reg = sc->ure_rxbufsz - URE_FRAMELEN(ifp->if_mtu) - 468 sizeof(struct ure_rxpkt) - URE_RX_BUF_ALIGN; 469 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | 470 URE_FLAG_8156B)) { 471 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, 472 reg / 8); 473 474 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 475 (sc->ure_flags & URE_FLAG_8153B) ? 158 : 80); 476 ure_write_2(sc, URE_USB_PM_CTRL_STATUS, 477 URE_MCU_TYPE_USB, 1875); 478 } else { 479 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, 480 reg / 4); 481 switch (sc->ure_udev->speed) { 482 case USB_SPEED_SUPER: 483 reg = URE_COALESCE_SUPER / 8; 484 break; 485 case USB_SPEED_HIGH: 486 reg = URE_COALESCE_HIGH / 8; 487 break; 488 default: 489 reg = URE_COALESCE_SLOW / 8; 490 break; 491 } 492 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 493 reg); 494 } 495 496 if ((sc->ure_chip & URE_CHIP_VER_6010) || 497 (sc->ure_flags & URE_FLAG_8156B)) { 498 URE_CLRBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, 499 URE_FC_PATCH_TASK); 500 usbd_delay_ms(sc->ure_udev, 1); 501 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, 502 URE_FC_PATCH_TASK); 503 } 504 } 505 506 /* Reset the packet filter. */ 507 URE_CLRBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN); 508 URE_SETBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN); 509 510 /* Enable transmit and receive. */ 511 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE); 512 513 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) { 514 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB, 515 URE_OWN_UPDATE | URE_OWN_CLEAR); 516 } 517 518 URE_CLRBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 519 } 520 521 int 522 ure_ifmedia_upd(struct ifnet *ifp) 523 { 524 struct ure_softc *sc = ifp->if_softc; 525 struct mii_data *mii = &sc->ure_mii; 526 struct ifmedia *ifm = &sc->ure_ifmedia; 527 int anar, gig, err, reg; 528 529 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 530 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 531 return (EINVAL); 532 533 reg = ure_ocp_reg_read(sc, 0xa5d4); 534 reg &= ~URE_ADV_2500TFDX; 535 536 anar = gig = 0; 537 switch (IFM_SUBTYPE(ifm->ifm_media)) { 538 case IFM_AUTO: 539 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 540 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 541 reg |= URE_ADV_2500TFDX; 542 break; 543 case IFM_2500_T: 544 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 545 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 546 reg |= URE_ADV_2500TFDX; 547 ifp->if_baudrate = IF_Mbps(2500); 548 break; 549 case IFM_1000_T: 550 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 551 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 552 ifp->if_baudrate = IF_Gbps(1); 553 break; 554 case IFM_100_TX: 555 anar |= ANAR_TX | ANAR_TX_FD; 556 ifp->if_baudrate = IF_Mbps(100); 557 break; 558 case IFM_10_T: 559 anar |= ANAR_10 | ANAR_10_FD; 560 ifp->if_baudrate = IF_Mbps(10); 561 break; 562 default: 563 printf("%s: unsupported media type\n", 564 sc->ure_dev.dv_xname); 565 return (EINVAL); 566 } 567 568 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_ANAR * 2, 569 anar | ANAR_PAUSE_ASYM | ANAR_FC); 570 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_100T2CR * 2, gig); 571 ure_ocp_reg_write(sc, 0xa5d4, reg); 572 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR, 573 BMCR_AUTOEN | BMCR_STARTNEG); 574 575 return (0); 576 } 577 578 if (mii->mii_instance) { 579 struct mii_softc *miisc; 580 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 581 PHY_RESET(miisc); 582 } 583 584 err = mii_mediachg(mii); 585 if (err == ENXIO) 586 return (0); 587 else 588 return (err); 589 } 590 591 void 592 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 593 { 594 struct ure_softc *sc = ifp->if_softc; 595 struct mii_data *mii = &sc->ure_mii; 596 uint16_t status = 0; 597 598 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 599 ifmr->ifm_status = IFM_AVALID; 600 if (ure_get_link_status(sc)) { 601 ifmr->ifm_status |= IFM_ACTIVE; 602 status = ure_read_2(sc, URE_PLA_PHYSTATUS, 603 URE_MCU_TYPE_PLA); 604 if ((status & URE_PHYSTATUS_FDX) || 605 (status & URE_PHYSTATUS_2500MBPS)) 606 ifmr->ifm_active |= IFM_FDX; 607 else 608 ifmr->ifm_active |= IFM_HDX; 609 if (status & URE_PHYSTATUS_10MBPS) 610 ifmr->ifm_active |= IFM_10_T; 611 else if (status & URE_PHYSTATUS_100MBPS) 612 ifmr->ifm_active |= IFM_100_TX; 613 else if (status & URE_PHYSTATUS_1000MBPS) 614 ifmr->ifm_active |= IFM_1000_T; 615 else if (status & URE_PHYSTATUS_2500MBPS) 616 ifmr->ifm_active |= IFM_2500_T; 617 } 618 return; 619 } 620 621 mii_pollstat(mii); 622 ifmr->ifm_active = mii->mii_media_active; 623 ifmr->ifm_status = mii->mii_media_status; 624 } 625 626 void 627 ure_add_media_types(struct ure_softc *sc) 628 { 629 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 630 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 631 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 632 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, 633 NULL); 634 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 635 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, 636 NULL); 637 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_2500_T, 0, NULL); 638 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_2500_T | IFM_FDX, 0, 639 NULL); 640 } 641 642 void 643 ure_link_state(struct ure_softc *sc) 644 { 645 struct ifnet *ifp = &sc->ure_ac.ac_if; 646 int link = LINK_STATE_DOWN; 647 648 if (ure_get_link_status(sc)) 649 link = LINK_STATE_UP; 650 651 if (ifp->if_link_state != link) { 652 ifp->if_link_state = link; 653 if_link_state_change(ifp); 654 } 655 } 656 657 int 658 ure_get_link_status(struct ure_softc *sc) 659 { 660 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & 661 URE_PHYSTATUS_LINK) { 662 sc->ure_flags |= URE_FLAG_LINK; 663 return (1); 664 } else { 665 sc->ure_flags &= ~URE_FLAG_LINK; 666 return (0); 667 } 668 } 669 670 void 671 ure_iff(struct ure_softc *sc) 672 { 673 struct ifnet *ifp = &sc->ure_ac.ac_if; 674 struct ether_multi *enm; 675 struct ether_multistep step; 676 uint32_t hashes[2] = { 0, 0 }; 677 uint32_t hash; 678 uint32_t rxmode; 679 680 if (usbd_is_dying(sc->ure_udev)) 681 return; 682 683 rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA); 684 rxmode &= ~URE_RCR_ACPT_ALL; 685 ifp->if_flags &= ~IFF_ALLMULTI; 686 687 /* 688 * Always accept frames destined to our station address. 689 * Always accept broadcast frames. 690 */ 691 rxmode |= URE_RCR_APM | URE_RCR_AB; 692 693 if (ifp->if_flags & IFF_PROMISC || sc->ure_ac.ac_multirangecnt > 0) { 694 ifp->if_flags |= IFF_ALLMULTI; 695 rxmode |= URE_RCR_AM; 696 if (ifp->if_flags & IFF_PROMISC) 697 rxmode |= URE_RCR_AAP; 698 hashes[0] = hashes[1] = 0xffffffff; 699 } else { 700 rxmode |= URE_RCR_AM; 701 702 ETHER_FIRST_MULTI(step, &sc->ure_ac, enm); 703 while (enm != NULL) { 704 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) 705 >> 26; 706 if (hash < 32) 707 hashes[0] |= (1 << hash); 708 else 709 hashes[1] |= (1 << (hash - 32)); 710 711 ETHER_NEXT_MULTI(step, enm); 712 } 713 714 hash = swap32(hashes[0]); 715 hashes[0] = swap32(hashes[1]); 716 hashes[1] = hash; 717 } 718 719 ure_write_mem(sc, URE_PLA_MAR, URE_MCU_TYPE_PLA | URE_BYTE_EN_DWORD, 720 hashes, sizeof(hashes)); 721 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 722 } 723 724 void 725 ure_rxvlan(struct ure_softc *sc) 726 { 727 struct ifnet *ifp = &sc->ure_ac.ac_if; 728 uint16_t reg; 729 730 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 731 reg = ure_read_2(sc, URE_PLA_RCR1, URE_MCU_TYPE_PLA); 732 reg &= ~(URE_INNER_VLAN | URE_OUTER_VLAN); 733 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 734 reg |= (URE_INNER_VLAN | URE_OUTER_VLAN); 735 ure_write_2(sc, URE_PLA_RCR1, URE_MCU_TYPE_PLA, reg); 736 } else { 737 reg = ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA); 738 reg &= ~URE_CPCR_RX_VLAN; 739 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 740 reg |= URE_CPCR_RX_VLAN; 741 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, reg); 742 } 743 } 744 745 void 746 ure_reset(struct ure_softc *sc) 747 { 748 int i; 749 750 if (sc->ure_flags & URE_FLAG_8156) { 751 URE_CLRBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_TE); 752 URE_CLRBIT_2(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, 753 BMU_RESET_EP_IN); 754 URE_SETBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 755 URE_CDC_ECM_EN); 756 URE_CLRBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE); 757 URE_SETBIT_2(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, 758 BMU_RESET_EP_IN); 759 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 760 URE_CDC_ECM_EN); 761 } else { 762 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 763 764 for (i = 0; i < URE_TIMEOUT; i++) { 765 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) & 766 URE_CR_RST)) 767 break; 768 DELAY(100); 769 } 770 if (i == URE_TIMEOUT) 771 printf("%s: reset never completed\n", 772 sc->ure_dev.dv_xname); 773 } 774 } 775 776 void 777 ure_watchdog(struct ifnet *ifp) 778 { 779 struct ure_softc *sc = ifp->if_softc; 780 struct ure_chain *c; 781 usbd_status err; 782 int i, s; 783 784 ifp->if_timer = 0; 785 786 if (usbd_is_dying(sc->ure_udev)) 787 return; 788 789 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) 790 return; 791 792 sc = ifp->if_softc; 793 s = splnet(); 794 795 ifp->if_oerrors++; 796 DPRINTF(("%s: watchdog timeout\n", sc->ure_dev.dv_xname)); 797 798 for (i = 0; i < URE_TX_LIST_CNT; i++) { 799 c = &sc->ure_cdata.ure_tx_chain[i]; 800 if (c->uc_cnt > 0) { 801 usbd_get_xfer_status(c->uc_xfer, NULL, NULL, NULL, 802 &err); 803 ure_txeof(c->uc_xfer, c, err); 804 } 805 } 806 807 if (ifq_is_oactive(&ifp->if_snd)) 808 ifq_restart(&ifp->if_snd); 809 splx(s); 810 } 811 812 void 813 ure_init(void *xsc) 814 { 815 struct ure_softc *sc = xsc; 816 struct ure_chain *c; 817 struct ifnet *ifp = &sc->ure_ac.ac_if; 818 usbd_status err; 819 int s, i; 820 821 s = splnet(); 822 823 /* Cancel pending I/O. */ 824 ure_stop(sc); 825 826 if (sc->ure_flags & URE_FLAG_8152) 827 ure_rtl8152_nic_reset(sc); 828 else 829 ure_rtl8153_nic_reset(sc); 830 831 if (ure_xfer_list_init(sc, sc->ure_cdata.ure_rx_chain, 832 sc->ure_rxbufsz, URE_RX_LIST_CNT) == ENOBUFS) { 833 printf("%s: rx list init failed\n", sc->ure_dev.dv_xname); 834 splx(s); 835 return; 836 } 837 838 if (ure_xfer_list_init(sc, sc->ure_cdata.ure_tx_chain, 839 sc->ure_txbufsz, URE_TX_LIST_CNT) == ENOBUFS) { 840 printf("%s: tx list init failed\n", sc->ure_dev.dv_xname); 841 splx(s); 842 return; 843 } 844 845 /* Initialize the SLIST we are using for the multiple tx buffers */ 846 SLIST_INIT(&sc->ure_cdata.ure_tx_free); 847 for (i = 0; i < URE_TX_LIST_CNT; i++) 848 SLIST_INSERT_HEAD(&sc->ure_cdata.ure_tx_free, 849 &sc->ure_cdata.ure_tx_chain[i], uc_list); 850 851 /* Setup MAC address, and enable TX/RX. */ 852 ure_ifmedia_init(ifp); 853 854 /* Load the multicast filter. */ 855 ure_iff(sc); 856 857 /* Open RX and TX pipes. */ 858 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_RX], 859 USBD_EXCLUSIVE_USE, &sc->ure_ep[URE_ENDPT_RX]); 860 if (err) { 861 printf("%s: open rx pipe failed: %s\n", 862 sc->ure_dev.dv_xname, usbd_errstr(err)); 863 splx(s); 864 return; 865 } 866 867 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_TX], 868 USBD_EXCLUSIVE_USE, &sc->ure_ep[URE_ENDPT_TX]); 869 if (err) { 870 printf("%s: open tx pipe failed: %s\n", 871 sc->ure_dev.dv_xname, usbd_errstr(err)); 872 splx(s); 873 return; 874 } 875 876 /* Start up the receive pipe. */ 877 for (i = 0; i < URE_RX_LIST_CNT; i++) { 878 c = &sc->ure_cdata.ure_rx_chain[i]; 879 usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_RX], 880 c, c->uc_buf, c->uc_bufmax, 881 USBD_SHORT_XFER_OK | USBD_NO_COPY, 882 USBD_NO_TIMEOUT, ure_rxeof); 883 usbd_transfer(c->uc_xfer); 884 } 885 886 ure_ifmedia_upd(ifp); 887 888 /* Indicate we are up and running. */ 889 sc->ure_flags &= ~URE_FLAG_LINK; 890 ifp->if_flags |= IFF_RUNNING; 891 ifq_clr_oactive(&ifp->if_snd); 892 893 timeout_add_sec(&sc->ure_stat_ch, 1); 894 895 splx(s); 896 } 897 898 void 899 ure_start(struct ifnet *ifp) 900 { 901 struct ure_softc *sc = ifp->if_softc; 902 struct ure_cdata *cd = &sc->ure_cdata; 903 struct ure_chain *c; 904 struct mbuf *m = NULL; 905 uint32_t new_buflen; 906 int s, mlen; 907 908 if (!(sc->ure_flags & URE_FLAG_LINK) || 909 (ifp->if_flags & (IFF_RUNNING|IFF_UP)) != 910 (IFF_RUNNING|IFF_UP)) { 911 return; 912 } 913 914 s = splnet(); 915 916 c = SLIST_FIRST(&cd->ure_tx_free); 917 while (c != NULL) { 918 m = ifq_deq_begin(&ifp->if_snd); 919 if (m == NULL) 920 break; 921 922 mlen = m->m_pkthdr.len; 923 924 /* Discard packet larger than buffer. */ 925 if (mlen + sizeof(struct ure_txpkt) >= c->uc_bufmax) { 926 ifq_deq_commit(&ifp->if_snd, m); 927 m_freem(m); 928 ifp->if_oerrors++; 929 continue; 930 } 931 932 /* 933 * If packet larger than remaining space, send buffer and 934 * continue. 935 */ 936 new_buflen = roundup(c->uc_buflen, URE_TX_BUF_ALIGN); 937 if (new_buflen + sizeof(struct ure_txpkt) + mlen >= 938 c->uc_bufmax) { 939 ifq_deq_rollback(&ifp->if_snd, m); 940 SLIST_REMOVE_HEAD(&cd->ure_tx_free, uc_list); 941 if (ure_encap_xfer(ifp, sc, c)) { 942 SLIST_INSERT_HEAD(&cd->ure_tx_free, c, 943 uc_list); 944 break; 945 } 946 c = SLIST_FIRST(&cd->ure_tx_free); 947 continue; 948 } 949 950 /* Append packet to current buffer. */ 951 mlen = ure_encap_txpkt(m, c->uc_buf + new_buflen, 952 c->uc_bufmax - new_buflen); 953 if (mlen <= 0) { 954 ifq_deq_rollback(&ifp->if_snd, m); 955 break; 956 } 957 958 ifq_deq_commit(&ifp->if_snd, m); 959 c->uc_cnt += 1; 960 c->uc_buflen = new_buflen + mlen; 961 962 #if NBPFILTER > 0 963 if (ifp->if_bpf) 964 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 965 #endif 966 967 m_freem(m); 968 } 969 970 if (c != NULL) { 971 /* Send current buffer unless empty */ 972 if (c->uc_buflen > 0 && c->uc_cnt > 0) { 973 SLIST_REMOVE_HEAD(&cd->ure_tx_free, uc_list); 974 if (ure_encap_xfer(ifp, sc, c)) { 975 SLIST_INSERT_HEAD(&cd->ure_tx_free, c, 976 uc_list); 977 } 978 c = SLIST_FIRST(&cd->ure_tx_free); 979 } 980 } 981 982 ifp->if_timer = 5; 983 if (c == NULL) 984 ifq_set_oactive(&ifp->if_snd); 985 splx(s); 986 } 987 988 void 989 ure_tick(void *xsc) 990 { 991 struct ure_softc *sc = xsc; 992 993 if (sc == NULL) 994 return; 995 996 if (usbd_is_dying(sc->ure_udev)) 997 return; 998 999 usb_add_task(sc->ure_udev, &sc->ure_tick_task); 1000 } 1001 1002 void 1003 ure_stop(struct ure_softc *sc) 1004 { 1005 struct ure_cdata *cd; 1006 struct ifnet *ifp; 1007 usbd_status err; 1008 1009 ure_reset(sc); 1010 1011 ifp = &sc->ure_ac.ac_if; 1012 ifp->if_timer = 0; 1013 ifp->if_flags &= ~IFF_RUNNING; 1014 ifq_clr_oactive(&ifp->if_snd); 1015 1016 timeout_del(&sc->ure_stat_ch); 1017 sc->ure_flags &= ~URE_FLAG_LINK; 1018 1019 if (sc->ure_ep[URE_ENDPT_RX] != NULL) { 1020 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_RX]); 1021 if (err) { 1022 printf("%s: close rx pipe failed: %s\n", 1023 sc->ure_dev.dv_xname, usbd_errstr(err)); 1024 } 1025 sc->ure_ep[URE_ENDPT_RX] = NULL; 1026 } 1027 1028 if (sc->ure_ep[URE_ENDPT_TX] != NULL) { 1029 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_TX]); 1030 if (err) { 1031 printf("%s: close tx pipe failed: %s\n", 1032 sc->ure_dev.dv_xname, usbd_errstr(err)); 1033 } 1034 sc->ure_ep[URE_ENDPT_TX] = NULL; 1035 } 1036 1037 cd = &sc->ure_cdata; 1038 ure_xfer_list_free(sc, cd->ure_rx_chain, URE_RX_LIST_CNT); 1039 ure_xfer_list_free(sc, cd->ure_tx_chain, URE_TX_LIST_CNT); 1040 } 1041 1042 int 1043 ure_xfer_list_init(struct ure_softc *sc, struct ure_chain *ch, 1044 uint32_t bufsize, int listlen) 1045 { 1046 struct ure_chain *c; 1047 int i; 1048 1049 for (i = 0; i < listlen; i++) { 1050 c = &ch[i]; 1051 c->uc_sc = sc; 1052 c->uc_idx = i; 1053 c->uc_buflen = 0; 1054 c->uc_bufmax = bufsize; 1055 c->uc_cnt = 0; 1056 if (c->uc_xfer == NULL) { 1057 c->uc_xfer = usbd_alloc_xfer(sc->ure_udev); 1058 if (c->uc_xfer == NULL) 1059 return (ENOBUFS); 1060 c->uc_buf = usbd_alloc_buffer(c->uc_xfer, c->uc_bufmax); 1061 if (c->uc_buf == NULL) { 1062 usbd_free_xfer(c->uc_xfer); 1063 c->uc_xfer = NULL; 1064 return (ENOBUFS); 1065 } 1066 } 1067 } 1068 1069 return (0); 1070 } 1071 1072 void 1073 ure_xfer_list_free(struct ure_softc *sc, struct ure_chain *ch, int listlen) 1074 { 1075 int i; 1076 1077 for (i = 0; i < listlen; i++) { 1078 if (ch[i].uc_buf != NULL) { 1079 ch[i].uc_buf = NULL; 1080 } 1081 ch[i].uc_cnt = 0; 1082 if (ch[i].uc_xfer != NULL) { 1083 usbd_free_xfer(ch[i].uc_xfer); 1084 ch[i].uc_xfer = NULL; 1085 } 1086 } 1087 } 1088 1089 void 1090 ure_rtl8152_init(struct ure_softc *sc) 1091 { 1092 uint32_t pwrctrl; 1093 1094 /* Disable ALDPS. */ 1095 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 1096 URE_DIS_SDSAVE); 1097 usbd_delay_ms(sc->ure_udev, 20); 1098 1099 if (sc->ure_chip & URE_CHIP_VER_4C00) 1100 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 1101 URE_LED_MODE_MASK); 1102 1103 URE_CLRBIT_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, URE_POWER_CUT); 1104 URE_CLRBIT_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 1105 URE_RESUME_INDICATE); 1106 1107 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 1108 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 1109 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 1110 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 1111 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 1112 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 1113 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 1114 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 1115 URE_SPDWN_LINKCHG_MSK); 1116 1117 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET); 1118 1119 /* Enable Rx aggregation. */ 1120 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1121 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1122 } 1123 1124 void 1125 ure_rtl8153_init(struct ure_softc *sc) 1126 { 1127 uint16_t reg; 1128 uint8_t u1u2[8]; 1129 int i; 1130 1131 memset(u1u2, 0x00, sizeof(u1u2)); 1132 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, u1u2, 1133 sizeof(u1u2)); 1134 1135 for (i = 0; i < 500; i++) { 1136 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 1137 URE_AUTOLOAD_DONE) 1138 break; 1139 usbd_delay_ms(sc->ure_udev, 20); 1140 } 1141 if (i == 500) 1142 printf("%s: timeout waiting for chip autoload\n", 1143 sc->ure_dev.dv_xname); 1144 1145 ure_rtl8153_phy_status(sc, 0); 1146 1147 if (sc->ure_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 | 1148 URE_CHIP_VER_5C20)) { 1149 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG, 1150 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 1151 } 1152 1153 ure_rtl8153_phy_status(sc, URE_PHY_STAT_LAN_ON); 1154 1155 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1156 1157 if (sc->ure_chip & URE_CHIP_VER_5C10) { 1158 reg = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 1159 reg &= ~URE_PWD_DN_SCALE_MASK; 1160 reg |= URE_PWD_DN_SCALE(96); 1161 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, reg); 1162 1163 URE_SETBIT_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 1164 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 1165 } else if (sc->ure_chip & URE_CHIP_VER_5C20) { 1166 URE_CLRBIT_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 1167 URE_ECM_ALDPS); 1168 } 1169 if (sc->ure_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) { 1170 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB)) 1171 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, 1172 URE_DYNAMIC_BURST); 1173 else 1174 URE_CLRBIT_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, 1175 URE_DYNAMIC_BURST); 1176 } 1177 1178 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, URE_EP4_FULL_FC); 1179 1180 URE_CLRBIT_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, URE_TIMER11_EN); 1181 1182 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 1183 URE_LED_MODE_MASK); 1184 1185 if ((sc->ure_chip & URE_CHIP_VER_5C10) && 1186 sc->ure_udev->speed != USB_SPEED_SUPER) 1187 reg = URE_LPM_TIMER_500MS; 1188 else 1189 reg = URE_LPM_TIMER_500US; 1190 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 1191 URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM | reg); 1192 1193 reg = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 1194 reg &= ~URE_SEN_VAL_MASK; 1195 reg |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 1196 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, reg); 1197 1198 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 1199 1200 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 1201 URE_PWR_EN | URE_PHASE2_EN); 1202 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS); 1203 1204 memset(u1u2, 0xff, sizeof(u1u2)); 1205 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, u1u2, 1206 sizeof(u1u2)); 1207 1208 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0); 1209 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 0); 1210 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 0); 1211 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0); 1212 1213 /* Enable Rx aggregation. */ 1214 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1215 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1216 1217 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET); 1218 } 1219 1220 void 1221 ure_rtl8153b_init(struct ure_softc *sc) 1222 { 1223 uint16_t reg; 1224 int i; 1225 1226 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1227 URE_CLRBIT_1(sc, URE_USB_ECM_OP, URE_MCU_TYPE_USB, 1228 URE_EN_ALL_SPEED); 1229 ure_write_2(sc, URE_USB_SPEED_OPTION, URE_MCU_TYPE_USB, 0); 1230 URE_SETBIT_2(sc, URE_USB_ECM_OPTION, URE_MCU_TYPE_USB, 1231 URE_BYPASS_MAC_RESET); 1232 1233 if (sc->ure_flags & URE_FLAG_8156B) 1234 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 1235 URE_RX_DETECT8); 1236 } 1237 1238 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, LPM_U1U2_EN); 1239 1240 if (sc->ure_flags & URE_FLAG_8156B) 1241 ure_wait_for_flash(sc); 1242 1243 for (i = 0; i < 500; i++) { 1244 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 1245 URE_AUTOLOAD_DONE) 1246 break; 1247 usbd_delay_ms(sc->ure_udev, 20); 1248 } 1249 if (i == 500) 1250 printf("%s: timeout waiting for chip autoload\n", 1251 sc->ure_dev.dv_xname); 1252 1253 ure_rtl8153_phy_status(sc, 0); 1254 ure_rtl8153_phy_status(sc, URE_PHY_STAT_LAN_ON); 1255 1256 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1257 1258 /* MSC timer, 32760 ms. */ 1259 ure_write_2(sc, URE_USB_MSC_TIMER, URE_MCU_TYPE_USB, 4095); 1260 1261 if (!(sc->ure_flags & URE_FLAG_8153B)) { 1262 /* U1/U2/L1 idle timer, 500 us. */ 1263 ure_write_2(sc, URE_USB_U1U2_TIMER, URE_MCU_TYPE_USB, 500); 1264 } 1265 1266 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN); 1267 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS); 1268 1269 URE_CLRBIT_1(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 1270 URE_UPS_EN | URE_USP_PREWAKE); 1271 URE_CLRBIT_1(sc, URE_USB_MISC_2, URE_MCU_TYPE_USB, 1272 URE_UPS_FORCE_PWR_DOWN); 1273 1274 URE_CLRBIT_1(sc, URE_PLA_INDICATE_FALG, URE_MCU_TYPE_PLA, 1275 URE_UPCOMING_RUNTIME_D3); 1276 URE_CLRBIT_1(sc, URE_PLA_SUSPEND_FLAG, URE_MCU_TYPE_PLA, 1277 URE_LINK_CHG_EVENT); 1278 URE_CLRBIT_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, 1279 URE_LINK_CHANGE_FLAG); 1280 1281 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 1282 URE_CLRBIT_2(sc, URE_PLA_CONFIG34, URE_MCU_TYPE_PLA, 1283 URE_LINK_OFF_WAKE_EN); 1284 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 1285 1286 if (sc->ure_flags & URE_FLAG_8153B) { 1287 reg = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA); 1288 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & 1289 URE_PHYSTATUS_LINK) 1290 reg |= URE_CUR_LINK_OK; 1291 else 1292 reg &= ~URE_CUR_LINK_OK; 1293 ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, 1294 reg | URE_POLL_LINK_CHG); 1295 } 1296 1297 if (sc->ure_udev->speed == USB_SPEED_SUPER) { 1298 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, 1299 LPM_U1U2_EN); 1300 } 1301 1302 if (sc->ure_flags & URE_FLAG_8156B) { 1303 URE_CLRBIT_2(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_SLOT_EN); 1304 URE_SETBIT_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 1305 URE_FLOW_CTRL_EN); 1306 1307 /* Enable fc timer and set timer to 600 ms. */ 1308 ure_write_2(sc, URE_USB_FC_TIMER, URE_MCU_TYPE_USB, 1309 URE_CTRL_TIMER_EN | 75); 1310 1311 reg = ure_read_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB); 1312 if (!(ure_read_2(sc, URE_PLA_POL_GPIO_CTRL, URE_MCU_TYPE_PLA) & 1313 URE_DACK_DET_EN)) 1314 reg |= URE_FLOW_CTRL_PATCH_2; 1315 reg &= ~URE_AUTO_SPEEDUP; 1316 ure_write_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB, reg); 1317 1318 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, 1319 URE_FC_PATCH_TASK); 1320 } 1321 1322 /* MAC clock speed down. */ 1323 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1324 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0x0403); 1325 reg = ure_read_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA); 1326 reg &= ~URE_EEE_SPDWN_RATIO_MASK; 1327 reg |= URE_MAC_CLK_SPDWN_EN | 0x0003; 1328 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, reg); 1329 1330 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 1331 URE_PLA_MCU_SPDWN_EN); 1332 1333 reg = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA); 1334 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & 1335 URE_PHYSTATUS_LINK) 1336 reg |= URE_CUR_LINK_OK; 1337 else 1338 reg &= ~URE_CUR_LINK_OK; 1339 ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, 1340 reg | URE_POLL_LINK_CHG); 1341 } else 1342 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 1343 URE_MAC_CLK_SPDWN_EN); 1344 1345 /* Enable Rx aggregation. */ 1346 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1347 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1348 1349 if (sc->ure_flags & URE_FLAG_8156) 1350 URE_SETBIT_1(sc, URE_USB_BMU_CONFIG, URE_MCU_TYPE_USB, 1351 URE_ACT_ODMA); 1352 1353 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET); 1354 } 1355 1356 void 1357 ure_rtl8152_nic_reset(struct ure_softc *sc) 1358 { 1359 uint32_t rx_fifo1, rx_fifo2; 1360 int i; 1361 1362 /* Disable ALDPS. */ 1363 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 1364 URE_DIS_SDSAVE); 1365 usbd_delay_ms(sc->ure_udev, 20); 1366 1367 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL); 1368 1369 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 1370 ure_disable_teredo(sc); 1371 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 1372 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 1373 1374 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB); 1375 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN); 1376 for (i = 0; i < URE_TIMEOUT; i++) { 1377 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1378 URE_LINK_LIST_READY) 1379 break; 1380 usbd_delay_ms(sc->ure_udev, 1); 1381 } 1382 if (i == URE_TIMEOUT) 1383 printf("%s: timeout waiting for OOB control\n", 1384 sc->ure_dev.dv_xname); 1385 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL); 1386 for (i = 0; i < URE_TIMEOUT; i++) { 1387 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1388 URE_LINK_LIST_READY) 1389 break; 1390 usbd_delay_ms(sc->ure_udev, 1); 1391 } 1392 if (i == URE_TIMEOUT) 1393 printf("%s: timeout waiting for OOB control\n", 1394 sc->ure_dev.dv_xname); 1395 1396 ure_reset(sc); 1397 1398 /* Configure Rx FIFO threshold. */ 1399 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 1400 URE_RXFIFO_THR1_NORMAL); 1401 if (sc->ure_udev->speed == USB_SPEED_FULL) { 1402 rx_fifo1 = URE_RXFIFO_THR2_FULL; 1403 rx_fifo2 = URE_RXFIFO_THR3_FULL; 1404 } else { 1405 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 1406 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 1407 } 1408 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 1409 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 1410 1411 /* Configure Tx FIFO threshold. */ 1412 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 1413 URE_TXFIFO_THR_NORMAL); 1414 1415 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 1416 URE_TX_AGG_MAX_THRESHOLD); 1417 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 1418 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 1419 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 1420 1421 ure_rxvlan(sc); 1422 ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA, 1423 ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1424 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO); 1425 1426 /* Enable ALDPS. */ 1427 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, 1428 URE_ENPWRSAVE | URE_ENPDNPS | URE_LINKENA | URE_DIS_SDSAVE); 1429 } 1430 1431 void 1432 ure_rtl8153_nic_reset(struct ure_softc *sc) 1433 { 1434 struct ifnet *ifp = &sc->ure_ac.ac_if; 1435 uint32_t reg = 0; 1436 uint8_t u1u2[8] = { 0 }; 1437 int i; 1438 1439 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) { 1440 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, 1441 LPM_U1U2_EN); 1442 } else { 1443 memset(u1u2, 0x00, sizeof(u1u2)); 1444 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, 1445 u1u2, sizeof(u1u2)); 1446 } 1447 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1448 1449 /* Disable ALDPS. */ 1450 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1451 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 1452 for (i = 0; i < 20; i++) { 1453 usbd_delay_ms(sc->ure_udev, 1); 1454 if (ure_read_2(sc, 0xe000, URE_MCU_TYPE_PLA) & 0x0100) 1455 break; 1456 } 1457 1458 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 1459 ure_disable_teredo(sc); 1460 1461 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL); 1462 1463 ure_reset(sc); 1464 ure_reset_bmu(sc); 1465 1466 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB); 1467 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN); 1468 1469 if (!(sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B))) { 1470 for (i = 0; i < URE_TIMEOUT; i++) { 1471 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1472 URE_LINK_LIST_READY) 1473 break; 1474 usbd_delay_ms(sc->ure_udev, 1); 1475 } 1476 if (i == URE_TIMEOUT) 1477 printf("%s: timeout waiting for OOB control\n", 1478 sc->ure_dev.dv_xname); 1479 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 1480 URE_RE_INIT_LL); 1481 for (i = 0; i < URE_TIMEOUT; i++) { 1482 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1483 URE_LINK_LIST_READY) 1484 break; 1485 usbd_delay_ms(sc->ure_udev, 1); 1486 } 1487 if (i == URE_TIMEOUT) 1488 printf("%s: timeout waiting for OOB control\n", 1489 sc->ure_dev.dv_xname); 1490 } 1491 1492 ure_rxvlan(sc); 1493 1494 ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA, 1495 URE_FRAMELEN(ifp->if_mtu)); 1496 ure_write_1(sc, URE_PLA_MTPS, URE_MCU_TYPE_PLA, MTPS_JUMBO); 1497 1498 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1499 ure_write_2(sc, URE_PLA_RX_FIFO_FULL, URE_MCU_TYPE_PLA, 1500 (sc->ure_flags & URE_FLAG_8156) ? 1024 : 512); 1501 ure_write_2(sc, URE_PLA_RX_FIFO_EMPTY, URE_MCU_TYPE_PLA, 1502 (sc->ure_flags & URE_FLAG_8156) ? 2048 : 1024); 1503 1504 /* Tx share fifo free credit full threshold. */ 1505 ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 8); 1506 ure_write_2(sc, URE_PLA_TXFIFO_FULL, URE_MCU_TYPE_PLA, 128); 1507 1508 if (sc->ure_flags & URE_FLAG_8156) 1509 URE_SETBIT_2(sc, URE_USB_BMU_CONFIG, URE_MCU_TYPE_USB, 1510 URE_ACT_ODMA); 1511 1512 /* FIFO settings */ 1513 reg = ure_read_2(sc, URE_PLA_RXFIFO_FULL, URE_MCU_TYPE_PLA); 1514 reg &= ~URE_RXFIFO_FULL_MASK; 1515 ure_write_2(sc, URE_PLA_RXFIFO_FULL, URE_MCU_TYPE_PLA, 1516 reg | 0x0008); 1517 1518 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 1519 URE_PLA_MCU_SPDWN_EN); 1520 1521 URE_CLRBIT_2(sc, URE_USB_SPEED_OPTION, URE_MCU_TYPE_USB, 1522 URE_RG_PWRDN_EN | URE_ALL_SPEED_OFF); 1523 1524 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, 1525 0x00600400); 1526 } 1527 1528 if (!(sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B))) { 1529 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 1530 URE_TCR0_AUTO_FIFO); 1531 ure_reset(sc); 1532 1533 /* Configure Rx FIFO threshold. */ 1534 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 1535 URE_RXFIFO_THR1_NORMAL); 1536 ure_write_2(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, 1537 URE_RXFIFO_THR2_NORMAL); 1538 ure_write_2(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, 1539 URE_RXFIFO_THR3_NORMAL); 1540 1541 /* Configure Tx FIFO threshold. */ 1542 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 1543 URE_TXFIFO_THR_NORMAL2); 1544 1545 if (sc->ure_flags & URE_FLAG_8153B) { 1546 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, 1547 URE_RX_THR_B); 1548 1549 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, 1550 URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN); 1551 } else { 1552 URE_SETBIT_1(sc, URE_PLA_CONFIG6, URE_MCU_TYPE_PLA, 1553 URE_LANWAKE_CLR_EN); 1554 URE_CLRBIT_1(sc, URE_PLA_LWAKE_CTRL_REG, 1555 URE_MCU_TYPE_PLA, URE_LANWAKE_PIN); 1556 URE_CLRBIT_2(sc, URE_USB_SSPHYLINK1, URE_MCU_TYPE_USB, 1557 URE_DELAY_PHY_PWR_CHG); 1558 } 1559 } 1560 1561 /* Enable ALDPS. */ 1562 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1563 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | URE_EN_ALDPS); 1564 1565 if ((sc->ure_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) || 1566 (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B))) 1567 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 1568 URE_U2P3_ENABLE); 1569 1570 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) { 1571 if (sc->ure_udev->speed == USB_SPEED_SUPER) 1572 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, 1573 LPM_U1U2_EN); 1574 } else { 1575 memset(u1u2, 0xff, sizeof(u1u2)); 1576 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, 1577 u1u2, sizeof(u1u2)); 1578 } 1579 } 1580 1581 uint16_t 1582 ure_rtl8153_phy_status(struct ure_softc *sc, int desired) 1583 { 1584 uint16_t reg; 1585 int i; 1586 1587 for (i = 0; i < 500; i++) { 1588 reg = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & 1589 URE_PHY_STAT_MASK; 1590 if (desired) { 1591 if (reg == desired) 1592 break; 1593 } else { 1594 if (reg == URE_PHY_STAT_LAN_ON || 1595 reg == URE_PHY_STAT_PWRDN || 1596 reg == URE_PHY_STAT_EXT_INIT) 1597 break; 1598 } 1599 usbd_delay_ms(sc->ure_udev, 20); 1600 } 1601 if (i == 500) 1602 printf("%s: timeout waiting for phy to stabilize\n", 1603 sc->ure_dev.dv_xname); 1604 1605 return reg; 1606 } 1607 1608 void 1609 ure_wait_for_flash(struct ure_softc *sc) 1610 { 1611 int i; 1612 1613 if ((ure_read_2(sc, URE_PLA_GPHY_CTRL, URE_MCU_TYPE_PLA) & 1614 URE_GPHY_FLASH) && 1615 !(ure_read_2(sc, URE_USB_GPHY_CTRL, URE_MCU_TYPE_USB) & 1616 URE_BYPASS_FLASH)) { 1617 for (i = 0; i < 100; i++) { 1618 if (ure_read_2(sc, URE_USB_GPHY_CTRL, 1619 URE_MCU_TYPE_USB) & URE_GPHY_PATCH_DONE) 1620 break; 1621 DELAY(1000); 1622 } 1623 if (i == 100) 1624 printf("%s: timeout waiting for loading flash\n", 1625 sc->ure_dev.dv_xname); 1626 } 1627 } 1628 1629 void 1630 ure_reset_bmu(struct ure_softc *sc) 1631 { 1632 uint8_t reg; 1633 1634 reg = ure_read_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB); 1635 reg &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); 1636 ure_write_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, reg); 1637 reg |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; 1638 ure_write_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, reg); 1639 } 1640 1641 void 1642 ure_disable_teredo(struct ure_softc *sc) 1643 { 1644 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) 1645 ure_write_1(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 0xff); 1646 else { 1647 URE_CLRBIT_2(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 1648 URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | 1649 URE_OOB_TEREDO_EN); 1650 } 1651 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, URE_WDT6_SET_MODE); 1652 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 1653 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 1654 } 1655 1656 int 1657 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1658 { 1659 struct ure_softc *sc = ifp->if_softc; 1660 struct ifreq *ifr = (struct ifreq *)data; 1661 int s, error = 0; 1662 1663 s = splnet(); 1664 1665 switch (cmd) { 1666 case SIOCSIFADDR: 1667 ifp->if_flags |= IFF_UP; 1668 if (!(ifp->if_flags & IFF_RUNNING)) 1669 ure_init(sc); 1670 break; 1671 1672 case SIOCSIFFLAGS: 1673 if (ifp->if_flags & IFF_UP) { 1674 if (ifp->if_flags & IFF_RUNNING) 1675 error = ENETRESET; 1676 else 1677 ure_init(sc); 1678 } else { 1679 if (ifp->if_flags & IFF_RUNNING) 1680 ure_stop(sc); 1681 } 1682 break; 1683 1684 case SIOCGIFMEDIA: 1685 case SIOCSIFMEDIA: 1686 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) 1687 error = ifmedia_ioctl(ifp, ifr, &sc->ure_ifmedia, cmd); 1688 else 1689 error = ifmedia_ioctl(ifp, ifr, &sc->ure_mii.mii_media, 1690 cmd); 1691 break; 1692 1693 default: 1694 error = ether_ioctl(ifp, &sc->ure_ac, cmd, data); 1695 } 1696 1697 if (error == ENETRESET) { 1698 if (ifp->if_flags & IFF_RUNNING) 1699 ure_iff(sc); 1700 error = 0; 1701 } 1702 1703 splx(s); 1704 1705 return (error); 1706 } 1707 1708 int 1709 ure_match(struct device *parent, void *match, void *aux) 1710 { 1711 struct usb_attach_arg *uaa = aux; 1712 1713 if (uaa->iface == NULL || uaa->configno != 1) 1714 return (UMATCH_NONE); 1715 1716 return (usb_lookup(ure_devs, uaa->vendor, uaa->product) != NULL ? 1717 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 1718 } 1719 1720 void 1721 ure_attach(struct device *parent, struct device *self, void *aux) 1722 { 1723 struct ure_softc *sc = (struct ure_softc *)self; 1724 struct usb_attach_arg *uaa = aux; 1725 usb_interface_descriptor_t *id; 1726 usb_endpoint_descriptor_t *ed; 1727 u_char eaddr[8]; /* 4byte padded */ 1728 struct ifnet *ifp; 1729 int i, mii_flags = 0, s; 1730 uint16_t ver; 1731 1732 sc->ure_udev = uaa->device; 1733 sc->ure_iface = uaa->iface; 1734 1735 usb_init_task(&sc->ure_tick_task, ure_tick_task, sc, 1736 USB_TASK_TYPE_GENERIC); 1737 1738 id = usbd_get_interface_descriptor(sc->ure_iface); 1739 1740 for (i = 0; i < id->bNumEndpoints; i++) { 1741 ed = usbd_interface2endpoint_descriptor(sc->ure_iface, i); 1742 if (!ed) { 1743 printf("%s: couldn't get ep %d\n", 1744 sc->ure_dev.dv_xname, i); 1745 return; 1746 } 1747 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 1748 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 1749 sc->ure_ed[URE_ENDPT_RX] = ed->bEndpointAddress; 1750 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 1751 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 1752 sc->ure_ed[URE_ENDPT_TX] = ed->bEndpointAddress; 1753 } 1754 } 1755 1756 sc->ure_txbufsz = URE_TX_BUFSZ; 1757 sc->ure_rxbufsz = URE_8153_RX_BUFSZ; 1758 1759 s = splnet(); 1760 1761 sc->ure_phyno = 0; 1762 printf("%s: ", sc->ure_dev.dv_xname); 1763 1764 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 1765 switch (ver) { 1766 case 0x4c00: 1767 sc->ure_flags = URE_FLAG_8152; 1768 sc->ure_rxbufsz = URE_8152_RX_BUFSZ; 1769 sc->ure_chip |= URE_CHIP_VER_4C00; 1770 printf("RTL8152 (0x4c00)"); 1771 break; 1772 case 0x4c10: 1773 sc->ure_flags = URE_FLAG_8152; 1774 sc->ure_rxbufsz = URE_8152_RX_BUFSZ; 1775 sc->ure_chip |= URE_CHIP_VER_4C10; 1776 printf("RTL8152 (0x4c10)"); 1777 break; 1778 case 0x5c00: 1779 sc->ure_chip |= URE_CHIP_VER_5C00; 1780 printf("RTL8153 (0x5c00)"); 1781 break; 1782 case 0x5c10: 1783 sc->ure_chip |= URE_CHIP_VER_5C10; 1784 printf("RTL8153 (0x5c10)"); 1785 break; 1786 case 0x5c20: 1787 sc->ure_chip |= URE_CHIP_VER_5C20; 1788 printf("RTL8153 (0x5c20)"); 1789 break; 1790 case 0x5c30: 1791 sc->ure_chip |= URE_CHIP_VER_5C30; 1792 printf("RTL8153 (0x5c30)"); 1793 break; 1794 case 0x6000: 1795 sc->ure_flags = URE_FLAG_8153B; 1796 printf("RTL8153B (0x6000)"); 1797 break; 1798 case 0x6010: 1799 sc->ure_flags = URE_FLAG_8153B; 1800 printf("RTL8153B (0x6010)"); 1801 break; 1802 case 0x7020: 1803 sc->ure_flags = URE_FLAG_8156; 1804 printf("RTL8156 (0x7020)"); 1805 break; 1806 case 0x7030: 1807 sc->ure_flags = URE_FLAG_8156; 1808 printf("RTL8156 (0x7030)"); 1809 break; 1810 case 0x7410: 1811 sc->ure_flags = URE_FLAG_8156B; 1812 printf("RTL8156B (0x7410)"); 1813 break; 1814 default: 1815 printf(", unknown ver %02x", ver); 1816 break; 1817 } 1818 1819 if (sc->ure_flags & URE_FLAG_8152) 1820 ure_rtl8152_init(sc); 1821 else if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 | 1822 URE_FLAG_8156B)) 1823 ure_rtl8153b_init(sc); 1824 else 1825 ure_rtl8153_init(sc); 1826 1827 if (sc->ure_chip & URE_CHIP_VER_4C00) 1828 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr, 1829 sizeof(eaddr)); 1830 else 1831 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr, 1832 sizeof(eaddr)); 1833 1834 printf(", address %s\n", ether_sprintf(eaddr)); 1835 1836 bcopy(eaddr, (char *)&sc->ure_ac.ac_enaddr, ETHER_ADDR_LEN); 1837 1838 ifp = &sc->ure_ac.ac_if; 1839 ifp->if_softc = sc; 1840 strlcpy(ifp->if_xname, sc->ure_dev.dv_xname, IFNAMSIZ); 1841 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1842 ifp->if_ioctl = ure_ioctl; 1843 ifp->if_start = ure_start; 1844 ifp->if_watchdog = ure_watchdog; 1845 1846 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 | 1847 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1848 1849 #if NVLAN > 0 1850 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1851 #endif 1852 1853 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1854 ifmedia_init(&sc->ure_ifmedia, IFM_IMASK, ure_ifmedia_upd, 1855 ure_ifmedia_sts); 1856 ure_add_media_types(sc); 1857 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1858 ifmedia_set(&sc->ure_ifmedia, IFM_ETHER | IFM_AUTO); 1859 sc->ure_ifmedia.ifm_media = sc->ure_ifmedia.ifm_cur->ifm_media; 1860 } else { 1861 rw_init(&sc->ure_mii_lock, "uremii"); 1862 1863 sc->ure_mii.mii_ifp = ifp; 1864 sc->ure_mii.mii_readreg = ure_miibus_readreg; 1865 sc->ure_mii.mii_writereg = ure_miibus_writereg; 1866 sc->ure_mii.mii_statchg = ure_miibus_statchg; 1867 sc->ure_mii.mii_flags = MIIF_AUTOTSLEEP; 1868 1869 ifmedia_init(&sc->ure_mii.mii_media, 0, ure_ifmedia_upd, 1870 ure_ifmedia_sts); 1871 if (!(sc->ure_flags & URE_FLAG_8152)) 1872 mii_flags |= MIIF_DOPAUSE; 1873 mii_attach(self, &sc->ure_mii, 0xffffffff, sc->ure_phyno, 1874 MII_OFFSET_ANY, mii_flags); 1875 if (LIST_FIRST(&sc->ure_mii.mii_phys) == NULL) { 1876 ifmedia_add(&sc->ure_mii.mii_media, 1877 IFM_ETHER | IFM_NONE, 0, NULL); 1878 ifmedia_set(&sc->ure_mii.mii_media, 1879 IFM_ETHER | IFM_NONE); 1880 } else 1881 ifmedia_set(&sc->ure_mii.mii_media, 1882 IFM_ETHER | IFM_AUTO); 1883 } 1884 1885 if_attach(ifp); 1886 ether_ifattach(ifp); 1887 1888 timeout_set(&sc->ure_stat_ch, ure_tick, sc); 1889 1890 splx(s); 1891 } 1892 1893 int 1894 ure_detach(struct device *self, int flags) 1895 { 1896 struct ure_softc *sc = (struct ure_softc *)self; 1897 struct ifnet *ifp = &sc->ure_ac.ac_if; 1898 int s; 1899 1900 if (timeout_initialized(&sc->ure_stat_ch)) 1901 timeout_del(&sc->ure_stat_ch); 1902 1903 if (sc->ure_ep[URE_ENDPT_TX] != NULL) 1904 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_TX]); 1905 if (sc->ure_ep[URE_ENDPT_RX] != NULL) 1906 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_RX]); 1907 1908 usb_rem_task(sc->ure_udev, &sc->ure_tick_task); 1909 1910 s = splusb(); 1911 1912 if (--sc->ure_refcnt >= 0) { 1913 usb_detach_wait(&sc->ure_dev); 1914 } 1915 1916 if (ifp->if_flags & IFF_RUNNING) 1917 ure_stop(sc); 1918 1919 mii_detach(&sc->ure_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1920 ifmedia_delete_instance(&sc->ure_mii.mii_media, IFM_INST_ANY); 1921 if (ifp->if_softc != NULL) { 1922 ether_ifdetach(ifp); 1923 if_detach(ifp); 1924 } 1925 1926 splx(s); 1927 1928 return 0; 1929 } 1930 1931 void 1932 ure_tick_task(void *xsc) 1933 { 1934 struct ure_softc *sc = xsc; 1935 struct mii_data *mii; 1936 int s; 1937 1938 if (sc == NULL) 1939 return; 1940 1941 if (usbd_is_dying(sc->ure_udev)) 1942 return; 1943 mii = &sc->ure_mii; 1944 1945 s = splnet(); 1946 if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) 1947 ure_link_state(sc); 1948 else { 1949 mii_tick(mii); 1950 if ((sc->ure_flags & URE_FLAG_LINK) == 0) 1951 ure_miibus_statchg(&sc->ure_dev); 1952 } 1953 timeout_add_sec(&sc->ure_stat_ch, 1); 1954 splx(s); 1955 } 1956 1957 void 1958 ure_lock_mii(struct ure_softc *sc) 1959 { 1960 sc->ure_refcnt++; 1961 rw_enter_write(&sc->ure_mii_lock); 1962 } 1963 1964 void 1965 ure_unlock_mii(struct ure_softc *sc) 1966 { 1967 rw_exit_write(&sc->ure_mii_lock); 1968 if (--sc->ure_refcnt < 0) 1969 usb_detach_wakeup(&sc->ure_dev); 1970 } 1971 1972 void 1973 ure_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1974 { 1975 struct ure_chain *c = (struct ure_chain *)priv; 1976 struct ure_softc *sc = c->uc_sc; 1977 struct ifnet *ifp = &sc->ure_ac.ac_if; 1978 u_char *buf = c->uc_buf; 1979 uint32_t cflags, rxvlan, total_len; 1980 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1981 struct mbuf *m; 1982 int pktlen = 0, s; 1983 struct ure_rxpkt rxhdr; 1984 1985 if (usbd_is_dying(sc->ure_udev)) 1986 return; 1987 1988 if (!(ifp->if_flags & IFF_RUNNING)) 1989 return; 1990 1991 if (status != USBD_NORMAL_COMPLETION) { 1992 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 1993 return; 1994 if (usbd_ratecheck(&sc->ure_rx_notice)) { 1995 printf("%s: usb errors on rx: %s\n", 1996 sc->ure_dev.dv_xname, usbd_errstr(status)); 1997 } 1998 if (status == USBD_STALLED) 1999 usbd_clear_endpoint_stall_async( 2000 sc->ure_ep[URE_ENDPT_RX]); 2001 goto done; 2002 } 2003 2004 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL); 2005 DPRINTFN(3, ("received %d bytes\n", total_len)); 2006 2007 do { 2008 if (total_len < sizeof(rxhdr)) { 2009 DPRINTF(("too few bytes left for a packet header\n")); 2010 ifp->if_ierrors++; 2011 goto done; 2012 } 2013 2014 buf += roundup(pktlen, URE_RX_BUF_ALIGN); 2015 2016 memcpy(&rxhdr, buf, sizeof(rxhdr)); 2017 total_len -= sizeof(rxhdr); 2018 2019 pktlen = letoh32(rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK; 2020 DPRINTFN(4, ("next packet is %d bytes\n", pktlen)); 2021 if (pktlen > total_len) { 2022 DPRINTF(("not enough bytes left for next packet\n")); 2023 ifp->if_ierrors++; 2024 goto done; 2025 } 2026 2027 total_len -= roundup(pktlen, URE_RX_BUF_ALIGN); 2028 buf += sizeof(rxhdr); 2029 2030 m = m_devget(buf, pktlen - ETHER_CRC_LEN, ETHER_ALIGN); 2031 if (m == NULL) { 2032 DPRINTF(("unable to allocate mbuf for next packet\n")); 2033 ifp->if_ierrors++; 2034 goto done; 2035 } 2036 2037 cflags = letoh32(rxhdr.ure_csum); 2038 rxvlan = letoh32(rxhdr.ure_vlan); 2039 2040 /* Check IP header checksum. */ 2041 if ((rxvlan & URE_RXPKT_IPV4) && 2042 !(cflags & URE_RXPKT_IPSUMBAD)) 2043 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 2044 2045 /* Check TCP/UDP checksum. */ 2046 if ((rxvlan & (URE_RXPKT_IPV4 | URE_RXPKT_IPV6)) && 2047 (((rxvlan & URE_RXPKT_TCP) && 2048 !(cflags & URE_RXPKT_TCPSUMBAD)) || 2049 ((rxvlan & URE_RXPKT_UDP) && 2050 !(cflags & URE_RXPKT_UDPSUMBAD)))) 2051 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | 2052 M_UDP_CSUM_IN_OK; 2053 #if NVLAN > 0 2054 if (rxvlan & URE_RXPKT_VLAN_TAG) { 2055 m->m_pkthdr.ether_vtag = 2056 swap16(rxvlan & URE_RXPKT_VLAN_DATA); 2057 m->m_flags |= M_VLANTAG; 2058 } 2059 #endif 2060 2061 ml_enqueue(&ml, m); 2062 } while (total_len > 0); 2063 2064 done: 2065 s = splnet(); 2066 if_input(ifp, &ml); 2067 splx(s); 2068 memset(c->uc_buf, 0, sc->ure_rxbufsz); 2069 2070 usbd_setup_xfer(xfer, sc->ure_ep[URE_ENDPT_RX], c, c->uc_buf, 2071 sc->ure_rxbufsz, USBD_SHORT_XFER_OK | USBD_NO_COPY, 2072 USBD_NO_TIMEOUT, ure_rxeof); 2073 usbd_transfer(xfer); 2074 } 2075 2076 2077 void 2078 ure_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2079 { 2080 struct ure_softc *sc; 2081 struct ure_chain *c; 2082 struct ifnet *ifp; 2083 int s; 2084 2085 c = priv; 2086 sc = c->uc_sc; 2087 ifp = &sc->ure_ac.ac_if; 2088 2089 if (usbd_is_dying(sc->ure_udev)) 2090 return; 2091 2092 if (status != USBD_NORMAL_COMPLETION) 2093 DPRINTF(("%s: %s uc_idx=%u : %s\n", sc->ure_dev.dv_xname, 2094 __func__, c->uc_idx, usbd_errstr(status))); 2095 2096 s = splnet(); 2097 2098 c->uc_cnt = 0; 2099 c->uc_buflen = 0; 2100 2101 SLIST_INSERT_HEAD(&sc->ure_cdata.ure_tx_free, c, uc_list); 2102 2103 if (status != USBD_NORMAL_COMPLETION) { 2104 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) { 2105 splx(s); 2106 return; 2107 } 2108 2109 ifp->if_oerrors++; 2110 printf("%s: usb error on tx: %s\n", sc->ure_dev.dv_xname, 2111 usbd_errstr(status)); 2112 2113 if (status == USBD_STALLED) 2114 usbd_clear_endpoint_stall_async( 2115 sc->ure_ep[URE_ENDPT_TX]); 2116 splx(s); 2117 return; 2118 } 2119 2120 ifp->if_timer = 0; 2121 if (ifq_is_oactive(&ifp->if_snd)) 2122 ifq_restart(&ifp->if_snd); 2123 splx(s); 2124 } 2125 2126 int 2127 ure_encap_txpkt(struct mbuf *m, char *buf, uint32_t maxlen) 2128 { 2129 struct ure_txpkt txhdr; 2130 uint32_t len = sizeof(txhdr), cflags = 0; 2131 2132 if (len + m->m_pkthdr.len > maxlen) 2133 return (-1); 2134 2135 if ((m->m_pkthdr.csum_flags & 2136 (M_IPV4_CSUM_OUT | M_TCP_CSUM_OUT | M_UDP_CSUM_OUT)) != 0) { 2137 cflags |= URE_TXPKT_IPV4; 2138 if (m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) 2139 cflags |= URE_TXPKT_TCP; 2140 if (m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) 2141 cflags |= URE_TXPKT_UDP; 2142 } 2143 2144 #if NVLAN > 0 2145 if (m->m_flags & M_VLANTAG) 2146 cflags |= URE_TXPKT_VLAN_TAG | swap16(m->m_pkthdr.ether_vtag); 2147 #endif 2148 2149 txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS | 2150 URE_TXPKT_TX_LS); 2151 txhdr.ure_vlan = htole32(cflags); 2152 memcpy(buf, &txhdr, len); 2153 2154 m_copydata(m, 0, m->m_pkthdr.len, buf + len); 2155 len += m->m_pkthdr.len; 2156 2157 return (len); 2158 } 2159 2160 int 2161 ure_encap_xfer(struct ifnet *ifp, struct ure_softc *sc, struct ure_chain *c) 2162 { 2163 usbd_status err; 2164 2165 usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_TX], c, c->uc_buf, 2166 c->uc_buflen, USBD_FORCE_SHORT_XFER | USBD_NO_COPY, 10000, 2167 ure_txeof); 2168 2169 err = usbd_transfer(c->uc_xfer); 2170 if (err != USBD_IN_PROGRESS) { 2171 c->uc_cnt = 0; 2172 c->uc_buflen = 0; 2173 ure_stop(sc); 2174 return (EIO); 2175 } 2176 2177 return (0); 2178 } 2179