1 /* $OpenBSD: if_ure.c,v 1.21 2020/10/14 23:47:55 jsg Exp $ */ 2 /*- 3 * Copyright (c) 2015, 2016, 2019 Kevin Lo <kevlo@openbsd.org> 4 * Copyright (c) 2020 Jonathon Fletcher <jonathon.fletcher@gmail.com> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "bpfilter.h" 30 #include "vlan.h" 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/sockio.h> 35 #include <sys/rwlock.h> 36 #include <sys/mbuf.h> 37 #include <sys/kernel.h> 38 #include <sys/socket.h> 39 #include <sys/device.h> 40 41 #include <machine/bus.h> 42 43 #include <net/if.h> 44 #include <net/if_media.h> 45 46 #if NBPFILTER > 0 47 #include <net/bpf.h> 48 #endif 49 50 #include <netinet/in.h> 51 #include <netinet/if_ether.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 56 #include <dev/usb/usb.h> 57 #include <dev/usb/usbdi.h> 58 #include <dev/usb/usbdi_util.h> 59 #include <dev/usb/usbdivar.h> 60 #include <dev/usb/usbdevs.h> 61 62 #include <dev/ic/rtl81x9reg.h> 63 #include <dev/usb/if_urereg.h> 64 65 #ifdef URE_DEBUG 66 #define DPRINTF(x) do { if (uredebug) printf x; } while (0) 67 #define DPRINTFN(n,x) do { if (uredebug >= (n)) printf x; } while (0) 68 int uredebug = 0; 69 #else 70 #define DPRINTF(x) 71 #define DPRINTFN(n,x) 72 #endif 73 74 const struct usb_devno ure_devs[] = { 75 { USB_VENDOR_ASUS, USB_PRODUCT_ASUS_RTL8156 }, 76 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8152B }, 77 { USB_VENDOR_BELKIN, USB_PRODUCT_BELKIN_RTL8153 }, 78 { USB_VENDOR_CISCOLINKSYS, USB_PRODUCT_CISCOLINKSYS_USB3GIGV1 }, 79 { USB_VENDOR_CLEVO, USB_PRODUCT_CLEVO_RTL8153B }, 80 { USB_VENDOR_CLUB3D, USB_PRODUCT_CLUB3D_RTL8153 }, 81 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8153_1 }, 82 { USB_VENDOR_DLINK, USB_PRODUCT_DLINK_RTL8153_2 }, 83 { USB_VENDOR_DYNABOOK, USB_PRODUCT_DYNABOOK_RTL8153B_1 }, 84 { USB_VENDOR_DYNABOOK, USB_PRODUCT_DYNABOOK_RTL8153B_2 }, 85 { USB_VENDOR_ELECOM, USB_PRODUCT_ELECOM_RTL8153B }, 86 { USB_VENDOR_ELECOM, USB_PRODUCT_ELECOM_RTL8156B }, 87 { USB_VENDOR_IOI, USB_PRODUCT_IOI_RTL8153 }, 88 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_DOCK_ETHERNET }, 89 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ONELINK }, 90 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ONELINKPLUS }, 91 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_ONELINKPRO }, 92 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_1 }, 93 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_2 }, 94 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_3 }, 95 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_4 }, 96 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_5 }, 97 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_6 }, 98 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_7 }, 99 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_8 }, 100 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153B_9 }, 101 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153_1 }, 102 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153_2 }, 103 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_RTL8153_3 }, 104 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TABLETDOCK }, 105 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TB3DOCK }, 106 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TB3DOCKGEN2 }, 107 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_TB3GFXDOCK }, 108 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_USBCDOCKGEN2 }, 109 { USB_VENDOR_LENOVO, USB_PRODUCT_LENOVO_WIGIGDOCK }, 110 { USB_VENDOR_LG, USB_PRODUCT_LG_RTL8153 }, 111 { USB_VENDOR_LG, USB_PRODUCT_LG_RTL8153B }, 112 { USB_VENDOR_LUXSHARE, USB_PRODUCT_LUXSHARE_RTL8153 }, 113 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_DOCKETH }, 114 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_DOCKETH2 }, 115 { USB_VENDOR_MICROSOFT, USB_PRODUCT_MICROSOFT_SURFETH }, 116 { USB_VENDOR_NVIDIA, USB_PRODUCT_NVIDIA_TEGRAETH }, 117 { USB_VENDOR_PIONEERDJ, USB_PRODUCT_PIONEERDJ_RTL8152B }, 118 { USB_VENDOR_PIONEERDJ, USB_PRODUCT_PIONEERDJ_RTL8153B }, 119 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 }, 120 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152B }, 121 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8153 }, 122 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8156 }, 123 { USB_VENDOR_SAMSUNG2, USB_PRODUCT_SAMSUNG2_RTL8153 }, 124 { USB_VENDOR_TOSHIBA, USB_PRODUCT_TOSHIBA_RTL8153B }, 125 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_EU300 }, 126 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_RTL8152B_1 }, 127 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_RTL8152B_2 }, 128 { USB_VENDOR_TPLINK, USB_PRODUCT_TPLINK_RTL8153 }, 129 { USB_VENDOR_TRENDNET, USB_PRODUCT_TRENDNET_RTL8156 }, 130 { USB_VENDOR_TTL, USB_PRODUCT_TTL_RTL8153 }, 131 { USB_VENDOR_TWINHEAD, USB_PRODUCT_TWINHEAD_RTL8153B }, 132 { USB_VENDOR_XIAOMI, USB_PRODUCT_XIAOMI_RTL8152B }, 133 }; 134 135 int ure_match(struct device *, void *, void *); 136 void ure_attach(struct device *, struct device *, void *); 137 int ure_detach(struct device *, int); 138 139 struct cfdriver ure_cd = { 140 NULL, "ure", DV_IFNET 141 }; 142 143 const struct cfattach ure_ca = { 144 sizeof(struct ure_softc), ure_match, ure_attach, ure_detach 145 }; 146 147 int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t, 148 void *, int); 149 int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *, 150 int); 151 int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *, 152 int); 153 uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t); 154 uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t); 155 uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t); 156 int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t); 157 int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t); 158 int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t); 159 uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t); 160 void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t); 161 162 void ure_init(void *); 163 void ure_stop(struct ure_softc *); 164 void ure_start(struct ifnet *); 165 void ure_reset(struct ure_softc *); 166 void ure_watchdog(struct ifnet *); 167 168 void ure_miibus_statchg(struct device *); 169 int ure_miibus_readreg(struct device *, int, int); 170 void ure_miibus_writereg(struct device *, int, int, int); 171 void ure_lock_mii(struct ure_softc *); 172 void ure_unlock_mii(struct ure_softc *); 173 174 int ure_encap_txpkt(struct mbuf *, char *, uint32_t); 175 int ure_encap_xfer(struct ifnet *, struct ure_softc *, 176 struct ure_chain *); 177 void ure_rxeof(struct usbd_xfer *, void *, usbd_status); 178 void ure_txeof(struct usbd_xfer *, void *, usbd_status); 179 int ure_xfer_list_init(struct ure_softc *, struct ure_chain *, 180 uint32_t, int); 181 void ure_xfer_list_free(struct ure_softc *, struct ure_chain *, int); 182 183 void ure_tick_task(void *); 184 void ure_tick(void *); 185 186 int ure_ifmedia_upd(struct ifnet *); 187 void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *); 188 void ure_add_media_types(struct ure_softc *); 189 void ure_link_state(struct ure_softc *); 190 int ure_get_link_status(struct ure_softc *); 191 void ure_iff(struct ure_softc *); 192 void ure_rxvlan(struct ure_softc *); 193 int ure_ioctl(struct ifnet *, u_long, caddr_t); 194 void ure_rtl8152_init(struct ure_softc *); 195 void ure_rtl8153_init(struct ure_softc *); 196 void ure_rtl8153b_init(struct ure_softc *); 197 void ure_rtl8152_nic_reset(struct ure_softc *); 198 void ure_rtl8153_nic_reset(struct ure_softc *); 199 void ure_rtl8153_phy_status(struct ure_softc *, int); 200 void ure_reset_bmu(struct ure_softc *); 201 void ure_disable_teredo(struct ure_softc *); 202 203 #define URE_SETBIT_1(sc, reg, index, x) \ 204 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x)) 205 #define URE_SETBIT_2(sc, reg, index, x) \ 206 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x)) 207 #define URE_SETBIT_4(sc, reg, index, x) \ 208 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x)) 209 210 #define URE_CLRBIT_1(sc, reg, index, x) \ 211 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~(x)) 212 #define URE_CLRBIT_2(sc, reg, index, x) \ 213 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~(x)) 214 #define URE_CLRBIT_4(sc, reg, index, x) \ 215 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~(x)) 216 217 int 218 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index, 219 void *buf, int len) 220 { 221 usb_device_request_t req; 222 usbd_status err; 223 224 if (usbd_is_dying(sc->ure_udev)) 225 return 0; 226 227 if (rw == URE_CTL_WRITE) 228 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 229 else 230 req.bmRequestType = UT_READ_VENDOR_DEVICE; 231 req.bRequest = UR_SET_ADDRESS; 232 USETW(req.wValue, val); 233 USETW(req.wIndex, index); 234 USETW(req.wLength, len); 235 236 DPRINTFN(5, ("ure_ctl: rw %d, val 0x%04hu, index 0x%04hu, len %d\n", 237 rw, val, index, len)); 238 err = usbd_do_request(sc->ure_udev, &req, buf); 239 if (err) { 240 DPRINTF(("ure_ctl: error %d\n", err)); 241 return -1; 242 } 243 244 return 0; 245 } 246 247 int 248 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 249 void *buf, int len) 250 { 251 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len)); 252 } 253 254 int 255 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 256 void *buf, int len) 257 { 258 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len)); 259 } 260 261 uint8_t 262 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index) 263 { 264 uint32_t val; 265 uint8_t temp[4]; 266 uint8_t shift; 267 268 shift = (reg & 3) << 3; 269 reg &= ~3; 270 271 ure_read_mem(sc, reg, index, &temp, 4); 272 val = UGETDW(temp); 273 val >>= shift; 274 275 return (val & 0xff); 276 } 277 278 uint16_t 279 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index) 280 { 281 uint32_t val; 282 uint8_t temp[4]; 283 uint8_t shift; 284 285 shift = (reg & 2) << 3; 286 reg &= ~3; 287 288 ure_read_mem(sc, reg, index, &temp, 4); 289 val = UGETDW(temp); 290 val >>= shift; 291 292 return (val & 0xffff); 293 } 294 295 uint32_t 296 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index) 297 { 298 uint8_t temp[4]; 299 300 ure_read_mem(sc, reg, index, &temp, 4); 301 return (UGETDW(temp)); 302 } 303 304 int 305 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 306 { 307 uint16_t byen; 308 uint8_t temp[4]; 309 uint8_t shift; 310 311 byen = URE_BYTE_EN_BYTE; 312 shift = reg & 3; 313 val &= 0xff; 314 315 if (reg & 3) { 316 byen <<= shift; 317 val <<= (shift << 3); 318 reg &= ~3; 319 } 320 321 USETDW(temp, val); 322 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 323 } 324 325 int 326 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 327 { 328 uint16_t byen; 329 uint8_t temp[4]; 330 uint8_t shift; 331 332 byen = URE_BYTE_EN_WORD; 333 shift = reg & 2; 334 val &= 0xffff; 335 336 if (reg & 2) { 337 byen <<= shift; 338 val <<= (shift << 3); 339 reg &= ~3; 340 } 341 342 USETDW(temp, val); 343 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 344 } 345 346 int 347 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 348 { 349 uint8_t temp[4]; 350 351 USETDW(temp, val); 352 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4)); 353 } 354 355 uint16_t 356 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr) 357 { 358 uint16_t reg; 359 360 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 361 reg = (addr & 0x0fff) | 0xb000; 362 363 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA)); 364 } 365 366 void 367 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 368 { 369 uint16_t reg; 370 371 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 372 reg = (addr & 0x0fff) | 0xb000; 373 374 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data); 375 } 376 377 int 378 ure_miibus_readreg(struct device *dev, int phy, int reg) 379 { 380 struct ure_softc *sc = (void *)dev; 381 uint16_t val; 382 383 if (usbd_is_dying(sc->ure_udev)) 384 return 0; 385 386 /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */ 387 if (reg == RL_GMEDIASTAT) 388 return ure_read_1(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA); 389 390 ure_lock_mii(sc); 391 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2); 392 ure_unlock_mii(sc); 393 394 return val; /* letoh16? */ 395 } 396 397 void 398 ure_miibus_writereg(struct device *dev, int phy, int reg, int val) 399 { 400 struct ure_softc *sc = (void *)dev; 401 402 ure_lock_mii(sc); 403 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val); /* htole16? */ 404 ure_unlock_mii(sc); 405 } 406 407 void 408 ure_miibus_statchg(struct device *dev) 409 { 410 struct ure_softc *sc = (void *)dev; 411 struct mii_data *mii = &sc->ure_mii; 412 struct ifnet *ifp = &sc->ure_ac.ac_if; 413 414 if ((ifp->if_flags & IFF_RUNNING) == 0) 415 return; 416 417 sc->ure_flags &= ~URE_FLAG_LINK; 418 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 419 (IFM_ACTIVE | IFM_AVALID)) { 420 switch (IFM_SUBTYPE(mii->mii_media_active)) { 421 case IFM_10_T: 422 case IFM_100_TX: 423 sc->ure_flags |= URE_FLAG_LINK; 424 break; 425 case IFM_1000_T: 426 if ((sc->ure_flags & URE_FLAG_8152) != 0) 427 break; 428 sc->ure_flags |= URE_FLAG_LINK; 429 break; 430 default: 431 break; 432 } 433 } 434 435 /* Lost link, do nothing. */ 436 if ((sc->ure_flags & URE_FLAG_LINK) == 0) 437 return; 438 } 439 440 int 441 ure_ifmedia_upd(struct ifnet *ifp) 442 { 443 struct ure_softc *sc = ifp->if_softc; 444 struct mii_data *mii = &sc->ure_mii; 445 struct ifmedia *ifm = &sc->ure_ifmedia; 446 int anar, gig, err, reg; 447 448 if (sc->ure_flags & URE_FLAG_8156) { 449 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 450 return (EINVAL); 451 452 reg = ure_ocp_reg_read(sc, 0xa5d4); 453 reg &= ~URE_ADV_2500TFDX; 454 455 anar = gig = 0; 456 switch (IFM_SUBTYPE(ifm->ifm_media)) { 457 case IFM_AUTO: 458 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 459 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 460 reg |= URE_ADV_2500TFDX; 461 break; 462 case IFM_2500_T: 463 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 464 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 465 reg |= URE_ADV_2500TFDX; 466 ifp->if_baudrate = IF_Mbps(2500); 467 break; 468 case IFM_1000_T: 469 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 470 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 471 ifp->if_baudrate = IF_Gbps(1); 472 break; 473 case IFM_100_TX: 474 anar |= ANAR_TX | ANAR_TX_FD; 475 ifp->if_baudrate = IF_Mbps(100); 476 break; 477 case IFM_10_T: 478 anar |= ANAR_10 | ANAR_10_FD; 479 ifp->if_baudrate = IF_Mbps(10); 480 break; 481 default: 482 printf("%s: unsupported media type\n", 483 sc->ure_dev.dv_xname); 484 return (EINVAL); 485 } 486 487 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_ANAR * 2, 488 anar | ANAR_PAUSE_ASYM | ANAR_FC); 489 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_100T2CR * 2, gig); 490 ure_ocp_reg_write(sc, 0xa5d4, reg); 491 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR, 492 BMCR_AUTOEN | BMCR_STARTNEG); 493 494 return (0); 495 } 496 497 if (mii->mii_instance) { 498 struct mii_softc *miisc; 499 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 500 PHY_RESET(miisc); 501 } 502 503 err = mii_mediachg(mii); 504 if (err == ENXIO) 505 return (0); 506 else 507 return (err); 508 } 509 510 void 511 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 512 { 513 struct ure_softc *sc = ifp->if_softc; 514 struct mii_data *mii = &sc->ure_mii; 515 uint16_t status = 0; 516 517 if (sc->ure_flags & URE_FLAG_8156) { 518 ifmr->ifm_status = IFM_AVALID; 519 if (ure_get_link_status(sc)) { 520 ifmr->ifm_status |= IFM_ACTIVE; 521 status = ure_read_2(sc, URE_PLA_PHYSTATUS, 522 URE_MCU_TYPE_PLA); 523 if ((status & URE_PHYSTATUS_FDX) || 524 (status & URE_PHYSTATUS_2500MBPS)) 525 ifmr->ifm_active |= IFM_FDX; 526 else 527 ifmr->ifm_active |= IFM_HDX; 528 if (status & URE_PHYSTATUS_10MBPS) 529 ifmr->ifm_active |= IFM_10_T; 530 else if (status & URE_PHYSTATUS_100MBPS) 531 ifmr->ifm_active |= IFM_100_TX; 532 else if (status & URE_PHYSTATUS_1000MBPS) 533 ifmr->ifm_active |= IFM_1000_T; 534 else if (status & URE_PHYSTATUS_2500MBPS) 535 ifmr->ifm_active |= IFM_2500_T; 536 } 537 return; 538 } 539 540 mii_pollstat(mii); 541 ifmr->ifm_active = mii->mii_media_active; 542 ifmr->ifm_status = mii->mii_media_status; 543 } 544 545 void 546 ure_add_media_types(struct ure_softc *sc) 547 { 548 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 549 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 550 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 551 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, 552 NULL); 553 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 554 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, 555 NULL); 556 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_2500_T, 0, NULL); 557 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_2500_T | IFM_FDX, 0, 558 NULL); 559 } 560 561 void 562 ure_link_state(struct ure_softc *sc) 563 { 564 struct ifnet *ifp = &sc->ure_ac.ac_if; 565 int link = LINK_STATE_DOWN; 566 567 if (ure_get_link_status(sc)) 568 link = LINK_STATE_UP; 569 570 if (ifp->if_link_state != link) { 571 ifp->if_link_state = link; 572 if_link_state_change(ifp); 573 } 574 } 575 576 int 577 ure_get_link_status(struct ure_softc *sc) 578 { 579 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & 580 URE_PHYSTATUS_LINK) { 581 sc->ure_flags |= URE_FLAG_LINK; 582 return (1); 583 } else { 584 sc->ure_flags &= ~URE_FLAG_LINK; 585 return (0); 586 } 587 } 588 589 void 590 ure_iff(struct ure_softc *sc) 591 { 592 struct ifnet *ifp = &sc->ure_ac.ac_if; 593 struct ether_multi *enm; 594 struct ether_multistep step; 595 uint32_t hashes[2] = { 0, 0 }; 596 uint32_t hash; 597 uint32_t rxmode; 598 599 if (usbd_is_dying(sc->ure_udev)) 600 return; 601 602 rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA); 603 rxmode &= ~URE_RCR_ACPT_ALL; 604 ifp->if_flags &= ~IFF_ALLMULTI; 605 606 /* 607 * Always accept frames destined to our station address. 608 * Always accept broadcast frames. 609 */ 610 rxmode |= URE_RCR_APM | URE_RCR_AB; 611 612 if (ifp->if_flags & IFF_PROMISC || sc->ure_ac.ac_multirangecnt > 0) { 613 ifp->if_flags |= IFF_ALLMULTI; 614 rxmode |= URE_RCR_AM; 615 if (ifp->if_flags & IFF_PROMISC) 616 rxmode |= URE_RCR_AAP; 617 hashes[0] = hashes[1] = 0xffffffff; 618 } else { 619 rxmode |= URE_RCR_AM; 620 621 ETHER_FIRST_MULTI(step, &sc->ure_ac, enm); 622 while (enm != NULL) { 623 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) 624 >> 26; 625 if (hash < 32) 626 hashes[0] |= (1 << hash); 627 else 628 hashes[1] |= (1 << (hash - 32)); 629 630 ETHER_NEXT_MULTI(step, enm); 631 } 632 633 hash = swap32(hashes[0]); 634 hashes[0] = swap32(hashes[1]); 635 hashes[1] = hash; 636 } 637 638 ure_write_mem(sc, URE_PLA_MAR, URE_MCU_TYPE_PLA | URE_BYTE_EN_DWORD, 639 hashes, sizeof(hashes)); 640 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 641 } 642 643 void 644 ure_rxvlan(struct ure_softc *sc) 645 { 646 struct ifnet *ifp = &sc->ure_ac.ac_if; 647 uint16_t reg; 648 649 if (sc->ure_flags & URE_FLAG_8156) { 650 reg = ure_read_2(sc, 0xc012, URE_MCU_TYPE_PLA); 651 reg &= ~0x00c0; 652 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 653 reg |= 0x00c0; 654 ure_write_2(sc, 0xc012, URE_MCU_TYPE_PLA, reg); 655 } else { 656 reg = ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA); 657 reg &= ~URE_CPCR_RX_VLAN; 658 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) 659 reg |= URE_CPCR_RX_VLAN; 660 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, reg); 661 } 662 } 663 664 void 665 ure_reset(struct ure_softc *sc) 666 { 667 int i; 668 669 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 670 671 for (i = 0; i < URE_TIMEOUT; i++) { 672 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) & 673 URE_CR_RST)) 674 break; 675 DELAY(100); 676 } 677 if (i == URE_TIMEOUT) 678 printf("%s: reset never completed\n", sc->ure_dev.dv_xname); 679 } 680 681 void 682 ure_watchdog(struct ifnet *ifp) 683 { 684 struct ure_softc *sc = ifp->if_softc; 685 struct ure_chain *c; 686 usbd_status err; 687 int i, s; 688 689 ifp->if_timer = 0; 690 691 if (usbd_is_dying(sc->ure_udev)) 692 return; 693 694 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) 695 return; 696 697 sc = ifp->if_softc; 698 s = splnet(); 699 700 ifp->if_oerrors++; 701 DPRINTF(("%s: watchdog timeout\n", sc->ure_dev.dv_xname)); 702 703 for (i = 0; i < URE_TX_LIST_CNT; i++) { 704 c = &sc->ure_cdata.ure_tx_chain[i]; 705 if (c->uc_cnt > 0) { 706 usbd_get_xfer_status(c->uc_xfer, NULL, NULL, NULL, 707 &err); 708 ure_txeof(c->uc_xfer, c, err); 709 } 710 } 711 712 if (ifq_is_oactive(&ifp->if_snd)) 713 ifq_restart(&ifp->if_snd); 714 splx(s); 715 } 716 717 void 718 ure_init(void *xsc) 719 { 720 struct ure_softc *sc = xsc; 721 struct ure_chain *c; 722 struct ifnet *ifp = &sc->ure_ac.ac_if; 723 usbd_status err; 724 uint32_t reg = 0; 725 int s, i; 726 727 s = splnet(); 728 729 /* Cancel pending I/O. */ 730 ure_stop(sc); 731 732 if (sc->ure_flags & URE_FLAG_8152) 733 ure_rtl8152_nic_reset(sc); 734 else 735 ure_rtl8153_nic_reset(sc); 736 737 if (ure_xfer_list_init(sc, sc->ure_cdata.ure_rx_chain, 738 sc->ure_rxbufsz, URE_RX_LIST_CNT) == ENOBUFS) { 739 printf("%s: rx list init failed\n", sc->ure_dev.dv_xname); 740 splx(s); 741 return; 742 } 743 744 if (ure_xfer_list_init(sc, sc->ure_cdata.ure_tx_chain, 745 sc->ure_txbufsz, URE_TX_LIST_CNT) == ENOBUFS) { 746 printf("%s: tx list init failed\n", sc->ure_dev.dv_xname); 747 splx(s); 748 return; 749 } 750 751 /* Initialize the SLIST we are using for the multiple tx buffers */ 752 SLIST_INIT(&sc->ure_cdata.ure_tx_free); 753 for (i = 0; i < URE_TX_LIST_CNT; i++) 754 SLIST_INSERT_HEAD(&sc->ure_cdata.ure_tx_free, 755 &sc->ure_cdata.ure_tx_chain[i], uc_list); 756 757 /* Set MAC address. */ 758 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 759 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 760 sc->ure_ac.ac_enaddr, 8); 761 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 762 763 if (!(sc->ure_flags & URE_FLAG_8152)) { 764 reg = sc->ure_rxbufsz - URE_FRAMELEN(ifp->if_mtu) + 765 sizeof(struct ure_rxpkt) + URE_RX_BUF_ALIGN; 766 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156)) { 767 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, 768 reg / 8); 769 770 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 771 (sc->ure_flags & URE_FLAG_8153B) ? 16 : 80); 772 ure_write_2(sc, URE_USB_PM_CTRL_STATUS, 773 URE_MCU_TYPE_USB, 1875); 774 } else { 775 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, 776 reg / 4); 777 switch (sc->ure_udev->speed) { 778 case USB_SPEED_SUPER: 779 reg = URE_COALESCE_SUPER / 8; 780 break; 781 case USB_SPEED_HIGH: 782 reg = URE_COALESCE_HIGH / 8; 783 break; 784 default: 785 reg = URE_COALESCE_SLOW / 8; 786 break; 787 } 788 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 789 reg); 790 } 791 } 792 793 /* Reset the packet filter. */ 794 URE_CLRBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN); 795 URE_SETBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN); 796 797 /* Enable transmit and receive. */ 798 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE); 799 800 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156)) { 801 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB, 802 URE_OWN_UPDATE | URE_OWN_CLEAR); 803 } 804 805 URE_CLRBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 806 807 /* Load the multicast filter. */ 808 ure_iff(sc); 809 810 /* Open RX and TX pipes. */ 811 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_RX], 812 USBD_EXCLUSIVE_USE, &sc->ure_ep[URE_ENDPT_RX]); 813 if (err) { 814 printf("%s: open rx pipe failed: %s\n", 815 sc->ure_dev.dv_xname, usbd_errstr(err)); 816 splx(s); 817 return; 818 } 819 820 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_TX], 821 USBD_EXCLUSIVE_USE, &sc->ure_ep[URE_ENDPT_TX]); 822 if (err) { 823 printf("%s: open tx pipe failed: %s\n", 824 sc->ure_dev.dv_xname, usbd_errstr(err)); 825 splx(s); 826 return; 827 } 828 829 /* Start up the receive pipe. */ 830 for (i = 0; i < URE_RX_LIST_CNT; i++) { 831 c = &sc->ure_cdata.ure_rx_chain[i]; 832 usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_RX], 833 c, c->uc_buf, c->uc_bufmax, 834 USBD_SHORT_XFER_OK | USBD_NO_COPY, 835 USBD_NO_TIMEOUT, ure_rxeof); 836 usbd_transfer(c->uc_xfer); 837 } 838 839 ure_ifmedia_upd(ifp); 840 841 /* Indicate we are up and running. */ 842 sc->ure_flags &= ~URE_FLAG_LINK; 843 ifp->if_flags |= IFF_RUNNING; 844 ifq_clr_oactive(&ifp->if_snd); 845 846 timeout_add_sec(&sc->ure_stat_ch, 1); 847 848 splx(s); 849 } 850 851 void 852 ure_start(struct ifnet *ifp) 853 { 854 struct ure_softc *sc = ifp->if_softc; 855 struct ure_cdata *cd = &sc->ure_cdata; 856 struct ure_chain *c; 857 struct mbuf *m = NULL; 858 uint32_t new_buflen; 859 int s, mlen; 860 861 if (!(sc->ure_flags & URE_FLAG_LINK) || 862 (ifp->if_flags & (IFF_RUNNING|IFF_UP)) != 863 (IFF_RUNNING|IFF_UP)) { 864 return; 865 } 866 867 s = splnet(); 868 869 c = SLIST_FIRST(&cd->ure_tx_free); 870 while (c != NULL) { 871 m = ifq_deq_begin(&ifp->if_snd); 872 if (m == NULL) 873 break; 874 875 mlen = m->m_pkthdr.len; 876 877 /* Discard packet larger than buffer. */ 878 if (mlen + sizeof(struct ure_txpkt) >= c->uc_bufmax) { 879 ifq_deq_commit(&ifp->if_snd, m); 880 m_freem(m); 881 ifp->if_oerrors++; 882 continue; 883 } 884 885 /* 886 * If packet larger than remaining space, send buffer and 887 * continue. 888 */ 889 new_buflen = roundup(c->uc_buflen, URE_TX_BUF_ALIGN); 890 if (new_buflen + sizeof(struct ure_txpkt) + mlen >= 891 c->uc_bufmax) { 892 ifq_deq_rollback(&ifp->if_snd, m); 893 SLIST_REMOVE_HEAD(&cd->ure_tx_free, uc_list); 894 if (ure_encap_xfer(ifp, sc, c)) { 895 SLIST_INSERT_HEAD(&cd->ure_tx_free, c, 896 uc_list); 897 break; 898 } 899 c = SLIST_FIRST(&cd->ure_tx_free); 900 continue; 901 } 902 903 /* Append packet to current buffer. */ 904 mlen = ure_encap_txpkt(m, c->uc_buf + new_buflen, 905 c->uc_bufmax - new_buflen); 906 if (mlen <= 0) { 907 ifq_deq_rollback(&ifp->if_snd, m); 908 break; 909 } 910 911 ifq_deq_commit(&ifp->if_snd, m); 912 c->uc_cnt += 1; 913 c->uc_buflen = new_buflen + mlen; 914 915 #if NBPFILTER > 0 916 if (ifp->if_bpf) 917 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 918 #endif 919 920 m_freem(m); 921 } 922 923 if (c != NULL) { 924 /* Send current buffer unless empty */ 925 if (c->uc_buflen > 0 && c->uc_cnt > 0) { 926 SLIST_REMOVE_HEAD(&cd->ure_tx_free, uc_list); 927 if (ure_encap_xfer(ifp, sc, c)) { 928 SLIST_INSERT_HEAD(&cd->ure_tx_free, c, 929 uc_list); 930 } 931 c = SLIST_FIRST(&cd->ure_tx_free); 932 } 933 } 934 935 ifp->if_timer = 5; 936 if (c == NULL) 937 ifq_set_oactive(&ifp->if_snd); 938 splx(s); 939 } 940 941 void 942 ure_tick(void *xsc) 943 { 944 struct ure_softc *sc = xsc; 945 946 if (sc == NULL) 947 return; 948 949 if (usbd_is_dying(sc->ure_udev)) 950 return; 951 952 usb_add_task(sc->ure_udev, &sc->ure_tick_task); 953 } 954 955 void 956 ure_stop(struct ure_softc *sc) 957 { 958 struct ure_cdata *cd; 959 struct ifnet *ifp; 960 usbd_status err; 961 962 ure_reset(sc); 963 964 ifp = &sc->ure_ac.ac_if; 965 ifp->if_timer = 0; 966 ifp->if_flags &= ~IFF_RUNNING; 967 ifq_clr_oactive(&ifp->if_snd); 968 969 timeout_del(&sc->ure_stat_ch); 970 sc->ure_flags &= ~URE_FLAG_LINK; 971 972 if (sc->ure_ep[URE_ENDPT_RX] != NULL) { 973 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_RX]); 974 if (err) { 975 printf("%s: close rx pipe failed: %s\n", 976 sc->ure_dev.dv_xname, usbd_errstr(err)); 977 } 978 sc->ure_ep[URE_ENDPT_RX] = NULL; 979 } 980 981 if (sc->ure_ep[URE_ENDPT_TX] != NULL) { 982 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_TX]); 983 if (err) { 984 printf("%s: close tx pipe failed: %s\n", 985 sc->ure_dev.dv_xname, usbd_errstr(err)); 986 } 987 sc->ure_ep[URE_ENDPT_TX] = NULL; 988 } 989 990 cd = &sc->ure_cdata; 991 ure_xfer_list_free(sc, cd->ure_rx_chain, URE_RX_LIST_CNT); 992 ure_xfer_list_free(sc, cd->ure_tx_chain, URE_TX_LIST_CNT); 993 } 994 995 int 996 ure_xfer_list_init(struct ure_softc *sc, struct ure_chain *ch, 997 uint32_t bufsize, int listlen) 998 { 999 struct ure_chain *c; 1000 int i; 1001 1002 for (i = 0; i < listlen; i++) { 1003 c = &ch[i]; 1004 c->uc_sc = sc; 1005 c->uc_idx = i; 1006 c->uc_buflen = 0; 1007 c->uc_bufmax = bufsize; 1008 c->uc_cnt = 0; 1009 if (c->uc_xfer == NULL) { 1010 c->uc_xfer = usbd_alloc_xfer(sc->ure_udev); 1011 if (c->uc_xfer == NULL) 1012 return (ENOBUFS); 1013 c->uc_buf = usbd_alloc_buffer(c->uc_xfer, c->uc_bufmax); 1014 if (c->uc_buf == NULL) { 1015 usbd_free_xfer(c->uc_xfer); 1016 c->uc_xfer = NULL; 1017 return (ENOBUFS); 1018 } 1019 } 1020 } 1021 1022 return (0); 1023 } 1024 1025 void 1026 ure_xfer_list_free(struct ure_softc *sc, struct ure_chain *ch, int listlen) 1027 { 1028 int i; 1029 1030 for (i = 0; i < listlen; i++) { 1031 if (ch[i].uc_buf != NULL) { 1032 ch[i].uc_buf = NULL; 1033 } 1034 ch[i].uc_cnt = 0; 1035 if (ch[i].uc_xfer != NULL) { 1036 usbd_free_xfer(ch[i].uc_xfer); 1037 ch[i].uc_xfer = NULL; 1038 } 1039 } 1040 } 1041 1042 void 1043 ure_rtl8152_init(struct ure_softc *sc) 1044 { 1045 uint32_t pwrctrl; 1046 1047 /* Disable ALDPS. */ 1048 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 1049 URE_DIS_SDSAVE); 1050 usbd_delay_ms(sc->ure_udev, 20); 1051 1052 if (sc->ure_chip & URE_CHIP_VER_4C00) 1053 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 1054 URE_LED_MODE_MASK); 1055 1056 URE_CLRBIT_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, URE_POWER_CUT); 1057 URE_CLRBIT_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 1058 URE_RESUME_INDICATE); 1059 1060 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 1061 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 1062 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 1063 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 1064 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 1065 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 1066 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 1067 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 1068 URE_SPDWN_LINKCHG_MSK); 1069 1070 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET); 1071 1072 /* Enable Rx aggregation. */ 1073 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1074 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1075 } 1076 1077 void 1078 ure_rtl8153_init(struct ure_softc *sc) 1079 { 1080 uint16_t reg; 1081 uint8_t u1u2[8]; 1082 int i; 1083 1084 memset(u1u2, 0x00, sizeof(u1u2)); 1085 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, u1u2, 1086 sizeof(u1u2)); 1087 1088 for (i = 0; i < 500; i++) { 1089 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 1090 URE_AUTOLOAD_DONE) 1091 break; 1092 usbd_delay_ms(sc->ure_udev, 20); 1093 } 1094 if (i == 500) 1095 printf("%s: timeout waiting for chip autoload\n", 1096 sc->ure_dev.dv_xname); 1097 1098 ure_rtl8153_phy_status(sc, 0); 1099 1100 if (sc->ure_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 | 1101 URE_CHIP_VER_5C20)) { 1102 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG, 1103 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 1104 } 1105 1106 ure_rtl8153_phy_status(sc, 1); 1107 1108 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1109 1110 if (sc->ure_chip & URE_CHIP_VER_5C10) { 1111 reg = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 1112 reg &= ~URE_PWD_DN_SCALE_MASK; 1113 reg |= URE_PWD_DN_SCALE(96); 1114 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, reg); 1115 1116 URE_SETBIT_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 1117 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 1118 } else if (sc->ure_chip & URE_CHIP_VER_5C20) { 1119 URE_CLRBIT_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 1120 URE_ECM_ALDPS); 1121 } 1122 if (sc->ure_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) { 1123 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB)) 1124 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, 1125 URE_DYNAMIC_BURST); 1126 else 1127 URE_CLRBIT_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, 1128 URE_DYNAMIC_BURST); 1129 } 1130 1131 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, URE_EP4_FULL_FC); 1132 1133 URE_CLRBIT_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, URE_TIMER11_EN); 1134 1135 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 1136 URE_LED_MODE_MASK); 1137 1138 if ((sc->ure_chip & URE_CHIP_VER_5C10) && 1139 sc->ure_udev->speed != USB_SPEED_SUPER) 1140 reg = URE_LPM_TIMER_500MS; 1141 else 1142 reg = URE_LPM_TIMER_500US; 1143 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 1144 URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM | reg); 1145 1146 reg = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 1147 reg &= ~URE_SEN_VAL_MASK; 1148 reg |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 1149 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, reg); 1150 1151 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 1152 1153 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 1154 URE_PWR_EN | URE_PHASE2_EN); 1155 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS); 1156 1157 memset(u1u2, 0xff, sizeof(u1u2)); 1158 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, u1u2, 1159 sizeof(u1u2)); 1160 1161 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0); 1162 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 0); 1163 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 0); 1164 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0); 1165 1166 /* Enable Rx aggregation. */ 1167 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1168 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1169 1170 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET); 1171 } 1172 1173 void 1174 ure_rtl8153b_init(struct ure_softc *sc) 1175 { 1176 uint16_t reg; 1177 int i; 1178 1179 if (sc->ure_flags & URE_FLAG_8156) { 1180 URE_CLRBIT_1(sc, 0xd26b, URE_MCU_TYPE_USB, 0x01); 1181 ure_write_2(sc, 0xd32a, URE_MCU_TYPE_USB, 0); 1182 URE_SETBIT_2(sc, 0xcfee, URE_MCU_TYPE_USB, 0x0020); 1183 } 1184 1185 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, LPM_U1U2_EN); 1186 1187 for (i = 0; i < 500; i++) { 1188 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 1189 URE_AUTOLOAD_DONE) 1190 break; 1191 usbd_delay_ms(sc->ure_udev, 20); 1192 } 1193 if (i == 500) 1194 printf("%s: timeout waiting for chip autoload\n", 1195 sc->ure_dev.dv_xname); 1196 1197 ure_rtl8153_phy_status(sc, 0); 1198 ure_rtl8153_phy_status(sc, 1); 1199 1200 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1201 1202 /* MSC timer, 32760 ms. */ 1203 ure_write_2(sc, URE_USB_MSC_TIMER, URE_MCU_TYPE_USB, 0x0fff); 1204 1205 /* U1/U2/L1 idle timer, 500 us. */ 1206 ure_write_2(sc, URE_USB_U1U2_TIMER, URE_MCU_TYPE_USB, 500); 1207 1208 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN); 1209 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS); 1210 1211 URE_CLRBIT_1(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 1212 URE_UPS_EN | URE_USP_PREWAKE); 1213 URE_CLRBIT_1(sc, 0xcfff, URE_MCU_TYPE_USB, 0x01); 1214 1215 if (!(sc->ure_flags & URE_FLAG_8156)) { 1216 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, 1217 URE_PCUT_STATUS); 1218 ure_rtl8153_phy_status(sc, 0); 1219 } 1220 1221 URE_CLRBIT_1(sc, URE_PLA_INDICATE_FALG, URE_MCU_TYPE_PLA, 1222 URE_UPCOMING_RUNTIME_D3); 1223 URE_CLRBIT_1(sc, URE_PLA_SUSPEND_FLAG, URE_MCU_TYPE_PLA, 1224 URE_LINK_CHG_EVENT); 1225 URE_CLRBIT_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, 1226 URE_LINK_CHANGE_FLAG); 1227 1228 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 1229 URE_CLRBIT_2(sc, URE_PLA_CONFIG34, URE_MCU_TYPE_PLA, 1230 URE_LINK_OFF_WAKE_EN); 1231 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 1232 1233 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, LPM_U1U2_EN); 1234 1235 /* MAC clock speed down. */ 1236 if (sc->ure_flags & URE_FLAG_8156) { 1237 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0x0403); 1238 reg = ure_read_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA) & 1239 ~0xff; 1240 reg |= URE_MAC_CLK_SPDWN_EN | 0x0003; 1241 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, reg); 1242 1243 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 1244 0x4000); 1245 1246 reg = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA); 1247 if (ure_get_link_status(sc)) 1248 reg |= 0x8000; 1249 else 1250 reg &= ~0x8000; 1251 reg |= 0x0001; 1252 ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, reg); 1253 } else 1254 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 1255 URE_MAC_CLK_SPDWN_EN); 1256 1257 /* Enable Rx aggregation. */ 1258 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1259 URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1260 1261 if (sc->ure_flags & URE_FLAG_8156) 1262 URE_SETBIT_1(sc, 0xcfd9, URE_MCU_TYPE_USB, 0x04); 1263 1264 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET); 1265 } 1266 1267 void 1268 ure_rtl8152_nic_reset(struct ure_softc *sc) 1269 { 1270 uint32_t rx_fifo1, rx_fifo2; 1271 int i; 1272 1273 /* Disable ALDPS. */ 1274 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 1275 URE_DIS_SDSAVE); 1276 usbd_delay_ms(sc->ure_udev, 20); 1277 1278 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL); 1279 1280 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 1281 ure_disable_teredo(sc); 1282 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 1283 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 1284 1285 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB); 1286 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN); 1287 for (i = 0; i < URE_TIMEOUT; i++) { 1288 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1289 URE_LINK_LIST_READY) 1290 break; 1291 usbd_delay_ms(sc->ure_udev, 1); 1292 } 1293 if (i == URE_TIMEOUT) 1294 printf("%s: timeout waiting for OOB control\n", 1295 sc->ure_dev.dv_xname); 1296 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL); 1297 for (i = 0; i < URE_TIMEOUT; i++) { 1298 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1299 URE_LINK_LIST_READY) 1300 break; 1301 usbd_delay_ms(sc->ure_udev, 1); 1302 } 1303 if (i == URE_TIMEOUT) 1304 printf("%s: timeout waiting for OOB control\n", 1305 sc->ure_dev.dv_xname); 1306 1307 ure_reset(sc); 1308 1309 /* Configure Rx FIFO threshold. */ 1310 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 1311 URE_RXFIFO_THR1_NORMAL); 1312 if (sc->ure_udev->speed == USB_SPEED_FULL) { 1313 rx_fifo1 = URE_RXFIFO_THR2_FULL; 1314 rx_fifo2 = URE_RXFIFO_THR3_FULL; 1315 } else { 1316 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 1317 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 1318 } 1319 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 1320 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 1321 1322 /* Configure Tx FIFO threshold. */ 1323 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 1324 URE_TXFIFO_THR_NORMAL); 1325 1326 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 1327 URE_TX_AGG_MAX_THRESHOLD); 1328 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 1329 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 1330 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 1331 1332 ure_rxvlan(sc); 1333 ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA, 1334 ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1335 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO); 1336 1337 /* Enable ALDPS. */ 1338 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, 1339 URE_ENPWRSAVE | URE_ENPDNPS | URE_LINKENA | URE_DIS_SDSAVE); 1340 } 1341 1342 void 1343 ure_rtl8153_nic_reset(struct ure_softc *sc) 1344 { 1345 struct ifnet *ifp = &sc->ure_ac.ac_if; 1346 uint32_t reg = 0; 1347 uint8_t u1u2[8] = { 0 }; 1348 int i; 1349 1350 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156)) { 1351 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, 1352 LPM_U1U2_EN); 1353 } else { 1354 memset(u1u2, 0x00, sizeof(u1u2)); 1355 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, 1356 u1u2, sizeof(u1u2)); 1357 } 1358 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1359 1360 /* Disable ALDPS. */ 1361 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1362 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 1363 for (i = 0; i < 20; i++) { 1364 usbd_delay_ms(sc->ure_udev, 1); 1365 if (ure_read_2(sc, 0xe000, URE_MCU_TYPE_PLA) & 0x0100) 1366 break; 1367 } 1368 if (sc->ure_flags & URE_FLAG_8153B) { 1369 URE_CLRBIT_4(sc, URE_USB_UPS_FLAGS, URE_MCU_TYPE_USB, 1370 URE_UPS_FLAGS_EN_ALDPS); 1371 } 1372 1373 if (!(sc->ure_flags & URE_FLAG_8156)) { 1374 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0); 1375 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 0); 1376 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 0); 1377 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0); 1378 } 1379 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 1380 ure_disable_teredo(sc); 1381 1382 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL); 1383 1384 if (sc->ure_flags & URE_FLAG_8156) 1385 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 1386 else 1387 ure_reset(sc); 1388 1389 ure_reset_bmu(sc); 1390 1391 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB); 1392 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN); 1393 1394 if (!(sc->ure_flags & URE_FLAG_8156)) { 1395 for (i = 0; i < URE_TIMEOUT; i++) { 1396 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1397 URE_LINK_LIST_READY) 1398 break; 1399 usbd_delay_ms(sc->ure_udev, 1); 1400 } 1401 if (i == URE_TIMEOUT) 1402 printf("%s: timeout waiting for OOB control\n", 1403 sc->ure_dev.dv_xname); 1404 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 1405 URE_RE_INIT_LL); 1406 for (i = 0; i < URE_TIMEOUT; i++) { 1407 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1408 URE_LINK_LIST_READY) 1409 break; 1410 usbd_delay_ms(sc->ure_udev, 1); 1411 } 1412 if (i == URE_TIMEOUT) 1413 printf("%s: timeout waiting for OOB control\n", 1414 sc->ure_dev.dv_xname); 1415 } 1416 ure_rxvlan(sc); 1417 ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA, 1418 URE_FRAMELEN(ifp->if_mtu)); 1419 ure_write_1(sc, URE_PLA_MTPS, URE_MCU_TYPE_PLA, MTPS_JUMBO); 1420 1421 if (!(sc->ure_flags & URE_FLAG_8156)) { 1422 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 1423 URE_TCR0_AUTO_FIFO); 1424 ure_reset(sc); 1425 } 1426 1427 /* Configure Rx FIFO threshold. */ 1428 if (sc->ure_flags & URE_FLAG_8156) { 1429 ure_write_2(sc, URE_PLA_RXFIFO_CTRL0 + 2, URE_MCU_TYPE_PLA, 1430 0x0008); 1431 ure_write_2(sc, URE_PLA_RXFIFO_CTRL1 + 2, URE_MCU_TYPE_PLA, 1432 0x0100); 1433 ure_write_2(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, 0); 1434 } else { 1435 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 1436 URE_RXFIFO_THR1_NORMAL); 1437 ure_write_2(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, 1438 URE_RXFIFO_THR2_NORMAL); 1439 ure_write_2(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, 1440 URE_RXFIFO_THR3_NORMAL); 1441 } 1442 1443 /* Configure Tx FIFO threshold. */ 1444 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 1445 URE_TXFIFO_THR_NORMAL2); 1446 1447 if (sc->ure_flags & URE_FLAG_8156) { 1448 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 1449 0x4000); 1450 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, 1451 0x00600400); 1452 } else if (sc->ure_flags & URE_FLAG_8153B) { 1453 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, 1454 URE_RX_THR_B); 1455 } 1456 1457 /* Enable ALDPS. */ 1458 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1459 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | URE_EN_ALDPS); 1460 if (sc->ure_flags & URE_FLAG_8153B) { 1461 reg = ure_read_4(sc, URE_USB_UPS_FLAGS, URE_MCU_TYPE_USB) & 1462 URE_UPS_FLAGS_MASK; 1463 ure_write_4(sc, URE_USB_UPS_FLAGS, URE_MCU_TYPE_USB, 1464 reg | URE_UPS_FLAGS_EN_ALDPS); 1465 } 1466 1467 if ((sc->ure_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) || 1468 (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156))) 1469 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 1470 URE_U2P3_ENABLE); 1471 1472 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156)) { 1473 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, 1474 LPM_U1U2_EN); 1475 } else { 1476 memset(u1u2, 0xff, sizeof(u1u2)); 1477 ure_write_mem(sc, URE_USB_TOLERANCE, URE_BYTE_EN_SIX_BYTES, 1478 u1u2, sizeof(u1u2)); 1479 } 1480 } 1481 1482 void 1483 ure_rtl8153_phy_status(struct ure_softc *sc, int enable) 1484 { 1485 uint16_t reg; 1486 int i; 1487 1488 for (i = 0; i < 500; i++) { 1489 reg = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & 1490 URE_PHY_STAT_MASK; 1491 if (enable) { 1492 if (reg == URE_PHY_STAT_LAN_ON) 1493 break; 1494 } else { 1495 if (reg == URE_PHY_STAT_LAN_ON || 1496 reg == URE_PHY_STAT_PWRDN || 1497 reg == URE_PHY_STAT_EXT_INIT) 1498 break; 1499 } 1500 usbd_delay_ms(sc->ure_udev, 20); 1501 } 1502 if (i == 500) 1503 printf("%s: timeout waiting for phy to stabilize\n", 1504 sc->ure_dev.dv_xname); 1505 } 1506 1507 void 1508 ure_reset_bmu(struct ure_softc *sc) 1509 { 1510 URE_CLRBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, 1511 BMU_RESET_EP_IN | BMU_RESET_EP_OUT); 1512 URE_SETBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, 1513 BMU_RESET_EP_IN | BMU_RESET_EP_OUT); 1514 } 1515 1516 void 1517 ure_disable_teredo(struct ure_softc *sc) 1518 { 1519 if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156)) 1520 ure_write_1(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 0xff); 1521 else { 1522 URE_CLRBIT_2(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 1523 URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | 1524 URE_OOB_TEREDO_EN); 1525 } 1526 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, URE_WDT6_SET_MODE); 1527 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 1528 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 1529 } 1530 1531 int 1532 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1533 { 1534 struct ure_softc *sc = ifp->if_softc; 1535 struct ifreq *ifr = (struct ifreq *)data; 1536 int s, error = 0; 1537 1538 s = splnet(); 1539 1540 switch (cmd) { 1541 case SIOCSIFADDR: 1542 ifp->if_flags |= IFF_UP; 1543 if (!(ifp->if_flags & IFF_RUNNING)) 1544 ure_init(sc); 1545 break; 1546 1547 case SIOCSIFFLAGS: 1548 if (ifp->if_flags & IFF_UP) { 1549 if (ifp->if_flags & IFF_RUNNING) 1550 error = ENETRESET; 1551 else 1552 ure_init(sc); 1553 } else { 1554 if (ifp->if_flags & IFF_RUNNING) 1555 ure_stop(sc); 1556 } 1557 break; 1558 1559 case SIOCGIFMEDIA: 1560 case SIOCSIFMEDIA: 1561 if (sc->ure_flags & URE_FLAG_8156) 1562 error = ifmedia_ioctl(ifp, ifr, &sc->ure_ifmedia, cmd); 1563 else 1564 error = ifmedia_ioctl(ifp, ifr, &sc->ure_mii.mii_media, 1565 cmd); 1566 break; 1567 1568 default: 1569 error = ether_ioctl(ifp, &sc->ure_ac, cmd, data); 1570 } 1571 1572 if (error == ENETRESET) { 1573 if (ifp->if_flags & IFF_RUNNING) 1574 ure_iff(sc); 1575 error = 0; 1576 } 1577 1578 splx(s); 1579 1580 return (error); 1581 } 1582 1583 int 1584 ure_match(struct device *parent, void *match, void *aux) 1585 { 1586 struct usb_attach_arg *uaa = aux; 1587 1588 if (uaa->iface == NULL || uaa->configno != 1) 1589 return (UMATCH_NONE); 1590 1591 return (usb_lookup(ure_devs, uaa->vendor, uaa->product) != NULL ? 1592 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 1593 } 1594 1595 void 1596 ure_attach(struct device *parent, struct device *self, void *aux) 1597 { 1598 struct ure_softc *sc = (struct ure_softc *)self; 1599 struct usb_attach_arg *uaa = aux; 1600 usb_interface_descriptor_t *id; 1601 usb_endpoint_descriptor_t *ed; 1602 u_char eaddr[8]; /* 4byte padded */ 1603 struct ifnet *ifp; 1604 int i, mii_flags = 0, s; 1605 uint16_t ver; 1606 1607 sc->ure_udev = uaa->device; 1608 sc->ure_iface = uaa->iface; 1609 1610 usb_init_task(&sc->ure_tick_task, ure_tick_task, sc, 1611 USB_TASK_TYPE_GENERIC); 1612 usb_init_task(&sc->ure_stop_task, (void (*)(void *))ure_stop, sc, 1613 USB_TASK_TYPE_GENERIC); 1614 1615 id = usbd_get_interface_descriptor(sc->ure_iface); 1616 1617 for (i = 0; i < id->bNumEndpoints; i++) { 1618 ed = usbd_interface2endpoint_descriptor(sc->ure_iface, i); 1619 if (!ed) { 1620 printf("%s: couldn't get ep %d\n", 1621 sc->ure_dev.dv_xname, i); 1622 return; 1623 } 1624 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 1625 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 1626 sc->ure_ed[URE_ENDPT_RX] = ed->bEndpointAddress; 1627 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 1628 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 1629 sc->ure_ed[URE_ENDPT_TX] = ed->bEndpointAddress; 1630 } 1631 } 1632 1633 sc->ure_txbufsz = URE_TX_BUFSZ; 1634 sc->ure_rxbufsz = URE_8153_RX_BUFSZ; 1635 1636 s = splnet(); 1637 1638 sc->ure_phyno = 0; 1639 printf("%s: ", sc->ure_dev.dv_xname); 1640 1641 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 1642 switch (ver) { 1643 case 0x4c00: 1644 sc->ure_flags = URE_FLAG_8152; 1645 sc->ure_rxbufsz = URE_8152_RX_BUFSZ; 1646 sc->ure_chip |= URE_CHIP_VER_4C00; 1647 printf("RTL8152 (0x4c00)"); 1648 break; 1649 case 0x4c10: 1650 sc->ure_flags = URE_FLAG_8152; 1651 sc->ure_rxbufsz = URE_8152_RX_BUFSZ; 1652 sc->ure_chip |= URE_CHIP_VER_4C10; 1653 printf("RTL8152 (0x4c10)"); 1654 break; 1655 case 0x5c00: 1656 sc->ure_chip |= URE_CHIP_VER_5C00; 1657 printf("RTL8153 (0x5c00)"); 1658 break; 1659 case 0x5c10: 1660 sc->ure_chip |= URE_CHIP_VER_5C10; 1661 printf("RTL8153 (0x5c10)"); 1662 break; 1663 case 0x5c20: 1664 sc->ure_chip |= URE_CHIP_VER_5C20; 1665 printf("RTL8153 (0x5c20)"); 1666 break; 1667 case 0x5c30: 1668 sc->ure_chip |= URE_CHIP_VER_5C30; 1669 printf("RTL8153 (0x5c30)"); 1670 break; 1671 case 0x6000: 1672 sc->ure_flags = URE_FLAG_8153B; 1673 printf("RTL8153B (0x6000)"); 1674 break; 1675 case 0x6010: 1676 sc->ure_flags = URE_FLAG_8153B; 1677 printf("RTL8153B (0x6010)"); 1678 break; 1679 case 0x7020: 1680 sc->ure_flags = URE_FLAG_8156; 1681 printf("RTL8156 (0x7020)"); 1682 break; 1683 case 0x7030: 1684 sc->ure_flags = URE_FLAG_8156; 1685 printf("RTL8156 (0x7030)"); 1686 break; 1687 default: 1688 printf(", unknown ver %02x", ver); 1689 break; 1690 } 1691 1692 if (sc->ure_flags & URE_FLAG_8152) 1693 ure_rtl8152_init(sc); 1694 else if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156)) 1695 ure_rtl8153b_init(sc); 1696 else 1697 ure_rtl8153_init(sc); 1698 1699 if (sc->ure_chip & URE_CHIP_VER_4C00) 1700 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr, 1701 sizeof(eaddr)); 1702 else 1703 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr, 1704 sizeof(eaddr)); 1705 1706 printf(", address %s\n", ether_sprintf(eaddr)); 1707 1708 bcopy(eaddr, (char *)&sc->ure_ac.ac_enaddr, ETHER_ADDR_LEN); 1709 1710 ifp = &sc->ure_ac.ac_if; 1711 ifp->if_softc = sc; 1712 strlcpy(ifp->if_xname, sc->ure_dev.dv_xname, IFNAMSIZ); 1713 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1714 ifp->if_ioctl = ure_ioctl; 1715 ifp->if_start = ure_start; 1716 ifp->if_watchdog = ure_watchdog; 1717 1718 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 | 1719 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 1720 1721 #if NVLAN > 0 1722 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1723 #endif 1724 1725 if (sc->ure_flags & URE_FLAG_8156) { 1726 ifmedia_init(&sc->ure_ifmedia, IFM_IMASK, ure_ifmedia_upd, 1727 ure_ifmedia_sts); 1728 ure_add_media_types(sc); 1729 ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1730 ifmedia_set(&sc->ure_ifmedia, IFM_ETHER | IFM_AUTO); 1731 sc->ure_ifmedia.ifm_media = sc->ure_ifmedia.ifm_cur->ifm_media; 1732 } else { 1733 rw_init(&sc->ure_mii_lock, "uremii"); 1734 1735 sc->ure_mii.mii_ifp = ifp; 1736 sc->ure_mii.mii_readreg = ure_miibus_readreg; 1737 sc->ure_mii.mii_writereg = ure_miibus_writereg; 1738 sc->ure_mii.mii_statchg = ure_miibus_statchg; 1739 sc->ure_mii.mii_flags = MIIF_AUTOTSLEEP; 1740 1741 ifmedia_init(&sc->ure_mii.mii_media, 0, ure_ifmedia_upd, 1742 ure_ifmedia_sts); 1743 if (!(sc->ure_flags & URE_FLAG_8152)) 1744 mii_flags |= MIIF_DOPAUSE; 1745 mii_attach(self, &sc->ure_mii, 0xffffffff, sc->ure_phyno, 1746 MII_OFFSET_ANY, mii_flags); 1747 if (LIST_FIRST(&sc->ure_mii.mii_phys) == NULL) { 1748 ifmedia_add(&sc->ure_mii.mii_media, 1749 IFM_ETHER | IFM_NONE, 0, NULL); 1750 ifmedia_set(&sc->ure_mii.mii_media, 1751 IFM_ETHER | IFM_NONE); 1752 } else 1753 ifmedia_set(&sc->ure_mii.mii_media, 1754 IFM_ETHER | IFM_AUTO); 1755 } 1756 1757 if_attach(ifp); 1758 ether_ifattach(ifp); 1759 1760 timeout_set(&sc->ure_stat_ch, ure_tick, sc); 1761 1762 splx(s); 1763 } 1764 1765 int 1766 ure_detach(struct device *self, int flags) 1767 { 1768 struct ure_softc *sc = (struct ure_softc *)self; 1769 struct ifnet *ifp = &sc->ure_ac.ac_if; 1770 int s; 1771 1772 if (timeout_initialized(&sc->ure_stat_ch)) 1773 timeout_del(&sc->ure_stat_ch); 1774 1775 if (sc->ure_ep[URE_ENDPT_TX] != NULL) 1776 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_TX]); 1777 if (sc->ure_ep[URE_ENDPT_RX] != NULL) 1778 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_RX]); 1779 1780 usb_rem_task(sc->ure_udev, &sc->ure_tick_task); 1781 usb_rem_task(sc->ure_udev, &sc->ure_stop_task); 1782 1783 s = splusb(); 1784 1785 if (--sc->ure_refcnt >= 0) { 1786 usb_detach_wait(&sc->ure_dev); 1787 } 1788 1789 if (ifp->if_flags & IFF_RUNNING) 1790 ure_stop(sc); 1791 1792 mii_detach(&sc->ure_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1793 ifmedia_delete_instance(&sc->ure_mii.mii_media, IFM_INST_ANY); 1794 if (ifp->if_softc != NULL) { 1795 ether_ifdetach(ifp); 1796 if_detach(ifp); 1797 } 1798 1799 splx(s); 1800 1801 return 0; 1802 } 1803 1804 void 1805 ure_tick_task(void *xsc) 1806 { 1807 struct ure_softc *sc = xsc; 1808 struct mii_data *mii; 1809 int s; 1810 1811 if (sc == NULL) 1812 return; 1813 1814 if (usbd_is_dying(sc->ure_udev)) 1815 return; 1816 mii = &sc->ure_mii; 1817 1818 s = splnet(); 1819 if (sc->ure_flags & URE_FLAG_8156) 1820 ure_link_state(sc); 1821 else { 1822 mii_tick(mii); 1823 if ((sc->ure_flags & URE_FLAG_LINK) == 0) 1824 ure_miibus_statchg(&sc->ure_dev); 1825 } 1826 timeout_add_sec(&sc->ure_stat_ch, 1); 1827 splx(s); 1828 } 1829 1830 void 1831 ure_lock_mii(struct ure_softc *sc) 1832 { 1833 sc->ure_refcnt++; 1834 rw_enter_write(&sc->ure_mii_lock); 1835 } 1836 1837 void 1838 ure_unlock_mii(struct ure_softc *sc) 1839 { 1840 rw_exit_write(&sc->ure_mii_lock); 1841 if (--sc->ure_refcnt < 0) 1842 usb_detach_wakeup(&sc->ure_dev); 1843 } 1844 1845 void 1846 ure_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1847 { 1848 struct ure_chain *c = (struct ure_chain *)priv; 1849 struct ure_softc *sc = c->uc_sc; 1850 struct ifnet *ifp = &sc->ure_ac.ac_if; 1851 u_char *buf = c->uc_buf; 1852 uint32_t cflags, rxvlan, total_len; 1853 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1854 struct mbuf *m; 1855 int pktlen = 0, s; 1856 struct ure_rxpkt rxhdr; 1857 1858 if (usbd_is_dying(sc->ure_udev)) 1859 return; 1860 1861 if (!(ifp->if_flags & IFF_RUNNING)) 1862 return; 1863 1864 if (status != USBD_NORMAL_COMPLETION) { 1865 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 1866 return; 1867 if (usbd_ratecheck(&sc->ure_rx_notice)) { 1868 printf("%s: usb errors on rx: %s\n", 1869 sc->ure_dev.dv_xname, usbd_errstr(status)); 1870 } 1871 if (status == USBD_STALLED) 1872 usbd_clear_endpoint_stall_async( 1873 sc->ure_ep[URE_ENDPT_RX]); 1874 goto done; 1875 } 1876 1877 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL); 1878 DPRINTFN(3, ("received %d bytes\n", total_len)); 1879 1880 do { 1881 if (total_len < sizeof(rxhdr)) { 1882 DPRINTF(("too few bytes left for a packet header\n")); 1883 ifp->if_ierrors++; 1884 goto done; 1885 } 1886 1887 buf += roundup(pktlen, URE_RX_BUF_ALIGN); 1888 1889 memcpy(&rxhdr, buf, sizeof(rxhdr)); 1890 total_len -= sizeof(rxhdr); 1891 1892 pktlen = letoh32(rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK; 1893 DPRINTFN(4, ("next packet is %d bytes\n", pktlen)); 1894 if (pktlen > total_len) { 1895 DPRINTF(("not enough bytes left for next packet\n")); 1896 ifp->if_ierrors++; 1897 goto done; 1898 } 1899 1900 total_len -= roundup(pktlen, URE_RX_BUF_ALIGN); 1901 buf += sizeof(rxhdr); 1902 1903 m = m_devget(buf, pktlen, ETHER_ALIGN); 1904 if (m == NULL) { 1905 DPRINTF(("unable to allocate mbuf for next packet\n")); 1906 ifp->if_ierrors++; 1907 goto done; 1908 } 1909 1910 cflags = letoh32(rxhdr.ure_csum); 1911 rxvlan = letoh32(rxhdr.ure_vlan); 1912 1913 /* Check IP header checksum. */ 1914 if ((rxvlan & URE_RXPKT_IPV4) && 1915 !(cflags & URE_RXPKT_IPSUMBAD)) 1916 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1917 1918 /* Check TCP/UDP checksum. */ 1919 if ((rxvlan & (URE_RXPKT_IPV4 | URE_RXPKT_IPV6)) && 1920 (((rxvlan & URE_RXPKT_TCP) && 1921 !(cflags & URE_RXPKT_TCPSUMBAD)) || 1922 ((rxvlan & URE_RXPKT_UDP) && 1923 !(cflags & URE_RXPKT_UDPSUMBAD)))) 1924 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | 1925 M_UDP_CSUM_IN_OK; 1926 #if NVLAN > 0 1927 if (rxvlan & URE_RXPKT_VLAN_TAG) { 1928 m->m_pkthdr.ether_vtag = 1929 swap16(rxvlan & URE_RXPKT_VLAN_DATA); 1930 m->m_flags |= M_VLANTAG; 1931 } 1932 #endif 1933 1934 ml_enqueue(&ml, m); 1935 } while (total_len > 0); 1936 1937 done: 1938 s = splnet(); 1939 if_input(ifp, &ml); 1940 splx(s); 1941 memset(c->uc_buf, 0, sc->ure_rxbufsz); 1942 1943 usbd_setup_xfer(xfer, sc->ure_ep[URE_ENDPT_RX], c, c->uc_buf, 1944 sc->ure_rxbufsz, USBD_SHORT_XFER_OK | USBD_NO_COPY, 1945 USBD_NO_TIMEOUT, ure_rxeof); 1946 usbd_transfer(xfer); 1947 } 1948 1949 1950 void 1951 ure_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1952 { 1953 struct ure_softc *sc; 1954 struct ure_chain *c; 1955 struct ifnet *ifp; 1956 int s; 1957 1958 c = priv; 1959 sc = c->uc_sc; 1960 ifp = &sc->ure_ac.ac_if; 1961 1962 if (usbd_is_dying(sc->ure_udev)) 1963 return; 1964 1965 if (status != USBD_NORMAL_COMPLETION) 1966 DPRINTF(("%s: %s uc_idx=%u : %s\n", sc->ure_dev.dv_xname, 1967 __func__, c->uc_idx, usbd_errstr(status))); 1968 1969 s = splnet(); 1970 1971 c->uc_cnt = 0; 1972 c->uc_buflen = 0; 1973 1974 SLIST_INSERT_HEAD(&sc->ure_cdata.ure_tx_free, c, uc_list); 1975 1976 if (status != USBD_NORMAL_COMPLETION) { 1977 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) { 1978 splx(s); 1979 return; 1980 } 1981 1982 ifp->if_oerrors++; 1983 printf("%s: usb error on tx: %s\n", sc->ure_dev.dv_xname, 1984 usbd_errstr(status)); 1985 1986 if (status == USBD_STALLED) 1987 usbd_clear_endpoint_stall_async( 1988 sc->ure_ep[URE_ENDPT_TX]); 1989 splx(s); 1990 return; 1991 } 1992 1993 ifp->if_timer = 0; 1994 if (ifq_is_oactive(&ifp->if_snd)) 1995 ifq_restart(&ifp->if_snd); 1996 splx(s); 1997 } 1998 1999 int 2000 ure_encap_txpkt(struct mbuf *m, char *buf, uint32_t maxlen) 2001 { 2002 struct ure_txpkt txhdr; 2003 uint32_t len = sizeof(txhdr), cflags = 0; 2004 2005 if (len + m->m_pkthdr.len > maxlen) 2006 return (-1); 2007 2008 if ((m->m_pkthdr.csum_flags & 2009 (M_IPV4_CSUM_OUT | M_TCP_CSUM_OUT | M_UDP_CSUM_OUT)) != 0) { 2010 cflags |= URE_TXPKT_IPV4; 2011 if (m->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) 2012 cflags |= URE_TXPKT_TCP; 2013 if (m->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) 2014 cflags |= URE_TXPKT_UDP; 2015 } 2016 2017 #if NVLAN > 0 2018 if (m->m_flags & M_VLANTAG) 2019 cflags |= swap16(m->m_pkthdr.ether_vtag | URE_TXPKT_VLAN_TAG); 2020 #endif 2021 2022 txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS | 2023 URE_TXPKT_TX_LS); 2024 txhdr.ure_vlan = htole32(cflags); 2025 memcpy(buf, &txhdr, len); 2026 2027 m_copydata(m, 0, m->m_pkthdr.len, buf + len); 2028 len += m->m_pkthdr.len; 2029 2030 return (len); 2031 } 2032 2033 int 2034 ure_encap_xfer(struct ifnet *ifp, struct ure_softc *sc, struct ure_chain *c) 2035 { 2036 usbd_status err; 2037 2038 usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_TX], c, c->uc_buf, 2039 c->uc_buflen, USBD_FORCE_SHORT_XFER | USBD_NO_COPY, 10000, 2040 ure_txeof); 2041 2042 err = usbd_transfer(c->uc_xfer); 2043 if (err != USBD_IN_PROGRESS) { 2044 c->uc_cnt = 0; 2045 c->uc_buflen = 0; 2046 ure_stop(sc); 2047 return (EIO); 2048 } 2049 2050 return (0); 2051 } 2052