1 /*- 2 * Copyright (c) 2015 Kevin Lo <kevlo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include "bpfilter.h" 28 29 #include <sys/cdefs.h> 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/sockio.h> 34 #include <sys/rwlock.h> 35 #include <sys/mbuf.h> 36 #include <sys/kernel.h> 37 #include <sys/socket.h> 38 #include <sys/device.h> 39 40 #include <machine/bus.h> 41 42 #include <net/if.h> 43 #include <net/if_media.h> 44 45 #if NBPFILTER > 0 46 #include <net/bpf.h> 47 #endif 48 49 #include <netinet/in.h> 50 #include <netinet/if_ether.h> 51 52 #include <dev/mii/miivar.h> 53 54 #include <dev/usb/usb.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdi_util.h> 57 #include <dev/usb/usbdivar.h> 58 #include <dev/usb/usbdevs.h> 59 60 #include "if_urereg.h" 61 62 #ifdef URE_DEBUG 63 #define DPRINTF(x) do { if (uredebug) printf x; } while (0) 64 #define DPRINTFN(n,x) do { if (uredebug >= (n)) printf x; } while (0) 65 int uredebug = 0; 66 #else 67 #define DPRINTF(x) 68 #define DPRINTFN(n,x) 69 #endif 70 71 72 const struct usb_devno ure_devs[] = { 73 { USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_RTL8152 } 74 }; 75 76 int ure_match(struct device *, void *, void *); 77 void ure_attach(struct device *, struct device *, void *); 78 int ure_detach(struct device *, int); 79 80 struct cfdriver ure_cd = { 81 NULL, "ure", DV_IFNET 82 }; 83 84 const struct cfattach ure_ca = { 85 sizeof(struct ure_softc), ure_match, ure_attach, ure_detach 86 }; 87 88 int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t, 89 void *, int); 90 int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *, 91 int); 92 int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *, 93 int); 94 uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t); 95 uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t); 96 uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t); 97 int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t); 98 int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t); 99 int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t); 100 uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t); 101 void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t); 102 103 void ure_init(void *); 104 void ure_stop(struct ure_softc *); 105 void ure_start(struct ifnet *); 106 void ure_reset(struct ure_softc *); 107 108 void ure_miibus_statchg(struct device *); 109 int ure_miibus_readreg(struct device *, int, int); 110 void ure_miibus_writereg(struct device *, int, int, int); 111 void ure_lock_mii(struct ure_softc *); 112 void ure_unlock_mii(struct ure_softc *); 113 114 int ure_encap(struct ure_softc *, struct mbuf *, int); 115 void ure_rxeof(struct usbd_xfer *, void *, usbd_status); 116 void ure_txeof(struct usbd_xfer *, void *, usbd_status); 117 int ure_rx_list_init(struct ure_softc *); 118 int ure_tx_list_init(struct ure_softc *); 119 struct mbuf * ure_newbuf(void); 120 121 void ure_tick_task(void *); 122 void ure_tick(void *); 123 124 int ure_ifmedia_upd(struct ifnet *); 125 void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *); 126 int ure_ioctl(struct ifnet *, u_long, caddr_t); 127 void ure_rtl8152_init(struct ure_softc *); 128 void ure_disable_teredo(struct ure_softc *); 129 void ure_init_fifo(struct ure_softc *); 130 131 132 133 int 134 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index, 135 void *buf, int len) 136 { 137 usb_device_request_t req; 138 usbd_status err; 139 140 if (usbd_is_dying(sc->ure_udev)) 141 return 0; 142 143 if (rw == URE_CTL_WRITE) 144 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 145 else 146 req.bmRequestType = UT_READ_VENDOR_DEVICE; 147 req.bRequest = UR_SET_ADDRESS; 148 USETW(req.wValue, val); 149 USETW(req.wIndex, index); 150 USETW(req.wLength, len); 151 152 DPRINTFN(5, ("ure_ctl: rw %d, val 0x%04hu, index 0x%04hu, len %d\n", 153 rw, val, index, len)); 154 err = usbd_do_request(sc->ure_udev, &req, buf); 155 if (err) { 156 DPRINTF(("ure_ctl: error %d\n", err)); 157 return -1; 158 } 159 160 return 0; 161 } 162 163 int 164 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 165 void *buf, int len) 166 { 167 168 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len)); 169 } 170 171 int 172 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 173 void *buf, int len) 174 { 175 176 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len)); 177 } 178 179 uint8_t 180 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index) 181 { 182 uint32_t val; 183 uint8_t temp[4]; 184 uint8_t shift; 185 186 shift = (reg & 3) << 3; 187 reg &= ~3; 188 189 ure_read_mem(sc, reg, index, &temp, 4); 190 val = UGETDW(temp); 191 val >>= shift; 192 193 return (val & 0xff); 194 } 195 196 uint16_t 197 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index) 198 { 199 uint32_t val; 200 uint8_t temp[4]; 201 uint8_t shift; 202 203 shift = (reg & 2) << 3; 204 reg &= ~3; 205 206 ure_read_mem(sc, reg, index, &temp, 4); 207 val = UGETDW(temp); 208 val >>= shift; 209 210 return (val & 0xffff); 211 } 212 213 uint32_t 214 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index) 215 { 216 uint8_t temp[4]; 217 218 ure_read_mem(sc, reg, index, &temp, 4); 219 return (UGETDW(temp)); 220 } 221 222 int 223 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 224 { 225 uint16_t byen; 226 uint8_t temp[4]; 227 uint8_t shift; 228 229 byen = URE_BYTE_EN_BYTE; 230 shift = reg & 3; 231 val &= 0xff; 232 233 if (reg & 3) { 234 byen <<= shift; 235 val <<= (shift << 3); 236 reg &= ~3; 237 } 238 239 USETDW(temp, val); 240 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 241 } 242 243 int 244 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 245 { 246 uint16_t byen; 247 uint8_t temp[4]; 248 uint8_t shift; 249 250 byen = URE_BYTE_EN_WORD; 251 shift = reg & 2; 252 val &= 0xffff; 253 254 if (reg & 2) { 255 byen <<= shift; 256 val <<= (shift << 3); 257 reg &= ~3; 258 } 259 260 USETDW(temp, val); 261 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 262 } 263 264 int 265 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 266 { 267 uint8_t temp[4]; 268 269 USETDW(temp, val); 270 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4)); 271 } 272 273 uint16_t 274 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr) 275 { 276 uint16_t reg; 277 278 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 279 reg = (addr & 0x0fff) | 0xb000; 280 281 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA)); 282 } 283 284 void 285 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 286 { 287 uint16_t reg; 288 289 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 290 reg = (addr & 0x0fff) | 0xb000; 291 292 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data); 293 } 294 295 int 296 ure_miibus_readreg(struct device *dev, int phy, int reg) 297 { 298 struct ure_softc *sc = (void *)dev; 299 uint16_t val; 300 301 if (usbd_is_dying(sc->ure_udev)) 302 return 0; 303 304 ure_lock_mii(sc); 305 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2); 306 ure_unlock_mii(sc); 307 308 return val; /* letoh16? */ 309 } 310 311 void 312 ure_miibus_writereg(struct device *dev, int phy, int reg, int val) 313 { 314 struct ure_softc *sc = (void *)dev; 315 316 ure_lock_mii(sc); 317 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val); /* htole16? */ 318 ure_unlock_mii(sc); 319 } 320 321 void 322 ure_miibus_statchg(struct device *dev) 323 { 324 struct ure_softc *sc = (void *)dev; 325 struct mii_data *mii = &sc->ure_mii; 326 struct ifnet *ifp = &sc->ure_ac.ac_if; 327 328 if ((ifp->if_flags & IFF_RUNNING) == 0) 329 return; 330 331 sc->ure_flags &= ~URE_FLAG_LINK; 332 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 333 (IFM_ACTIVE | IFM_AVALID)) { 334 switch (IFM_SUBTYPE(mii->mii_media_active)) { 335 case IFM_10_T: 336 case IFM_100_TX: 337 sc->ure_flags |= URE_FLAG_LINK; 338 break; 339 default: 340 break; 341 } 342 } 343 } 344 345 int 346 ure_ifmedia_upd(struct ifnet *ifp) 347 { 348 struct ure_softc *sc = ifp->if_softc; 349 struct mii_data *mii = &sc->ure_mii; 350 int err; 351 352 sc->ure_flags &= ~URE_FLAG_LINK; 353 if (mii->mii_instance) { 354 struct mii_softc *miisc; 355 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 356 PHY_RESET(miisc); 357 } 358 359 err = mii_mediachg(mii); 360 if (err == ENXIO) 361 return 0; 362 else 363 return err; 364 } 365 366 void 367 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 368 { 369 struct ure_softc *sc = ifp->if_softc; 370 struct mii_data *mii = &sc->ure_mii; 371 372 mii_pollstat(mii); 373 ifmr->ifm_active = mii->mii_media_active; 374 ifmr->ifm_status = mii->mii_media_status; 375 } 376 377 void 378 ure_iff(struct ure_softc *sc) 379 { 380 struct ifnet *ifp = &sc->ure_ac.ac_if; 381 struct ether_multi *enm; 382 struct ether_multistep step; 383 uint32_t hashes[2] = { 0, 0 }; 384 uint32_t hash; 385 uint32_t rxmode; 386 387 if (usbd_is_dying(sc->ure_udev)) 388 return; 389 390 ifp->if_flags &= ~IFF_ALLMULTI; 391 rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA); 392 if (ifp->if_flags & IFF_PROMISC || sc->ure_ac.ac_multirangecnt > 0) { 393 ifp->if_flags |= IFF_ALLMULTI; 394 if (ifp->if_flags & IFF_PROMISC) 395 rxmode |= URE_RCR_AAP; 396 rxmode |= URE_RCR_AM; 397 hashes[0] = hashes[1] = 0xffffffff; 398 } else { 399 ETHER_FIRST_MULTI(step, &sc->ure_ac, enm); 400 while (enm != NULL) { 401 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) 402 >> 26; 403 if (hash < 32) 404 hashes[0] |= (1 << hash); 405 else 406 hashes[1] |= (1 << (hash - 32)); 407 408 ETHER_NEXT_MULTI(step, enm); 409 } 410 411 hash = swap32(hashes[0]); 412 hashes[0] = swap32(hashes[1]); 413 hashes[1] = hash; 414 rxmode |= URE_RCR_AM; 415 } 416 417 ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]); 418 ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]); 419 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 420 } 421 422 void 423 ure_reset(struct ure_softc *sc) 424 { 425 int i; 426 427 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 428 429 for (i = 0; i < URE_TIMEOUT; i++) { 430 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) & 431 URE_CR_RST)) 432 break; 433 usbd_delay_ms(sc->ure_udev, 10); 434 } 435 if (i == URE_TIMEOUT) 436 printf("%s: reset never completed\n", sc->ure_dev.dv_xname); 437 } 438 439 void 440 ure_init(void *xsc) 441 { 442 struct ure_softc *sc = xsc; 443 struct ure_chain *c; 444 struct ifnet *ifp = &sc->ure_ac.ac_if; 445 uint32_t rxmode; 446 usbd_status err; 447 int s, i; 448 449 s = splnet(); 450 451 /* Cancel pending I/O. */ 452 ure_stop(sc); 453 454 ure_reset(sc); 455 456 if (ure_rx_list_init(sc) == ENOBUFS) { 457 printf("%s: rx list init failed\n", sc->ure_dev.dv_xname); 458 splx(s); 459 return; 460 } 461 462 if (ure_tx_list_init(sc) == ENOBUFS) { 463 printf("%s: tx list init failed\n", sc->ure_dev.dv_xname); 464 splx(s); 465 return; 466 } 467 468 /* Set MAC address. */ 469 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 470 sc->ure_ac.ac_enaddr, 8); 471 472 /* Reset the packet filter. */ 473 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, 474 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) & 475 ~URE_FMC_FCR_MCU_EN); 476 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, 477 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) | 478 URE_FMC_FCR_MCU_EN); 479 480 /* Enable transmit and receive. */ 481 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 482 ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | 483 URE_CR_TE); 484 485 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 486 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & 487 ~URE_RXDY_GATED_EN); 488 489 /* Set Rx mode. */ 490 rxmode = URE_RCR_APM; 491 492 /* If we want promiscuous mode, set the allframes bit. */ 493 if (ifp->if_flags & IFF_PROMISC) 494 rxmode |= URE_RCR_AAP; 495 496 if (ifp->if_flags & IFF_BROADCAST) 497 rxmode |= URE_RCR_AB; 498 499 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 500 501 /* Load the multicast filter. */ 502 ure_iff(sc); 503 504 /* Open RX and TX pipes. */ 505 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_RX], 506 USBD_EXCLUSIVE_USE, &sc->ure_ep[URE_ENDPT_RX]); 507 if (err) { 508 printf("%s: open rx pipe failed: %s\n", 509 sc->ure_dev.dv_xname, usbd_errstr(err)); 510 splx(s); 511 return; 512 } 513 514 err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_TX], 515 USBD_EXCLUSIVE_USE, &sc->ure_ep[URE_ENDPT_TX]); 516 if (err) { 517 printf("%s: open tx pipe failed: %s\n", 518 sc->ure_dev.dv_xname, usbd_errstr(err)); 519 splx(s); 520 return; 521 } 522 523 /* Start up the receive pipe. */ 524 for (i = 0; i < URE_RX_LIST_CNT; i++) { 525 c = &sc->ure_cdata.rx_chain[i]; 526 usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_RX], 527 c, c->uc_buf, sc->ure_bufsz, 528 USBD_SHORT_XFER_OK | USBD_NO_COPY, 529 USBD_NO_TIMEOUT, ure_rxeof); 530 usbd_transfer(c->uc_xfer); 531 } 532 533 /* Indicate we are up and running. */ 534 ifp->if_flags |= IFF_RUNNING; 535 ifq_clr_oactive(&ifp->if_snd); 536 537 timeout_add_sec(&sc->ure_stat_ch, 1); 538 539 splx(s); 540 } 541 542 void 543 ure_start(struct ifnet *ifp) 544 { 545 struct ure_softc *sc = ifp->if_softc; 546 struct mbuf *m_head = NULL; 547 548 if ((sc->ure_flags & URE_FLAG_LINK) == 0 || 549 ifq_is_oactive(&ifp->if_snd)) { 550 return; 551 } 552 553 m_head = ifq_deq_begin(&ifp->if_snd); 554 if (m_head == NULL) { 555 return; 556 } 557 558 if (ure_encap(sc, m_head, 0)) { 559 ifq_deq_rollback(&ifp->if_snd, m_head); 560 ifq_set_oactive(&ifp->if_snd); 561 return; 562 } 563 ifq_deq_commit(&ifp->if_snd, m_head); 564 565 #if NBPFILTER > 0 566 if (ifp->if_bpf) 567 bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 568 #endif 569 ifq_set_oactive(&ifp->if_snd); 570 } 571 572 void 573 ure_tick(void *xsc) 574 { 575 struct ure_softc *sc = xsc; 576 577 if (sc == NULL) 578 return; 579 580 if (usbd_is_dying(sc->ure_udev)) 581 return; 582 583 usb_add_task(sc->ure_udev, &sc->ure_tick_task); 584 } 585 586 void 587 ure_stop(struct ure_softc *sc) 588 { 589 usbd_status err; 590 struct ifnet *ifp; 591 int i; 592 593 ure_reset(sc); 594 595 ifp = &sc->ure_ac.ac_if; 596 ifp->if_timer = 0; 597 ifp->if_flags &= ~IFF_RUNNING; 598 ifq_clr_oactive(&ifp->if_snd); 599 600 timeout_del(&sc->ure_stat_ch); 601 602 if (sc->ure_ep[URE_ENDPT_RX] != NULL) { 603 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_RX]); 604 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_RX]); 605 if (err) { 606 printf("%s: close rx pipe failed: %s\n", 607 sc->ure_dev.dv_xname, usbd_errstr(err)); 608 } 609 sc->ure_ep[URE_ENDPT_RX] = NULL; 610 } 611 612 if (sc->ure_ep[URE_ENDPT_TX] != NULL) { 613 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_TX]); 614 err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_TX]); 615 if (err) { 616 printf("%s: close tx pipe failed: %s\n", 617 sc->ure_dev.dv_xname, usbd_errstr(err)); 618 } 619 sc->ure_ep[URE_ENDPT_TX] = NULL; 620 } 621 622 for (i = 0; i < URE_RX_LIST_CNT; i++) { 623 if (sc->ure_cdata.rx_chain[i].uc_mbuf != NULL) { 624 m_freem(sc->ure_cdata.rx_chain[i].uc_mbuf); 625 sc->ure_cdata.rx_chain[i].uc_mbuf = NULL; 626 } 627 if (sc->ure_cdata.rx_chain[i].uc_xfer != NULL) { 628 usbd_free_xfer(sc->ure_cdata.rx_chain[i].uc_xfer); 629 sc->ure_cdata.rx_chain[i].uc_xfer = NULL; 630 } 631 } 632 633 for (i = 0; i < URE_TX_LIST_CNT; i++) { 634 if (sc->ure_cdata.tx_chain[i].uc_mbuf != NULL) { 635 m_freem(sc->ure_cdata.tx_chain[i].uc_mbuf); 636 sc->ure_cdata.tx_chain[i].uc_mbuf = NULL; 637 } 638 if (sc->ure_cdata.tx_chain[i].uc_xfer != NULL) { 639 usbd_free_xfer(sc->ure_cdata.tx_chain[i].uc_xfer); 640 sc->ure_cdata.tx_chain[i].uc_xfer = NULL; 641 } 642 } 643 } 644 645 void 646 ure_rtl8152_init(struct ure_softc *sc) 647 { 648 uint32_t pwrctrl; 649 650 /* Disable ALDPS. */ 651 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 652 URE_DIS_SDSAVE); 653 usbd_delay_ms(sc->ure_udev, 20); 654 655 if (sc->ure_chip & URE_CHIP_VER_4C00) { 656 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 657 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 658 ~URE_LED_MODE_MASK); 659 } 660 661 ure_write_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, 662 ure_read_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & 663 ~URE_POWER_CUT); 664 ure_write_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 665 ure_read_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & 666 ~URE_RESUME_INDICATE); 667 668 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 669 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 670 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 671 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 672 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 673 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 674 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 675 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 676 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 677 URE_SPDWN_LINKCHG_MSK); 678 679 /* Disable Rx aggregation. */ 680 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 681 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) | 682 URE_RX_AGG_DISABLE); 683 684 /* Disable ALDPS. */ 685 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 686 URE_DIS_SDSAVE); 687 usbd_delay_ms(sc->ure_udev, 20); 688 689 ure_init_fifo(sc); 690 691 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 692 URE_TX_AGG_MAX_THRESHOLD); 693 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 694 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 695 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 696 } 697 698 void 699 ure_disable_teredo(struct ure_softc *sc) 700 { 701 ure_write_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 702 ure_read_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & 703 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 704 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, 705 URE_WDT6_SET_MODE); 706 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 707 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 708 } 709 710 void 711 ure_init_fifo(struct ure_softc *sc) 712 { 713 uint32_t rx_fifo1, rx_fifo2; 714 int i; 715 716 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 717 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | 718 URE_RXDY_GATED_EN); 719 720 ure_disable_teredo(sc); 721 722 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, 723 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA) & 724 ~URE_RCR_ACPT_ALL); 725 726 ure_reset(sc); 727 728 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 729 730 ure_write_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, 731 ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 732 ~URE_NOW_IS_OOB); 733 734 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 735 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & 736 ~URE_MCU_BORW_EN); 737 for (i = 0; i < URE_TIMEOUT; i++) { 738 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 739 URE_LINK_LIST_READY) 740 break; 741 usbd_delay_ms(sc->ure_udev, 10); 742 } 743 if (i == URE_TIMEOUT) 744 printf("%s timeout waiting for OOB control\n", 745 sc->ure_dev.dv_xname); 746 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 747 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | 748 URE_RE_INIT_LL); 749 for (i = 0; i < URE_TIMEOUT; i++) { 750 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 751 URE_LINK_LIST_READY) 752 break; 753 usbd_delay_ms(sc->ure_udev, 10); 754 } 755 if (i == URE_TIMEOUT) 756 printf("%s: timeout waiting for OOB control\n", 757 sc->ure_dev.dv_xname); 758 759 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 760 ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & 761 ~URE_CPCR_RX_VLAN); 762 ure_write_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 763 ure_read_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | 764 URE_TCR0_AUTO_FIFO); 765 766 /* Configure Rx FIFO threshold and coalescing. */ 767 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 768 URE_RXFIFO_THR1_NORMAL); 769 if (sc->ure_udev->speed == USB_SPEED_FULL) { 770 rx_fifo1 = URE_RXFIFO_THR2_FULL; 771 rx_fifo2 = URE_RXFIFO_THR3_FULL; 772 } else { 773 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 774 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 775 } 776 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 777 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 778 779 /* Configure Tx FIFO threshold. */ 780 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 781 URE_TXFIFO_THR_NORMAL); 782 } 783 784 int 785 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 786 { 787 struct ure_softc *sc = ifp->if_softc;; 788 struct ifreq *ifr = (struct ifreq *)data; 789 int s, error = 0; 790 791 s = splnet(); 792 793 switch (cmd) { 794 case SIOCSIFADDR: 795 ifp->if_flags |= IFF_UP; 796 if (!(ifp->if_flags & IFF_RUNNING)) 797 ure_init(sc); 798 break; 799 800 case SIOCSIFFLAGS: 801 if (ifp->if_flags & IFF_UP) { 802 if (ifp->if_flags & IFF_RUNNING) 803 error = ENETRESET; 804 else 805 ure_init(sc); 806 } else { 807 if (ifp->if_flags & IFF_RUNNING) 808 ure_stop(sc); 809 } 810 break; 811 812 case SIOCGIFMEDIA: 813 case SIOCSIFMEDIA: 814 error = ifmedia_ioctl(ifp, ifr, &sc->ure_mii.mii_media, cmd); 815 break; 816 817 default: 818 error = ether_ioctl(ifp, &sc->ure_ac, cmd, data); 819 } 820 821 if (error == ENETRESET) { 822 if (ifp->if_flags & IFF_RUNNING) 823 ure_iff(sc); 824 error = 0; 825 } 826 827 splx(s); 828 829 return (error); 830 } 831 832 int 833 ure_match(struct device *parent, void *match, void *aux) 834 { 835 struct usb_attach_arg *uaa = aux; 836 837 /* 838 if (uaa->configno != URE_CONFIG_IDX) 839 return UMATCH_NONE; 840 if (uaa->ifaceno != URE_IFACE_IDX) 841 return UMATCH_NONE; 842 */ 843 if (uaa->iface == NULL || uaa->configno != 1) 844 return UMATCH_NONE; 845 846 return (usb_lookup(ure_devs, uaa->vendor, uaa->product) != NULL ? 847 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE); 848 } 849 850 void 851 ure_attach(struct device *parent, struct device *self, void *aux) 852 { 853 struct ure_softc *sc = (struct ure_softc *)self; 854 struct usb_attach_arg *uaa = aux; 855 usb_interface_descriptor_t *id; 856 usb_endpoint_descriptor_t *ed; 857 struct mii_data *mii; 858 u_char eaddr[8]; /* 4byte padded */ 859 struct ifnet *ifp; 860 int i, s; 861 uint16_t ver; 862 863 sc->ure_udev = uaa->device; 864 sc->ure_iface = uaa->iface; 865 866 usb_init_task(&sc->ure_tick_task, ure_tick_task, sc, 867 USB_TASK_TYPE_GENERIC); 868 rw_init(&sc->ure_mii_lock, "uremii"); 869 usb_init_task(&sc->ure_stop_task, (void (*)(void *))ure_stop, sc, 870 USB_TASK_TYPE_GENERIC); 871 872 id = usbd_get_interface_descriptor(sc->ure_iface); 873 874 sc->ure_bufsz = 16 * 1024; 875 876 for (i = 0; i < id->bNumEndpoints; i++) { 877 ed = usbd_interface2endpoint_descriptor(sc->ure_iface, i); 878 if (!ed) { 879 printf("%s: couldn't get ep %d\n", 880 sc->ure_dev.dv_xname, i); 881 return; 882 } 883 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN && 884 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 885 sc->ure_ed[URE_ENDPT_RX] = ed->bEndpointAddress; 886 } else if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 887 UE_GET_XFERTYPE(ed->bmAttributes) == UE_BULK) { 888 sc->ure_ed[URE_ENDPT_TX] = ed->bEndpointAddress; 889 } 890 } 891 892 s = splnet(); 893 894 sc->ure_phyno = 0; 895 printf("%s: ", sc->ure_dev.dv_xname); 896 897 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 898 switch (ver) { 899 case 0x4c00: 900 sc->ure_chip |= URE_CHIP_VER_4C00; 901 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA, eaddr, 902 sizeof(eaddr)); 903 printf("ver 4c00"); 904 break; 905 case 0x4c10: 906 sc->ure_chip |= URE_CHIP_VER_4C10; 907 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, eaddr, 908 sizeof(eaddr)); 909 printf("ver 4c01"); 910 break; 911 default: 912 printf(", unknown ver %02x", ver); 913 /* fake addr? or just fail? */ 914 break; 915 } 916 917 printf(", address %s\n", ether_sprintf(eaddr)); 918 919 bcopy(eaddr, (char *)&sc->ure_ac.ac_enaddr, ETHER_ADDR_LEN); 920 921 ure_rtl8152_init(sc); 922 923 ifp = &sc->ure_ac.ac_if; 924 ifp->if_softc = sc; 925 strlcpy(ifp->if_xname, sc->ure_dev.dv_xname, IFNAMSIZ); 926 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 927 ifp->if_ioctl = ure_ioctl; 928 ifp->if_start = ure_start; 929 ifp->if_capabilities = 0; 930 931 mii = &sc->ure_mii; 932 mii->mii_ifp = ifp; 933 mii->mii_readreg = ure_miibus_readreg; 934 mii->mii_writereg = ure_miibus_writereg; 935 mii->mii_statchg = ure_miibus_statchg; 936 mii->mii_flags = MIIF_AUTOTSLEEP; 937 938 ifmedia_init(&mii->mii_media, 0, ure_ifmedia_upd, ure_ifmedia_sts); 939 mii_attach(self, mii, 0xffffffff, sc->ure_phyno, MII_OFFSET_ANY, 0); 940 941 if (LIST_FIRST(&mii->mii_phys) == NULL) { 942 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 943 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 944 } else 945 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 946 947 if_attach(ifp); 948 ether_ifattach(ifp); 949 950 timeout_set(&sc->ure_stat_ch, ure_tick, sc); 951 952 splx(s); 953 } 954 955 int 956 ure_detach(struct device *self, int flags) 957 { 958 struct ure_softc *sc = (struct ure_softc *)self; 959 struct ifnet *ifp = &sc->ure_ac.ac_if; 960 int s; 961 962 if (timeout_initialized(&sc->ure_stat_ch)) 963 timeout_del(&sc->ure_stat_ch); 964 965 if (sc->ure_ep[URE_ENDPT_TX] != NULL) 966 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_TX]); 967 if (sc->ure_ep[URE_ENDPT_RX] != NULL) 968 usbd_abort_pipe(sc->ure_ep[URE_ENDPT_RX]); 969 970 usb_rem_task(sc->ure_udev, &sc->ure_tick_task); 971 usb_rem_task(sc->ure_udev, &sc->ure_stop_task); 972 973 s = splusb(); 974 975 if (--sc->ure_refcnt >= 0) { 976 usb_detach_wait(&sc->ure_dev); 977 } 978 979 if (ifp->if_flags & IFF_RUNNING) 980 ure_stop(sc); 981 982 mii_detach(&sc->ure_mii, MII_PHY_ANY, MII_OFFSET_ANY); 983 ifmedia_delete_instance(&sc->ure_mii.mii_media, IFM_INST_ANY); 984 if (ifp->if_softc != NULL) { 985 ether_ifdetach(ifp); 986 if_detach(ifp); 987 } 988 989 splx(s); 990 991 return 0; 992 } 993 994 void 995 ure_tick_task(void *xsc) 996 { 997 int s; 998 struct ure_softc *sc = xsc; 999 struct mii_data *mii; 1000 1001 if (sc == NULL) 1002 return; 1003 1004 if (usbd_is_dying(sc->ure_udev)) 1005 return; 1006 mii = &sc->ure_mii; 1007 1008 s = splnet(); 1009 mii_tick(mii); 1010 if ((sc->ure_flags & URE_FLAG_LINK) == 0) 1011 ure_miibus_statchg(&sc->ure_dev); 1012 timeout_add_sec(&sc->ure_stat_ch, 1); 1013 splx(s); 1014 } 1015 1016 void 1017 ure_lock_mii(struct ure_softc *sc) 1018 { 1019 sc->ure_refcnt++; 1020 rw_enter_write(&sc->ure_mii_lock); 1021 } 1022 1023 void 1024 ure_unlock_mii(struct ure_softc *sc) 1025 { 1026 rw_exit_write(&sc->ure_mii_lock); 1027 if (--sc->ure_refcnt < 0) 1028 usb_detach_wakeup(&sc->ure_dev); 1029 } 1030 1031 void 1032 ure_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1033 { 1034 struct ure_chain *c = (struct ure_chain *)priv; 1035 struct ure_softc *sc = c->uc_sc; 1036 struct ifnet *ifp = &sc->ure_ac.ac_if; 1037 u_char *buf = c->uc_buf; 1038 uint32_t total_len; 1039 uint16_t pktlen = 0; 1040 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 1041 struct mbuf *m; 1042 int s; 1043 struct ure_rxpkt rxhdr; 1044 1045 if (usbd_is_dying(sc->ure_udev)) 1046 return; 1047 1048 if (!(ifp->if_flags & IFF_RUNNING)) 1049 return; 1050 1051 if (status != USBD_NORMAL_COMPLETION) { 1052 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) 1053 return; 1054 if (usbd_ratecheck(&sc->ure_rx_notice)) { 1055 printf("%s: usb errors on rx: %s\n", 1056 sc->ure_dev.dv_xname, usbd_errstr(status)); 1057 } 1058 if (status == USBD_STALLED) 1059 usbd_clear_endpoint_stall_async(sc->ure_ep[URE_ENDPT_RX]); 1060 goto done; 1061 } 1062 1063 usbd_get_xfer_status(xfer, NULL, NULL, &total_len, NULL); 1064 DPRINTFN(3, ("received %d bytes\n", total_len)); 1065 1066 do { 1067 if (total_len < sizeof(rxhdr)) { 1068 DPRINTF(("too few bytes left for a packet header\n")); 1069 ifp->if_ierrors++; 1070 goto done; 1071 } 1072 1073 buf += pktlen; 1074 1075 memcpy(&rxhdr, buf, sizeof(rxhdr)); 1076 total_len -= sizeof(rxhdr); 1077 1078 pktlen = lemtoh32(&rxhdr.ure_pktlen) & URE_RXPKT_LEN_MASK; 1079 DPRINTFN(4, ("next packet is %d bytes\n", pktlen)); 1080 if (pktlen > total_len) { 1081 DPRINTF(("not enough bytes left for next packet\n")); 1082 ifp->if_ierrors++; 1083 goto done; 1084 } 1085 1086 total_len -= pktlen; 1087 buf += sizeof(rxhdr); 1088 1089 m = ure_newbuf(); 1090 if (m == NULL) { 1091 DPRINTF(("unable to allocate mbuf for next packet\n")); 1092 ifp->if_ierrors++; 1093 goto done; 1094 } 1095 1096 m->m_pkthdr.len = m->m_len = pktlen; 1097 m_adj(m, ETHER_ALIGN); 1098 1099 memcpy(mtod(m, char *), buf, pktlen); 1100 ml_enqueue(&ml, m); 1101 } while (total_len > 0); 1102 1103 done: 1104 s = splnet(); 1105 if_input(ifp, &ml); 1106 splx(s); 1107 memset(c->uc_buf, 0, sc->ure_bufsz); 1108 1109 usbd_setup_xfer(xfer, sc->ure_ep[URE_ENDPT_RX], c, c->uc_buf, 1110 sc->ure_bufsz, USBD_SHORT_XFER_OK | USBD_NO_COPY, 1111 USBD_NO_TIMEOUT, ure_rxeof); 1112 usbd_transfer(xfer); 1113 } 1114 1115 1116 void 1117 ure_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 1118 { 1119 struct ure_softc *sc; 1120 struct ure_chain *c; 1121 struct ifnet *ifp; 1122 int s; 1123 1124 c = priv; 1125 sc = c->uc_sc; 1126 ifp = &sc->ure_ac.ac_if; 1127 1128 if (usbd_is_dying(sc->ure_udev)) 1129 return; 1130 1131 DPRINTFN(2, ("tx completion\n")); 1132 1133 s = splnet(); 1134 1135 if (status != USBD_NORMAL_COMPLETION) { 1136 if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) { 1137 splx(s); 1138 return; 1139 } 1140 ifp->if_oerrors++; 1141 printf("%s: usb error on tx: %s\n", sc->ure_dev.dv_xname, 1142 usbd_errstr(status)); 1143 if (status == USBD_STALLED) 1144 usbd_clear_endpoint_stall_async(sc->ure_ep[URE_ENDPT_TX]); 1145 splx(s); 1146 return; 1147 } 1148 1149 ifp->if_timer = 0; 1150 ifq_clr_oactive(&ifp->if_snd); 1151 1152 m_freem(c->uc_mbuf); 1153 c->uc_mbuf = NULL; 1154 1155 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 1156 ure_start(ifp); 1157 1158 ifp->if_opackets++; 1159 splx(s); 1160 1161 } 1162 1163 int 1164 ure_tx_list_init(struct ure_softc *sc) 1165 { 1166 struct ure_cdata *cd; 1167 struct ure_chain *c; 1168 int i; 1169 1170 cd = &sc->ure_cdata; 1171 for (i = 0; i < URE_TX_LIST_CNT; i++) { 1172 c = &cd->tx_chain[i]; 1173 c->uc_sc = sc; 1174 c->uc_idx = i; 1175 c->uc_mbuf = NULL; 1176 if (c->uc_xfer == NULL) { 1177 c->uc_xfer = usbd_alloc_xfer(sc->ure_udev); 1178 if (c->uc_xfer == NULL) 1179 return ENOBUFS; 1180 c->uc_buf = usbd_alloc_buffer(c->uc_xfer, 1181 sc->ure_bufsz); 1182 if (c->uc_buf == NULL) { 1183 usbd_free_xfer(c->uc_xfer); 1184 return ENOBUFS; 1185 } 1186 } 1187 } 1188 1189 return 0; 1190 } 1191 1192 int 1193 ure_rx_list_init(struct ure_softc *sc) 1194 { 1195 struct ure_cdata *cd; 1196 struct ure_chain *c; 1197 int i; 1198 1199 cd = &sc->ure_cdata; 1200 for (i = 0; i < URE_RX_LIST_CNT; i++) { 1201 c = &cd->rx_chain[i]; 1202 c->uc_sc = sc; 1203 c->uc_idx = i; 1204 c->uc_mbuf = NULL; 1205 if (c->uc_xfer == NULL) { 1206 c->uc_xfer = usbd_alloc_xfer(sc->ure_udev); 1207 if (c->uc_xfer == NULL) 1208 return ENOBUFS; 1209 c->uc_buf = usbd_alloc_buffer(c->uc_xfer, 1210 sc->ure_bufsz); 1211 if (c->uc_buf == NULL) { 1212 usbd_free_xfer(c->uc_xfer); 1213 return ENOBUFS; 1214 } 1215 } 1216 } 1217 1218 return 0; 1219 } 1220 1221 struct mbuf * 1222 ure_newbuf(void) 1223 { 1224 struct mbuf *m; 1225 1226 MGETHDR(m, M_DONTWAIT, MT_DATA); 1227 if (m == NULL) 1228 return NULL; 1229 1230 MCLGET(m, M_DONTWAIT); 1231 if (!(m->m_flags & M_EXT)) { 1232 m_freem(m); 1233 return NULL; 1234 } 1235 1236 return m; 1237 } 1238 1239 int 1240 ure_encap(struct ure_softc *sc, struct mbuf *m, int idx) 1241 { 1242 struct ure_chain *c; 1243 usbd_status err; 1244 struct ure_txpkt txhdr; 1245 uint32_t frm_len = 0; 1246 u_char *buf; 1247 1248 c = &sc->ure_cdata.tx_chain[idx]; 1249 buf = c->uc_buf; 1250 1251 /* header */ 1252 htolem32(&txhdr.ure_pktlen, m->m_pkthdr.len | URE_TXPKT_TX_FS | 1253 URE_TXPKT_TX_LS); 1254 txhdr.ure_rsvd0 = 0; 1255 memcpy(buf, &txhdr, sizeof(txhdr)); 1256 buf += sizeof(txhdr); 1257 frm_len = sizeof(txhdr); 1258 1259 /* packet */ 1260 m_copydata(m, 0, m->m_pkthdr.len, buf); 1261 frm_len += m->m_pkthdr.len; 1262 1263 c->uc_mbuf = m; 1264 1265 DPRINTFN(2, ("tx %d bytes\n", frm_len)); 1266 usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_TX], c, c->uc_buf, 1267 frm_len, USBD_FORCE_SHORT_XFER | USBD_NO_COPY, 10000, ure_txeof); 1268 1269 err = usbd_transfer(c->uc_xfer); 1270 if (err != USBD_IN_PROGRESS) { 1271 ure_stop(sc); 1272 return EIO; 1273 } 1274 1275 sc->ure_cdata.tx_cnt++; 1276 return 0; 1277 } 1278