1 /* $OpenBSD: if_run.c,v 1.116 2016/04/13 11:03:37 mpi Exp $ */ 2 3 /*- 4 * Copyright (c) 2008-2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2013-2014 Kevin Lo 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Ralink Technology RT2700U/RT2800U/RT3000U/RT3900E chipset driver. 22 * http://www.ralinktech.com/ 23 */ 24 25 #include "bpfilter.h" 26 27 #include <sys/param.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/timeout.h> 34 #include <sys/conf.h> 35 #include <sys/device.h> 36 #include <sys/endian.h> 37 38 #include <machine/intr.h> 39 40 #if NBPFILTER > 0 41 #include <net/bpf.h> 42 #endif 43 #include <net/if.h> 44 #include <net/if_dl.h> 45 #include <net/if_media.h> 46 47 #include <netinet/in.h> 48 #include <netinet/if_ether.h> 49 50 #include <net80211/ieee80211_var.h> 51 #include <net80211/ieee80211_amrr.h> 52 #include <net80211/ieee80211_radiotap.h> 53 54 #include <dev/usb/usb.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdi_util.h> 57 #include <dev/usb/usbdevs.h> 58 59 #include <dev/ic/rt2860reg.h> /* shared with ral(4) */ 60 #include <dev/usb/if_runvar.h> 61 62 #ifdef RUN_DEBUG 63 #define DPRINTF(x) do { if (run_debug) printf x; } while (0) 64 #define DPRINTFN(n, x) do { if (run_debug >= (n)) printf x; } while (0) 65 int run_debug = 0; 66 #else 67 #define DPRINTF(x) 68 #define DPRINTFN(n, x) 69 #endif 70 71 #define USB_ID(v, p) { USB_VENDOR_##v, USB_PRODUCT_##v##_##p } 72 static const struct usb_devno run_devs[] = { 73 USB_ID(ABOCOM, RT2770), 74 USB_ID(ABOCOM, RT2870), 75 USB_ID(ABOCOM, RT3070), 76 USB_ID(ABOCOM, RT3071), 77 USB_ID(ABOCOM, RT3072), 78 USB_ID(ABOCOM2, RT2870_1), 79 USB_ID(ACCTON, RT2770), 80 USB_ID(ACCTON, RT2870_1), 81 USB_ID(ACCTON, RT2870_2), 82 USB_ID(ACCTON, RT2870_3), 83 USB_ID(ACCTON, RT2870_4), 84 USB_ID(ACCTON, RT2870_5), 85 USB_ID(ACCTON, RT3070), 86 USB_ID(ACCTON, RT3070_1), 87 USB_ID(ACCTON, RT3070_2), 88 USB_ID(ACCTON, RT3070_3), 89 USB_ID(ACCTON, RT3070_4), 90 USB_ID(ACCTON, RT3070_5), 91 USB_ID(ACCTON, RT3070_6), 92 USB_ID(AIRTIES, RT3070), 93 USB_ID(AIRTIES, RT3070_2), 94 USB_ID(ALLWIN, RT2070), 95 USB_ID(ALLWIN, RT2770), 96 USB_ID(ALLWIN, RT2870), 97 USB_ID(ALLWIN, RT3070), 98 USB_ID(ALLWIN, RT3071), 99 USB_ID(ALLWIN, RT3072), 100 USB_ID(ALLWIN, RT3572), 101 USB_ID(AMIGO, RT2870_1), 102 USB_ID(AMIGO, RT2870_2), 103 USB_ID(AMIT, CGWLUSB2GNR), 104 USB_ID(AMIT, RT2870_1), 105 USB_ID(AMIT2, RT2870), 106 USB_ID(ASUS, RT2870_1), 107 USB_ID(ASUS, RT2870_2), 108 USB_ID(ASUS, RT2870_3), 109 USB_ID(ASUS, RT2870_4), 110 USB_ID(ASUS, RT2870_5), 111 USB_ID(ASUS, RT3070_1), 112 USB_ID(ASUS, USBN13), 113 USB_ID(ASUS, USBN53), 114 USB_ID(ASUS, USBN66), 115 USB_ID(ASUS2, USBN11), 116 USB_ID(AZUREWAVE, RT2870_1), 117 USB_ID(AZUREWAVE, RT2870_2), 118 USB_ID(AZUREWAVE, RT3070_1), 119 USB_ID(AZUREWAVE, RT3070_2), 120 USB_ID(AZUREWAVE, RT3070_3), 121 USB_ID(AZUREWAVE, RT3070_4), 122 USB_ID(AZUREWAVE, RT3070_5), 123 USB_ID(BELKIN, F9L1103), 124 USB_ID(BELKIN, F5D8053V3), 125 USB_ID(BELKIN, F5D8055), 126 USB_ID(BELKIN, F5D8055V2), 127 USB_ID(BELKIN, F6D4050V1), 128 USB_ID(BELKIN, F6D4050V2), 129 USB_ID(BELKIN, F7D1101V2), 130 USB_ID(BELKIN, RT2870_1), 131 USB_ID(BELKIN, RT2870_2), 132 USB_ID(BEWAN, RT3070), 133 USB_ID(CISCOLINKSYS, AE1000), 134 USB_ID(CISCOLINKSYS, AM10), 135 USB_ID(CISCOLINKSYS2, RT3070), 136 USB_ID(CISCOLINKSYS3, RT3070), 137 USB_ID(CONCEPTRONIC2, RT2870_1), 138 USB_ID(CONCEPTRONIC2, RT2870_2), 139 USB_ID(CONCEPTRONIC2, RT2870_3), 140 USB_ID(CONCEPTRONIC2, RT2870_4), 141 USB_ID(CONCEPTRONIC2, RT2870_5), 142 USB_ID(CONCEPTRONIC2, RT2870_6), 143 USB_ID(CONCEPTRONIC2, RT2870_7), 144 USB_ID(CONCEPTRONIC2, RT2870_8), 145 USB_ID(CONCEPTRONIC2, RT3070_1), 146 USB_ID(CONCEPTRONIC2, RT3070_2), 147 USB_ID(CONCEPTRONIC2, RT3070_3), 148 USB_ID(CONCEPTRONIC2, VIGORN61), 149 USB_ID(COREGA, CGWLUSB300GNM), 150 USB_ID(COREGA, RT2870_1), 151 USB_ID(COREGA, RT2870_2), 152 USB_ID(COREGA, RT2870_3), 153 USB_ID(COREGA, RT3070), 154 USB_ID(CYBERTAN, RT2870), 155 USB_ID(DLINK, DWA127), 156 USB_ID(DLINK, DWA140B3), 157 USB_ID(DLINK, DWA160B2), 158 USB_ID(DLINK, DWA162), 159 USB_ID(DLINK, RT2870), 160 USB_ID(DLINK, RT3072), 161 USB_ID(DLINK2, DWA130), 162 USB_ID(DLINK2, RT2870_1), 163 USB_ID(DLINK2, RT2870_2), 164 USB_ID(DLINK2, RT3070_1), 165 USB_ID(DLINK2, RT3070_2), 166 USB_ID(DLINK2, RT3070_3), 167 USB_ID(DLINK2, RT3070_4), 168 USB_ID(DLINK2, RT3070_5), 169 USB_ID(DLINK2, RT3072), 170 USB_ID(DLINK2, RT3072_1), 171 USB_ID(DVICO, RT3070), 172 USB_ID(EDIMAX, EW7717), 173 USB_ID(EDIMAX, EW7718), 174 USB_ID(EDIMAX, EW7722UTN), 175 USB_ID(EDIMAX, RT2870_1), 176 USB_ID(ENCORE, RT3070_1), 177 USB_ID(ENCORE, RT3070_2), 178 USB_ID(ENCORE, RT3070_3), 179 USB_ID(GIGABYTE, GNWB31N), 180 USB_ID(GIGABYTE, GNWB32L), 181 USB_ID(GIGABYTE, RT2870_1), 182 USB_ID(GIGASET, RT3070_1), 183 USB_ID(GIGASET, RT3070_2), 184 USB_ID(GUILLEMOT, HWNU300), 185 USB_ID(HAWKING, HWDN2), 186 USB_ID(HAWKING, HWUN2), 187 USB_ID(HAWKING, RT2870_1), 188 USB_ID(HAWKING, RT2870_2), 189 USB_ID(HAWKING, RT2870_3), 190 USB_ID(HAWKING, RT2870_4), 191 USB_ID(HAWKING, RT2870_5), 192 USB_ID(IODATA, RT3072_1), 193 USB_ID(IODATA, RT3072_2), 194 USB_ID(IODATA, RT3072_3), 195 USB_ID(IODATA, RT3072_4), 196 USB_ID(LINKSYS4, RT3070), 197 USB_ID(LINKSYS4, WUSB100), 198 USB_ID(LINKSYS4, WUSB54GCV3), 199 USB_ID(LINKSYS4, WUSB600N), 200 USB_ID(LINKSYS4, WUSB600NV2), 201 USB_ID(LOGITEC, LANW150NU2), 202 USB_ID(LOGITEC, LANW300NU2), 203 USB_ID(LOGITEC, LANW300NU2S), 204 USB_ID(LOGITEC, RT2870_1), 205 USB_ID(LOGITEC, RT2870_2), 206 USB_ID(LOGITEC, RT2870_3), 207 USB_ID(MELCO, RT2870_1), 208 USB_ID(MELCO, RT2870_2), 209 USB_ID(MELCO, WLIUCAG300N), 210 USB_ID(MELCO, WLIUCG300N), 211 USB_ID(MELCO, WLIUCG301N), 212 USB_ID(MELCO, WLIUCGN), 213 USB_ID(MELCO, WLIUCGNHP), 214 USB_ID(MELCO, WLIUCGNM), 215 USB_ID(MELCO, WLIUCGNM2), 216 USB_ID(MOTOROLA4, RT2770), 217 USB_ID(MOTOROLA4, RT3070), 218 USB_ID(MSI, RT3070_1), 219 USB_ID(MSI, RT3070_2), 220 USB_ID(MSI, RT3070_3), 221 USB_ID(MSI, RT3070_4), 222 USB_ID(MSI, RT3070_5), 223 USB_ID(MSI, RT3070_6), 224 USB_ID(MSI, RT3070_7), 225 USB_ID(MSI, RT3070_8), 226 USB_ID(MSI, RT3070_9), 227 USB_ID(MSI, RT3070_10), 228 USB_ID(MSI, RT3070_11), 229 USB_ID(MSI, RT3070_12), 230 USB_ID(MSI, RT3070_13), 231 USB_ID(MSI, RT3070_14), 232 USB_ID(MSI, RT3070_15), 233 USB_ID(OVISLINK, RT3071), 234 USB_ID(OVISLINK, RT3072), 235 USB_ID(PARA, RT3070), 236 USB_ID(PEGATRON, RT2870), 237 USB_ID(PEGATRON, RT3070), 238 USB_ID(PEGATRON, RT3070_2), 239 USB_ID(PEGATRON, RT3070_3), 240 USB_ID(PEGATRON, RT3072), 241 USB_ID(PHILIPS, RT2870), 242 USB_ID(PLANEX2, GWUS300MINIS), 243 USB_ID(PLANEX2, GWUSMICRO300), 244 USB_ID(PLANEX2, GWUSMICRON), 245 USB_ID(PLANEX2, RT2870), 246 USB_ID(PLANEX2, RT3070), 247 USB_ID(QCOM, RT2870), 248 USB_ID(QUANTA, RT3070), 249 USB_ID(RALINK, RT2070), 250 USB_ID(RALINK, RT2770), 251 USB_ID(RALINK, RT2870), 252 USB_ID(RALINK, RT3070), 253 USB_ID(RALINK, RT3071), 254 USB_ID(RALINK, RT3072), 255 USB_ID(RALINK, RT3370), 256 USB_ID(RALINK, RT3572), 257 USB_ID(RALINK, RT3573), 258 USB_ID(RALINK, RT5370), 259 USB_ID(RALINK, RT5572), 260 USB_ID(RALINK, RT8070), 261 USB_ID(SAMSUNG, WIS09ABGN), 262 USB_ID(SAMSUNG2, RT2870_1), 263 USB_ID(SENAO, RT2870_1), 264 USB_ID(SENAO, RT2870_2), 265 USB_ID(SENAO, RT2870_3), 266 USB_ID(SENAO, RT2870_4), 267 USB_ID(SENAO, RT3070), 268 USB_ID(SENAO, RT3071), 269 USB_ID(SENAO, RT3072_1), 270 USB_ID(SENAO, RT3072_2), 271 USB_ID(SENAO, RT3072_3), 272 USB_ID(SENAO, RT3072_4), 273 USB_ID(SENAO, RT3072_5), 274 USB_ID(SITECOMEU, WL302), 275 USB_ID(SITECOMEU, WL315), 276 USB_ID(SITECOMEU, WL321), 277 USB_ID(SITECOMEU, RT3070_3), 278 USB_ID(SITECOMEU, WL302), 279 USB_ID(SITECOMEU, WL344), 280 USB_ID(SITECOMEU, WL329), 281 USB_ID(SITECOMEU, WL345), 282 USB_ID(SITECOMEU, RT2870_1), 283 USB_ID(SITECOMEU, RT2870_2), 284 USB_ID(SITECOMEU, RT2870_3), 285 USB_ID(SITECOMEU, RT3070_1), 286 USB_ID(SITECOMEU, RT3072_3), 287 USB_ID(SITECOMEU, RT3072_4), 288 USB_ID(SITECOMEU, RT3072_5), 289 USB_ID(SITECOMEU, RT3072_6), 290 USB_ID(SITECOMEU, WL302), 291 USB_ID(SITECOMEU, WL315), 292 USB_ID(SITECOMEU, WL321), 293 USB_ID(SITECOMEU, WL324), 294 USB_ID(SITECOMEU, WL329), 295 USB_ID(SITECOMEU, WL343), 296 USB_ID(SITECOMEU, WL344), 297 USB_ID(SITECOMEU, WL345), 298 USB_ID(SITECOMEU, WL349V4), 299 USB_ID(SITECOMEU, WL608), 300 USB_ID(SITECOMEU, WLA4000), 301 USB_ID(SITECOMEU, WLA5000), 302 USB_ID(SPARKLAN, RT2870_1), 303 USB_ID(SPARKLAN, RT2870_2), 304 USB_ID(SPARKLAN, RT3070), 305 USB_ID(SWEEX2, LW153), 306 USB_ID(SWEEX2, LW303), 307 USB_ID(SWEEX2, LW313), 308 USB_ID(TOSHIBA, RT3070), 309 USB_ID(UMEDIA, RT2870_1), 310 USB_ID(UMEDIA, TEW645UB), 311 USB_ID(ZCOM, RT2870_1), 312 USB_ID(ZCOM, RT2870_2), 313 USB_ID(ZINWELL, RT2870_1), 314 USB_ID(ZINWELL, RT2870_2), 315 USB_ID(ZINWELL, RT3070), 316 USB_ID(ZINWELL, RT3072_1), 317 USB_ID(ZINWELL, RT3072_2), 318 USB_ID(ZYXEL, NWD2105), 319 USB_ID(ZYXEL, NWD211AN), 320 USB_ID(ZYXEL, RT2870_1), 321 USB_ID(ZYXEL, RT2870_2), 322 USB_ID(ZYXEL, RT3070) 323 }; 324 325 int run_match(struct device *, void *, void *); 326 void run_attach(struct device *, struct device *, void *); 327 int run_detach(struct device *, int); 328 int run_alloc_rx_ring(struct run_softc *); 329 void run_free_rx_ring(struct run_softc *); 330 int run_alloc_tx_ring(struct run_softc *, int); 331 void run_free_tx_ring(struct run_softc *, int); 332 int run_load_microcode(struct run_softc *); 333 int run_reset(struct run_softc *); 334 int run_read(struct run_softc *, uint16_t, uint32_t *); 335 int run_read_region_1(struct run_softc *, uint16_t, uint8_t *, 336 int); 337 int run_write_2(struct run_softc *, uint16_t, uint16_t); 338 int run_write(struct run_softc *, uint16_t, uint32_t); 339 int run_write_region_1(struct run_softc *, uint16_t, 340 const uint8_t *, int); 341 int run_set_region_4(struct run_softc *, uint16_t, uint32_t, int); 342 int run_efuse_read(struct run_softc *, uint16_t, uint16_t *); 343 int run_efuse_read_2(struct run_softc *, uint16_t, uint16_t *); 344 int run_eeprom_read_2(struct run_softc *, uint16_t, uint16_t *); 345 int run_rt2870_rf_write(struct run_softc *, uint8_t, uint32_t); 346 int run_rt3070_rf_read(struct run_softc *, uint8_t, uint8_t *); 347 int run_rt3070_rf_write(struct run_softc *, uint8_t, uint8_t); 348 int run_bbp_read(struct run_softc *, uint8_t, uint8_t *); 349 int run_bbp_write(struct run_softc *, uint8_t, uint8_t); 350 int run_mcu_cmd(struct run_softc *, uint8_t, uint16_t); 351 const char * run_get_rf(int); 352 void run_get_txpower(struct run_softc *); 353 void run_rt3593_get_txpower(struct run_softc *); 354 int run_read_eeprom(struct run_softc *); 355 struct ieee80211_node *run_node_alloc(struct ieee80211com *); 356 int run_media_change(struct ifnet *); 357 void run_next_scan(void *); 358 void run_task(void *); 359 void run_do_async(struct run_softc *, void (*)(struct run_softc *, 360 void *), void *, int); 361 int run_newstate(struct ieee80211com *, enum ieee80211_state, int); 362 void run_newstate_cb(struct run_softc *, void *); 363 void run_updateedca(struct ieee80211com *); 364 void run_updateedca_cb(struct run_softc *, void *); 365 int run_set_key(struct ieee80211com *, struct ieee80211_node *, 366 struct ieee80211_key *); 367 void run_set_key_cb(struct run_softc *, void *); 368 void run_delete_key(struct ieee80211com *, struct ieee80211_node *, 369 struct ieee80211_key *); 370 void run_delete_key_cb(struct run_softc *, void *); 371 void run_calibrate_to(void *); 372 void run_calibrate_cb(struct run_softc *, void *); 373 void run_newassoc(struct ieee80211com *, struct ieee80211_node *, 374 int); 375 void run_rx_frame(struct run_softc *, uint8_t *, int); 376 void run_rxeof(struct usbd_xfer *, void *, usbd_status); 377 void run_txeof(struct usbd_xfer *, void *, usbd_status); 378 int run_tx(struct run_softc *, struct mbuf *, 379 struct ieee80211_node *); 380 void run_start(struct ifnet *); 381 void run_watchdog(struct ifnet *); 382 int run_ioctl(struct ifnet *, u_long, caddr_t); 383 void run_iq_calib(struct run_softc *, u_int); 384 void run_select_chan_group(struct run_softc *, int); 385 void run_set_agc(struct run_softc *, uint8_t); 386 void run_set_rx_antenna(struct run_softc *, int); 387 void run_rt2870_set_chan(struct run_softc *, u_int); 388 void run_rt3070_set_chan(struct run_softc *, u_int); 389 void run_rt3572_set_chan(struct run_softc *, u_int); 390 void run_rt3593_set_chan(struct run_softc *, u_int); 391 void run_rt5390_set_chan(struct run_softc *, u_int); 392 void run_rt5592_set_chan(struct run_softc *, u_int); 393 int run_set_chan(struct run_softc *, struct ieee80211_channel *); 394 void run_enable_tsf_sync(struct run_softc *); 395 void run_enable_mrr(struct run_softc *); 396 void run_set_txpreamble(struct run_softc *); 397 void run_set_basicrates(struct run_softc *); 398 void run_set_leds(struct run_softc *, uint16_t); 399 void run_set_bssid(struct run_softc *, const uint8_t *); 400 void run_set_macaddr(struct run_softc *, const uint8_t *); 401 void run_updateslot(struct ieee80211com *); 402 void run_updateslot_cb(struct run_softc *, void *); 403 #if NBPFILTER > 0 404 int8_t run_rssi2dbm(struct run_softc *, uint8_t, uint8_t); 405 #endif 406 void run_rt5390_bbp_init(struct run_softc *); 407 int run_bbp_init(struct run_softc *); 408 int run_rt3070_rf_init(struct run_softc *); 409 void run_rt3593_rf_init(struct run_softc *); 410 void run_rt5390_rf_init(struct run_softc *); 411 int run_rt3070_filter_calib(struct run_softc *, uint8_t, uint8_t, 412 uint8_t *); 413 void run_rt3070_rf_setup(struct run_softc *); 414 void run_rt3593_rf_setup(struct run_softc *); 415 void run_rt5390_rf_setup(struct run_softc *); 416 int run_txrx_enable(struct run_softc *); 417 void run_adjust_freq_offset(struct run_softc *); 418 int run_init(struct ifnet *); 419 void run_stop(struct ifnet *, int); 420 421 struct cfdriver run_cd = { 422 NULL, "run", DV_IFNET 423 }; 424 425 const struct cfattach run_ca = { 426 sizeof (struct run_softc), run_match, run_attach, run_detach 427 }; 428 429 static const struct { 430 uint32_t reg; 431 uint32_t val; 432 } rt2870_def_mac[] = { 433 RT2870_DEF_MAC 434 }; 435 436 static const struct { 437 uint8_t reg; 438 uint8_t val; 439 } rt2860_def_bbp[] = { 440 RT2860_DEF_BBP 441 },rt5390_def_bbp[] = { 442 RT5390_DEF_BBP 443 },rt5592_def_bbp[] = { 444 RT5592_DEF_BBP 445 }; 446 447 /* 448 * Default values for BBP register R196 for RT5592. 449 */ 450 static const uint8_t rt5592_bbp_r196[] = { 451 0xe0, 0x1f, 0x38, 0x32, 0x08, 0x28, 0x19, 0x0a, 0xff, 0x00, 452 0x16, 0x10, 0x10, 0x0b, 0x36, 0x2c, 0x26, 0x24, 0x42, 0x36, 453 0x30, 0x2d, 0x4c, 0x46, 0x3d, 0x40, 0x3e, 0x42, 0x3d, 0x40, 454 0x3c, 0x34, 0x2c, 0x2f, 0x3c, 0x35, 0x2e, 0x2a, 0x49, 0x41, 455 0x36, 0x31, 0x30, 0x30, 0x0e, 0x0d, 0x28, 0x21, 0x1c, 0x16, 456 0x50, 0x4a, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 457 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 458 0x00, 0x00, 0x7d, 0x14, 0x32, 0x2c, 0x36, 0x4c, 0x43, 0x2c, 459 0x2e, 0x36, 0x30, 0x6e 460 }; 461 462 static const struct rfprog { 463 uint8_t chan; 464 uint32_t r1, r2, r3, r4; 465 } rt2860_rf2850[] = { 466 RT2860_RF2850 467 }; 468 469 struct { 470 uint8_t n, r, k; 471 } rt3070_freqs[] = { 472 RT3070_RF3052 473 }; 474 475 static const struct rt5592_freqs { 476 uint16_t n; 477 uint8_t k, m, r; 478 } rt5592_freqs_20mhz[] = { 479 RT5592_RF5592_20MHZ 480 },rt5592_freqs_40mhz[] = { 481 RT5592_RF5592_40MHZ 482 }; 483 484 static const struct { 485 uint8_t reg; 486 uint8_t val; 487 } rt3070_def_rf[] = { 488 RT3070_DEF_RF 489 },rt3572_def_rf[] = { 490 RT3572_DEF_RF 491 },rt3593_def_rf[] = { 492 RT3593_DEF_RF 493 },rt5390_def_rf[] = { 494 RT5390_DEF_RF 495 },rt5392_def_rf[] = { 496 RT5392_DEF_RF 497 },rt5592_def_rf[] = { 498 RT5592_DEF_RF 499 },rt5592_2ghz_def_rf[] = { 500 RT5592_2GHZ_DEF_RF 501 },rt5592_5ghz_def_rf[] = { 502 RT5592_5GHZ_DEF_RF 503 }; 504 505 static const struct { 506 u_int firstchan; 507 u_int lastchan; 508 uint8_t reg; 509 uint8_t val; 510 } rt5592_chan_5ghz[] = { 511 RT5592_CHAN_5GHZ 512 }; 513 514 int 515 run_match(struct device *parent, void *match, void *aux) 516 { 517 struct usb_attach_arg *uaa = aux; 518 519 if (uaa->iface == NULL || uaa->configno != 1) 520 return UMATCH_NONE; 521 522 return (usb_lookup(run_devs, uaa->vendor, uaa->product) != NULL) ? 523 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE; 524 } 525 526 void 527 run_attach(struct device *parent, struct device *self, void *aux) 528 { 529 struct run_softc *sc = (struct run_softc *)self; 530 struct usb_attach_arg *uaa = aux; 531 struct ieee80211com *ic = &sc->sc_ic; 532 struct ifnet *ifp = &ic->ic_if; 533 usb_interface_descriptor_t *id; 534 usb_endpoint_descriptor_t *ed; 535 int i, nrx, ntx, ntries; 536 uint32_t ver; 537 538 sc->sc_udev = uaa->device; 539 sc->sc_iface = uaa->iface; 540 541 /* 542 * Find all bulk endpoints. There are 7 bulk endpoints: 1 for RX 543 * and 6 for TX (4 EDCAs + HCCA + Prio). 544 * Update 03-14-2009: some devices like the Planex GW-US300MiniS 545 * seem to have only 4 TX bulk endpoints (Fukaumi Naoki). 546 */ 547 nrx = ntx = 0; 548 id = usbd_get_interface_descriptor(sc->sc_iface); 549 for (i = 0; i < id->bNumEndpoints; i++) { 550 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 551 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) 552 continue; 553 554 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 555 sc->rxq.pipe_no = ed->bEndpointAddress; 556 nrx++; 557 } else if (ntx < 4) { 558 sc->txq[ntx].pipe_no = ed->bEndpointAddress; 559 ntx++; 560 } 561 } 562 /* make sure we've got them all */ 563 if (nrx < 1 || ntx < 4) { 564 printf("%s: missing endpoint\n", sc->sc_dev.dv_xname); 565 return; 566 } 567 568 usb_init_task(&sc->sc_task, run_task, sc, USB_TASK_TYPE_GENERIC); 569 timeout_set(&sc->scan_to, run_next_scan, sc); 570 timeout_set(&sc->calib_to, run_calibrate_to, sc); 571 572 sc->amrr.amrr_min_success_threshold = 1; 573 sc->amrr.amrr_max_success_threshold = 10; 574 575 /* wait for the chip to settle */ 576 for (ntries = 0; ntries < 100; ntries++) { 577 if (run_read(sc, RT2860_ASIC_VER_ID, &ver) != 0) 578 return; 579 if (ver != 0 && ver != 0xffffffff) 580 break; 581 DELAY(10); 582 } 583 if (ntries == 100) { 584 printf("%s: timeout waiting for NIC to initialize\n", 585 sc->sc_dev.dv_xname); 586 return; 587 } 588 sc->mac_ver = ver >> 16; 589 sc->mac_rev = ver & 0xffff; 590 591 /* retrieve RF rev. no and various other things from EEPROM */ 592 run_read_eeprom(sc); 593 594 printf("%s: MAC/BBP RT%04X (rev 0x%04X), RF %s (MIMO %dT%dR), " 595 "address %s\n", sc->sc_dev.dv_xname, sc->mac_ver, 596 sc->mac_rev, run_get_rf(sc->rf_rev), sc->ntxchains, 597 sc->nrxchains, ether_sprintf(ic->ic_myaddr)); 598 599 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 600 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 601 ic->ic_state = IEEE80211_S_INIT; 602 603 /* set device capabilities */ 604 ic->ic_caps = 605 IEEE80211_C_MONITOR | /* monitor mode supported */ 606 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 607 IEEE80211_C_SHSLOT | /* short slot time supported */ 608 IEEE80211_C_WEP | /* WEP */ 609 IEEE80211_C_RSN; /* WPA/RSN */ 610 611 if (sc->rf_rev == RT2860_RF_2750 || 612 sc->rf_rev == RT2860_RF_2850 || 613 sc->rf_rev == RT3070_RF_3052 || 614 sc->rf_rev == RT3070_RF_3053 || 615 sc->rf_rev == RT5592_RF_5592) { 616 /* set supported .11a rates */ 617 ic->ic_sup_rates[IEEE80211_MODE_11A] = 618 ieee80211_std_rateset_11a; 619 620 /* set supported .11a channels */ 621 for (i = 14; i < nitems(rt2860_rf2850); i++) { 622 uint8_t chan = rt2860_rf2850[i].chan; 623 ic->ic_channels[chan].ic_freq = 624 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 625 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 626 } 627 } 628 629 /* set supported .11b and .11g rates */ 630 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 631 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 632 633 /* set supported .11b and .11g channels (1 through 14) */ 634 for (i = 1; i <= 14; i++) { 635 ic->ic_channels[i].ic_freq = 636 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 637 ic->ic_channels[i].ic_flags = 638 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 639 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 640 } 641 642 ifp->if_softc = sc; 643 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 644 ifp->if_ioctl = run_ioctl; 645 ifp->if_start = run_start; 646 ifp->if_watchdog = run_watchdog; 647 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 648 649 if_attach(ifp); 650 ieee80211_ifattach(ifp); 651 ic->ic_node_alloc = run_node_alloc; 652 ic->ic_newassoc = run_newassoc; 653 ic->ic_updateslot = run_updateslot; 654 ic->ic_updateedca = run_updateedca; 655 ic->ic_set_key = run_set_key; 656 ic->ic_delete_key = run_delete_key; 657 /* override state transition machine */ 658 sc->sc_newstate = ic->ic_newstate; 659 ic->ic_newstate = run_newstate; 660 ieee80211_media_init(ifp, run_media_change, ieee80211_media_status); 661 662 #if NBPFILTER > 0 663 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 664 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 665 666 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 667 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 668 sc->sc_rxtap.wr_ihdr.it_present = htole32(RUN_RX_RADIOTAP_PRESENT); 669 670 sc->sc_txtap_len = sizeof sc->sc_txtapu; 671 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 672 sc->sc_txtap.wt_ihdr.it_present = htole32(RUN_TX_RADIOTAP_PRESENT); 673 #endif 674 } 675 676 int 677 run_detach(struct device *self, int flags) 678 { 679 struct run_softc *sc = (struct run_softc *)self; 680 struct ifnet *ifp = &sc->sc_ic.ic_if; 681 int qid, s; 682 683 s = splusb(); 684 685 if (timeout_initialized(&sc->scan_to)) 686 timeout_del(&sc->scan_to); 687 if (timeout_initialized(&sc->calib_to)) 688 timeout_del(&sc->calib_to); 689 690 /* wait for all queued asynchronous commands to complete */ 691 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 692 693 usbd_ref_wait(sc->sc_udev); 694 695 if (ifp->if_softc != NULL) { 696 ifp->if_flags &= ~IFF_RUNNING; 697 ifq_clr_oactive(&ifp->if_snd); 698 ieee80211_ifdetach(ifp); 699 if_detach(ifp); 700 } 701 702 for (qid = 0; qid < 4; qid++) 703 run_free_tx_ring(sc, qid); 704 run_free_rx_ring(sc); 705 706 splx(s); 707 708 return 0; 709 } 710 711 int 712 run_alloc_rx_ring(struct run_softc *sc) 713 { 714 struct run_rx_ring *rxq = &sc->rxq; 715 int i, error; 716 717 error = usbd_open_pipe(sc->sc_iface, rxq->pipe_no, 0, &rxq->pipeh); 718 if (error != 0) 719 goto fail; 720 721 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 722 struct run_rx_data *data = &rxq->data[i]; 723 724 data->sc = sc; /* backpointer for callbacks */ 725 726 data->xfer = usbd_alloc_xfer(sc->sc_udev); 727 if (data->xfer == NULL) { 728 error = ENOMEM; 729 goto fail; 730 } 731 data->buf = usbd_alloc_buffer(data->xfer, RUN_MAX_RXSZ); 732 if (data->buf == NULL) { 733 error = ENOMEM; 734 goto fail; 735 } 736 } 737 if (error != 0) 738 fail: run_free_rx_ring(sc); 739 return error; 740 } 741 742 void 743 run_free_rx_ring(struct run_softc *sc) 744 { 745 struct run_rx_ring *rxq = &sc->rxq; 746 int i; 747 748 if (rxq->pipeh != NULL) { 749 usbd_abort_pipe(rxq->pipeh); 750 usbd_close_pipe(rxq->pipeh); 751 rxq->pipeh = NULL; 752 } 753 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 754 if (rxq->data[i].xfer != NULL) 755 usbd_free_xfer(rxq->data[i].xfer); 756 rxq->data[i].xfer = NULL; 757 } 758 } 759 760 int 761 run_alloc_tx_ring(struct run_softc *sc, int qid) 762 { 763 struct run_tx_ring *txq = &sc->txq[qid]; 764 int i, error; 765 uint16_t txwisize; 766 767 txwisize = sizeof(struct rt2860_txwi); 768 if (sc->mac_ver == 0x5592) 769 txwisize += sizeof(uint32_t); 770 771 txq->cur = txq->queued = 0; 772 773 error = usbd_open_pipe(sc->sc_iface, txq->pipe_no, 0, &txq->pipeh); 774 if (error != 0) 775 goto fail; 776 777 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 778 struct run_tx_data *data = &txq->data[i]; 779 780 data->sc = sc; /* backpointer for callbacks */ 781 data->qid = qid; 782 783 data->xfer = usbd_alloc_xfer(sc->sc_udev); 784 if (data->xfer == NULL) { 785 error = ENOMEM; 786 goto fail; 787 } 788 data->buf = usbd_alloc_buffer(data->xfer, RUN_MAX_TXSZ); 789 if (data->buf == NULL) { 790 error = ENOMEM; 791 goto fail; 792 } 793 /* zeroize the TXD + TXWI part */ 794 memset(data->buf, 0, sizeof(struct rt2870_txd) + txwisize); 795 } 796 if (error != 0) 797 fail: run_free_tx_ring(sc, qid); 798 return error; 799 } 800 801 void 802 run_free_tx_ring(struct run_softc *sc, int qid) 803 { 804 struct run_tx_ring *txq = &sc->txq[qid]; 805 int i; 806 807 if (txq->pipeh != NULL) { 808 usbd_abort_pipe(txq->pipeh); 809 usbd_close_pipe(txq->pipeh); 810 txq->pipeh = NULL; 811 } 812 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 813 if (txq->data[i].xfer != NULL) 814 usbd_free_xfer(txq->data[i].xfer); 815 txq->data[i].xfer = NULL; 816 } 817 } 818 819 int 820 run_load_microcode(struct run_softc *sc) 821 { 822 usb_device_request_t req; 823 const char *fwname; 824 u_char *ucode; 825 size_t size; 826 uint32_t tmp; 827 int ntries, error; 828 829 /* RT3071/RT3072 use a different firmware */ 830 if (sc->mac_ver != 0x2860 && 831 sc->mac_ver != 0x2872 && 832 sc->mac_ver != 0x3070) 833 fwname = "run-rt3071"; 834 else 835 fwname = "run-rt2870"; 836 837 if ((error = loadfirmware(fwname, &ucode, &size)) != 0) { 838 printf("%s: failed loadfirmware of file %s (error %d)\n", 839 sc->sc_dev.dv_xname, fwname, error); 840 return error; 841 } 842 if (size != 4096) { 843 printf("%s: invalid firmware size (should be 4KB)\n", 844 sc->sc_dev.dv_xname); 845 free(ucode, M_DEVBUF, 0); 846 return EINVAL; 847 } 848 849 run_read(sc, RT2860_ASIC_VER_ID, &tmp); 850 /* write microcode image */ 851 run_write_region_1(sc, RT2870_FW_BASE, ucode, size); 852 free(ucode, M_DEVBUF, 0); 853 run_write(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 854 run_write(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 855 856 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 857 req.bRequest = RT2870_RESET; 858 USETW(req.wValue, 8); 859 USETW(req.wIndex, 0); 860 USETW(req.wLength, 0); 861 if ((error = usbd_do_request(sc->sc_udev, &req, NULL)) != 0) 862 return error; 863 864 usbd_delay_ms(sc->sc_udev, 10); 865 run_write(sc, RT2860_H2M_BBPAGENT, 0); 866 run_write(sc, RT2860_H2M_MAILBOX, 0); 867 run_write(sc, RT2860_H2M_INTSRC, 0); 868 if ((error = run_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0)) != 0) 869 return error; 870 871 /* wait until microcontroller is ready */ 872 for (ntries = 0; ntries < 1000; ntries++) { 873 if ((error = run_read(sc, RT2860_SYS_CTRL, &tmp)) != 0) 874 return error; 875 if (tmp & RT2860_MCU_READY) 876 break; 877 DELAY(1000); 878 } 879 if (ntries == 1000) { 880 printf("%s: timeout waiting for MCU to initialize\n", 881 sc->sc_dev.dv_xname); 882 return ETIMEDOUT; 883 } 884 DPRINTF(("microcode successfully loaded after %d tries\n", ntries)); 885 return 0; 886 } 887 888 int 889 run_reset(struct run_softc *sc) 890 { 891 usb_device_request_t req; 892 893 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 894 req.bRequest = RT2870_RESET; 895 USETW(req.wValue, 1); 896 USETW(req.wIndex, 0); 897 USETW(req.wLength, 0); 898 return usbd_do_request(sc->sc_udev, &req, NULL); 899 } 900 901 int 902 run_read(struct run_softc *sc, uint16_t reg, uint32_t *val) 903 { 904 uint32_t tmp; 905 int error; 906 907 error = run_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof tmp); 908 if (error == 0) 909 *val = letoh32(tmp); 910 else 911 *val = 0xffffffff; 912 return error; 913 } 914 915 int 916 run_read_region_1(struct run_softc *sc, uint16_t reg, uint8_t *buf, int len) 917 { 918 usb_device_request_t req; 919 920 req.bmRequestType = UT_READ_VENDOR_DEVICE; 921 req.bRequest = RT2870_READ_REGION_1; 922 USETW(req.wValue, 0); 923 USETW(req.wIndex, reg); 924 USETW(req.wLength, len); 925 return usbd_do_request(sc->sc_udev, &req, buf); 926 } 927 928 int 929 run_write_2(struct run_softc *sc, uint16_t reg, uint16_t val) 930 { 931 usb_device_request_t req; 932 933 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 934 req.bRequest = RT2870_WRITE_2; 935 USETW(req.wValue, val); 936 USETW(req.wIndex, reg); 937 USETW(req.wLength, 0); 938 return usbd_do_request(sc->sc_udev, &req, NULL); 939 } 940 941 int 942 run_write(struct run_softc *sc, uint16_t reg, uint32_t val) 943 { 944 int error; 945 946 if ((error = run_write_2(sc, reg, val & 0xffff)) == 0) 947 error = run_write_2(sc, reg + 2, val >> 16); 948 return error; 949 } 950 951 int 952 run_write_region_1(struct run_softc *sc, uint16_t reg, const uint8_t *buf, 953 int len) 954 { 955 #if 1 956 int i, error = 0; 957 /* 958 * NB: the WRITE_REGION_1 command is not stable on RT2860. 959 * We thus issue multiple WRITE_2 commands instead. 960 */ 961 KASSERT((len & 1) == 0); 962 for (i = 0; i < len && error == 0; i += 2) 963 error = run_write_2(sc, reg + i, buf[i] | buf[i + 1] << 8); 964 return error; 965 #else 966 usb_device_request_t req; 967 968 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 969 req.bRequest = RT2870_WRITE_REGION_1; 970 USETW(req.wValue, 0); 971 USETW(req.wIndex, reg); 972 USETW(req.wLength, len); 973 return usbd_do_request(sc->sc_udev, &req, buf); 974 #endif 975 } 976 977 int 978 run_set_region_4(struct run_softc *sc, uint16_t reg, uint32_t val, int count) 979 { 980 int error = 0; 981 982 for (; count > 0 && error == 0; count--, reg += 4) 983 error = run_write(sc, reg, val); 984 return error; 985 } 986 987 /* Read 16-bit from eFUSE ROM. */ 988 int 989 run_efuse_read(struct run_softc *sc, uint16_t addr, uint16_t *val) 990 { 991 uint32_t tmp; 992 uint16_t reg; 993 int error, ntries; 994 995 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 996 return error; 997 998 /*- 999 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1000 * DATA0: F E D C 1001 * DATA1: B A 9 8 1002 * DATA2: 7 6 5 4 1003 * DATA3: 3 2 1 0 1004 */ 1005 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1006 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1007 run_write(sc, RT3070_EFUSE_CTRL, tmp); 1008 for (ntries = 0; ntries < 100; ntries++) { 1009 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1010 return error; 1011 if (!(tmp & RT3070_EFSROM_KICK)) 1012 break; 1013 DELAY(2); 1014 } 1015 if (ntries == 100) 1016 return ETIMEDOUT; 1017 1018 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) { 1019 *val = 0xffff; /* address not found */ 1020 return 0; 1021 } 1022 /* determine to which 32-bit register our 16-bit word belongs */ 1023 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1024 if ((error = run_read(sc, reg, &tmp)) != 0) 1025 return error; 1026 1027 tmp >>= (8 * (addr & 0x3)); 1028 *val = (addr & 1) ? tmp >> 16 : tmp & 0xffff; 1029 return 0; 1030 } 1031 1032 /* Read 16-bit from eFUSE ROM for RT3xxx. */ 1033 int 1034 run_efuse_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1035 { 1036 uint32_t tmp; 1037 uint16_t reg; 1038 int error, ntries; 1039 1040 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1041 return error; 1042 1043 addr *= 2; 1044 /*- 1045 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1046 * DATA0: F E D C 1047 * DATA1: B A 9 8 1048 * DATA2: 7 6 5 4 1049 * DATA3: 3 2 1 0 1050 */ 1051 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1052 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1053 run_write(sc, RT3070_EFUSE_CTRL, tmp); 1054 for (ntries = 0; ntries < 100; ntries++) { 1055 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1056 return error; 1057 if (!(tmp & RT3070_EFSROM_KICK)) 1058 break; 1059 DELAY(2); 1060 } 1061 if (ntries == 100) 1062 return ETIMEDOUT; 1063 1064 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) { 1065 *val = 0xffff; /* address not found */ 1066 return 0; 1067 } 1068 /* determine to which 32-bit register our 16-bit word belongs */ 1069 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1070 if ((error = run_read(sc, reg, &tmp)) != 0) 1071 return error; 1072 1073 *val = (addr & 2) ? tmp >> 16 : tmp & 0xffff; 1074 return 0; 1075 } 1076 1077 int 1078 run_eeprom_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1079 { 1080 usb_device_request_t req; 1081 uint16_t tmp; 1082 int error; 1083 1084 addr *= 2; 1085 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1086 req.bRequest = RT2870_EEPROM_READ; 1087 USETW(req.wValue, 0); 1088 USETW(req.wIndex, addr); 1089 USETW(req.wLength, sizeof tmp); 1090 error = usbd_do_request(sc->sc_udev, &req, &tmp); 1091 if (error == 0) 1092 *val = letoh16(tmp); 1093 else 1094 *val = 0xffff; 1095 return error; 1096 } 1097 1098 static __inline int 1099 run_srom_read(struct run_softc *sc, uint16_t addr, uint16_t *val) 1100 { 1101 /* either eFUSE ROM or EEPROM */ 1102 return sc->sc_srom_read(sc, addr, val); 1103 } 1104 1105 int 1106 run_rt2870_rf_write(struct run_softc *sc, uint8_t reg, uint32_t val) 1107 { 1108 uint32_t tmp; 1109 int error, ntries; 1110 1111 for (ntries = 0; ntries < 10; ntries++) { 1112 if ((error = run_read(sc, RT2860_RF_CSR_CFG0, &tmp)) != 0) 1113 return error; 1114 if (!(tmp & RT2860_RF_REG_CTRL)) 1115 break; 1116 } 1117 if (ntries == 10) 1118 return ETIMEDOUT; 1119 1120 /* RF registers are 24-bit on the RT2860 */ 1121 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 1122 (val & 0x3fffff) << 2 | (reg & 3); 1123 return run_write(sc, RT2860_RF_CSR_CFG0, tmp); 1124 } 1125 1126 int 1127 run_rt3070_rf_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1128 { 1129 uint32_t tmp; 1130 int error, ntries; 1131 1132 for (ntries = 0; ntries < 100; ntries++) { 1133 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1134 return error; 1135 if (!(tmp & RT3070_RF_KICK)) 1136 break; 1137 } 1138 if (ntries == 100) 1139 return ETIMEDOUT; 1140 1141 tmp = RT3070_RF_KICK | reg << 8; 1142 if ((error = run_write(sc, RT3070_RF_CSR_CFG, tmp)) != 0) 1143 return error; 1144 1145 for (ntries = 0; ntries < 100; ntries++) { 1146 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1147 return error; 1148 if (!(tmp & RT3070_RF_KICK)) 1149 break; 1150 } 1151 if (ntries == 100) 1152 return ETIMEDOUT; 1153 1154 *val = tmp & 0xff; 1155 return 0; 1156 } 1157 1158 int 1159 run_rt3070_rf_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1160 { 1161 uint32_t tmp; 1162 int error, ntries; 1163 1164 for (ntries = 0; ntries < 10; ntries++) { 1165 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1166 return error; 1167 if (!(tmp & RT3070_RF_KICK)) 1168 break; 1169 } 1170 if (ntries == 10) 1171 return ETIMEDOUT; 1172 1173 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 1174 return run_write(sc, RT3070_RF_CSR_CFG, tmp); 1175 } 1176 1177 int 1178 run_bbp_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1179 { 1180 uint32_t tmp; 1181 int ntries, error; 1182 1183 for (ntries = 0; ntries < 10; ntries++) { 1184 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1185 return error; 1186 if (!(tmp & RT2860_BBP_CSR_KICK)) 1187 break; 1188 } 1189 if (ntries == 10) 1190 return ETIMEDOUT; 1191 1192 tmp = RT2860_BBP_CSR_READ | RT2860_BBP_CSR_KICK | reg << 8; 1193 if ((error = run_write(sc, RT2860_BBP_CSR_CFG, tmp)) != 0) 1194 return error; 1195 1196 for (ntries = 0; ntries < 10; ntries++) { 1197 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1198 return error; 1199 if (!(tmp & RT2860_BBP_CSR_KICK)) 1200 break; 1201 } 1202 if (ntries == 10) 1203 return ETIMEDOUT; 1204 1205 *val = tmp & 0xff; 1206 return 0; 1207 } 1208 1209 int 1210 run_bbp_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1211 { 1212 uint32_t tmp; 1213 int ntries, error; 1214 1215 for (ntries = 0; ntries < 10; ntries++) { 1216 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1217 return error; 1218 if (!(tmp & RT2860_BBP_CSR_KICK)) 1219 break; 1220 } 1221 if (ntries == 10) 1222 return ETIMEDOUT; 1223 1224 tmp = RT2860_BBP_CSR_KICK | reg << 8 | val; 1225 return run_write(sc, RT2860_BBP_CSR_CFG, tmp); 1226 } 1227 1228 /* 1229 * Send a command to the 8051 microcontroller unit. 1230 */ 1231 int 1232 run_mcu_cmd(struct run_softc *sc, uint8_t cmd, uint16_t arg) 1233 { 1234 uint32_t tmp; 1235 int error, ntries; 1236 1237 for (ntries = 0; ntries < 100; ntries++) { 1238 if ((error = run_read(sc, RT2860_H2M_MAILBOX, &tmp)) != 0) 1239 return error; 1240 if (!(tmp & RT2860_H2M_BUSY)) 1241 break; 1242 } 1243 if (ntries == 100) 1244 return ETIMEDOUT; 1245 1246 tmp = RT2860_H2M_BUSY | RT2860_TOKEN_NO_INTR << 16 | arg; 1247 if ((error = run_write(sc, RT2860_H2M_MAILBOX, tmp)) == 0) 1248 error = run_write(sc, RT2860_HOST_CMD, cmd); 1249 return error; 1250 } 1251 1252 /* 1253 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 1254 * Used to adjust per-rate Tx power registers. 1255 */ 1256 static __inline uint32_t 1257 b4inc(uint32_t b32, int8_t delta) 1258 { 1259 int8_t i, b4; 1260 1261 for (i = 0; i < 8; i++) { 1262 b4 = b32 & 0xf; 1263 b4 += delta; 1264 if (b4 < 0) 1265 b4 = 0; 1266 else if (b4 > 0xf) 1267 b4 = 0xf; 1268 b32 = b32 >> 4 | b4 << 28; 1269 } 1270 return b32; 1271 } 1272 1273 const char * 1274 run_get_rf(int rev) 1275 { 1276 switch (rev) { 1277 case RT2860_RF_2820: return "RT2820"; 1278 case RT2860_RF_2850: return "RT2850"; 1279 case RT2860_RF_2720: return "RT2720"; 1280 case RT2860_RF_2750: return "RT2750"; 1281 case RT3070_RF_3020: return "RT3020"; 1282 case RT3070_RF_2020: return "RT2020"; 1283 case RT3070_RF_3021: return "RT3021"; 1284 case RT3070_RF_3022: return "RT3022"; 1285 case RT3070_RF_3052: return "RT3052"; 1286 case RT3070_RF_3053: return "RT3053"; 1287 case RT5592_RF_5592: return "RT5592"; 1288 case RT5390_RF_5370: return "RT5370"; 1289 case RT5390_RF_5372: return "RT5372"; 1290 } 1291 return "unknown"; 1292 } 1293 1294 void 1295 run_rt3593_get_txpower(struct run_softc *sc) 1296 { 1297 uint16_t addr, val; 1298 int i; 1299 1300 /* Read power settings for 2GHz channels. */ 1301 for (i = 0; i < 14; i += 2) { 1302 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE1 : 1303 RT2860_EEPROM_PWR2GHZ_BASE1; 1304 run_srom_read(sc, addr + i / 2, &val); 1305 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1306 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1307 1308 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE2 : 1309 RT2860_EEPROM_PWR2GHZ_BASE2; 1310 run_srom_read(sc, addr + i / 2, &val); 1311 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1312 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1313 1314 if (sc->ntxchains == 3) { 1315 run_srom_read(sc, RT3593_EEPROM_PWR2GHZ_BASE3 + i / 2, 1316 &val); 1317 sc->txpow3[i + 0] = (int8_t)(val & 0xff); 1318 sc->txpow3[i + 1] = (int8_t)(val >> 8); 1319 } 1320 } 1321 /* Fix broken Tx power entries. */ 1322 for (i = 0; i < 14; i++) { 1323 if (sc->txpow1[i] > 31) 1324 sc->txpow1[i] = 5; 1325 if (sc->txpow2[i] > 31) 1326 sc->txpow2[i] = 5; 1327 if (sc->ntxchains == 3) { 1328 if (sc->txpow3[i] > 31) 1329 sc->txpow3[i] = 5; 1330 } 1331 } 1332 /* Read power settings for 5GHz channels. */ 1333 for (i = 0; i < 40; i += 2) { 1334 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1335 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1336 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1337 1338 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1339 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1340 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1341 1342 if (sc->ntxchains == 3) { 1343 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE3 + i / 2, 1344 &val); 1345 sc->txpow3[i + 14] = (int8_t)(val & 0xff); 1346 sc->txpow3[i + 15] = (int8_t)(val >> 8); 1347 } 1348 } 1349 } 1350 1351 void 1352 run_get_txpower(struct run_softc *sc) 1353 { 1354 uint16_t val; 1355 int i; 1356 1357 /* Read power settings for 2GHz channels. */ 1358 for (i = 0; i < 14; i += 2) { 1359 run_srom_read(sc, RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2, &val); 1360 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1361 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1362 1363 if (sc->mac_ver != 0x5390) { 1364 run_srom_read(sc, 1365 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2, &val); 1366 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1367 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1368 } 1369 } 1370 /* Fix broken Tx power entries. */ 1371 for (i = 0; i < 14; i++) { 1372 if (sc->mac_ver >= 0x5390) { 1373 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 27) 1374 sc->txpow1[i] = 5; 1375 } else { 1376 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31) 1377 sc->txpow1[i] = 5; 1378 } 1379 if (sc->mac_ver > 0x5390) { 1380 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 27) 1381 sc->txpow2[i] = 5; 1382 } else if (sc->mac_ver < 0x5390) { 1383 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31) 1384 sc->txpow2[i] = 5; 1385 } 1386 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1387 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 1388 } 1389 /* Read power settings for 5GHz channels. */ 1390 for (i = 0; i < 40; i += 2) { 1391 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1392 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1393 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1394 1395 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1396 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1397 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1398 } 1399 /* Fix broken Tx power entries. */ 1400 for (i = 0; i < 40; i++ ) { 1401 if (sc->mac_ver != 0x5592) { 1402 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 1403 sc->txpow1[14 + i] = 5; 1404 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 1405 sc->txpow2[14 + i] = 5; 1406 } 1407 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1408 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 1409 sc->txpow2[14 + i])); 1410 } 1411 } 1412 1413 int 1414 run_read_eeprom(struct run_softc *sc) 1415 { 1416 struct ieee80211com *ic = &sc->sc_ic; 1417 int8_t delta_2ghz, delta_5ghz; 1418 uint32_t tmp; 1419 uint16_t val; 1420 int ridx, ant, i; 1421 1422 /* check whether the ROM is eFUSE ROM or EEPROM */ 1423 sc->sc_srom_read = run_eeprom_read_2; 1424 if (sc->mac_ver >= 0x3070) { 1425 run_read(sc, RT3070_EFUSE_CTRL, &tmp); 1426 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 1427 if (tmp & RT3070_SEL_EFUSE || sc->mac_ver == 0x3593) 1428 sc->sc_srom_read = run_efuse_read_2; 1429 } 1430 1431 /* read ROM version */ 1432 run_srom_read(sc, RT2860_EEPROM_VERSION, &val); 1433 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); 1434 1435 /* read MAC address */ 1436 run_srom_read(sc, RT2860_EEPROM_MAC01, &val); 1437 ic->ic_myaddr[0] = val & 0xff; 1438 ic->ic_myaddr[1] = val >> 8; 1439 run_srom_read(sc, RT2860_EEPROM_MAC23, &val); 1440 ic->ic_myaddr[2] = val & 0xff; 1441 ic->ic_myaddr[3] = val >> 8; 1442 run_srom_read(sc, RT2860_EEPROM_MAC45, &val); 1443 ic->ic_myaddr[4] = val & 0xff; 1444 ic->ic_myaddr[5] = val >> 8; 1445 1446 if (sc->mac_ver < 0x3593) { 1447 /* read vendor BBP settings */ 1448 for (i = 0; i < 10; i++) { 1449 run_srom_read(sc, RT2860_EEPROM_BBP_BASE + i, &val); 1450 sc->bbp[i].val = val & 0xff; 1451 sc->bbp[i].reg = val >> 8; 1452 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, 1453 sc->bbp[i].val)); 1454 } 1455 if (sc->mac_ver >= 0x3071) { 1456 /* read vendor RF settings */ 1457 for (i = 0; i < 10; i++) { 1458 run_srom_read(sc, RT3071_EEPROM_RF_BASE + i, 1459 &val); 1460 sc->rf[i].val = val & 0xff; 1461 sc->rf[i].reg = val >> 8; 1462 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 1463 sc->rf[i].val)); 1464 } 1465 } 1466 } 1467 1468 /* read RF frequency offset from EEPROM */ 1469 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_FREQ_LEDS : 1470 RT3593_EEPROM_FREQ, &val); 1471 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 1472 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 1473 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_FREQ_LEDS : 1474 RT3593_EEPROM_FREQ_LEDS, &val); 1475 if ((val >> 8) != 0xff) { 1476 /* read LEDs operating mode */ 1477 sc->leds = val >> 8; 1478 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED1 : 1479 RT3593_EEPROM_LED1, &sc->led[0]); 1480 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED2 : 1481 RT3593_EEPROM_LED2, &sc->led[1]); 1482 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED3 : 1483 RT3593_EEPROM_LED3, &sc->led[2]); 1484 } else { 1485 /* broken EEPROM, use default settings */ 1486 sc->leds = 0x01; 1487 sc->led[0] = 0x5555; 1488 sc->led[1] = 0x2221; 1489 sc->led[2] = 0x5627; /* differs from RT2860 */ 1490 } 1491 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 1492 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 1493 1494 /* read RF information */ 1495 if (sc->mac_ver == 0x5390 || sc->mac_ver == 0x5392) 1496 run_srom_read(sc, 0x00, &val); 1497 else 1498 run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val); 1499 if (val == 0xffff) { 1500 DPRINTF(("invalid EEPROM antenna info, using default\n")); 1501 if (sc->mac_ver == 0x3572) { 1502 /* default to RF3052 2T2R */ 1503 sc->rf_rev = RT3070_RF_3052; 1504 sc->ntxchains = 2; 1505 sc->nrxchains = 2; 1506 } else if (sc->mac_ver >= 0x3070) { 1507 /* default to RF3020 1T1R */ 1508 sc->rf_rev = RT3070_RF_3020; 1509 sc->ntxchains = 1; 1510 sc->nrxchains = 1; 1511 } else { 1512 /* default to RF2820 1T2R */ 1513 sc->rf_rev = RT2860_RF_2820; 1514 sc->ntxchains = 1; 1515 sc->nrxchains = 2; 1516 } 1517 } else { 1518 if (sc->mac_ver == 0x5390 || sc->mac_ver == 0x5392) { 1519 sc->rf_rev = val; 1520 run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val); 1521 } else 1522 sc->rf_rev = (val >> 8) & 0xf; 1523 sc->ntxchains = (val >> 4) & 0xf; 1524 sc->nrxchains = val & 0xf; 1525 } 1526 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 1527 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 1528 1529 /* check if RF supports automatic Tx access gain control */ 1530 run_srom_read(sc, RT2860_EEPROM_CONFIG, &val); 1531 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 1532 /* check if driver should patch the DAC issue */ 1533 if ((val >> 8) != 0xff) 1534 sc->patch_dac = (val >> 15) & 1; 1535 if ((val & 0xff) != 0xff) { 1536 sc->ext_5ghz_lna = (val >> 3) & 1; 1537 sc->ext_2ghz_lna = (val >> 2) & 1; 1538 /* check if RF supports automatic Tx access gain control */ 1539 sc->calib_2ghz = sc->calib_5ghz = (val >> 1) & 1; 1540 /* check if we have a hardware radio switch */ 1541 sc->rfswitch = val & 1; 1542 } 1543 1544 /* Read Tx power settings. */ 1545 if (sc->mac_ver == 0x3593) 1546 run_rt3593_get_txpower(sc); 1547 else 1548 run_get_txpower(sc); 1549 1550 /* read Tx power compensation for each Tx rate */ 1551 run_srom_read(sc, RT2860_EEPROM_DELTAPWR, &val); 1552 delta_2ghz = delta_5ghz = 0; 1553 if ((val & 0xff) != 0xff && (val & 0x80)) { 1554 delta_2ghz = val & 0xf; 1555 if (!(val & 0x40)) /* negative number */ 1556 delta_2ghz = -delta_2ghz; 1557 } 1558 val >>= 8; 1559 if ((val & 0xff) != 0xff && (val & 0x80)) { 1560 delta_5ghz = val & 0xf; 1561 if (!(val & 0x40)) /* negative number */ 1562 delta_5ghz = -delta_5ghz; 1563 } 1564 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 1565 delta_2ghz, delta_5ghz)); 1566 1567 for (ridx = 0; ridx < 5; ridx++) { 1568 uint32_t reg; 1569 1570 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2, &val); 1571 reg = val; 1572 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1, &val); 1573 reg |= (uint32_t)val << 16; 1574 1575 sc->txpow20mhz[ridx] = reg; 1576 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 1577 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 1578 1579 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 1580 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 1581 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 1582 } 1583 1584 /* read RSSI offsets and LNA gains from EEPROM */ 1585 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_2GHZ : 1586 RT3593_EEPROM_RSSI1_2GHZ, &val); 1587 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 1588 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 1589 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_2GHZ : 1590 RT3593_EEPROM_RSSI2_2GHZ, &val); 1591 if (sc->mac_ver >= 0x3070) { 1592 if (sc->mac_ver == 0x3593) { 1593 sc->txmixgain_2ghz = 0; 1594 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1595 } else { 1596 /* 1597 * On RT3070 chips (limited to 2 Rx chains), this ROM 1598 * field contains the Tx mixer gain for the 2GHz band. 1599 */ 1600 if ((val & 0xff) != 0xff) 1601 sc->txmixgain_2ghz = val & 0x7; 1602 } 1603 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 1604 } else 1605 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1606 if (sc->mac_ver == 0x3593) 1607 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1608 sc->lna[2] = val >> 8; /* channel group 2 */ 1609 1610 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_5GHZ : 1611 RT3593_EEPROM_RSSI1_5GHZ, &val); 1612 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 1613 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 1614 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_5GHZ : 1615 RT3593_EEPROM_RSSI2_5GHZ, &val); 1616 if (sc->mac_ver == 0x3572) { 1617 /* 1618 * On RT3572 chips (limited to 2 Rx chains), this ROM 1619 * field contains the Tx mixer gain for the 5GHz band. 1620 */ 1621 if ((val & 0xff) != 0xff) 1622 sc->txmixgain_5ghz = val & 0x7; 1623 DPRINTF(("tx mixer gain=%u (5GHz)\n", sc->txmixgain_5ghz)); 1624 } else 1625 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 1626 if (sc->mac_ver == 0x3593) { 1627 sc->txmixgain_5ghz = 0; 1628 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1629 } 1630 sc->lna[3] = val >> 8; /* channel group 3 */ 1631 1632 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LNA : 1633 RT3593_EEPROM_LNA, &val); 1634 sc->lna[0] = val & 0xff; /* channel group 0 */ 1635 sc->lna[1] = val >> 8; /* channel group 1 */ 1636 1637 /* fix broken 5GHz LNA entries */ 1638 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 1639 DPRINTF(("invalid LNA for channel group %d\n", 2)); 1640 sc->lna[2] = sc->lna[1]; 1641 } 1642 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 1643 DPRINTF(("invalid LNA for channel group %d\n", 3)); 1644 sc->lna[3] = sc->lna[1]; 1645 } 1646 1647 /* fix broken RSSI offset entries */ 1648 for (ant = 0; ant < 3; ant++) { 1649 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 1650 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 1651 ant + 1, sc->rssi_2ghz[ant])); 1652 sc->rssi_2ghz[ant] = 0; 1653 } 1654 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 1655 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 1656 ant + 1, sc->rssi_5ghz[ant])); 1657 sc->rssi_5ghz[ant] = 0; 1658 } 1659 } 1660 return 0; 1661 } 1662 1663 struct ieee80211_node * 1664 run_node_alloc(struct ieee80211com *ic) 1665 { 1666 return malloc(sizeof (struct run_node), M_DEVBUF, M_NOWAIT | M_ZERO); 1667 } 1668 1669 int 1670 run_media_change(struct ifnet *ifp) 1671 { 1672 struct run_softc *sc = ifp->if_softc; 1673 struct ieee80211com *ic = &sc->sc_ic; 1674 uint8_t rate, ridx; 1675 int error; 1676 1677 error = ieee80211_media_change(ifp); 1678 if (error != ENETRESET) 1679 return error; 1680 1681 if (ic->ic_fixed_rate != -1) { 1682 rate = ic->ic_sup_rates[ic->ic_curmode]. 1683 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1684 for (ridx = 0; ridx <= RT2860_RIDX_MAX; ridx++) 1685 if (rt2860_rates[ridx].rate == rate) 1686 break; 1687 sc->fixed_ridx = ridx; 1688 } 1689 1690 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1691 (IFF_UP | IFF_RUNNING)) { 1692 run_stop(ifp, 0); 1693 run_init(ifp); 1694 } 1695 1696 return 0; 1697 } 1698 1699 void 1700 run_next_scan(void *arg) 1701 { 1702 struct run_softc *sc = arg; 1703 1704 if (usbd_is_dying(sc->sc_udev)) 1705 return; 1706 1707 usbd_ref_incr(sc->sc_udev); 1708 1709 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1710 ieee80211_next_scan(&sc->sc_ic.ic_if); 1711 1712 usbd_ref_decr(sc->sc_udev); 1713 } 1714 1715 void 1716 run_task(void *arg) 1717 { 1718 struct run_softc *sc = arg; 1719 struct run_host_cmd_ring *ring = &sc->cmdq; 1720 struct run_host_cmd *cmd; 1721 int s; 1722 1723 if (usbd_is_dying(sc->sc_udev)) 1724 return; 1725 1726 /* process host commands */ 1727 s = splusb(); 1728 while (ring->next != ring->cur) { 1729 cmd = &ring->cmd[ring->next]; 1730 splx(s); 1731 /* callback */ 1732 cmd->cb(sc, cmd->data); 1733 s = splusb(); 1734 ring->queued--; 1735 ring->next = (ring->next + 1) % RUN_HOST_CMD_RING_COUNT; 1736 } 1737 splx(s); 1738 } 1739 1740 void 1741 run_do_async(struct run_softc *sc, void (*cb)(struct run_softc *, void *), 1742 void *arg, int len) 1743 { 1744 struct run_host_cmd_ring *ring = &sc->cmdq; 1745 struct run_host_cmd *cmd; 1746 int s; 1747 1748 if (usbd_is_dying(sc->sc_udev)) 1749 return; 1750 1751 s = splusb(); 1752 cmd = &ring->cmd[ring->cur]; 1753 cmd->cb = cb; 1754 KASSERT(len <= sizeof (cmd->data)); 1755 memcpy(cmd->data, arg, len); 1756 ring->cur = (ring->cur + 1) % RUN_HOST_CMD_RING_COUNT; 1757 1758 /* if there is no pending command already, schedule a task */ 1759 if (++ring->queued == 1) 1760 usb_add_task(sc->sc_udev, &sc->sc_task); 1761 splx(s); 1762 } 1763 1764 int 1765 run_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1766 { 1767 struct run_softc *sc = ic->ic_softc; 1768 struct run_cmd_newstate cmd; 1769 1770 /* do it in a process context */ 1771 cmd.state = nstate; 1772 cmd.arg = arg; 1773 run_do_async(sc, run_newstate_cb, &cmd, sizeof cmd); 1774 return 0; 1775 } 1776 1777 void 1778 run_newstate_cb(struct run_softc *sc, void *arg) 1779 { 1780 struct run_cmd_newstate *cmd = arg; 1781 struct ieee80211com *ic = &sc->sc_ic; 1782 enum ieee80211_state ostate; 1783 struct ieee80211_node *ni; 1784 uint32_t tmp, sta[3]; 1785 uint8_t wcid; 1786 int s; 1787 1788 s = splnet(); 1789 ostate = ic->ic_state; 1790 1791 if (ostate == IEEE80211_S_RUN) { 1792 /* turn link LED off */ 1793 run_set_leds(sc, RT2860_LED_RADIO); 1794 } 1795 1796 switch (cmd->state) { 1797 case IEEE80211_S_INIT: 1798 if (ostate == IEEE80211_S_RUN) { 1799 /* abort TSF synchronization */ 1800 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 1801 run_write(sc, RT2860_BCN_TIME_CFG, 1802 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 1803 RT2860_TBTT_TIMER_EN)); 1804 } 1805 break; 1806 1807 case IEEE80211_S_SCAN: 1808 run_set_chan(sc, ic->ic_bss->ni_chan); 1809 if (!usbd_is_dying(sc->sc_udev)) 1810 timeout_add_msec(&sc->scan_to, 200); 1811 break; 1812 1813 case IEEE80211_S_AUTH: 1814 case IEEE80211_S_ASSOC: 1815 run_set_chan(sc, ic->ic_bss->ni_chan); 1816 break; 1817 1818 case IEEE80211_S_RUN: 1819 run_set_chan(sc, ic->ic_bss->ni_chan); 1820 1821 ni = ic->ic_bss; 1822 1823 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1824 run_updateslot(ic); 1825 run_enable_mrr(sc); 1826 run_set_txpreamble(sc); 1827 run_set_basicrates(sc); 1828 run_set_bssid(sc, ni->ni_bssid); 1829 } 1830 if (ic->ic_opmode == IEEE80211_M_STA) { 1831 /* add BSS entry to the WCID table */ 1832 wcid = RUN_AID2WCID(ni->ni_associd); 1833 run_write_region_1(sc, RT2860_WCID_ENTRY(wcid), 1834 ni->ni_macaddr, IEEE80211_ADDR_LEN); 1835 1836 /* fake a join to init the tx rate */ 1837 run_newassoc(ic, ni, 1); 1838 } 1839 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1840 run_enable_tsf_sync(sc); 1841 1842 /* clear statistic registers used by AMRR */ 1843 run_read_region_1(sc, RT2860_TX_STA_CNT0, 1844 (uint8_t *)sta, sizeof sta); 1845 /* start calibration timer */ 1846 if (!usbd_is_dying(sc->sc_udev)) 1847 timeout_add_sec(&sc->calib_to, 1); 1848 } 1849 1850 /* turn link LED on */ 1851 run_set_leds(sc, RT2860_LED_RADIO | 1852 (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan) ? 1853 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 1854 break; 1855 } 1856 (void)sc->sc_newstate(ic, cmd->state, cmd->arg); 1857 splx(s); 1858 } 1859 1860 void 1861 run_updateedca(struct ieee80211com *ic) 1862 { 1863 /* do it in a process context */ 1864 run_do_async(ic->ic_softc, run_updateedca_cb, NULL, 0); 1865 } 1866 1867 /* ARGSUSED */ 1868 void 1869 run_updateedca_cb(struct run_softc *sc, void *arg) 1870 { 1871 struct ieee80211com *ic = &sc->sc_ic; 1872 int s, aci; 1873 1874 s = splnet(); 1875 /* update MAC TX configuration registers */ 1876 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 1877 run_write(sc, RT2860_EDCA_AC_CFG(aci), 1878 ic->ic_edca_ac[aci].ac_ecwmax << 16 | 1879 ic->ic_edca_ac[aci].ac_ecwmin << 12 | 1880 ic->ic_edca_ac[aci].ac_aifsn << 8 | 1881 ic->ic_edca_ac[aci].ac_txoplimit); 1882 } 1883 1884 /* update SCH/DMA registers too */ 1885 run_write(sc, RT2860_WMM_AIFSN_CFG, 1886 ic->ic_edca_ac[EDCA_AC_VO].ac_aifsn << 12 | 1887 ic->ic_edca_ac[EDCA_AC_VI].ac_aifsn << 8 | 1888 ic->ic_edca_ac[EDCA_AC_BK].ac_aifsn << 4 | 1889 ic->ic_edca_ac[EDCA_AC_BE].ac_aifsn); 1890 run_write(sc, RT2860_WMM_CWMIN_CFG, 1891 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmin << 12 | 1892 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmin << 8 | 1893 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmin << 4 | 1894 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmin); 1895 run_write(sc, RT2860_WMM_CWMAX_CFG, 1896 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmax << 12 | 1897 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmax << 8 | 1898 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmax << 4 | 1899 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmax); 1900 run_write(sc, RT2860_WMM_TXOP0_CFG, 1901 ic->ic_edca_ac[EDCA_AC_BK].ac_txoplimit << 16 | 1902 ic->ic_edca_ac[EDCA_AC_BE].ac_txoplimit); 1903 run_write(sc, RT2860_WMM_TXOP1_CFG, 1904 ic->ic_edca_ac[EDCA_AC_VO].ac_txoplimit << 16 | 1905 ic->ic_edca_ac[EDCA_AC_VI].ac_txoplimit); 1906 splx(s); 1907 } 1908 1909 int 1910 run_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1911 struct ieee80211_key *k) 1912 { 1913 struct run_softc *sc = ic->ic_softc; 1914 struct run_cmd_key cmd; 1915 1916 /* defer setting of WEP keys until interface is brought up */ 1917 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 1918 (IFF_UP | IFF_RUNNING)) 1919 return 0; 1920 1921 /* do it in a process context */ 1922 cmd.key = *k; 1923 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 1924 run_do_async(sc, run_set_key_cb, &cmd, sizeof cmd); 1925 return 0; 1926 } 1927 1928 void 1929 run_set_key_cb(struct run_softc *sc, void *arg) 1930 { 1931 struct run_cmd_key *cmd = arg; 1932 struct ieee80211_key *k = &cmd->key; 1933 uint32_t attr; 1934 uint16_t base; 1935 uint8_t mode, wcid, iv[8]; 1936 1937 /* map net80211 cipher to RT2860 security mode */ 1938 switch (k->k_cipher) { 1939 case IEEE80211_CIPHER_WEP40: 1940 mode = RT2860_MODE_WEP40; 1941 break; 1942 case IEEE80211_CIPHER_WEP104: 1943 mode = RT2860_MODE_WEP104; 1944 break; 1945 case IEEE80211_CIPHER_TKIP: 1946 mode = RT2860_MODE_TKIP; 1947 break; 1948 case IEEE80211_CIPHER_CCMP: 1949 mode = RT2860_MODE_AES_CCMP; 1950 break; 1951 default: 1952 return; 1953 } 1954 1955 if (k->k_flags & IEEE80211_KEY_GROUP) { 1956 wcid = 0; /* NB: update WCID0 for group keys */ 1957 base = RT2860_SKEY(0, k->k_id); 1958 } else { 1959 wcid = RUN_AID2WCID(cmd->associd); 1960 base = RT2860_PKEY(wcid); 1961 } 1962 1963 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 1964 run_write_region_1(sc, base, k->k_key, 16); 1965 run_write_region_1(sc, base + 16, &k->k_key[24], 8); 1966 run_write_region_1(sc, base + 24, &k->k_key[16], 8); 1967 } else { 1968 /* roundup len to 16-bit: XXX fix write_region_1() instead */ 1969 run_write_region_1(sc, base, k->k_key, (k->k_len + 1) & ~1); 1970 } 1971 1972 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 1973 (k->k_flags & IEEE80211_KEY_TX)) { 1974 /* set initial packet number in IV+EIV */ 1975 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 1976 k->k_cipher == IEEE80211_CIPHER_WEP104) { 1977 memset(iv, 0, sizeof iv); 1978 iv[3] = sc->sc_ic.ic_def_txkey << 6; 1979 } else { 1980 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 1981 iv[0] = k->k_tsc >> 8; 1982 iv[1] = (iv[0] | 0x20) & 0x7f; 1983 iv[2] = k->k_tsc; 1984 } else /* CCMP */ { 1985 iv[0] = k->k_tsc; 1986 iv[1] = k->k_tsc >> 8; 1987 iv[2] = 0; 1988 } 1989 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 1990 iv[4] = k->k_tsc >> 16; 1991 iv[5] = k->k_tsc >> 24; 1992 iv[6] = k->k_tsc >> 32; 1993 iv[7] = k->k_tsc >> 40; 1994 } 1995 run_write_region_1(sc, RT2860_IVEIV(wcid), iv, 8); 1996 } 1997 1998 if (k->k_flags & IEEE80211_KEY_GROUP) { 1999 /* install group key */ 2000 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2001 attr &= ~(0xf << (k->k_id * 4)); 2002 attr |= mode << (k->k_id * 4); 2003 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2004 } else { 2005 /* install pairwise key */ 2006 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2007 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 2008 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2009 } 2010 } 2011 2012 void 2013 run_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2014 struct ieee80211_key *k) 2015 { 2016 struct run_softc *sc = ic->ic_softc; 2017 struct run_cmd_key cmd; 2018 2019 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 2020 ic->ic_state != IEEE80211_S_RUN) 2021 return; /* nothing to do */ 2022 2023 /* do it in a process context */ 2024 cmd.key = *k; 2025 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 2026 run_do_async(sc, run_delete_key_cb, &cmd, sizeof cmd); 2027 } 2028 2029 void 2030 run_delete_key_cb(struct run_softc *sc, void *arg) 2031 { 2032 struct run_cmd_key *cmd = arg; 2033 struct ieee80211_key *k = &cmd->key; 2034 uint32_t attr; 2035 uint8_t wcid; 2036 2037 if (k->k_flags & IEEE80211_KEY_GROUP) { 2038 /* remove group key */ 2039 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2040 attr &= ~(0xf << (k->k_id * 4)); 2041 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2042 2043 } else { 2044 /* remove pairwise key */ 2045 wcid = RUN_AID2WCID(cmd->associd); 2046 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2047 attr &= ~0xf; 2048 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2049 } 2050 } 2051 2052 void 2053 run_calibrate_to(void *arg) 2054 { 2055 /* do it in a process context */ 2056 run_do_async(arg, run_calibrate_cb, NULL, 0); 2057 /* next timeout will be rescheduled in the calibration task */ 2058 } 2059 2060 /* ARGSUSED */ 2061 void 2062 run_calibrate_cb(struct run_softc *sc, void *arg) 2063 { 2064 struct ifnet *ifp = &sc->sc_ic.ic_if; 2065 uint32_t sta[3]; 2066 int s, error; 2067 2068 /* read statistic counters (clear on read) and update AMRR state */ 2069 error = run_read_region_1(sc, RT2860_TX_STA_CNT0, (uint8_t *)sta, 2070 sizeof sta); 2071 if (error != 0) 2072 goto skip; 2073 2074 DPRINTF(("retrycnt=%d txcnt=%d failcnt=%d\n", 2075 letoh32(sta[1]) >> 16, letoh32(sta[1]) & 0xffff, 2076 letoh32(sta[0]) & 0xffff)); 2077 2078 s = splnet(); 2079 /* count failed TX as errors */ 2080 ifp->if_oerrors += letoh32(sta[0]) & 0xffff; 2081 2082 sc->amn.amn_retrycnt = 2083 (letoh32(sta[0]) & 0xffff) + /* failed TX count */ 2084 (letoh32(sta[1]) >> 16); /* TX retransmission count */ 2085 2086 sc->amn.amn_txcnt = 2087 sc->amn.amn_retrycnt + 2088 (letoh32(sta[1]) & 0xffff); /* successful TX count */ 2089 2090 ieee80211_amrr_choose(&sc->amrr, sc->sc_ic.ic_bss, &sc->amn); 2091 splx(s); 2092 2093 skip: 2094 if (!usbd_is_dying(sc->sc_udev)) 2095 timeout_add_sec(&sc->calib_to, 1); 2096 } 2097 2098 void 2099 run_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 2100 { 2101 struct run_softc *sc = ic->ic_softc; 2102 struct run_node *rn = (void *)ni; 2103 struct ieee80211_rateset *rs = &ni->ni_rates; 2104 uint8_t rate; 2105 int ridx, i, j; 2106 2107 DPRINTF(("new assoc isnew=%d addr=%s\n", 2108 isnew, ether_sprintf(ni->ni_macaddr))); 2109 2110 ieee80211_amrr_node_init(&sc->amrr, &sc->amn); 2111 /* start at lowest available bit-rate, AMRR will raise */ 2112 ni->ni_txrate = 0; 2113 2114 for (i = 0; i < rs->rs_nrates; i++) { 2115 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2116 /* convert 802.11 rate to hardware rate index */ 2117 for (ridx = 0; ridx < RT2860_RIDX_MAX; ridx++) 2118 if (rt2860_rates[ridx].rate == rate) 2119 break; 2120 rn->ridx[i] = ridx; 2121 /* determine rate of control response frames */ 2122 for (j = i; j >= 0; j--) { 2123 if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC) && 2124 rt2860_rates[rn->ridx[i]].phy == 2125 rt2860_rates[rn->ridx[j]].phy) 2126 break; 2127 } 2128 if (j >= 0) { 2129 rn->ctl_ridx[i] = rn->ridx[j]; 2130 } else { 2131 /* no basic rate found, use mandatory one */ 2132 rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx; 2133 } 2134 DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n", 2135 rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i])); 2136 } 2137 } 2138 2139 /* 2140 * Return the Rx chain with the highest RSSI for a given frame. 2141 */ 2142 static __inline uint8_t 2143 run_maxrssi_chain(struct run_softc *sc, const struct rt2860_rxwi *rxwi) 2144 { 2145 uint8_t rxchain = 0; 2146 2147 if (sc->nrxchains > 1) { 2148 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 2149 rxchain = 1; 2150 if (sc->nrxchains > 2) 2151 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 2152 rxchain = 2; 2153 } 2154 return rxchain; 2155 } 2156 2157 void 2158 run_rx_frame(struct run_softc *sc, uint8_t *buf, int dmalen) 2159 { 2160 struct ieee80211com *ic = &sc->sc_ic; 2161 struct ifnet *ifp = &ic->ic_if; 2162 struct ieee80211_frame *wh; 2163 struct ieee80211_rxinfo rxi; 2164 struct ieee80211_node *ni; 2165 struct rt2870_rxd *rxd; 2166 struct rt2860_rxwi *rxwi; 2167 struct mbuf *m; 2168 uint32_t flags; 2169 uint16_t len; 2170 #if NBPFILTER > 0 2171 uint16_t phy; 2172 #endif 2173 uint16_t rxwisize; 2174 uint8_t ant, rssi; 2175 int s; 2176 2177 rxwi = (struct rt2860_rxwi *)buf; 2178 rxwisize = sizeof(struct rt2860_rxwi); 2179 if (sc->mac_ver == 0x5592) 2180 rxwisize += sizeof(uint64_t); 2181 else if (sc->mac_ver == 0x3593) 2182 rxwisize += sizeof(uint32_t); 2183 len = letoh16(rxwi->len) & 0xfff; 2184 if (__predict_false(len > dmalen)) { 2185 DPRINTF(("bad RXWI length %u > %u\n", len, dmalen)); 2186 return; 2187 } 2188 /* Rx descriptor is located at the end */ 2189 rxd = (struct rt2870_rxd *)(buf + dmalen); 2190 flags = letoh32(rxd->flags); 2191 2192 if (__predict_false(flags & (RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 2193 ifp->if_ierrors++; 2194 return; 2195 } 2196 2197 if (__predict_false((flags & RT2860_RX_MICERR))) { 2198 /* report MIC failures to net80211 for TKIP */ 2199 ic->ic_stats.is_rx_locmicfail++; 2200 ieee80211_michael_mic_failure(ic, 0/* XXX */); 2201 ifp->if_ierrors++; 2202 return; 2203 } 2204 2205 wh = (struct ieee80211_frame *)(buf + rxwisize); 2206 rxi.rxi_flags = 0; 2207 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2208 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 2209 rxi.rxi_flags |= IEEE80211_RXI_HWDEC; 2210 } 2211 2212 if (flags & RT2860_RX_L2PAD) { 2213 u_int hdrlen = ieee80211_get_hdrlen(wh); 2214 memmove((caddr_t)wh + 2, wh, hdrlen); 2215 wh = (struct ieee80211_frame *)((caddr_t)wh + 2); 2216 } 2217 2218 /* could use m_devget but net80211 wants contig mgmt frames */ 2219 MGETHDR(m, M_DONTWAIT, MT_DATA); 2220 if (__predict_false(m == NULL)) { 2221 ifp->if_ierrors++; 2222 return; 2223 } 2224 if (len > MHLEN) { 2225 MCLGET(m, M_DONTWAIT); 2226 if (__predict_false(!(m->m_flags & M_EXT))) { 2227 ifp->if_ierrors++; 2228 m_freem(m); 2229 return; 2230 } 2231 } 2232 /* finalize mbuf */ 2233 memcpy(mtod(m, caddr_t), wh, len); 2234 m->m_pkthdr.len = m->m_len = len; 2235 2236 ant = run_maxrssi_chain(sc, rxwi); 2237 rssi = rxwi->rssi[ant]; 2238 2239 #if NBPFILTER > 0 2240 if (__predict_false(sc->sc_drvbpf != NULL)) { 2241 struct run_rx_radiotap_header *tap = &sc->sc_rxtap; 2242 struct mbuf mb; 2243 2244 tap->wr_flags = 0; 2245 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 2246 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 2247 tap->wr_antsignal = rssi; 2248 tap->wr_antenna = ant; 2249 tap->wr_dbm_antsignal = run_rssi2dbm(sc, rssi, ant); 2250 tap->wr_rate = 2; /* in case it can't be found below */ 2251 phy = letoh16(rxwi->phy); 2252 switch (phy & RT2860_PHY_MODE) { 2253 case RT2860_PHY_CCK: 2254 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 2255 case 0: tap->wr_rate = 2; break; 2256 case 1: tap->wr_rate = 4; break; 2257 case 2: tap->wr_rate = 11; break; 2258 case 3: tap->wr_rate = 22; break; 2259 } 2260 if (phy & RT2860_PHY_SHPRE) 2261 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2262 break; 2263 case RT2860_PHY_OFDM: 2264 switch (phy & RT2860_PHY_MCS) { 2265 case 0: tap->wr_rate = 12; break; 2266 case 1: tap->wr_rate = 18; break; 2267 case 2: tap->wr_rate = 24; break; 2268 case 3: tap->wr_rate = 36; break; 2269 case 4: tap->wr_rate = 48; break; 2270 case 5: tap->wr_rate = 72; break; 2271 case 6: tap->wr_rate = 96; break; 2272 case 7: tap->wr_rate = 108; break; 2273 } 2274 break; 2275 } 2276 mb.m_data = (caddr_t)tap; 2277 mb.m_len = sc->sc_rxtap_len; 2278 mb.m_next = m; 2279 mb.m_nextpkt = NULL; 2280 mb.m_type = 0; 2281 mb.m_flags = 0; 2282 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 2283 } 2284 #endif 2285 2286 s = splnet(); 2287 ni = ieee80211_find_rxnode(ic, wh); 2288 rxi.rxi_rssi = rssi; 2289 rxi.rxi_tstamp = 0; /* unused */ 2290 ieee80211_input(ifp, m, ni, &rxi); 2291 2292 /* node is no longer needed */ 2293 ieee80211_release_node(ic, ni); 2294 splx(s); 2295 } 2296 2297 void 2298 run_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2299 { 2300 struct run_rx_data *data = priv; 2301 struct run_softc *sc = data->sc; 2302 uint8_t *buf; 2303 uint32_t dmalen; 2304 int xferlen; 2305 uint16_t rxwisize; 2306 2307 rxwisize = sizeof(struct rt2860_rxwi); 2308 if (sc->mac_ver == 0x5592) 2309 rxwisize += sizeof(uint64_t); 2310 else if (sc->mac_ver == 0x3593) 2311 rxwisize += sizeof(uint32_t); 2312 2313 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2314 DPRINTF(("RX status=%d\n", status)); 2315 if (status == USBD_STALLED) 2316 usbd_clear_endpoint_stall_async(sc->rxq.pipeh); 2317 if (status != USBD_CANCELLED) 2318 goto skip; 2319 return; 2320 } 2321 usbd_get_xfer_status(xfer, NULL, NULL, &xferlen, NULL); 2322 2323 if (__predict_false(xferlen < sizeof (uint32_t) + rxwisize + 2324 sizeof(struct rt2870_rxd))) { 2325 DPRINTF(("xfer too short %d\n", xferlen)); 2326 goto skip; 2327 } 2328 2329 /* HW can aggregate multiple 802.11 frames in a single USB xfer */ 2330 buf = data->buf; 2331 while (xferlen > 8) { 2332 dmalen = letoh32(*(uint32_t *)buf) & 0xffff; 2333 2334 if (__predict_false(dmalen == 0 || (dmalen & 3) != 0)) { 2335 DPRINTF(("bad DMA length %u\n", dmalen)); 2336 break; 2337 } 2338 if (__predict_false(dmalen + 8 > xferlen)) { 2339 DPRINTF(("bad DMA length %u > %d\n", 2340 dmalen + 8, xferlen)); 2341 break; 2342 } 2343 run_rx_frame(sc, buf + sizeof (uint32_t), dmalen); 2344 buf += dmalen + 8; 2345 xferlen -= dmalen + 8; 2346 } 2347 2348 skip: /* setup a new transfer */ 2349 usbd_setup_xfer(xfer, sc->rxq.pipeh, data, data->buf, RUN_MAX_RXSZ, 2350 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, run_rxeof); 2351 (void)usbd_transfer(data->xfer); 2352 } 2353 2354 void 2355 run_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2356 { 2357 struct run_tx_data *data = priv; 2358 struct run_softc *sc = data->sc; 2359 struct run_tx_ring *txq = &sc->txq[data->qid]; 2360 struct ifnet *ifp = &sc->sc_ic.ic_if; 2361 int s; 2362 2363 s = splnet(); 2364 txq->queued--; 2365 sc->qfullmsk &= ~(1 << data->qid); 2366 2367 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2368 DPRINTF(("TX status=%d\n", status)); 2369 if (status == USBD_STALLED) 2370 usbd_clear_endpoint_stall_async(txq->pipeh); 2371 ifp->if_oerrors++; 2372 splx(s); 2373 return; 2374 } 2375 2376 sc->sc_tx_timer = 0; 2377 ifp->if_opackets++; 2378 ifq_clr_oactive(&ifp->if_snd); 2379 run_start(ifp); 2380 splx(s); 2381 } 2382 2383 int 2384 run_tx(struct run_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 2385 { 2386 struct ieee80211com *ic = &sc->sc_ic; 2387 struct run_node *rn = (void *)ni; 2388 struct ieee80211_frame *wh; 2389 struct run_tx_ring *ring; 2390 struct run_tx_data *data; 2391 struct rt2870_txd *txd; 2392 struct rt2860_txwi *txwi; 2393 uint16_t qos, dur; 2394 uint16_t txwisize; 2395 uint8_t type, mcs, tid, qid; 2396 int error, hasqos, ridx, ctl_ridx, xferlen; 2397 2398 wh = mtod(m, struct ieee80211_frame *); 2399 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2400 2401 if ((hasqos = ieee80211_has_qos(wh))) { 2402 qos = ieee80211_get_qos(wh); 2403 tid = qos & IEEE80211_QOS_TID; 2404 qid = ieee80211_up_to_ac(ic, tid); 2405 } else { 2406 qos = 0; 2407 tid = 0; 2408 qid = EDCA_AC_BE; 2409 } 2410 ring = &sc->txq[qid]; 2411 data = &ring->data[ring->cur]; 2412 2413 /* pickup a rate index */ 2414 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2415 type != IEEE80211_FC0_TYPE_DATA) { 2416 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2417 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 2418 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2419 } else if (ic->ic_fixed_rate != -1) { 2420 ridx = sc->fixed_ridx; 2421 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2422 } else { 2423 ridx = rn->ridx[ni->ni_txrate]; 2424 ctl_ridx = rn->ctl_ridx[ni->ni_txrate]; 2425 } 2426 2427 /* get MCS code from rate index */ 2428 mcs = rt2860_rates[ridx].mcs; 2429 2430 txwisize = sizeof(struct rt2860_txwi); 2431 if (sc->mac_ver == 0x5592) 2432 txwisize += sizeof(uint32_t); 2433 xferlen = txwisize + m->m_pkthdr.len; 2434 2435 /* roundup to 32-bit alignment */ 2436 xferlen = (xferlen + 3) & ~3; 2437 2438 txd = (struct rt2870_txd *)data->buf; 2439 txd->flags = RT2860_TX_QSEL_EDCA; 2440 txd->len = htole16(xferlen); 2441 2442 /* setup TX Wireless Information */ 2443 txwi = (struct rt2860_txwi *)(txd + 1); 2444 txwi->flags = 0; 2445 txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ; 2446 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ? 2447 RUN_AID2WCID(ni->ni_associd) : 0xff; 2448 txwi->len = htole16(m->m_pkthdr.len); 2449 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 2450 txwi->phy = htole16(RT2860_PHY_CCK); 2451 if (ridx != RT2860_RIDX_CCK1 && 2452 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 2453 mcs |= RT2860_PHY_SHPRE; 2454 } else 2455 txwi->phy = htole16(RT2860_PHY_OFDM); 2456 txwi->phy |= htole16(mcs); 2457 2458 txwi->txop = RT2860_TX_TXOP_BACKOFF; 2459 2460 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2461 (!hasqos || (qos & IEEE80211_QOS_ACK_POLICY_MASK) != 2462 IEEE80211_QOS_ACK_POLICY_NOACK)) { 2463 txwi->xflags |= RT2860_TX_ACK; 2464 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2465 dur = rt2860_rates[ctl_ridx].sp_ack_dur; 2466 else 2467 dur = rt2860_rates[ctl_ridx].lp_ack_dur; 2468 *(uint16_t *)wh->i_dur = htole16(dur); 2469 } 2470 2471 #if NBPFILTER > 0 2472 if (__predict_false(sc->sc_drvbpf != NULL)) { 2473 struct run_tx_radiotap_header *tap = &sc->sc_txtap; 2474 struct mbuf mb; 2475 2476 tap->wt_flags = 0; 2477 tap->wt_rate = rt2860_rates[ridx].rate; 2478 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 2479 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 2480 tap->wt_hwqueue = qid; 2481 if (mcs & RT2860_PHY_SHPRE) 2482 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2483 2484 mb.m_data = (caddr_t)tap; 2485 mb.m_len = sc->sc_txtap_len; 2486 mb.m_next = m; 2487 mb.m_nextpkt = NULL; 2488 mb.m_type = 0; 2489 mb.m_flags = 0; 2490 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 2491 } 2492 #endif 2493 2494 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)txwi + txwisize); 2495 m_freem(m); 2496 2497 xferlen += sizeof (*txd) + 4; 2498 2499 usbd_setup_xfer(data->xfer, ring->pipeh, data, data->buf, xferlen, 2500 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, RUN_TX_TIMEOUT, run_txeof); 2501 error = usbd_transfer(data->xfer); 2502 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) 2503 return error; 2504 2505 ieee80211_release_node(ic, ni); 2506 2507 ring->cur = (ring->cur + 1) % RUN_TX_RING_COUNT; 2508 if (++ring->queued >= RUN_TX_RING_COUNT) 2509 sc->qfullmsk |= 1 << qid; 2510 2511 return 0; 2512 } 2513 2514 void 2515 run_start(struct ifnet *ifp) 2516 { 2517 struct run_softc *sc = ifp->if_softc; 2518 struct ieee80211com *ic = &sc->sc_ic; 2519 struct ieee80211_node *ni; 2520 struct mbuf *m; 2521 2522 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 2523 return; 2524 2525 for (;;) { 2526 if (sc->qfullmsk != 0) { 2527 ifq_set_oactive(&ifp->if_snd); 2528 break; 2529 } 2530 /* send pending management frames first */ 2531 m = mq_dequeue(&ic->ic_mgtq); 2532 if (m != NULL) { 2533 ni = m->m_pkthdr.ph_cookie; 2534 goto sendit; 2535 } 2536 if (ic->ic_state != IEEE80211_S_RUN) 2537 break; 2538 2539 /* encapsulate and send data frames */ 2540 IFQ_DEQUEUE(&ifp->if_snd, m); 2541 if (m == NULL) 2542 break; 2543 #if NBPFILTER > 0 2544 if (ifp->if_bpf != NULL) 2545 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 2546 #endif 2547 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 2548 continue; 2549 sendit: 2550 #if NBPFILTER > 0 2551 if (ic->ic_rawbpf != NULL) 2552 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 2553 #endif 2554 if (run_tx(sc, m, ni) != 0) { 2555 ieee80211_release_node(ic, ni); 2556 ifp->if_oerrors++; 2557 continue; 2558 } 2559 2560 sc->sc_tx_timer = 5; 2561 ifp->if_timer = 1; 2562 } 2563 } 2564 2565 void 2566 run_watchdog(struct ifnet *ifp) 2567 { 2568 struct run_softc *sc = ifp->if_softc; 2569 2570 ifp->if_timer = 0; 2571 2572 if (sc->sc_tx_timer > 0) { 2573 if (--sc->sc_tx_timer == 0) { 2574 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 2575 /* run_init(ifp); XXX needs a process context! */ 2576 ifp->if_oerrors++; 2577 return; 2578 } 2579 ifp->if_timer = 1; 2580 } 2581 2582 ieee80211_watchdog(ifp); 2583 } 2584 2585 int 2586 run_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2587 { 2588 struct run_softc *sc = ifp->if_softc; 2589 struct ieee80211com *ic = &sc->sc_ic; 2590 struct ifreq *ifr; 2591 int s, error = 0; 2592 2593 if (usbd_is_dying(sc->sc_udev)) 2594 return ENXIO; 2595 2596 usbd_ref_incr(sc->sc_udev); 2597 2598 s = splnet(); 2599 2600 switch (cmd) { 2601 case SIOCSIFADDR: 2602 ifp->if_flags |= IFF_UP; 2603 /* FALLTHROUGH */ 2604 case SIOCSIFFLAGS: 2605 if (ifp->if_flags & IFF_UP) { 2606 if (!(ifp->if_flags & IFF_RUNNING)) 2607 run_init(ifp); 2608 } else { 2609 if (ifp->if_flags & IFF_RUNNING) 2610 run_stop(ifp, 1); 2611 } 2612 break; 2613 2614 case SIOCADDMULTI: 2615 case SIOCDELMULTI: 2616 ifr = (struct ifreq *)data; 2617 error = (cmd == SIOCADDMULTI) ? 2618 ether_addmulti(ifr, &ic->ic_ac) : 2619 ether_delmulti(ifr, &ic->ic_ac); 2620 2621 if (error == ENETRESET) 2622 error = 0; 2623 break; 2624 2625 case SIOCS80211CHANNEL: 2626 /* 2627 * This allows for fast channel switching in monitor mode 2628 * (used by kismet). 2629 */ 2630 error = ieee80211_ioctl(ifp, cmd, data); 2631 if (error == ENETRESET && 2632 ic->ic_opmode == IEEE80211_M_MONITOR) { 2633 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2634 (IFF_UP | IFF_RUNNING)) 2635 run_set_chan(sc, ic->ic_ibss_chan); 2636 error = 0; 2637 } 2638 break; 2639 2640 default: 2641 error = ieee80211_ioctl(ifp, cmd, data); 2642 } 2643 2644 if (error == ENETRESET) { 2645 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2646 (IFF_UP | IFF_RUNNING)) { 2647 run_stop(ifp, 0); 2648 run_init(ifp); 2649 } 2650 error = 0; 2651 } 2652 2653 splx(s); 2654 2655 usbd_ref_decr(sc->sc_udev); 2656 2657 return error; 2658 } 2659 2660 void 2661 run_iq_calib(struct run_softc *sc, u_int chan) 2662 { 2663 uint16_t val; 2664 2665 /* Tx0 IQ gain. */ 2666 run_bbp_write(sc, 158, 0x2c); 2667 if (chan <= 14) 2668 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ, &val); 2669 else if (chan <= 64) { 2670 run_efuse_read(sc, 2671 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ, &val); 2672 } else if (chan <= 138) { 2673 run_efuse_read(sc, 2674 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ, &val); 2675 } else if (chan <= 165) { 2676 run_efuse_read(sc, 2677 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ, 2678 &val); 2679 } else 2680 val = 0; 2681 run_bbp_write(sc, 159, val); 2682 2683 /* Tx0 IQ phase. */ 2684 run_bbp_write(sc, 158, 0x2d); 2685 if (chan <= 14) { 2686 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ, &val); 2687 } else if (chan <= 64) { 2688 run_efuse_read(sc, 2689 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ, &val); 2690 } else if (chan <= 138) { 2691 run_efuse_read(sc, 2692 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ, &val); 2693 } else if (chan <= 165) { 2694 run_efuse_read(sc, 2695 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ, &val); 2696 } else 2697 val = 0; 2698 run_bbp_write(sc, 159, val); 2699 2700 /* Tx1 IQ gain. */ 2701 run_bbp_write(sc, 158, 0x4a); 2702 if (chan <= 14) { 2703 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ, &val); 2704 } else if (chan <= 64) { 2705 run_efuse_read(sc, 2706 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ, &val); 2707 } else if (chan <= 138) { 2708 run_efuse_read(sc, 2709 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ, &val); 2710 } else if (chan <= 165) { 2711 run_efuse_read(sc, 2712 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ, &val); 2713 } else 2714 val = 0; 2715 run_bbp_write(sc, 159, val); 2716 2717 /* Tx1 IQ phase. */ 2718 run_bbp_write(sc, 158, 0x4b); 2719 if (chan <= 14) { 2720 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ, &val); 2721 } else if (chan <= 64) { 2722 run_efuse_read(sc, 2723 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ, &val); 2724 } else if (chan <= 138) { 2725 run_efuse_read(sc, 2726 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ, &val); 2727 } else if (chan <= 165) { 2728 run_efuse_read(sc, 2729 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ, &val); 2730 } else 2731 val = 0; 2732 run_bbp_write(sc, 159, val); 2733 2734 /* RF IQ compensation control. */ 2735 run_bbp_write(sc, 158, 0x04); 2736 run_efuse_read(sc, RT5390_EEPROM_RF_IQ_COMPENSATION_CTL, &val); 2737 run_bbp_write(sc, 159, val); 2738 2739 /* RF IQ imbalance compensation control. */ 2740 run_bbp_write(sc, 158, 0x03); 2741 run_efuse_read(sc, 2742 RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL, &val); 2743 run_bbp_write(sc, 159, val); 2744 } 2745 2746 void 2747 run_select_chan_group(struct run_softc *sc, int group) 2748 { 2749 uint32_t tmp; 2750 uint8_t agc; 2751 2752 run_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2753 run_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2754 run_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2755 if (sc->mac_ver < 0x3572) 2756 run_bbp_write(sc, 86, 0x00); 2757 2758 if (sc->mac_ver == 0x3593) { 2759 run_bbp_write(sc, 77, 0x98); 2760 run_bbp_write(sc, 83, (group == 0) ? 0x8a : 0x9a); 2761 } 2762 2763 if (group == 0) { 2764 if (sc->ext_2ghz_lna) { 2765 if (sc->mac_ver >= 0x5390) 2766 run_bbp_write(sc, 75, 0x52); 2767 else { 2768 run_bbp_write(sc, 82, 0x62); 2769 run_bbp_write(sc, 75, 0x46); 2770 } 2771 } else { 2772 if (sc->mac_ver == 0x5592) { 2773 run_bbp_write(sc, 79, 0x1c); 2774 run_bbp_write(sc, 80, 0x0e); 2775 run_bbp_write(sc, 81, 0x3a); 2776 run_bbp_write(sc, 82, 0x62); 2777 2778 run_bbp_write(sc, 195, 0x80); 2779 run_bbp_write(sc, 196, 0xe0); 2780 run_bbp_write(sc, 195, 0x81); 2781 run_bbp_write(sc, 196, 0x1f); 2782 run_bbp_write(sc, 195, 0x82); 2783 run_bbp_write(sc, 196, 0x38); 2784 run_bbp_write(sc, 195, 0x83); 2785 run_bbp_write(sc, 196, 0x32); 2786 run_bbp_write(sc, 195, 0x85); 2787 run_bbp_write(sc, 196, 0x28); 2788 run_bbp_write(sc, 195, 0x86); 2789 run_bbp_write(sc, 196, 0x19); 2790 } else if (sc->mac_ver >= 0x5390) 2791 run_bbp_write(sc, 75, 0x50); 2792 else { 2793 run_bbp_write(sc, 82, 2794 (sc->mac_ver == 0x3593) ? 0x62 : 0x84); 2795 run_bbp_write(sc, 75, 0x50); 2796 } 2797 } 2798 } else { 2799 if (sc->mac_ver == 0x5592) { 2800 run_bbp_write(sc, 79, 0x18); 2801 run_bbp_write(sc, 80, 0x08); 2802 run_bbp_write(sc, 81, 0x38); 2803 run_bbp_write(sc, 82, 0x92); 2804 2805 run_bbp_write(sc, 195, 0x80); 2806 run_bbp_write(sc, 196, 0xf0); 2807 run_bbp_write(sc, 195, 0x81); 2808 run_bbp_write(sc, 196, 0x1e); 2809 run_bbp_write(sc, 195, 0x82); 2810 run_bbp_write(sc, 196, 0x28); 2811 run_bbp_write(sc, 195, 0x83); 2812 run_bbp_write(sc, 196, 0x20); 2813 run_bbp_write(sc, 195, 0x85); 2814 run_bbp_write(sc, 196, 0x7f); 2815 run_bbp_write(sc, 195, 0x86); 2816 run_bbp_write(sc, 196, 0x7f); 2817 } else if (sc->mac_ver == 0x3572) 2818 run_bbp_write(sc, 82, 0x94); 2819 else 2820 run_bbp_write(sc, 82, 2821 (sc->mac_ver == 0x3593) ? 0x82 : 0xf2); 2822 if (sc->ext_5ghz_lna) 2823 run_bbp_write(sc, 75, 0x46); 2824 else 2825 run_bbp_write(sc, 75, 0x50); 2826 } 2827 2828 run_read(sc, RT2860_TX_BAND_CFG, &tmp); 2829 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2830 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2831 run_write(sc, RT2860_TX_BAND_CFG, tmp); 2832 2833 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2834 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2835 if (sc->mac_ver == 0x3593) 2836 tmp |= 1 << 29 | 1 << 28; 2837 if (sc->nrxchains > 1) 2838 tmp |= RT2860_LNA_PE1_EN; 2839 if (group == 0) { /* 2GHz */ 2840 tmp |= RT2860_PA_PE_G0_EN; 2841 if (sc->ntxchains > 1) 2842 tmp |= RT2860_PA_PE_G1_EN; 2843 if (sc->mac_ver == 0x3593) { 2844 if (sc->ntxchains > 2) 2845 tmp |= 1 << 25; 2846 } 2847 } else { /* 5GHz */ 2848 tmp |= RT2860_PA_PE_A0_EN; 2849 if (sc->ntxchains > 1) 2850 tmp |= RT2860_PA_PE_A1_EN; 2851 } 2852 if (sc->mac_ver == 0x3572) { 2853 run_rt3070_rf_write(sc, 8, 0x00); 2854 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2855 run_rt3070_rf_write(sc, 8, 0x80); 2856 } else 2857 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2858 2859 if (sc->mac_ver == 0x5592) { 2860 run_bbp_write(sc, 195, 0x8d); 2861 run_bbp_write(sc, 196, 0x1a); 2862 } 2863 2864 if (sc->mac_ver == 0x3593) { 2865 run_read(sc, RT2860_GPIO_CTRL, &tmp); 2866 tmp &= ~0x01010000; 2867 if (group == 0) 2868 tmp |= 0x00010000; 2869 tmp = (tmp & ~0x00009090) | 0x00000090; 2870 run_write(sc, RT2860_GPIO_CTRL, tmp); 2871 } 2872 2873 /* set initial AGC value */ 2874 if (group == 0) { /* 2GHz band */ 2875 if (sc->mac_ver >= 0x3070) 2876 agc = 0x1c + sc->lna[0] * 2; 2877 else 2878 agc = 0x2e + sc->lna[0]; 2879 } else { /* 5GHz band */ 2880 if (sc->mac_ver == 0x5592) 2881 agc = 0x24 + sc->lna[group] * 2; 2882 else if (sc->mac_ver == 0x3572 || sc->mac_ver == 0x3593) 2883 agc = 0x22 + (sc->lna[group] * 5) / 3; 2884 else 2885 agc = 0x32 + (sc->lna[group] * 5) / 3; 2886 } 2887 run_set_agc(sc, agc); 2888 } 2889 2890 void 2891 run_rt2870_set_chan(struct run_softc *sc, u_int chan) 2892 { 2893 const struct rfprog *rfprog = rt2860_rf2850; 2894 uint32_t r2, r3, r4; 2895 int8_t txpow1, txpow2; 2896 int i; 2897 2898 /* find the settings for this channel (we know it exists) */ 2899 for (i = 0; rfprog[i].chan != chan; i++); 2900 2901 r2 = rfprog[i].r2; 2902 if (sc->ntxchains == 1) 2903 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2904 if (sc->nrxchains == 1) 2905 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2906 else if (sc->nrxchains == 2) 2907 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2908 2909 /* use Tx power values from EEPROM */ 2910 txpow1 = sc->txpow1[i]; 2911 txpow2 = sc->txpow2[i]; 2912 if (chan > 14) { 2913 if (txpow1 >= 0) 2914 txpow1 = txpow1 << 1 | 1; 2915 else 2916 txpow1 = (7 + txpow1) << 1; 2917 if (txpow2 >= 0) 2918 txpow2 = txpow2 << 1 | 1; 2919 else 2920 txpow2 = (7 + txpow2) << 1; 2921 } 2922 r3 = rfprog[i].r3 | txpow1 << 7; 2923 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2924 2925 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2926 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2927 run_rt2870_rf_write(sc, RT2860_RF3, r3); 2928 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2929 2930 DELAY(200); 2931 2932 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2933 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2934 run_rt2870_rf_write(sc, RT2860_RF3, r3 | 1); 2935 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2936 2937 DELAY(200); 2938 2939 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2940 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2941 run_rt2870_rf_write(sc, RT2860_RF3, r3); 2942 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2943 } 2944 2945 void 2946 run_rt3070_set_chan(struct run_softc *sc, u_int chan) 2947 { 2948 int8_t txpow1, txpow2; 2949 uint8_t rf; 2950 int i; 2951 2952 /* find the settings for this channel (we know it exists) */ 2953 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2954 2955 /* use Tx power values from EEPROM */ 2956 txpow1 = sc->txpow1[i]; 2957 txpow2 = sc->txpow2[i]; 2958 2959 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 2960 2961 /* RT3370/RT3390: RF R3 [7:4] is not reserved bits. */ 2962 run_rt3070_rf_read(sc, 3, &rf); 2963 rf = (rf & ~0x0f) | rt3070_freqs[i].k; 2964 run_rt3070_rf_write(sc, 3, rf); 2965 2966 run_rt3070_rf_read(sc, 6, &rf); 2967 rf = (rf & ~0x03) | rt3070_freqs[i].r; 2968 run_rt3070_rf_write(sc, 6, rf); 2969 2970 /* set Tx0 power */ 2971 run_rt3070_rf_read(sc, 12, &rf); 2972 rf = (rf & ~0x1f) | txpow1; 2973 run_rt3070_rf_write(sc, 12, rf); 2974 2975 /* set Tx1 power */ 2976 run_rt3070_rf_read(sc, 13, &rf); 2977 rf = (rf & ~0x1f) | txpow2; 2978 run_rt3070_rf_write(sc, 13, rf); 2979 2980 run_rt3070_rf_read(sc, 1, &rf); 2981 rf &= ~0xfc; 2982 if (sc->ntxchains == 1) 2983 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 2984 else if (sc->ntxchains == 2) 2985 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 2986 if (sc->nrxchains == 1) 2987 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2988 else if (sc->nrxchains == 2) 2989 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 2990 run_rt3070_rf_write(sc, 1, rf); 2991 2992 /* set RF offset */ 2993 run_rt3070_rf_read(sc, 23, &rf); 2994 rf = (rf & ~0x7f) | sc->freq; 2995 run_rt3070_rf_write(sc, 23, rf); 2996 2997 /* program RF filter */ 2998 run_rt3070_rf_read(sc, 24, &rf); /* Tx */ 2999 rf = (rf & ~0x3f) | sc->rf24_20mhz; 3000 run_rt3070_rf_write(sc, 24, rf); 3001 run_rt3070_rf_read(sc, 31, &rf); /* Rx */ 3002 rf = (rf & ~0x3f) | sc->rf24_20mhz; 3003 run_rt3070_rf_write(sc, 31, rf); 3004 3005 /* enable RF tuning */ 3006 run_rt3070_rf_read(sc, 7, &rf); 3007 run_rt3070_rf_write(sc, 7, rf | 0x01); 3008 } 3009 3010 void 3011 run_rt3572_set_chan(struct run_softc *sc, u_int chan) 3012 { 3013 int8_t txpow1, txpow2; 3014 uint32_t tmp; 3015 uint8_t rf; 3016 int i; 3017 3018 /* find the settings for this channel (we know it exists) */ 3019 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3020 3021 /* use Tx power values from EEPROM */ 3022 txpow1 = sc->txpow1[i]; 3023 txpow2 = sc->txpow2[i]; 3024 3025 if (chan <= 14) { 3026 run_bbp_write(sc, 25, sc->bbp25); 3027 run_bbp_write(sc, 26, sc->bbp26); 3028 } else { 3029 /* enable IQ phase correction */ 3030 run_bbp_write(sc, 25, 0x09); 3031 run_bbp_write(sc, 26, 0xff); 3032 } 3033 3034 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 3035 run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k); 3036 run_rt3070_rf_read(sc, 6, &rf); 3037 rf = (rf & ~0x0f) | rt3070_freqs[i].r; 3038 rf |= (chan <= 14) ? 0x08 : 0x04; 3039 run_rt3070_rf_write(sc, 6, rf); 3040 3041 /* set PLL mode */ 3042 run_rt3070_rf_read(sc, 5, &rf); 3043 rf &= ~(0x08 | 0x04); 3044 rf |= (chan <= 14) ? 0x04 : 0x08; 3045 run_rt3070_rf_write(sc, 5, rf); 3046 3047 /* set Tx power for chain 0 */ 3048 if (chan <= 14) 3049 rf = 0x60 | txpow1; 3050 else 3051 rf = 0xe0 | (txpow1 & 0xc) << 1 | (txpow1 & 0x3); 3052 run_rt3070_rf_write(sc, 12, rf); 3053 3054 /* set Tx power for chain 1 */ 3055 if (chan <= 14) 3056 rf = 0x60 | txpow2; 3057 else 3058 rf = 0xe0 | (txpow2 & 0xc) << 1 | (txpow2 & 0x3); 3059 run_rt3070_rf_write(sc, 13, rf); 3060 3061 /* set Tx/Rx streams */ 3062 run_rt3070_rf_read(sc, 1, &rf); 3063 rf &= ~0xfc; 3064 if (sc->ntxchains == 1) 3065 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 3066 else if (sc->ntxchains == 2) 3067 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 3068 if (sc->nrxchains == 1) 3069 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 3070 else if (sc->nrxchains == 2) 3071 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 3072 run_rt3070_rf_write(sc, 1, rf); 3073 3074 /* set RF offset */ 3075 run_rt3070_rf_read(sc, 23, &rf); 3076 rf = (rf & ~0x7f) | sc->freq; 3077 run_rt3070_rf_write(sc, 23, rf); 3078 3079 /* program RF filter */ 3080 rf = sc->rf24_20mhz; 3081 run_rt3070_rf_write(sc, 24, rf); /* Tx */ 3082 run_rt3070_rf_write(sc, 31, rf); /* Rx */ 3083 3084 /* enable RF tuning */ 3085 run_rt3070_rf_read(sc, 7, &rf); 3086 rf = (chan <= 14) ? 0xd8 : ((rf & ~0xc8) | 0x14); 3087 run_rt3070_rf_write(sc, 7, rf); 3088 3089 /* TSSI */ 3090 rf = (chan <= 14) ? 0xc3 : 0xc0; 3091 run_rt3070_rf_write(sc, 9, rf); 3092 3093 /* set loop filter 1 */ 3094 run_rt3070_rf_write(sc, 10, 0xf1); 3095 /* set loop filter 2 */ 3096 run_rt3070_rf_write(sc, 11, (chan <= 14) ? 0xb9 : 0x00); 3097 3098 /* set tx_mx2_ic */ 3099 run_rt3070_rf_write(sc, 15, (chan <= 14) ? 0x53 : 0x43); 3100 /* set tx_mx1_ic */ 3101 if (chan <= 14) 3102 rf = 0x48 | sc->txmixgain_2ghz; 3103 else 3104 rf = 0x78 | sc->txmixgain_5ghz; 3105 run_rt3070_rf_write(sc, 16, rf); 3106 3107 /* set tx_lo1 */ 3108 run_rt3070_rf_write(sc, 17, 0x23); 3109 /* set tx_lo2 */ 3110 if (chan <= 14) 3111 rf = 0x93; 3112 else if (chan <= 64) 3113 rf = 0xb7; 3114 else if (chan <= 128) 3115 rf = 0x74; 3116 else 3117 rf = 0x72; 3118 run_rt3070_rf_write(sc, 19, rf); 3119 3120 /* set rx_lo1 */ 3121 if (chan <= 14) 3122 rf = 0xb3; 3123 else if (chan <= 64) 3124 rf = 0xf6; 3125 else if (chan <= 128) 3126 rf = 0xf4; 3127 else 3128 rf = 0xf3; 3129 run_rt3070_rf_write(sc, 20, rf); 3130 3131 /* set pfd_delay */ 3132 if (chan <= 14) 3133 rf = 0x15; 3134 else if (chan <= 64) 3135 rf = 0x3d; 3136 else 3137 rf = 0x01; 3138 run_rt3070_rf_write(sc, 25, rf); 3139 3140 /* set rx_lo2 */ 3141 run_rt3070_rf_write(sc, 26, (chan <= 14) ? 0x85 : 0x87); 3142 /* set ldo_rf_vc */ 3143 run_rt3070_rf_write(sc, 27, (chan <= 14) ? 0x00 : 0x01); 3144 /* set drv_cc */ 3145 run_rt3070_rf_write(sc, 29, (chan <= 14) ? 0x9b : 0x9f); 3146 3147 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3148 tmp &= ~0x8080; 3149 if (chan <= 14) 3150 tmp |= 0x80; 3151 run_write(sc, RT2860_GPIO_CTRL, tmp); 3152 3153 /* enable RF tuning */ 3154 run_rt3070_rf_read(sc, 7, &rf); 3155 run_rt3070_rf_write(sc, 7, rf | 0x01); 3156 3157 DELAY(2000); 3158 } 3159 3160 void 3161 run_rt3593_set_chan(struct run_softc *sc, u_int chan) 3162 { 3163 int8_t txpow1, txpow2, txpow3; 3164 uint8_t h20mhz, rf; 3165 int i; 3166 3167 /* find the settings for this channel (we know it exists) */ 3168 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3169 3170 /* use Tx power values from EEPROM */ 3171 txpow1 = sc->txpow1[i]; 3172 txpow2 = sc->txpow2[i]; 3173 txpow3 = (sc->ntxchains == 3) ? sc->txpow3[i] : 0; 3174 3175 if (chan <= 14) { 3176 run_bbp_write(sc, 25, sc->bbp25); 3177 run_bbp_write(sc, 26, sc->bbp26); 3178 } else { 3179 /* Enable IQ phase correction. */ 3180 run_bbp_write(sc, 25, 0x09); 3181 run_bbp_write(sc, 26, 0xff); 3182 } 3183 3184 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3185 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3186 run_rt3070_rf_read(sc, 11, &rf); 3187 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3188 run_rt3070_rf_write(sc, 11, rf); 3189 3190 /* Set pll_idoh. */ 3191 run_rt3070_rf_read(sc, 11, &rf); 3192 rf &= ~0x4c; 3193 rf |= (chan <= 14) ? 0x44 : 0x48; 3194 run_rt3070_rf_write(sc, 11, rf); 3195 3196 if (chan <= 14) 3197 rf = txpow1 & 0x1f; 3198 else 3199 rf = 0x40 | ((txpow1 & 0x18) << 1) | (txpow1 & 0x07); 3200 run_rt3070_rf_write(sc, 53, rf); 3201 3202 if (chan <= 14) 3203 rf = txpow2 & 0x1f; 3204 else 3205 rf = 0x40 | ((txpow2 & 0x18) << 1) | (txpow2 & 0x07); 3206 run_rt3070_rf_write(sc, 55, rf); 3207 3208 if (chan <= 14) 3209 rf = txpow3 & 0x1f; 3210 else 3211 rf = 0x40 | ((txpow3 & 0x18) << 1) | (txpow3 & 0x07); 3212 run_rt3070_rf_write(sc, 54, rf); 3213 3214 rf = RT3070_RF_BLOCK | RT3070_PLL_PD; 3215 if (sc->ntxchains == 3) 3216 rf |= RT3070_TX0_PD | RT3070_TX1_PD | RT3070_TX2_PD; 3217 else 3218 rf |= RT3070_TX0_PD | RT3070_TX1_PD; 3219 rf |= RT3070_RX0_PD | RT3070_RX1_PD | RT3070_RX2_PD; 3220 run_rt3070_rf_write(sc, 1, rf); 3221 3222 run_adjust_freq_offset(sc); 3223 3224 run_rt3070_rf_write(sc, 31, (chan <= 14) ? 0xa0 : 0x80); 3225 3226 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 3227 run_rt3070_rf_read(sc, 30, &rf); 3228 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 3229 run_rt3070_rf_write(sc, 30, rf); 3230 3231 run_rt3070_rf_read(sc, 36, &rf); 3232 if (chan <= 14) 3233 rf |= 0x80; 3234 else 3235 rf &= ~0x80; 3236 run_rt3070_rf_write(sc, 36, rf); 3237 3238 /* Set vcolo_bs. */ 3239 run_rt3070_rf_write(sc, 34, (chan <= 14) ? 0x3c : 0x20); 3240 /* Set pfd_delay. */ 3241 run_rt3070_rf_write(sc, 12, (chan <= 14) ? 0x1a : 0x12); 3242 3243 /* Set vco bias current control. */ 3244 run_rt3070_rf_read(sc, 6, &rf); 3245 rf &= ~0xc0; 3246 if (chan <= 14) 3247 rf |= 0x40; 3248 else if (chan <= 128) 3249 rf |= 0x80; 3250 else 3251 rf |= 0x40; 3252 run_rt3070_rf_write(sc, 6, rf); 3253 3254 run_rt3070_rf_read(sc, 30, &rf); 3255 rf = (rf & ~0x18) | 0x10; 3256 run_rt3070_rf_write(sc, 30, rf); 3257 3258 run_rt3070_rf_write(sc, 10, (chan <= 14) ? 0xd3 : 0xd8); 3259 run_rt3070_rf_write(sc, 13, (chan <= 14) ? 0x12 : 0x23); 3260 3261 run_rt3070_rf_read(sc, 51, &rf); 3262 rf = (rf & ~0x03) | 0x01; 3263 run_rt3070_rf_write(sc, 51, rf); 3264 /* Set tx_mx1_cc. */ 3265 run_rt3070_rf_read(sc, 51, &rf); 3266 rf &= ~0x1c; 3267 rf |= (chan <= 14) ? 0x14 : 0x10; 3268 run_rt3070_rf_write(sc, 51, rf); 3269 /* Set tx_mx1_ic. */ 3270 run_rt3070_rf_read(sc, 51, &rf); 3271 rf &= ~0xe0; 3272 rf |= (chan <= 14) ? 0x60 : 0x40; 3273 run_rt3070_rf_write(sc, 51, rf); 3274 /* Set tx_lo1_ic. */ 3275 run_rt3070_rf_read(sc, 49, &rf); 3276 rf &= ~0x1c; 3277 rf |= (chan <= 14) ? 0x0c : 0x08; 3278 run_rt3070_rf_write(sc, 49, rf); 3279 /* Set tx_lo1_en. */ 3280 run_rt3070_rf_read(sc, 50, &rf); 3281 run_rt3070_rf_write(sc, 50, rf & ~0x20); 3282 /* Set drv_cc. */ 3283 run_rt3070_rf_read(sc, 57, &rf); 3284 rf &= ~0xfc; 3285 rf |= (chan <= 14) ? 0x6c : 0x3c; 3286 run_rt3070_rf_write(sc, 57, rf); 3287 /* Set rx_mix1_ic, rxa_lnactr, lna_vc, lna_inbias_en and lna_en. */ 3288 run_rt3070_rf_write(sc, 44, (chan <= 14) ? 0x93 : 0x9b); 3289 /* Set drv_gnd_a, tx_vga_cc_a and tx_mx2_gain. */ 3290 run_rt3070_rf_write(sc, 52, (chan <= 14) ? 0x45 : 0x05); 3291 /* Enable VCO calibration. */ 3292 run_rt3070_rf_read(sc, 3, &rf); 3293 rf &= ~RT3593_VCOCAL; 3294 rf |= (chan <= 14) ? RT3593_VCOCAL : 0xbe; 3295 run_rt3070_rf_write(sc, 3, rf); 3296 3297 if (chan <= 14) 3298 rf = 0x23; 3299 else if (chan <= 64) 3300 rf = 0x36; 3301 else if (chan <= 128) 3302 rf = 0x32; 3303 else 3304 rf = 0x30; 3305 run_rt3070_rf_write(sc, 39, rf); 3306 if (chan <= 14) 3307 rf = 0xbb; 3308 else if (chan <= 64) 3309 rf = 0xeb; 3310 else if (chan <= 128) 3311 rf = 0xb3; 3312 else 3313 rf = 0x9b; 3314 run_rt3070_rf_write(sc, 45, rf); 3315 3316 /* Set FEQ/AEQ control. */ 3317 run_bbp_write(sc, 105, 0x34); 3318 } 3319 3320 void 3321 run_rt5390_set_chan(struct run_softc *sc, u_int chan) 3322 { 3323 int8_t txpow1, txpow2; 3324 uint8_t rf; 3325 int i; 3326 3327 /* find the settings for this channel (we know it exists) */ 3328 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3329 3330 /* use Tx power values from EEPROM */ 3331 txpow1 = sc->txpow1[i]; 3332 txpow2 = sc->txpow2[i]; 3333 3334 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3335 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3336 run_rt3070_rf_read(sc, 11, &rf); 3337 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3338 run_rt3070_rf_write(sc, 11, rf); 3339 3340 run_rt3070_rf_read(sc, 49, &rf); 3341 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3342 /* The valid range of the RF R49 is 0x00 to 0x27. */ 3343 if ((rf & 0x3f) > 0x27) 3344 rf = (rf & ~0x3f) | 0x27; 3345 run_rt3070_rf_write(sc, 49, rf); 3346 3347 if (sc->mac_ver == 0x5392) { 3348 run_rt3070_rf_read(sc, 50, &rf); 3349 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3350 /* The valid range of the RF R50 is 0x00 to 0x27. */ 3351 if ((rf & 0x3f) > 0x27) 3352 rf = (rf & ~0x3f) | 0x27; 3353 run_rt3070_rf_write(sc, 50, rf); 3354 } 3355 3356 run_rt3070_rf_read(sc, 1, &rf); 3357 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 3358 if (sc->mac_ver == 0x5392) 3359 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 3360 run_rt3070_rf_write(sc, 1, rf); 3361 3362 if (sc->mac_ver != 0x5392) { 3363 run_rt3070_rf_read(sc, 2, &rf); 3364 rf |= 0x80; 3365 run_rt3070_rf_write(sc, 2, rf); 3366 DELAY(10); 3367 rf &= 0x7f; 3368 run_rt3070_rf_write(sc, 2, rf); 3369 } 3370 3371 run_adjust_freq_offset(sc); 3372 3373 if (sc->mac_ver == 0x5392) { 3374 /* Fix for RT5392C. */ 3375 if (sc->mac_rev >= 0x0223) { 3376 if (chan <= 4) 3377 rf = 0x0f; 3378 else if (chan >= 5 && chan <= 7) 3379 rf = 0x0e; 3380 else 3381 rf = 0x0d; 3382 run_rt3070_rf_write(sc, 23, rf); 3383 3384 if (chan <= 4) 3385 rf = 0x0c; 3386 else if (chan == 5) 3387 rf = 0x0b; 3388 else if (chan >= 6 && chan <= 7) 3389 rf = 0x0a; 3390 else if (chan >= 8 && chan <= 10) 3391 rf = 0x09; 3392 else 3393 rf = 0x08; 3394 run_rt3070_rf_write(sc, 59, rf); 3395 } else { 3396 if (chan <= 11) 3397 rf = 0x0f; 3398 else 3399 rf = 0x0b; 3400 run_rt3070_rf_write(sc, 59, rf); 3401 } 3402 } else { 3403 /* Fix for RT5390F. */ 3404 if (sc->mac_rev >= 0x0502) { 3405 if (chan <= 11) 3406 rf = 0x43; 3407 else 3408 rf = 0x23; 3409 run_rt3070_rf_write(sc, 55, rf); 3410 3411 if (chan <= 11) 3412 rf = 0x0f; 3413 else if (chan == 12) 3414 rf = 0x0d; 3415 else 3416 rf = 0x0b; 3417 run_rt3070_rf_write(sc, 59, rf); 3418 } else { 3419 run_rt3070_rf_write(sc, 55, 0x44); 3420 run_rt3070_rf_write(sc, 59, 0x8f); 3421 } 3422 } 3423 3424 /* Enable VCO calibration. */ 3425 run_rt3070_rf_read(sc, 3, &rf); 3426 rf |= RT3593_VCOCAL; 3427 run_rt3070_rf_write(sc, 3, rf); 3428 } 3429 3430 void 3431 run_rt5592_set_chan(struct run_softc *sc, u_int chan) 3432 { 3433 const struct rt5592_freqs *freqs; 3434 uint32_t tmp; 3435 uint8_t reg, rf, txpow_bound; 3436 int8_t txpow1, txpow2; 3437 int i; 3438 3439 run_read(sc, RT5592_DEBUG_INDEX, &tmp); 3440 freqs = (tmp & RT5592_SEL_XTAL) ? 3441 rt5592_freqs_40mhz : rt5592_freqs_20mhz; 3442 3443 /* find the settings for this channel (we know it exists) */ 3444 for (i = 0; rt2860_rf2850[i].chan != chan; i++, freqs++); 3445 3446 /* use Tx power values from EEPROM */ 3447 txpow1 = sc->txpow1[i]; 3448 txpow2 = sc->txpow2[i]; 3449 3450 run_read(sc, RT3070_LDO_CFG0, &tmp); 3451 tmp &= ~0x1c000000; 3452 if (chan > 14) 3453 tmp |= 0x14000000; 3454 run_write(sc, RT3070_LDO_CFG0, tmp); 3455 3456 /* N setting. */ 3457 run_rt3070_rf_write(sc, 8, freqs->n & 0xff); 3458 run_rt3070_rf_read(sc, 9, &rf); 3459 rf &= ~(1 << 4); 3460 rf |= ((freqs->n & 0x0100) >> 8) << 4; 3461 run_rt3070_rf_write(sc, 9, rf); 3462 3463 /* K setting. */ 3464 run_rt3070_rf_read(sc, 9, &rf); 3465 rf &= ~0x0f; 3466 rf |= (freqs->k & 0x0f); 3467 run_rt3070_rf_write(sc, 9, rf); 3468 3469 /* Mode setting. */ 3470 run_rt3070_rf_read(sc, 11, &rf); 3471 rf &= ~0x0c; 3472 rf |= ((freqs->m - 0x8) & 0x3) << 2; 3473 run_rt3070_rf_write(sc, 11, rf); 3474 run_rt3070_rf_read(sc, 9, &rf); 3475 rf &= ~(1 << 7); 3476 rf |= (((freqs->m - 0x8) & 0x4) >> 2) << 7; 3477 run_rt3070_rf_write(sc, 9, rf); 3478 3479 /* R setting. */ 3480 run_rt3070_rf_read(sc, 11, &rf); 3481 rf &= ~0x03; 3482 rf |= (freqs->r - 0x1); 3483 run_rt3070_rf_write(sc, 11, rf); 3484 3485 if (chan <= 14) { 3486 /* Initialize RF registers for 2GHZ. */ 3487 for (i = 0; i < nitems(rt5592_2ghz_def_rf); i++) { 3488 run_rt3070_rf_write(sc, rt5592_2ghz_def_rf[i].reg, 3489 rt5592_2ghz_def_rf[i].val); 3490 } 3491 3492 rf = (chan <= 10) ? 0x07 : 0x06; 3493 run_rt3070_rf_write(sc, 23, rf); 3494 run_rt3070_rf_write(sc, 59, rf); 3495 3496 run_rt3070_rf_write(sc, 55, 0x43); 3497 3498 /* 3499 * RF R49/R50 Tx power ALC code. 3500 * G-band bit<7:6>=1:0, bit<5:0> range from 0x0 ~ 0x27. 3501 */ 3502 reg = 2; 3503 txpow_bound = 0x27; 3504 } else { 3505 /* Initialize RF registers for 5GHZ. */ 3506 for (i = 0; i < nitems(rt5592_5ghz_def_rf); i++) { 3507 run_rt3070_rf_write(sc, rt5592_5ghz_def_rf[i].reg, 3508 rt5592_5ghz_def_rf[i].val); 3509 } 3510 for (i = 0; i < nitems(rt5592_chan_5ghz); i++) { 3511 if (chan >= rt5592_chan_5ghz[i].firstchan && 3512 chan <= rt5592_chan_5ghz[i].lastchan) { 3513 run_rt3070_rf_write(sc, rt5592_chan_5ghz[i].reg, 3514 rt5592_chan_5ghz[i].val); 3515 } 3516 } 3517 3518 /* 3519 * RF R49/R50 Tx power ALC code. 3520 * A-band bit<7:6>=1:1, bit<5:0> range from 0x0 ~ 0x2b. 3521 */ 3522 reg = 3; 3523 txpow_bound = 0x2b; 3524 } 3525 3526 /* RF R49 ch0 Tx power ALC code. */ 3527 run_rt3070_rf_read(sc, 49, &rf); 3528 rf &= ~0xc0; 3529 rf |= (reg << 6); 3530 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3531 if ((rf & 0x3f) > txpow_bound) 3532 rf = (rf & ~0x3f) | txpow_bound; 3533 run_rt3070_rf_write(sc, 49, rf); 3534 3535 /* RF R50 ch1 Tx power ALC code. */ 3536 run_rt3070_rf_read(sc, 50, &rf); 3537 rf &= ~(1 << 7 | 1 << 6); 3538 rf |= (reg << 6); 3539 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3540 if ((rf & 0x3f) > txpow_bound) 3541 rf = (rf & ~0x3f) | txpow_bound; 3542 run_rt3070_rf_write(sc, 50, rf); 3543 3544 /* Enable RF_BLOCK, PLL_PD, RX0_PD, and TX0_PD. */ 3545 run_rt3070_rf_read(sc, 1, &rf); 3546 rf |= (RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD); 3547 if (sc->ntxchains > 1) 3548 rf |= RT3070_TX1_PD; 3549 if (sc->nrxchains > 1) 3550 rf |= RT3070_RX1_PD; 3551 run_rt3070_rf_write(sc, 1, rf); 3552 3553 run_rt3070_rf_write(sc, 6, 0xe4); 3554 3555 run_rt3070_rf_write(sc, 30, 0x10); 3556 run_rt3070_rf_write(sc, 31, 0x80); 3557 run_rt3070_rf_write(sc, 32, 0x80); 3558 3559 run_adjust_freq_offset(sc); 3560 3561 /* Enable VCO calibration. */ 3562 run_rt3070_rf_read(sc, 3, &rf); 3563 rf |= RT3593_VCOCAL; 3564 run_rt3070_rf_write(sc, 3, rf); 3565 } 3566 3567 void 3568 run_set_agc(struct run_softc *sc, uint8_t agc) 3569 { 3570 uint8_t bbp; 3571 3572 if (sc->mac_ver == 0x3572) { 3573 run_bbp_read(sc, 27, &bbp); 3574 bbp &= ~(0x3 << 5); 3575 run_bbp_write(sc, 27, bbp | 0 << 5); /* select Rx0 */ 3576 run_bbp_write(sc, 66, agc); 3577 run_bbp_write(sc, 27, bbp | 1 << 5); /* select Rx1 */ 3578 run_bbp_write(sc, 66, agc); 3579 } else 3580 run_bbp_write(sc, 66, agc); 3581 } 3582 3583 void 3584 run_set_rx_antenna(struct run_softc *sc, int aux) 3585 { 3586 uint32_t tmp; 3587 uint8_t bbp152; 3588 3589 if (aux) { 3590 if (sc->rf_rev == RT5390_RF_5370) { 3591 run_bbp_read(sc, 152, &bbp152); 3592 run_bbp_write(sc, 152, bbp152 & ~0x80); 3593 } else { 3594 run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, 0); 3595 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3596 run_write(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08); 3597 } 3598 } else { 3599 if (sc->rf_rev == RT5390_RF_5370) { 3600 run_bbp_read(sc, 152, &bbp152); 3601 run_bbp_write(sc, 152, bbp152 | 0x80); 3602 } else { 3603 run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, 1); 3604 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3605 run_write(sc, RT2860_GPIO_CTRL, tmp & ~0x0808); 3606 } 3607 } 3608 } 3609 3610 int 3611 run_set_chan(struct run_softc *sc, struct ieee80211_channel *c) 3612 { 3613 struct ieee80211com *ic = &sc->sc_ic; 3614 u_int chan, group; 3615 3616 chan = ieee80211_chan2ieee(ic, c); 3617 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3618 return EINVAL; 3619 3620 if (sc->mac_ver == 0x5592) 3621 run_rt5592_set_chan(sc, chan); 3622 else if (sc->mac_ver >= 0x5390) 3623 run_rt5390_set_chan(sc, chan); 3624 else if (sc->mac_ver == 0x3593) 3625 run_rt3593_set_chan(sc, chan); 3626 else if (sc->mac_ver == 0x3572) 3627 run_rt3572_set_chan(sc, chan); 3628 else if (sc->mac_ver >= 0x3070) 3629 run_rt3070_set_chan(sc, chan); 3630 else 3631 run_rt2870_set_chan(sc, chan); 3632 3633 /* determine channel group */ 3634 if (chan <= 14) 3635 group = 0; 3636 else if (chan <= 64) 3637 group = 1; 3638 else if (chan <= 128) 3639 group = 2; 3640 else 3641 group = 3; 3642 3643 /* XXX necessary only when group has changed! */ 3644 run_select_chan_group(sc, group); 3645 3646 DELAY(1000); 3647 3648 /* Perform IQ calibration. */ 3649 if (sc->mac_ver >= 0x5392) 3650 run_iq_calib(sc, chan); 3651 3652 return 0; 3653 } 3654 3655 void 3656 run_enable_tsf_sync(struct run_softc *sc) 3657 { 3658 struct ieee80211com *ic = &sc->sc_ic; 3659 uint32_t tmp; 3660 3661 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 3662 tmp &= ~0x1fffff; 3663 tmp |= ic->ic_bss->ni_intval * 16; 3664 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 3665 /* local TSF is always updated with remote TSF on beacon reception */ 3666 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 3667 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 3668 } 3669 3670 void 3671 run_enable_mrr(struct run_softc *sc) 3672 { 3673 #define CCK(mcs) (mcs) 3674 #define OFDM(mcs) (1 << 3 | (mcs)) 3675 run_write(sc, RT2860_LG_FBK_CFG0, 3676 OFDM(6) << 28 | /* 54->48 */ 3677 OFDM(5) << 24 | /* 48->36 */ 3678 OFDM(4) << 20 | /* 36->24 */ 3679 OFDM(3) << 16 | /* 24->18 */ 3680 OFDM(2) << 12 | /* 18->12 */ 3681 OFDM(1) << 8 | /* 12-> 9 */ 3682 OFDM(0) << 4 | /* 9-> 6 */ 3683 OFDM(0)); /* 6-> 6 */ 3684 3685 run_write(sc, RT2860_LG_FBK_CFG1, 3686 CCK(2) << 12 | /* 11->5.5 */ 3687 CCK(1) << 8 | /* 5.5-> 2 */ 3688 CCK(0) << 4 | /* 2-> 1 */ 3689 CCK(0)); /* 1-> 1 */ 3690 #undef OFDM 3691 #undef CCK 3692 } 3693 3694 void 3695 run_set_txpreamble(struct run_softc *sc) 3696 { 3697 uint32_t tmp; 3698 3699 run_read(sc, RT2860_AUTO_RSP_CFG, &tmp); 3700 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 3701 tmp |= RT2860_CCK_SHORT_EN; 3702 else 3703 tmp &= ~RT2860_CCK_SHORT_EN; 3704 run_write(sc, RT2860_AUTO_RSP_CFG, tmp); 3705 } 3706 3707 void 3708 run_set_basicrates(struct run_softc *sc) 3709 { 3710 struct ieee80211com *ic = &sc->sc_ic; 3711 3712 /* set basic rates mask */ 3713 if (ic->ic_curmode == IEEE80211_MODE_11B) 3714 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x003); 3715 else if (ic->ic_curmode == IEEE80211_MODE_11A) 3716 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x150); 3717 else /* 11g */ 3718 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x15f); 3719 } 3720 3721 void 3722 run_set_leds(struct run_softc *sc, uint16_t which) 3723 { 3724 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 3725 which | (sc->leds & 0x7f)); 3726 } 3727 3728 void 3729 run_set_bssid(struct run_softc *sc, const uint8_t *bssid) 3730 { 3731 run_write(sc, RT2860_MAC_BSSID_DW0, 3732 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3733 run_write(sc, RT2860_MAC_BSSID_DW1, 3734 bssid[4] | bssid[5] << 8); 3735 } 3736 3737 void 3738 run_set_macaddr(struct run_softc *sc, const uint8_t *addr) 3739 { 3740 run_write(sc, RT2860_MAC_ADDR_DW0, 3741 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3742 run_write(sc, RT2860_MAC_ADDR_DW1, 3743 addr[4] | addr[5] << 8 | 0xff << 16); 3744 } 3745 3746 void 3747 run_updateslot(struct ieee80211com *ic) 3748 { 3749 /* do it in a process context */ 3750 run_do_async(ic->ic_softc, run_updateslot_cb, NULL, 0); 3751 } 3752 3753 /* ARGSUSED */ 3754 void 3755 run_updateslot_cb(struct run_softc *sc, void *arg) 3756 { 3757 uint32_t tmp; 3758 3759 run_read(sc, RT2860_BKOFF_SLOT_CFG, &tmp); 3760 tmp &= ~0xff; 3761 tmp |= (sc->sc_ic.ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 3762 run_write(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3763 } 3764 3765 #if NBPFILTER > 0 3766 int8_t 3767 run_rssi2dbm(struct run_softc *sc, uint8_t rssi, uint8_t rxchain) 3768 { 3769 struct ieee80211com *ic = &sc->sc_ic; 3770 struct ieee80211_channel *c = ic->ic_ibss_chan; 3771 int delta; 3772 3773 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3774 u_int chan = ieee80211_chan2ieee(ic, c); 3775 delta = sc->rssi_5ghz[rxchain]; 3776 3777 /* determine channel group */ 3778 if (chan <= 64) 3779 delta -= sc->lna[1]; 3780 else if (chan <= 128) 3781 delta -= sc->lna[2]; 3782 else 3783 delta -= sc->lna[3]; 3784 } else 3785 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3786 3787 return -12 - delta - rssi; 3788 } 3789 #endif 3790 3791 void 3792 run_rt5390_bbp_init(struct run_softc *sc) 3793 { 3794 int i; 3795 uint8_t bbp; 3796 3797 /* Apply maximum likelihood detection for 2 stream case. */ 3798 run_bbp_read(sc, 105, &bbp); 3799 if (sc->nrxchains > 1) 3800 run_bbp_write(sc, 105, bbp | RT5390_MLD); 3801 3802 /* Avoid data lost and CRC error. */ 3803 run_bbp_read(sc, 4, &bbp); 3804 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3805 3806 if (sc->mac_ver == 0x5592) { 3807 for (i = 0; i < nitems(rt5592_def_bbp); i++) { 3808 run_bbp_write(sc, rt5592_def_bbp[i].reg, 3809 rt5592_def_bbp[i].val); 3810 } 3811 for (i = 0; i < nitems(rt5592_bbp_r196); i++) { 3812 run_bbp_write(sc, 195, i + 0x80); 3813 run_bbp_write(sc, 196, rt5592_bbp_r196[i]); 3814 } 3815 } else { 3816 for (i = 0; i < nitems(rt5390_def_bbp); i++) { 3817 run_bbp_write(sc, rt5390_def_bbp[i].reg, 3818 rt5390_def_bbp[i].val); 3819 } 3820 } 3821 if (sc->mac_ver == 0x5392) { 3822 run_bbp_write(sc, 88, 0x90); 3823 run_bbp_write(sc, 95, 0x9a); 3824 run_bbp_write(sc, 98, 0x12); 3825 run_bbp_write(sc, 106, 0x12); 3826 run_bbp_write(sc, 134, 0xd0); 3827 run_bbp_write(sc, 135, 0xf6); 3828 run_bbp_write(sc, 148, 0x84); 3829 } 3830 3831 run_bbp_read(sc, 152, &bbp); 3832 run_bbp_write(sc, 152, bbp | 0x80); 3833 3834 /* Fix BBP254 for RT5592C. */ 3835 if (sc->mac_ver == 0x5592 && sc->mac_rev >= 0x0221) { 3836 run_bbp_read(sc, 254, &bbp); 3837 run_bbp_write(sc, 254, bbp | 0x80); 3838 } 3839 3840 /* Disable hardware antenna diversity. */ 3841 if (sc->mac_ver == 0x5390) 3842 run_bbp_write(sc, 154, 0); 3843 3844 /* Initialize Rx CCK/OFDM frequency offset report. */ 3845 run_bbp_write(sc, 142, 1); 3846 run_bbp_write(sc, 143, 57); 3847 } 3848 3849 int 3850 run_bbp_init(struct run_softc *sc) 3851 { 3852 int i, error, ntries; 3853 uint8_t bbp0; 3854 3855 /* wait for BBP to wake up */ 3856 for (ntries = 0; ntries < 20; ntries++) { 3857 if ((error = run_bbp_read(sc, 0, &bbp0)) != 0) 3858 return error; 3859 if (bbp0 != 0 && bbp0 != 0xff) 3860 break; 3861 } 3862 if (ntries == 20) 3863 return ETIMEDOUT; 3864 3865 /* initialize BBP registers to default values */ 3866 if (sc->mac_ver >= 0x5390) 3867 run_rt5390_bbp_init(sc); 3868 else { 3869 for (i = 0; i < nitems(rt2860_def_bbp); i++) { 3870 run_bbp_write(sc, rt2860_def_bbp[i].reg, 3871 rt2860_def_bbp[i].val); 3872 } 3873 } 3874 3875 if (sc->mac_ver == 0x3593) { 3876 run_bbp_write(sc, 79, 0x13); 3877 run_bbp_write(sc, 80, 0x05); 3878 run_bbp_write(sc, 81, 0x33); 3879 run_bbp_write(sc, 86, 0x46); 3880 run_bbp_write(sc, 137, 0x0f); 3881 } 3882 3883 /* fix BBP84 for RT2860E */ 3884 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3885 run_bbp_write(sc, 84, 0x19); 3886 3887 if (sc->mac_ver >= 0x3070 && (sc->mac_ver != 0x3593 && 3888 sc->mac_ver != 0x5592)) { 3889 run_bbp_write(sc, 79, 0x13); 3890 run_bbp_write(sc, 80, 0x05); 3891 run_bbp_write(sc, 81, 0x33); 3892 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3893 run_bbp_write(sc, 69, 0x16); 3894 run_bbp_write(sc, 73, 0x12); 3895 } 3896 return 0; 3897 } 3898 3899 int 3900 run_rt3070_rf_init(struct run_softc *sc) 3901 { 3902 uint32_t tmp; 3903 uint8_t bbp4, mingain, rf, target; 3904 int i; 3905 3906 run_rt3070_rf_read(sc, 30, &rf); 3907 /* toggle RF R30 bit 7 */ 3908 run_rt3070_rf_write(sc, 30, rf | 0x80); 3909 DELAY(1000); 3910 run_rt3070_rf_write(sc, 30, rf & ~0x80); 3911 3912 /* initialize RF registers to default value */ 3913 if (sc->mac_ver == 0x3572) { 3914 for (i = 0; i < nitems(rt3572_def_rf); i++) { 3915 run_rt3070_rf_write(sc, rt3572_def_rf[i].reg, 3916 rt3572_def_rf[i].val); 3917 } 3918 } else { 3919 for (i = 0; i < nitems(rt3070_def_rf); i++) { 3920 run_rt3070_rf_write(sc, rt3070_def_rf[i].reg, 3921 rt3070_def_rf[i].val); 3922 } 3923 } 3924 if (sc->mac_ver == 0x3070 && sc->mac_rev < 0x0201) { 3925 /* 3926 * Change voltage from 1.2V to 1.35V for RT3070. 3927 * The DAC issue (RT3070_LDO_CFG0) has been fixed 3928 * in RT3070(F). 3929 */ 3930 run_read(sc, RT3070_LDO_CFG0, &tmp); 3931 tmp = (tmp & ~0x0f000000) | 0x0d000000; 3932 run_write(sc, RT3070_LDO_CFG0, tmp); 3933 3934 } else if (sc->mac_ver == 0x3071) { 3935 run_rt3070_rf_read(sc, 6, &rf); 3936 run_rt3070_rf_write(sc, 6, rf | 0x40); 3937 run_rt3070_rf_write(sc, 31, 0x14); 3938 3939 run_read(sc, RT3070_LDO_CFG0, &tmp); 3940 tmp &= ~0x1f000000; 3941 if (sc->mac_rev < 0x0211) 3942 tmp |= 0x0d000000; /* 1.35V */ 3943 else 3944 tmp |= 0x01000000; /* 1.2V */ 3945 run_write(sc, RT3070_LDO_CFG0, tmp); 3946 3947 /* patch LNA_PE_G1 */ 3948 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 3949 run_write(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 3950 3951 } else if (sc->mac_ver == 0x3572) { 3952 run_rt3070_rf_read(sc, 6, &rf); 3953 run_rt3070_rf_write(sc, 6, rf | 0x40); 3954 /* increase voltage from 1.2V to 1.35V */ 3955 run_read(sc, RT3070_LDO_CFG0, &tmp); 3956 tmp = (tmp & ~0x1f000000) | 0x0d000000; 3957 run_write(sc, RT3070_LDO_CFG0, tmp); 3958 3959 if (sc->mac_rev < 0x0211 || !sc->patch_dac) { 3960 DELAY(1); /* wait for 1msec */ 3961 /* decrease voltage back to 1.2V */ 3962 tmp = (tmp & ~0x1f000000) | 0x01000000; 3963 run_write(sc, RT3070_LDO_CFG0, tmp); 3964 } 3965 } 3966 3967 /* select 20MHz bandwidth */ 3968 run_rt3070_rf_read(sc, 31, &rf); 3969 run_rt3070_rf_write(sc, 31, rf & ~0x20); 3970 3971 /* calibrate filter for 20MHz bandwidth */ 3972 sc->rf24_20mhz = 0x1f; /* default value */ 3973 target = (sc->mac_ver < 0x3071) ? 0x16 : 0x13; 3974 run_rt3070_filter_calib(sc, 0x07, target, &sc->rf24_20mhz); 3975 3976 /* select 40MHz bandwidth */ 3977 run_bbp_read(sc, 4, &bbp4); 3978 run_bbp_write(sc, 4, (bbp4 & ~0x18) | 0x10); 3979 run_rt3070_rf_read(sc, 31, &rf); 3980 run_rt3070_rf_write(sc, 31, rf | 0x20); 3981 3982 /* calibrate filter for 40MHz bandwidth */ 3983 sc->rf24_40mhz = 0x2f; /* default value */ 3984 target = (sc->mac_ver < 0x3071) ? 0x19 : 0x15; 3985 run_rt3070_filter_calib(sc, 0x27, target, &sc->rf24_40mhz); 3986 3987 /* go back to 20MHz bandwidth */ 3988 run_bbp_read(sc, 4, &bbp4); 3989 run_bbp_write(sc, 4, bbp4 & ~0x18); 3990 3991 if (sc->mac_ver == 0x3572) { 3992 /* save default BBP registers 25 and 26 values */ 3993 run_bbp_read(sc, 25, &sc->bbp25); 3994 run_bbp_read(sc, 26, &sc->bbp26); 3995 3996 } else if (sc->mac_rev < 0x0201 || sc->mac_rev < 0x0211) 3997 run_rt3070_rf_write(sc, 27, 0x03); 3998 3999 run_read(sc, RT3070_OPT_14, &tmp); 4000 run_write(sc, RT3070_OPT_14, tmp | 1); 4001 4002 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 4003 run_rt3070_rf_read(sc, 17, &rf); 4004 rf &= ~RT3070_TX_LO1; 4005 if ((sc->mac_ver == 0x3070 || 4006 (sc->mac_ver == 0x3071 && sc->mac_rev >= 0x0211)) && 4007 !sc->ext_2ghz_lna) 4008 rf |= 0x20; /* fix for long range Rx issue */ 4009 mingain = (sc->mac_ver == 0x3070) ? 1 : 2; 4010 if (sc->txmixgain_2ghz >= mingain) 4011 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 4012 run_rt3070_rf_write(sc, 17, rf); 4013 } 4014 if (sc->mac_ver == 0x3071) { 4015 run_rt3070_rf_read(sc, 1, &rf); 4016 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 4017 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 4018 run_rt3070_rf_write(sc, 1, rf); 4019 4020 run_rt3070_rf_read(sc, 15, &rf); 4021 run_rt3070_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 4022 4023 run_rt3070_rf_read(sc, 20, &rf); 4024 run_rt3070_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 4025 4026 run_rt3070_rf_read(sc, 21, &rf); 4027 run_rt3070_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 4028 } 4029 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 4030 /* fix Tx to Rx IQ glitch by raising RF voltage */ 4031 run_rt3070_rf_read(sc, 27, &rf); 4032 rf &= ~0x77; 4033 if (sc->mac_rev < 0x0211) 4034 rf |= 0x03; 4035 run_rt3070_rf_write(sc, 27, rf); 4036 } 4037 return 0; 4038 } 4039 4040 void 4041 run_rt3593_rf_init(struct run_softc *sc) 4042 { 4043 uint32_t tmp; 4044 uint8_t rf; 4045 int i; 4046 4047 /* Disable the GPIO bits 4 and 7 for LNA PE control. */ 4048 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 4049 tmp &= ~(1 << 4 | 1 << 7); 4050 run_write(sc, RT3070_GPIO_SWITCH, tmp); 4051 4052 /* Initialize RF registers to default value. */ 4053 for (i = 0; i < nitems(rt3593_def_rf); i++) { 4054 run_rt3070_rf_write(sc, rt3593_def_rf[i].reg, 4055 rt3593_def_rf[i].val); 4056 } 4057 4058 /* Toggle RF R2 to initiate calibration. */ 4059 run_rt3070_rf_write(sc, 2, RT3593_RESCAL); 4060 4061 /* Initialize RF frequency offset. */ 4062 run_adjust_freq_offset(sc); 4063 4064 run_rt3070_rf_read(sc, 18, &rf); 4065 run_rt3070_rf_write(sc, 18, rf | RT3593_AUTOTUNE_BYPASS); 4066 4067 /* 4068 * Increase voltage from 1.2V to 1.35V, wait for 1 msec to 4069 * decrease voltage back to 1.2V. 4070 */ 4071 run_read(sc, RT3070_LDO_CFG0, &tmp); 4072 tmp = (tmp & ~0x1f000000) | 0x0d000000; 4073 run_write(sc, RT3070_LDO_CFG0, tmp); 4074 DELAY(1); 4075 tmp = (tmp & ~0x1f000000) | 0x01000000; 4076 run_write(sc, RT3070_LDO_CFG0, tmp); 4077 4078 sc->rf24_20mhz = 0x1f; 4079 sc->rf24_40mhz = 0x2f; 4080 4081 /* Save default BBP registers 25 and 26 values. */ 4082 run_bbp_read(sc, 25, &sc->bbp25); 4083 run_bbp_read(sc, 26, &sc->bbp26); 4084 4085 run_read(sc, RT3070_OPT_14, &tmp); 4086 run_write(sc, RT3070_OPT_14, tmp | 1); 4087 } 4088 4089 void 4090 run_rt5390_rf_init(struct run_softc *sc) 4091 { 4092 uint32_t tmp; 4093 uint8_t rf; 4094 int i; 4095 4096 /* Toggle RF R2 to initiate calibration. */ 4097 if (sc->mac_ver == 0x5390) { 4098 run_rt3070_rf_read(sc, 2, &rf); 4099 run_rt3070_rf_write(sc, 2, rf | RT3593_RESCAL); 4100 DELAY(10); 4101 run_rt3070_rf_write(sc, 2, rf & ~RT3593_RESCAL); 4102 } else { 4103 run_rt3070_rf_write(sc, 2, RT3593_RESCAL); 4104 DELAY(10); 4105 } 4106 4107 /* Initialize RF registers to default value. */ 4108 if (sc->mac_ver == 0x5592) { 4109 for (i = 0; i < nitems(rt5592_def_rf); i++) { 4110 run_rt3070_rf_write(sc, rt5592_def_rf[i].reg, 4111 rt5592_def_rf[i].val); 4112 } 4113 /* Initialize RF frequency offset. */ 4114 run_adjust_freq_offset(sc); 4115 } else if (sc->mac_ver == 0x5392) { 4116 for (i = 0; i < nitems(rt5392_def_rf); i++) { 4117 run_rt3070_rf_write(sc, rt5392_def_rf[i].reg, 4118 rt5392_def_rf[i].val); 4119 } 4120 if (sc->mac_rev >= 0x0223) { 4121 run_rt3070_rf_write(sc, 23, 0x0f); 4122 run_rt3070_rf_write(sc, 24, 0x3e); 4123 run_rt3070_rf_write(sc, 51, 0x32); 4124 run_rt3070_rf_write(sc, 53, 0x22); 4125 run_rt3070_rf_write(sc, 56, 0xc1); 4126 run_rt3070_rf_write(sc, 59, 0x0f); 4127 } 4128 } else { 4129 for (i = 0; i < nitems(rt5390_def_rf); i++) { 4130 run_rt3070_rf_write(sc, rt5390_def_rf[i].reg, 4131 rt5390_def_rf[i].val); 4132 } 4133 if (sc->mac_rev >= 0x0502) { 4134 run_rt3070_rf_write(sc, 6, 0xe0); 4135 run_rt3070_rf_write(sc, 25, 0x80); 4136 run_rt3070_rf_write(sc, 46, 0x73); 4137 run_rt3070_rf_write(sc, 53, 0x00); 4138 run_rt3070_rf_write(sc, 56, 0x42); 4139 run_rt3070_rf_write(sc, 61, 0xd1); 4140 } 4141 } 4142 4143 sc->rf24_20mhz = 0x1f; /* default value */ 4144 sc->rf24_40mhz = (sc->mac_ver == 0x5592) ? 0 : 0x2f; 4145 4146 if (sc->mac_rev < 0x0211) 4147 run_rt3070_rf_write(sc, 27, 0x3); 4148 4149 run_read(sc, RT3070_OPT_14, &tmp); 4150 run_write(sc, RT3070_OPT_14, tmp | 1); 4151 } 4152 4153 int 4154 run_rt3070_filter_calib(struct run_softc *sc, uint8_t init, uint8_t target, 4155 uint8_t *val) 4156 { 4157 uint8_t rf22, rf24; 4158 uint8_t bbp55_pb, bbp55_sb, delta; 4159 int ntries; 4160 4161 /* program filter */ 4162 run_rt3070_rf_read(sc, 24, &rf24); 4163 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 4164 run_rt3070_rf_write(sc, 24, rf24); 4165 4166 /* enable baseband loopback mode */ 4167 run_rt3070_rf_read(sc, 22, &rf22); 4168 run_rt3070_rf_write(sc, 22, rf22 | 0x01); 4169 4170 /* set power and frequency of passband test tone */ 4171 run_bbp_write(sc, 24, 0x00); 4172 for (ntries = 0; ntries < 100; ntries++) { 4173 /* transmit test tone */ 4174 run_bbp_write(sc, 25, 0x90); 4175 DELAY(1000); 4176 /* read received power */ 4177 run_bbp_read(sc, 55, &bbp55_pb); 4178 if (bbp55_pb != 0) 4179 break; 4180 } 4181 if (ntries == 100) 4182 return ETIMEDOUT; 4183 4184 /* set power and frequency of stopband test tone */ 4185 run_bbp_write(sc, 24, 0x06); 4186 for (ntries = 0; ntries < 100; ntries++) { 4187 /* transmit test tone */ 4188 run_bbp_write(sc, 25, 0x90); 4189 DELAY(1000); 4190 /* read received power */ 4191 run_bbp_read(sc, 55, &bbp55_sb); 4192 4193 delta = bbp55_pb - bbp55_sb; 4194 if (delta > target) 4195 break; 4196 4197 /* reprogram filter */ 4198 rf24++; 4199 run_rt3070_rf_write(sc, 24, rf24); 4200 } 4201 if (ntries < 100) { 4202 if (rf24 != init) 4203 rf24--; /* backtrack */ 4204 *val = rf24; 4205 run_rt3070_rf_write(sc, 24, rf24); 4206 } 4207 4208 /* restore initial state */ 4209 run_bbp_write(sc, 24, 0x00); 4210 4211 /* disable baseband loopback mode */ 4212 run_rt3070_rf_read(sc, 22, &rf22); 4213 run_rt3070_rf_write(sc, 22, rf22 & ~0x01); 4214 4215 return 0; 4216 } 4217 4218 void 4219 run_rt3070_rf_setup(struct run_softc *sc) 4220 { 4221 uint8_t bbp, rf; 4222 int i; 4223 4224 if (sc->mac_ver == 0x3572) { 4225 /* enable DC filter */ 4226 if (sc->mac_rev >= 0x0201) 4227 run_bbp_write(sc, 103, 0xc0); 4228 4229 run_bbp_read(sc, 138, &bbp); 4230 if (sc->ntxchains == 1) 4231 bbp |= 0x20; /* turn off DAC1 */ 4232 if (sc->nrxchains == 1) 4233 bbp &= ~0x02; /* turn off ADC1 */ 4234 run_bbp_write(sc, 138, bbp); 4235 4236 if (sc->mac_rev >= 0x0211) { 4237 /* improve power consumption */ 4238 run_bbp_read(sc, 31, &bbp); 4239 run_bbp_write(sc, 31, bbp & ~0x03); 4240 } 4241 4242 run_rt3070_rf_read(sc, 16, &rf); 4243 rf = (rf & ~0x07) | sc->txmixgain_2ghz; 4244 run_rt3070_rf_write(sc, 16, rf); 4245 4246 } else if (sc->mac_ver == 0x3071) { 4247 /* enable DC filter */ 4248 if (sc->mac_rev >= 0x0211) { 4249 run_bbp_write(sc, 103, 0xc0); 4250 4251 /* improve power consumption */ 4252 run_bbp_read(sc, 31, &bbp); 4253 run_bbp_write(sc, 31, bbp & ~0x03); 4254 } 4255 4256 run_bbp_read(sc, 138, &bbp); 4257 if (sc->ntxchains == 1) 4258 bbp |= 0x20; /* turn off DAC1 */ 4259 if (sc->nrxchains == 1) 4260 bbp &= ~0x02; /* turn off ADC1 */ 4261 run_bbp_write(sc, 138, bbp); 4262 4263 run_write(sc, RT2860_TX_SW_CFG1, 0); 4264 if (sc->mac_rev < 0x0211) { 4265 run_write(sc, RT2860_TX_SW_CFG2, 4266 sc->patch_dac ? 0x2c : 0x0f); 4267 } else 4268 run_write(sc, RT2860_TX_SW_CFG2, 0); 4269 4270 } else if (sc->mac_ver == 0x3070) { 4271 if (sc->mac_rev >= 0x0201) { 4272 /* enable DC filter */ 4273 run_bbp_write(sc, 103, 0xc0); 4274 4275 /* improve power consumption */ 4276 run_bbp_read(sc, 31, &bbp); 4277 run_bbp_write(sc, 31, bbp & ~0x03); 4278 } 4279 4280 if (sc->mac_rev < 0x0201) { 4281 run_write(sc, RT2860_TX_SW_CFG1, 0); 4282 run_write(sc, RT2860_TX_SW_CFG2, 0x2c); 4283 } else 4284 run_write(sc, RT2860_TX_SW_CFG2, 0); 4285 } 4286 4287 /* initialize RF registers from ROM for >=RT3071*/ 4288 if (sc->mac_ver >= 0x3071) { 4289 for (i = 0; i < 10; i++) { 4290 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 4291 continue; 4292 run_rt3070_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 4293 } 4294 } 4295 } 4296 4297 void 4298 run_rt3593_rf_setup(struct run_softc *sc) 4299 { 4300 uint8_t bbp, rf; 4301 4302 if (sc->mac_rev >= 0x0211) { 4303 /* Enable DC filter. */ 4304 run_bbp_write(sc, 103, 0xc0); 4305 } 4306 run_write(sc, RT2860_TX_SW_CFG1, 0); 4307 if (sc->mac_rev < 0x0211) { 4308 run_write(sc, RT2860_TX_SW_CFG2, 4309 sc->patch_dac ? 0x2c : 0x0f); 4310 } else 4311 run_write(sc, RT2860_TX_SW_CFG2, 0); 4312 4313 run_rt3070_rf_read(sc, 50, &rf); 4314 run_rt3070_rf_write(sc, 50, rf & ~RT3593_TX_LO2); 4315 4316 run_rt3070_rf_read(sc, 51, &rf); 4317 rf = (rf & ~(RT3593_TX_LO1 | 0x0c)) | 4318 ((sc->txmixgain_2ghz & 0x07) << 2); 4319 run_rt3070_rf_write(sc, 51, rf); 4320 4321 run_rt3070_rf_read(sc, 38, &rf); 4322 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4323 4324 run_rt3070_rf_read(sc, 39, &rf); 4325 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4326 4327 run_rt3070_rf_read(sc, 1, &rf); 4328 run_rt3070_rf_write(sc, 1, rf & ~(RT3070_RF_BLOCK | RT3070_PLL_PD)); 4329 4330 run_rt3070_rf_read(sc, 30, &rf); 4331 rf = (rf & ~0x18) | 0x10; 4332 run_rt3070_rf_write(sc, 30, rf); 4333 4334 /* Apply maximum likelihood detection for 2 stream case. */ 4335 run_bbp_read(sc, 105, &bbp); 4336 if (sc->nrxchains > 1) 4337 run_bbp_write(sc, 105, bbp | RT5390_MLD); 4338 4339 /* Avoid data lost and CRC error. */ 4340 run_bbp_read(sc, 4, &bbp); 4341 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4342 4343 run_bbp_write(sc, 92, 0x02); 4344 run_bbp_write(sc, 82, 0x82); 4345 run_bbp_write(sc, 106, 0x05); 4346 run_bbp_write(sc, 104, 0x92); 4347 run_bbp_write(sc, 88, 0x90); 4348 run_bbp_write(sc, 148, 0xc8); 4349 run_bbp_write(sc, 47, 0x48); 4350 run_bbp_write(sc, 120, 0x50); 4351 4352 run_bbp_write(sc, 163, 0x9d); 4353 4354 /* SNR mapping. */ 4355 run_bbp_write(sc, 142, 0x06); 4356 run_bbp_write(sc, 143, 0xa0); 4357 run_bbp_write(sc, 142, 0x07); 4358 run_bbp_write(sc, 143, 0xa1); 4359 run_bbp_write(sc, 142, 0x08); 4360 run_bbp_write(sc, 143, 0xa2); 4361 4362 run_bbp_write(sc, 31, 0x08); 4363 run_bbp_write(sc, 68, 0x0b); 4364 run_bbp_write(sc, 105, 0x04); 4365 } 4366 4367 void 4368 run_rt5390_rf_setup(struct run_softc *sc) 4369 { 4370 uint8_t bbp, rf; 4371 4372 if (sc->mac_rev >= 0x0211) { 4373 /* Enable DC filter. */ 4374 run_bbp_write(sc, 103, 0xc0); 4375 4376 if (sc->mac_ver != 0x5592) { 4377 /* Improve power consumption. */ 4378 run_bbp_read(sc, 31, &bbp); 4379 run_bbp_write(sc, 31, bbp & ~0x03); 4380 } 4381 } 4382 4383 run_bbp_read(sc, 138, &bbp); 4384 if (sc->ntxchains == 1) 4385 bbp |= 0x20; /* turn off DAC1 */ 4386 if (sc->nrxchains == 1) 4387 bbp &= ~0x02; /* turn off ADC1 */ 4388 run_bbp_write(sc, 138, bbp); 4389 4390 run_rt3070_rf_read(sc, 38, &rf); 4391 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4392 4393 run_rt3070_rf_read(sc, 39, &rf); 4394 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4395 4396 /* Avoid data lost and CRC error. */ 4397 run_bbp_read(sc, 4, &bbp); 4398 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4399 4400 run_rt3070_rf_read(sc, 30, &rf); 4401 rf = (rf & ~0x18) | 0x10; 4402 run_rt3070_rf_write(sc, 30, rf); 4403 4404 if (sc->mac_ver != 0x5592) { 4405 run_write(sc, RT2860_TX_SW_CFG1, 0); 4406 if (sc->mac_rev < 0x0211) { 4407 run_write(sc, RT2860_TX_SW_CFG2, 4408 sc->patch_dac ? 0x2c : 0x0f); 4409 } else 4410 run_write(sc, RT2860_TX_SW_CFG2, 0); 4411 } 4412 } 4413 4414 int 4415 run_txrx_enable(struct run_softc *sc) 4416 { 4417 uint32_t tmp; 4418 int error, ntries; 4419 4420 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 4421 for (ntries = 0; ntries < 200; ntries++) { 4422 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4423 return error; 4424 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4425 break; 4426 DELAY(1000); 4427 } 4428 if (ntries == 200) 4429 return ETIMEDOUT; 4430 4431 DELAY(50); 4432 4433 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | RT2860_TX_WB_DDONE; 4434 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4435 4436 /* enable Rx bulk aggregation (set timeout and limit) */ 4437 tmp = RT2860_USB_TX_EN | RT2860_USB_RX_EN | RT2860_USB_RX_AGG_EN | 4438 RT2860_USB_RX_AGG_TO(128) | RT2860_USB_RX_AGG_LMT(2); 4439 run_write(sc, RT2860_USB_DMA_CFG, tmp); 4440 4441 /* set Rx filter */ 4442 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 4443 if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) { 4444 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 4445 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 4446 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 4447 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 4448 if (sc->sc_ic.ic_opmode == IEEE80211_M_STA) 4449 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 4450 } 4451 run_write(sc, RT2860_RX_FILTR_CFG, tmp); 4452 4453 run_write(sc, RT2860_MAC_SYS_CTRL, 4454 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4455 4456 return 0; 4457 } 4458 4459 void 4460 run_adjust_freq_offset(struct run_softc *sc) 4461 { 4462 uint8_t rf, tmp; 4463 4464 run_rt3070_rf_read(sc, 17, &rf); 4465 tmp = rf; 4466 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 4467 rf = MIN(rf, 0x5f); 4468 4469 if (tmp != rf) 4470 run_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf); 4471 } 4472 4473 int 4474 run_init(struct ifnet *ifp) 4475 { 4476 struct run_softc *sc = ifp->if_softc; 4477 struct ieee80211com *ic = &sc->sc_ic; 4478 uint32_t tmp; 4479 uint8_t bbp1, bbp3; 4480 int i, error, qid, ridx, ntries; 4481 4482 if (usbd_is_dying(sc->sc_udev)) 4483 return ENXIO; 4484 4485 for (ntries = 0; ntries < 100; ntries++) { 4486 if ((error = run_read(sc, RT2860_ASIC_VER_ID, &tmp)) != 0) 4487 goto fail; 4488 if (tmp != 0 && tmp != 0xffffffff) 4489 break; 4490 DELAY(10); 4491 } 4492 if (ntries == 100) { 4493 error = ETIMEDOUT; 4494 goto fail; 4495 } 4496 4497 if ((error = run_load_microcode(sc)) != 0) { 4498 printf("%s: could not load 8051 microcode\n", 4499 sc->sc_dev.dv_xname); 4500 goto fail; 4501 } 4502 4503 /* init host command ring */ 4504 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4505 4506 /* init Tx rings (4 EDCAs) */ 4507 for (qid = 0; qid < 4; qid++) { 4508 if ((error = run_alloc_tx_ring(sc, qid)) != 0) 4509 goto fail; 4510 } 4511 /* init Rx ring */ 4512 if ((error = run_alloc_rx_ring(sc)) != 0) 4513 goto fail; 4514 4515 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 4516 run_set_macaddr(sc, ic->ic_myaddr); 4517 4518 for (ntries = 0; ntries < 100; ntries++) { 4519 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4520 goto fail; 4521 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4522 break; 4523 DELAY(1000); 4524 } 4525 if (ntries == 100) { 4526 printf("%s: timeout waiting for DMA engine\n", 4527 sc->sc_dev.dv_xname); 4528 error = ETIMEDOUT; 4529 goto fail; 4530 } 4531 tmp &= 0xff0; 4532 tmp |= RT2860_TX_WB_DDONE; 4533 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4534 4535 /* turn off PME_OEN to solve high-current issue */ 4536 run_read(sc, RT2860_SYS_CTRL, &tmp); 4537 run_write(sc, RT2860_SYS_CTRL, tmp & ~RT2860_PME_OEN); 4538 4539 run_write(sc, RT2860_MAC_SYS_CTRL, 4540 RT2860_BBP_HRST | RT2860_MAC_SRST); 4541 run_write(sc, RT2860_USB_DMA_CFG, 0); 4542 4543 if ((error = run_reset(sc)) != 0) { 4544 printf("%s: could not reset chipset\n", sc->sc_dev.dv_xname); 4545 goto fail; 4546 } 4547 4548 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 4549 4550 /* init Tx power for all Tx rates (from EEPROM) */ 4551 for (ridx = 0; ridx < 5; ridx++) { 4552 if (sc->txpow20mhz[ridx] == 0xffffffff) 4553 continue; 4554 run_write(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 4555 } 4556 4557 for (i = 0; i < nitems(rt2870_def_mac); i++) 4558 run_write(sc, rt2870_def_mac[i].reg, rt2870_def_mac[i].val); 4559 run_write(sc, RT2860_WMM_AIFSN_CFG, 0x00002273); 4560 run_write(sc, RT2860_WMM_CWMIN_CFG, 0x00002344); 4561 run_write(sc, RT2860_WMM_CWMAX_CFG, 0x000034aa); 4562 4563 if (sc->mac_ver >= 0x5390) { 4564 run_write(sc, RT2860_TX_SW_CFG0, 4565 4 << RT2860_DLY_PAPE_EN_SHIFT | 4); 4566 if (sc->mac_ver >= 0x5392) { 4567 run_write(sc, RT2860_MAX_LEN_CFG, 0x00002fff); 4568 if (sc->mac_ver == 0x5592) { 4569 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcba980); 4570 run_write(sc, RT2860_TXOP_HLDR_ET, 0x00000082); 4571 } else { 4572 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcb4980); 4573 run_write(sc, RT2860_LG_FBK_CFG0, 0xedcba322); 4574 } 4575 } 4576 } else if (sc->mac_ver == 0x3593) { 4577 run_write(sc, RT2860_TX_SW_CFG0, 4578 4 << RT2860_DLY_PAPE_EN_SHIFT | 2); 4579 } else if (sc->mac_ver >= 0x3070) { 4580 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 4581 run_write(sc, RT2860_TX_SW_CFG0, 4582 4 << RT2860_DLY_PAPE_EN_SHIFT); 4583 } 4584 4585 /* wait while MAC is busy */ 4586 for (ntries = 0; ntries < 100; ntries++) { 4587 if ((error = run_read(sc, RT2860_MAC_STATUS_REG, &tmp)) != 0) 4588 goto fail; 4589 if (!(tmp & (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 4590 break; 4591 DELAY(1000); 4592 } 4593 if (ntries == 100) { 4594 error = ETIMEDOUT; 4595 goto fail; 4596 } 4597 4598 /* clear Host to MCU mailbox */ 4599 run_write(sc, RT2860_H2M_BBPAGENT, 0); 4600 run_write(sc, RT2860_H2M_MAILBOX, 0); 4601 DELAY(1000); 4602 4603 if ((error = run_bbp_init(sc)) != 0) { 4604 printf("%s: could not initialize BBP\n", sc->sc_dev.dv_xname); 4605 goto fail; 4606 } 4607 4608 /* abort TSF synchronization */ 4609 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 4610 tmp &= ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 4611 RT2860_TBTT_TIMER_EN); 4612 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 4613 4614 /* clear RX WCID search table */ 4615 run_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 4616 /* clear WCID attribute table */ 4617 run_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 8 * 32); 4618 /* clear shared key table */ 4619 run_set_region_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 4620 /* clear shared key mode */ 4621 run_set_region_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 4622 4623 run_read(sc, RT2860_US_CYC_CNT, &tmp); 4624 tmp = (tmp & ~0xff) | 0x1e; 4625 run_write(sc, RT2860_US_CYC_CNT, tmp); 4626 4627 if (sc->mac_rev != 0x0101) 4628 run_write(sc, RT2860_TXOP_CTRL_CFG, 0x0000583f); 4629 4630 run_write(sc, RT2860_WMM_TXOP0_CFG, 0); 4631 run_write(sc, RT2860_WMM_TXOP1_CFG, 48 << 16 | 96); 4632 4633 /* write vendor-specific BBP values (from EEPROM) */ 4634 if (sc->mac_ver < 0x3593) { 4635 for (i = 0; i < 8; i++) { 4636 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 4637 continue; 4638 run_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 4639 } 4640 } 4641 4642 /* select Main antenna for 1T1R devices */ 4643 if (sc->rf_rev == RT3070_RF_3020 || sc->rf_rev == RT5390_RF_5370) 4644 run_set_rx_antenna(sc, 0); 4645 4646 /* send LEDs operating mode to microcontroller */ 4647 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0]); 4648 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1]); 4649 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2]); 4650 4651 if (sc->mac_ver >= 0x5390) 4652 run_rt5390_rf_init(sc); 4653 else if (sc->mac_ver == 0x3593) 4654 run_rt3593_rf_init(sc); 4655 else if (sc->mac_ver >= 0x3070) 4656 run_rt3070_rf_init(sc); 4657 4658 /* disable non-existing Rx chains */ 4659 run_bbp_read(sc, 3, &bbp3); 4660 bbp3 &= ~(1 << 3 | 1 << 4); 4661 if (sc->nrxchains == 2) 4662 bbp3 |= 1 << 3; 4663 else if (sc->nrxchains == 3) 4664 bbp3 |= 1 << 4; 4665 run_bbp_write(sc, 3, bbp3); 4666 4667 /* disable non-existing Tx chains */ 4668 run_bbp_read(sc, 1, &bbp1); 4669 if (sc->ntxchains == 1) 4670 bbp1 &= ~(1 << 3 | 1 << 4); 4671 run_bbp_write(sc, 1, bbp1); 4672 4673 if (sc->mac_ver >= 0x5390) 4674 run_rt5390_rf_setup(sc); 4675 else if (sc->mac_ver == 0x3593) 4676 run_rt3593_rf_setup(sc); 4677 else if (sc->mac_ver >= 0x3070) 4678 run_rt3070_rf_setup(sc); 4679 4680 /* select default channel */ 4681 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 4682 run_set_chan(sc, ic->ic_ibss_chan); 4683 4684 /* turn radio LED on */ 4685 run_set_leds(sc, RT2860_LED_RADIO); 4686 4687 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 4688 struct run_rx_data *data = &sc->rxq.data[i]; 4689 4690 usbd_setup_xfer(data->xfer, sc->rxq.pipeh, data, data->buf, 4691 RUN_MAX_RXSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 4692 USBD_NO_TIMEOUT, run_rxeof); 4693 error = usbd_transfer(data->xfer); 4694 if (error != 0 && error != USBD_IN_PROGRESS) 4695 goto fail; 4696 } 4697 4698 if ((error = run_txrx_enable(sc)) != 0) 4699 goto fail; 4700 4701 ifp->if_flags |= IFF_RUNNING; 4702 ifq_clr_oactive(&ifp->if_snd); 4703 4704 if (ic->ic_flags & IEEE80211_F_WEPON) { 4705 /* install WEP keys */ 4706 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4707 (void)run_set_key(ic, NULL, &ic->ic_nw_keys[i]); 4708 } 4709 4710 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4711 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4712 else 4713 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4714 4715 if (error != 0) 4716 fail: run_stop(ifp, 1); 4717 return error; 4718 } 4719 4720 void 4721 run_stop(struct ifnet *ifp, int disable) 4722 { 4723 struct run_softc *sc = ifp->if_softc; 4724 struct ieee80211com *ic = &sc->sc_ic; 4725 uint32_t tmp; 4726 int s, ntries, qid; 4727 4728 if (ifp->if_flags & IFF_RUNNING) 4729 run_set_leds(sc, 0); /* turn all LEDs off */ 4730 4731 sc->sc_tx_timer = 0; 4732 ifp->if_timer = 0; 4733 ifp->if_flags &= ~IFF_RUNNING; 4734 ifq_clr_oactive(&ifp->if_snd); 4735 4736 timeout_del(&sc->scan_to); 4737 timeout_del(&sc->calib_to); 4738 4739 s = splusb(); 4740 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4741 /* wait for all queued asynchronous commands to complete */ 4742 usb_wait_task(sc->sc_udev, &sc->sc_task); 4743 splx(s); 4744 4745 /* Disable Tx/Rx DMA. */ 4746 run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp); 4747 tmp &= ~(RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 4748 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4749 4750 for (ntries = 0; ntries < 100; ntries++) { 4751 if (run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp) != 0) 4752 break; 4753 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4754 break; 4755 DELAY(10); 4756 } 4757 if (ntries == 100) { 4758 printf("%s: timeout waiting for DMA engine\n", 4759 sc->sc_dev.dv_xname); 4760 } 4761 4762 /* disable Tx/Rx */ 4763 run_read(sc, RT2860_MAC_SYS_CTRL, &tmp); 4764 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4765 run_write(sc, RT2860_MAC_SYS_CTRL, tmp); 4766 4767 /* wait for pending Tx to complete */ 4768 for (ntries = 0; ntries < 100; ntries++) { 4769 if (run_read(sc, RT2860_TXRXQ_PCNT, &tmp) != 0) 4770 break; 4771 if ((tmp & RT2860_TX2Q_PCNT_MASK) == 0) 4772 break; 4773 } 4774 DELAY(1000); 4775 run_write(sc, RT2860_USB_DMA_CFG, 0); 4776 4777 /* reset adapter */ 4778 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4779 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 4780 4781 /* reset Tx and Rx rings */ 4782 sc->qfullmsk = 0; 4783 for (qid = 0; qid < 4; qid++) 4784 run_free_tx_ring(sc, qid); 4785 run_free_rx_ring(sc); 4786 } 4787