1 /* $OpenBSD: if_run.c,v 1.128 2020/01/05 08:58:25 jsg Exp $ */ 2 3 /*- 4 * Copyright (c) 2008-2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2013-2014 Kevin Lo 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /*- 21 * Ralink Technology RT2700U/RT2800U/RT3000U/RT3900E chipset driver. 22 * http://www.ralinktech.com/ 23 */ 24 25 #include "bpfilter.h" 26 27 #include <sys/param.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/timeout.h> 34 #include <sys/conf.h> 35 #include <sys/device.h> 36 #include <sys/endian.h> 37 38 #include <machine/intr.h> 39 40 #if NBPFILTER > 0 41 #include <net/bpf.h> 42 #endif 43 #include <net/if.h> 44 #include <net/if_dl.h> 45 #include <net/if_media.h> 46 47 #include <netinet/in.h> 48 #include <netinet/if_ether.h> 49 50 #include <net80211/ieee80211_var.h> 51 #include <net80211/ieee80211_amrr.h> 52 #include <net80211/ieee80211_radiotap.h> 53 54 #include <dev/usb/usb.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdi_util.h> 57 #include <dev/usb/usbdevs.h> 58 59 #include <dev/ic/rt2860reg.h> /* shared with ral(4) */ 60 #include <dev/usb/if_runvar.h> 61 62 #ifdef RUN_DEBUG 63 #define DPRINTF(x) do { if (run_debug) printf x; } while (0) 64 #define DPRINTFN(n, x) do { if (run_debug >= (n)) printf x; } while (0) 65 int run_debug = 0; 66 #else 67 #define DPRINTF(x) 68 #define DPRINTFN(n, x) 69 #endif 70 71 #define USB_ID(v, p) { USB_VENDOR_##v, USB_PRODUCT_##v##_##p } 72 static const struct usb_devno run_devs[] = { 73 USB_ID(ABOCOM, RT2770), 74 USB_ID(ABOCOM, RT2870), 75 USB_ID(ABOCOM, RT3070), 76 USB_ID(ABOCOM, RT3071), 77 USB_ID(ABOCOM, RT3072), 78 USB_ID(ABOCOM2, RT2870_1), 79 USB_ID(ACCTON, RT2770), 80 USB_ID(ACCTON, RT2870_1), 81 USB_ID(ACCTON, RT2870_2), 82 USB_ID(ACCTON, RT2870_3), 83 USB_ID(ACCTON, RT2870_4), 84 USB_ID(ACCTON, RT2870_5), 85 USB_ID(ACCTON, RT3070), 86 USB_ID(ACCTON, RT3070_1), 87 USB_ID(ACCTON, RT3070_2), 88 USB_ID(ACCTON, RT3070_3), 89 USB_ID(ACCTON, RT3070_4), 90 USB_ID(ACCTON, RT3070_5), 91 USB_ID(ACCTON, RT3070_6), 92 USB_ID(AIRTIES, RT3070), 93 USB_ID(AIRTIES, RT3070_2), 94 USB_ID(ALLWIN, RT2070), 95 USB_ID(ALLWIN, RT2770), 96 USB_ID(ALLWIN, RT2870), 97 USB_ID(ALLWIN, RT3070), 98 USB_ID(ALLWIN, RT3071), 99 USB_ID(ALLWIN, RT3072), 100 USB_ID(ALLWIN, RT3572), 101 USB_ID(AMIGO, RT2870_1), 102 USB_ID(AMIGO, RT2870_2), 103 USB_ID(AMIT, CGWLUSB2GNR), 104 USB_ID(AMIT, RT2870_1), 105 USB_ID(AMIT2, RT2870), 106 USB_ID(ASUS, RT2870_1), 107 USB_ID(ASUS, RT2870_2), 108 USB_ID(ASUS, RT2870_3), 109 USB_ID(ASUS, RT2870_4), 110 USB_ID(ASUS, RT2870_5), 111 USB_ID(ASUS, RT3070_1), 112 USB_ID(ASUS, USBN13), 113 USB_ID(ASUS, USBN53), 114 USB_ID(ASUS, USBN66), 115 USB_ID(ASUS2, USBN11), 116 USB_ID(AZUREWAVE, RT2870_1), 117 USB_ID(AZUREWAVE, RT2870_2), 118 USB_ID(AZUREWAVE, RT3070_1), 119 USB_ID(AZUREWAVE, RT3070_2), 120 USB_ID(AZUREWAVE, RT3070_3), 121 USB_ID(AZUREWAVE, RT3070_4), 122 USB_ID(AZUREWAVE, RT3070_5), 123 USB_ID(BELKIN, F9L1103), 124 USB_ID(BELKIN, F5D8053V3), 125 USB_ID(BELKIN, F5D8055), 126 USB_ID(BELKIN, F5D8055V2), 127 USB_ID(BELKIN, F6D4050V1), 128 USB_ID(BELKIN, F6D4050V2), 129 USB_ID(BELKIN, F7D1101V2), 130 USB_ID(BELKIN, RT2870_1), 131 USB_ID(BELKIN, RT2870_2), 132 USB_ID(BEWAN, RT3070), 133 USB_ID(CISCOLINKSYS, AE1000), 134 USB_ID(CISCOLINKSYS, AM10), 135 USB_ID(CISCOLINKSYS2, RT3070), 136 USB_ID(CISCOLINKSYS3, RT3070), 137 USB_ID(CONCEPTRONIC2, RT2870_1), 138 USB_ID(CONCEPTRONIC2, RT2870_2), 139 USB_ID(CONCEPTRONIC2, RT2870_3), 140 USB_ID(CONCEPTRONIC2, RT2870_5), 141 USB_ID(CONCEPTRONIC2, RT2870_6), 142 USB_ID(CONCEPTRONIC2, RT2870_7), 143 USB_ID(CONCEPTRONIC2, RT2870_8), 144 USB_ID(CONCEPTRONIC2, RT3070_1), 145 USB_ID(CONCEPTRONIC2, RT3070_2), 146 USB_ID(CONCEPTRONIC2, RT3070_3), 147 USB_ID(CONCEPTRONIC2, VIGORN61), 148 USB_ID(COREGA, CGWLUSB300GNM), 149 USB_ID(COREGA, RT2870_1), 150 USB_ID(COREGA, RT2870_2), 151 USB_ID(COREGA, RT2870_3), 152 USB_ID(COREGA, RT3070), 153 USB_ID(CYBERTAN, RT2870), 154 USB_ID(DLINK, DWA125B2), 155 USB_ID(DLINK, DWA127), 156 USB_ID(DLINK, DWA130F1), 157 USB_ID(DLINK, DWA137A1), 158 USB_ID(DLINK, DWA140B3), 159 USB_ID(DLINK, DWA140D1), 160 USB_ID(DLINK, DWA160B2), 161 USB_ID(DLINK, DWA162), 162 USB_ID(DLINK, RT2870), 163 USB_ID(DLINK, RT3072), 164 USB_ID(DLINK2, DWA130), 165 USB_ID(DLINK2, RT2870_1), 166 USB_ID(DLINK2, RT2870_2), 167 USB_ID(DLINK2, RT3070_1), 168 USB_ID(DLINK2, RT3070_2), 169 USB_ID(DLINK2, RT3070_3), 170 USB_ID(DLINK2, RT3070_4), 171 USB_ID(DLINK2, RT3070_5), 172 USB_ID(DLINK2, RT3072), 173 USB_ID(DLINK2, RT3072_1), 174 USB_ID(DVICO, RT3070), 175 USB_ID(EDIMAX, EW7717), 176 USB_ID(EDIMAX, EW7718), 177 USB_ID(EDIMAX, EW7722UTN), 178 USB_ID(EDIMAX, RT2870_1), 179 USB_ID(ENCORE, RT3070_1), 180 USB_ID(ENCORE, RT3070_2), 181 USB_ID(ENCORE, RT3070_3), 182 USB_ID(GIGABYTE, GNWB31N), 183 USB_ID(GIGABYTE, GNWB32L), 184 USB_ID(GIGABYTE, RT2870_1), 185 USB_ID(GIGASET, RT3070_1), 186 USB_ID(GIGASET, RT3070_2), 187 USB_ID(GUILLEMOT, HWNU300), 188 USB_ID(HAWKING, HWDN2), 189 USB_ID(HAWKING, HWUN2), 190 USB_ID(HAWKING, RT2870_1), 191 USB_ID(HAWKING, RT2870_2), 192 USB_ID(HAWKING, RT2870_3), 193 USB_ID(HAWKING, RT2870_4), 194 USB_ID(HAWKING, RT2870_5), 195 USB_ID(IODATA, RT3072_1), 196 USB_ID(IODATA, RT3072_2), 197 USB_ID(IODATA, RT3072_3), 198 USB_ID(IODATA, RT3072_4), 199 USB_ID(LINKSYS4, RT3070), 200 USB_ID(LINKSYS4, WUSB100), 201 USB_ID(LINKSYS4, WUSB54GCV3), 202 USB_ID(LINKSYS4, WUSB600N), 203 USB_ID(LINKSYS4, WUSB600NV2), 204 USB_ID(LOGITEC, LANW150NU2), 205 USB_ID(LOGITEC, LANW300NU2), 206 USB_ID(LOGITEC, LANW300NU2S), 207 USB_ID(LOGITEC, RT2870_1), 208 USB_ID(LOGITEC, RT2870_2), 209 USB_ID(LOGITEC, RT2870_3), 210 USB_ID(MELCO, RT2870_1), 211 USB_ID(MELCO, RT2870_2), 212 USB_ID(MELCO, WLIUCAG300N), 213 USB_ID(MELCO, WLIUCG300N), 214 USB_ID(MELCO, WLIUCG301N), 215 USB_ID(MELCO, WLIUCGN), 216 USB_ID(MELCO, WLIUCGNHP), 217 USB_ID(MELCO, WLIUCGNM), 218 USB_ID(MELCO, WLIUCGNM2), 219 USB_ID(MOTOROLA4, RT2770), 220 USB_ID(MOTOROLA4, RT3070), 221 USB_ID(MSI, RT3070_1), 222 USB_ID(MSI, RT3070_2), 223 USB_ID(MSI, RT3070_3), 224 USB_ID(MSI, RT3070_4), 225 USB_ID(MSI, RT3070_5), 226 USB_ID(MSI, RT3070_6), 227 USB_ID(MSI, RT3070_7), 228 USB_ID(MSI, RT3070_8), 229 USB_ID(MSI, RT3070_9), 230 USB_ID(MSI, RT3070_10), 231 USB_ID(MSI, RT3070_11), 232 USB_ID(MSI, RT3070_12), 233 USB_ID(MSI, RT3070_13), 234 USB_ID(MSI, RT3070_14), 235 USB_ID(MSI, RT3070_15), 236 USB_ID(OVISLINK, RT3071), 237 USB_ID(OVISLINK, RT3072), 238 USB_ID(PARA, RT3070), 239 USB_ID(PEGATRON, RT2870), 240 USB_ID(PEGATRON, RT3070), 241 USB_ID(PEGATRON, RT3070_2), 242 USB_ID(PEGATRON, RT3070_3), 243 USB_ID(PEGATRON, RT3072), 244 USB_ID(PHILIPS, RT2870), 245 USB_ID(PLANEX2, GWUS300MINIS), 246 USB_ID(PLANEX2, GWUSMICRO300), 247 USB_ID(PLANEX2, GWUSMICRON), 248 USB_ID(PLANEX2, RT2870), 249 USB_ID(PLANEX2, RT3070), 250 USB_ID(QCOM, RT2870), 251 USB_ID(QUANTA, RT3070), 252 USB_ID(RALINK, RT2070), 253 USB_ID(RALINK, RT2770), 254 USB_ID(RALINK, RT2870), 255 USB_ID(RALINK, RT3070), 256 USB_ID(RALINK, RT3071), 257 USB_ID(RALINK, RT3072), 258 USB_ID(RALINK, RT3370), 259 USB_ID(RALINK, RT3572), 260 USB_ID(RALINK, RT3573), 261 USB_ID(RALINK, RT5370), 262 USB_ID(RALINK, RT5572), 263 USB_ID(RALINK, RT8070), 264 USB_ID(SAMSUNG, WIS09ABGN), 265 USB_ID(SAMSUNG2, RT2870_1), 266 USB_ID(SENAO, RT2870_1), 267 USB_ID(SENAO, RT2870_2), 268 USB_ID(SENAO, RT2870_3), 269 USB_ID(SENAO, RT2870_4), 270 USB_ID(SENAO, RT3070), 271 USB_ID(SENAO, RT3071), 272 USB_ID(SENAO, RT3072_1), 273 USB_ID(SENAO, RT3072_2), 274 USB_ID(SENAO, RT3072_3), 275 USB_ID(SENAO, RT3072_4), 276 USB_ID(SENAO, RT3072_5), 277 USB_ID(SITECOMEU, WL302), 278 USB_ID(SITECOMEU, WL315), 279 USB_ID(SITECOMEU, WL321), 280 USB_ID(SITECOMEU, RT3070_3), 281 USB_ID(SITECOMEU, WL302), 282 USB_ID(SITECOMEU, WL344), 283 USB_ID(SITECOMEU, WL329), 284 USB_ID(SITECOMEU, WL345), 285 USB_ID(SITECOMEU, RT2870_1), 286 USB_ID(SITECOMEU, RT2870_2), 287 USB_ID(SITECOMEU, RT2870_3), 288 USB_ID(SITECOMEU, RT3070_1), 289 USB_ID(SITECOMEU, RT3072_3), 290 USB_ID(SITECOMEU, RT3072_4), 291 USB_ID(SITECOMEU, RT3072_5), 292 USB_ID(SITECOMEU, RT3072_6), 293 USB_ID(SITECOMEU, WL302), 294 USB_ID(SITECOMEU, WL315), 295 USB_ID(SITECOMEU, WL321), 296 USB_ID(SITECOMEU, WL324), 297 USB_ID(SITECOMEU, WL329), 298 USB_ID(SITECOMEU, WL343), 299 USB_ID(SITECOMEU, WL344), 300 USB_ID(SITECOMEU, WL345), 301 USB_ID(SITECOMEU, WL349V4), 302 USB_ID(SITECOMEU, WL608), 303 USB_ID(SITECOMEU, WLA4000), 304 USB_ID(SITECOMEU, WLA5000), 305 USB_ID(SPARKLAN, RT2870_1), 306 USB_ID(SPARKLAN, RT2870_2), 307 USB_ID(SPARKLAN, RT3070), 308 USB_ID(SWEEX2, LW153), 309 USB_ID(SWEEX2, LW303), 310 USB_ID(SWEEX2, LW313), 311 USB_ID(TOSHIBA, RT3070), 312 USB_ID(UMEDIA, RT2870_1), 313 USB_ID(UMEDIA, TEW645UB), 314 USB_ID(ZCOM, RT2870_1), 315 USB_ID(ZCOM, RT2870_2), 316 USB_ID(ZINWELL, RT2870_1), 317 USB_ID(ZINWELL, RT2870_2), 318 USB_ID(ZINWELL, RT3070), 319 USB_ID(ZINWELL, RT3072_1), 320 USB_ID(ZINWELL, RT3072_2), 321 USB_ID(ZYXEL, NWD2105), 322 USB_ID(ZYXEL, NWD211AN), 323 USB_ID(ZYXEL, RT2870_1), 324 USB_ID(ZYXEL, RT2870_2), 325 USB_ID(ZYXEL, RT3070) 326 }; 327 328 int run_match(struct device *, void *, void *); 329 void run_attach(struct device *, struct device *, void *); 330 int run_detach(struct device *, int); 331 int run_alloc_rx_ring(struct run_softc *); 332 void run_free_rx_ring(struct run_softc *); 333 int run_alloc_tx_ring(struct run_softc *, int); 334 void run_free_tx_ring(struct run_softc *, int); 335 int run_load_microcode(struct run_softc *); 336 int run_reset(struct run_softc *); 337 int run_read(struct run_softc *, uint16_t, uint32_t *); 338 int run_read_region_1(struct run_softc *, uint16_t, uint8_t *, 339 int); 340 int run_write_2(struct run_softc *, uint16_t, uint16_t); 341 int run_write(struct run_softc *, uint16_t, uint32_t); 342 int run_write_region_1(struct run_softc *, uint16_t, 343 const uint8_t *, int); 344 int run_set_region_4(struct run_softc *, uint16_t, uint32_t, int); 345 int run_efuse_read(struct run_softc *, uint16_t, uint16_t *); 346 int run_efuse_read_2(struct run_softc *, uint16_t, uint16_t *); 347 int run_eeprom_read_2(struct run_softc *, uint16_t, uint16_t *); 348 int run_rt2870_rf_write(struct run_softc *, uint8_t, uint32_t); 349 int run_rt3070_rf_read(struct run_softc *, uint8_t, uint8_t *); 350 int run_rt3070_rf_write(struct run_softc *, uint8_t, uint8_t); 351 int run_bbp_read(struct run_softc *, uint8_t, uint8_t *); 352 int run_bbp_write(struct run_softc *, uint8_t, uint8_t); 353 int run_mcu_cmd(struct run_softc *, uint8_t, uint16_t); 354 const char * run_get_rf(int); 355 void run_get_txpower(struct run_softc *); 356 void run_rt3593_get_txpower(struct run_softc *); 357 int run_read_eeprom(struct run_softc *); 358 struct ieee80211_node *run_node_alloc(struct ieee80211com *); 359 int run_media_change(struct ifnet *); 360 void run_next_scan(void *); 361 void run_task(void *); 362 void run_do_async(struct run_softc *, void (*)(struct run_softc *, 363 void *), void *, int); 364 int run_newstate(struct ieee80211com *, enum ieee80211_state, int); 365 void run_newstate_cb(struct run_softc *, void *); 366 void run_updateedca(struct ieee80211com *); 367 void run_updateedca_cb(struct run_softc *, void *); 368 int run_set_key(struct ieee80211com *, struct ieee80211_node *, 369 struct ieee80211_key *); 370 void run_set_key_cb(struct run_softc *, void *); 371 void run_delete_key(struct ieee80211com *, struct ieee80211_node *, 372 struct ieee80211_key *); 373 void run_delete_key_cb(struct run_softc *, void *); 374 void run_calibrate_to(void *); 375 void run_calibrate_cb(struct run_softc *, void *); 376 void run_newassoc(struct ieee80211com *, struct ieee80211_node *, 377 int); 378 void run_rx_frame(struct run_softc *, uint8_t *, int, 379 struct mbuf_list *); 380 void run_rxeof(struct usbd_xfer *, void *, usbd_status); 381 void run_txeof(struct usbd_xfer *, void *, usbd_status); 382 int run_tx(struct run_softc *, struct mbuf *, 383 struct ieee80211_node *); 384 void run_start(struct ifnet *); 385 void run_watchdog(struct ifnet *); 386 int run_ioctl(struct ifnet *, u_long, caddr_t); 387 void run_iq_calib(struct run_softc *, u_int); 388 void run_select_chan_group(struct run_softc *, int); 389 void run_set_agc(struct run_softc *, uint8_t); 390 void run_set_rx_antenna(struct run_softc *, int); 391 void run_rt2870_set_chan(struct run_softc *, u_int); 392 void run_rt3070_set_chan(struct run_softc *, u_int); 393 void run_rt3572_set_chan(struct run_softc *, u_int); 394 void run_rt3593_set_chan(struct run_softc *, u_int); 395 void run_rt5390_set_chan(struct run_softc *, u_int); 396 void run_rt5592_set_chan(struct run_softc *, u_int); 397 int run_set_chan(struct run_softc *, struct ieee80211_channel *); 398 void run_enable_tsf_sync(struct run_softc *); 399 void run_enable_mrr(struct run_softc *); 400 void run_set_txpreamble(struct run_softc *); 401 void run_set_basicrates(struct run_softc *); 402 void run_set_leds(struct run_softc *, uint16_t); 403 void run_set_bssid(struct run_softc *, const uint8_t *); 404 void run_set_macaddr(struct run_softc *, const uint8_t *); 405 void run_updateslot(struct ieee80211com *); 406 void run_updateslot_cb(struct run_softc *, void *); 407 #if NBPFILTER > 0 408 int8_t run_rssi2dbm(struct run_softc *, uint8_t, uint8_t); 409 #endif 410 void run_rt5390_bbp_init(struct run_softc *); 411 int run_bbp_init(struct run_softc *); 412 int run_rt3070_rf_init(struct run_softc *); 413 void run_rt3593_rf_init(struct run_softc *); 414 void run_rt5390_rf_init(struct run_softc *); 415 int run_rt3070_filter_calib(struct run_softc *, uint8_t, uint8_t, 416 uint8_t *); 417 void run_rt3070_rf_setup(struct run_softc *); 418 void run_rt3593_rf_setup(struct run_softc *); 419 void run_rt5390_rf_setup(struct run_softc *); 420 int run_txrx_enable(struct run_softc *); 421 void run_adjust_freq_offset(struct run_softc *); 422 int run_init(struct ifnet *); 423 void run_stop(struct ifnet *, int); 424 425 struct cfdriver run_cd = { 426 NULL, "run", DV_IFNET 427 }; 428 429 const struct cfattach run_ca = { 430 sizeof (struct run_softc), run_match, run_attach, run_detach 431 }; 432 433 static const struct { 434 uint32_t reg; 435 uint32_t val; 436 } rt2870_def_mac[] = { 437 RT2870_DEF_MAC 438 }; 439 440 static const struct { 441 uint8_t reg; 442 uint8_t val; 443 } rt2860_def_bbp[] = { 444 RT2860_DEF_BBP 445 },rt5390_def_bbp[] = { 446 RT5390_DEF_BBP 447 },rt5592_def_bbp[] = { 448 RT5592_DEF_BBP 449 }; 450 451 /* 452 * Default values for BBP register R196 for RT5592. 453 */ 454 static const uint8_t rt5592_bbp_r196[] = { 455 0xe0, 0x1f, 0x38, 0x32, 0x08, 0x28, 0x19, 0x0a, 0xff, 0x00, 456 0x16, 0x10, 0x10, 0x0b, 0x36, 0x2c, 0x26, 0x24, 0x42, 0x36, 457 0x30, 0x2d, 0x4c, 0x46, 0x3d, 0x40, 0x3e, 0x42, 0x3d, 0x40, 458 0x3c, 0x34, 0x2c, 0x2f, 0x3c, 0x35, 0x2e, 0x2a, 0x49, 0x41, 459 0x36, 0x31, 0x30, 0x30, 0x0e, 0x0d, 0x28, 0x21, 0x1c, 0x16, 460 0x50, 0x4a, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 461 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 462 0x00, 0x00, 0x7d, 0x14, 0x32, 0x2c, 0x36, 0x4c, 0x43, 0x2c, 463 0x2e, 0x36, 0x30, 0x6e 464 }; 465 466 static const struct rfprog { 467 uint8_t chan; 468 uint32_t r1, r2, r3, r4; 469 } rt2860_rf2850[] = { 470 RT2860_RF2850 471 }; 472 473 struct { 474 uint8_t n, r, k; 475 } rt3070_freqs[] = { 476 RT3070_RF3052 477 }; 478 479 static const struct rt5592_freqs { 480 uint16_t n; 481 uint8_t k, m, r; 482 } rt5592_freqs_20mhz[] = { 483 RT5592_RF5592_20MHZ 484 },rt5592_freqs_40mhz[] = { 485 RT5592_RF5592_40MHZ 486 }; 487 488 static const struct { 489 uint8_t reg; 490 uint8_t val; 491 } rt3070_def_rf[] = { 492 RT3070_DEF_RF 493 },rt3572_def_rf[] = { 494 RT3572_DEF_RF 495 },rt3593_def_rf[] = { 496 RT3593_DEF_RF 497 },rt5390_def_rf[] = { 498 RT5390_DEF_RF 499 },rt5392_def_rf[] = { 500 RT5392_DEF_RF 501 },rt5592_def_rf[] = { 502 RT5592_DEF_RF 503 },rt5592_2ghz_def_rf[] = { 504 RT5592_2GHZ_DEF_RF 505 },rt5592_5ghz_def_rf[] = { 506 RT5592_5GHZ_DEF_RF 507 }; 508 509 static const struct { 510 u_int firstchan; 511 u_int lastchan; 512 uint8_t reg; 513 uint8_t val; 514 } rt5592_chan_5ghz[] = { 515 RT5592_CHAN_5GHZ 516 }; 517 518 int 519 run_match(struct device *parent, void *match, void *aux) 520 { 521 struct usb_attach_arg *uaa = aux; 522 523 if (uaa->iface == NULL || uaa->configno != 1) 524 return UMATCH_NONE; 525 526 return (usb_lookup(run_devs, uaa->vendor, uaa->product) != NULL) ? 527 UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE; 528 } 529 530 void 531 run_attach(struct device *parent, struct device *self, void *aux) 532 { 533 struct run_softc *sc = (struct run_softc *)self; 534 struct usb_attach_arg *uaa = aux; 535 struct ieee80211com *ic = &sc->sc_ic; 536 struct ifnet *ifp = &ic->ic_if; 537 usb_interface_descriptor_t *id; 538 usb_endpoint_descriptor_t *ed; 539 int i, nrx, ntx, ntries; 540 uint32_t ver; 541 542 sc->sc_udev = uaa->device; 543 sc->sc_iface = uaa->iface; 544 545 /* 546 * Find all bulk endpoints. There are 7 bulk endpoints: 1 for RX 547 * and 6 for TX (4 EDCAs + HCCA + Prio). 548 * Update 03-14-2009: some devices like the Planex GW-US300MiniS 549 * seem to have only 4 TX bulk endpoints (Fukaumi Naoki). 550 */ 551 nrx = ntx = 0; 552 id = usbd_get_interface_descriptor(sc->sc_iface); 553 for (i = 0; i < id->bNumEndpoints; i++) { 554 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i); 555 if (ed == NULL || UE_GET_XFERTYPE(ed->bmAttributes) != UE_BULK) 556 continue; 557 558 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) { 559 sc->rxq.pipe_no = ed->bEndpointAddress; 560 nrx++; 561 } else if (ntx < 4) { 562 sc->txq[ntx].pipe_no = ed->bEndpointAddress; 563 ntx++; 564 } 565 } 566 /* make sure we've got them all */ 567 if (nrx < 1 || ntx < 4) { 568 printf("%s: missing endpoint\n", sc->sc_dev.dv_xname); 569 return; 570 } 571 572 usb_init_task(&sc->sc_task, run_task, sc, USB_TASK_TYPE_GENERIC); 573 timeout_set(&sc->scan_to, run_next_scan, sc); 574 timeout_set(&sc->calib_to, run_calibrate_to, sc); 575 576 sc->amrr.amrr_min_success_threshold = 1; 577 sc->amrr.amrr_max_success_threshold = 10; 578 579 /* wait for the chip to settle */ 580 for (ntries = 0; ntries < 100; ntries++) { 581 if (run_read(sc, RT2860_ASIC_VER_ID, &ver) != 0) 582 return; 583 if (ver != 0 && ver != 0xffffffff) 584 break; 585 DELAY(10); 586 } 587 if (ntries == 100) { 588 printf("%s: timeout waiting for NIC to initialize\n", 589 sc->sc_dev.dv_xname); 590 return; 591 } 592 sc->mac_ver = ver >> 16; 593 sc->mac_rev = ver & 0xffff; 594 595 /* retrieve RF rev. no and various other things from EEPROM */ 596 run_read_eeprom(sc); 597 598 printf("%s: MAC/BBP RT%04X (rev 0x%04X), RF %s (MIMO %dT%dR), " 599 "address %s\n", sc->sc_dev.dv_xname, sc->mac_ver, 600 sc->mac_rev, run_get_rf(sc->rf_rev), sc->ntxchains, 601 sc->nrxchains, ether_sprintf(ic->ic_myaddr)); 602 603 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 604 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 605 ic->ic_state = IEEE80211_S_INIT; 606 607 /* set device capabilities */ 608 ic->ic_caps = 609 IEEE80211_C_MONITOR | /* monitor mode supported */ 610 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 611 IEEE80211_C_SHSLOT | /* short slot time supported */ 612 IEEE80211_C_WEP | /* WEP */ 613 IEEE80211_C_RSN; /* WPA/RSN */ 614 615 if (sc->rf_rev == RT2860_RF_2750 || 616 sc->rf_rev == RT2860_RF_2850 || 617 sc->rf_rev == RT3070_RF_3052 || 618 sc->rf_rev == RT3070_RF_3053 || 619 sc->rf_rev == RT5592_RF_5592) { 620 /* set supported .11a rates */ 621 ic->ic_sup_rates[IEEE80211_MODE_11A] = 622 ieee80211_std_rateset_11a; 623 624 /* set supported .11a channels */ 625 for (i = 14; i < nitems(rt2860_rf2850); i++) { 626 uint8_t chan = rt2860_rf2850[i].chan; 627 ic->ic_channels[chan].ic_freq = 628 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 629 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 630 } 631 } 632 633 /* set supported .11b and .11g rates */ 634 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 635 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 636 637 /* set supported .11b and .11g channels (1 through 14) */ 638 for (i = 1; i <= 14; i++) { 639 ic->ic_channels[i].ic_freq = 640 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 641 ic->ic_channels[i].ic_flags = 642 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 643 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 644 } 645 646 ifp->if_softc = sc; 647 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 648 ifp->if_ioctl = run_ioctl; 649 ifp->if_start = run_start; 650 ifp->if_watchdog = run_watchdog; 651 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 652 653 if_attach(ifp); 654 ieee80211_ifattach(ifp); 655 ic->ic_node_alloc = run_node_alloc; 656 ic->ic_newassoc = run_newassoc; 657 ic->ic_updateslot = run_updateslot; 658 ic->ic_updateedca = run_updateedca; 659 ic->ic_set_key = run_set_key; 660 ic->ic_delete_key = run_delete_key; 661 /* override state transition machine */ 662 sc->sc_newstate = ic->ic_newstate; 663 ic->ic_newstate = run_newstate; 664 ieee80211_media_init(ifp, run_media_change, ieee80211_media_status); 665 666 #if NBPFILTER > 0 667 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO, 668 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 669 670 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 671 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 672 sc->sc_rxtap.wr_ihdr.it_present = htole32(RUN_RX_RADIOTAP_PRESENT); 673 674 sc->sc_txtap_len = sizeof sc->sc_txtapu; 675 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 676 sc->sc_txtap.wt_ihdr.it_present = htole32(RUN_TX_RADIOTAP_PRESENT); 677 #endif 678 } 679 680 int 681 run_detach(struct device *self, int flags) 682 { 683 struct run_softc *sc = (struct run_softc *)self; 684 struct ifnet *ifp = &sc->sc_ic.ic_if; 685 int qid, s; 686 687 s = splusb(); 688 689 if (timeout_initialized(&sc->scan_to)) 690 timeout_del(&sc->scan_to); 691 if (timeout_initialized(&sc->calib_to)) 692 timeout_del(&sc->calib_to); 693 694 /* wait for all queued asynchronous commands to complete */ 695 usb_rem_wait_task(sc->sc_udev, &sc->sc_task); 696 697 usbd_ref_wait(sc->sc_udev); 698 699 if (ifp->if_softc != NULL) { 700 ifp->if_flags &= ~IFF_RUNNING; 701 ifq_clr_oactive(&ifp->if_snd); 702 ieee80211_ifdetach(ifp); 703 if_detach(ifp); 704 } 705 706 for (qid = 0; qid < 4; qid++) 707 run_free_tx_ring(sc, qid); 708 run_free_rx_ring(sc); 709 710 splx(s); 711 712 return 0; 713 } 714 715 int 716 run_alloc_rx_ring(struct run_softc *sc) 717 { 718 struct run_rx_ring *rxq = &sc->rxq; 719 int i, error; 720 721 error = usbd_open_pipe(sc->sc_iface, rxq->pipe_no, 0, &rxq->pipeh); 722 if (error != 0) 723 goto fail; 724 725 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 726 struct run_rx_data *data = &rxq->data[i]; 727 728 data->sc = sc; /* backpointer for callbacks */ 729 730 data->xfer = usbd_alloc_xfer(sc->sc_udev); 731 if (data->xfer == NULL) { 732 error = ENOMEM; 733 goto fail; 734 } 735 data->buf = usbd_alloc_buffer(data->xfer, RUN_MAX_RXSZ); 736 if (data->buf == NULL) { 737 error = ENOMEM; 738 goto fail; 739 } 740 } 741 if (error != 0) 742 fail: run_free_rx_ring(sc); 743 return error; 744 } 745 746 void 747 run_free_rx_ring(struct run_softc *sc) 748 { 749 struct run_rx_ring *rxq = &sc->rxq; 750 int i; 751 752 if (rxq->pipeh != NULL) { 753 usbd_abort_pipe(rxq->pipeh); 754 usbd_close_pipe(rxq->pipeh); 755 rxq->pipeh = NULL; 756 } 757 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 758 if (rxq->data[i].xfer != NULL) 759 usbd_free_xfer(rxq->data[i].xfer); 760 rxq->data[i].xfer = NULL; 761 } 762 } 763 764 int 765 run_alloc_tx_ring(struct run_softc *sc, int qid) 766 { 767 struct run_tx_ring *txq = &sc->txq[qid]; 768 int i, error; 769 uint16_t txwisize; 770 771 txwisize = sizeof(struct rt2860_txwi); 772 if (sc->mac_ver == 0x5592) 773 txwisize += sizeof(uint32_t); 774 775 txq->cur = txq->queued = 0; 776 777 error = usbd_open_pipe(sc->sc_iface, txq->pipe_no, 0, &txq->pipeh); 778 if (error != 0) 779 goto fail; 780 781 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 782 struct run_tx_data *data = &txq->data[i]; 783 784 data->sc = sc; /* backpointer for callbacks */ 785 data->qid = qid; 786 787 data->xfer = usbd_alloc_xfer(sc->sc_udev); 788 if (data->xfer == NULL) { 789 error = ENOMEM; 790 goto fail; 791 } 792 data->buf = usbd_alloc_buffer(data->xfer, RUN_MAX_TXSZ); 793 if (data->buf == NULL) { 794 error = ENOMEM; 795 goto fail; 796 } 797 /* zeroize the TXD + TXWI part */ 798 memset(data->buf, 0, sizeof(struct rt2870_txd) + txwisize); 799 } 800 if (error != 0) 801 fail: run_free_tx_ring(sc, qid); 802 return error; 803 } 804 805 void 806 run_free_tx_ring(struct run_softc *sc, int qid) 807 { 808 struct run_tx_ring *txq = &sc->txq[qid]; 809 int i; 810 811 if (txq->pipeh != NULL) { 812 usbd_abort_pipe(txq->pipeh); 813 usbd_close_pipe(txq->pipeh); 814 txq->pipeh = NULL; 815 } 816 for (i = 0; i < RUN_TX_RING_COUNT; i++) { 817 if (txq->data[i].xfer != NULL) 818 usbd_free_xfer(txq->data[i].xfer); 819 txq->data[i].xfer = NULL; 820 } 821 } 822 823 int 824 run_load_microcode(struct run_softc *sc) 825 { 826 usb_device_request_t req; 827 const char *fwname; 828 u_char *ucode; 829 size_t size; 830 uint32_t tmp; 831 int ntries, error; 832 833 /* RT3071/RT3072 use a different firmware */ 834 if (sc->mac_ver != 0x2860 && 835 sc->mac_ver != 0x2872 && 836 sc->mac_ver != 0x3070) 837 fwname = "run-rt3071"; 838 else 839 fwname = "run-rt2870"; 840 841 if ((error = loadfirmware(fwname, &ucode, &size)) != 0) { 842 printf("%s: failed loadfirmware of file %s (error %d)\n", 843 sc->sc_dev.dv_xname, fwname, error); 844 return error; 845 } 846 if (size != 4096) { 847 printf("%s: invalid firmware size (should be 4KB)\n", 848 sc->sc_dev.dv_xname); 849 free(ucode, M_DEVBUF, size); 850 return EINVAL; 851 } 852 853 /* write microcode image */ 854 run_write_region_1(sc, RT2870_FW_BASE, ucode, size); 855 free(ucode, M_DEVBUF, size); 856 run_write(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 857 run_write(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 858 859 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 860 req.bRequest = RT2870_RESET; 861 USETW(req.wValue, 8); 862 USETW(req.wIndex, 0); 863 USETW(req.wLength, 0); 864 if ((error = usbd_do_request(sc->sc_udev, &req, NULL)) != 0) 865 return error; 866 867 usbd_delay_ms(sc->sc_udev, 10); 868 run_write(sc, RT2860_H2M_BBPAGENT, 0); 869 run_write(sc, RT2860_H2M_MAILBOX, 0); 870 run_write(sc, RT2860_H2M_INTSRC, 0); 871 if ((error = run_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0)) != 0) 872 return error; 873 874 /* wait until microcontroller is ready */ 875 for (ntries = 0; ntries < 1000; ntries++) { 876 if ((error = run_read(sc, RT2860_SYS_CTRL, &tmp)) != 0) 877 return error; 878 if (tmp & RT2860_MCU_READY) 879 break; 880 DELAY(1000); 881 } 882 if (ntries == 1000) { 883 printf("%s: timeout waiting for MCU to initialize\n", 884 sc->sc_dev.dv_xname); 885 return ETIMEDOUT; 886 } 887 DPRINTF(("microcode successfully loaded after %d tries\n", ntries)); 888 return 0; 889 } 890 891 int 892 run_reset(struct run_softc *sc) 893 { 894 usb_device_request_t req; 895 896 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 897 req.bRequest = RT2870_RESET; 898 USETW(req.wValue, 1); 899 USETW(req.wIndex, 0); 900 USETW(req.wLength, 0); 901 return usbd_do_request(sc->sc_udev, &req, NULL); 902 } 903 904 int 905 run_read(struct run_softc *sc, uint16_t reg, uint32_t *val) 906 { 907 uint32_t tmp; 908 int error; 909 910 error = run_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof tmp); 911 if (error == 0) 912 *val = letoh32(tmp); 913 else 914 *val = 0xffffffff; 915 return error; 916 } 917 918 int 919 run_read_region_1(struct run_softc *sc, uint16_t reg, uint8_t *buf, int len) 920 { 921 usb_device_request_t req; 922 923 req.bmRequestType = UT_READ_VENDOR_DEVICE; 924 req.bRequest = RT2870_READ_REGION_1; 925 USETW(req.wValue, 0); 926 USETW(req.wIndex, reg); 927 USETW(req.wLength, len); 928 return usbd_do_request(sc->sc_udev, &req, buf); 929 } 930 931 int 932 run_write_2(struct run_softc *sc, uint16_t reg, uint16_t val) 933 { 934 usb_device_request_t req; 935 936 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 937 req.bRequest = RT2870_WRITE_2; 938 USETW(req.wValue, val); 939 USETW(req.wIndex, reg); 940 USETW(req.wLength, 0); 941 return usbd_do_request(sc->sc_udev, &req, NULL); 942 } 943 944 int 945 run_write(struct run_softc *sc, uint16_t reg, uint32_t val) 946 { 947 int error; 948 949 if ((error = run_write_2(sc, reg, val & 0xffff)) == 0) 950 error = run_write_2(sc, reg + 2, val >> 16); 951 return error; 952 } 953 954 int 955 run_write_region_1(struct run_softc *sc, uint16_t reg, const uint8_t *buf, 956 int len) 957 { 958 #if 1 959 int i, error = 0; 960 /* 961 * NB: the WRITE_REGION_1 command is not stable on RT2860. 962 * We thus issue multiple WRITE_2 commands instead. 963 */ 964 KASSERT((len & 1) == 0); 965 for (i = 0; i < len && error == 0; i += 2) 966 error = run_write_2(sc, reg + i, buf[i] | buf[i + 1] << 8); 967 return error; 968 #else 969 usb_device_request_t req; 970 971 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 972 req.bRequest = RT2870_WRITE_REGION_1; 973 USETW(req.wValue, 0); 974 USETW(req.wIndex, reg); 975 USETW(req.wLength, len); 976 return usbd_do_request(sc->sc_udev, &req, buf); 977 #endif 978 } 979 980 int 981 run_set_region_4(struct run_softc *sc, uint16_t reg, uint32_t val, int count) 982 { 983 int error = 0; 984 985 for (; count > 0 && error == 0; count--, reg += 4) 986 error = run_write(sc, reg, val); 987 return error; 988 } 989 990 /* Read 16-bit from eFUSE ROM. */ 991 int 992 run_efuse_read(struct run_softc *sc, uint16_t addr, uint16_t *val) 993 { 994 uint32_t tmp; 995 uint16_t reg; 996 int error, ntries; 997 998 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 999 return error; 1000 1001 /*- 1002 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1003 * DATA0: F E D C 1004 * DATA1: B A 9 8 1005 * DATA2: 7 6 5 4 1006 * DATA3: 3 2 1 0 1007 */ 1008 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1009 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1010 run_write(sc, RT3070_EFUSE_CTRL, tmp); 1011 for (ntries = 0; ntries < 100; ntries++) { 1012 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1013 return error; 1014 if (!(tmp & RT3070_EFSROM_KICK)) 1015 break; 1016 DELAY(2); 1017 } 1018 if (ntries == 100) 1019 return ETIMEDOUT; 1020 1021 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) { 1022 *val = 0xffff; /* address not found */ 1023 return 0; 1024 } 1025 /* determine to which 32-bit register our 16-bit word belongs */ 1026 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1027 if ((error = run_read(sc, reg, &tmp)) != 0) 1028 return error; 1029 1030 tmp >>= (8 * (addr & 0x3)); 1031 *val = (addr & 1) ? tmp >> 16 : tmp & 0xffff; 1032 return 0; 1033 } 1034 1035 /* Read 16-bit from eFUSE ROM for RT3xxx. */ 1036 int 1037 run_efuse_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1038 { 1039 uint32_t tmp; 1040 uint16_t reg; 1041 int error, ntries; 1042 1043 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1044 return error; 1045 1046 addr *= 2; 1047 /*- 1048 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 1049 * DATA0: F E D C 1050 * DATA1: B A 9 8 1051 * DATA2: 7 6 5 4 1052 * DATA3: 3 2 1 0 1053 */ 1054 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 1055 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 1056 run_write(sc, RT3070_EFUSE_CTRL, tmp); 1057 for (ntries = 0; ntries < 100; ntries++) { 1058 if ((error = run_read(sc, RT3070_EFUSE_CTRL, &tmp)) != 0) 1059 return error; 1060 if (!(tmp & RT3070_EFSROM_KICK)) 1061 break; 1062 DELAY(2); 1063 } 1064 if (ntries == 100) 1065 return ETIMEDOUT; 1066 1067 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) { 1068 *val = 0xffff; /* address not found */ 1069 return 0; 1070 } 1071 /* determine to which 32-bit register our 16-bit word belongs */ 1072 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1073 if ((error = run_read(sc, reg, &tmp)) != 0) 1074 return error; 1075 1076 *val = (addr & 2) ? tmp >> 16 : tmp & 0xffff; 1077 return 0; 1078 } 1079 1080 int 1081 run_eeprom_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val) 1082 { 1083 usb_device_request_t req; 1084 uint16_t tmp; 1085 int error; 1086 1087 addr *= 2; 1088 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1089 req.bRequest = RT2870_EEPROM_READ; 1090 USETW(req.wValue, 0); 1091 USETW(req.wIndex, addr); 1092 USETW(req.wLength, sizeof tmp); 1093 error = usbd_do_request(sc->sc_udev, &req, &tmp); 1094 if (error == 0) 1095 *val = letoh16(tmp); 1096 else 1097 *val = 0xffff; 1098 return error; 1099 } 1100 1101 static __inline int 1102 run_srom_read(struct run_softc *sc, uint16_t addr, uint16_t *val) 1103 { 1104 /* either eFUSE ROM or EEPROM */ 1105 return sc->sc_srom_read(sc, addr, val); 1106 } 1107 1108 int 1109 run_rt2870_rf_write(struct run_softc *sc, uint8_t reg, uint32_t val) 1110 { 1111 uint32_t tmp; 1112 int error, ntries; 1113 1114 for (ntries = 0; ntries < 10; ntries++) { 1115 if ((error = run_read(sc, RT2860_RF_CSR_CFG0, &tmp)) != 0) 1116 return error; 1117 if (!(tmp & RT2860_RF_REG_CTRL)) 1118 break; 1119 } 1120 if (ntries == 10) 1121 return ETIMEDOUT; 1122 1123 /* RF registers are 24-bit on the RT2860 */ 1124 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 1125 (val & 0x3fffff) << 2 | (reg & 3); 1126 return run_write(sc, RT2860_RF_CSR_CFG0, tmp); 1127 } 1128 1129 int 1130 run_rt3070_rf_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1131 { 1132 uint32_t tmp; 1133 int error, ntries; 1134 1135 for (ntries = 0; ntries < 100; ntries++) { 1136 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1137 return error; 1138 if (!(tmp & RT3070_RF_KICK)) 1139 break; 1140 } 1141 if (ntries == 100) 1142 return ETIMEDOUT; 1143 1144 tmp = RT3070_RF_KICK | reg << 8; 1145 if ((error = run_write(sc, RT3070_RF_CSR_CFG, tmp)) != 0) 1146 return error; 1147 1148 for (ntries = 0; ntries < 100; ntries++) { 1149 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1150 return error; 1151 if (!(tmp & RT3070_RF_KICK)) 1152 break; 1153 } 1154 if (ntries == 100) 1155 return ETIMEDOUT; 1156 1157 *val = tmp & 0xff; 1158 return 0; 1159 } 1160 1161 int 1162 run_rt3070_rf_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1163 { 1164 uint32_t tmp; 1165 int error, ntries; 1166 1167 for (ntries = 0; ntries < 10; ntries++) { 1168 if ((error = run_read(sc, RT3070_RF_CSR_CFG, &tmp)) != 0) 1169 return error; 1170 if (!(tmp & RT3070_RF_KICK)) 1171 break; 1172 } 1173 if (ntries == 10) 1174 return ETIMEDOUT; 1175 1176 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 1177 return run_write(sc, RT3070_RF_CSR_CFG, tmp); 1178 } 1179 1180 int 1181 run_bbp_read(struct run_softc *sc, uint8_t reg, uint8_t *val) 1182 { 1183 uint32_t tmp; 1184 int ntries, error; 1185 1186 for (ntries = 0; ntries < 10; ntries++) { 1187 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1188 return error; 1189 if (!(tmp & RT2860_BBP_CSR_KICK)) 1190 break; 1191 } 1192 if (ntries == 10) 1193 return ETIMEDOUT; 1194 1195 tmp = RT2860_BBP_CSR_READ | RT2860_BBP_CSR_KICK | reg << 8; 1196 if ((error = run_write(sc, RT2860_BBP_CSR_CFG, tmp)) != 0) 1197 return error; 1198 1199 for (ntries = 0; ntries < 10; ntries++) { 1200 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1201 return error; 1202 if (!(tmp & RT2860_BBP_CSR_KICK)) 1203 break; 1204 } 1205 if (ntries == 10) 1206 return ETIMEDOUT; 1207 1208 *val = tmp & 0xff; 1209 return 0; 1210 } 1211 1212 int 1213 run_bbp_write(struct run_softc *sc, uint8_t reg, uint8_t val) 1214 { 1215 uint32_t tmp; 1216 int ntries, error; 1217 1218 for (ntries = 0; ntries < 10; ntries++) { 1219 if ((error = run_read(sc, RT2860_BBP_CSR_CFG, &tmp)) != 0) 1220 return error; 1221 if (!(tmp & RT2860_BBP_CSR_KICK)) 1222 break; 1223 } 1224 if (ntries == 10) 1225 return ETIMEDOUT; 1226 1227 tmp = RT2860_BBP_CSR_KICK | reg << 8 | val; 1228 return run_write(sc, RT2860_BBP_CSR_CFG, tmp); 1229 } 1230 1231 /* 1232 * Send a command to the 8051 microcontroller unit. 1233 */ 1234 int 1235 run_mcu_cmd(struct run_softc *sc, uint8_t cmd, uint16_t arg) 1236 { 1237 uint32_t tmp; 1238 int error, ntries; 1239 1240 for (ntries = 0; ntries < 100; ntries++) { 1241 if ((error = run_read(sc, RT2860_H2M_MAILBOX, &tmp)) != 0) 1242 return error; 1243 if (!(tmp & RT2860_H2M_BUSY)) 1244 break; 1245 } 1246 if (ntries == 100) 1247 return ETIMEDOUT; 1248 1249 tmp = RT2860_H2M_BUSY | RT2860_TOKEN_NO_INTR << 16 | arg; 1250 if ((error = run_write(sc, RT2860_H2M_MAILBOX, tmp)) == 0) 1251 error = run_write(sc, RT2860_HOST_CMD, cmd); 1252 return error; 1253 } 1254 1255 /* 1256 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 1257 * Used to adjust per-rate Tx power registers. 1258 */ 1259 static __inline uint32_t 1260 b4inc(uint32_t b32, int8_t delta) 1261 { 1262 int8_t i, b4; 1263 1264 for (i = 0; i < 8; i++) { 1265 b4 = b32 & 0xf; 1266 b4 += delta; 1267 if (b4 < 0) 1268 b4 = 0; 1269 else if (b4 > 0xf) 1270 b4 = 0xf; 1271 b32 = b32 >> 4 | b4 << 28; 1272 } 1273 return b32; 1274 } 1275 1276 const char * 1277 run_get_rf(int rev) 1278 { 1279 switch (rev) { 1280 case RT2860_RF_2820: return "RT2820"; 1281 case RT2860_RF_2850: return "RT2850"; 1282 case RT2860_RF_2720: return "RT2720"; 1283 case RT2860_RF_2750: return "RT2750"; 1284 case RT3070_RF_3020: return "RT3020"; 1285 case RT3070_RF_2020: return "RT2020"; 1286 case RT3070_RF_3021: return "RT3021"; 1287 case RT3070_RF_3022: return "RT3022"; 1288 case RT3070_RF_3052: return "RT3052"; 1289 case RT3070_RF_3053: return "RT3053"; 1290 case RT5592_RF_5592: return "RT5592"; 1291 case RT5390_RF_5370: return "RT5370"; 1292 case RT5390_RF_5372: return "RT5372"; 1293 } 1294 return "unknown"; 1295 } 1296 1297 void 1298 run_rt3593_get_txpower(struct run_softc *sc) 1299 { 1300 uint16_t addr, val; 1301 int i; 1302 1303 /* Read power settings for 2GHz channels. */ 1304 for (i = 0; i < 14; i += 2) { 1305 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE1 : 1306 RT2860_EEPROM_PWR2GHZ_BASE1; 1307 run_srom_read(sc, addr + i / 2, &val); 1308 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1309 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1310 1311 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE2 : 1312 RT2860_EEPROM_PWR2GHZ_BASE2; 1313 run_srom_read(sc, addr + i / 2, &val); 1314 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1315 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1316 1317 if (sc->ntxchains == 3) { 1318 run_srom_read(sc, RT3593_EEPROM_PWR2GHZ_BASE3 + i / 2, 1319 &val); 1320 sc->txpow3[i + 0] = (int8_t)(val & 0xff); 1321 sc->txpow3[i + 1] = (int8_t)(val >> 8); 1322 } 1323 } 1324 /* Fix broken Tx power entries. */ 1325 for (i = 0; i < 14; i++) { 1326 if (sc->txpow1[i] > 31) 1327 sc->txpow1[i] = 5; 1328 if (sc->txpow2[i] > 31) 1329 sc->txpow2[i] = 5; 1330 if (sc->ntxchains == 3) { 1331 if (sc->txpow3[i] > 31) 1332 sc->txpow3[i] = 5; 1333 } 1334 } 1335 /* Read power settings for 5GHz channels. */ 1336 for (i = 0; i < 40; i += 2) { 1337 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1338 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1339 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1340 1341 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1342 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1343 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1344 1345 if (sc->ntxchains == 3) { 1346 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE3 + i / 2, 1347 &val); 1348 sc->txpow3[i + 14] = (int8_t)(val & 0xff); 1349 sc->txpow3[i + 15] = (int8_t)(val >> 8); 1350 } 1351 } 1352 } 1353 1354 void 1355 run_get_txpower(struct run_softc *sc) 1356 { 1357 uint16_t val; 1358 int i; 1359 1360 /* Read power settings for 2GHz channels. */ 1361 for (i = 0; i < 14; i += 2) { 1362 run_srom_read(sc, RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2, &val); 1363 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 1364 sc->txpow1[i + 1] = (int8_t)(val >> 8); 1365 1366 if (sc->mac_ver != 0x5390) { 1367 run_srom_read(sc, 1368 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2, &val); 1369 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 1370 sc->txpow2[i + 1] = (int8_t)(val >> 8); 1371 } 1372 } 1373 /* Fix broken Tx power entries. */ 1374 for (i = 0; i < 14; i++) { 1375 if (sc->mac_ver >= 0x5390) { 1376 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 27) 1377 sc->txpow1[i] = 5; 1378 } else { 1379 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31) 1380 sc->txpow1[i] = 5; 1381 } 1382 if (sc->mac_ver > 0x5390) { 1383 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 27) 1384 sc->txpow2[i] = 5; 1385 } else if (sc->mac_ver < 0x5390) { 1386 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31) 1387 sc->txpow2[i] = 5; 1388 } 1389 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1390 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 1391 } 1392 /* Read power settings for 5GHz channels. */ 1393 for (i = 0; i < 40; i += 2) { 1394 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2, &val); 1395 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 1396 sc->txpow1[i + 15] = (int8_t)(val >> 8); 1397 1398 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2, &val); 1399 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 1400 sc->txpow2[i + 15] = (int8_t)(val >> 8); 1401 } 1402 /* Fix broken Tx power entries. */ 1403 for (i = 0; i < 40; i++ ) { 1404 if (sc->mac_ver != 0x5592) { 1405 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 1406 sc->txpow1[14 + i] = 5; 1407 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 1408 sc->txpow2[14 + i] = 5; 1409 } 1410 DPRINTF(("chan %d: power1=%d, power2=%d\n", 1411 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 1412 sc->txpow2[14 + i])); 1413 } 1414 } 1415 1416 int 1417 run_read_eeprom(struct run_softc *sc) 1418 { 1419 struct ieee80211com *ic = &sc->sc_ic; 1420 int8_t delta_2ghz, delta_5ghz; 1421 uint32_t tmp; 1422 uint16_t val; 1423 int ridx, ant, i; 1424 1425 /* check whether the ROM is eFUSE ROM or EEPROM */ 1426 sc->sc_srom_read = run_eeprom_read_2; 1427 if (sc->mac_ver >= 0x3070) { 1428 run_read(sc, RT3070_EFUSE_CTRL, &tmp); 1429 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 1430 if (tmp & RT3070_SEL_EFUSE || sc->mac_ver == 0x3593) 1431 sc->sc_srom_read = run_efuse_read_2; 1432 } 1433 1434 /* read ROM version */ 1435 run_srom_read(sc, RT2860_EEPROM_VERSION, &val); 1436 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); 1437 1438 /* read MAC address */ 1439 run_srom_read(sc, RT2860_EEPROM_MAC01, &val); 1440 ic->ic_myaddr[0] = val & 0xff; 1441 ic->ic_myaddr[1] = val >> 8; 1442 run_srom_read(sc, RT2860_EEPROM_MAC23, &val); 1443 ic->ic_myaddr[2] = val & 0xff; 1444 ic->ic_myaddr[3] = val >> 8; 1445 run_srom_read(sc, RT2860_EEPROM_MAC45, &val); 1446 ic->ic_myaddr[4] = val & 0xff; 1447 ic->ic_myaddr[5] = val >> 8; 1448 1449 if (sc->mac_ver < 0x3593) { 1450 /* read vendor BBP settings */ 1451 for (i = 0; i < 10; i++) { 1452 run_srom_read(sc, RT2860_EEPROM_BBP_BASE + i, &val); 1453 sc->bbp[i].val = val & 0xff; 1454 sc->bbp[i].reg = val >> 8; 1455 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, 1456 sc->bbp[i].val)); 1457 } 1458 if (sc->mac_ver >= 0x3071) { 1459 /* read vendor RF settings */ 1460 for (i = 0; i < 10; i++) { 1461 run_srom_read(sc, RT3071_EEPROM_RF_BASE + i, 1462 &val); 1463 sc->rf[i].val = val & 0xff; 1464 sc->rf[i].reg = val >> 8; 1465 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 1466 sc->rf[i].val)); 1467 } 1468 } 1469 } 1470 1471 /* read RF frequency offset from EEPROM */ 1472 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_FREQ_LEDS : 1473 RT3593_EEPROM_FREQ, &val); 1474 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 1475 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 1476 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_FREQ_LEDS : 1477 RT3593_EEPROM_FREQ_LEDS, &val); 1478 if ((val >> 8) != 0xff) { 1479 /* read LEDs operating mode */ 1480 sc->leds = val >> 8; 1481 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED1 : 1482 RT3593_EEPROM_LED1, &sc->led[0]); 1483 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED2 : 1484 RT3593_EEPROM_LED2, &sc->led[1]); 1485 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED3 : 1486 RT3593_EEPROM_LED3, &sc->led[2]); 1487 } else { 1488 /* broken EEPROM, use default settings */ 1489 sc->leds = 0x01; 1490 sc->led[0] = 0x5555; 1491 sc->led[1] = 0x2221; 1492 sc->led[2] = 0x5627; /* differs from RT2860 */ 1493 } 1494 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 1495 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 1496 1497 /* read RF information */ 1498 if (sc->mac_ver == 0x5390 || sc->mac_ver == 0x5392) 1499 run_srom_read(sc, 0x00, &val); 1500 else 1501 run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val); 1502 if (val == 0xffff) { 1503 DPRINTF(("invalid EEPROM antenna info, using default\n")); 1504 if (sc->mac_ver == 0x3572) { 1505 /* default to RF3052 2T2R */ 1506 sc->rf_rev = RT3070_RF_3052; 1507 sc->ntxchains = 2; 1508 sc->nrxchains = 2; 1509 } else if (sc->mac_ver >= 0x3070) { 1510 /* default to RF3020 1T1R */ 1511 sc->rf_rev = RT3070_RF_3020; 1512 sc->ntxchains = 1; 1513 sc->nrxchains = 1; 1514 } else { 1515 /* default to RF2820 1T2R */ 1516 sc->rf_rev = RT2860_RF_2820; 1517 sc->ntxchains = 1; 1518 sc->nrxchains = 2; 1519 } 1520 } else { 1521 if (sc->mac_ver == 0x5390 || sc->mac_ver == 0x5392) { 1522 sc->rf_rev = val; 1523 run_srom_read(sc, RT2860_EEPROM_ANTENNA, &val); 1524 } else 1525 sc->rf_rev = (val >> 8) & 0xf; 1526 sc->ntxchains = (val >> 4) & 0xf; 1527 sc->nrxchains = val & 0xf; 1528 } 1529 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 1530 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 1531 1532 /* check if RF supports automatic Tx access gain control */ 1533 run_srom_read(sc, RT2860_EEPROM_CONFIG, &val); 1534 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 1535 /* check if driver should patch the DAC issue */ 1536 if ((val >> 8) != 0xff) 1537 sc->patch_dac = (val >> 15) & 1; 1538 if ((val & 0xff) != 0xff) { 1539 sc->ext_5ghz_lna = (val >> 3) & 1; 1540 sc->ext_2ghz_lna = (val >> 2) & 1; 1541 /* check if RF supports automatic Tx access gain control */ 1542 sc->calib_2ghz = sc->calib_5ghz = (val >> 1) & 1; 1543 /* check if we have a hardware radio switch */ 1544 sc->rfswitch = val & 1; 1545 } 1546 1547 /* Read Tx power settings. */ 1548 if (sc->mac_ver == 0x3593) 1549 run_rt3593_get_txpower(sc); 1550 else 1551 run_get_txpower(sc); 1552 1553 /* read Tx power compensation for each Tx rate */ 1554 run_srom_read(sc, RT2860_EEPROM_DELTAPWR, &val); 1555 delta_2ghz = delta_5ghz = 0; 1556 if ((val & 0xff) != 0xff && (val & 0x80)) { 1557 delta_2ghz = val & 0xf; 1558 if (!(val & 0x40)) /* negative number */ 1559 delta_2ghz = -delta_2ghz; 1560 } 1561 val >>= 8; 1562 if ((val & 0xff) != 0xff && (val & 0x80)) { 1563 delta_5ghz = val & 0xf; 1564 if (!(val & 0x40)) /* negative number */ 1565 delta_5ghz = -delta_5ghz; 1566 } 1567 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 1568 delta_2ghz, delta_5ghz)); 1569 1570 for (ridx = 0; ridx < 5; ridx++) { 1571 uint32_t reg; 1572 1573 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2, &val); 1574 reg = val; 1575 run_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1, &val); 1576 reg |= (uint32_t)val << 16; 1577 1578 sc->txpow20mhz[ridx] = reg; 1579 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 1580 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 1581 1582 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 1583 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 1584 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 1585 } 1586 1587 /* read RSSI offsets and LNA gains from EEPROM */ 1588 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_2GHZ : 1589 RT3593_EEPROM_RSSI1_2GHZ, &val); 1590 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 1591 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 1592 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_2GHZ : 1593 RT3593_EEPROM_RSSI2_2GHZ, &val); 1594 if (sc->mac_ver >= 0x3070) { 1595 if (sc->mac_ver == 0x3593) { 1596 sc->txmixgain_2ghz = 0; 1597 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1598 } else { 1599 /* 1600 * On RT3070 chips (limited to 2 Rx chains), this ROM 1601 * field contains the Tx mixer gain for the 2GHz band. 1602 */ 1603 if ((val & 0xff) != 0xff) 1604 sc->txmixgain_2ghz = val & 0x7; 1605 } 1606 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 1607 } else 1608 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 1609 if (sc->mac_ver == 0x3593) 1610 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1611 sc->lna[2] = val >> 8; /* channel group 2 */ 1612 1613 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_5GHZ : 1614 RT3593_EEPROM_RSSI1_5GHZ, &val); 1615 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 1616 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 1617 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_5GHZ : 1618 RT3593_EEPROM_RSSI2_5GHZ, &val); 1619 if (sc->mac_ver == 0x3572) { 1620 /* 1621 * On RT3572 chips (limited to 2 Rx chains), this ROM 1622 * field contains the Tx mixer gain for the 5GHz band. 1623 */ 1624 if ((val & 0xff) != 0xff) 1625 sc->txmixgain_5ghz = val & 0x7; 1626 DPRINTF(("tx mixer gain=%u (5GHz)\n", sc->txmixgain_5ghz)); 1627 } else 1628 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 1629 if (sc->mac_ver == 0x3593) { 1630 sc->txmixgain_5ghz = 0; 1631 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ, &val); 1632 } 1633 sc->lna[3] = val >> 8; /* channel group 3 */ 1634 1635 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LNA : 1636 RT3593_EEPROM_LNA, &val); 1637 sc->lna[0] = val & 0xff; /* channel group 0 */ 1638 sc->lna[1] = val >> 8; /* channel group 1 */ 1639 1640 /* fix broken 5GHz LNA entries */ 1641 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 1642 DPRINTF(("invalid LNA for channel group %d\n", 2)); 1643 sc->lna[2] = sc->lna[1]; 1644 } 1645 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 1646 DPRINTF(("invalid LNA for channel group %d\n", 3)); 1647 sc->lna[3] = sc->lna[1]; 1648 } 1649 1650 /* fix broken RSSI offset entries */ 1651 for (ant = 0; ant < 3; ant++) { 1652 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 1653 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 1654 ant + 1, sc->rssi_2ghz[ant])); 1655 sc->rssi_2ghz[ant] = 0; 1656 } 1657 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 1658 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 1659 ant + 1, sc->rssi_5ghz[ant])); 1660 sc->rssi_5ghz[ant] = 0; 1661 } 1662 } 1663 return 0; 1664 } 1665 1666 struct ieee80211_node * 1667 run_node_alloc(struct ieee80211com *ic) 1668 { 1669 return malloc(sizeof (struct run_node), M_DEVBUF, M_NOWAIT | M_ZERO); 1670 } 1671 1672 int 1673 run_media_change(struct ifnet *ifp) 1674 { 1675 struct run_softc *sc = ifp->if_softc; 1676 struct ieee80211com *ic = &sc->sc_ic; 1677 uint8_t rate, ridx; 1678 int error; 1679 1680 error = ieee80211_media_change(ifp); 1681 if (error != ENETRESET) 1682 return error; 1683 1684 if (ic->ic_fixed_rate != -1) { 1685 rate = ic->ic_sup_rates[ic->ic_curmode]. 1686 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1687 for (ridx = 0; ridx <= RT2860_RIDX_MAX; ridx++) 1688 if (rt2860_rates[ridx].rate == rate) 1689 break; 1690 sc->fixed_ridx = ridx; 1691 } 1692 1693 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1694 (IFF_UP | IFF_RUNNING)) { 1695 run_stop(ifp, 0); 1696 error = run_init(ifp); 1697 } 1698 1699 return error; 1700 } 1701 1702 void 1703 run_next_scan(void *arg) 1704 { 1705 struct run_softc *sc = arg; 1706 1707 if (usbd_is_dying(sc->sc_udev)) 1708 return; 1709 1710 usbd_ref_incr(sc->sc_udev); 1711 1712 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN) 1713 ieee80211_next_scan(&sc->sc_ic.ic_if); 1714 1715 usbd_ref_decr(sc->sc_udev); 1716 } 1717 1718 void 1719 run_task(void *arg) 1720 { 1721 struct run_softc *sc = arg; 1722 struct run_host_cmd_ring *ring = &sc->cmdq; 1723 struct run_host_cmd *cmd; 1724 int s; 1725 1726 if (usbd_is_dying(sc->sc_udev)) 1727 return; 1728 1729 /* process host commands */ 1730 s = splusb(); 1731 while (ring->next != ring->cur) { 1732 cmd = &ring->cmd[ring->next]; 1733 splx(s); 1734 /* callback */ 1735 cmd->cb(sc, cmd->data); 1736 s = splusb(); 1737 ring->queued--; 1738 ring->next = (ring->next + 1) % RUN_HOST_CMD_RING_COUNT; 1739 } 1740 splx(s); 1741 } 1742 1743 void 1744 run_do_async(struct run_softc *sc, void (*cb)(struct run_softc *, void *), 1745 void *arg, int len) 1746 { 1747 struct run_host_cmd_ring *ring = &sc->cmdq; 1748 struct run_host_cmd *cmd; 1749 int s; 1750 1751 if (usbd_is_dying(sc->sc_udev)) 1752 return; 1753 1754 s = splusb(); 1755 cmd = &ring->cmd[ring->cur]; 1756 cmd->cb = cb; 1757 KASSERT(len <= sizeof (cmd->data)); 1758 memcpy(cmd->data, arg, len); 1759 ring->cur = (ring->cur + 1) % RUN_HOST_CMD_RING_COUNT; 1760 1761 /* if there is no pending command already, schedule a task */ 1762 if (++ring->queued == 1) 1763 usb_add_task(sc->sc_udev, &sc->sc_task); 1764 splx(s); 1765 } 1766 1767 int 1768 run_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1769 { 1770 struct run_softc *sc = ic->ic_softc; 1771 struct run_cmd_newstate cmd; 1772 1773 /* do it in a process context */ 1774 cmd.state = nstate; 1775 cmd.arg = arg; 1776 run_do_async(sc, run_newstate_cb, &cmd, sizeof cmd); 1777 return 0; 1778 } 1779 1780 void 1781 run_newstate_cb(struct run_softc *sc, void *arg) 1782 { 1783 struct run_cmd_newstate *cmd = arg; 1784 struct ieee80211com *ic = &sc->sc_ic; 1785 enum ieee80211_state ostate; 1786 struct ieee80211_node *ni; 1787 uint32_t tmp, sta[3]; 1788 uint8_t wcid; 1789 int s; 1790 1791 s = splnet(); 1792 ostate = ic->ic_state; 1793 1794 if (ostate == IEEE80211_S_RUN) { 1795 /* turn link LED off */ 1796 run_set_leds(sc, RT2860_LED_RADIO); 1797 } 1798 1799 switch (cmd->state) { 1800 case IEEE80211_S_INIT: 1801 if (ostate == IEEE80211_S_RUN) { 1802 /* abort TSF synchronization */ 1803 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 1804 run_write(sc, RT2860_BCN_TIME_CFG, 1805 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 1806 RT2860_TBTT_TIMER_EN)); 1807 } 1808 break; 1809 1810 case IEEE80211_S_SCAN: 1811 run_set_chan(sc, ic->ic_bss->ni_chan); 1812 if (!usbd_is_dying(sc->sc_udev)) 1813 timeout_add_msec(&sc->scan_to, 200); 1814 break; 1815 1816 case IEEE80211_S_AUTH: 1817 case IEEE80211_S_ASSOC: 1818 run_set_chan(sc, ic->ic_bss->ni_chan); 1819 break; 1820 1821 case IEEE80211_S_RUN: 1822 run_set_chan(sc, ic->ic_bss->ni_chan); 1823 1824 ni = ic->ic_bss; 1825 1826 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1827 run_updateslot(ic); 1828 run_enable_mrr(sc); 1829 run_set_txpreamble(sc); 1830 run_set_basicrates(sc); 1831 run_set_bssid(sc, ni->ni_bssid); 1832 } 1833 if (ic->ic_opmode == IEEE80211_M_STA) { 1834 /* add BSS entry to the WCID table */ 1835 wcid = RUN_AID2WCID(ni->ni_associd); 1836 run_write_region_1(sc, RT2860_WCID_ENTRY(wcid), 1837 ni->ni_macaddr, IEEE80211_ADDR_LEN); 1838 1839 /* fake a join to init the tx rate */ 1840 run_newassoc(ic, ni, 1); 1841 } 1842 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1843 run_enable_tsf_sync(sc); 1844 1845 /* clear statistic registers used by AMRR */ 1846 run_read_region_1(sc, RT2860_TX_STA_CNT0, 1847 (uint8_t *)sta, sizeof sta); 1848 /* start calibration timer */ 1849 if (!usbd_is_dying(sc->sc_udev)) 1850 timeout_add_sec(&sc->calib_to, 1); 1851 } 1852 1853 /* turn link LED on */ 1854 run_set_leds(sc, RT2860_LED_RADIO | 1855 (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan) ? 1856 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 1857 break; 1858 } 1859 (void)sc->sc_newstate(ic, cmd->state, cmd->arg); 1860 splx(s); 1861 } 1862 1863 void 1864 run_updateedca(struct ieee80211com *ic) 1865 { 1866 /* do it in a process context */ 1867 run_do_async(ic->ic_softc, run_updateedca_cb, NULL, 0); 1868 } 1869 1870 /* ARGSUSED */ 1871 void 1872 run_updateedca_cb(struct run_softc *sc, void *arg) 1873 { 1874 struct ieee80211com *ic = &sc->sc_ic; 1875 int s, aci; 1876 1877 s = splnet(); 1878 /* update MAC TX configuration registers */ 1879 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 1880 run_write(sc, RT2860_EDCA_AC_CFG(aci), 1881 ic->ic_edca_ac[aci].ac_ecwmax << 16 | 1882 ic->ic_edca_ac[aci].ac_ecwmin << 12 | 1883 ic->ic_edca_ac[aci].ac_aifsn << 8 | 1884 ic->ic_edca_ac[aci].ac_txoplimit); 1885 } 1886 1887 /* update SCH/DMA registers too */ 1888 run_write(sc, RT2860_WMM_AIFSN_CFG, 1889 ic->ic_edca_ac[EDCA_AC_VO].ac_aifsn << 12 | 1890 ic->ic_edca_ac[EDCA_AC_VI].ac_aifsn << 8 | 1891 ic->ic_edca_ac[EDCA_AC_BK].ac_aifsn << 4 | 1892 ic->ic_edca_ac[EDCA_AC_BE].ac_aifsn); 1893 run_write(sc, RT2860_WMM_CWMIN_CFG, 1894 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmin << 12 | 1895 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmin << 8 | 1896 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmin << 4 | 1897 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmin); 1898 run_write(sc, RT2860_WMM_CWMAX_CFG, 1899 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmax << 12 | 1900 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmax << 8 | 1901 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmax << 4 | 1902 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmax); 1903 run_write(sc, RT2860_WMM_TXOP0_CFG, 1904 ic->ic_edca_ac[EDCA_AC_BK].ac_txoplimit << 16 | 1905 ic->ic_edca_ac[EDCA_AC_BE].ac_txoplimit); 1906 run_write(sc, RT2860_WMM_TXOP1_CFG, 1907 ic->ic_edca_ac[EDCA_AC_VO].ac_txoplimit << 16 | 1908 ic->ic_edca_ac[EDCA_AC_VI].ac_txoplimit); 1909 splx(s); 1910 } 1911 1912 int 1913 run_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1914 struct ieee80211_key *k) 1915 { 1916 struct run_softc *sc = ic->ic_softc; 1917 struct run_cmd_key cmd; 1918 1919 /* defer setting of WEP keys until interface is brought up */ 1920 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 1921 (IFF_UP | IFF_RUNNING)) 1922 return 0; 1923 1924 /* do it in a process context */ 1925 cmd.key = *k; 1926 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 1927 run_do_async(sc, run_set_key_cb, &cmd, sizeof cmd); 1928 return 0; 1929 } 1930 1931 void 1932 run_set_key_cb(struct run_softc *sc, void *arg) 1933 { 1934 struct run_cmd_key *cmd = arg; 1935 struct ieee80211_key *k = &cmd->key; 1936 uint32_t attr; 1937 uint16_t base; 1938 uint8_t mode, wcid, iv[8]; 1939 1940 /* map net80211 cipher to RT2860 security mode */ 1941 switch (k->k_cipher) { 1942 case IEEE80211_CIPHER_WEP40: 1943 mode = RT2860_MODE_WEP40; 1944 break; 1945 case IEEE80211_CIPHER_WEP104: 1946 mode = RT2860_MODE_WEP104; 1947 break; 1948 case IEEE80211_CIPHER_TKIP: 1949 mode = RT2860_MODE_TKIP; 1950 break; 1951 case IEEE80211_CIPHER_CCMP: 1952 mode = RT2860_MODE_AES_CCMP; 1953 break; 1954 default: 1955 return; 1956 } 1957 1958 if (k->k_flags & IEEE80211_KEY_GROUP) { 1959 wcid = 0; /* NB: update WCID0 for group keys */ 1960 base = RT2860_SKEY(0, k->k_id); 1961 } else { 1962 wcid = RUN_AID2WCID(cmd->associd); 1963 base = RT2860_PKEY(wcid); 1964 } 1965 1966 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 1967 run_write_region_1(sc, base, k->k_key, 16); 1968 run_write_region_1(sc, base + 16, &k->k_key[24], 8); 1969 run_write_region_1(sc, base + 24, &k->k_key[16], 8); 1970 } else { 1971 /* roundup len to 16-bit: XXX fix write_region_1() instead */ 1972 run_write_region_1(sc, base, k->k_key, (k->k_len + 1) & ~1); 1973 } 1974 1975 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 1976 (k->k_flags & IEEE80211_KEY_TX)) { 1977 /* set initial packet number in IV+EIV */ 1978 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 1979 k->k_cipher == IEEE80211_CIPHER_WEP104) { 1980 memset(iv, 0, sizeof iv); 1981 iv[3] = sc->sc_ic.ic_def_txkey << 6; 1982 } else { 1983 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 1984 iv[0] = k->k_tsc >> 8; 1985 iv[1] = (iv[0] | 0x20) & 0x7f; 1986 iv[2] = k->k_tsc; 1987 } else /* CCMP */ { 1988 iv[0] = k->k_tsc; 1989 iv[1] = k->k_tsc >> 8; 1990 iv[2] = 0; 1991 } 1992 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 1993 iv[4] = k->k_tsc >> 16; 1994 iv[5] = k->k_tsc >> 24; 1995 iv[6] = k->k_tsc >> 32; 1996 iv[7] = k->k_tsc >> 40; 1997 } 1998 run_write_region_1(sc, RT2860_IVEIV(wcid), iv, 8); 1999 } 2000 2001 if (k->k_flags & IEEE80211_KEY_GROUP) { 2002 /* install group key */ 2003 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2004 attr &= ~(0xf << (k->k_id * 4)); 2005 attr |= mode << (k->k_id * 4); 2006 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2007 } else { 2008 /* install pairwise key */ 2009 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2010 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 2011 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2012 } 2013 } 2014 2015 void 2016 run_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 2017 struct ieee80211_key *k) 2018 { 2019 struct run_softc *sc = ic->ic_softc; 2020 struct run_cmd_key cmd; 2021 2022 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 2023 ic->ic_state != IEEE80211_S_RUN) 2024 return; /* nothing to do */ 2025 2026 /* do it in a process context */ 2027 cmd.key = *k; 2028 cmd.associd = (ni != NULL) ? ni->ni_associd : 0; 2029 run_do_async(sc, run_delete_key_cb, &cmd, sizeof cmd); 2030 } 2031 2032 void 2033 run_delete_key_cb(struct run_softc *sc, void *arg) 2034 { 2035 struct run_cmd_key *cmd = arg; 2036 struct ieee80211_key *k = &cmd->key; 2037 uint32_t attr; 2038 uint8_t wcid; 2039 2040 if (k->k_flags & IEEE80211_KEY_GROUP) { 2041 /* remove group key */ 2042 run_read(sc, RT2860_SKEY_MODE_0_7, &attr); 2043 attr &= ~(0xf << (k->k_id * 4)); 2044 run_write(sc, RT2860_SKEY_MODE_0_7, attr); 2045 2046 } else { 2047 /* remove pairwise key */ 2048 wcid = RUN_AID2WCID(cmd->associd); 2049 run_read(sc, RT2860_WCID_ATTR(wcid), &attr); 2050 attr &= ~0xf; 2051 run_write(sc, RT2860_WCID_ATTR(wcid), attr); 2052 } 2053 } 2054 2055 void 2056 run_calibrate_to(void *arg) 2057 { 2058 /* do it in a process context */ 2059 run_do_async(arg, run_calibrate_cb, NULL, 0); 2060 /* next timeout will be rescheduled in the calibration task */ 2061 } 2062 2063 /* ARGSUSED */ 2064 void 2065 run_calibrate_cb(struct run_softc *sc, void *arg) 2066 { 2067 struct ifnet *ifp = &sc->sc_ic.ic_if; 2068 uint32_t sta[3]; 2069 int s, error; 2070 2071 /* read statistic counters (clear on read) and update AMRR state */ 2072 error = run_read_region_1(sc, RT2860_TX_STA_CNT0, (uint8_t *)sta, 2073 sizeof sta); 2074 if (error != 0) 2075 goto skip; 2076 2077 DPRINTF(("retrycnt=%d txcnt=%d failcnt=%d\n", 2078 letoh32(sta[1]) >> 16, letoh32(sta[1]) & 0xffff, 2079 letoh32(sta[0]) & 0xffff)); 2080 2081 s = splnet(); 2082 /* count failed TX as errors */ 2083 ifp->if_oerrors += letoh32(sta[0]) & 0xffff; 2084 2085 sc->amn.amn_retrycnt = 2086 (letoh32(sta[0]) & 0xffff) + /* failed TX count */ 2087 (letoh32(sta[1]) >> 16); /* TX retransmission count */ 2088 2089 sc->amn.amn_txcnt = 2090 sc->amn.amn_retrycnt + 2091 (letoh32(sta[1]) & 0xffff); /* successful TX count */ 2092 2093 ieee80211_amrr_choose(&sc->amrr, sc->sc_ic.ic_bss, &sc->amn); 2094 splx(s); 2095 2096 skip: 2097 if (!usbd_is_dying(sc->sc_udev)) 2098 timeout_add_sec(&sc->calib_to, 1); 2099 } 2100 2101 void 2102 run_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 2103 { 2104 struct run_softc *sc = ic->ic_softc; 2105 struct run_node *rn = (void *)ni; 2106 struct ieee80211_rateset *rs = &ni->ni_rates; 2107 uint8_t rate; 2108 int ridx, i, j; 2109 2110 DPRINTF(("new assoc isnew=%d addr=%s\n", 2111 isnew, ether_sprintf(ni->ni_macaddr))); 2112 2113 ieee80211_amrr_node_init(&sc->amrr, &sc->amn); 2114 /* start at lowest available bit-rate, AMRR will raise */ 2115 ni->ni_txrate = 0; 2116 2117 for (i = 0; i < rs->rs_nrates; i++) { 2118 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL; 2119 /* convert 802.11 rate to hardware rate index */ 2120 for (ridx = 0; ridx < RT2860_RIDX_MAX; ridx++) 2121 if (rt2860_rates[ridx].rate == rate) 2122 break; 2123 rn->ridx[i] = ridx; 2124 /* determine rate of control response frames */ 2125 for (j = i; j >= 0; j--) { 2126 if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC) && 2127 rt2860_rates[rn->ridx[i]].phy == 2128 rt2860_rates[rn->ridx[j]].phy) 2129 break; 2130 } 2131 if (j >= 0) { 2132 rn->ctl_ridx[i] = rn->ridx[j]; 2133 } else { 2134 /* no basic rate found, use mandatory one */ 2135 rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx; 2136 } 2137 DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n", 2138 rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i])); 2139 } 2140 } 2141 2142 /* 2143 * Return the Rx chain with the highest RSSI for a given frame. 2144 */ 2145 static __inline uint8_t 2146 run_maxrssi_chain(struct run_softc *sc, const struct rt2860_rxwi *rxwi) 2147 { 2148 uint8_t rxchain = 0; 2149 2150 if (sc->nrxchains > 1) { 2151 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 2152 rxchain = 1; 2153 if (sc->nrxchains > 2) 2154 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 2155 rxchain = 2; 2156 } 2157 return rxchain; 2158 } 2159 2160 void 2161 run_rx_frame(struct run_softc *sc, uint8_t *buf, int dmalen, 2162 struct mbuf_list *ml) 2163 { 2164 struct ieee80211com *ic = &sc->sc_ic; 2165 struct ifnet *ifp = &ic->ic_if; 2166 struct ieee80211_frame *wh; 2167 struct ieee80211_rxinfo rxi; 2168 struct ieee80211_node *ni; 2169 struct rt2870_rxd *rxd; 2170 struct rt2860_rxwi *rxwi; 2171 struct mbuf *m; 2172 uint32_t flags; 2173 uint16_t len; 2174 #if NBPFILTER > 0 2175 uint16_t phy; 2176 #endif 2177 uint16_t rxwisize; 2178 uint8_t ant, rssi; 2179 int s; 2180 2181 rxwi = (struct rt2860_rxwi *)buf; 2182 rxwisize = sizeof(struct rt2860_rxwi); 2183 if (sc->mac_ver == 0x5592) 2184 rxwisize += sizeof(uint64_t); 2185 else if (sc->mac_ver == 0x3593) 2186 rxwisize += sizeof(uint32_t); 2187 len = letoh16(rxwi->len) & 0xfff; 2188 if (__predict_false(len > dmalen)) { 2189 DPRINTF(("bad RXWI length %u > %u\n", len, dmalen)); 2190 return; 2191 } 2192 if (len > MCLBYTES) { 2193 DPRINTF(("frame too large (length=%d)\n", len)); 2194 ifp->if_ierrors++; 2195 return; 2196 } 2197 /* Rx descriptor is located at the end */ 2198 rxd = (struct rt2870_rxd *)(buf + dmalen); 2199 flags = letoh32(rxd->flags); 2200 2201 if (__predict_false(flags & (RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 2202 ifp->if_ierrors++; 2203 return; 2204 } 2205 2206 if (__predict_false((flags & RT2860_RX_MICERR))) { 2207 /* report MIC failures to net80211 for TKIP */ 2208 ic->ic_stats.is_rx_locmicfail++; 2209 ieee80211_michael_mic_failure(ic, 0/* XXX */); 2210 ifp->if_ierrors++; 2211 return; 2212 } 2213 2214 wh = (struct ieee80211_frame *)(buf + rxwisize); 2215 rxi.rxi_flags = 0; 2216 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 2217 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 2218 rxi.rxi_flags |= IEEE80211_RXI_HWDEC; 2219 } 2220 2221 if (flags & RT2860_RX_L2PAD) { 2222 u_int hdrlen = ieee80211_get_hdrlen(wh); 2223 memmove((caddr_t)wh + 2, wh, hdrlen); 2224 wh = (struct ieee80211_frame *)((caddr_t)wh + 2); 2225 } 2226 2227 /* could use m_devget but net80211 wants contig mgmt frames */ 2228 MGETHDR(m, M_DONTWAIT, MT_DATA); 2229 if (__predict_false(m == NULL)) { 2230 ifp->if_ierrors++; 2231 return; 2232 } 2233 if (len > MHLEN) { 2234 MCLGET(m, M_DONTWAIT); 2235 if (__predict_false(!(m->m_flags & M_EXT))) { 2236 ifp->if_ierrors++; 2237 m_freem(m); 2238 return; 2239 } 2240 } 2241 /* finalize mbuf */ 2242 memcpy(mtod(m, caddr_t), wh, len); 2243 m->m_pkthdr.len = m->m_len = len; 2244 2245 ant = run_maxrssi_chain(sc, rxwi); 2246 rssi = rxwi->rssi[ant]; 2247 2248 #if NBPFILTER > 0 2249 if (__predict_false(sc->sc_drvbpf != NULL)) { 2250 struct run_rx_radiotap_header *tap = &sc->sc_rxtap; 2251 struct mbuf mb; 2252 2253 tap->wr_flags = 0; 2254 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq); 2255 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags); 2256 tap->wr_antsignal = rssi; 2257 tap->wr_antenna = ant; 2258 tap->wr_dbm_antsignal = run_rssi2dbm(sc, rssi, ant); 2259 tap->wr_rate = 2; /* in case it can't be found below */ 2260 phy = letoh16(rxwi->phy); 2261 switch (phy & RT2860_PHY_MODE) { 2262 case RT2860_PHY_CCK: 2263 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 2264 case 0: tap->wr_rate = 2; break; 2265 case 1: tap->wr_rate = 4; break; 2266 case 2: tap->wr_rate = 11; break; 2267 case 3: tap->wr_rate = 22; break; 2268 } 2269 if (phy & RT2860_PHY_SHPRE) 2270 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2271 break; 2272 case RT2860_PHY_OFDM: 2273 switch (phy & RT2860_PHY_MCS) { 2274 case 0: tap->wr_rate = 12; break; 2275 case 1: tap->wr_rate = 18; break; 2276 case 2: tap->wr_rate = 24; break; 2277 case 3: tap->wr_rate = 36; break; 2278 case 4: tap->wr_rate = 48; break; 2279 case 5: tap->wr_rate = 72; break; 2280 case 6: tap->wr_rate = 96; break; 2281 case 7: tap->wr_rate = 108; break; 2282 } 2283 break; 2284 } 2285 mb.m_data = (caddr_t)tap; 2286 mb.m_len = sc->sc_rxtap_len; 2287 mb.m_next = m; 2288 mb.m_nextpkt = NULL; 2289 mb.m_type = 0; 2290 mb.m_flags = 0; 2291 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN); 2292 } 2293 #endif 2294 2295 s = splnet(); 2296 ni = ieee80211_find_rxnode(ic, wh); 2297 rxi.rxi_rssi = rssi; 2298 rxi.rxi_tstamp = 0; /* unused */ 2299 ieee80211_inputm(ifp, m, ni, &rxi, ml); 2300 2301 /* node is no longer needed */ 2302 ieee80211_release_node(ic, ni); 2303 splx(s); 2304 } 2305 2306 void 2307 run_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2308 { 2309 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 2310 struct run_rx_data *data = priv; 2311 struct run_softc *sc = data->sc; 2312 uint8_t *buf; 2313 uint32_t dmalen; 2314 int xferlen; 2315 uint16_t rxwisize; 2316 2317 rxwisize = sizeof(struct rt2860_rxwi); 2318 if (sc->mac_ver == 0x5592) 2319 rxwisize += sizeof(uint64_t); 2320 else if (sc->mac_ver == 0x3593) 2321 rxwisize += sizeof(uint32_t); 2322 2323 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2324 DPRINTF(("RX status=%d\n", status)); 2325 if (status == USBD_STALLED) 2326 usbd_clear_endpoint_stall_async(sc->rxq.pipeh); 2327 if (status != USBD_CANCELLED) 2328 goto skip; 2329 return; 2330 } 2331 usbd_get_xfer_status(xfer, NULL, NULL, &xferlen, NULL); 2332 2333 if (__predict_false(xferlen < sizeof (uint32_t) + rxwisize + 2334 sizeof(struct rt2870_rxd))) { 2335 DPRINTF(("xfer too short %d\n", xferlen)); 2336 goto skip; 2337 } 2338 2339 /* HW can aggregate multiple 802.11 frames in a single USB xfer */ 2340 buf = data->buf; 2341 while (xferlen > 8) { 2342 dmalen = letoh32(*(uint32_t *)buf) & 0xffff; 2343 2344 if (__predict_false(dmalen == 0 || (dmalen & 3) != 0)) { 2345 DPRINTF(("bad DMA length %u\n", dmalen)); 2346 break; 2347 } 2348 if (__predict_false(dmalen + 8 > xferlen)) { 2349 DPRINTF(("bad DMA length %u > %d\n", 2350 dmalen + 8, xferlen)); 2351 break; 2352 } 2353 run_rx_frame(sc, buf + sizeof (uint32_t), dmalen, &ml); 2354 buf += dmalen + 8; 2355 xferlen -= dmalen + 8; 2356 } 2357 if_input(&sc->sc_ic.ic_if, &ml); 2358 2359 skip: /* setup a new transfer */ 2360 usbd_setup_xfer(xfer, sc->rxq.pipeh, data, data->buf, RUN_MAX_RXSZ, 2361 USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, run_rxeof); 2362 (void)usbd_transfer(data->xfer); 2363 } 2364 2365 void 2366 run_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) 2367 { 2368 struct run_tx_data *data = priv; 2369 struct run_softc *sc = data->sc; 2370 struct run_tx_ring *txq = &sc->txq[data->qid]; 2371 struct ifnet *ifp = &sc->sc_ic.ic_if; 2372 int s; 2373 2374 s = splnet(); 2375 txq->queued--; 2376 sc->qfullmsk &= ~(1 << data->qid); 2377 2378 if (__predict_false(status != USBD_NORMAL_COMPLETION)) { 2379 DPRINTF(("TX status=%d\n", status)); 2380 if (status == USBD_STALLED) 2381 usbd_clear_endpoint_stall_async(txq->pipeh); 2382 ifp->if_oerrors++; 2383 splx(s); 2384 return; 2385 } 2386 2387 sc->sc_tx_timer = 0; 2388 ifq_clr_oactive(&ifp->if_snd); 2389 run_start(ifp); 2390 splx(s); 2391 } 2392 2393 int 2394 run_tx(struct run_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 2395 { 2396 struct ieee80211com *ic = &sc->sc_ic; 2397 struct run_node *rn = (void *)ni; 2398 struct ieee80211_frame *wh; 2399 struct run_tx_ring *ring; 2400 struct run_tx_data *data; 2401 struct rt2870_txd *txd; 2402 struct rt2860_txwi *txwi; 2403 uint16_t qos, dur; 2404 uint16_t txwisize; 2405 uint8_t type, mcs, tid, qid; 2406 int error, hasqos, ridx, ctl_ridx, xferlen; 2407 2408 wh = mtod(m, struct ieee80211_frame *); 2409 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2410 2411 if ((hasqos = ieee80211_has_qos(wh))) { 2412 qos = ieee80211_get_qos(wh); 2413 tid = qos & IEEE80211_QOS_TID; 2414 qid = ieee80211_up_to_ac(ic, tid); 2415 } else { 2416 qos = 0; 2417 tid = 0; 2418 qid = EDCA_AC_BE; 2419 } 2420 ring = &sc->txq[qid]; 2421 data = &ring->data[ring->cur]; 2422 2423 /* pickup a rate index */ 2424 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 2425 type != IEEE80211_FC0_TYPE_DATA) { 2426 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ? 2427 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 2428 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2429 } else if (ic->ic_fixed_rate != -1) { 2430 ridx = sc->fixed_ridx; 2431 ctl_ridx = rt2860_rates[ridx].ctl_ridx; 2432 } else { 2433 ridx = rn->ridx[ni->ni_txrate]; 2434 ctl_ridx = rn->ctl_ridx[ni->ni_txrate]; 2435 } 2436 2437 /* get MCS code from rate index */ 2438 mcs = rt2860_rates[ridx].mcs; 2439 2440 txwisize = sizeof(struct rt2860_txwi); 2441 if (sc->mac_ver == 0x5592) 2442 txwisize += sizeof(uint32_t); 2443 xferlen = txwisize + m->m_pkthdr.len; 2444 2445 /* roundup to 32-bit alignment */ 2446 xferlen = (xferlen + 3) & ~3; 2447 2448 txd = (struct rt2870_txd *)data->buf; 2449 txd->flags = RT2860_TX_QSEL_EDCA; 2450 txd->len = htole16(xferlen); 2451 2452 /* setup TX Wireless Information */ 2453 txwi = (struct rt2860_txwi *)(txd + 1); 2454 txwi->flags = 0; 2455 txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ; 2456 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ? 2457 RUN_AID2WCID(ni->ni_associd) : 0xff; 2458 txwi->len = htole16(m->m_pkthdr.len); 2459 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 2460 txwi->phy = htole16(RT2860_PHY_CCK); 2461 if (ridx != RT2860_RIDX_CCK1 && 2462 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 2463 mcs |= RT2860_PHY_SHPRE; 2464 } else 2465 txwi->phy = htole16(RT2860_PHY_OFDM); 2466 txwi->phy |= htole16(mcs); 2467 2468 txwi->txop = RT2860_TX_TXOP_BACKOFF; 2469 2470 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 2471 (!hasqos || (qos & IEEE80211_QOS_ACK_POLICY_MASK) != 2472 IEEE80211_QOS_ACK_POLICY_NOACK)) { 2473 txwi->xflags |= RT2860_TX_ACK; 2474 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2475 dur = rt2860_rates[ctl_ridx].sp_ack_dur; 2476 else 2477 dur = rt2860_rates[ctl_ridx].lp_ack_dur; 2478 *(uint16_t *)wh->i_dur = htole16(dur); 2479 } 2480 2481 #if NBPFILTER > 0 2482 if (__predict_false(sc->sc_drvbpf != NULL)) { 2483 struct run_tx_radiotap_header *tap = &sc->sc_txtap; 2484 struct mbuf mb; 2485 2486 tap->wt_flags = 0; 2487 tap->wt_rate = rt2860_rates[ridx].rate; 2488 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq); 2489 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags); 2490 tap->wt_hwqueue = qid; 2491 if (mcs & RT2860_PHY_SHPRE) 2492 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2493 2494 mb.m_data = (caddr_t)tap; 2495 mb.m_len = sc->sc_txtap_len; 2496 mb.m_next = m; 2497 mb.m_nextpkt = NULL; 2498 mb.m_type = 0; 2499 mb.m_flags = 0; 2500 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT); 2501 } 2502 #endif 2503 2504 m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)txwi + txwisize); 2505 m_freem(m); 2506 2507 xferlen += sizeof (*txd) + 4; 2508 2509 usbd_setup_xfer(data->xfer, ring->pipeh, data, data->buf, xferlen, 2510 USBD_FORCE_SHORT_XFER | USBD_NO_COPY, RUN_TX_TIMEOUT, run_txeof); 2511 error = usbd_transfer(data->xfer); 2512 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)) 2513 return error; 2514 2515 ieee80211_release_node(ic, ni); 2516 2517 ring->cur = (ring->cur + 1) % RUN_TX_RING_COUNT; 2518 if (++ring->queued >= RUN_TX_RING_COUNT) 2519 sc->qfullmsk |= 1 << qid; 2520 2521 return 0; 2522 } 2523 2524 void 2525 run_start(struct ifnet *ifp) 2526 { 2527 struct run_softc *sc = ifp->if_softc; 2528 struct ieee80211com *ic = &sc->sc_ic; 2529 struct ieee80211_node *ni; 2530 struct mbuf *m; 2531 2532 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 2533 return; 2534 2535 for (;;) { 2536 if (sc->qfullmsk != 0) { 2537 ifq_set_oactive(&ifp->if_snd); 2538 break; 2539 } 2540 /* send pending management frames first */ 2541 m = mq_dequeue(&ic->ic_mgtq); 2542 if (m != NULL) { 2543 ni = m->m_pkthdr.ph_cookie; 2544 goto sendit; 2545 } 2546 if (ic->ic_state != IEEE80211_S_RUN) 2547 break; 2548 2549 /* encapsulate and send data frames */ 2550 IFQ_DEQUEUE(&ifp->if_snd, m); 2551 if (m == NULL) 2552 break; 2553 #if NBPFILTER > 0 2554 if (ifp->if_bpf != NULL) 2555 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 2556 #endif 2557 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 2558 continue; 2559 sendit: 2560 #if NBPFILTER > 0 2561 if (ic->ic_rawbpf != NULL) 2562 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 2563 #endif 2564 if (run_tx(sc, m, ni) != 0) { 2565 ieee80211_release_node(ic, ni); 2566 ifp->if_oerrors++; 2567 continue; 2568 } 2569 2570 sc->sc_tx_timer = 5; 2571 ifp->if_timer = 1; 2572 } 2573 } 2574 2575 void 2576 run_watchdog(struct ifnet *ifp) 2577 { 2578 struct run_softc *sc = ifp->if_softc; 2579 2580 ifp->if_timer = 0; 2581 2582 if (sc->sc_tx_timer > 0) { 2583 if (--sc->sc_tx_timer == 0) { 2584 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 2585 /* run_init(ifp); XXX needs a process context! */ 2586 ifp->if_oerrors++; 2587 return; 2588 } 2589 ifp->if_timer = 1; 2590 } 2591 2592 ieee80211_watchdog(ifp); 2593 } 2594 2595 int 2596 run_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2597 { 2598 struct run_softc *sc = ifp->if_softc; 2599 struct ieee80211com *ic = &sc->sc_ic; 2600 int s, error = 0; 2601 2602 if (usbd_is_dying(sc->sc_udev)) 2603 return ENXIO; 2604 2605 usbd_ref_incr(sc->sc_udev); 2606 2607 s = splnet(); 2608 2609 switch (cmd) { 2610 case SIOCSIFADDR: 2611 ifp->if_flags |= IFF_UP; 2612 /* FALLTHROUGH */ 2613 case SIOCSIFFLAGS: 2614 if (ifp->if_flags & IFF_UP) { 2615 if (!(ifp->if_flags & IFF_RUNNING)) 2616 run_init(ifp); 2617 } else { 2618 if (ifp->if_flags & IFF_RUNNING) 2619 run_stop(ifp, 1); 2620 } 2621 break; 2622 2623 case SIOCS80211CHANNEL: 2624 /* 2625 * This allows for fast channel switching in monitor mode 2626 * (used by kismet). 2627 */ 2628 error = ieee80211_ioctl(ifp, cmd, data); 2629 if (error == ENETRESET && 2630 ic->ic_opmode == IEEE80211_M_MONITOR) { 2631 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2632 (IFF_UP | IFF_RUNNING)) 2633 run_set_chan(sc, ic->ic_ibss_chan); 2634 error = 0; 2635 } 2636 break; 2637 2638 default: 2639 error = ieee80211_ioctl(ifp, cmd, data); 2640 } 2641 2642 if (error == ENETRESET) { 2643 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 2644 (IFF_UP | IFF_RUNNING)) { 2645 run_stop(ifp, 0); 2646 run_init(ifp); 2647 } 2648 error = 0; 2649 } 2650 2651 splx(s); 2652 2653 usbd_ref_decr(sc->sc_udev); 2654 2655 return error; 2656 } 2657 2658 void 2659 run_iq_calib(struct run_softc *sc, u_int chan) 2660 { 2661 uint16_t val; 2662 2663 /* Tx0 IQ gain. */ 2664 run_bbp_write(sc, 158, 0x2c); 2665 if (chan <= 14) 2666 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ, &val); 2667 else if (chan <= 64) { 2668 run_efuse_read(sc, 2669 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ, &val); 2670 } else if (chan <= 138) { 2671 run_efuse_read(sc, 2672 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ, &val); 2673 } else if (chan <= 165) { 2674 run_efuse_read(sc, 2675 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ, 2676 &val); 2677 } else 2678 val = 0; 2679 run_bbp_write(sc, 159, val); 2680 2681 /* Tx0 IQ phase. */ 2682 run_bbp_write(sc, 158, 0x2d); 2683 if (chan <= 14) { 2684 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ, &val); 2685 } else if (chan <= 64) { 2686 run_efuse_read(sc, 2687 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ, &val); 2688 } else if (chan <= 138) { 2689 run_efuse_read(sc, 2690 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ, &val); 2691 } else if (chan <= 165) { 2692 run_efuse_read(sc, 2693 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ, &val); 2694 } else 2695 val = 0; 2696 run_bbp_write(sc, 159, val); 2697 2698 /* Tx1 IQ gain. */ 2699 run_bbp_write(sc, 158, 0x4a); 2700 if (chan <= 14) { 2701 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ, &val); 2702 } else if (chan <= 64) { 2703 run_efuse_read(sc, 2704 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ, &val); 2705 } else if (chan <= 138) { 2706 run_efuse_read(sc, 2707 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ, &val); 2708 } else if (chan <= 165) { 2709 run_efuse_read(sc, 2710 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ, &val); 2711 } else 2712 val = 0; 2713 run_bbp_write(sc, 159, val); 2714 2715 /* Tx1 IQ phase. */ 2716 run_bbp_write(sc, 158, 0x4b); 2717 if (chan <= 14) { 2718 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ, &val); 2719 } else if (chan <= 64) { 2720 run_efuse_read(sc, 2721 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ, &val); 2722 } else if (chan <= 138) { 2723 run_efuse_read(sc, 2724 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ, &val); 2725 } else if (chan <= 165) { 2726 run_efuse_read(sc, 2727 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ, &val); 2728 } else 2729 val = 0; 2730 run_bbp_write(sc, 159, val); 2731 2732 /* RF IQ compensation control. */ 2733 run_bbp_write(sc, 158, 0x04); 2734 run_efuse_read(sc, RT5390_EEPROM_RF_IQ_COMPENSATION_CTL, &val); 2735 run_bbp_write(sc, 159, val); 2736 2737 /* RF IQ imbalance compensation control. */ 2738 run_bbp_write(sc, 158, 0x03); 2739 run_efuse_read(sc, 2740 RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL, &val); 2741 run_bbp_write(sc, 159, val); 2742 } 2743 2744 void 2745 run_select_chan_group(struct run_softc *sc, int group) 2746 { 2747 uint32_t tmp; 2748 uint8_t agc; 2749 2750 run_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2751 run_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2752 run_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2753 if (sc->mac_ver < 0x3572) 2754 run_bbp_write(sc, 86, 0x00); 2755 2756 if (sc->mac_ver == 0x3593) { 2757 run_bbp_write(sc, 77, 0x98); 2758 run_bbp_write(sc, 83, (group == 0) ? 0x8a : 0x9a); 2759 } 2760 2761 if (group == 0) { 2762 if (sc->ext_2ghz_lna) { 2763 if (sc->mac_ver >= 0x5390) 2764 run_bbp_write(sc, 75, 0x52); 2765 else { 2766 run_bbp_write(sc, 82, 0x62); 2767 run_bbp_write(sc, 75, 0x46); 2768 } 2769 } else { 2770 if (sc->mac_ver == 0x5592) { 2771 run_bbp_write(sc, 79, 0x1c); 2772 run_bbp_write(sc, 80, 0x0e); 2773 run_bbp_write(sc, 81, 0x3a); 2774 run_bbp_write(sc, 82, 0x62); 2775 2776 run_bbp_write(sc, 195, 0x80); 2777 run_bbp_write(sc, 196, 0xe0); 2778 run_bbp_write(sc, 195, 0x81); 2779 run_bbp_write(sc, 196, 0x1f); 2780 run_bbp_write(sc, 195, 0x82); 2781 run_bbp_write(sc, 196, 0x38); 2782 run_bbp_write(sc, 195, 0x83); 2783 run_bbp_write(sc, 196, 0x32); 2784 run_bbp_write(sc, 195, 0x85); 2785 run_bbp_write(sc, 196, 0x28); 2786 run_bbp_write(sc, 195, 0x86); 2787 run_bbp_write(sc, 196, 0x19); 2788 } else if (sc->mac_ver >= 0x5390) 2789 run_bbp_write(sc, 75, 0x50); 2790 else { 2791 run_bbp_write(sc, 82, 2792 (sc->mac_ver == 0x3593) ? 0x62 : 0x84); 2793 run_bbp_write(sc, 75, 0x50); 2794 } 2795 } 2796 } else { 2797 if (sc->mac_ver == 0x5592) { 2798 run_bbp_write(sc, 79, 0x18); 2799 run_bbp_write(sc, 80, 0x08); 2800 run_bbp_write(sc, 81, 0x38); 2801 run_bbp_write(sc, 82, 0x92); 2802 2803 run_bbp_write(sc, 195, 0x80); 2804 run_bbp_write(sc, 196, 0xf0); 2805 run_bbp_write(sc, 195, 0x81); 2806 run_bbp_write(sc, 196, 0x1e); 2807 run_bbp_write(sc, 195, 0x82); 2808 run_bbp_write(sc, 196, 0x28); 2809 run_bbp_write(sc, 195, 0x83); 2810 run_bbp_write(sc, 196, 0x20); 2811 run_bbp_write(sc, 195, 0x85); 2812 run_bbp_write(sc, 196, 0x7f); 2813 run_bbp_write(sc, 195, 0x86); 2814 run_bbp_write(sc, 196, 0x7f); 2815 } else if (sc->mac_ver == 0x3572) 2816 run_bbp_write(sc, 82, 0x94); 2817 else 2818 run_bbp_write(sc, 82, 2819 (sc->mac_ver == 0x3593) ? 0x82 : 0xf2); 2820 if (sc->ext_5ghz_lna) 2821 run_bbp_write(sc, 75, 0x46); 2822 else 2823 run_bbp_write(sc, 75, 0x50); 2824 } 2825 2826 run_read(sc, RT2860_TX_BAND_CFG, &tmp); 2827 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2828 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2829 run_write(sc, RT2860_TX_BAND_CFG, tmp); 2830 2831 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2832 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2833 if (sc->mac_ver == 0x3593) 2834 tmp |= 1 << 29 | 1 << 28; 2835 if (sc->nrxchains > 1) 2836 tmp |= RT2860_LNA_PE1_EN; 2837 if (group == 0) { /* 2GHz */ 2838 tmp |= RT2860_PA_PE_G0_EN; 2839 if (sc->ntxchains > 1) 2840 tmp |= RT2860_PA_PE_G1_EN; 2841 if (sc->mac_ver == 0x3593) { 2842 if (sc->ntxchains > 2) 2843 tmp |= 1 << 25; 2844 } 2845 } else { /* 5GHz */ 2846 tmp |= RT2860_PA_PE_A0_EN; 2847 if (sc->ntxchains > 1) 2848 tmp |= RT2860_PA_PE_A1_EN; 2849 } 2850 if (sc->mac_ver == 0x3572) { 2851 run_rt3070_rf_write(sc, 8, 0x00); 2852 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2853 run_rt3070_rf_write(sc, 8, 0x80); 2854 } else 2855 run_write(sc, RT2860_TX_PIN_CFG, tmp); 2856 2857 if (sc->mac_ver == 0x5592) { 2858 run_bbp_write(sc, 195, 0x8d); 2859 run_bbp_write(sc, 196, 0x1a); 2860 } 2861 2862 if (sc->mac_ver == 0x3593) { 2863 run_read(sc, RT2860_GPIO_CTRL, &tmp); 2864 tmp &= ~0x01010000; 2865 if (group == 0) 2866 tmp |= 0x00010000; 2867 tmp = (tmp & ~0x00009090) | 0x00000090; 2868 run_write(sc, RT2860_GPIO_CTRL, tmp); 2869 } 2870 2871 /* set initial AGC value */ 2872 if (group == 0) { /* 2GHz band */ 2873 if (sc->mac_ver >= 0x3070) 2874 agc = 0x1c + sc->lna[0] * 2; 2875 else 2876 agc = 0x2e + sc->lna[0]; 2877 } else { /* 5GHz band */ 2878 if (sc->mac_ver == 0x5592) 2879 agc = 0x24 + sc->lna[group] * 2; 2880 else if (sc->mac_ver == 0x3572 || sc->mac_ver == 0x3593) 2881 agc = 0x22 + (sc->lna[group] * 5) / 3; 2882 else 2883 agc = 0x32 + (sc->lna[group] * 5) / 3; 2884 } 2885 run_set_agc(sc, agc); 2886 } 2887 2888 void 2889 run_rt2870_set_chan(struct run_softc *sc, u_int chan) 2890 { 2891 const struct rfprog *rfprog = rt2860_rf2850; 2892 uint32_t r2, r3, r4; 2893 int8_t txpow1, txpow2; 2894 int i; 2895 2896 /* find the settings for this channel (we know it exists) */ 2897 for (i = 0; rfprog[i].chan != chan; i++); 2898 2899 r2 = rfprog[i].r2; 2900 if (sc->ntxchains == 1) 2901 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2902 if (sc->nrxchains == 1) 2903 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2904 else if (sc->nrxchains == 2) 2905 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2906 2907 /* use Tx power values from EEPROM */ 2908 txpow1 = sc->txpow1[i]; 2909 txpow2 = sc->txpow2[i]; 2910 if (chan > 14) { 2911 if (txpow1 >= 0) 2912 txpow1 = txpow1 << 1 | 1; 2913 else 2914 txpow1 = (7 + txpow1) << 1; 2915 if (txpow2 >= 0) 2916 txpow2 = txpow2 << 1 | 1; 2917 else 2918 txpow2 = (7 + txpow2) << 1; 2919 } 2920 r3 = rfprog[i].r3 | txpow1 << 7; 2921 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2922 2923 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2924 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2925 run_rt2870_rf_write(sc, RT2860_RF3, r3); 2926 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2927 2928 DELAY(200); 2929 2930 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2931 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2932 run_rt2870_rf_write(sc, RT2860_RF3, r3 | 1); 2933 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2934 2935 DELAY(200); 2936 2937 run_rt2870_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2938 run_rt2870_rf_write(sc, RT2860_RF2, r2); 2939 run_rt2870_rf_write(sc, RT2860_RF3, r3); 2940 run_rt2870_rf_write(sc, RT2860_RF4, r4); 2941 } 2942 2943 void 2944 run_rt3070_set_chan(struct run_softc *sc, u_int chan) 2945 { 2946 int8_t txpow1, txpow2; 2947 uint8_t rf; 2948 int i; 2949 2950 /* find the settings for this channel (we know it exists) */ 2951 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2952 2953 /* use Tx power values from EEPROM */ 2954 txpow1 = sc->txpow1[i]; 2955 txpow2 = sc->txpow2[i]; 2956 2957 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 2958 2959 /* RT3370/RT3390: RF R3 [7:4] is not reserved bits. */ 2960 run_rt3070_rf_read(sc, 3, &rf); 2961 rf = (rf & ~0x0f) | rt3070_freqs[i].k; 2962 run_rt3070_rf_write(sc, 3, rf); 2963 2964 run_rt3070_rf_read(sc, 6, &rf); 2965 rf = (rf & ~0x03) | rt3070_freqs[i].r; 2966 run_rt3070_rf_write(sc, 6, rf); 2967 2968 /* set Tx0 power */ 2969 run_rt3070_rf_read(sc, 12, &rf); 2970 rf = (rf & ~0x1f) | txpow1; 2971 run_rt3070_rf_write(sc, 12, rf); 2972 2973 /* set Tx1 power */ 2974 run_rt3070_rf_read(sc, 13, &rf); 2975 rf = (rf & ~0x1f) | txpow2; 2976 run_rt3070_rf_write(sc, 13, rf); 2977 2978 run_rt3070_rf_read(sc, 1, &rf); 2979 rf &= ~0xfc; 2980 if (sc->ntxchains == 1) 2981 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 2982 else if (sc->ntxchains == 2) 2983 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 2984 if (sc->nrxchains == 1) 2985 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2986 else if (sc->nrxchains == 2) 2987 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 2988 run_rt3070_rf_write(sc, 1, rf); 2989 2990 /* set RF offset */ 2991 run_rt3070_rf_read(sc, 23, &rf); 2992 rf = (rf & ~0x7f) | sc->freq; 2993 run_rt3070_rf_write(sc, 23, rf); 2994 2995 /* program RF filter */ 2996 run_rt3070_rf_read(sc, 24, &rf); /* Tx */ 2997 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2998 run_rt3070_rf_write(sc, 24, rf); 2999 run_rt3070_rf_read(sc, 31, &rf); /* Rx */ 3000 rf = (rf & ~0x3f) | sc->rf24_20mhz; 3001 run_rt3070_rf_write(sc, 31, rf); 3002 3003 /* enable RF tuning */ 3004 run_rt3070_rf_read(sc, 7, &rf); 3005 run_rt3070_rf_write(sc, 7, rf | 0x01); 3006 } 3007 3008 void 3009 run_rt3572_set_chan(struct run_softc *sc, u_int chan) 3010 { 3011 int8_t txpow1, txpow2; 3012 uint32_t tmp; 3013 uint8_t rf; 3014 int i; 3015 3016 /* find the settings for this channel (we know it exists) */ 3017 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3018 3019 /* use Tx power values from EEPROM */ 3020 txpow1 = sc->txpow1[i]; 3021 txpow2 = sc->txpow2[i]; 3022 3023 if (chan <= 14) { 3024 run_bbp_write(sc, 25, sc->bbp25); 3025 run_bbp_write(sc, 26, sc->bbp26); 3026 } else { 3027 /* enable IQ phase correction */ 3028 run_bbp_write(sc, 25, 0x09); 3029 run_bbp_write(sc, 26, 0xff); 3030 } 3031 3032 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n); 3033 run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k); 3034 run_rt3070_rf_read(sc, 6, &rf); 3035 rf = (rf & ~0x0f) | rt3070_freqs[i].r; 3036 rf |= (chan <= 14) ? 0x08 : 0x04; 3037 run_rt3070_rf_write(sc, 6, rf); 3038 3039 /* set PLL mode */ 3040 run_rt3070_rf_read(sc, 5, &rf); 3041 rf &= ~(0x08 | 0x04); 3042 rf |= (chan <= 14) ? 0x04 : 0x08; 3043 run_rt3070_rf_write(sc, 5, rf); 3044 3045 /* set Tx power for chain 0 */ 3046 if (chan <= 14) 3047 rf = 0x60 | txpow1; 3048 else 3049 rf = 0xe0 | (txpow1 & 0xc) << 1 | (txpow1 & 0x3); 3050 run_rt3070_rf_write(sc, 12, rf); 3051 3052 /* set Tx power for chain 1 */ 3053 if (chan <= 14) 3054 rf = 0x60 | txpow2; 3055 else 3056 rf = 0xe0 | (txpow2 & 0xc) << 1 | (txpow2 & 0x3); 3057 run_rt3070_rf_write(sc, 13, rf); 3058 3059 /* set Tx/Rx streams */ 3060 run_rt3070_rf_read(sc, 1, &rf); 3061 rf &= ~0xfc; 3062 if (sc->ntxchains == 1) 3063 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */ 3064 else if (sc->ntxchains == 2) 3065 rf |= 1 << 7; /* 2T: disable Tx chain 3 */ 3066 if (sc->nrxchains == 1) 3067 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 3068 else if (sc->nrxchains == 2) 3069 rf |= 1 << 6; /* 2R: disable Rx chain 3 */ 3070 run_rt3070_rf_write(sc, 1, rf); 3071 3072 /* set RF offset */ 3073 run_rt3070_rf_read(sc, 23, &rf); 3074 rf = (rf & ~0x7f) | sc->freq; 3075 run_rt3070_rf_write(sc, 23, rf); 3076 3077 /* program RF filter */ 3078 rf = sc->rf24_20mhz; 3079 run_rt3070_rf_write(sc, 24, rf); /* Tx */ 3080 run_rt3070_rf_write(sc, 31, rf); /* Rx */ 3081 3082 /* enable RF tuning */ 3083 run_rt3070_rf_read(sc, 7, &rf); 3084 rf = (chan <= 14) ? 0xd8 : ((rf & ~0xc8) | 0x14); 3085 run_rt3070_rf_write(sc, 7, rf); 3086 3087 /* TSSI */ 3088 rf = (chan <= 14) ? 0xc3 : 0xc0; 3089 run_rt3070_rf_write(sc, 9, rf); 3090 3091 /* set loop filter 1 */ 3092 run_rt3070_rf_write(sc, 10, 0xf1); 3093 /* set loop filter 2 */ 3094 run_rt3070_rf_write(sc, 11, (chan <= 14) ? 0xb9 : 0x00); 3095 3096 /* set tx_mx2_ic */ 3097 run_rt3070_rf_write(sc, 15, (chan <= 14) ? 0x53 : 0x43); 3098 /* set tx_mx1_ic */ 3099 if (chan <= 14) 3100 rf = 0x48 | sc->txmixgain_2ghz; 3101 else 3102 rf = 0x78 | sc->txmixgain_5ghz; 3103 run_rt3070_rf_write(sc, 16, rf); 3104 3105 /* set tx_lo1 */ 3106 run_rt3070_rf_write(sc, 17, 0x23); 3107 /* set tx_lo2 */ 3108 if (chan <= 14) 3109 rf = 0x93; 3110 else if (chan <= 64) 3111 rf = 0xb7; 3112 else if (chan <= 128) 3113 rf = 0x74; 3114 else 3115 rf = 0x72; 3116 run_rt3070_rf_write(sc, 19, rf); 3117 3118 /* set rx_lo1 */ 3119 if (chan <= 14) 3120 rf = 0xb3; 3121 else if (chan <= 64) 3122 rf = 0xf6; 3123 else if (chan <= 128) 3124 rf = 0xf4; 3125 else 3126 rf = 0xf3; 3127 run_rt3070_rf_write(sc, 20, rf); 3128 3129 /* set pfd_delay */ 3130 if (chan <= 14) 3131 rf = 0x15; 3132 else if (chan <= 64) 3133 rf = 0x3d; 3134 else 3135 rf = 0x01; 3136 run_rt3070_rf_write(sc, 25, rf); 3137 3138 /* set rx_lo2 */ 3139 run_rt3070_rf_write(sc, 26, (chan <= 14) ? 0x85 : 0x87); 3140 /* set ldo_rf_vc */ 3141 run_rt3070_rf_write(sc, 27, (chan <= 14) ? 0x00 : 0x01); 3142 /* set drv_cc */ 3143 run_rt3070_rf_write(sc, 29, (chan <= 14) ? 0x9b : 0x9f); 3144 3145 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3146 tmp &= ~0x8080; 3147 if (chan <= 14) 3148 tmp |= 0x80; 3149 run_write(sc, RT2860_GPIO_CTRL, tmp); 3150 3151 /* enable RF tuning */ 3152 run_rt3070_rf_read(sc, 7, &rf); 3153 run_rt3070_rf_write(sc, 7, rf | 0x01); 3154 3155 DELAY(2000); 3156 } 3157 3158 void 3159 run_rt3593_set_chan(struct run_softc *sc, u_int chan) 3160 { 3161 int8_t txpow1, txpow2, txpow3; 3162 uint8_t h20mhz, rf; 3163 int i; 3164 3165 /* find the settings for this channel (we know it exists) */ 3166 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3167 3168 /* use Tx power values from EEPROM */ 3169 txpow1 = sc->txpow1[i]; 3170 txpow2 = sc->txpow2[i]; 3171 txpow3 = (sc->ntxchains == 3) ? sc->txpow3[i] : 0; 3172 3173 if (chan <= 14) { 3174 run_bbp_write(sc, 25, sc->bbp25); 3175 run_bbp_write(sc, 26, sc->bbp26); 3176 } else { 3177 /* Enable IQ phase correction. */ 3178 run_bbp_write(sc, 25, 0x09); 3179 run_bbp_write(sc, 26, 0xff); 3180 } 3181 3182 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3183 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3184 run_rt3070_rf_read(sc, 11, &rf); 3185 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3186 run_rt3070_rf_write(sc, 11, rf); 3187 3188 /* Set pll_idoh. */ 3189 run_rt3070_rf_read(sc, 11, &rf); 3190 rf &= ~0x4c; 3191 rf |= (chan <= 14) ? 0x44 : 0x48; 3192 run_rt3070_rf_write(sc, 11, rf); 3193 3194 if (chan <= 14) 3195 rf = txpow1 & 0x1f; 3196 else 3197 rf = 0x40 | ((txpow1 & 0x18) << 1) | (txpow1 & 0x07); 3198 run_rt3070_rf_write(sc, 53, rf); 3199 3200 if (chan <= 14) 3201 rf = txpow2 & 0x1f; 3202 else 3203 rf = 0x40 | ((txpow2 & 0x18) << 1) | (txpow2 & 0x07); 3204 run_rt3070_rf_write(sc, 55, rf); 3205 3206 if (chan <= 14) 3207 rf = txpow3 & 0x1f; 3208 else 3209 rf = 0x40 | ((txpow3 & 0x18) << 1) | (txpow3 & 0x07); 3210 run_rt3070_rf_write(sc, 54, rf); 3211 3212 rf = RT3070_RF_BLOCK | RT3070_PLL_PD; 3213 if (sc->ntxchains == 3) 3214 rf |= RT3070_TX0_PD | RT3070_TX1_PD | RT3070_TX2_PD; 3215 else 3216 rf |= RT3070_TX0_PD | RT3070_TX1_PD; 3217 rf |= RT3070_RX0_PD | RT3070_RX1_PD | RT3070_RX2_PD; 3218 run_rt3070_rf_write(sc, 1, rf); 3219 3220 run_adjust_freq_offset(sc); 3221 3222 run_rt3070_rf_write(sc, 31, (chan <= 14) ? 0xa0 : 0x80); 3223 3224 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 3225 run_rt3070_rf_read(sc, 30, &rf); 3226 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 3227 run_rt3070_rf_write(sc, 30, rf); 3228 3229 run_rt3070_rf_read(sc, 36, &rf); 3230 if (chan <= 14) 3231 rf |= 0x80; 3232 else 3233 rf &= ~0x80; 3234 run_rt3070_rf_write(sc, 36, rf); 3235 3236 /* Set vcolo_bs. */ 3237 run_rt3070_rf_write(sc, 34, (chan <= 14) ? 0x3c : 0x20); 3238 /* Set pfd_delay. */ 3239 run_rt3070_rf_write(sc, 12, (chan <= 14) ? 0x1a : 0x12); 3240 3241 /* Set vco bias current control. */ 3242 run_rt3070_rf_read(sc, 6, &rf); 3243 rf &= ~0xc0; 3244 if (chan <= 14) 3245 rf |= 0x40; 3246 else if (chan <= 128) 3247 rf |= 0x80; 3248 else 3249 rf |= 0x40; 3250 run_rt3070_rf_write(sc, 6, rf); 3251 3252 run_rt3070_rf_read(sc, 30, &rf); 3253 rf = (rf & ~0x18) | 0x10; 3254 run_rt3070_rf_write(sc, 30, rf); 3255 3256 run_rt3070_rf_write(sc, 10, (chan <= 14) ? 0xd3 : 0xd8); 3257 run_rt3070_rf_write(sc, 13, (chan <= 14) ? 0x12 : 0x23); 3258 3259 run_rt3070_rf_read(sc, 51, &rf); 3260 rf = (rf & ~0x03) | 0x01; 3261 run_rt3070_rf_write(sc, 51, rf); 3262 /* Set tx_mx1_cc. */ 3263 run_rt3070_rf_read(sc, 51, &rf); 3264 rf &= ~0x1c; 3265 rf |= (chan <= 14) ? 0x14 : 0x10; 3266 run_rt3070_rf_write(sc, 51, rf); 3267 /* Set tx_mx1_ic. */ 3268 run_rt3070_rf_read(sc, 51, &rf); 3269 rf &= ~0xe0; 3270 rf |= (chan <= 14) ? 0x60 : 0x40; 3271 run_rt3070_rf_write(sc, 51, rf); 3272 /* Set tx_lo1_ic. */ 3273 run_rt3070_rf_read(sc, 49, &rf); 3274 rf &= ~0x1c; 3275 rf |= (chan <= 14) ? 0x0c : 0x08; 3276 run_rt3070_rf_write(sc, 49, rf); 3277 /* Set tx_lo1_en. */ 3278 run_rt3070_rf_read(sc, 50, &rf); 3279 run_rt3070_rf_write(sc, 50, rf & ~0x20); 3280 /* Set drv_cc. */ 3281 run_rt3070_rf_read(sc, 57, &rf); 3282 rf &= ~0xfc; 3283 rf |= (chan <= 14) ? 0x6c : 0x3c; 3284 run_rt3070_rf_write(sc, 57, rf); 3285 /* Set rx_mix1_ic, rxa_lnactr, lna_vc, lna_inbias_en and lna_en. */ 3286 run_rt3070_rf_write(sc, 44, (chan <= 14) ? 0x93 : 0x9b); 3287 /* Set drv_gnd_a, tx_vga_cc_a and tx_mx2_gain. */ 3288 run_rt3070_rf_write(sc, 52, (chan <= 14) ? 0x45 : 0x05); 3289 /* Enable VCO calibration. */ 3290 run_rt3070_rf_read(sc, 3, &rf); 3291 rf &= ~RT3593_VCOCAL; 3292 rf |= (chan <= 14) ? RT3593_VCOCAL : 0xbe; 3293 run_rt3070_rf_write(sc, 3, rf); 3294 3295 if (chan <= 14) 3296 rf = 0x23; 3297 else if (chan <= 64) 3298 rf = 0x36; 3299 else if (chan <= 128) 3300 rf = 0x32; 3301 else 3302 rf = 0x30; 3303 run_rt3070_rf_write(sc, 39, rf); 3304 if (chan <= 14) 3305 rf = 0xbb; 3306 else if (chan <= 64) 3307 rf = 0xeb; 3308 else if (chan <= 128) 3309 rf = 0xb3; 3310 else 3311 rf = 0x9b; 3312 run_rt3070_rf_write(sc, 45, rf); 3313 3314 /* Set FEQ/AEQ control. */ 3315 run_bbp_write(sc, 105, 0x34); 3316 } 3317 3318 void 3319 run_rt5390_set_chan(struct run_softc *sc, u_int chan) 3320 { 3321 int8_t txpow1, txpow2; 3322 uint8_t rf; 3323 int i; 3324 3325 /* find the settings for this channel (we know it exists) */ 3326 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 3327 3328 /* use Tx power values from EEPROM */ 3329 txpow1 = sc->txpow1[i]; 3330 txpow2 = sc->txpow2[i]; 3331 3332 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n); 3333 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f); 3334 run_rt3070_rf_read(sc, 11, &rf); 3335 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03); 3336 run_rt3070_rf_write(sc, 11, rf); 3337 3338 run_rt3070_rf_read(sc, 49, &rf); 3339 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3340 /* The valid range of the RF R49 is 0x00 to 0x27. */ 3341 if ((rf & 0x3f) > 0x27) 3342 rf = (rf & ~0x3f) | 0x27; 3343 run_rt3070_rf_write(sc, 49, rf); 3344 3345 if (sc->mac_ver == 0x5392) { 3346 run_rt3070_rf_read(sc, 50, &rf); 3347 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3348 /* The valid range of the RF R50 is 0x00 to 0x27. */ 3349 if ((rf & 0x3f) > 0x27) 3350 rf = (rf & ~0x3f) | 0x27; 3351 run_rt3070_rf_write(sc, 50, rf); 3352 } 3353 3354 run_rt3070_rf_read(sc, 1, &rf); 3355 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 3356 if (sc->mac_ver == 0x5392) 3357 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 3358 run_rt3070_rf_write(sc, 1, rf); 3359 3360 if (sc->mac_ver != 0x5392) { 3361 run_rt3070_rf_read(sc, 2, &rf); 3362 rf |= 0x80; 3363 run_rt3070_rf_write(sc, 2, rf); 3364 DELAY(10); 3365 rf &= 0x7f; 3366 run_rt3070_rf_write(sc, 2, rf); 3367 } 3368 3369 run_adjust_freq_offset(sc); 3370 3371 if (sc->mac_ver == 0x5392) { 3372 /* Fix for RT5392C. */ 3373 if (sc->mac_rev >= 0x0223) { 3374 if (chan <= 4) 3375 rf = 0x0f; 3376 else if (chan >= 5 && chan <= 7) 3377 rf = 0x0e; 3378 else 3379 rf = 0x0d; 3380 run_rt3070_rf_write(sc, 23, rf); 3381 3382 if (chan <= 4) 3383 rf = 0x0c; 3384 else if (chan == 5) 3385 rf = 0x0b; 3386 else if (chan >= 6 && chan <= 7) 3387 rf = 0x0a; 3388 else if (chan >= 8 && chan <= 10) 3389 rf = 0x09; 3390 else 3391 rf = 0x08; 3392 run_rt3070_rf_write(sc, 59, rf); 3393 } else { 3394 if (chan <= 11) 3395 rf = 0x0f; 3396 else 3397 rf = 0x0b; 3398 run_rt3070_rf_write(sc, 59, rf); 3399 } 3400 } else { 3401 /* Fix for RT5390F. */ 3402 if (sc->mac_rev >= 0x0502) { 3403 if (chan <= 11) 3404 rf = 0x43; 3405 else 3406 rf = 0x23; 3407 run_rt3070_rf_write(sc, 55, rf); 3408 3409 if (chan <= 11) 3410 rf = 0x0f; 3411 else if (chan == 12) 3412 rf = 0x0d; 3413 else 3414 rf = 0x0b; 3415 run_rt3070_rf_write(sc, 59, rf); 3416 } else { 3417 run_rt3070_rf_write(sc, 55, 0x44); 3418 run_rt3070_rf_write(sc, 59, 0x8f); 3419 } 3420 } 3421 3422 /* Enable VCO calibration. */ 3423 run_rt3070_rf_read(sc, 3, &rf); 3424 rf |= RT3593_VCOCAL; 3425 run_rt3070_rf_write(sc, 3, rf); 3426 } 3427 3428 void 3429 run_rt5592_set_chan(struct run_softc *sc, u_int chan) 3430 { 3431 const struct rt5592_freqs *freqs; 3432 uint32_t tmp; 3433 uint8_t reg, rf, txpow_bound; 3434 int8_t txpow1, txpow2; 3435 int i; 3436 3437 run_read(sc, RT5592_DEBUG_INDEX, &tmp); 3438 freqs = (tmp & RT5592_SEL_XTAL) ? 3439 rt5592_freqs_40mhz : rt5592_freqs_20mhz; 3440 3441 /* find the settings for this channel (we know it exists) */ 3442 for (i = 0; rt2860_rf2850[i].chan != chan; i++, freqs++); 3443 3444 /* use Tx power values from EEPROM */ 3445 txpow1 = sc->txpow1[i]; 3446 txpow2 = sc->txpow2[i]; 3447 3448 run_read(sc, RT3070_LDO_CFG0, &tmp); 3449 tmp &= ~0x1c000000; 3450 if (chan > 14) 3451 tmp |= 0x14000000; 3452 run_write(sc, RT3070_LDO_CFG0, tmp); 3453 3454 /* N setting. */ 3455 run_rt3070_rf_write(sc, 8, freqs->n & 0xff); 3456 run_rt3070_rf_read(sc, 9, &rf); 3457 rf &= ~(1 << 4); 3458 rf |= ((freqs->n & 0x0100) >> 8) << 4; 3459 run_rt3070_rf_write(sc, 9, rf); 3460 3461 /* K setting. */ 3462 run_rt3070_rf_read(sc, 9, &rf); 3463 rf &= ~0x0f; 3464 rf |= (freqs->k & 0x0f); 3465 run_rt3070_rf_write(sc, 9, rf); 3466 3467 /* Mode setting. */ 3468 run_rt3070_rf_read(sc, 11, &rf); 3469 rf &= ~0x0c; 3470 rf |= ((freqs->m - 0x8) & 0x3) << 2; 3471 run_rt3070_rf_write(sc, 11, rf); 3472 run_rt3070_rf_read(sc, 9, &rf); 3473 rf &= ~(1 << 7); 3474 rf |= (((freqs->m - 0x8) & 0x4) >> 2) << 7; 3475 run_rt3070_rf_write(sc, 9, rf); 3476 3477 /* R setting. */ 3478 run_rt3070_rf_read(sc, 11, &rf); 3479 rf &= ~0x03; 3480 rf |= (freqs->r - 0x1); 3481 run_rt3070_rf_write(sc, 11, rf); 3482 3483 if (chan <= 14) { 3484 /* Initialize RF registers for 2GHZ. */ 3485 for (i = 0; i < nitems(rt5592_2ghz_def_rf); i++) { 3486 run_rt3070_rf_write(sc, rt5592_2ghz_def_rf[i].reg, 3487 rt5592_2ghz_def_rf[i].val); 3488 } 3489 3490 rf = (chan <= 10) ? 0x07 : 0x06; 3491 run_rt3070_rf_write(sc, 23, rf); 3492 run_rt3070_rf_write(sc, 59, rf); 3493 3494 run_rt3070_rf_write(sc, 55, 0x43); 3495 3496 /* 3497 * RF R49/R50 Tx power ALC code. 3498 * G-band bit<7:6>=1:0, bit<5:0> range from 0x0 ~ 0x27. 3499 */ 3500 reg = 2; 3501 txpow_bound = 0x27; 3502 } else { 3503 /* Initialize RF registers for 5GHZ. */ 3504 for (i = 0; i < nitems(rt5592_5ghz_def_rf); i++) { 3505 run_rt3070_rf_write(sc, rt5592_5ghz_def_rf[i].reg, 3506 rt5592_5ghz_def_rf[i].val); 3507 } 3508 for (i = 0; i < nitems(rt5592_chan_5ghz); i++) { 3509 if (chan >= rt5592_chan_5ghz[i].firstchan && 3510 chan <= rt5592_chan_5ghz[i].lastchan) { 3511 run_rt3070_rf_write(sc, rt5592_chan_5ghz[i].reg, 3512 rt5592_chan_5ghz[i].val); 3513 } 3514 } 3515 3516 /* 3517 * RF R49/R50 Tx power ALC code. 3518 * A-band bit<7:6>=1:1, bit<5:0> range from 0x0 ~ 0x2b. 3519 */ 3520 reg = 3; 3521 txpow_bound = 0x2b; 3522 } 3523 3524 /* RF R49 ch0 Tx power ALC code. */ 3525 run_rt3070_rf_read(sc, 49, &rf); 3526 rf &= ~0xc0; 3527 rf |= (reg << 6); 3528 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 3529 if ((rf & 0x3f) > txpow_bound) 3530 rf = (rf & ~0x3f) | txpow_bound; 3531 run_rt3070_rf_write(sc, 49, rf); 3532 3533 /* RF R50 ch1 Tx power ALC code. */ 3534 run_rt3070_rf_read(sc, 50, &rf); 3535 rf &= ~(1 << 7 | 1 << 6); 3536 rf |= (reg << 6); 3537 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 3538 if ((rf & 0x3f) > txpow_bound) 3539 rf = (rf & ~0x3f) | txpow_bound; 3540 run_rt3070_rf_write(sc, 50, rf); 3541 3542 /* Enable RF_BLOCK, PLL_PD, RX0_PD, and TX0_PD. */ 3543 run_rt3070_rf_read(sc, 1, &rf); 3544 rf |= (RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD); 3545 if (sc->ntxchains > 1) 3546 rf |= RT3070_TX1_PD; 3547 if (sc->nrxchains > 1) 3548 rf |= RT3070_RX1_PD; 3549 run_rt3070_rf_write(sc, 1, rf); 3550 3551 run_rt3070_rf_write(sc, 6, 0xe4); 3552 3553 run_rt3070_rf_write(sc, 30, 0x10); 3554 run_rt3070_rf_write(sc, 31, 0x80); 3555 run_rt3070_rf_write(sc, 32, 0x80); 3556 3557 run_adjust_freq_offset(sc); 3558 3559 /* Enable VCO calibration. */ 3560 run_rt3070_rf_read(sc, 3, &rf); 3561 rf |= RT3593_VCOCAL; 3562 run_rt3070_rf_write(sc, 3, rf); 3563 } 3564 3565 void 3566 run_set_agc(struct run_softc *sc, uint8_t agc) 3567 { 3568 uint8_t bbp; 3569 3570 if (sc->mac_ver == 0x3572) { 3571 run_bbp_read(sc, 27, &bbp); 3572 bbp &= ~(0x3 << 5); 3573 run_bbp_write(sc, 27, bbp | 0 << 5); /* select Rx0 */ 3574 run_bbp_write(sc, 66, agc); 3575 run_bbp_write(sc, 27, bbp | 1 << 5); /* select Rx1 */ 3576 run_bbp_write(sc, 66, agc); 3577 } else 3578 run_bbp_write(sc, 66, agc); 3579 } 3580 3581 void 3582 run_set_rx_antenna(struct run_softc *sc, int aux) 3583 { 3584 uint32_t tmp; 3585 uint8_t bbp152; 3586 3587 if (aux) { 3588 if (sc->rf_rev == RT5390_RF_5370) { 3589 run_bbp_read(sc, 152, &bbp152); 3590 run_bbp_write(sc, 152, bbp152 & ~0x80); 3591 } else { 3592 run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, 0); 3593 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3594 run_write(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08); 3595 } 3596 } else { 3597 if (sc->rf_rev == RT5390_RF_5370) { 3598 run_bbp_read(sc, 152, &bbp152); 3599 run_bbp_write(sc, 152, bbp152 | 0x80); 3600 } else { 3601 run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL, 1); 3602 run_read(sc, RT2860_GPIO_CTRL, &tmp); 3603 run_write(sc, RT2860_GPIO_CTRL, tmp & ~0x0808); 3604 } 3605 } 3606 } 3607 3608 int 3609 run_set_chan(struct run_softc *sc, struct ieee80211_channel *c) 3610 { 3611 struct ieee80211com *ic = &sc->sc_ic; 3612 u_int chan, group; 3613 3614 chan = ieee80211_chan2ieee(ic, c); 3615 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 3616 return EINVAL; 3617 3618 if (sc->mac_ver == 0x5592) 3619 run_rt5592_set_chan(sc, chan); 3620 else if (sc->mac_ver >= 0x5390) 3621 run_rt5390_set_chan(sc, chan); 3622 else if (sc->mac_ver == 0x3593) 3623 run_rt3593_set_chan(sc, chan); 3624 else if (sc->mac_ver == 0x3572) 3625 run_rt3572_set_chan(sc, chan); 3626 else if (sc->mac_ver >= 0x3070) 3627 run_rt3070_set_chan(sc, chan); 3628 else 3629 run_rt2870_set_chan(sc, chan); 3630 3631 /* determine channel group */ 3632 if (chan <= 14) 3633 group = 0; 3634 else if (chan <= 64) 3635 group = 1; 3636 else if (chan <= 128) 3637 group = 2; 3638 else 3639 group = 3; 3640 3641 /* XXX necessary only when group has changed! */ 3642 run_select_chan_group(sc, group); 3643 3644 DELAY(1000); 3645 3646 /* Perform IQ calibration. */ 3647 if (sc->mac_ver >= 0x5392) 3648 run_iq_calib(sc, chan); 3649 3650 return 0; 3651 } 3652 3653 void 3654 run_enable_tsf_sync(struct run_softc *sc) 3655 { 3656 struct ieee80211com *ic = &sc->sc_ic; 3657 uint32_t tmp; 3658 3659 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 3660 tmp &= ~0x1fffff; 3661 tmp |= ic->ic_bss->ni_intval * 16; 3662 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 3663 /* local TSF is always updated with remote TSF on beacon reception */ 3664 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 3665 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 3666 } 3667 3668 void 3669 run_enable_mrr(struct run_softc *sc) 3670 { 3671 #define CCK(mcs) (mcs) 3672 #define OFDM(mcs) (1 << 3 | (mcs)) 3673 run_write(sc, RT2860_LG_FBK_CFG0, 3674 OFDM(6) << 28 | /* 54->48 */ 3675 OFDM(5) << 24 | /* 48->36 */ 3676 OFDM(4) << 20 | /* 36->24 */ 3677 OFDM(3) << 16 | /* 24->18 */ 3678 OFDM(2) << 12 | /* 18->12 */ 3679 OFDM(1) << 8 | /* 12-> 9 */ 3680 OFDM(0) << 4 | /* 9-> 6 */ 3681 OFDM(0)); /* 6-> 6 */ 3682 3683 run_write(sc, RT2860_LG_FBK_CFG1, 3684 CCK(2) << 12 | /* 11->5.5 */ 3685 CCK(1) << 8 | /* 5.5-> 2 */ 3686 CCK(0) << 4 | /* 2-> 1 */ 3687 CCK(0)); /* 1-> 1 */ 3688 #undef OFDM 3689 #undef CCK 3690 } 3691 3692 void 3693 run_set_txpreamble(struct run_softc *sc) 3694 { 3695 uint32_t tmp; 3696 3697 run_read(sc, RT2860_AUTO_RSP_CFG, &tmp); 3698 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 3699 tmp |= RT2860_CCK_SHORT_EN; 3700 else 3701 tmp &= ~RT2860_CCK_SHORT_EN; 3702 run_write(sc, RT2860_AUTO_RSP_CFG, tmp); 3703 } 3704 3705 void 3706 run_set_basicrates(struct run_softc *sc) 3707 { 3708 struct ieee80211com *ic = &sc->sc_ic; 3709 3710 /* set basic rates mask */ 3711 if (ic->ic_curmode == IEEE80211_MODE_11B) 3712 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x003); 3713 else if (ic->ic_curmode == IEEE80211_MODE_11A) 3714 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x150); 3715 else /* 11g */ 3716 run_write(sc, RT2860_LEGACY_BASIC_RATE, 0x15f); 3717 } 3718 3719 void 3720 run_set_leds(struct run_softc *sc, uint16_t which) 3721 { 3722 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 3723 which | (sc->leds & 0x7f)); 3724 } 3725 3726 void 3727 run_set_bssid(struct run_softc *sc, const uint8_t *bssid) 3728 { 3729 run_write(sc, RT2860_MAC_BSSID_DW0, 3730 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3731 run_write(sc, RT2860_MAC_BSSID_DW1, 3732 bssid[4] | bssid[5] << 8); 3733 } 3734 3735 void 3736 run_set_macaddr(struct run_softc *sc, const uint8_t *addr) 3737 { 3738 run_write(sc, RT2860_MAC_ADDR_DW0, 3739 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3740 run_write(sc, RT2860_MAC_ADDR_DW1, 3741 addr[4] | addr[5] << 8 | 0xff << 16); 3742 } 3743 3744 void 3745 run_updateslot(struct ieee80211com *ic) 3746 { 3747 /* do it in a process context */ 3748 run_do_async(ic->ic_softc, run_updateslot_cb, NULL, 0); 3749 } 3750 3751 /* ARGSUSED */ 3752 void 3753 run_updateslot_cb(struct run_softc *sc, void *arg) 3754 { 3755 uint32_t tmp; 3756 3757 run_read(sc, RT2860_BKOFF_SLOT_CFG, &tmp); 3758 tmp &= ~0xff; 3759 tmp |= (sc->sc_ic.ic_flags & IEEE80211_F_SHSLOT) ? 3760 IEEE80211_DUR_DS_SHSLOT : IEEE80211_DUR_DS_SLOT; 3761 run_write(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3762 } 3763 3764 #if NBPFILTER > 0 3765 int8_t 3766 run_rssi2dbm(struct run_softc *sc, uint8_t rssi, uint8_t rxchain) 3767 { 3768 struct ieee80211com *ic = &sc->sc_ic; 3769 struct ieee80211_channel *c = ic->ic_ibss_chan; 3770 int delta; 3771 3772 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3773 u_int chan = ieee80211_chan2ieee(ic, c); 3774 delta = sc->rssi_5ghz[rxchain]; 3775 3776 /* determine channel group */ 3777 if (chan <= 64) 3778 delta -= sc->lna[1]; 3779 else if (chan <= 128) 3780 delta -= sc->lna[2]; 3781 else 3782 delta -= sc->lna[3]; 3783 } else 3784 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3785 3786 return -12 - delta - rssi; 3787 } 3788 #endif 3789 3790 void 3791 run_rt5390_bbp_init(struct run_softc *sc) 3792 { 3793 int i; 3794 uint8_t bbp; 3795 3796 /* Apply maximum likelihood detection for 2 stream case. */ 3797 run_bbp_read(sc, 105, &bbp); 3798 if (sc->nrxchains > 1) 3799 run_bbp_write(sc, 105, bbp | RT5390_MLD); 3800 3801 /* Avoid data lost and CRC error. */ 3802 run_bbp_read(sc, 4, &bbp); 3803 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3804 3805 if (sc->mac_ver == 0x5592) { 3806 for (i = 0; i < nitems(rt5592_def_bbp); i++) { 3807 run_bbp_write(sc, rt5592_def_bbp[i].reg, 3808 rt5592_def_bbp[i].val); 3809 } 3810 for (i = 0; i < nitems(rt5592_bbp_r196); i++) { 3811 run_bbp_write(sc, 195, i + 0x80); 3812 run_bbp_write(sc, 196, rt5592_bbp_r196[i]); 3813 } 3814 } else { 3815 for (i = 0; i < nitems(rt5390_def_bbp); i++) { 3816 run_bbp_write(sc, rt5390_def_bbp[i].reg, 3817 rt5390_def_bbp[i].val); 3818 } 3819 } 3820 if (sc->mac_ver == 0x5392) { 3821 run_bbp_write(sc, 88, 0x90); 3822 run_bbp_write(sc, 95, 0x9a); 3823 run_bbp_write(sc, 98, 0x12); 3824 run_bbp_write(sc, 106, 0x12); 3825 run_bbp_write(sc, 134, 0xd0); 3826 run_bbp_write(sc, 135, 0xf6); 3827 run_bbp_write(sc, 148, 0x84); 3828 } 3829 3830 run_bbp_read(sc, 152, &bbp); 3831 run_bbp_write(sc, 152, bbp | 0x80); 3832 3833 /* Fix BBP254 for RT5592C. */ 3834 if (sc->mac_ver == 0x5592 && sc->mac_rev >= 0x0221) { 3835 run_bbp_read(sc, 254, &bbp); 3836 run_bbp_write(sc, 254, bbp | 0x80); 3837 } 3838 3839 /* Disable hardware antenna diversity. */ 3840 if (sc->mac_ver == 0x5390) 3841 run_bbp_write(sc, 154, 0); 3842 3843 /* Initialize Rx CCK/OFDM frequency offset report. */ 3844 run_bbp_write(sc, 142, 1); 3845 run_bbp_write(sc, 143, 57); 3846 } 3847 3848 int 3849 run_bbp_init(struct run_softc *sc) 3850 { 3851 int i, error, ntries; 3852 uint8_t bbp0; 3853 3854 /* wait for BBP to wake up */ 3855 for (ntries = 0; ntries < 20; ntries++) { 3856 if ((error = run_bbp_read(sc, 0, &bbp0)) != 0) 3857 return error; 3858 if (bbp0 != 0 && bbp0 != 0xff) 3859 break; 3860 } 3861 if (ntries == 20) 3862 return ETIMEDOUT; 3863 3864 /* initialize BBP registers to default values */ 3865 if (sc->mac_ver >= 0x5390) 3866 run_rt5390_bbp_init(sc); 3867 else { 3868 for (i = 0; i < nitems(rt2860_def_bbp); i++) { 3869 run_bbp_write(sc, rt2860_def_bbp[i].reg, 3870 rt2860_def_bbp[i].val); 3871 } 3872 } 3873 3874 if (sc->mac_ver == 0x3593) { 3875 run_bbp_write(sc, 79, 0x13); 3876 run_bbp_write(sc, 80, 0x05); 3877 run_bbp_write(sc, 81, 0x33); 3878 run_bbp_write(sc, 86, 0x46); 3879 run_bbp_write(sc, 137, 0x0f); 3880 } 3881 3882 /* fix BBP84 for RT2860E */ 3883 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3884 run_bbp_write(sc, 84, 0x19); 3885 3886 if (sc->mac_ver >= 0x3070 && (sc->mac_ver != 0x3593 && 3887 sc->mac_ver != 0x5592)) { 3888 run_bbp_write(sc, 79, 0x13); 3889 run_bbp_write(sc, 80, 0x05); 3890 run_bbp_write(sc, 81, 0x33); 3891 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3892 run_bbp_write(sc, 69, 0x16); 3893 run_bbp_write(sc, 73, 0x12); 3894 } 3895 return 0; 3896 } 3897 3898 int 3899 run_rt3070_rf_init(struct run_softc *sc) 3900 { 3901 uint32_t tmp; 3902 uint8_t bbp4, mingain, rf, target; 3903 int i; 3904 3905 run_rt3070_rf_read(sc, 30, &rf); 3906 /* toggle RF R30 bit 7 */ 3907 run_rt3070_rf_write(sc, 30, rf | 0x80); 3908 DELAY(1000); 3909 run_rt3070_rf_write(sc, 30, rf & ~0x80); 3910 3911 /* initialize RF registers to default value */ 3912 if (sc->mac_ver == 0x3572) { 3913 for (i = 0; i < nitems(rt3572_def_rf); i++) { 3914 run_rt3070_rf_write(sc, rt3572_def_rf[i].reg, 3915 rt3572_def_rf[i].val); 3916 } 3917 } else { 3918 for (i = 0; i < nitems(rt3070_def_rf); i++) { 3919 run_rt3070_rf_write(sc, rt3070_def_rf[i].reg, 3920 rt3070_def_rf[i].val); 3921 } 3922 } 3923 if (sc->mac_ver == 0x3070 && sc->mac_rev < 0x0201) { 3924 /* 3925 * Change voltage from 1.2V to 1.35V for RT3070. 3926 * The DAC issue (RT3070_LDO_CFG0) has been fixed 3927 * in RT3070(F). 3928 */ 3929 run_read(sc, RT3070_LDO_CFG0, &tmp); 3930 tmp = (tmp & ~0x0f000000) | 0x0d000000; 3931 run_write(sc, RT3070_LDO_CFG0, tmp); 3932 3933 } else if (sc->mac_ver == 0x3071) { 3934 run_rt3070_rf_read(sc, 6, &rf); 3935 run_rt3070_rf_write(sc, 6, rf | 0x40); 3936 run_rt3070_rf_write(sc, 31, 0x14); 3937 3938 run_read(sc, RT3070_LDO_CFG0, &tmp); 3939 tmp &= ~0x1f000000; 3940 if (sc->mac_rev < 0x0211) 3941 tmp |= 0x0d000000; /* 1.35V */ 3942 else 3943 tmp |= 0x01000000; /* 1.2V */ 3944 run_write(sc, RT3070_LDO_CFG0, tmp); 3945 3946 /* patch LNA_PE_G1 */ 3947 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 3948 run_write(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 3949 3950 } else if (sc->mac_ver == 0x3572) { 3951 run_rt3070_rf_read(sc, 6, &rf); 3952 run_rt3070_rf_write(sc, 6, rf | 0x40); 3953 /* increase voltage from 1.2V to 1.35V */ 3954 run_read(sc, RT3070_LDO_CFG0, &tmp); 3955 tmp = (tmp & ~0x1f000000) | 0x0d000000; 3956 run_write(sc, RT3070_LDO_CFG0, tmp); 3957 3958 if (sc->mac_rev < 0x0211 || !sc->patch_dac) { 3959 DELAY(1); /* wait for 1msec */ 3960 /* decrease voltage back to 1.2V */ 3961 tmp = (tmp & ~0x1f000000) | 0x01000000; 3962 run_write(sc, RT3070_LDO_CFG0, tmp); 3963 } 3964 } 3965 3966 /* select 20MHz bandwidth */ 3967 run_rt3070_rf_read(sc, 31, &rf); 3968 run_rt3070_rf_write(sc, 31, rf & ~0x20); 3969 3970 /* calibrate filter for 20MHz bandwidth */ 3971 sc->rf24_20mhz = 0x1f; /* default value */ 3972 target = (sc->mac_ver < 0x3071) ? 0x16 : 0x13; 3973 run_rt3070_filter_calib(sc, 0x07, target, &sc->rf24_20mhz); 3974 3975 /* select 40MHz bandwidth */ 3976 run_bbp_read(sc, 4, &bbp4); 3977 run_bbp_write(sc, 4, (bbp4 & ~0x18) | 0x10); 3978 run_rt3070_rf_read(sc, 31, &rf); 3979 run_rt3070_rf_write(sc, 31, rf | 0x20); 3980 3981 /* calibrate filter for 40MHz bandwidth */ 3982 sc->rf24_40mhz = 0x2f; /* default value */ 3983 target = (sc->mac_ver < 0x3071) ? 0x19 : 0x15; 3984 run_rt3070_filter_calib(sc, 0x27, target, &sc->rf24_40mhz); 3985 3986 /* go back to 20MHz bandwidth */ 3987 run_bbp_read(sc, 4, &bbp4); 3988 run_bbp_write(sc, 4, bbp4 & ~0x18); 3989 3990 if (sc->mac_ver == 0x3572) { 3991 /* save default BBP registers 25 and 26 values */ 3992 run_bbp_read(sc, 25, &sc->bbp25); 3993 run_bbp_read(sc, 26, &sc->bbp26); 3994 3995 } else if (sc->mac_rev < 0x0201 || sc->mac_rev < 0x0211) 3996 run_rt3070_rf_write(sc, 27, 0x03); 3997 3998 run_read(sc, RT3070_OPT_14, &tmp); 3999 run_write(sc, RT3070_OPT_14, tmp | 1); 4000 4001 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 4002 run_rt3070_rf_read(sc, 17, &rf); 4003 rf &= ~RT3070_TX_LO1; 4004 if ((sc->mac_ver == 0x3070 || 4005 (sc->mac_ver == 0x3071 && sc->mac_rev >= 0x0211)) && 4006 !sc->ext_2ghz_lna) 4007 rf |= 0x20; /* fix for long range Rx issue */ 4008 mingain = (sc->mac_ver == 0x3070) ? 1 : 2; 4009 if (sc->txmixgain_2ghz >= mingain) 4010 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 4011 run_rt3070_rf_write(sc, 17, rf); 4012 } 4013 if (sc->mac_ver == 0x3071) { 4014 run_rt3070_rf_read(sc, 1, &rf); 4015 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 4016 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 4017 run_rt3070_rf_write(sc, 1, rf); 4018 4019 run_rt3070_rf_read(sc, 15, &rf); 4020 run_rt3070_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 4021 4022 run_rt3070_rf_read(sc, 20, &rf); 4023 run_rt3070_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 4024 4025 run_rt3070_rf_read(sc, 21, &rf); 4026 run_rt3070_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 4027 } 4028 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) { 4029 /* fix Tx to Rx IQ glitch by raising RF voltage */ 4030 run_rt3070_rf_read(sc, 27, &rf); 4031 rf &= ~0x77; 4032 if (sc->mac_rev < 0x0211) 4033 rf |= 0x03; 4034 run_rt3070_rf_write(sc, 27, rf); 4035 } 4036 return 0; 4037 } 4038 4039 void 4040 run_rt3593_rf_init(struct run_softc *sc) 4041 { 4042 uint32_t tmp; 4043 uint8_t rf; 4044 int i; 4045 4046 /* Disable the GPIO bits 4 and 7 for LNA PE control. */ 4047 run_read(sc, RT3070_GPIO_SWITCH, &tmp); 4048 tmp &= ~(1 << 4 | 1 << 7); 4049 run_write(sc, RT3070_GPIO_SWITCH, tmp); 4050 4051 /* Initialize RF registers to default value. */ 4052 for (i = 0; i < nitems(rt3593_def_rf); i++) { 4053 run_rt3070_rf_write(sc, rt3593_def_rf[i].reg, 4054 rt3593_def_rf[i].val); 4055 } 4056 4057 /* Toggle RF R2 to initiate calibration. */ 4058 run_rt3070_rf_write(sc, 2, RT3593_RESCAL); 4059 4060 /* Initialize RF frequency offset. */ 4061 run_adjust_freq_offset(sc); 4062 4063 run_rt3070_rf_read(sc, 18, &rf); 4064 run_rt3070_rf_write(sc, 18, rf | RT3593_AUTOTUNE_BYPASS); 4065 4066 /* 4067 * Increase voltage from 1.2V to 1.35V, wait for 1 msec to 4068 * decrease voltage back to 1.2V. 4069 */ 4070 run_read(sc, RT3070_LDO_CFG0, &tmp); 4071 tmp = (tmp & ~0x1f000000) | 0x0d000000; 4072 run_write(sc, RT3070_LDO_CFG0, tmp); 4073 DELAY(1); 4074 tmp = (tmp & ~0x1f000000) | 0x01000000; 4075 run_write(sc, RT3070_LDO_CFG0, tmp); 4076 4077 sc->rf24_20mhz = 0x1f; 4078 sc->rf24_40mhz = 0x2f; 4079 4080 /* Save default BBP registers 25 and 26 values. */ 4081 run_bbp_read(sc, 25, &sc->bbp25); 4082 run_bbp_read(sc, 26, &sc->bbp26); 4083 4084 run_read(sc, RT3070_OPT_14, &tmp); 4085 run_write(sc, RT3070_OPT_14, tmp | 1); 4086 } 4087 4088 void 4089 run_rt5390_rf_init(struct run_softc *sc) 4090 { 4091 uint32_t tmp; 4092 uint8_t rf; 4093 int i; 4094 4095 /* Toggle RF R2 to initiate calibration. */ 4096 if (sc->mac_ver == 0x5390) { 4097 run_rt3070_rf_read(sc, 2, &rf); 4098 run_rt3070_rf_write(sc, 2, rf | RT3593_RESCAL); 4099 DELAY(10); 4100 run_rt3070_rf_write(sc, 2, rf & ~RT3593_RESCAL); 4101 } else { 4102 run_rt3070_rf_write(sc, 2, RT3593_RESCAL); 4103 DELAY(10); 4104 } 4105 4106 /* Initialize RF registers to default value. */ 4107 if (sc->mac_ver == 0x5592) { 4108 for (i = 0; i < nitems(rt5592_def_rf); i++) { 4109 run_rt3070_rf_write(sc, rt5592_def_rf[i].reg, 4110 rt5592_def_rf[i].val); 4111 } 4112 /* Initialize RF frequency offset. */ 4113 run_adjust_freq_offset(sc); 4114 } else if (sc->mac_ver == 0x5392) { 4115 for (i = 0; i < nitems(rt5392_def_rf); i++) { 4116 run_rt3070_rf_write(sc, rt5392_def_rf[i].reg, 4117 rt5392_def_rf[i].val); 4118 } 4119 if (sc->mac_rev >= 0x0223) { 4120 run_rt3070_rf_write(sc, 23, 0x0f); 4121 run_rt3070_rf_write(sc, 24, 0x3e); 4122 run_rt3070_rf_write(sc, 51, 0x32); 4123 run_rt3070_rf_write(sc, 53, 0x22); 4124 run_rt3070_rf_write(sc, 56, 0xc1); 4125 run_rt3070_rf_write(sc, 59, 0x0f); 4126 } 4127 } else { 4128 for (i = 0; i < nitems(rt5390_def_rf); i++) { 4129 run_rt3070_rf_write(sc, rt5390_def_rf[i].reg, 4130 rt5390_def_rf[i].val); 4131 } 4132 if (sc->mac_rev >= 0x0502) { 4133 run_rt3070_rf_write(sc, 6, 0xe0); 4134 run_rt3070_rf_write(sc, 25, 0x80); 4135 run_rt3070_rf_write(sc, 46, 0x73); 4136 run_rt3070_rf_write(sc, 53, 0x00); 4137 run_rt3070_rf_write(sc, 56, 0x42); 4138 run_rt3070_rf_write(sc, 61, 0xd1); 4139 } 4140 } 4141 4142 sc->rf24_20mhz = 0x1f; /* default value */ 4143 sc->rf24_40mhz = (sc->mac_ver == 0x5592) ? 0 : 0x2f; 4144 4145 if (sc->mac_rev < 0x0211) 4146 run_rt3070_rf_write(sc, 27, 0x3); 4147 4148 run_read(sc, RT3070_OPT_14, &tmp); 4149 run_write(sc, RT3070_OPT_14, tmp | 1); 4150 } 4151 4152 int 4153 run_rt3070_filter_calib(struct run_softc *sc, uint8_t init, uint8_t target, 4154 uint8_t *val) 4155 { 4156 uint8_t rf22, rf24; 4157 uint8_t bbp55_pb, bbp55_sb, delta; 4158 int ntries; 4159 4160 /* program filter */ 4161 run_rt3070_rf_read(sc, 24, &rf24); 4162 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 4163 run_rt3070_rf_write(sc, 24, rf24); 4164 4165 /* enable baseband loopback mode */ 4166 run_rt3070_rf_read(sc, 22, &rf22); 4167 run_rt3070_rf_write(sc, 22, rf22 | 0x01); 4168 4169 /* set power and frequency of passband test tone */ 4170 run_bbp_write(sc, 24, 0x00); 4171 for (ntries = 0; ntries < 100; ntries++) { 4172 /* transmit test tone */ 4173 run_bbp_write(sc, 25, 0x90); 4174 DELAY(1000); 4175 /* read received power */ 4176 run_bbp_read(sc, 55, &bbp55_pb); 4177 if (bbp55_pb != 0) 4178 break; 4179 } 4180 if (ntries == 100) 4181 return ETIMEDOUT; 4182 4183 /* set power and frequency of stopband test tone */ 4184 run_bbp_write(sc, 24, 0x06); 4185 for (ntries = 0; ntries < 100; ntries++) { 4186 /* transmit test tone */ 4187 run_bbp_write(sc, 25, 0x90); 4188 DELAY(1000); 4189 /* read received power */ 4190 run_bbp_read(sc, 55, &bbp55_sb); 4191 4192 delta = bbp55_pb - bbp55_sb; 4193 if (delta > target) 4194 break; 4195 4196 /* reprogram filter */ 4197 rf24++; 4198 run_rt3070_rf_write(sc, 24, rf24); 4199 } 4200 if (ntries < 100) { 4201 if (rf24 != init) 4202 rf24--; /* backtrack */ 4203 *val = rf24; 4204 run_rt3070_rf_write(sc, 24, rf24); 4205 } 4206 4207 /* restore initial state */ 4208 run_bbp_write(sc, 24, 0x00); 4209 4210 /* disable baseband loopback mode */ 4211 run_rt3070_rf_read(sc, 22, &rf22); 4212 run_rt3070_rf_write(sc, 22, rf22 & ~0x01); 4213 4214 return 0; 4215 } 4216 4217 void 4218 run_rt3070_rf_setup(struct run_softc *sc) 4219 { 4220 uint8_t bbp, rf; 4221 int i; 4222 4223 if (sc->mac_ver == 0x3572) { 4224 /* enable DC filter */ 4225 if (sc->mac_rev >= 0x0201) 4226 run_bbp_write(sc, 103, 0xc0); 4227 4228 run_bbp_read(sc, 138, &bbp); 4229 if (sc->ntxchains == 1) 4230 bbp |= 0x20; /* turn off DAC1 */ 4231 if (sc->nrxchains == 1) 4232 bbp &= ~0x02; /* turn off ADC1 */ 4233 run_bbp_write(sc, 138, bbp); 4234 4235 if (sc->mac_rev >= 0x0211) { 4236 /* improve power consumption */ 4237 run_bbp_read(sc, 31, &bbp); 4238 run_bbp_write(sc, 31, bbp & ~0x03); 4239 } 4240 4241 run_rt3070_rf_read(sc, 16, &rf); 4242 rf = (rf & ~0x07) | sc->txmixgain_2ghz; 4243 run_rt3070_rf_write(sc, 16, rf); 4244 4245 } else if (sc->mac_ver == 0x3071) { 4246 /* enable DC filter */ 4247 if (sc->mac_rev >= 0x0211) { 4248 run_bbp_write(sc, 103, 0xc0); 4249 4250 /* improve power consumption */ 4251 run_bbp_read(sc, 31, &bbp); 4252 run_bbp_write(sc, 31, bbp & ~0x03); 4253 } 4254 4255 run_bbp_read(sc, 138, &bbp); 4256 if (sc->ntxchains == 1) 4257 bbp |= 0x20; /* turn off DAC1 */ 4258 if (sc->nrxchains == 1) 4259 bbp &= ~0x02; /* turn off ADC1 */ 4260 run_bbp_write(sc, 138, bbp); 4261 4262 run_write(sc, RT2860_TX_SW_CFG1, 0); 4263 if (sc->mac_rev < 0x0211) { 4264 run_write(sc, RT2860_TX_SW_CFG2, 4265 sc->patch_dac ? 0x2c : 0x0f); 4266 } else 4267 run_write(sc, RT2860_TX_SW_CFG2, 0); 4268 4269 } else if (sc->mac_ver == 0x3070) { 4270 if (sc->mac_rev >= 0x0201) { 4271 /* enable DC filter */ 4272 run_bbp_write(sc, 103, 0xc0); 4273 4274 /* improve power consumption */ 4275 run_bbp_read(sc, 31, &bbp); 4276 run_bbp_write(sc, 31, bbp & ~0x03); 4277 } 4278 4279 if (sc->mac_rev < 0x0201) { 4280 run_write(sc, RT2860_TX_SW_CFG1, 0); 4281 run_write(sc, RT2860_TX_SW_CFG2, 0x2c); 4282 } else 4283 run_write(sc, RT2860_TX_SW_CFG2, 0); 4284 } 4285 4286 /* initialize RF registers from ROM for >=RT3071*/ 4287 if (sc->mac_ver >= 0x3071) { 4288 for (i = 0; i < 10; i++) { 4289 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 4290 continue; 4291 run_rt3070_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 4292 } 4293 } 4294 } 4295 4296 void 4297 run_rt3593_rf_setup(struct run_softc *sc) 4298 { 4299 uint8_t bbp, rf; 4300 4301 if (sc->mac_rev >= 0x0211) { 4302 /* Enable DC filter. */ 4303 run_bbp_write(sc, 103, 0xc0); 4304 } 4305 run_write(sc, RT2860_TX_SW_CFG1, 0); 4306 if (sc->mac_rev < 0x0211) { 4307 run_write(sc, RT2860_TX_SW_CFG2, 4308 sc->patch_dac ? 0x2c : 0x0f); 4309 } else 4310 run_write(sc, RT2860_TX_SW_CFG2, 0); 4311 4312 run_rt3070_rf_read(sc, 50, &rf); 4313 run_rt3070_rf_write(sc, 50, rf & ~RT3593_TX_LO2); 4314 4315 run_rt3070_rf_read(sc, 51, &rf); 4316 rf = (rf & ~(RT3593_TX_LO1 | 0x0c)) | 4317 ((sc->txmixgain_2ghz & 0x07) << 2); 4318 run_rt3070_rf_write(sc, 51, rf); 4319 4320 run_rt3070_rf_read(sc, 38, &rf); 4321 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4322 4323 run_rt3070_rf_read(sc, 39, &rf); 4324 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4325 4326 run_rt3070_rf_read(sc, 1, &rf); 4327 run_rt3070_rf_write(sc, 1, rf & ~(RT3070_RF_BLOCK | RT3070_PLL_PD)); 4328 4329 run_rt3070_rf_read(sc, 30, &rf); 4330 rf = (rf & ~0x18) | 0x10; 4331 run_rt3070_rf_write(sc, 30, rf); 4332 4333 /* Apply maximum likelihood detection for 2 stream case. */ 4334 run_bbp_read(sc, 105, &bbp); 4335 if (sc->nrxchains > 1) 4336 run_bbp_write(sc, 105, bbp | RT5390_MLD); 4337 4338 /* Avoid data lost and CRC error. */ 4339 run_bbp_read(sc, 4, &bbp); 4340 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4341 4342 run_bbp_write(sc, 92, 0x02); 4343 run_bbp_write(sc, 82, 0x82); 4344 run_bbp_write(sc, 106, 0x05); 4345 run_bbp_write(sc, 104, 0x92); 4346 run_bbp_write(sc, 88, 0x90); 4347 run_bbp_write(sc, 148, 0xc8); 4348 run_bbp_write(sc, 47, 0x48); 4349 run_bbp_write(sc, 120, 0x50); 4350 4351 run_bbp_write(sc, 163, 0x9d); 4352 4353 /* SNR mapping. */ 4354 run_bbp_write(sc, 142, 0x06); 4355 run_bbp_write(sc, 143, 0xa0); 4356 run_bbp_write(sc, 142, 0x07); 4357 run_bbp_write(sc, 143, 0xa1); 4358 run_bbp_write(sc, 142, 0x08); 4359 run_bbp_write(sc, 143, 0xa2); 4360 4361 run_bbp_write(sc, 31, 0x08); 4362 run_bbp_write(sc, 68, 0x0b); 4363 run_bbp_write(sc, 105, 0x04); 4364 } 4365 4366 void 4367 run_rt5390_rf_setup(struct run_softc *sc) 4368 { 4369 uint8_t bbp, rf; 4370 4371 if (sc->mac_rev >= 0x0211) { 4372 /* Enable DC filter. */ 4373 run_bbp_write(sc, 103, 0xc0); 4374 4375 if (sc->mac_ver != 0x5592) { 4376 /* Improve power consumption. */ 4377 run_bbp_read(sc, 31, &bbp); 4378 run_bbp_write(sc, 31, bbp & ~0x03); 4379 } 4380 } 4381 4382 run_bbp_read(sc, 138, &bbp); 4383 if (sc->ntxchains == 1) 4384 bbp |= 0x20; /* turn off DAC1 */ 4385 if (sc->nrxchains == 1) 4386 bbp &= ~0x02; /* turn off ADC1 */ 4387 run_bbp_write(sc, 138, bbp); 4388 4389 run_rt3070_rf_read(sc, 38, &rf); 4390 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1); 4391 4392 run_rt3070_rf_read(sc, 39, &rf); 4393 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2); 4394 4395 /* Avoid data lost and CRC error. */ 4396 run_bbp_read(sc, 4, &bbp); 4397 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 4398 4399 run_rt3070_rf_read(sc, 30, &rf); 4400 rf = (rf & ~0x18) | 0x10; 4401 run_rt3070_rf_write(sc, 30, rf); 4402 4403 if (sc->mac_ver != 0x5592) { 4404 run_write(sc, RT2860_TX_SW_CFG1, 0); 4405 if (sc->mac_rev < 0x0211) { 4406 run_write(sc, RT2860_TX_SW_CFG2, 4407 sc->patch_dac ? 0x2c : 0x0f); 4408 } else 4409 run_write(sc, RT2860_TX_SW_CFG2, 0); 4410 } 4411 } 4412 4413 int 4414 run_txrx_enable(struct run_softc *sc) 4415 { 4416 uint32_t tmp; 4417 int error, ntries; 4418 4419 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 4420 for (ntries = 0; ntries < 200; ntries++) { 4421 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4422 return error; 4423 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4424 break; 4425 DELAY(1000); 4426 } 4427 if (ntries == 200) 4428 return ETIMEDOUT; 4429 4430 DELAY(50); 4431 4432 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | RT2860_TX_WB_DDONE; 4433 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4434 4435 /* enable Rx bulk aggregation (set timeout and limit) */ 4436 tmp = RT2860_USB_TX_EN | RT2860_USB_RX_EN | RT2860_USB_RX_AGG_EN | 4437 RT2860_USB_RX_AGG_TO(128) | RT2860_USB_RX_AGG_LMT(2); 4438 run_write(sc, RT2860_USB_DMA_CFG, tmp); 4439 4440 /* set Rx filter */ 4441 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 4442 if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) { 4443 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 4444 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 4445 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 4446 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 4447 if (sc->sc_ic.ic_opmode == IEEE80211_M_STA) 4448 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 4449 } 4450 run_write(sc, RT2860_RX_FILTR_CFG, tmp); 4451 4452 run_write(sc, RT2860_MAC_SYS_CTRL, 4453 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4454 4455 return 0; 4456 } 4457 4458 void 4459 run_adjust_freq_offset(struct run_softc *sc) 4460 { 4461 uint8_t rf, tmp; 4462 4463 run_rt3070_rf_read(sc, 17, &rf); 4464 tmp = rf; 4465 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 4466 rf = MIN(rf, 0x5f); 4467 4468 if (tmp != rf) 4469 run_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf); 4470 } 4471 4472 int 4473 run_init(struct ifnet *ifp) 4474 { 4475 struct run_softc *sc = ifp->if_softc; 4476 struct ieee80211com *ic = &sc->sc_ic; 4477 uint32_t tmp; 4478 uint8_t bbp1, bbp3; 4479 int i, error, qid, ridx, ntries; 4480 4481 if (usbd_is_dying(sc->sc_udev)) 4482 return ENXIO; 4483 4484 for (ntries = 0; ntries < 100; ntries++) { 4485 if ((error = run_read(sc, RT2860_ASIC_VER_ID, &tmp)) != 0) 4486 goto fail; 4487 if (tmp != 0 && tmp != 0xffffffff) 4488 break; 4489 DELAY(10); 4490 } 4491 if (ntries == 100) { 4492 error = ETIMEDOUT; 4493 goto fail; 4494 } 4495 4496 if ((error = run_load_microcode(sc)) != 0) { 4497 printf("%s: could not load 8051 microcode\n", 4498 sc->sc_dev.dv_xname); 4499 goto fail; 4500 } 4501 4502 /* init host command ring */ 4503 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0; 4504 4505 /* init Tx rings (4 EDCAs) */ 4506 for (qid = 0; qid < 4; qid++) { 4507 if ((error = run_alloc_tx_ring(sc, qid)) != 0) 4508 goto fail; 4509 } 4510 /* init Rx ring */ 4511 if ((error = run_alloc_rx_ring(sc)) != 0) 4512 goto fail; 4513 4514 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 4515 run_set_macaddr(sc, ic->ic_myaddr); 4516 4517 for (ntries = 0; ntries < 100; ntries++) { 4518 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp)) != 0) 4519 goto fail; 4520 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4521 break; 4522 DELAY(1000); 4523 } 4524 if (ntries == 100) { 4525 printf("%s: timeout waiting for DMA engine\n", 4526 sc->sc_dev.dv_xname); 4527 error = ETIMEDOUT; 4528 goto fail; 4529 } 4530 tmp &= 0xff0; 4531 tmp |= RT2860_TX_WB_DDONE; 4532 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4533 4534 /* turn off PME_OEN to solve high-current issue */ 4535 run_read(sc, RT2860_SYS_CTRL, &tmp); 4536 run_write(sc, RT2860_SYS_CTRL, tmp & ~RT2860_PME_OEN); 4537 4538 run_write(sc, RT2860_MAC_SYS_CTRL, 4539 RT2860_BBP_HRST | RT2860_MAC_SRST); 4540 run_write(sc, RT2860_USB_DMA_CFG, 0); 4541 4542 if ((error = run_reset(sc)) != 0) { 4543 printf("%s: could not reset chipset\n", sc->sc_dev.dv_xname); 4544 goto fail; 4545 } 4546 4547 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 4548 4549 /* init Tx power for all Tx rates (from EEPROM) */ 4550 for (ridx = 0; ridx < 5; ridx++) { 4551 if (sc->txpow20mhz[ridx] == 0xffffffff) 4552 continue; 4553 run_write(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 4554 } 4555 4556 for (i = 0; i < nitems(rt2870_def_mac); i++) 4557 run_write(sc, rt2870_def_mac[i].reg, rt2870_def_mac[i].val); 4558 run_write(sc, RT2860_WMM_AIFSN_CFG, 0x00002273); 4559 run_write(sc, RT2860_WMM_CWMIN_CFG, 0x00002344); 4560 run_write(sc, RT2860_WMM_CWMAX_CFG, 0x000034aa); 4561 4562 if (sc->mac_ver >= 0x5390) { 4563 run_write(sc, RT2860_TX_SW_CFG0, 4564 4 << RT2860_DLY_PAPE_EN_SHIFT | 4); 4565 if (sc->mac_ver >= 0x5392) { 4566 run_write(sc, RT2860_MAX_LEN_CFG, 0x00002fff); 4567 if (sc->mac_ver == 0x5592) { 4568 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcba980); 4569 run_write(sc, RT2860_TXOP_HLDR_ET, 0x00000082); 4570 } else { 4571 run_write(sc, RT2860_HT_FBK_CFG1, 0xedcb4980); 4572 run_write(sc, RT2860_LG_FBK_CFG0, 0xedcba322); 4573 } 4574 } 4575 } else if (sc->mac_ver == 0x3593) { 4576 run_write(sc, RT2860_TX_SW_CFG0, 4577 4 << RT2860_DLY_PAPE_EN_SHIFT | 2); 4578 } else if (sc->mac_ver >= 0x3070) { 4579 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 4580 run_write(sc, RT2860_TX_SW_CFG0, 4581 4 << RT2860_DLY_PAPE_EN_SHIFT); 4582 } 4583 4584 /* wait while MAC is busy */ 4585 for (ntries = 0; ntries < 100; ntries++) { 4586 if ((error = run_read(sc, RT2860_MAC_STATUS_REG, &tmp)) != 0) 4587 goto fail; 4588 if (!(tmp & (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 4589 break; 4590 DELAY(1000); 4591 } 4592 if (ntries == 100) { 4593 error = ETIMEDOUT; 4594 goto fail; 4595 } 4596 4597 /* clear Host to MCU mailbox */ 4598 run_write(sc, RT2860_H2M_BBPAGENT, 0); 4599 run_write(sc, RT2860_H2M_MAILBOX, 0); 4600 DELAY(1000); 4601 4602 if ((error = run_bbp_init(sc)) != 0) { 4603 printf("%s: could not initialize BBP\n", sc->sc_dev.dv_xname); 4604 goto fail; 4605 } 4606 4607 /* abort TSF synchronization */ 4608 run_read(sc, RT2860_BCN_TIME_CFG, &tmp); 4609 tmp &= ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 4610 RT2860_TBTT_TIMER_EN); 4611 run_write(sc, RT2860_BCN_TIME_CFG, tmp); 4612 4613 /* clear RX WCID search table */ 4614 run_set_region_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 4615 /* clear WCID attribute table */ 4616 run_set_region_4(sc, RT2860_WCID_ATTR(0), 0, 8 * 32); 4617 /* clear shared key table */ 4618 run_set_region_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 4619 /* clear shared key mode */ 4620 run_set_region_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 4621 4622 run_read(sc, RT2860_US_CYC_CNT, &tmp); 4623 tmp = (tmp & ~0xff) | 0x1e; 4624 run_write(sc, RT2860_US_CYC_CNT, tmp); 4625 4626 if (sc->mac_rev != 0x0101) 4627 run_write(sc, RT2860_TXOP_CTRL_CFG, 0x0000583f); 4628 4629 run_write(sc, RT2860_WMM_TXOP0_CFG, 0); 4630 run_write(sc, RT2860_WMM_TXOP1_CFG, 48 << 16 | 96); 4631 4632 /* write vendor-specific BBP values (from EEPROM) */ 4633 if (sc->mac_ver < 0x3593) { 4634 for (i = 0; i < 8; i++) { 4635 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 4636 continue; 4637 run_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 4638 } 4639 } 4640 4641 /* select Main antenna for 1T1R devices */ 4642 if (sc->rf_rev == RT3070_RF_3020 || sc->rf_rev == RT5390_RF_5370) 4643 run_set_rx_antenna(sc, 0); 4644 4645 /* send LEDs operating mode to microcontroller */ 4646 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0]); 4647 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1]); 4648 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2]); 4649 4650 if (sc->mac_ver >= 0x5390) 4651 run_rt5390_rf_init(sc); 4652 else if (sc->mac_ver == 0x3593) 4653 run_rt3593_rf_init(sc); 4654 else if (sc->mac_ver >= 0x3070) 4655 run_rt3070_rf_init(sc); 4656 4657 /* disable non-existing Rx chains */ 4658 run_bbp_read(sc, 3, &bbp3); 4659 bbp3 &= ~(1 << 3 | 1 << 4); 4660 if (sc->nrxchains == 2) 4661 bbp3 |= 1 << 3; 4662 else if (sc->nrxchains == 3) 4663 bbp3 |= 1 << 4; 4664 run_bbp_write(sc, 3, bbp3); 4665 4666 /* disable non-existing Tx chains */ 4667 run_bbp_read(sc, 1, &bbp1); 4668 if (sc->ntxchains == 1) 4669 bbp1 &= ~(1 << 3 | 1 << 4); 4670 run_bbp_write(sc, 1, bbp1); 4671 4672 if (sc->mac_ver >= 0x5390) 4673 run_rt5390_rf_setup(sc); 4674 else if (sc->mac_ver == 0x3593) 4675 run_rt3593_rf_setup(sc); 4676 else if (sc->mac_ver >= 0x3070) 4677 run_rt3070_rf_setup(sc); 4678 4679 /* select default channel */ 4680 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 4681 run_set_chan(sc, ic->ic_ibss_chan); 4682 4683 /* turn radio LED on */ 4684 run_set_leds(sc, RT2860_LED_RADIO); 4685 4686 for (i = 0; i < RUN_RX_RING_COUNT; i++) { 4687 struct run_rx_data *data = &sc->rxq.data[i]; 4688 4689 usbd_setup_xfer(data->xfer, sc->rxq.pipeh, data, data->buf, 4690 RUN_MAX_RXSZ, USBD_SHORT_XFER_OK | USBD_NO_COPY, 4691 USBD_NO_TIMEOUT, run_rxeof); 4692 error = usbd_transfer(data->xfer); 4693 if (error != 0 && error != USBD_IN_PROGRESS) 4694 goto fail; 4695 } 4696 4697 if ((error = run_txrx_enable(sc)) != 0) 4698 goto fail; 4699 4700 ifp->if_flags |= IFF_RUNNING; 4701 ifq_clr_oactive(&ifp->if_snd); 4702 4703 if (ic->ic_flags & IEEE80211_F_WEPON) { 4704 /* install WEP keys */ 4705 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4706 (void)run_set_key(ic, NULL, &ic->ic_nw_keys[i]); 4707 } 4708 4709 if (ic->ic_opmode == IEEE80211_M_MONITOR) 4710 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 4711 else 4712 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 4713 4714 if (error != 0) 4715 fail: run_stop(ifp, 1); 4716 return error; 4717 } 4718 4719 void 4720 run_stop(struct ifnet *ifp, int disable) 4721 { 4722 struct run_softc *sc = ifp->if_softc; 4723 struct ieee80211com *ic = &sc->sc_ic; 4724 uint32_t tmp; 4725 int s, ntries, qid; 4726 4727 if (ifp->if_flags & IFF_RUNNING) 4728 run_set_leds(sc, 0); /* turn all LEDs off */ 4729 4730 sc->sc_tx_timer = 0; 4731 ifp->if_timer = 0; 4732 ifp->if_flags &= ~IFF_RUNNING; 4733 ifq_clr_oactive(&ifp->if_snd); 4734 4735 timeout_del(&sc->scan_to); 4736 timeout_del(&sc->calib_to); 4737 4738 s = splusb(); 4739 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 4740 /* wait for all queued asynchronous commands to complete */ 4741 usb_wait_task(sc->sc_udev, &sc->sc_task); 4742 splx(s); 4743 4744 /* Disable Tx/Rx DMA. */ 4745 run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp); 4746 tmp &= ~(RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 4747 run_write(sc, RT2860_WPDMA_GLO_CFG, tmp); 4748 4749 for (ntries = 0; ntries < 100; ntries++) { 4750 if (run_read(sc, RT2860_WPDMA_GLO_CFG, &tmp) != 0) 4751 break; 4752 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4753 break; 4754 DELAY(10); 4755 } 4756 if (ntries == 100) { 4757 printf("%s: timeout waiting for DMA engine\n", 4758 sc->sc_dev.dv_xname); 4759 } 4760 4761 /* disable Tx/Rx */ 4762 run_read(sc, RT2860_MAC_SYS_CTRL, &tmp); 4763 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4764 run_write(sc, RT2860_MAC_SYS_CTRL, tmp); 4765 4766 /* wait for pending Tx to complete */ 4767 for (ntries = 0; ntries < 100; ntries++) { 4768 if (run_read(sc, RT2860_TXRXQ_PCNT, &tmp) != 0) 4769 break; 4770 if ((tmp & RT2860_TX2Q_PCNT_MASK) == 0) 4771 break; 4772 } 4773 DELAY(1000); 4774 run_write(sc, RT2860_USB_DMA_CFG, 0); 4775 4776 /* reset adapter */ 4777 run_write(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4778 run_write(sc, RT2860_MAC_SYS_CTRL, 0); 4779 4780 /* reset Tx and Rx rings */ 4781 sc->qfullmsk = 0; 4782 for (qid = 0; qid < 4; qid++) 4783 run_free_tx_ring(sc, qid); 4784 run_free_rx_ring(sc); 4785 } 4786